From f3d096b0a87770fc3efe647f3b6de136479206ab Mon Sep 17 00:00:00 2001 From: "Naveen H.S" Date: Wed, 17 Apr 2013 05:37:10 +0000 Subject: [PATCH] aarch64.md (*adds__multp2): New pattern. gcc/ 2013-04-16 Naveen H.S * config/aarch64/aarch64.md (*adds__multp2): New pattern. (*subs__multp2): New pattern. (*adds__): New pattern. (*subs__): New pattern. gcc/testsuite/ 2013-04-16 Naveen H.S * gcc.target/aarch64/adds3.c: New. * gcc.target/aarch64/subs3.c: New. From-SVN: r198020 --- gcc/ChangeLog | 8 +++ gcc/config/aarch64/aarch64.md | 72 ++++++++++++++++++++++++ gcc/testsuite/ChangeLog | 5 ++ gcc/testsuite/gcc.target/aarch64/adds3.c | 61 ++++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/subs3.c | 61 ++++++++++++++++++++ 5 files changed, 207 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/adds3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/subs3.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2a9d001e255..3ccbb0c1ea2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2013-04-16 Naveen H.S + + * config/aarch64/aarch64.md (*adds__multp2): + New pattern. + (*subs__multp2): New pattern. + (*adds__): New pattern. + (*subs__): New pattern. + 2013-04-16 Naveen H.S * config/aarch64/aarch64.md (*adds_mul_imm_): New pattern. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 715a3727a8b..c85e685dd57 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1325,6 +1325,78 @@ (set_attr "mode" "")] ) +(define_insn "*adds__" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (plus:GPI + (ANY_EXTEND:GPI (match_operand:ALLX 1 "register_operand" "r")) + (match_operand:GPI 2 "register_operand" "r")) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=r") + (plus:GPI (ANY_EXTEND:GPI (match_dup 1)) (match_dup 2)))] + "" + "adds\\t%0, %2, %1, xt" + [(set_attr "v8type" "alus_ext") + (set_attr "mode" "")] +) + +(define_insn "*subs__" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (minus:GPI (match_operand:GPI 1 "register_operand" "r") + (ANY_EXTEND:GPI + (match_operand:ALLX 2 "register_operand" "r"))) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=r") + (minus:GPI (match_dup 1) (ANY_EXTEND:GPI (match_dup 2))))] + "" + "subs\\t%0, %1, %2, xt" + [(set_attr "v8type" "alus_ext") + (set_attr "mode" "")] +) + +(define_insn "*adds__multp2" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (plus:GPI (ANY_EXTRACT:GPI + (mult:GPI (match_operand:GPI 1 "register_operand" "r") + (match_operand 2 "aarch64_pwr_imm3" "Up3")) + (match_operand 3 "const_int_operand" "n") + (const_int 0)) + (match_operand:GPI 4 "register_operand" "r")) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=r") + (plus:GPI (ANY_EXTRACT:GPI (mult:GPI (match_dup 1) (match_dup 2)) + (match_dup 3) + (const_int 0)) + (match_dup 4)))] + "aarch64_is_extend_from_extract (mode, operands[2], operands[3])" + "adds\\t%0, %4, %1, xt%e3 %p2" + [(set_attr "v8type" "alus_ext") + (set_attr "mode" "")] +) + +(define_insn "*subs__multp2" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (minus:GPI (match_operand:GPI 4 "register_operand" "r") + (ANY_EXTRACT:GPI + (mult:GPI (match_operand:GPI 1 "register_operand" "r") + (match_operand 2 "aarch64_pwr_imm3" "Up3")) + (match_operand 3 "const_int_operand" "n") + (const_int 0))) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=r") + (minus:GPI (match_dup 4) (ANY_EXTRACT:GPI + (mult:GPI (match_dup 1) (match_dup 2)) + (match_dup 3) + (const_int 0))))] + "aarch64_is_extend_from_extract (mode, operands[2], operands[3])" + "subs\\t%0, %4, %1, xt%e3 %p2" + [(set_attr "v8type" "alus_ext") + (set_attr "mode" "")] +) + (define_insn "*add3nr_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 27eb8300865..d9a432cb2cb 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2013-04-16 Naveen H.S + + * gcc.target/aarch64/adds3.c: New. + * gcc.target/aarch64/subs3.c: New. + 2013-04-16 Naveen H.S * gcc.target/aarch64/adds1.c: New. diff --git a/gcc/testsuite/gcc.target/aarch64/adds3.c b/gcc/testsuite/gcc.target/aarch64/adds3.c new file mode 100644 index 00000000000..18efd1c2154 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/adds3.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps -fno-inline" } */ + +extern void abort (void); +typedef long long s64; + +int +adds_ext (s64 a, int b, int c) +{ + s64 d = a + b; + + if (d == 0) + return a + c; + else + return b + d + c; +} + +int +adds_shift_ext (s64 a, int b, int c) +{ + s64 d = (a + ((s64)b << 3)); + + if (d == 0) + return a + c; + else + return b + d + c; +} + +int main () +{ + int x; + s64 y; + + x = adds_ext (0x13000002ll, 41, 15); + if (x != 318767203) + abort (); + + x = adds_ext (0x50505050ll, 29, 4); + if (x != 1347440782) + abort (); + + x = adds_ext (0x12121212121ll, 2, 14); + if (x != 555819315) + abort (); + + x = adds_shift_ext (0x123456789ll, 4, 12); + if (x != 591751097) + abort (); + + x = adds_shift_ext (0x02020202ll, 9, 8); + if (x != 33686107) + abort (); + + x = adds_shift_ext (0x987987987987ll, 23, 41); + if (x != -2020050305) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, sxtw" 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/subs3.c b/gcc/testsuite/gcc.target/aarch64/subs3.c new file mode 100644 index 00000000000..90f20b84391 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/subs3.c @@ -0,0 +1,61 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps -fno-inline" } */ + +extern void abort (void); +typedef long long s64; + +int +subs_ext (s64 a, int b, int c) +{ + s64 d = a - b; + + if (d == 0) + return a + c; + else + return b + d + c; +} + +int +subs_shift_ext (s64 a, int b, int c) +{ + s64 d = (a - ((s64)b << 3)); + + if (d == 0) + return a + c; + else + return b + d + c; +} + +int main () +{ + int x; + s64 y; + + x = subs_ext (0x13000002ll, 41, 15); + if (x != 318767121) + abort (); + + x = subs_ext (0x50505050ll, 29, 4); + if (x != 1347440724) + abort (); + + x = subs_ext (0x12121212121ll, 2, 14); + if (x != 555819311) + abort (); + + x = subs_shift_ext (0x123456789ll, 4, 12); + if (x != 591751033) + abort (); + + x = subs_shift_ext (0x02020202ll, 9, 8); + if (x != 33685963) + abort (); + + x = subs_shift_ext (0x987987987987ll, 23, 41); + if (x != -2020050673) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, sxtw" 2 } } */ -- 2.30.2