From f3e1bafba499b29896db2919c8bc46e5935381b8 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Mon, 20 Jul 2020 16:05:44 +0200 Subject: [PATCH] Add simple test for DQSPattern --- gram/test/test_common.py | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/gram/test/test_common.py b/gram/test/test_common.py index 10e6159..bfc1447 100644 --- a/gram/test/test_common.py +++ b/gram/test/test_common.py @@ -1 +1,30 @@ -import unittest +from nmigen import * +from nmigen.hdl.ast import Past + +from gram.common import DQSPattern +from utils import * + +class DQSPatternTestCase(FHDLTestCase): + def test_async(self): + m = Module() + m.d.sync += Signal().eq(0) # Workaround for nMigen#417 + m.submodules.dut = dut = DQSPattern(register=False) + + def process(): + yield dut.preamble.eq(1) # Preamble=1, Postamble=0 + yield + self.assertEqual((yield dut.o), 0b00010101) + + yield dut.postamble.eq(1) # Preamble=1, Postamble=1 + yield + self.assertEqual((yield dut.o), 0b00010101) + + yield dut.preamble.eq(0) # Preamble=0, Postamble=1 + yield + self.assertEqual((yield dut.o), 0b01010100) + + yield dut.postamble.eq(0) # Preamble=1, Postamble=1 + yield + self.assertEqual((yield dut.o), 0b01010101) + + runSimulation(m, process, "test_dqspattern_async.vcd") -- 2.30.2