From f3eb8a3d6d72232d8a492da548cef57d303a87e2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 23 Dec 2021 19:47:39 +0000 Subject: [PATCH] uniquify names in dcache.py --- src/soc/experiment/dcache.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 5c9c526a..f63ed521 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -628,9 +628,9 @@ class DCachePendingHit(Elaboratable): with m.If(virt_mode): for j in range(TLB_NUM_WAYS): # tlb_num_way_t s_tag = Signal(TAG_BITS, name="s_tag%d" % j) - s_hit = Signal() - s_pte = Signal(TLB_PTE_BITS) - s_ra = Signal(REAL_ADDR_BITS) + s_hit = Signal(name="s_hit%d" % j) + s_pte = Signal(TLB_PTE_BITS, name="s_pte%d" % j) + s_ra = Signal(REAL_ADDR_BITS, name="s_ra%d" % j) # read the PTE, calc the Real Address, get tge tag comb += s_pte.eq(read_tlb_pte(j, tlb_way.pte)) comb += s_ra.eq(Cat(req_addr[0:TLB_LG_PGSZ], -- 2.30.2