From f3f84ec2f8cdc325e9ef8a41786502b00b8eefce Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 29 Jul 2022 02:26:11 +0100 Subject: [PATCH] clarify --- openpower/sv/comparison_table.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn index 6b0d39063..f3d5e7061 100644 --- a/openpower/sv/comparison_table.mdwn +++ b/openpower/sv/comparison_table.mdwn @@ -18,7 +18,7 @@ * (6): big-integer add is just `sv.adde`. For optimal performance Bigint Mul and divide first require addition of two scalar operations (in turn, naturally Vectorised by SVP64). See [[sv/biginteger/analysis]] * (7): See [[sv/svp64/appendix]] and [ARM SVE Fault-First](https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf) * (8): Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]] -* (9): Turns standard ops into a type of "cmp". See [[sv/svp64/appendix]] +* (9): Predicate-result effectively turns any standard op into a type of "cmp". See [[sv/svp64/appendix]] * (10): Any non-power-of-two Matrices up to 127 FMACs (or other FMA-style op), full triple-loop Schedule. See [[sv/remap]] * (11): DCT (Lee) and FFT Full Triple-loops supported, RADIX2-only. Normally only found in VLIW DSPs (TI MSP30, Qualcom Hexagon). See [[sv/remap]] * (12): VSX's Vector Registers are mis-named: they are 100% PackedSIMD. AVX-512 is not a Vector ISA either. See [Flynn's Taxonomy](https://en.wikipedia.org/wiki/Flynn%27s_taxonomy) -- 2.30.2