From f43d91bdbfcad92e317722acb78864b78cf7bd77 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 24 May 2020 13:01:50 +0100 Subject: [PATCH] output registers need to be Data type (consistently) --- src/soc/fu/alu/pipe_data.py | 2 +- src/soc/fu/cr/pipe_data.py | 3 ++- src/soc/fu/logical/pipe_data.py | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py index 42bea516..cdd5c97a 100644 --- a/src/soc/fu/alu/pipe_data.py +++ b/src/soc/fu/alu/pipe_data.py @@ -39,7 +39,7 @@ class ALUOutputData(IntegerData): ('XER', 'xer_so', '32')] def __init__(self, pspec): super().__init__(pspec) - self.o = Signal(64, reset_less=True, name="stage_o") + self.o = Data(64, name="stage_o") self.cr0 = Data(4, name="cr0") self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32 self.xer_ov = Data(2, name="xer_ov") # bit0: ov, bit1: ov32 diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py index 0eae72f0..4b736a0b 100644 --- a/src/soc/fu/cr/pipe_data.py +++ b/src/soc/fu/cr/pipe_data.py @@ -50,7 +50,7 @@ class CROutputData(IntegerData): ('CR', 'cr_o', '0:3')] # 4 bit range def __init__(self, pspec): super().__init__(pspec) - self.o = Signal(64, reset_less=True) # RA + self.o = Data(64, name="o") # RA self.full_cr = Data(32, name="cr_out") # CR in self.cr_o = Data(4, name="cr_o") @@ -66,6 +66,7 @@ class CROutputData(IntegerData): self.full_cr.eq(i.full_cr), self.cr_o.eq(i.cr_o)] + class CRPipeSpec(CommonPipeSpec): regspec = (CRInputData.regspec, CROutputData.regspec) opsubsetkls = CompCROpSubset diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py index 9ded5f4a..71137733 100644 --- a/src/soc/fu/logical/pipe_data.py +++ b/src/soc/fu/logical/pipe_data.py @@ -35,7 +35,7 @@ class LogicalOutputData(IntegerData): ('XER', 'xer_so', '32')] def __init__(self, pspec): super().__init__(pspec) - self.o = Signal(64, reset_less=True, name="stage_o") + self.o = Data(64, name="stage_o") # RT self.cr0 = Data(4, name="cr0") self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32 self.xer_so = Data(1, name="xer_so") -- 2.30.2