From f457ef94da5ab102818f9010407f759ca17e7cc4 Mon Sep 17 00:00:00 2001 From: Peter Bergner Date: Wed, 18 Jan 2017 20:23:35 -0600 Subject: [PATCH] re PR target/78516 (ICE in lra_assign for e500v2) PR target/78516 * config/rs6000/spe.md (mov_si_e500_subreg0): Fix constraints. Use the evmergelohi instruction. (mov_si_e500_subreg4_2_le): Likewise. (mov_sitf_e500_subreg8_2_be): Likewise. (mov_sitf_e500_subreg12_2_le): Likewise. (mov_si_e500_subreg0_2_le): Fix constraints. (mov_si_e500_subreg4_2_be): Likewise. (mov_sitf_e500_subreg8_2_le): Likewise. (mov_sitf_e500_subreg12_2_be): Likewise. From-SVN: r244609 --- gcc/ChangeLog | 13 +++++++++++++ gcc/config/rs6000/spe.md | 26 +++++++++++++------------- 2 files changed, 26 insertions(+), 13 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 69f783e523a..5d4d73463ca 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2017-01-18 Peter Bergner + + PR target/78516 + * config/rs6000/spe.md (mov_si_e500_subreg0): Fix constraints. + Use the evmergelohi instruction. + (mov_si_e500_subreg4_2_le): Likewise. + (mov_sitf_e500_subreg8_2_be): Likewise. + (mov_sitf_e500_subreg12_2_le): Likewise. + (mov_si_e500_subreg0_2_le): Fix constraints. + (mov_si_e500_subreg4_2_be): Likewise. + (mov_sitf_e500_subreg8_2_le): Likewise. + (mov_sitf_e500_subreg12_2_be): Likewise. + 2017-01-18 Bill Schmidt * config/rs6000/altivec.md (altivec_vbpermq): Change "type" diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md index 06dce2b2c71..2351152dc24 100644 --- a/gcc/config/rs6000/spe.md +++ b/gcc/config/rs6000/spe.md @@ -2559,19 +2559,19 @@ ;; ??? Could use evstwwe for memory stores in some cases, depending on ;; the offset. (define_insn "*mov_si_e500_subreg0_2_be" - [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") + [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m") (subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 0))] "WORDS_BIG_ENDIAN && ((TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode)) || (TARGET_SPE && mode != DFmode && mode != TFmode))" "@ - evmergehi %0,%0,%1 + evmergelohi %0,%1,%1 evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0" [(set_attr "length" "4,8")]) (define_insn "*mov_si_e500_subreg0_2_le" - [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") - (subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,r") 0))] + [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m") + (subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 0))] "!WORDS_BIG_ENDIAN && ((TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode)) || (TARGET_SPE && mode != DFmode && mode != TFmode))" @@ -2630,7 +2630,7 @@ [(set_attr "length" "8")]) (define_insn "*mov_si_e500_subreg4_2_be" - [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") + [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m") (subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))] "WORDS_BIG_ENDIAN && ((TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode)) @@ -2640,13 +2640,13 @@ stw%U0%X0 %1,%0") (define_insn "*mov_si_e500_subreg4_2_le" - [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") + [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m") (subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 4))] "!WORDS_BIG_ENDIAN && ((TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode)) || (TARGET_SPE && mode != DFmode && mode != TFmode))" "@ - evmergehi %0,%0,%1 + evmergelohi %0,%1,%1 evmergelohi %1,%1,%1\;stw%U0%X0 %1,%0" [(set_attr "length" "4,8")]) @@ -2668,16 +2668,16 @@ lwz%U1%X1 %L0,%1") (define_insn "*mov_sitf_e500_subreg8_2_be" - [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") + [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m") (subreg:SI (match_operand:TF 1 "register_operand" "+r,&r") 8))] "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE" "@ - evmergehi %0,%0,%L1 + evmergelohi %0,%L1,%L1 evmergelohi %L1,%L1,%L1\;stw%U0%X0 %L1,%0" [(set_attr "length" "4,8")]) (define_insn "*mov_sitf_e500_subreg8_2_le" - [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") + [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m") (subreg:SI (match_operand:TF 1 "register_operand" "r,r") 8))] "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE" "@ @@ -2702,7 +2702,7 @@ [(set_attr "length" "4,12")]) (define_insn "*mov_sitf_e500_subreg12_2_be" - [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") + [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m") (subreg:SI (match_operand:TF 1 "register_operand" "r,r") 12))] "WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE" "@ @@ -2710,11 +2710,11 @@ stw%U0%X0 %L1,%0") (define_insn "*mov_sitf_e500_subreg12_2_le" - [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m") + [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,m") (subreg:SI (match_operand:TF 1 "register_operand" "+r,&r") 12))] "!WORDS_BIG_ENDIAN && TARGET_E500_DOUBLE" "@ - evmergehi %0,%0,%L1 + evmergelohi %0,%L1,%L1 evmergelohi %L1,%L1,%L1\;stw%U0%X0 %L1,%0" [(set_attr "length" "4,8")]) -- 2.30.2