From f46efacd01c8f503b239dd16122ec6de5a684877 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 19 Jun 2019 22:24:51 -0400 Subject: [PATCH] radeonsi: flatten the switch for DPBB tunables MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Bas Nieuwenhuizen Tested-by: Dieter Nützel --- .../drivers/radeonsi/si_state_binning.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c index 6285ccc28c2..a6b1830b661 100644 --- a/src/gallium/drivers/radeonsi/si_state_binning.c +++ b/src/gallium/drivers/radeonsi/si_state_binning.c @@ -402,20 +402,10 @@ void si_emit_dpbb_state(struct si_context *sctx) unsigned persistent_states_per_bin; /* allowed range: [0, 31] */ unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */ - switch (sctx->family) { - case CHIP_VEGA10: - case CHIP_VEGA12: - case CHIP_VEGA20: - case CHIP_RAVEN: - case CHIP_RAVEN2: - /* Tuned for Raven. Vega might need different values. */ - context_states_per_bin = 5; - persistent_states_per_bin = 31; - fpovs_per_batch = 63; - break; - default: - assert(0); - } + /* Tuned for Raven. Vega might need different values. */ + context_states_per_bin = 5; + persistent_states_per_bin = 31; + fpovs_per_batch = 63; /* Emit registers. */ struct uvec2 bin_size_extend = {}; -- 2.30.2