From f48c6920b7aa777c0c569f444e3db88211835cec Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 13:12:48 -0700 Subject: [PATCH] Add read_aiger to CHANGELOG --- CHANGELOG | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG b/CHANGELOG index 36b64e111..839fefcf1 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass + - Added "read_aiger" frontend - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" -- 2.30.2