From f48d45633444da842260d61d688f839b8d05fa0b Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 25 Jun 2019 16:14:20 +0100
Subject: [PATCH] move add to its own simple example

---
 simple_v_extension/simple_add_example.mdwn | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/simple_v_extension/simple_add_example.mdwn b/simple_v_extension/simple_add_example.mdwn
index 41e737701..34f77f80d 100644
--- a/simple_v_extension/simple_add_example.mdwn
+++ b/simple_v_extension/simple_add_example.mdwn
@@ -5,7 +5,7 @@
       rs1 = int_vec[rs1].isvector ? int_vec[rs1].regidx : rs1;
       rs2 = int_vec[rs2].isvector ? int_vec[rs2].regidx : rs2;
       for (i = 0; i < VL; i++)
-        xSTATE.srcoffs = i # save context
+        STATE.srcoffs = i # save context
         if (predval & 1<<i) # predication uses intregs
            ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
            if (!int_vec[rd ].isvector) break;
@@ -14,7 +14,7 @@
         if (int_vec[rs2].isvector)  { irs2 += 1; }
         if (id == VL or irs1 == VL or irs2 == VL) {
           # end VL hardware loop
-          xSTATE.srcoffs = 0; # reset
-          xSTATE.ssvoffs = 0; # reset
+          STATE.srcoffs = 0; # reset
+          STATE.ssvoffs = 0; # reset
           return;
         }
-- 
2.30.2