From f490e2b46fc5ba0e6ed6860ddf13c2cb4467ed46 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Thu, 23 Jul 2020 14:33:08 +0200 Subject: [PATCH] Use clk pin definition from upstream nmigen-boards --- examples/ecpix5_85.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/examples/ecpix5_85.py b/examples/ecpix5_85.py index 5f9cf90..62f06ef 100644 --- a/examples/ecpix5_85.py +++ b/examples/ecpix5_85.py @@ -56,8 +56,7 @@ class _ECPIX5Platform(LatticeECP5Platform): Resource("eth_int", 0, PinsN("B13", dir="i"), Attrs(IO_TYPE="LVCMOS33")), Resource("ddr3", 0, - Subsignal("clk", Pins("H3", dir="o")), - #Subsignal("clk", DiffPairs("H3", "J3", dir="o"), Attrs(IO_TYPE="SSTL135D_I")), + Subsignal("clk", DiffPairs("H3", "J3", dir="o"), Attrs(IO_TYPE="SSTL135D_I")), Subsignal("clk_en", Pins("P1", dir="o")), Subsignal("we", PinsN("R3", dir="o")), Subsignal("ras", PinsN("T3", dir="o")), -- 2.30.2