From f494799a7f09deebacb5696fde7514e3329de246 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Fri, 13 Mar 2020 11:47:15 -0400 Subject: [PATCH] turnip: RB_CCU_CNTL fixes * Correct bypass value for a618 * Bypass value for blitter * Don't set RB_CCU_CNTL again unnecessarily in tu6_emit_binning_pass Signed-off-by: Jonathan Marek Part-of: --- src/freedreno/vulkan/tu_blit.c | 6 ++++++ src/freedreno/vulkan/tu_cmd_buffer.c | 16 +++++++--------- src/freedreno/vulkan/tu_device.c | 10 ++++------ src/freedreno/vulkan/tu_private.h | 3 ++- 4 files changed, 19 insertions(+), 16 deletions(-) diff --git a/src/freedreno/vulkan/tu_blit.c b/src/freedreno/vulkan/tu_blit.c index bdd45d0db77..116528d5a4f 100644 --- a/src/freedreno/vulkan/tu_blit.c +++ b/src/freedreno/vulkan/tu_blit.c @@ -212,6 +212,8 @@ emit_blit_step(struct tu_cmd_buffer *cmdbuf, struct tu_cs *cs, void tu_blit(struct tu_cmd_buffer *cmdbuf, struct tu_cs *cs, struct tu_blit *blt) { + struct tu_physical_device *phys_dev = cmdbuf->device->physical_device; + switch (blt->type) { case TU_BLIT_COPY: blt->stencil_read = @@ -282,6 +284,10 @@ void tu_blit(struct tu_cmd_buffer *cmdbuf, struct tu_cs *cs, tu6_emit_event_write(cmdbuf, cs, PC_CCU_INVALIDATE_COLOR, false); tu6_emit_event_write(cmdbuf, cs, PC_CCU_INVALIDATE_DEPTH, false); + tu_cs_emit_wfi(cs); + tu_cs_emit_regs(cs, + A6XX_RB_CCU_CNTL(.offset = phys_dev->ccu_offset_bypass)); + /* buffer copy setup */ tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1); tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BLIT2DSCALE)); diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c index f61f5b89f94..f20019a1b30 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.c +++ b/src/freedreno/vulkan/tu_cmd_buffer.c @@ -1047,11 +1047,14 @@ tu6_emit_restart_index(struct tu_cs *cs, uint32_t restart_index) static void tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs) { + const struct tu_physical_device *phys_dev = cmd->device->physical_device; + tu6_emit_cache_flush(cmd, cs); tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 0xfffff); - tu_cs_emit_write_reg(cs, REG_A6XX_RB_CCU_CNTL, A6XX_RB_CCU_CNTL_OFFSET(0x20000)); + tu_cs_emit_regs(cs, + A6XX_RB_CCU_CNTL(.offset = phys_dev->ccu_offset_bypass)); tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000); tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE04, 0x8); tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0); @@ -1391,11 +1394,6 @@ tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu_cs_emit_pkt7(cs, CP_SET_MODE, 1); tu_cs_emit(cs, 0x0); - tu_cs_emit_wfi(cs); - - tu_cs_emit_regs(cs, - A6XX_RB_CCU_CNTL(.dword = phys_dev->magic.RB_CCU_CNTL_gmem)); - cmd->wait_for_idle = false; } @@ -1476,6 +1474,7 @@ static void tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs, const struct VkRect2D *renderArea) { + const struct tu_physical_device *phys_dev = cmd->device->physical_device; const struct tu_framebuffer *fb = cmd->state.framebuffer; assert(fb->width > 0 && fb->height > 0); @@ -1498,7 +1497,7 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs, tu6_emit_wfi(cmd, cs); tu_cs_emit_regs(cs, - A6XX_RB_CCU_CNTL(.offset = 0x20000)); + A6XX_RB_CCU_CNTL(.offset = phys_dev->ccu_offset_bypass)); /* enable stream-out, with sysmem there is only one pass: */ tu_cs_emit_regs(cs, @@ -1558,10 +1557,9 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1); tu_cs_emit(cs, 0x0); - /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */ tu6_emit_wfi(cmd, cs); tu_cs_emit_regs(cs, - A6XX_RB_CCU_CNTL(.dword = phys_dev->magic.RB_CCU_CNTL_gmem)); + A6XX_RB_CCU_CNTL(.offset = phys_dev->ccu_offset_gmem, .gmem = 1)); const struct tu_tiling_config *tiling = &cmd->state.tiling_config; if (use_hw_binning(cmd)) { diff --git a/src/freedreno/vulkan/tu_device.c b/src/freedreno/vulkan/tu_device.c index a784f026b00..e908fc0a862 100644 --- a/src/freedreno/vulkan/tu_device.c +++ b/src/freedreno/vulkan/tu_device.c @@ -268,9 +268,8 @@ tu_physical_device_init(struct tu_physical_device *device, device->tile_align_w = 64; device->tile_align_h = 16; device->magic.RB_UNKNOWN_8E04_blit = 0x00100000; - device->magic.RB_CCU_CNTL_gmem = A6XX_RB_CCU_CNTL_OFFSET(0x7c000) | - A6XX_RB_CCU_CNTL_GMEM | - A6XX_RB_CCU_CNTL_UNK2; + device->ccu_offset_gmem = 0x7c000; /* 0x7e000 in some cases? */ + device->ccu_offset_bypass = 0x10000; device->magic.PC_UNKNOWN_9805 = 0x0; device->magic.SP_UNKNOWN_A0F8 = 0x0; break; @@ -279,9 +278,8 @@ tu_physical_device_init(struct tu_physical_device *device, device->tile_align_w = 64; device->tile_align_h = 16; device->magic.RB_UNKNOWN_8E04_blit = 0x01000000; - device->magic.RB_CCU_CNTL_gmem = A6XX_RB_CCU_CNTL_OFFSET(0xf8000) | - A6XX_RB_CCU_CNTL_GMEM | - A6XX_RB_CCU_CNTL_UNK2; + device->ccu_offset_gmem = 0xf8000; + device->ccu_offset_bypass = 0x20000; device->magic.PC_UNKNOWN_9805 = 0x1; device->magic.SP_UNKNOWN_A0F8 = 0x1; break; diff --git a/src/freedreno/vulkan/tu_private.h b/src/freedreno/vulkan/tu_private.h index d5d63a6bd79..4378406eb93 100644 --- a/src/freedreno/vulkan/tu_private.h +++ b/src/freedreno/vulkan/tu_private.h @@ -316,10 +316,11 @@ struct tu_physical_device uint64_t gmem_base; uint32_t tile_align_w; uint32_t tile_align_h; + uint32_t ccu_offset_gmem; + uint32_t ccu_offset_bypass; struct { uint32_t RB_UNKNOWN_8E04_blit; /* for CP_BLIT's */ - uint32_t RB_CCU_CNTL_gmem; /* for GMEM */ uint32_t PC_UNKNOWN_9805; uint32_t SP_UNKNOWN_A0F8; } magic; -- 2.30.2