From f49f84c3917bced4fef6c8c43a1f1ddf6c6dc2e9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 12 May 2020 13:34:30 +0100 Subject: [PATCH] when doing LD-immediate only acknowledge register 1 rd-req --- src/soc/experiment/compldst_multi.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py index a2dcaa12..a15a88fd 100644 --- a/src/soc/experiment/compldst_multi.py +++ b/src/soc/experiment/compldst_multi.py @@ -571,7 +571,10 @@ def load(dut, src1, src2, imm, imm_ok=True, update=False): yield yield dut.issue_i.eq(0) yield - yield dut.rd.go.eq(0b11) + if imm_ok: + yield dut.rd.go.eq(0b01) + else: + yield dut.rd.go.eq(0b11) yield from wait_for(dut.rd.rel) yield dut.rd.go.eq(0) -- 2.30.2