From f4ab58c1a07c58525018649573ffff92eb3ccf19 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 21 Oct 2019 10:42:30 +0200 Subject: [PATCH] radv: do not create meta pipelines with 16 samples The driver only supports up to 8 samples, so it's useless to create more pipelines than needed. This fixes a conditional jump reported by Valgrind on GFX10: ==194282== Conditional jump or move depends on uninitialised value(s) ==194282== at 0xDBF925A: radv_gfx10_compute_bin_size (radv_pipeline.c:3242) ==194282== by 0xDBF95A6: radv_pipeline_generate_binning_state (radv_pipeline.c:3334) ==194282== by 0xDBFC1A0: radv_pipeline_generate_pm4 (radv_pipeline.c:4440) ==194282== by 0xDBFD15E: radv_pipeline_init (radv_pipeline.c:4764) ==194282== by 0xDBFD23E: radv_graphics_pipeline_create (radv_pipeline.c:4788) ==194282== by 0xDBB95A3: create_pipeline (radv_meta_clear.c:114) ==194282== by 0xDBB9AC5: create_color_pipeline (radv_meta_clear.c:297) ==194282== by 0xDBBCF05: radv_device_init_meta_clear_state (radv_meta_clear.c:1277) ==194282== by 0xDB9ACD9: radv_device_init_meta (radv_meta.c:363) ==194282== by 0xDB7FE3A: radv_CreateDevice (radv_device.c:2080 This is caused by an out of bound access of 'fmask_array' (ie. index is 4 as for 16 samples). Cc: Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_meta_blit2d.c | 4 ++-- src/amd/vulkan/radv_private.h | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/amd/vulkan/radv_meta_blit2d.c b/src/amd/vulkan/radv_meta_blit2d.c index de3d5791611..e9aa951ff22 100644 --- a/src/amd/vulkan/radv_meta_blit2d.c +++ b/src/amd/vulkan/radv_meta_blit2d.c @@ -698,7 +698,7 @@ radv_device_finish_meta_blit2d_state(struct radv_device *device) state->blit2d_stencil_only_rp[j], &state->alloc); } - for (unsigned log2_samples = 0; log2_samples < 1 + MAX_SAMPLES_LOG2; ++log2_samples) { + for (unsigned log2_samples = 0; log2_samples < MAX_SAMPLES_LOG2; ++log2_samples) { for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) { radv_DestroyPipelineLayout(radv_device_to_handle(device), state->blit2d[log2_samples].p_layouts[src], @@ -1310,7 +1310,7 @@ radv_device_init_meta_blit2d_state(struct radv_device *device, bool on_demand) VkResult result; bool create_3d = device->physical_device->rad_info.chip_class == GFX9; - for (unsigned log2_samples = 0; log2_samples < 1 + MAX_SAMPLES_LOG2; log2_samples++) { + for (unsigned log2_samples = 0; log2_samples < MAX_SAMPLES_LOG2; log2_samples++) { for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) { if (src == BLIT2D_SRC_TYPE_IMAGE_3D && !create_3d) continue; diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 1158a30f767..0f5aac29484 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -475,7 +475,7 @@ struct radv_meta_state { VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES]; VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES]; VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES]; - } clear[1 + MAX_SAMPLES_LOG2]; + } clear[MAX_SAMPLES_LOG2]; VkPipelineLayout clear_color_p_layout; VkPipelineLayout clear_depth_p_layout; @@ -518,7 +518,7 @@ struct radv_meta_state { VkPipeline depth_only_pipeline[5]; VkPipeline stencil_only_pipeline[5]; - } blit2d[1 + MAX_SAMPLES_LOG2]; + } blit2d[MAX_SAMPLES_LOG2]; VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT]; VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT]; @@ -623,7 +623,7 @@ struct radv_meta_state { VkPipeline decompress_pipeline; VkPipeline resummarize_pipeline; VkRenderPass pass; - } depth_decomp[1 + MAX_SAMPLES_LOG2]; + } depth_decomp[MAX_SAMPLES_LOG2]; struct { VkPipelineLayout p_layout; -- 2.30.2