From f4c1736d72b030ee5ae958d04905e944e3d7b5f4 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Thu, 3 Jun 2021 12:42:38 +0100
Subject: [PATCH]

---
 openpower/sv/int_fp_mv.mdwn | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index 4faf14df3..de5acef7e 100644
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -77,15 +77,19 @@ All of the following instructions use the standard OpenPower conversion to/from
 
 ## FPR to GPR moves
 
-`fmvtg RT, FRA`
+* `fmvtg RT, FRA`
+* `fmvtg. RT, FRA`
 
-move a 64-bit float from a FPR to a GPR, just copying bits.
+move a 64-bit float from a FPR to a GPR, just copying bits directly.
+Rc=1 tests RT and sets CR0
 
-`fmvtgs RT, FRA`
+* `fmvtgs RT, FRA`
+* `fmvtgs. RT, FRA`
 
 move a 32-bit float from a FPR to a GPR, just copying bits. Converts the
 64-bit float in `FRA` to a 32-bit float, then writes the 32-bit float to
 `RT`.
+Rc=1 tests RT and sets CR0
 
 ## GPR to FPR moves
 
@@ -99,6 +103,8 @@ move a 32-bit float from a GPR to a FPR, just copying bits. Converts the
 32-bit float in `RA` to a 64-bit float, then writes the 64-bit float to
 `FRT`.
 
+TODO: Rc=1 variants? also, any exceptions or FPSCR bits set?
+
 ### Float load immediate (kinda a variant of `fmvfg`)
 
 `fmvis FRT, FI`
-- 
2.30.2