From f4f9a9dc64fbf544a05a76e4634ed9f38cce40fc Mon Sep 17 00:00:00 2001
From: Wei Xiao <wei3.xiao@intel.com>
Date: Thu, 17 Jan 2019 09:34:00 +0000
Subject: [PATCH] re PR target/88794 (fixupimm intrinsics are unusable)

2019-01-17  Wei Xiao  <wei3.xiao@intel.com>

        PR target/88794
        Revert:
        2018-11-12  Wei Xiao  <wei3.xiao@intel.com>

        * config/i386/sse.md: Combine VFIXUPIMM* patterns
        (<avx512>_fixupimm<mode>_maskz<round_saeonly_expand_name>): Update.
        (<avx512>_fixupimm<mode><sd_maskz_name><round_saeonly_name>): Update.
        (<avx512>_fixupimm<mode>_mask<round_saeonly_name>): Remove.
        (avx512f_sfixupimm<mode>_maskz<round_saeonly_expand_name>): Update.
        (avx512f_sfixupimm<mode><sd_maskz_name><round_saeonly_name>): Update.
        (avx512f_sfixupimm<mode>_mask<round_saeonly_name>): Remove.

From-SVN: r268012
---
 gcc/ChangeLog          | 14 ++++++++++++++
 gcc/config/i386/sse.md | 42 ++++++++++++++++++++++++++++++++++++------
 2 files changed, 50 insertions(+), 6 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 47bccb5bbab..e379d2edcbe 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2019-01-17  Wei Xiao  <wei3.xiao@intel.com>
+
+	PR target/88794
+	Revert:
+	2018-11-12  Wei Xiao  <wei3.xiao@intel.com>
+
+	* config/i386/sse.md: Combine VFIXUPIMM* patterns
+	(<avx512>_fixupimm<mode>_maskz<round_saeonly_expand_name>): Update.
+	(<avx512>_fixupimm<mode><sd_maskz_name><round_saeonly_name>): Update.
+	(<avx512>_fixupimm<mode>_mask<round_saeonly_name>): Remove.
+	(avx512f_sfixupimm<mode>_maskz<round_saeonly_expand_name>): Update.
+	(avx512f_sfixupimm<mode><sd_maskz_name><round_saeonly_name>): Update.
+	(avx512f_sfixupimm<mode>_mask<round_saeonly_name>): Remove.
+
 2019-01-17  Wei Xiao  <wei3.xiao@intel.com>
 
 	PR target/88794
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e4697ba0359..48708a41b3b 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -8867,14 +8867,14 @@
    (match_operand:<avx512fmaskmode> 4 "register_operand")]
   "TARGET_AVX512F"
 {
-  emit_insn (gen_<avx512>_fixupimm<mode>_mask<round_saeonly_expand_name> (
+  emit_insn (gen_<avx512>_fixupimm<mode>_maskz_1<round_saeonly_expand_name> (
 	operands[0], operands[1], operands[2], operands[3],
 	CONST0_RTX (<MODE>mode), operands[4]
 	<round_saeonly_expand_operand5>));
   DONE;
 })
 
-(define_insn "<avx512>_fixupimm<mode><mask_name><round_saeonly_name>"
+(define_insn "<avx512>_fixupimm<mode><sd_maskz_name><round_saeonly_name>"
   [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v")
         (unspec:VF_AVX512VL
           [(match_operand:VF_AVX512VL 1 "register_operand" "v")
@@ -8882,7 +8882,22 @@
            (match_operand:SI 3 "const_0_to_255_operand")]
            UNSPEC_FIXUPIMM))]
   "TARGET_AVX512F"
-  "vfixupimm<ssemodesuffix>\t{%3, <round_saeonly_mask_op4>%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2<round_saeonly_mask_op4>, %3}";
+  "vfixupimm<ssemodesuffix>\t{%3, <round_saeonly_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %2<round_saeonly_sd_mask_op4>, %3}";
+  [(set_attr "prefix" "evex")
+   (set_attr "mode" "<MODE>")])
+
+(define_insn "<avx512>_fixupimm<mode>_mask<round_saeonly_name>"
+  [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v")
+	(vec_merge:VF_AVX512VL
+          (unspec:VF_AVX512VL
+            [(match_operand:VF_AVX512VL 1 "register_operand" "v")
+             (match_operand:<sseintvecmode> 2 "nonimmediate_operand" "<round_saeonly_constraint>")
+             (match_operand:SI 3 "const_0_to_255_operand")]
+             UNSPEC_FIXUPIMM)
+	  (match_operand:VF_AVX512VL 4 "register_operand" "0")
+	  (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
+  "TARGET_AVX512F"
+  "vfixupimm<ssemodesuffix>\t{%3, <round_saeonly_op6>%2, %1, %0%{%5%}|%0%{%5%}, %1, %2<round_saeonly_op6>, %3}";
   [(set_attr "prefix" "evex")
    (set_attr "mode" "<MODE>")])
 
@@ -8894,14 +8909,14 @@
    (match_operand:<avx512fmaskmode> 4 "register_operand")]
   "TARGET_AVX512F"
 {
-  emit_insn (gen_avx512f_sfixupimm<mode>_mask<round_saeonly_expand_name> (
+  emit_insn (gen_avx512f_sfixupimm<mode>_maskz_1<round_saeonly_expand_name> (
 	operands[0], operands[1], operands[2], operands[3],
 	CONST0_RTX (<MODE>mode), operands[4]
 	<round_saeonly_expand_operand5>));
   DONE;
 })
 
-(define_insn "avx512f_sfixupimm<mode><mask_name><round_saeonly_name>"
+(define_insn "avx512f_sfixupimm<mode><sd_maskz_name><round_saeonly_name>"
   [(set (match_operand:VF_128 0 "register_operand" "=v")
         (unspec:VF_128
           [(match_operand:VF_128 1 "register_operand" "v")
@@ -8909,7 +8924,22 @@
 	     (match_operand:SI 3 "const_0_to_255_operand")]
 	    UNSPEC_FIXUPIMM))]
    "TARGET_AVX512F"
-  "vfixupimm<ssescalarmodesuffix>\t{%3, <round_saeonly_mask_op4>%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %<iptr>2<round_saeonly_mask_op4>, %3}";
+   "vfixupimm<ssescalarmodesuffix>\t{%3, <round_saeonly_sd_mask_op4>%2, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %<iptr>2<round_saeonly_sd_mask_op4>, %3}";
+   [(set_attr "prefix" "evex")
+   (set_attr "mode" "<ssescalarmode>")])
+
+(define_insn "avx512f_sfixupimm<mode>_mask<round_saeonly_name>"
+  [(set (match_operand:VF_128 0 "register_operand" "=v")
+	(vec_merge:VF_128
+	    (unspec:VF_128
+	       [(match_operand:VF_128 1 "register_operand" "v")
+		(match_operand:<sseintvecmode> 2 "<round_saeonly_nimm_predicate>" "<round_saeonly_constraint>")
+		(match_operand:SI 3 "const_0_to_255_operand")]
+	       UNSPEC_FIXUPIMM)
+	  (match_operand:VF_128 4 "register_operand" "0")
+	  (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
+  "TARGET_AVX512F"
+  "vfixupimm<ssescalarmodesuffix>\t{%3, <round_saeonly_op6>%2, %1, %0%{%5%}|%0%{%5%}, %1, %<iptr>2<round_saeonly_op6>, %3}";
   [(set_attr "prefix" "evex")
    (set_attr "mode" "<ssescalarmode>")])
 
-- 
2.30.2