From f51c724c7e65498f1c0af15c6d566397257b6d5f Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Mon, 26 Nov 2018 17:50:03 +0000 Subject: [PATCH] [arm][1/3] Rename mul64 attr to widen_mul64 The mul64 attribute in types.md causes some confusion as it is used to represent aarch32 instructions that do widening multiplication to generate 32->64 bit results. But these types are shared with aarch64, which has native 64-bit multiplication operations. Those are currently not properly represented, which I will fix in follow-up patches. For now, this patch renames the mul64 attribute to widen_mul64 to more clearly communicate its meaning. It mechanically updates all users of that name in config/arm/ (there are no users in config/aarch64). There is thus no change in behaviour. * config/arm/types.md (mul64): Rename to... (widen_mul64): ... This. * config/arm/arm-generic.md: Rename mul64 to widen_mul64. * config/arm/cortex-a15.md: Likewise. * config/arm/cortex-a5.md: Likewise. * config/arm/cortex-a53.md: Likewise. * config/arm/cortex-a57.md: Likewise. * config/arm/cortex-a7.md: Likewise. * config/arm/cortex-m4.md: Likewise. * config/arm/exynos-m1.md: Likewise. * config/arm/marvell-pj4.md: Likewise. * config/arm/xgene1.md: Likewise. From-SVN: r266471 --- gcc/ChangeLog | 15 +++++++++++++++ gcc/config/arm/arm-generic.md | 8 ++++---- gcc/config/arm/cortex-a15.md | 2 +- gcc/config/arm/cortex-a5.md | 2 +- gcc/config/arm/cortex-a53.md | 2 +- gcc/config/arm/cortex-a57.md | 2 +- gcc/config/arm/cortex-a7.md | 2 +- gcc/config/arm/cortex-m4.md | 2 +- gcc/config/arm/exynos-m1.md | 2 +- gcc/config/arm/marvell-pj4.md | 4 ++-- gcc/config/arm/types.md | 4 ++-- gcc/config/arm/xgene1.md | 4 ++-- 12 files changed, 32 insertions(+), 17 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b68fdad91ad..f98017b29e3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2018-11-26 Kyrylo Tkachov + + * config/arm/types.md (mul64): Rename to... + (widen_mul64): ... This. + * config/arm/arm-generic.md: Rename mul64 to widen_mul64. + * config/arm/cortex-a15.md: Likewise. + * config/arm/cortex-a5.md: Likewise. + * config/arm/cortex-a53.md: Likewise. + * config/arm/cortex-a57.md: Likewise. + * config/arm/cortex-a7.md: Likewise. + * config/arm/cortex-m4.md: Likewise. + * config/arm/exynos-m1.md: Likewise. + * config/arm/marvell-pj4.md: Likewise. + * config/arm/xgene1.md: Likewise. + 2018-11-26 Richard Biener PR tree-optimization/88182 diff --git a/gcc/config/arm/arm-generic.md b/gcc/config/arm/arm-generic.md index da97303c758..9b8f65c4314 100644 --- a/gcc/config/arm/arm-generic.md +++ b/gcc/config/arm/arm-generic.md @@ -116,7 +116,7 @@ (and (eq_attr "generic_sched" "yes") (and (eq_attr "ldsched" "no") (ior (eq_attr "mul32" "yes") - (eq_attr "mul64" "yes")))) + (eq_attr "widen_mul64" "yes")))) "core*16") (define_insn_reservation "mult_ldsched_strongarm" 3 @@ -124,7 +124,7 @@ (and (eq_attr "ldsched" "yes") (and (eq_attr "tune" "strongarm") (ior (eq_attr "mul32" "yes") - (eq_attr "mul64" "yes"))))) + (eq_attr "widen_mul64" "yes"))))) "core*2") (define_insn_reservation "mult_ldsched" 4 @@ -132,7 +132,7 @@ (and (eq_attr "ldsched" "yes") (and (eq_attr "tune" "!strongarm") (ior (eq_attr "mul32" "yes") - (eq_attr "mul64" "yes"))))) + (eq_attr "widen_mul64" "yes"))))) "core*4") (define_insn_reservation "multi_cycle" 32 @@ -141,7 +141,7 @@ (and (eq_attr "type" "!load_byte,load_4,load_8,load_12,load_16,\ store_4,store_8,store_12,store_16") (not (ior (eq_attr "mul32" "yes") - (eq_attr "mul64" "yes")))))) + (eq_attr "widen_mul64" "yes")))))) "core*32") (define_insn_reservation "single_cycle" 1 diff --git a/gcc/config/arm/cortex-a15.md b/gcc/config/arm/cortex-a15.md index eb923ff18c6..9bec99ae763 100644 --- a/gcc/config/arm/cortex-a15.md +++ b/gcc/config/arm/cortex-a15.md @@ -105,7 +105,7 @@ ;; 64-bit multiplies (define_insn_reservation "cortex_a15_mult64" 4 (and (eq_attr "tune" "cortexa15") - (eq_attr "mul64" "yes")) + (eq_attr "widen_mul64" "yes")) "ca15_issue1,ca15_mx*2") ;; Integer divide diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md index 8e1fea5f969..9ff98a236b7 100644 --- a/gcc/config/arm/cortex-a5.md +++ b/gcc/config/arm/cortex-a5.md @@ -93,7 +93,7 @@ (define_insn_reservation "cortex_a5_mul" 2 (and (eq_attr "tune" "cortexa5") (ior (eq_attr "mul32" "yes") - (eq_attr "mul64" "yes"))) + (eq_attr "widen_mul64" "yes"))) "cortex_a5_ex1") ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index d150ed20aed..5e9fa88c4a1 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -111,7 +111,7 @@ (define_insn_reservation "cortex_a53_mul" 4 (and (eq_attr "tune" "cortexa53") (ior (eq_attr "mul32" "yes") - (eq_attr "mul64" "yes"))) + (eq_attr "widen_mul64" "yes"))) "cortex_a53_slot_any+cortex_a53_imul") ;; From the perspective of the GCC scheduling state machine, if we wish to diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md index a029aeb5fa4..89e322cc248 100644 --- a/gcc/config/arm/cortex-a57.md +++ b/gcc/config/arm/cortex-a57.md @@ -328,7 +328,7 @@ (define_insn_reservation "cortex_a57_mult32" 3 (and (eq_attr "tune" "cortexa57") (ior (eq_attr "mul32" "yes") - (eq_attr "mul64" "yes"))) + (eq_attr "widen_mul64" "yes"))) "ca57_mx") ;; Integer divide diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md index 1765aeaf900..fee25161a9e 100644 --- a/gcc/config/arm/cortex-a7.md +++ b/gcc/config/arm/cortex-a7.md @@ -171,7 +171,7 @@ (define_insn_reservation "cortex_a7_mul" 2 (and (eq_attr "tune" "cortexa7") (ior (eq_attr "mul32" "yes") - (eq_attr "mul64" "yes"))) + (eq_attr "widen_mul64" "yes"))) "cortex_a7_both") ;; Forward the result of a multiply operation to the accumulator diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md index d2b2c694636..419f094999e 100644 --- a/gcc/config/arm/cortex-m4.md +++ b/gcc/config/arm/cortex-m4.md @@ -44,7 +44,7 @@ mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\ mrs,multiple,no_insn") (ior (eq_attr "mul32" "yes") - (eq_attr "mul64" "yes")))) + (eq_attr "widen_mul64" "yes")))) "cortex_m4_ex") ;; Byte, half-word and word load is two cycles. diff --git a/gcc/config/arm/exynos-m1.md b/gcc/config/arm/exynos-m1.md index e8f962f1875..2bdfd187ea8 100644 --- a/gcc/config/arm/exynos-m1.md +++ b/gcc/config/arm/exynos-m1.md @@ -417,7 +417,7 @@ (define_insn_reservation "exynos_m1_mlal" 4 (and (eq_attr "tune" "exynosm1") - (eq_attr "mul64" "yes")) + (eq_attr "widen_mul64" "yes")) "em1_alu, em1_c") ;; Integer divide diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md index 143a21e96ae..0e24a9abd09 100644 --- a/gcc/config/arm/marvell-pj4.md +++ b/gcc/config/arm/marvell-pj4.md @@ -119,8 +119,8 @@ (define_insn_reservation "pj4_ir_mul" 3 (and (eq_attr "tune" "marvell_pj4") (ior (eq_attr "mul32" "yes") - (eq_attr "mul64" "yes"))) - "pj4_is,pj4_mul,nothing*2,pj4_cp") + (eq_attr "widen_mul64" "yes"))) + "pj4_is,pj4_mul,nothing*2,pj4_cp") (define_insn_reservation "pj4_ir_div" 20 (and (eq_attr "tune" "marvell_pj4") diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index 055cb3e7d94..3f10367545c 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -1100,8 +1100,8 @@ (const_string "yes") (const_string "no"))) -; Is this an (integer side) multiply with a 64-bit result? -(define_attr "mul64" "no,yes" +; Is this an (integer side) widening multiply with a 64-bit result? +(define_attr "widen_mul64" "no,yes" (if_then_else (eq_attr "type" "smlalxy,umull,umulls,umaal,umlal,umlals,smull,smulls,smlal,smlals") diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md index b7bec62a406..893cb37e4bb 100644 --- a/gcc/config/arm/xgene1.md +++ b/gcc/config/arm/xgene1.md @@ -169,9 +169,9 @@ (eq_attr "mul32" "yes")) "xgene1_decode2op, xgene1_IXB + xgene1_multiply, xgene1_multiply, nothing, xgene1_IXB_compl") -(define_insn_reservation "xgene1_mul64" 5 +(define_insn_reservation "xgene1_widen_mul64" 5 (and (eq_attr "tune" "xgene1") - (eq_attr "mul64" "yes")) + (eq_attr "widen_mul64" "yes")) "xgene1_decode2op, xgene1_IXB + xgene1_multiply, xgene1_multiply, nothing*2, xgene1_IXB_compl") (define_insn_reservation "xgene1_div" 34 -- 2.30.2