From f5397c2b62277da0dd953ca3389fc6e02f2a7e83 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 14 Jan 2022 14:02:19 +0000 Subject: [PATCH] split out CacheTag Record to separate structure --- src/soc/experiment/dcache.py | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 971976bd..9f6ba0d4 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -164,16 +164,23 @@ print (" TAG_WIDTH", TAG_WIDTH) print (" NUM_WAYS", NUM_WAYS) print (" NUM_LINES", NUM_LINES) -def CacheTagArray(): + +def CacheTag(name=None): tag_layout = [('valid', NUM_WAYS), ('tag', TAG_RAM_WIDTH), ] - return Array(Record(tag_layout, name="tag%d" % x) for x in range(NUM_LINES)) + return Record(tag_layout, name=name) + + +def CacheTagArray(): + return Array(CacheTag(name="tag%d" % x) for x in range(NUM_LINES)) + def RowPerLineValidArray(): return Array(Signal(name="rows_valid%d" % x) \ for x in range(ROW_PER_LINE)) + # L1 TLB TLB_SET_BITS = log2_int(TLB_SET_SIZE) TLB_WAY_BITS = log2_int(TLB_NUM_WAYS) -- 2.30.2