From f547d317ad82742219a9ce62776fba06fd703af0 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Fri, 19 Aug 2022 15:50:57 +0100
Subject: [PATCH]

---
 openpower/sv/ldst.mdwn | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 62e6a2c2d..765f43a7b 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -30,8 +30,9 @@ Memory Operations as well.
 Vectorised Load and Store also presents an extra dimension (literally)
 which creates scenarios unique to Vector applications, that a Scalar
 (and even a SIMD) ISA simply never encounters.  SVP64 endeavours to
-add such modes without changing the behaviour of the underlying Base
-(Scalar) v3.0B operations.
+add the modes typically found in *all* Scalable Vector ISAs,
+without changing the behaviour of the underlying Base
+(Scalar) v3.0B operations in any way.
 
 # Modes overview
 
-- 
2.30.2