From f54f7e178896567d0d90d2ed96e175e804b2883e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 28 Jun 2020 13:17:09 +0100 Subject: [PATCH] sram address do not cut by LSBs --- src/soc/bus/test/test_minerva.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py index d9c7f101..01c00b25 100644 --- a/src/soc/bus/test/test_minerva.py +++ b/src/soc/bus/test/test_minerva.py @@ -11,7 +11,7 @@ class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit): m = super().elaborate(platform) comb = m.d.comb # small 16-entry Memory - self.mem = memory = Memory(width=self.data_wid, depth=16) + self.mem = memory = Memory(width=self.data_wid, depth=32) m.submodules.sram = sram = SRAM(memory=memory, granularity=8, features={'cti', 'bte', 'err'}) dbus = self.dbus @@ -27,7 +27,7 @@ class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit): comb += getattr(sram.bus, fanout).eq(getattr(dbus, fanout)) for fanin in fanins: comb += getattr(dbus, fanin).eq(getattr(sram.bus, fanin)) - # SRAM is row-addressed, so ignore LSBs - comb += sram.bus.adr.eq(dbus.adr[self.adr_lsbs:]) + # connect address + comb += sram.bus.adr.eq(dbus.adr) return m -- 2.30.2