From f564a658517f510dce12c5ef8bcc2a9ec9dd055b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 18 Apr 2015 09:33:34 +0200
Subject: [PATCH] Added ice40 test_arith

---
 techlibs/ice40/tests/test_arith.v  |  3 +++
 techlibs/ice40/tests/test_arith.ys | 10 ++++++++++
 2 files changed, 13 insertions(+)
 create mode 100644 techlibs/ice40/tests/test_arith.v
 create mode 100644 techlibs/ice40/tests/test_arith.ys

diff --git a/techlibs/ice40/tests/test_arith.v b/techlibs/ice40/tests/test_arith.v
new file mode 100644
index 000000000..77f79b973
--- /dev/null
+++ b/techlibs/ice40/tests/test_arith.v
@@ -0,0 +1,3 @@
+module test(input [4:0] a, b, c, output [4:0] y);
+	assign y = ((a+b) ^ (a-c)) - ((a*b) + (a*c) - (b*c));
+endmodule
diff --git a/techlibs/ice40/tests/test_arith.ys b/techlibs/ice40/tests/test_arith.ys
new file mode 100644
index 000000000..160c767fb
--- /dev/null
+++ b/techlibs/ice40/tests/test_arith.ys
@@ -0,0 +1,10 @@
+read_verilog test_arith.v
+synth_ice40
+techmap -map ../cells_sim.v
+rename test gate
+
+read_verilog test_arith.v
+rename test gold
+
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 -show-ports miter
-- 
2.30.2