From f57e234fdd52331d0aa6656a36efdebea9d11e9d Mon Sep 17 00:00:00 2001 From: =?utf8?q?Samuel=20Iglesias=20Gons=C3=A1lvez?= Date: Tue, 25 Apr 2017 12:28:18 +0200 Subject: [PATCH] i965/vec4: don't modify regioning parameters to the sources of DF align1 instructions MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The regioning parameters are now properly set by convert_to_hw_regs() and we don't need to fix them in the generator. That latter fix previously done in the generator was strictly speaking wrong for any non-identity regions. Signed-off-by: Samuel Iglesias Gonsálvez Cc: "17.1" Reviewed-by: Francisco Jerez --- src/intel/compiler/brw_vec4_generator.cpp | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp index e786ac6a0ca..753b00c4ed1 100644 --- a/src/intel/compiler/brw_vec4_generator.cpp +++ b/src/intel/compiler/brw_vec4_generator.cpp @@ -1980,8 +1980,6 @@ generate_code(struct brw_codegen *p, else spread_dst = stride(dst, 8, 4, 2); - src[0].vstride = BRW_VERTICAL_STRIDE_4; - src[0].width = BRW_WIDTH_4; brw_MOV(p, spread_dst, src[0]); brw_set_default_access_mode(p, BRW_ALIGN_16); @@ -2016,9 +2014,7 @@ generate_code(struct brw_codegen *p, src[0] = retype(src[0], BRW_REGISTER_TYPE_UD); if (inst->opcode == VEC4_OPCODE_PICK_HIGH_32BIT) src[0] = suboffset(src[0], 1); - src[0].vstride = BRW_VERTICAL_STRIDE_8; - src[0].width = BRW_WIDTH_4; - src[0].hstride = BRW_HORIZONTAL_STRIDE_2; + src[0] = spread(src[0], 2); brw_MOV(p, dst, src[0]); brw_set_default_access_mode(p, BRW_ALIGN_16); @@ -2041,9 +2037,6 @@ generate_code(struct brw_codegen *p, dst.hstride = BRW_HORIZONTAL_STRIDE_2; src[0] = retype(src[0], BRW_REGISTER_TYPE_UD); - src[0].vstride = BRW_VERTICAL_STRIDE_4; - src[0].width = BRW_WIDTH_4; - src[0].hstride = BRW_HORIZONTAL_STRIDE_1; brw_MOV(p, dst, src[0]); brw_set_default_access_mode(p, BRW_ALIGN_16); -- 2.30.2