From f57f94eedd990c5a52b7a53fce3dfedd7eb75348 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 30 Dec 2021 14:24:20 +0000 Subject: [PATCH] rename nia to cia in MMU input record and mmu FSM this gets the PC passed over when an instruction fault occurs in MSR.IR=True mode. previous tests were only working because the instructions started at 0x0000 and a full cache line was read by I-Cache. tests greater than a cache line would have failed --- src/soc/experiment/mmu.py | 16 +++++++++++++++- src/soc/fu/mmu/fsm.py | 6 +++--- src/soc/fu/mmu/mmu_input_record.py | 2 +- src/soc/simple/test/test_issuer_mmu_ifetch.py | 5 +++-- 4 files changed, 22 insertions(+), 7 deletions(-) diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py index 48502690..2176855d 100644 --- a/src/soc/experiment/mmu.py +++ b/src/soc/experiment/mmu.py @@ -732,6 +732,15 @@ def dcache_get(dut): 0x12010: 0x0a00010000000000, # page table } + # microwatt mmu.bin test 12, instruction-side + # PRTBL must be set to 0x12000, PID to 1, iside to 1 + mem = { + 0x0: 0x000000, # to get mtspr prtbl working + 0x13920: 0x01110000000000c0, # leaf node + 0x10008: 0x0930010000000080, # directory node + 0x12010: 0x0a00010000000000, # page table + } + while not stop: while True: # wait for dc_valid if stop: @@ -837,8 +846,13 @@ def mmu_sim(dut): addr = 0x39fffd # microwatt mmu.bin test 5 addr = 0x3a0000 # microwatt mmu.bin test 5 + # microwatt mmu.bin test 12 is instruction-side + addr = 0x324000 # microwatt mmu.bin test 12 + iside = 1 + # MMU PTE request - yield dut.l_in.load.eq(1) + yield dut.l_in.iside.eq(iside) + yield dut.l_in.load.eq(0) yield dut.l_in.priv.eq(1) yield dut.l_in.addr.eq(addr) yield dut.l_in.valid.eq(1) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index a9b5df22..24be3f54 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -91,7 +91,7 @@ class FSMMMUStage(ControlBase): i_data, o_data = self.p.i_data, self.n.o_data op = i_data.ctx.op - nia_i = op.nia + cia_i = op.cia msr_i = op.msr a_i, b_i, spr1_i = i_data.ra, i_data.rb, i_data.spr1 o, exc_o, spr1_o = o_data.o, o_data.exception, o_data.spr1 @@ -216,7 +216,7 @@ class FSMMMUStage(ControlBase): ########## with m.Case(MicrOp.OP_FETCH_FAILED): - comb += Display("MMUTEST: OP_FETCH_FAILED: @%x", nia_i) + comb += Display("MMUTEST: OP_FETCH_FAILED: @%x", cia_i) # trigger an instruction fetch failed MMU event. # PowerDecoder2 drops svstate.pc into NIA for us # really, this should be direct communication with the @@ -226,7 +226,7 @@ class FSMMMUStage(ControlBase): comb += valid.eq(1) # start "pulse" comb += ldst.instr_fault.eq(blip) comb += ldst.priv_mode.eq(~msr_i[MSR.PR]) - comb += ldst.maddr.eq(nia_i) + comb += ldst.maddr.eq(cia_i) # XXX should not access this! comb += done.eq(ldst.done) comb += self.debug0.eq(3) diff --git a/src/soc/fu/mmu/mmu_input_record.py b/src/soc/fu/mmu/mmu_input_record.py index 54256ca5..aea08bc8 100644 --- a/src/soc/fu/mmu/mmu_input_record.py +++ b/src/soc/fu/mmu/mmu_input_record.py @@ -13,7 +13,7 @@ class CompMMUOpSubset(CompOpSubsetBase): layout = (('insn_type', MicrOp), ('fn_unit', Function), ('insn', 32), - ('nia', 64), # for instruction fault (MMU PTE lookup) + ('cia', 64), # for instruction fault (MMU PTE lookup) ('msr', 64), # ditto, to set priv_mode etc. ('zero_a', 1), ) diff --git a/src/soc/simple/test/test_issuer_mmu_ifetch.py b/src/soc/simple/test/test_issuer_mmu_ifetch.py index a5031a53..81f1b323 100644 --- a/src/soc/simple/test/test_issuer_mmu_ifetch.py +++ b/src/soc/simple/test/test_issuer_mmu_ifetch.py @@ -59,9 +59,10 @@ class MMUTestCase(TestAccumulatorBase): initial_mem = {} # set virtual and non-privileged - initial_msr = 1 << MSR.PR # must set "problem" state - initial_msr |= 1 << MSR.DR # set "virtual" state for data + initial_msr = 0 << MSR.PR # must set "problem" state + #initial_msr |= 1 << MSR.DR # set "virtual" state for data initial_msr |= 1 << MSR.IR # set "virtual" state for instructions + initial_msr |= 1 << MSR.LE # set little-endian # set PRTBL to 0x1000000 initial_sprs = {720: 0x1000000} # PRTBL -- 2.30.2