From f59f584517059131de78dc66008a12f2f77efb75 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 15 Feb 2019 07:15:18 +0000 Subject: [PATCH] add summary update --- updates/015_2019feb15_summary.mdwn | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/updates/015_2019feb15_summary.mdwn b/updates/015_2019feb15_summary.mdwn index 6f85730..e6d9dfb 100644 --- a/updates/015_2019feb15_summary.mdwn +++ b/updates/015_2019feb15_summary.mdwn @@ -35,6 +35,15 @@ and denormalisation, as well as the packing and unpacking stages: they're all absolutely identical. Consequently we can abstract these stages out into base classes. +Also, an aside: many thanks to attie from #m-labs on Freenode: it turns +out that converting verilog to migen as a way to learn is something that +other people do as well. It's a nice coincidence that attie +converted the +[milkymist FPU](https://github.com/m-labs/milkymist/blob/master/cores/pfpu/rtl/pfpu_faddsub.v) over to +[migen](https://github.com/nakengelhardt/fpgagraphlib/blob/master/src/faddsub.py) +as a way to avoid having to learn both migen as well as IEEE754. +We'll be comparing notes :) + # Virtual Memory / TLB A [TLB](https://en.wikipedia.org/wiki/Translation_lookaside_buffer) -- 2.30.2