From f5a95fadeaed107910057c3bc08185d919c97638 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Wed, 17 May 2023 16:45:21 +0100
Subject: [PATCH]

---
 openpower/sv/cr_ops.mdwn | 1 -
 1 file changed, 1 deletion(-)

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 84390476e..bcd5a3be1 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -93,7 +93,6 @@ Fields:
   a CR bit and whether it is set (inv=0) or unset (inv=1)
 * **RG** Reverse-Gear: inverts the Vector Loop order (VL-1 downto 0) rather
   than the normal 0 upto VL-1
-* **SVM** sets "subvector" reduce mode
 * **VLi** VL inclusive: in fail-first mode, the truncation of
   VL *includes* the current element at the failure point rather
   than excludes it from the count.
-- 
2.30.2