From f5c5f7625552ba76d38184e19187a4badfc52dbc Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 1 Dec 2016 13:55:03 -0500 Subject: [PATCH] freedreno: update generated headers Signed-off-by: Rob Clark --- src/gallium/drivers/freedreno/a2xx/a2xx.xml.h | 10 ++- src/gallium/drivers/freedreno/a3xx/a3xx.xml.h | 20 ++++- src/gallium/drivers/freedreno/a4xx/a4xx.xml.h | 22 ++++- src/gallium/drivers/freedreno/a5xx/a5xx.xml.h | 83 +++++++++++++++++-- src/gallium/drivers/freedreno/a5xx/fd5_emit.c | 2 +- .../drivers/freedreno/adreno_common.xml.h | 5 +- .../drivers/freedreno/adreno_pm4.xml.h | 7 +- 7 files changed, 129 insertions(+), 20 deletions(-) diff --git a/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h b/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h index a1208b0185f..afb37515a6a 100644 --- a/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h +++ b/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h @@ -12,10 +12,10 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-12-05 13:03:25) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90537 bytes, from 2016-11-29 17:10:44) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 92389 bytes, from 2016-12-06 22:06:14) - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) Copyright (C) 2013-2016 by the following authors: @@ -445,12 +445,14 @@ static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; } #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; } @@ -621,6 +623,7 @@ static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) { + assert(!(val & 0x3ff)); return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; } @@ -635,6 +638,7 @@ static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_form #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) { + assert(!(val & 0x3ff)); return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; } @@ -1432,6 +1436,7 @@ static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; } @@ -1539,6 +1544,7 @@ static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; } diff --git a/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h b/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h index b3add879fc9..2306996686d 100644 --- a/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h +++ b/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h @@ -12,10 +12,10 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-12-05 13:03:25) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90537 bytes, from 2016-11-29 17:10:44) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 92389 bytes, from 2016-12-06 22:06:14) - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) Copyright (C) 2013-2016 by the following authors: @@ -1164,6 +1164,7 @@ static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val) #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4 static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK; } #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000 @@ -1262,6 +1263,7 @@ static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; } @@ -1270,6 +1272,7 @@ static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; } @@ -1402,6 +1405,7 @@ static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) { + assert(!(val & 0x3fff)); return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK; } @@ -1410,6 +1414,7 @@ static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4 static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK; } @@ -1418,6 +1423,7 @@ static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK; } @@ -1486,6 +1492,7 @@ static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_form #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) { + assert(!(val & 0xfff)); return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; } @@ -1494,6 +1501,7 @@ static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) #define A3XX_RB_DEPTH_PITCH__SHIFT 0 static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val) { + assert(!(val & 0x7)); return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK; } @@ -1557,6 +1565,7 @@ static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 11 static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) { + assert(!(val & 0xfff)); return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; } @@ -1565,6 +1574,7 @@ static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) #define A3XX_RB_STENCIL_PITCH__SHIFT 0 static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val) { + assert(!(val & 0x7)); return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK; } @@ -2482,6 +2492,7 @@ static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) #define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5 static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; } @@ -2620,6 +2631,7 @@ static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) #define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5 static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; } @@ -2800,12 +2812,14 @@ static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK; } #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; } @@ -3202,6 +3216,7 @@ static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) #define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val) { + assert(!(val & 0xfff)); return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK; } #define A3XX_TEX_CONST_3_DEPTH__MASK 0x0ffe0000 @@ -3214,6 +3229,7 @@ static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val) #define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT 28 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val) { + assert(!(val & 0xfff)); return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK; } diff --git a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h index 70c933877de..2f9f5876166 100644 --- a/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h +++ b/src/gallium/drivers/freedreno/a4xx/a4xx.xml.h @@ -12,10 +12,10 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-12-05 13:03:25) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90537 bytes, from 2016-11-29 17:10:44) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 92389 bytes, from 2016-12-06 22:06:14) - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) Copyright (C) 2013-2016 by the following authors: @@ -929,12 +929,14 @@ static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; } #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00 #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; } #define A4XX_RB_MODE_CONTROL_ENABLE_GMEM 0x00010000 @@ -1019,6 +1021,7 @@ static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) { + assert(!(val & 0xf)); return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; } @@ -1218,6 +1221,7 @@ static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2 static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val) { + assert(!(val & 0x3)); return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK; } @@ -1294,6 +1298,7 @@ static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) { + assert(!(val & 0x3fff)); return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK; } @@ -1302,6 +1307,7 @@ static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; } @@ -1310,6 +1316,7 @@ static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK; } @@ -1388,6 +1395,7 @@ static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format va #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) { + assert(!(val & 0xfff)); return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; } @@ -1396,6 +1404,7 @@ static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) #define A4XX_RB_DEPTH_PITCH__SHIFT 0 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; } @@ -1404,6 +1413,7 @@ static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) #define A4XX_RB_DEPTH_PITCH2__SHIFT 0 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; } @@ -1469,6 +1479,7 @@ static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12 static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) { + assert(!(val & 0xfff)); return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; } @@ -1477,6 +1488,7 @@ static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) #define A4XX_RB_STENCIL_PITCH__SHIFT 0 static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK; } @@ -2838,12 +2850,14 @@ static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK; } #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK; } @@ -3014,6 +3028,7 @@ static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x000022 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) { + assert(!(val & 0xf)); return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK; } @@ -4020,6 +4035,7 @@ static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) { + assert(!(val & 0xfff)); return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; } #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000 @@ -4034,12 +4050,14 @@ static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) { + assert(!(val & 0xfff)); return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK; } #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0 #define A4XX_TEX_CONST_4_BASE__SHIFT 5 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; } diff --git a/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h b/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h index 6b3b3e09a51..c351b62927e 100644 --- a/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h +++ b/src/gallium/drivers/freedreno/a5xx/a5xx.xml.h @@ -12,10 +12,10 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-12-05 13:03:25) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90537 bytes, from 2016-11-29 17:10:44) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 92389 bytes, from 2016-12-06 22:06:14) - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) Copyright (C) 2013-2016 by the following authors: @@ -49,6 +49,7 @@ enum a5xx_color_fmt { RB5_R4G4B4A4_UNORM = 8, RB5_R5G5B5A1_UNORM = 10, RB5_R5G6B5_UNORM = 14, + RB5_R8G8_UNORM = 15, RB5_R16_FLOAT = 23, RB5_R8G8B8A8_UNORM = 48, RB5_R8G8B8_UNORM = 49, @@ -1911,6 +1912,11 @@ static inline uint32_t A5XX_VSC_BIN_SIZE_Y(uint32_t val) #define REG_A5XX_GRAS_CNTL 0x0000e005 #define A5XX_GRAS_CNTL_VARYING 0x00000001 +#define A5XX_GRAS_CNTL_UNK3 0x00000008 +#define A5XX_GRAS_CNTL_XCOORD 0x00000040 +#define A5XX_GRAS_CNTL_YCOORD 0x00000080 +#define A5XX_GRAS_CNTL_ZCOORD 0x00000100 +#define A5XX_GRAS_CNTL_WCOORD 0x00000200 #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff @@ -2010,7 +2016,7 @@ static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val) #define REG_A5XX_UNKNOWN_E093 0x0000e093 #define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094 -#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_ALPHA_TEST_ENABLE 0x00000001 +#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001 #define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff @@ -2177,12 +2183,14 @@ static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) #define A5XX_RB_CNTL_WIDTH__SHIFT 0 static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK; } #define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00 #define A5XX_RB_CNTL_HEIGHT__SHIFT 9 static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK; } #define A5XX_RB_CNTL_BYPASS 0x00020000 @@ -2223,6 +2231,7 @@ static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val #define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144 #define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001 +#define A5XX_RB_RENDER_CONTROL0_UNK3 0x00000008 #define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040 #define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080 #define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100 @@ -2366,6 +2375,7 @@ static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + #define A5XX_RB_MRT_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val) { + assert(!(val & 0x3f)); return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK; } @@ -2374,6 +2384,7 @@ static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val) { + assert(!(val & 0x3f)); return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK; } @@ -2554,6 +2565,7 @@ static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_fo #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK; } @@ -2562,6 +2574,7 @@ static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; } @@ -2630,6 +2643,7 @@ static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v #define A5XX_RB_STENCIL_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val) { + assert(!(val & 0x3f)); return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK; } @@ -2638,6 +2652,7 @@ static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val) #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val) { + assert(!(val & 0x3f)); return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK; } @@ -2727,6 +2742,7 @@ static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val) #define A5XX_RB_BLIT_DST_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val) { + assert(!(val & 0x3f)); return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK; } @@ -2735,6 +2751,7 @@ static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val) #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) { + assert(!(val & 0x3f)); return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK; } @@ -2772,6 +2789,7 @@ static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val) { + assert(!(val & 0x3f)); return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK; } @@ -2780,6 +2798,7 @@ static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { re #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) { + assert(!(val & 0x3f)); return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK; } @@ -2792,6 +2811,7 @@ static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val) { + assert(!(val & 0x3f)); return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK; } @@ -2800,6 +2820,7 @@ static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val) #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val) { + assert(!(val & 0x3f)); return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK; } @@ -3497,7 +3518,13 @@ static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val) #define REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_4 0x0000e7dd -#define REG_A5XX_RB_2D_DST_FILL 0x00002101 +#define REG_A5XX_RB_2D_SRC_SOLID_DW0 0x00002101 + +#define REG_A5XX_RB_2D_SRC_SOLID_DW1 0x00002102 + +#define REG_A5XX_RB_2D_SRC_SOLID_DW2 0x00002103 + +#define REG_A5XX_RB_2D_SRC_SOLID_DW3 0x00002104 #define REG_A5XX_RB_2D_SRC_INFO 0x00002107 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff @@ -3517,6 +3544,22 @@ static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) #define REG_A5XX_RB_2D_SRC_HI 0x00002109 +#define REG_A5XX_RB_2D_SRC_SIZE 0x0000210a +#define A5XX_RB_2D_SRC_SIZE_PITCH__MASK 0x0000ffff +#define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT 0 +static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val) +{ + assert(!(val & 0x3f)); + return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK; +} +#define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK 0xffff0000 +#define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT 16 +static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val) +{ + assert(!(val & 0x3f)); + return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK; +} + #define REG_A5XX_RB_2D_DST_INFO 0x00002110 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 @@ -3531,14 +3574,30 @@ static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; } -#define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140 - -#define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141 - #define REG_A5XX_RB_2D_DST_LO 0x00002111 #define REG_A5XX_RB_2D_DST_HI 0x00002112 +#define REG_A5XX_RB_2D_DST_SIZE 0x00002113 +#define A5XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff +#define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT 0 +static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val) +{ + assert(!(val & 0x3f)); + return ((val >> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK; +} +#define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK 0xffff0000 +#define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT 16 +static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val) +{ + assert(!(val & 0x3f)); + return ((val >> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK; +} + +#define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140 + +#define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141 + #define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143 #define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144 @@ -3571,6 +3630,12 @@ static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK; } +#define REG_A5XX_UNKNOWN_2100 0x00002100 + +#define REG_A5XX_UNKNOWN_2180 0x00002180 + +#define REG_A5XX_UNKNOWN_2184 0x00002184 + #define REG_A5XX_TEX_SAMP_0 0x00000000 #define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 #define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 @@ -3727,6 +3792,7 @@ static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val) #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) { + assert(!(val & 0xfff)); return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK; } #define A5XX_TEX_CONST_3_FLAG 0x10000000 @@ -3736,6 +3802,7 @@ static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) #define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5 static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val) { + assert(!(val & 0x1f)); return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK; } diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c index ce8c89c7c43..57edb90dd81 100644 --- a/src/gallium/drivers/freedreno/a5xx/fd5_emit.c +++ b/src/gallium/drivers/freedreno/a5xx/fd5_emit.c @@ -298,7 +298,7 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring, OUT_RING(ring, COND(fragz, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z)); OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL, 1); - OUT_RING(ring, COND(fragz, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_ALPHA_TEST_ENABLE)); + OUT_RING(ring, COND(fragz, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z)); } if (dirty & FD_DIRTY_RASTERIZER) { diff --git a/src/gallium/drivers/freedreno/adreno_common.xml.h b/src/gallium/drivers/freedreno/adreno_common.xml.h index e1db0590b0c..c098c3944e3 100644 --- a/src/gallium/drivers/freedreno/adreno_common.xml.h +++ b/src/gallium/drivers/freedreno/adreno_common.xml.h @@ -12,10 +12,10 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-12-05 13:03:25) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90537 bytes, from 2016-11-29 17:10:44) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 92389 bytes, from 2016-12-06 22:06:14) - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) Copyright (C) 2013-2016 by the following authors: @@ -219,6 +219,7 @@ static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) { + assert(!(val & 0x3)); return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; } diff --git a/src/gallium/drivers/freedreno/adreno_pm4.xml.h b/src/gallium/drivers/freedreno/adreno_pm4.xml.h index 1413bdcc7e5..69d118f3243 100644 --- a/src/gallium/drivers/freedreno/adreno_pm4.xml.h +++ b/src/gallium/drivers/freedreno/adreno_pm4.xml.h @@ -12,10 +12,10 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-12-05 13:03:25) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90537 bytes, from 2016-11-29 17:10:44) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 92389 bytes, from 2016-12-06 22:06:14) - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) Copyright (C) 2013-2016 by the following authors: @@ -253,7 +253,7 @@ enum render_mode_cmd { enum cp_blit_cmd { BLIT_OP_FILL = 0, - BLIT_OP_BLIT = 1, + BLIT_OP_COPY = 1, }; #define REG_CP_LOAD_STATE_0 0x00000000 @@ -293,6 +293,7 @@ static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) { + assert(!(val & 0x3)); return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; } -- 2.30.2