From f5ca72938a16f7d4192c003d8205b1b810b8fb5a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 24 Jul 2020 14:06:48 +0100 Subject: [PATCH] add the div pipe kind plus prog.assembly to the assert debug output --- src/soc/fu/div/test/runner.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/fu/div/test/runner.py b/src/soc/fu/div/test/runner.py index a506c0a8..6ce4c7a9 100644 --- a/src/soc/fu/div/test/runner.py +++ b/src/soc/fu/div/test/runner.py @@ -188,8 +188,10 @@ class DivRunner(unittest.TestCase): # TODO: raise bugreport with whitequark # requesting a public API to access this "officially" # XXX print("time:", sim._state.timeline.now) + msg = "%s: %s" % (self.div_pipe_kind.name, core) + msg += " %s" % (repr(prog.assembly)) yield from self.check_alu_outputs(alu, pdecode2, - isa_sim, code) + isa_sim, msg) sim.add_sync_process(process) with sim.write_vcd(f"div_simulator_{self.div_pipe_kind.name}.vcd"): -- 2.30.2