From f5d07f008d0af77082c896b9b26b158be9c8096b Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 16 Oct 2023 22:22:50 -0700 Subject: [PATCH] powmod asm tests pass! --- src/openpower/test/bigint/powmod.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/openpower/test/bigint/powmod.py b/src/openpower/test/bigint/powmod.py index 56f48fff..7fc79468 100644 --- a/src/openpower/test/bigint/powmod.py +++ b/src/openpower/test/bigint/powmod.py @@ -1217,7 +1217,6 @@ class PowModCases(TestAccumulatorBase): base %= mod yield (base, exp, mod) - @skip_case("FIXME: divmod is too slow to test powmod") def case_powmod_256(self): for base, exp, mod in PowModCases.powmod_256_test_inputs(): expected = pow(base, exp, mod) @@ -1234,10 +1233,15 @@ class PowModCases(TestAccumulatorBase): for i in range(4): # write d in LE order to regs 32-35 initial_regs[32 + i] = (mod >> (64 * i)) % 2**64 - # only check regs up to r7 since that's where the output is. # don't check CR - e = ExpectedState(int_regs=initial_regs[:8], crregs=0) + e = ExpectedState(int_regs=initial_regs, crregs=0) + for i in range(128): + nonvolatile = 14 <= i <= 31 + if nonvolatile or i in (1, 2, 13): + continue + e.intregs[i] = None e.ca = None # ignored + e.sprs['SVSHAPE0'] = None for i in range(4): # write output in LE order to regs 4-7 e.intregs[4 + i] = (expected >> (64 * i)) % 2**64 -- 2.30.2