From f5dd2c182275a9de57e5186491012c402a6248e0 Mon Sep 17 00:00:00 2001 From: Samuel Iglesias Gonsalvez Date: Mon, 1 Jun 2015 09:45:51 +0200 Subject: [PATCH] i965/fs/nir: implement nir_intrinsic_get_buffer_size MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit v2: - Remove inst->regs_written assignment as the instruction only writes to one register. Signed-off-by: Samuel Iglesias Gonsalvez Reviewed-by: Kristian Høgsberg --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index e4ddadc79a8..97aef61657f 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -1734,6 +1734,30 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr break; } + case nir_intrinsic_get_buffer_size: { + nir_const_value *const_uniform_block = nir_src_as_const_value(instr->src[0]); + unsigned ubo_index = const_uniform_block ? const_uniform_block->u[0] : 0; + int reg_width = dispatch_width / 8; + + assert(shader->base.UniformBlocks[ubo_index].IsShaderStorage); + + /* Set LOD = 0 */ + fs_reg source = fs_reg(0); + + int mlen = 1 * reg_width; + fs_reg src_payload = fs_reg(GRF, alloc.allocate(mlen), + BRW_REGISTER_TYPE_UD); + bld.LOAD_PAYLOAD(src_payload, &source, 1, 0); + + fs_reg surf_index = fs_reg(prog_data->binding_table.ubo_start + ubo_index); + fs_inst *inst = bld.emit(FS_OPCODE_GET_BUFFER_SIZE, dest, + src_payload, surf_index); + inst->header_size = 0; + inst->mlen = mlen; + bld.emit(inst); + break; + } + default: unreachable("unknown intrinsic"); } -- 2.30.2