From f5ea783de1128c371f40da7bf3675428aad92109 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Mon, 1 Apr 2019 14:38:14 +0100 Subject: [PATCH] arch-arm: updateMiscReg not setting isHyp in aarch64 The isHyp flag should be set for a TLB::NormalTran when in EL2. This was happening in aarch32 only, where the CPSR mode is checked, while aarch64 was only using it for explicit EL2 translations, like for AT instructions. Change-Id: I54605811e9dde75b5cf8868190b0f4c2a8d46570 Signed-off-by: Giacomo Travaglini Reviewed-by: Nikos Nikoleris Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18394 Maintainer: Andreas Sandberg Tested-by: kokoro --- src/arch/arm/tlb.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index e54eb25d6..4b43a50a4 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -1308,7 +1308,8 @@ TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType) isPriv = aarch64EL != EL0; if (haveVirtualization) { vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48); - isHyp = tranType & HypMode; + isHyp = aarch64EL == EL2; + isHyp |= tranType & HypMode; isHyp &= (tranType & S1S2NsTran) == 0; isHyp &= (tranType & S1CTran) == 0; // Work out if we should skip the first stage of translation and go -- 2.30.2