From f5f9ed0a0d40680acb24d6a1c4fdb992e0277f67 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 12 Apr 2011 18:22:07 -0700 Subject: [PATCH] [xcc,sim] fixed RM field --- riscv/decode.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/riscv/decode.h b/riscv/decode.h index af6b57f..e6d0e8a 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -182,8 +182,10 @@ private: #define TARGET insn.jtype.target #define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS)) #define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS)) -#define RM ((insn.ftype.rm != 7) ? insn.ftype.rm : \ - ((fsr & FSR_RD) >> FSR_RD_SHIFT)) +#define RM ({ int rm = insn.ftype.rm; \ + if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \ + if(rm > 4) throw trap_illegal_instruction; \ + rm; }) #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction #define xpr64 (xprlen == 64) -- 2.30.2