From f60da4a5dcb00366f45e8423ab42d4bfa38051eb Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 9 May 2018 14:39:31 +0200 Subject: [PATCH] add VexRiscv submodule --- .gitmodules | 3 +++ litex/soc/cores/cpu/vexriscv/verilog | 1 + 2 files changed, 4 insertions(+) create mode 160000 litex/soc/cores/cpu/vexriscv/verilog diff --git a/.gitmodules b/.gitmodules index 69988365..26af8537 100644 --- a/.gitmodules +++ b/.gitmodules @@ -13,3 +13,6 @@ [submodule "litex/build/sim/core/modules/ethernet/tapcfg"] path = litex/build/sim/core/modules/ethernet/tapcfg url = https://github.com/nizox/tapcfg +[submodule "litex/soc/cores/cpu/vexriscv/verilog"] + path = litex/soc/cores/cpu/vexriscv/verilog + url = https://github.com/m-labs/VexRiscv-verilog.git diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog new file mode 160000 index 00000000..4811a121 --- /dev/null +++ b/litex/soc/cores/cpu/vexriscv/verilog @@ -0,0 +1 @@ +Subproject commit 4811a12127eef5dfaaa8df47a59e58a1e561b0eb -- 2.30.2