From f61ab17724bb60a6c5b4c3ca1bd69532b97d6d74 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 6 Dec 2020 16:50:20 +0000
Subject: [PATCH]

---
 openpower/sv/svp_rewrite/svp64/discussion.mdwn | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 openpower/sv/svp_rewrite/svp64/discussion.mdwn

diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
new file mode 100644
index 000000000..23c8cdb76
--- /dev/null
+++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
@@ -0,0 +1,12 @@
+# Notes on requirements for bit allocations
+
+* 2: SUBVL
+* 2: elwidth
+* 2: twin-predication (src, dest) elwidth
+* 1: select INT or CR predication
+* 3: predicate selection and inversion (QTY 2 for tpred)
+* 4x2 or 3x3: src1/2/3/dest Vector/Scalar reg
+
+totals: 22 bits leaving 2 spare for further modes.
+
+http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001434.html
-- 
2.30.2