From f6203e6bd65f7383f14a15e926fc4b8f5f9a3edf Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 29 Sep 2019 21:55:53 -0700 Subject: [PATCH] Missing endmodule --- techlibs/xilinx/abc_model.v | 1 + 1 file changed, 1 insertion(+) diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index b302e46f6..8255804c2 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -35,6 +35,7 @@ endmodule (* abc_box_id = 1000 *) module \$__ABC_ASYNC (input A, S, output Y); +endmodule // Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} // Necessary since RAMD* and SRL* have both combinatorial (i.e. -- 2.30.2