From f621254830d10825377bb7b1b567a40a36706993 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 8 Sep 2021 01:26:15 +0100 Subject: [PATCH] --- openpower/sv/cr_ops.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn index 7e86257e4..601a9bb28 100644 --- a/openpower/sv/cr_ops.mdwn +++ b/openpower/sv/cr_ops.mdwn @@ -9,7 +9,8 @@ has no meaning. Consequently an alternative Mode Format is required. This alternative mapping **only** applies to instructions that **only** reference a CR Field or CR bit as the sole exclusive result. This section **does not** apply to instructions which primarily produce arithmetic -results that also produce a CR Field (such as when Rc=1). +results that also, as an aside, produce a corresponding +CR Field (such as when Rc=1). Instructions that involve Rc=1 are definitively arithmetic in nature, where the corresponding Condition Register Field can be considered to be a "co-result". Thus, if the arithmetic result is Vectorised, so -- 2.30.2