From f623c4fd17aa6d6d94f5038e319d1d5d4f5cd7ef Mon Sep 17 00:00:00 2001 From: Timothy Hayes Date: Fri, 10 Jan 2020 17:55:24 +0000 Subject: [PATCH] cpu: Add HTM CPU API JIRA: https://gem5.atlassian.net/browse/GEM5-587 Change-Id: Iff95eb97603b4cb9629c04382a824b02594ee5c7 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30322 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- src/cpu/o3/cpu.cc | 10 +++++++++- src/cpu/o3/cpu.hh | 7 ++++++- src/cpu/simple/atomic.hh | 14 +++++++++++++- src/cpu/simple/base.hh | 15 +++++++++++++++ src/cpu/simple/timing.cc | 13 +++++++++++++ src/cpu/simple/timing.hh | 7 ++++++- 6 files changed, 62 insertions(+), 4 deletions(-) diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 562a3324b..613ffd19d 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019 ARM Limited + * Copyright (c) 2011-2012, 2014, 2016, 2017, 2019-2020 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -1827,5 +1827,13 @@ FullO3CPU::exitThreads() } } +template +void +FullO3CPU::htmSendAbortSignal(ThreadID tid, uint64_t htmUid, + HtmFailureFaultCause cause) +{ + panic("not yet supported!"); +} + // Forward declaration of FullO3CPU. template class FullO3CPU; diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index cc0e2cd06..137fbc89b 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2013, 2016-2019 ARM Limited + * Copyright (c) 2011-2013, 2016-2020 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -788,6 +788,11 @@ class FullO3CPU : public BaseO3CPU //number of misc Stats::Scalar miscRegfileReads; Stats::Scalar miscRegfileWrites; + + public: + // hardware transactional memory + void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, + HtmFailureFaultCause cause); }; #endif // __CPU_O3_CPU_HH__ diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index 7333e1ff4..2d0a46564 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2013, 2015, 2018 ARM Limited + * Copyright (c) 2012-2013, 2015, 2018, 2020 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -219,6 +219,18 @@ class AtomicSimpleCPU : public BaseSimpleCPU const std::vector& byte_enable = std::vector()) override; + Fault initiateHtmCmd(Request::Flags flags) override + { + panic("initiateHtmCmd() is for timing accesses, and should " + "never be called on AtomicSimpleCPU.\n"); + } + + void htmSendAbortSignal(HtmFailureFaultCause cause) override + { + panic("htmSendAbortSignal() is for timing accesses, and should " + "never be called on AtomicSimpleCPU.\n"); + } + Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, const std::vector& byte_enable = std::vector()) diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 9f5bf662b..82f52d9cc 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -176,6 +176,21 @@ class BaseSimpleCPU : public BaseCPU void serializeThread(CheckpointOut &cp, ThreadID tid) const override; void unserializeThread(CheckpointIn &cp, ThreadID tid) override; + /** Hardware transactional memory commands (HtmCmds), e.g. start a + * transaction and commit a transaction, are memory operations but are + * neither really (true) loads nor stores. For this reason the interface + * is extended and initiateHtmCmd() is used to instigate the command. */ + virtual Fault initiateHtmCmd(Request::Flags flags) = 0; + + /** This function is used to instruct the memory subsystem that a + * transaction should be aborted and the speculative state should be + * thrown away. This is called in the transaction's very last breath in + * the core. Afterwards, the core throws away its speculative state and + * resumes execution at the point the transaction started, i.e. reverses + * time. When instruction execution resumes, the core expects the + * memory subsystem to be in a stable, i.e. pre-speculative, state as + * well. */ + virtual void htmSendAbortSignal(HtmFailureFaultCause cause) = 0; }; #endif // __CPU_SIMPLE_BASE_HH__ diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 84d7d0eb7..d3adbcc52 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -1055,6 +1055,19 @@ TimingSimpleCPU::printAddr(Addr a) dcachePort.printAddr(a); } +Fault +TimingSimpleCPU::initiateHtmCmd(Request::Flags flags) +{ + panic("not yet supported!"); + return NoFault; +} + +void +TimingSimpleCPU::htmSendAbortSignal(HtmFailureFaultCause cause) +{ + panic("not yet supported!"); +} + //////////////////////////////////////////////////////////////////////// // diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index 2bb0fe643..c055896a0 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2013,2015,2018 ARM Limited + * Copyright (c) 2012-2013,2015,2018,2020 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -320,6 +320,11 @@ class TimingSimpleCPU : public BaseSimpleCPU */ void finishTranslation(WholeTranslationState *state); + /** hardware transactional memory **/ + Fault initiateHtmCmd(Request::Flags flags) override; + + void htmSendAbortSignal(HtmFailureFaultCause) override; + private: EventFunctionWrapper fetchEvent; -- 2.30.2