From f62f88274ae31065eaa331ad4c6c4adc0870df5d Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 18 Aug 2014 23:14:34 +0200 Subject: [PATCH] radeonsi: bump PRIMGROUP_SIZE for some cases MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Recommended by hw people. Reviewed-by: Alex Deucher Reviewed-by: Michel Dänzer --- src/gallium/drivers/radeonsi/si_state_draw.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index f5d65508340..0f700a8c9eb 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -384,13 +384,16 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx, { struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; unsigned prim = info->mode; - unsigned primgroup_size = 64; + unsigned primgroup_size = 128; /* recommended without a GS */ /* SWITCH_ON_EOP(0) is always preferable. */ bool wd_switch_on_eop = false; bool ia_switch_on_eop = false; bool partial_vs_wave = false; + if (sctx->gs_shader) + primgroup_size = 64; /* recommended with a GS */ + /* This is a hardware requirement. */ if ((rs && rs->line_stipple_enable) || (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) { -- 2.30.2