From f669afbfa3a75d04c992d93180b589e45de8dc21 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 5 Sep 2021 17:53:13 +0100 Subject: [PATCH] --- openpower/sv/ldst.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index 3a251bf3e..12115f6c5 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -259,7 +259,7 @@ The source override applies to RB, and before adding to RA in order to calculate the Effective Address, if SEA is set RB is sign-extended from elwidth bits to the full 64 bits. For other Modes (ffirst, saturate), -all EA computation is unsigned. +all EA computation with elwidth overrides is unsigned. Note that cache-inhibited LD/ST (`ldcix`) when VSPLAT is activated will perform **multiple** LD/ST operations, sequentially. `ldcix` even with scalar src will read the same memory location *multiple times*, storing the result in successive Vector destination registers. This because the cache-inhibit instructions are used to read and write memory-mapped peripherals. If a genuine cache-inhibited LD-VSPLAT is required then a *scalar* -- 2.30.2