From f67202e2a5bcda15cc0c41ddbb89a3d4204fdd98 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 13 Mar 2021 12:22:16 +0000
Subject: [PATCH] add setvl unit test

---
 src/soc/decoder/isa/test_caller_setvl.py | 51 ++++++++++++++++++++++++
 1 file changed, 51 insertions(+)
 create mode 100644 src/soc/decoder/isa/test_caller_setvl.py

diff --git a/src/soc/decoder/isa/test_caller_setvl.py b/src/soc/decoder/isa/test_caller_setvl.py
new file mode 100644
index 00000000..6833a925
--- /dev/null
+++ b/src/soc/decoder/isa/test_caller_setvl.py
@@ -0,0 +1,51 @@
+from nmigen import Module, Signal
+from nmigen.back.pysim import Simulator, Delay, Settle
+from nmutil.formaltest import FHDLTestCase
+import unittest
+from soc.decoder.isa.caller import ISACaller
+from soc.decoder.power_decoder import (create_pdecode)
+from soc.decoder.power_decoder2 import (PowerDecode2)
+from soc.simulator.program import Program
+from soc.decoder.isa.caller import ISACaller, SVP64State
+from soc.decoder.selectable_int import SelectableInt
+from soc.decoder.orderedset import OrderedSet
+from soc.decoder.isa.all import ISA
+from soc.decoder.isa.test_caller import Register, run_tst
+from soc.sv.trans.svp64 import SVP64Asm
+from soc.consts import SVP64CROffs
+from copy import deepcopy
+
+class DecoderTestCase(FHDLTestCase):
+
+    def _check_regs(self, sim, expected):
+        for i in range(32):
+            self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
+
+    def test_setvl_1(self):
+        lst = SVP64Asm(["setvl 1, 1, 3, 1, 1",
+                        ])
+        lst = list(lst)
+
+        # SVSTATE (in this case, VL=2)
+        svstate = SVP64State()
+        svstate.vl[0:7] = 2 # VL
+        svstate.maxvl[0:7] = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.spr.asint()))
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, svstate=svstate)
+            print(sim.gpr(1))
+            self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64))
+            self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
+
+    def run_tst_program(self, prog, initial_regs=None,
+                              svstate=None):
+        if initial_regs is None:
+            initial_regs = [0] * 32
+        simulator = run_tst(prog, initial_regs, svstate=svstate)
+        simulator.gpr.dump()
+        return simulator
+
+
+if __name__ == "__main__":
+    unittest.main()
-- 
2.30.2