From f68218dc5fb44608295d218ceb4c1f6081af9eb3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 20 Apr 2018 15:09:41 +0100 Subject: [PATCH] add implementation paradigms section --- simple_v_extension.mdwn | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index a448b487d..15ac732ae 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -1515,6 +1515,21 @@ Am still thinking through the implications as any dependent operations (particularly ones already decoded and moved into the execution FIFO) would still be there (and stalled). hmmm. +## Implementation Paradigms + +TODO: assess various implementation paradigms: + +* Single-issue In-order, reduced pipeline depth (traditional SIMD / DSP) +* In-order 5+ stage pipelines with instruction FIFOs and mild register-renaming +* Out-of-order with instruction FIFOs and aggressive register-renaming +* VLIW + +Also to be taken into consideration: + +* "Virtual" vectorisation: single-issue loop, no internal ALU parallelism +* Comphrensive vectorisation: FIFOs and internal parallelism +* Hybrid Parallelism + # References * SIMD considered harmful -- 2.30.2