From f698917d45cc12703603b85fb9bb3ea378984269 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Tue, 4 Dec 2018 20:41:52 +0100 Subject: [PATCH] re PR target/88188 (ICE in print_operand, at config/rs6000/rs6000.c) PR target/88188 * config/rs6000/rs6000.c (ccr_bit): Return -1 instead of assertion failures. (print_operand): Use REG_P instead of GET_CODE == REG. : Also check CR_REGNO_P (REGNO (x)). : Likewise. Remove GET_MODE check. * config/rs6000/rs6000.md (scc patterns): Assert ccr_bit didn't return -1. * gcc.target/powerpc/pr88188-2.c: New test. From-SVN: r266794 --- gcc/ChangeLog | 11 +++++++ gcc/config/rs6000/rs6000.c | 33 +++++++++++++------- gcc/config/rs6000/rs6000.md | 2 ++ gcc/testsuite/ChangeLog | 5 +++ gcc/testsuite/gcc.target/powerpc/pr88188-2.c | 8 +++++ 5 files changed, 48 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr88188-2.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0ab1186cd40..add8fbae1fc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2018-12-04 Jakub Jelinek + + PR target/88188 + * config/rs6000/rs6000.c (ccr_bit): Return -1 instead of assertion + failures. + (print_operand): Use REG_P instead of GET_CODE == REG. + : Also check CR_REGNO_P (REGNO (x)). + : Likewise. Remove GET_MODE check. + * config/rs6000/rs6000.md (scc patterns): Assert ccr_bit didn't + return -1. + 2018-12-04 Martin Sebor * doc/extend.texi (attribute aligned): Expand. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 4e35a05bb38..4f12558b0a8 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -20626,7 +20626,8 @@ ccr_bit (rtx op, int scc_p) reg = XEXP (op, 0); - gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg))); + if (!REG_P (reg) || !CR_REGNO_P (REGNO (reg))) + return -1; cc_mode = GET_MODE (reg); cc_regnum = REGNO (reg); @@ -20636,9 +20637,19 @@ ccr_bit (rtx op, int scc_p) /* When generating a sCOND operation, only positive conditions are allowed. */ - gcc_assert (!scc_p - || code == EQ || code == GT || code == LT || code == UNORDERED - || code == GTU || code == LTU); + if (scc_p) + switch (code) + { + case EQ: + case GT: + case LT: + case UNORDERED: + case GTU: + case LTU: + break; + default: + return -1; + } switch (code) { @@ -20663,7 +20674,7 @@ ccr_bit (rtx op, int scc_p) return scc_p ? base_bit + 3 : base_bit + 1; default: - gcc_unreachable (); + return -1; } } @@ -20756,7 +20767,7 @@ print_operand (FILE *file, rtx x, int code) case 'D': /* Like 'J' but get to the GT bit only. */ - if (!REG_P (x)) + if (!REG_P (x) || !CR_REGNO_P (REGNO (x))) { output_operand_lossage ("invalid %%D value"); return; @@ -20784,7 +20795,7 @@ print_operand (FILE *file, rtx x, int code) case 'E': /* X is a CR register. Print the number of the EQ bit of the CR */ - if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) + if (!REG_P (x) || !CR_REGNO_P (REGNO (x))) output_operand_lossage ("invalid %%E value"); else fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2); @@ -20793,7 +20804,7 @@ print_operand (FILE *file, rtx x, int code) case 'f': /* X is a CR register. Print the shift count needed to move it to the high-order four bits. */ - if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) + if (!REG_P (x) || !CR_REGNO_P (REGNO (x))) output_operand_lossage ("invalid %%f value"); else fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO)); @@ -20802,7 +20813,7 @@ print_operand (FILE *file, rtx x, int code) case 'F': /* Similar, but print the count for the rotate in the opposite direction. */ - if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) + if (!REG_P (x) || !CR_REGNO_P (REGNO (x))) output_operand_lossage ("invalid %%F value"); else fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO)); @@ -21000,7 +21011,7 @@ print_operand (FILE *file, rtx x, int code) case 'R': /* X is a CR register. Print the mask for `mtcrf'. */ - if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x))) + if (!REG_P (x) || !CR_REGNO_P (REGNO (x))) output_operand_lossage ("invalid %%R value"); else fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO)); @@ -21016,7 +21027,7 @@ print_operand (FILE *file, rtx x, int code) case 't': /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */ - if (!REG_P (x) || GET_MODE (x) != CCmode) + if (!REG_P (x) || !CR_REGNO_P (REGNO (x))) { output_operand_lossage ("invalid %%t value"); return; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 797d5c32e64..18987cd7207 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -11676,6 +11676,7 @@ int put_bit = 31 - (INTVAL (operands[3]) & 31); int count; + gcc_assert (is_bit != -1); if (is_bit >= put_bit) count = is_bit - put_bit; else @@ -11710,6 +11711,7 @@ int put_bit = 31 - (INTVAL (operands[3]) & 31); int count; + gcc_assert (is_bit != -1); /* Force split for non-cc0 compare. */ if (which_alternative == 1) return "#"; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 887705e2503..6daa60cf8a2 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-12-04 Jakub Jelinek + + PR target/88188 + * gcc.target/powerpc/pr88188-2.c: New test. + 2018-12-04 Marek Polacek PR c++/88184 - ICE when treating name as template-name. diff --git a/gcc/testsuite/gcc.target/powerpc/pr88188-2.c b/gcc/testsuite/gcc.target/powerpc/pr88188-2.c new file mode 100644 index 00000000000..8c3267b9562 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr88188-2.c @@ -0,0 +1,8 @@ +/* PR target/88188 */ +/* { dg-do compile } */ + +void +foo (void) +{ + __asm volatile ("%D0" : : "r" (0)); /* { dg-error "invalid %D value" } */ +} -- 2.30.2