From f6a0046fdd390a11e9e6ad728bc8b5b1a6b4c836 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 9 Jun 2022 11:07:03 +0100 Subject: [PATCH] --- openpower/sv/svp64_quirks.mdwn | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index 423cb47b3..299d624f2 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -85,10 +85,15 @@ Reduction and Saturation are common to see in Vector ISAs: it is just that they are usually added as explicit instructions, and NEC SX Aurora has even more iterative instructions. In SVP64 these concepts are applied in the abstract general form, which takes some -getting used to, as it may, when applied to non-commutative +getting used to. + +Reduction may, when applied to non-commutative instructions incorrectly, result in invalid results, but ultimately it is critical to think in terms of the "rules", that everything is -Scalar instructions in strict Program Order. +Scalar instructions in strict Program Order. Reduction on non-commutative +Scalar Operations is not *prohibited*: the strict Program Order allows +the programmer to think through what would happen and thus potentially +actually come up with legitimate use. **Branches** -- 2.30.2