From f6b9a2a0c58a6f8b29f801fd1631c7eee5138c3a Mon Sep 17 00:00:00 2001 From: Wilco Dijkstra Date: Mon, 14 Nov 2016 12:07:03 +0000 Subject: [PATCH] The second patch updates the Cortex-A57 scheduler now that we can differentiate between shifts and bitfield inserts. The second patch updates the Cortex-A57 scheduler now that we can differentiate between shifts and bitfield inserts. The Cortex-A57 Software Optimization Guide indicates that BFM operations use the integer multi-cycle pipeline, while ARM UXTB/H instructions use the Integer 1 or Integer 0 pipelines, so swap the bfm and extend reservations. This results in minor scheduling differences. * config/arm/cortex-a57.md (cortex_a57_alu): Move extend here, bfm... (cortex_a57_alu_shift): ...here. From-SVN: r242385 --- gcc/ChangeLog | 5 +++++ gcc/config/arm/cortex-a57.md | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 07173ab54e8..e1306dc51d2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2016-11-14 Wilco Dijkstra + + * config/arm/cortex-a57.md (cortex_a57_alu): Move extend here, bfm... + (cortex_a57_alu_shift): ...here. + 2016-11-14 Wilco Dijkstra * config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_3) diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md index da461846baa..63072509e50 100644 --- a/gcc/config/arm/cortex-a57.md +++ b/gcc/config/arm/cortex-a57.md @@ -297,7 +297,7 @@ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ - adr,bfm,bfx,clz,rbit,rev,alu_dsp_reg,\ + adr,bfx,extend,clz,rbit,rev,alu_dsp_reg,\ rotate_imm,shift_imm,shift_reg,\ mov_imm,mov_reg,\ mvn_imm,mvn_reg,\ @@ -307,7 +307,7 @@ ;; ALU ops with immediate shift (define_insn_reservation "cortex_a57_alu_shift" 3 (and (eq_attr "tune" "cortexa57") - (eq_attr "type" "extend,\ + (eq_attr "type" "bfm,\ alu_shift_imm,alus_shift_imm,\ crc,logic_shift_imm,logics_shift_imm,\ mov_shift,mvn_shift")) -- 2.30.2