From f6c354c55bcba26978c8dd04c3cc4f02231aebe4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 8 Apr 2019 16:22:07 -0700 Subject: [PATCH] Update CHANGELOG --- CHANGELOG | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CHANGELOG b/CHANGELOG index 95bbb3f33..36b64e111 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -16,7 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass - - Added "shregmap -tech xilinx", used by "synth_xilinx" + - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" Yosys 0.7 .. Yosys 0.8 -- 2.30.2