From f6d8bddb5a3f17f0043c9e86224fec26bd76df85 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 22 Mar 2021 17:15:00 +0000 Subject: [PATCH] add very small DFF srams variant --- experiments9/non_generated/full_core_ls180.il | 114017 +++++++-------- 1 file changed, 54642 insertions(+), 59375 deletions(-) diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il index 56e2e69..310e3c5 100644 --- a/experiments9/non_generated/full_core_ls180.il +++ b/experiments9/non_generated/full_core_ls180.il @@ -1,5 +1,5 @@ # Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) -autoidx 15098 +autoidx 15046 attribute \src "libresoc.v:5.1-335.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" @@ -217507,921 +217507,921 @@ module \int connect \memory_r_addr$2 \src2__addr connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:137575.1-140282.10" +attribute \src "libresoc.v:137575.1-140281.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag" attribute \generator "nMigen" module \jtag - attribute \src "libresoc.v:139714.3-139740.6" + attribute \src "libresoc.v:139713.3-139739.6" wire $0\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:139362.3-139377.6" + attribute \src "libresoc.v:139361.3-139376.6" wire $0\TAP_tdo[0:0] - attribute \src "libresoc.v:139875.3-139907.6" + attribute \src "libresoc.v:139874.3-139906.6" wire width 4 $0\dmi0__addr_i$next[3:0]$6091 - attribute \src "libresoc.v:139265.3-139266.41" + attribute \src "libresoc.v:139264.3-139265.41" wire width 4 $0\dmi0__addr_i[3:0] - attribute \src "libresoc.v:139961.3-139987.6" + attribute \src "libresoc.v:139960.3-139986.6" wire width 64 $0\dmi0__din$next[63:0]$6104 - attribute \src "libresoc.v:139261.3-139262.35" + attribute \src "libresoc.v:139260.3-139261.35" wire width 64 $0\dmi0__din[63:0] - attribute \src "libresoc.v:139564.3-139580.6" + attribute \src "libresoc.v:139563.3-139579.6" wire $0\dmi0_addrsr__oe$next[0:0]$6028 - attribute \src "libresoc.v:139293.3-139294.47" + attribute \src "libresoc.v:139292.3-139293.47" wire $0\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:139581.3-139601.6" + attribute \src "libresoc.v:139580.3-139600.6" wire width 8 $0\dmi0_addrsr_reg$next[7:0]$6032 - attribute \src "libresoc.v:139291.3-139292.47" + attribute \src "libresoc.v:139290.3-139291.47" wire width 8 $0\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:139546.3-139554.6" + attribute \src "libresoc.v:139545.3-139553.6" wire $0\dmi0_addrsr_update_core$next[0:0]$6022 - attribute \src "libresoc.v:139297.3-139298.63" + attribute \src "libresoc.v:139296.3-139297.63" wire $0\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:139555.3-139563.6" + attribute \src "libresoc.v:139554.3-139562.6" wire $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 - attribute \src "libresoc.v:139295.3-139296.73" + attribute \src "libresoc.v:139294.3-139295.73" wire $0\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:139988.3-140008.6" + attribute \src "libresoc.v:139987.3-140007.6" wire width 64 $0\dmi0_datasr__i$next[63:0]$6109 - attribute \src "libresoc.v:139259.3-139260.45" + attribute \src "libresoc.v:139258.3-139259.45" wire width 64 $0\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:139620.3-139636.6" + attribute \src "libresoc.v:139619.3-139635.6" wire width 2 $0\dmi0_datasr__oe$next[1:0]$6043 - attribute \src "libresoc.v:139285.3-139286.47" + attribute \src "libresoc.v:139284.3-139285.47" wire width 2 $0\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:139637.3-139657.6" + attribute \src "libresoc.v:139636.3-139656.6" wire width 64 $0\dmi0_datasr_reg$next[63:0]$6047 - attribute \src "libresoc.v:139283.3-139284.47" + attribute \src "libresoc.v:139282.3-139283.47" wire width 64 $0\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:139602.3-139610.6" + attribute \src "libresoc.v:139601.3-139609.6" wire $0\dmi0_datasr_update_core$next[0:0]$6037 - attribute \src "libresoc.v:139289.3-139290.63" + attribute \src "libresoc.v:139288.3-139289.63" wire $0\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:139611.3-139619.6" + attribute \src "libresoc.v:139610.3-139618.6" wire $0\dmi0_datasr_update_core_prev$next[0:0]$6040 - attribute \src "libresoc.v:139287.3-139288.73" + attribute \src "libresoc.v:139286.3-139287.73" wire $0\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:139908.3-139960.6" + attribute \src "libresoc.v:139907.3-139959.6" wire width 3 $0\fsm_state$499$next[2:0]$6097 - attribute \src "libresoc.v:139263.3-139264.45" + attribute \src "libresoc.v:139262.3-139263.45" wire width 3 $0\fsm_state$499[2:0]$5943 attribute \src "libresoc.v:138217.13-138217.35" wire width 3 $0\fsm_state$499[2:0]$6146 - attribute \src "libresoc.v:139774.3-139826.6" + attribute \src "libresoc.v:139773.3-139825.6" wire width 3 $0\fsm_state$next[2:0]$6074 - attribute \src "libresoc.v:139271.3-139272.35" + attribute \src "libresoc.v:139270.3-139271.35" wire width 3 $0\fsm_state[2:0] attribute \src "libresoc.v:137576.7-137576.20" wire $0\initial[0:0] - attribute \src "libresoc.v:140058.3-140078.6" + attribute \src "libresoc.v:140057.3-140077.6" wire width 152 $0\io_bd$next[151:0]$6129 - attribute \src "libresoc.v:139323.3-139324.27" + attribute \src "libresoc.v:139322.3-139323.27" wire width 152 $0\io_bd[151:0] - attribute \src "libresoc.v:140040.3-140057.6" + attribute \src "libresoc.v:140039.3-140056.6" wire width 152 $0\io_sr$next[151:0]$6125 - attribute \src "libresoc.v:139325.3-139326.27" + attribute \src "libresoc.v:139324.3-139325.27" wire width 152 $0\io_sr[151:0] - attribute \src "libresoc.v:139741.3-139773.6" + attribute \src "libresoc.v:139740.3-139772.6" wire width 29 $0\jtag_wb__adr$next[28:0]$6068 - attribute \src "libresoc.v:139273.3-139274.41" + attribute \src "libresoc.v:139272.3-139273.41" wire width 29 $0\jtag_wb__adr[28:0] - attribute \src "libresoc.v:139827.3-139853.6" + attribute \src "libresoc.v:139826.3-139852.6" wire width 64 $0\jtag_wb__dat_w$next[63:0]$6081 - attribute \src "libresoc.v:139269.3-139270.45" + attribute \src "libresoc.v:139268.3-139269.45" wire width 64 $0\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:139452.3-139468.6" + attribute \src "libresoc.v:139451.3-139467.6" wire $0\jtag_wb_addrsr__oe$next[0:0]$5998 - attribute \src "libresoc.v:139309.3-139310.53" + attribute \src "libresoc.v:139308.3-139309.53" wire $0\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:139469.3-139489.6" + attribute \src "libresoc.v:139468.3-139488.6" wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$6002 - attribute \src "libresoc.v:139307.3-139308.53" + attribute \src "libresoc.v:139306.3-139307.53" wire width 29 $0\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:139434.3-139442.6" + attribute \src "libresoc.v:139433.3-139441.6" wire $0\jtag_wb_addrsr_update_core$next[0:0]$5992 - attribute \src "libresoc.v:139313.3-139314.69" + attribute \src "libresoc.v:139312.3-139313.69" wire $0\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:139443.3-139451.6" + attribute \src "libresoc.v:139442.3-139450.6" wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 - attribute \src "libresoc.v:139311.3-139312.79" + attribute \src "libresoc.v:139310.3-139311.79" wire $0\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:139854.3-139874.6" + attribute \src "libresoc.v:139853.3-139873.6" wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6086 - attribute \src "libresoc.v:139267.3-139268.51" + attribute \src "libresoc.v:139266.3-139267.51" wire width 64 $0\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:139508.3-139524.6" + attribute \src "libresoc.v:139507.3-139523.6" wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$6013 - attribute \src "libresoc.v:139301.3-139302.53" + attribute \src "libresoc.v:139300.3-139301.53" wire width 2 $0\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:139525.3-139545.6" + attribute \src "libresoc.v:139524.3-139544.6" wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$6017 - attribute \src "libresoc.v:139299.3-139300.53" + attribute \src "libresoc.v:139298.3-139299.53" wire width 64 $0\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:139490.3-139498.6" + attribute \src "libresoc.v:139489.3-139497.6" wire $0\jtag_wb_datasr_update_core$next[0:0]$6007 - attribute \src "libresoc.v:139305.3-139306.69" + attribute \src "libresoc.v:139304.3-139305.69" wire $0\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:139499.3-139507.6" + attribute \src "libresoc.v:139498.3-139506.6" wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 - attribute \src "libresoc.v:139303.3-139304.79" + attribute \src "libresoc.v:139302.3-139303.79" wire $0\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:139396.3-139412.6" + attribute \src "libresoc.v:139395.3-139411.6" wire $0\sr0__oe$next[0:0]$5983 - attribute \src "libresoc.v:139317.3-139318.31" + attribute \src "libresoc.v:139316.3-139317.31" wire $0\sr0__oe[0:0] - attribute \src "libresoc.v:139413.3-139433.6" + attribute \src "libresoc.v:139412.3-139432.6" wire width 3 $0\sr0_reg$next[2:0]$5987 - attribute \src "libresoc.v:139315.3-139316.31" + attribute \src "libresoc.v:139314.3-139315.31" wire width 3 $0\sr0_reg[2:0] - attribute \src "libresoc.v:139378.3-139386.6" + attribute \src "libresoc.v:139377.3-139385.6" wire $0\sr0_update_core$next[0:0]$5977 - attribute \src "libresoc.v:139321.3-139322.47" + attribute \src "libresoc.v:139320.3-139321.47" wire $0\sr0_update_core[0:0] - attribute \src "libresoc.v:139387.3-139395.6" + attribute \src "libresoc.v:139386.3-139394.6" wire $0\sr0_update_core_prev$next[0:0]$5980 - attribute \src "libresoc.v:139319.3-139320.57" + attribute \src "libresoc.v:139318.3-139319.57" wire $0\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:140030.3-140039.6" + attribute \src "libresoc.v:140029.3-140038.6" wire width 3 $0\sr5__i[2:0] - attribute \src "libresoc.v:139676.3-139692.6" + attribute \src "libresoc.v:139675.3-139691.6" wire $0\sr5__oe$next[0:0]$6058 - attribute \src "libresoc.v:139277.3-139278.31" + attribute \src "libresoc.v:139276.3-139277.31" wire $0\sr5__oe[0:0] - attribute \src "libresoc.v:139693.3-139713.6" + attribute \src "libresoc.v:139692.3-139712.6" wire width 3 $0\sr5_reg$next[2:0]$6062 - attribute \src "libresoc.v:139275.3-139276.31" + attribute \src "libresoc.v:139274.3-139275.31" wire width 3 $0\sr5_reg[2:0] - attribute \src "libresoc.v:139658.3-139666.6" + attribute \src "libresoc.v:139657.3-139665.6" wire $0\sr5_update_core$next[0:0]$6052 - attribute \src "libresoc.v:139281.3-139282.47" + attribute \src "libresoc.v:139280.3-139281.47" wire $0\sr5_update_core[0:0] - attribute \src "libresoc.v:139667.3-139675.6" + attribute \src "libresoc.v:139666.3-139674.6" wire $0\sr5_update_core_prev$next[0:0]$6055 - attribute \src "libresoc.v:139279.3-139280.57" + attribute \src "libresoc.v:139278.3-139279.57" wire $0\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:140009.3-140029.6" + attribute \src "libresoc.v:140008.3-140028.6" wire $0\wb_dcache_en$next[0:0]$6114 - attribute \src "libresoc.v:139255.3-139256.41" + attribute \src "libresoc.v:139254.3-139255.41" wire $0\wb_dcache_en[0:0] - attribute \src "libresoc.v:140009.3-140029.6" + attribute \src "libresoc.v:140008.3-140028.6" wire $0\wb_icache_en$next[0:0]$6115 - attribute \src "libresoc.v:139253.3-139254.41" + attribute \src "libresoc.v:139252.3-139253.41" wire $0\wb_icache_en[0:0] - attribute \src "libresoc.v:140009.3-140029.6" + attribute \src "libresoc.v:140008.3-140028.6" wire $0\wb_sram_en$next[0:0]$6116 - attribute \src "libresoc.v:139257.3-139258.37" + attribute \src "libresoc.v:139256.3-139257.37" wire $0\wb_sram_en[0:0] - attribute \src "libresoc.v:139714.3-139740.6" + attribute \src "libresoc.v:139713.3-139739.6" wire $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:139362.3-139377.6" + attribute \src "libresoc.v:139361.3-139376.6" wire $1\TAP_tdo[0:0] - attribute \src "libresoc.v:139875.3-139907.6" + attribute \src "libresoc.v:139874.3-139906.6" wire width 4 $1\dmi0__addr_i$next[3:0]$6092 attribute \src "libresoc.v:138130.13-138130.32" wire width 4 $1\dmi0__addr_i[3:0] - attribute \src "libresoc.v:139961.3-139987.6" + attribute \src "libresoc.v:139960.3-139986.6" wire width 64 $1\dmi0__din$next[63:0]$6105 attribute \src "libresoc.v:138135.14-138135.46" wire width 64 $1\dmi0__din[63:0] - attribute \src "libresoc.v:139564.3-139580.6" + attribute \src "libresoc.v:139563.3-139579.6" wire $1\dmi0_addrsr__oe$next[0:0]$6029 attribute \src "libresoc.v:138149.7-138149.29" wire $1\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:139581.3-139601.6" + attribute \src "libresoc.v:139580.3-139600.6" wire width 8 $1\dmi0_addrsr_reg$next[7:0]$6033 attribute \src "libresoc.v:138157.13-138157.36" wire width 8 $1\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:139546.3-139554.6" + attribute \src "libresoc.v:139545.3-139553.6" wire $1\dmi0_addrsr_update_core$next[0:0]$6023 attribute \src "libresoc.v:138165.7-138165.37" wire $1\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:139555.3-139563.6" + attribute \src "libresoc.v:139554.3-139562.6" wire $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 attribute \src "libresoc.v:138169.7-138169.42" wire $1\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:139988.3-140008.6" + attribute \src "libresoc.v:139987.3-140007.6" wire width 64 $1\dmi0_datasr__i$next[63:0]$6110 attribute \src "libresoc.v:138173.14-138173.51" wire width 64 $1\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:139620.3-139636.6" + attribute \src "libresoc.v:139619.3-139635.6" wire width 2 $1\dmi0_datasr__oe$next[1:0]$6044 attribute \src "libresoc.v:138179.13-138179.35" wire width 2 $1\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:139637.3-139657.6" + attribute \src "libresoc.v:139636.3-139656.6" wire width 64 $1\dmi0_datasr_reg$next[63:0]$6048 attribute \src "libresoc.v:138187.14-138187.52" wire width 64 $1\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:139602.3-139610.6" + attribute \src "libresoc.v:139601.3-139609.6" wire $1\dmi0_datasr_update_core$next[0:0]$6038 attribute \src "libresoc.v:138195.7-138195.37" wire $1\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:139611.3-139619.6" + attribute \src "libresoc.v:139610.3-139618.6" wire $1\dmi0_datasr_update_core_prev$next[0:0]$6041 attribute \src "libresoc.v:138199.7-138199.42" wire $1\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:139908.3-139960.6" + attribute \src "libresoc.v:139907.3-139959.6" wire width 3 $1\fsm_state$499$next[2:0]$6098 - attribute \src "libresoc.v:139774.3-139826.6" + attribute \src "libresoc.v:139773.3-139825.6" wire width 3 $1\fsm_state$next[2:0]$6075 attribute \src "libresoc.v:138215.13-138215.29" wire width 3 $1\fsm_state[2:0] - attribute \src "libresoc.v:140058.3-140078.6" + attribute \src "libresoc.v:140057.3-140077.6" wire width 152 $1\io_bd$next[151:0]$6130 attribute \src "libresoc.v:138415.15-138415.66" wire width 152 $1\io_bd[151:0] - attribute \src "libresoc.v:140040.3-140057.6" + attribute \src "libresoc.v:140039.3-140056.6" wire width 152 $1\io_sr$next[151:0]$6126 attribute \src "libresoc.v:138427.15-138427.66" wire width 152 $1\io_sr[151:0] - attribute \src "libresoc.v:139741.3-139773.6" + attribute \src "libresoc.v:139740.3-139772.6" wire width 29 $1\jtag_wb__adr$next[28:0]$6069 attribute \src "libresoc.v:138436.14-138436.41" wire width 29 $1\jtag_wb__adr[28:0] - attribute \src "libresoc.v:139827.3-139853.6" + attribute \src "libresoc.v:139826.3-139852.6" wire width 64 $1\jtag_wb__dat_w$next[63:0]$6082 attribute \src "libresoc.v:138445.14-138445.51" wire width 64 $1\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:139452.3-139468.6" + attribute \src "libresoc.v:139451.3-139467.6" wire $1\jtag_wb_addrsr__oe$next[0:0]$5999 attribute \src "libresoc.v:138459.7-138459.32" wire $1\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:139469.3-139489.6" + attribute \src "libresoc.v:139468.3-139488.6" wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$6003 attribute \src "libresoc.v:138467.14-138467.47" wire width 29 $1\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:139434.3-139442.6" + attribute \src "libresoc.v:139433.3-139441.6" wire $1\jtag_wb_addrsr_update_core$next[0:0]$5993 attribute \src "libresoc.v:138475.7-138475.40" wire $1\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:139443.3-139451.6" + attribute \src "libresoc.v:139442.3-139450.6" wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 attribute \src "libresoc.v:138479.7-138479.45" wire $1\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:139854.3-139874.6" + attribute \src "libresoc.v:139853.3-139873.6" wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6087 attribute \src "libresoc.v:138483.14-138483.54" wire width 64 $1\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:139508.3-139524.6" + attribute \src "libresoc.v:139507.3-139523.6" wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$6014 attribute \src "libresoc.v:138489.13-138489.38" wire width 2 $1\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:139525.3-139545.6" + attribute \src "libresoc.v:139524.3-139544.6" wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$6018 attribute \src "libresoc.v:138497.14-138497.55" wire width 64 $1\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:139490.3-139498.6" + attribute \src "libresoc.v:139489.3-139497.6" wire $1\jtag_wb_datasr_update_core$next[0:0]$6008 attribute \src "libresoc.v:138505.7-138505.40" wire $1\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:139499.3-139507.6" + attribute \src "libresoc.v:139498.3-139506.6" wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 attribute \src "libresoc.v:138509.7-138509.45" wire $1\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:139396.3-139412.6" + attribute \src "libresoc.v:139395.3-139411.6" wire $1\sr0__oe$next[0:0]$5984 attribute \src "libresoc.v:138931.7-138931.21" wire $1\sr0__oe[0:0] - attribute \src "libresoc.v:139413.3-139433.6" + attribute \src "libresoc.v:139412.3-139432.6" wire width 3 $1\sr0_reg$next[2:0]$5988 attribute \src "libresoc.v:138939.13-138939.27" wire width 3 $1\sr0_reg[2:0] - attribute \src "libresoc.v:139378.3-139386.6" + attribute \src "libresoc.v:139377.3-139385.6" wire $1\sr0_update_core$next[0:0]$5978 attribute \src "libresoc.v:138947.7-138947.29" wire $1\sr0_update_core[0:0] - attribute \src "libresoc.v:139387.3-139395.6" + attribute \src "libresoc.v:139386.3-139394.6" wire $1\sr0_update_core_prev$next[0:0]$5981 attribute \src "libresoc.v:138951.7-138951.34" wire $1\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:140030.3-140039.6" + attribute \src "libresoc.v:140029.3-140038.6" wire width 3 $1\sr5__i[2:0] - attribute \src "libresoc.v:139676.3-139692.6" + attribute \src "libresoc.v:139675.3-139691.6" wire $1\sr5__oe$next[0:0]$6059 attribute \src "libresoc.v:138961.7-138961.21" wire $1\sr5__oe[0:0] - attribute \src "libresoc.v:139693.3-139713.6" + attribute \src "libresoc.v:139692.3-139712.6" wire width 3 $1\sr5_reg$next[2:0]$6063 attribute \src "libresoc.v:138969.13-138969.27" wire width 3 $1\sr5_reg[2:0] - attribute \src "libresoc.v:139658.3-139666.6" + attribute \src "libresoc.v:139657.3-139665.6" wire $1\sr5_update_core$next[0:0]$6053 attribute \src "libresoc.v:138977.7-138977.29" wire $1\sr5_update_core[0:0] - attribute \src "libresoc.v:139667.3-139675.6" + attribute \src "libresoc.v:139666.3-139674.6" wire $1\sr5_update_core_prev$next[0:0]$6056 attribute \src "libresoc.v:138981.7-138981.34" wire $1\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:140009.3-140029.6" + attribute \src "libresoc.v:140008.3-140028.6" wire $1\wb_dcache_en$next[0:0]$6117 attribute \src "libresoc.v:138986.7-138986.26" wire $1\wb_dcache_en[0:0] - attribute \src "libresoc.v:140009.3-140029.6" + attribute \src "libresoc.v:140008.3-140028.6" wire $1\wb_icache_en$next[0:0]$6118 attribute \src "libresoc.v:138991.7-138991.26" wire $1\wb_icache_en[0:0] - attribute \src "libresoc.v:140009.3-140029.6" + attribute \src "libresoc.v:140008.3-140028.6" wire $1\wb_sram_en$next[0:0]$6119 - attribute \src "libresoc.v:138996.7-138996.24" + attribute \src "libresoc.v:138995.7-138995.24" wire $1\wb_sram_en[0:0] - attribute \src "libresoc.v:139875.3-139907.6" + attribute \src "libresoc.v:139874.3-139906.6" wire width 4 $2\dmi0__addr_i$next[3:0]$6093 - attribute \src "libresoc.v:139961.3-139987.6" + attribute \src "libresoc.v:139960.3-139986.6" wire width 64 $2\dmi0__din$next[63:0]$6106 - attribute \src "libresoc.v:139564.3-139580.6" + attribute \src "libresoc.v:139563.3-139579.6" wire $2\dmi0_addrsr__oe$next[0:0]$6030 - attribute \src "libresoc.v:139581.3-139601.6" + attribute \src "libresoc.v:139580.3-139600.6" wire width 8 $2\dmi0_addrsr_reg$next[7:0]$6034 - attribute \src "libresoc.v:139988.3-140008.6" + attribute \src "libresoc.v:139987.3-140007.6" wire width 64 $2\dmi0_datasr__i$next[63:0]$6111 - attribute \src "libresoc.v:139620.3-139636.6" + attribute \src "libresoc.v:139619.3-139635.6" wire width 2 $2\dmi0_datasr__oe$next[1:0]$6045 - attribute \src "libresoc.v:139637.3-139657.6" + attribute \src "libresoc.v:139636.3-139656.6" wire width 64 $2\dmi0_datasr_reg$next[63:0]$6049 - attribute \src "libresoc.v:139908.3-139960.6" + attribute \src "libresoc.v:139907.3-139959.6" wire width 3 $2\fsm_state$499$next[2:0]$6099 - attribute \src "libresoc.v:139774.3-139826.6" + attribute \src "libresoc.v:139773.3-139825.6" wire width 3 $2\fsm_state$next[2:0]$6076 - attribute \src "libresoc.v:140058.3-140078.6" + attribute \src "libresoc.v:140057.3-140077.6" wire width 152 $2\io_bd$next[151:0]$6131 - attribute \src "libresoc.v:140040.3-140057.6" + attribute \src "libresoc.v:140039.3-140056.6" wire width 152 $2\io_sr$next[151:0]$6127 - attribute \src "libresoc.v:139741.3-139773.6" + attribute \src "libresoc.v:139740.3-139772.6" wire width 29 $2\jtag_wb__adr$next[28:0]$6070 - attribute \src "libresoc.v:139827.3-139853.6" + attribute \src "libresoc.v:139826.3-139852.6" wire width 64 $2\jtag_wb__dat_w$next[63:0]$6083 - attribute \src "libresoc.v:139452.3-139468.6" + attribute \src "libresoc.v:139451.3-139467.6" wire $2\jtag_wb_addrsr__oe$next[0:0]$6000 - attribute \src "libresoc.v:139469.3-139489.6" + attribute \src "libresoc.v:139468.3-139488.6" wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$6004 - attribute \src "libresoc.v:139854.3-139874.6" + attribute \src "libresoc.v:139853.3-139873.6" wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6088 - attribute \src "libresoc.v:139508.3-139524.6" + attribute \src "libresoc.v:139507.3-139523.6" wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$6015 - attribute \src "libresoc.v:139525.3-139545.6" + attribute \src "libresoc.v:139524.3-139544.6" wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$6019 - attribute \src "libresoc.v:139396.3-139412.6" + attribute \src "libresoc.v:139395.3-139411.6" wire $2\sr0__oe$next[0:0]$5985 - attribute \src "libresoc.v:139413.3-139433.6" + attribute \src "libresoc.v:139412.3-139432.6" wire width 3 $2\sr0_reg$next[2:0]$5989 - attribute \src "libresoc.v:139676.3-139692.6" + attribute \src "libresoc.v:139675.3-139691.6" wire $2\sr5__oe$next[0:0]$6060 - attribute \src "libresoc.v:139693.3-139713.6" + attribute \src "libresoc.v:139692.3-139712.6" wire width 3 $2\sr5_reg$next[2:0]$6064 - attribute \src "libresoc.v:140009.3-140029.6" + attribute \src "libresoc.v:140008.3-140028.6" wire $2\wb_dcache_en$next[0:0]$6120 - attribute \src "libresoc.v:140009.3-140029.6" + attribute \src "libresoc.v:140008.3-140028.6" wire $2\wb_icache_en$next[0:0]$6121 - attribute \src "libresoc.v:140009.3-140029.6" + attribute \src "libresoc.v:140008.3-140028.6" wire $2\wb_sram_en$next[0:0]$6122 - attribute \src "libresoc.v:139875.3-139907.6" + attribute \src "libresoc.v:139874.3-139906.6" wire width 4 $3\dmi0__addr_i$next[3:0]$6094 - attribute \src "libresoc.v:139961.3-139987.6" + attribute \src "libresoc.v:139960.3-139986.6" wire width 64 $3\dmi0__din$next[63:0]$6107 - attribute \src "libresoc.v:139581.3-139601.6" + attribute \src "libresoc.v:139580.3-139600.6" wire width 8 $3\dmi0_addrsr_reg$next[7:0]$6035 - attribute \src "libresoc.v:139988.3-140008.6" + attribute \src "libresoc.v:139987.3-140007.6" wire width 64 $3\dmi0_datasr__i$next[63:0]$6112 - attribute \src "libresoc.v:139637.3-139657.6" + attribute \src "libresoc.v:139636.3-139656.6" wire width 64 $3\dmi0_datasr_reg$next[63:0]$6050 - attribute \src "libresoc.v:139908.3-139960.6" + attribute \src "libresoc.v:139907.3-139959.6" wire width 3 $3\fsm_state$499$next[2:0]$6100 - attribute \src "libresoc.v:139774.3-139826.6" + attribute \src "libresoc.v:139773.3-139825.6" wire width 3 $3\fsm_state$next[2:0]$6077 - attribute \src "libresoc.v:139741.3-139773.6" + attribute \src "libresoc.v:139740.3-139772.6" wire width 29 $3\jtag_wb__adr$next[28:0]$6071 - attribute \src "libresoc.v:139827.3-139853.6" + attribute \src "libresoc.v:139826.3-139852.6" wire width 64 $3\jtag_wb__dat_w$next[63:0]$6084 - attribute \src "libresoc.v:139469.3-139489.6" + attribute \src "libresoc.v:139468.3-139488.6" wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$6005 - attribute \src "libresoc.v:139854.3-139874.6" + attribute \src "libresoc.v:139853.3-139873.6" wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6089 - attribute \src "libresoc.v:139525.3-139545.6" + attribute \src "libresoc.v:139524.3-139544.6" wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$6020 - attribute \src "libresoc.v:139413.3-139433.6" + attribute \src "libresoc.v:139412.3-139432.6" wire width 3 $3\sr0_reg$next[2:0]$5990 - attribute \src "libresoc.v:139693.3-139713.6" + attribute \src "libresoc.v:139692.3-139712.6" wire width 3 $3\sr5_reg$next[2:0]$6065 - attribute \src "libresoc.v:139875.3-139907.6" + attribute \src "libresoc.v:139874.3-139906.6" wire width 4 $4\dmi0__addr_i$next[3:0]$6095 - attribute \src "libresoc.v:139908.3-139960.6" + attribute \src "libresoc.v:139907.3-139959.6" wire width 3 $4\fsm_state$499$next[2:0]$6101 - attribute \src "libresoc.v:139774.3-139826.6" + attribute \src "libresoc.v:139773.3-139825.6" wire width 3 $4\fsm_state$next[2:0]$6078 - attribute \src "libresoc.v:139741.3-139773.6" + attribute \src "libresoc.v:139740.3-139772.6" wire width 29 $4\jtag_wb__adr$next[28:0]$6072 - attribute \src "libresoc.v:139908.3-139960.6" + attribute \src "libresoc.v:139907.3-139959.6" wire width 3 $5\fsm_state$499$next[2:0]$6102 - attribute \src "libresoc.v:139774.3-139826.6" + attribute \src "libresoc.v:139773.3-139825.6" wire width 3 $5\fsm_state$next[2:0]$6079 + attribute \src "libresoc.v:139216.19-139216.112" + wire width 30 $add$libresoc.v:139216$5900_Y attribute \src "libresoc.v:139217.19-139217.112" - wire width 30 $add$libresoc.v:139217$5900_Y - attribute \src "libresoc.v:139218.19-139218.112" - wire width 30 $add$libresoc.v:139218$5901_Y + wire width 30 $add$libresoc.v:139217$5901_Y + attribute \src "libresoc.v:139224.19-139224.112" + wire width 5 $add$libresoc.v:139224$5909_Y attribute \src "libresoc.v:139225.19-139225.112" - wire width 5 $add$libresoc.v:139225$5909_Y - attribute \src "libresoc.v:139226.19-139226.112" - wire width 5 $add$libresoc.v:139226$5910_Y - attribute \src "libresoc.v:139043.18-139043.112" - wire $and$libresoc.v:139043$5726_Y - attribute \src "libresoc.v:139110.18-139110.108" - wire $and$libresoc.v:139110$5793_Y - attribute \src "libresoc.v:139121.18-139121.110" - wire $and$libresoc.v:139121$5804_Y - attribute \src "libresoc.v:139147.19-139147.110" - wire $and$libresoc.v:139147$5830_Y - attribute \src "libresoc.v:139150.19-139150.114" - wire $and$libresoc.v:139150$5833_Y - attribute \src "libresoc.v:139152.19-139152.112" - wire $and$libresoc.v:139152$5835_Y - attribute \src "libresoc.v:139155.19-139155.113" - wire $and$libresoc.v:139155$5838_Y - attribute \src "libresoc.v:139157.19-139157.121" - wire $and$libresoc.v:139157$5840_Y - attribute \src "libresoc.v:139160.19-139160.114" - wire $and$libresoc.v:139160$5843_Y - attribute \src "libresoc.v:139162.19-139162.112" - wire $and$libresoc.v:139162$5845_Y - attribute \src "libresoc.v:139164.19-139164.113" - wire $and$libresoc.v:139164$5847_Y - attribute \src "libresoc.v:139168.19-139168.132" - wire $and$libresoc.v:139168$5851_Y - attribute \src "libresoc.v:139172.19-139172.114" - wire $and$libresoc.v:139172$5855_Y - attribute \src "libresoc.v:139174.19-139174.112" - wire $and$libresoc.v:139174$5857_Y - attribute \src "libresoc.v:139176.19-139176.113" - wire $and$libresoc.v:139176$5859_Y - attribute \src "libresoc.v:139179.19-139179.132" - wire $and$libresoc.v:139179$5862_Y - attribute \src "libresoc.v:139182.19-139182.114" - wire $and$libresoc.v:139182$5865_Y - attribute \src "libresoc.v:139184.19-139184.112" - wire $and$libresoc.v:139184$5867_Y - attribute \src "libresoc.v:139186.19-139186.113" - wire $and$libresoc.v:139186$5869_Y - attribute \src "libresoc.v:139188.18-139188.108" - wire $and$libresoc.v:139188$5871_Y - attribute \src "libresoc.v:139189.19-139189.129" - wire $and$libresoc.v:139189$5872_Y - attribute \src "libresoc.v:139193.19-139193.114" - wire $and$libresoc.v:139193$5876_Y - attribute \src "libresoc.v:139195.19-139195.112" - wire $and$libresoc.v:139195$5878_Y - attribute \src "libresoc.v:139197.19-139197.113" - wire $and$libresoc.v:139197$5880_Y - attribute \src "libresoc.v:139199.18-139199.111" - wire $and$libresoc.v:139199$5882_Y - attribute \src "libresoc.v:139200.19-139200.129" - wire $and$libresoc.v:139200$5883_Y - attribute \src "libresoc.v:139203.19-139203.114" - wire $and$libresoc.v:139203$5886_Y - attribute \src "libresoc.v:139205.19-139205.112" - wire $and$libresoc.v:139205$5888_Y - attribute \src "libresoc.v:139207.19-139207.113" - wire $and$libresoc.v:139207$5890_Y - attribute \src "libresoc.v:139209.19-139209.121" - wire $and$libresoc.v:139209$5892_Y - attribute \src "libresoc.v:139242.17-139242.106" - wire $and$libresoc.v:139242$5926_Y - attribute \src "libresoc.v:138999.17-138999.110" - wire $eq$libresoc.v:138999$5682_Y - attribute \src "libresoc.v:139010.18-139010.111" - wire $eq$libresoc.v:139010$5693_Y - attribute \src "libresoc.v:139021.18-139021.111" - wire $eq$libresoc.v:139021$5704_Y - attribute \src "libresoc.v:139054.17-139054.110" - wire $eq$libresoc.v:139054$5737_Y - attribute \src "libresoc.v:139055.18-139055.111" - wire $eq$libresoc.v:139055$5738_Y - attribute \src "libresoc.v:139066.18-139066.111" - wire $eq$libresoc.v:139066$5749_Y - attribute \src "libresoc.v:139088.18-139088.111" - wire $eq$libresoc.v:139088$5771_Y - attribute \src "libresoc.v:139132.18-139132.111" - wire $eq$libresoc.v:139132$5815_Y + wire width 5 $add$libresoc.v:139225$5910_Y + attribute \src "libresoc.v:139042.18-139042.112" + wire $and$libresoc.v:139042$5726_Y + attribute \src "libresoc.v:139109.18-139109.108" + wire $and$libresoc.v:139109$5793_Y + attribute \src "libresoc.v:139120.18-139120.110" + wire $and$libresoc.v:139120$5804_Y + attribute \src "libresoc.v:139146.19-139146.110" + wire $and$libresoc.v:139146$5830_Y + attribute \src "libresoc.v:139149.19-139149.114" + wire $and$libresoc.v:139149$5833_Y + attribute \src "libresoc.v:139151.19-139151.112" + wire $and$libresoc.v:139151$5835_Y + attribute \src "libresoc.v:139154.19-139154.113" + wire $and$libresoc.v:139154$5838_Y + attribute \src "libresoc.v:139156.19-139156.121" + wire $and$libresoc.v:139156$5840_Y + attribute \src "libresoc.v:139159.19-139159.114" + wire $and$libresoc.v:139159$5843_Y + attribute \src "libresoc.v:139161.19-139161.112" + wire $and$libresoc.v:139161$5845_Y + attribute \src "libresoc.v:139163.19-139163.113" + wire $and$libresoc.v:139163$5847_Y + attribute \src "libresoc.v:139167.19-139167.132" + wire $and$libresoc.v:139167$5851_Y + attribute \src "libresoc.v:139171.19-139171.114" + wire $and$libresoc.v:139171$5855_Y + attribute \src "libresoc.v:139173.19-139173.112" + wire $and$libresoc.v:139173$5857_Y + attribute \src "libresoc.v:139175.19-139175.113" + wire $and$libresoc.v:139175$5859_Y + attribute \src "libresoc.v:139178.19-139178.132" + wire $and$libresoc.v:139178$5862_Y + attribute \src "libresoc.v:139181.19-139181.114" + wire $and$libresoc.v:139181$5865_Y + attribute \src "libresoc.v:139183.19-139183.112" + wire $and$libresoc.v:139183$5867_Y + attribute \src "libresoc.v:139185.19-139185.113" + wire $and$libresoc.v:139185$5869_Y + attribute \src "libresoc.v:139187.18-139187.108" + wire $and$libresoc.v:139187$5871_Y + attribute \src "libresoc.v:139188.19-139188.129" + wire $and$libresoc.v:139188$5872_Y + attribute \src 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\src "libresoc.v:139169.19-139169.112" - wire $eq$libresoc.v:139169$5852_Y - attribute \src "libresoc.v:139170.19-139170.112" - wire $eq$libresoc.v:139170$5853_Y - attribute \src "libresoc.v:139180.19-139180.112" - wire $eq$libresoc.v:139180$5863_Y + wire $eq$libresoc.v:139169$5853_Y + attribute \src "libresoc.v:139179.19-139179.112" + wire $eq$libresoc.v:139179$5863_Y + attribute \src "libresoc.v:139189.19-139189.112" + wire $eq$libresoc.v:139189$5873_Y attribute \src "libresoc.v:139190.19-139190.112" - wire $eq$libresoc.v:139190$5873_Y - attribute \src "libresoc.v:139191.19-139191.112" - wire $eq$libresoc.v:139191$5874_Y - attribute \src "libresoc.v:139201.19-139201.112" - wire $eq$libresoc.v:139201$5884_Y - attribute \src "libresoc.v:139210.18-139210.111" - wire $eq$libresoc.v:139210$5893_Y - attribute \src "libresoc.v:139211.19-139211.110" - wire $eq$libresoc.v:139211$5894_Y + wire $eq$libresoc.v:139190$5874_Y + attribute \src "libresoc.v:139200.19-139200.112" + wire $eq$libresoc.v:139200$5884_Y + attribute \src "libresoc.v:139209.18-139209.111" + wire $eq$libresoc.v:139209$5893_Y + attribute \src "libresoc.v:139210.19-139210.110" + wire $eq$libresoc.v:139210$5894_Y + attribute \src "libresoc.v:139212.19-139212.110" + wire $eq$libresoc.v:139212$5896_Y attribute \src "libresoc.v:139213.19-139213.110" - wire $eq$libresoc.v:139213$5896_Y - attribute \src "libresoc.v:139214.19-139214.110" - wire $eq$libresoc.v:139214$5897_Y - attribute \src "libresoc.v:139216.19-139216.110" - wire $eq$libresoc.v:139216$5899_Y - attribute \src "libresoc.v:139220.18-139220.111" - wire $eq$libresoc.v:139220$5904_Y + wire $eq$libresoc.v:139213$5897_Y + attribute \src "libresoc.v:139215.19-139215.110" + wire $eq$libresoc.v:139215$5899_Y + attribute \src "libresoc.v:139219.18-139219.111" + wire $eq$libresoc.v:139219$5904_Y + attribute \src "libresoc.v:139220.19-139220.116" + wire $eq$libresoc.v:139220$5905_Y attribute \src "libresoc.v:139221.19-139221.116" - wire $eq$libresoc.v:139221$5905_Y - attribute \src "libresoc.v:139222.19-139222.116" - wire $eq$libresoc.v:139222$5906_Y - attribute \src "libresoc.v:139224.19-139224.116" - wire $eq$libresoc.v:139224$5908_Y - attribute \src "libresoc.v:139219.19-139219.106" - wire width 8 $extend$libresoc.v:139219$5902_Y - attribute \src "libresoc.v:139149.19-139149.109" - wire $ne$libresoc.v:139149$5832_Y - attribute \src "libresoc.v:139151.19-139151.109" - wire $ne$libresoc.v:139151$5834_Y - attribute \src "libresoc.v:139153.19-139153.109" - wire $ne$libresoc.v:139153$5836_Y - attribute \src "libresoc.v:139159.19-139159.120" - wire $ne$libresoc.v:139159$5842_Y - attribute \src "libresoc.v:139161.19-139161.120" - wire $ne$libresoc.v:139161$5844_Y - attribute \src "libresoc.v:139163.19-139163.120" - wire $ne$libresoc.v:139163$5846_Y - attribute \src "libresoc.v:139171.19-139171.120" - wire $ne$libresoc.v:139171$5854_Y - attribute \src "libresoc.v:139173.19-139173.120" - wire $ne$libresoc.v:139173$5856_Y - attribute \src "libresoc.v:139175.19-139175.120" - wire $ne$libresoc.v:139175$5858_Y - attribute \src "libresoc.v:139181.19-139181.117" - wire $ne$libresoc.v:139181$5864_Y - attribute \src "libresoc.v:139183.19-139183.117" - wire $ne$libresoc.v:139183$5866_Y - attribute \src "libresoc.v:139185.19-139185.117" - wire $ne$libresoc.v:139185$5868_Y - attribute \src "libresoc.v:139192.19-139192.117" - wire $ne$libresoc.v:139192$5875_Y - attribute \src "libresoc.v:139194.19-139194.117" - wire $ne$libresoc.v:139194$5877_Y - attribute \src "libresoc.v:139196.19-139196.117" - wire $ne$libresoc.v:139196$5879_Y - attribute \src "libresoc.v:139202.19-139202.109" - wire $ne$libresoc.v:139202$5885_Y - attribute \src "libresoc.v:139204.19-139204.109" - wire $ne$libresoc.v:139204$5887_Y - attribute \src "libresoc.v:139206.19-139206.109" - wire $ne$libresoc.v:139206$5889_Y - attribute \src "libresoc.v:139156.19-139156.110" - wire $not$libresoc.v:139156$5839_Y - attribute \src "libresoc.v:139167.19-139167.121" - wire $not$libresoc.v:139167$5850_Y - attribute \src "libresoc.v:139178.19-139178.121" - wire $not$libresoc.v:139178$5861_Y - attribute \src "libresoc.v:139187.19-139187.118" - wire $not$libresoc.v:139187$5870_Y - attribute \src "libresoc.v:139198.19-139198.118" - wire $not$libresoc.v:139198$5881_Y - attribute \src "libresoc.v:139208.19-139208.110" - wire $not$libresoc.v:139208$5891_Y - attribute \src "libresoc.v:139212.19-139212.100" - wire $not$libresoc.v:139212$5895_Y - attribute \src "libresoc.v:139032.18-139032.104" - wire $or$libresoc.v:139032$5715_Y - attribute \src "libresoc.v:139077.18-139077.104" - wire $or$libresoc.v:139077$5760_Y - attribute \src "libresoc.v:139099.18-139099.104" - wire $or$libresoc.v:139099$5782_Y - attribute \src "libresoc.v:139144.19-139144.107" - wire $or$libresoc.v:139144$5827_Y - attribute \src "libresoc.v:139146.19-139146.107" - wire $or$libresoc.v:139146$5829_Y - attribute \src "libresoc.v:139154.18-139154.104" - wire $or$libresoc.v:139154$5837_Y - attribute \src "libresoc.v:139177.18-139177.104" - wire $or$libresoc.v:139177$5860_Y - attribute \src "libresoc.v:139215.19-139215.107" - wire $or$libresoc.v:139215$5898_Y - attribute \src "libresoc.v:139223.19-139223.107" - wire $or$libresoc.v:139223$5907_Y - attribute \src "libresoc.v:139231.17-139231.101" - wire $or$libresoc.v:139231$5915_Y - attribute \src "libresoc.v:139219.19-139219.106" - wire width 8 $pos$libresoc.v:139219$5903_Y - attribute \src "libresoc.v:139000.18-139000.133" - wire $ternary$libresoc.v:139000$5683_Y - attribute \src "libresoc.v:139001.19-139001.133" - wire $ternary$libresoc.v:139001$5684_Y - attribute \src "libresoc.v:139002.19-139002.134" - wire $ternary$libresoc.v:139002$5685_Y - attribute \src "libresoc.v:139003.19-139003.133" - wire $ternary$libresoc.v:139003$5686_Y - attribute \src "libresoc.v:139004.19-139004.132" - wire $ternary$libresoc.v:139004$5687_Y + wire $eq$libresoc.v:139221$5906_Y + attribute \src "libresoc.v:139223.19-139223.116" + wire $eq$libresoc.v:139223$5908_Y + attribute \src "libresoc.v:139218.19-139218.106" + wire width 8 $extend$libresoc.v:139218$5902_Y + attribute \src "libresoc.v:139148.19-139148.109" + wire $ne$libresoc.v:139148$5832_Y + attribute \src "libresoc.v:139150.19-139150.109" + wire $ne$libresoc.v:139150$5834_Y + attribute \src "libresoc.v:139152.19-139152.109" + wire $ne$libresoc.v:139152$5836_Y + attribute \src "libresoc.v:139158.19-139158.120" + wire $ne$libresoc.v:139158$5842_Y + attribute \src "libresoc.v:139160.19-139160.120" + wire $ne$libresoc.v:139160$5844_Y + attribute \src "libresoc.v:139162.19-139162.120" + wire $ne$libresoc.v:139162$5846_Y + attribute \src "libresoc.v:139170.19-139170.120" + wire $ne$libresoc.v:139170$5854_Y + attribute \src "libresoc.v:139172.19-139172.120" + wire $ne$libresoc.v:139172$5856_Y + attribute \src "libresoc.v:139174.19-139174.120" + wire $ne$libresoc.v:139174$5858_Y + attribute \src "libresoc.v:139180.19-139180.117" + wire $ne$libresoc.v:139180$5864_Y + attribute \src "libresoc.v:139182.19-139182.117" + wire $ne$libresoc.v:139182$5866_Y + attribute \src "libresoc.v:139184.19-139184.117" + wire $ne$libresoc.v:139184$5868_Y + attribute \src "libresoc.v:139191.19-139191.117" + wire $ne$libresoc.v:139191$5875_Y + attribute \src "libresoc.v:139193.19-139193.117" + wire $ne$libresoc.v:139193$5877_Y + attribute \src "libresoc.v:139195.19-139195.117" + wire $ne$libresoc.v:139195$5879_Y + attribute \src "libresoc.v:139201.19-139201.109" + wire $ne$libresoc.v:139201$5885_Y + attribute \src "libresoc.v:139203.19-139203.109" + wire $ne$libresoc.v:139203$5887_Y + attribute \src "libresoc.v:139205.19-139205.109" + wire $ne$libresoc.v:139205$5889_Y + attribute \src "libresoc.v:139155.19-139155.110" + wire $not$libresoc.v:139155$5839_Y + attribute \src "libresoc.v:139166.19-139166.121" + wire $not$libresoc.v:139166$5850_Y + attribute \src "libresoc.v:139177.19-139177.121" + wire $not$libresoc.v:139177$5861_Y + attribute \src "libresoc.v:139186.19-139186.118" + wire $not$libresoc.v:139186$5870_Y + attribute \src "libresoc.v:139197.19-139197.118" + wire $not$libresoc.v:139197$5881_Y + attribute \src "libresoc.v:139207.19-139207.110" + wire $not$libresoc.v:139207$5891_Y + attribute \src "libresoc.v:139211.19-139211.100" + wire $not$libresoc.v:139211$5895_Y + attribute \src "libresoc.v:139031.18-139031.104" + wire $or$libresoc.v:139031$5715_Y + attribute \src "libresoc.v:139076.18-139076.104" + wire $or$libresoc.v:139076$5760_Y + attribute \src "libresoc.v:139098.18-139098.104" + wire $or$libresoc.v:139098$5782_Y + attribute \src "libresoc.v:139143.19-139143.107" + wire $or$libresoc.v:139143$5827_Y + attribute \src "libresoc.v:139145.19-139145.107" + wire $or$libresoc.v:139145$5829_Y + attribute \src "libresoc.v:139153.18-139153.104" + wire $or$libresoc.v:139153$5837_Y + attribute \src "libresoc.v:139176.18-139176.104" + wire $or$libresoc.v:139176$5860_Y + attribute \src "libresoc.v:139214.19-139214.107" + wire $or$libresoc.v:139214$5898_Y + attribute \src "libresoc.v:139222.19-139222.107" + wire $or$libresoc.v:139222$5907_Y + attribute \src "libresoc.v:139230.17-139230.101" + wire $or$libresoc.v:139230$5915_Y + attribute \src "libresoc.v:139218.19-139218.106" + wire width 8 $pos$libresoc.v:139218$5903_Y + attribute \src "libresoc.v:138999.18-138999.133" + wire $ternary$libresoc.v:138999$5683_Y + attribute \src "libresoc.v:139000.19-139000.133" + wire $ternary$libresoc.v:139000$5684_Y + attribute \src "libresoc.v:139001.19-139001.134" + wire $ternary$libresoc.v:139001$5685_Y + attribute \src "libresoc.v:139002.19-139002.133" + wire $ternary$libresoc.v:139002$5686_Y + attribute \src "libresoc.v:139003.19-139003.132" + wire $ternary$libresoc.v:139003$5687_Y + attribute \src "libresoc.v:139004.19-139004.133" + wire $ternary$libresoc.v:139004$5688_Y attribute \src "libresoc.v:139005.19-139005.133" - wire $ternary$libresoc.v:139005$5688_Y - attribute \src "libresoc.v:139006.19-139006.133" - wire $ternary$libresoc.v:139006$5689_Y - attribute \src "libresoc.v:139007.19-139007.132" - wire $ternary$libresoc.v:139007$5690_Y + wire $ternary$libresoc.v:139005$5689_Y + attribute \src "libresoc.v:139006.19-139006.132" + wire $ternary$libresoc.v:139006$5690_Y + attribute \src "libresoc.v:139007.19-139007.133" + wire $ternary$libresoc.v:139007$5691_Y attribute \src "libresoc.v:139008.19-139008.133" - wire $ternary$libresoc.v:139008$5691_Y - attribute \src "libresoc.v:139009.19-139009.133" - wire $ternary$libresoc.v:139009$5692_Y - attribute \src "libresoc.v:139011.19-139011.132" - wire $ternary$libresoc.v:139011$5694_Y + wire $ternary$libresoc.v:139008$5692_Y + attribute \src "libresoc.v:139010.19-139010.132" + wire $ternary$libresoc.v:139010$5694_Y + attribute \src "libresoc.v:139011.19-139011.133" + wire $ternary$libresoc.v:139011$5695_Y attribute \src "libresoc.v:139012.19-139012.133" - wire $ternary$libresoc.v:139012$5695_Y - attribute \src "libresoc.v:139013.19-139013.133" - wire $ternary$libresoc.v:139013$5696_Y - attribute \src "libresoc.v:139014.19-139014.132" - wire $ternary$libresoc.v:139014$5697_Y + wire $ternary$libresoc.v:139012$5696_Y + attribute \src "libresoc.v:139013.19-139013.132" + wire $ternary$libresoc.v:139013$5697_Y + attribute \src "libresoc.v:139014.19-139014.133" + wire $ternary$libresoc.v:139014$5698_Y attribute \src "libresoc.v:139015.19-139015.133" - wire $ternary$libresoc.v:139015$5698_Y - attribute \src "libresoc.v:139016.19-139016.133" - wire $ternary$libresoc.v:139016$5699_Y - attribute \src "libresoc.v:139017.19-139017.132" - wire $ternary$libresoc.v:139017$5700_Y + wire $ternary$libresoc.v:139015$5699_Y + attribute \src "libresoc.v:139016.19-139016.132" + wire $ternary$libresoc.v:139016$5700_Y + attribute \src "libresoc.v:139017.19-139017.133" + wire $ternary$libresoc.v:139017$5701_Y attribute \src "libresoc.v:139018.19-139018.133" - wire $ternary$libresoc.v:139018$5701_Y - attribute \src "libresoc.v:139019.19-139019.133" - wire $ternary$libresoc.v:139019$5702_Y - attribute \src "libresoc.v:139020.19-139020.132" - wire $ternary$libresoc.v:139020$5703_Y + wire $ternary$libresoc.v:139018$5702_Y + attribute \src "libresoc.v:139019.19-139019.132" + wire $ternary$libresoc.v:139019$5703_Y + attribute \src "libresoc.v:139021.19-139021.133" + wire $ternary$libresoc.v:139021$5705_Y attribute \src "libresoc.v:139022.19-139022.133" - wire $ternary$libresoc.v:139022$5705_Y - attribute \src "libresoc.v:139023.19-139023.133" - wire $ternary$libresoc.v:139023$5706_Y - attribute \src "libresoc.v:139024.19-139024.132" - wire $ternary$libresoc.v:139024$5707_Y + wire $ternary$libresoc.v:139022$5706_Y + attribute \src "libresoc.v:139023.19-139023.132" + wire $ternary$libresoc.v:139023$5707_Y + attribute \src "libresoc.v:139024.19-139024.133" + wire $ternary$libresoc.v:139024$5708_Y attribute \src "libresoc.v:139025.19-139025.133" - wire $ternary$libresoc.v:139025$5708_Y - attribute \src "libresoc.v:139026.19-139026.133" - wire $ternary$libresoc.v:139026$5709_Y - attribute \src "libresoc.v:139027.19-139027.132" - wire $ternary$libresoc.v:139027$5710_Y - attribute \src "libresoc.v:139028.19-139028.133" - wire $ternary$libresoc.v:139028$5711_Y - attribute \src "libresoc.v:139029.19-139029.134" - wire $ternary$libresoc.v:139029$5712_Y + wire $ternary$libresoc.v:139025$5709_Y + attribute \src "libresoc.v:139026.19-139026.132" + wire $ternary$libresoc.v:139026$5710_Y + attribute \src "libresoc.v:139027.19-139027.133" + wire $ternary$libresoc.v:139027$5711_Y + attribute \src "libresoc.v:139028.19-139028.134" + wire $ternary$libresoc.v:139028$5712_Y + attribute \src "libresoc.v:139029.19-139029.135" + wire $ternary$libresoc.v:139029$5713_Y attribute \src "libresoc.v:139030.19-139030.135" - wire $ternary$libresoc.v:139030$5713_Y - attribute \src "libresoc.v:139031.19-139031.135" - wire $ternary$libresoc.v:139031$5714_Y - attribute \src "libresoc.v:139033.19-139033.136" - wire $ternary$libresoc.v:139033$5716_Y - attribute \src "libresoc.v:139034.19-139034.134" - wire $ternary$libresoc.v:139034$5717_Y + wire $ternary$libresoc.v:139030$5714_Y + attribute \src "libresoc.v:139032.19-139032.136" + wire $ternary$libresoc.v:139032$5716_Y + attribute \src "libresoc.v:139033.19-139033.134" + wire $ternary$libresoc.v:139033$5717_Y + attribute \src "libresoc.v:139034.19-139034.135" + wire $ternary$libresoc.v:139034$5718_Y attribute \src "libresoc.v:139035.19-139035.135" - wire $ternary$libresoc.v:139035$5718_Y - attribute \src "libresoc.v:139036.19-139036.135" - wire $ternary$libresoc.v:139036$5719_Y - attribute \src "libresoc.v:139037.19-139037.136" - wire $ternary$libresoc.v:139037$5720_Y - attribute \src "libresoc.v:139038.19-139038.134" - wire $ternary$libresoc.v:139038$5721_Y - attribute \src "libresoc.v:139039.19-139039.133" - wire $ternary$libresoc.v:139039$5722_Y - attribute \src "libresoc.v:139040.19-139040.134" - wire $ternary$libresoc.v:139040$5723_Y - attribute \src "libresoc.v:139041.19-139041.133" - wire $ternary$libresoc.v:139041$5724_Y - attribute \src "libresoc.v:139042.19-139042.130" - wire $ternary$libresoc.v:139042$5725_Y - attribute \src "libresoc.v:139044.19-139044.130" - wire $ternary$libresoc.v:139044$5727_Y - attribute \src "libresoc.v:139045.19-139045.133" - wire $ternary$libresoc.v:139045$5728_Y - attribute \src "libresoc.v:139046.19-139046.132" - wire $ternary$libresoc.v:139046$5729_Y - attribute \src "libresoc.v:139047.19-139047.133" - wire $ternary$libresoc.v:139047$5730_Y - attribute \src "libresoc.v:139048.19-139048.132" - wire $ternary$libresoc.v:139048$5731_Y - attribute \src "libresoc.v:139049.19-139049.135" - wire $ternary$libresoc.v:139049$5732_Y - attribute \src "libresoc.v:139050.19-139050.134" - wire $ternary$libresoc.v:139050$5733_Y + wire $ternary$libresoc.v:139035$5719_Y + attribute \src "libresoc.v:139036.19-139036.136" + wire $ternary$libresoc.v:139036$5720_Y + attribute \src "libresoc.v:139037.19-139037.134" + wire $ternary$libresoc.v:139037$5721_Y + attribute \src "libresoc.v:139038.19-139038.133" + wire $ternary$libresoc.v:139038$5722_Y + attribute \src "libresoc.v:139039.19-139039.134" + wire $ternary$libresoc.v:139039$5723_Y + attribute \src "libresoc.v:139040.19-139040.133" + wire $ternary$libresoc.v:139040$5724_Y + attribute \src "libresoc.v:139041.19-139041.130" + wire $ternary$libresoc.v:139041$5725_Y + attribute \src "libresoc.v:139043.19-139043.130" + wire $ternary$libresoc.v:139043$5727_Y + attribute \src "libresoc.v:139044.19-139044.133" + wire $ternary$libresoc.v:139044$5728_Y + attribute \src "libresoc.v:139045.19-139045.132" + wire $ternary$libresoc.v:139045$5729_Y + attribute \src "libresoc.v:139046.19-139046.133" + wire $ternary$libresoc.v:139046$5730_Y + attribute \src "libresoc.v:139047.19-139047.132" + wire $ternary$libresoc.v:139047$5731_Y + attribute \src "libresoc.v:139048.19-139048.135" + wire $ternary$libresoc.v:139048$5732_Y + attribute \src "libresoc.v:139049.19-139049.134" + wire $ternary$libresoc.v:139049$5733_Y + attribute \src "libresoc.v:139050.19-139050.135" + wire $ternary$libresoc.v:139050$5734_Y attribute \src "libresoc.v:139051.19-139051.135" - wire $ternary$libresoc.v:139051$5734_Y - attribute \src "libresoc.v:139052.19-139052.135" - wire $ternary$libresoc.v:139052$5735_Y - attribute \src "libresoc.v:139053.19-139053.134" - wire $ternary$libresoc.v:139053$5736_Y + wire $ternary$libresoc.v:139051$5735_Y + attribute \src "libresoc.v:139052.19-139052.134" + wire $ternary$libresoc.v:139052$5736_Y + attribute \src "libresoc.v:139055.19-139055.135" + wire $ternary$libresoc.v:139055$5739_Y attribute \src "libresoc.v:139056.19-139056.135" - wire $ternary$libresoc.v:139056$5739_Y - attribute \src "libresoc.v:139057.19-139057.135" - wire $ternary$libresoc.v:139057$5740_Y - attribute \src "libresoc.v:139058.19-139058.134" - wire $ternary$libresoc.v:139058$5741_Y + wire $ternary$libresoc.v:139056$5740_Y + attribute \src "libresoc.v:139057.19-139057.134" + wire $ternary$libresoc.v:139057$5741_Y + attribute \src "libresoc.v:139058.19-139058.135" + wire $ternary$libresoc.v:139058$5742_Y attribute \src "libresoc.v:139059.19-139059.135" - wire $ternary$libresoc.v:139059$5742_Y - attribute \src "libresoc.v:139060.19-139060.135" - wire $ternary$libresoc.v:139060$5743_Y - attribute \src "libresoc.v:139061.19-139061.134" - wire $ternary$libresoc.v:139061$5744_Y - attribute \src "libresoc.v:139062.19-139062.135" - wire $ternary$libresoc.v:139062$5745_Y - attribute \src "libresoc.v:139063.19-139063.133" - wire $ternary$libresoc.v:139063$5746_Y - attribute \src "libresoc.v:139064.19-139064.134" - wire $ternary$libresoc.v:139064$5747_Y - attribute \src "libresoc.v:139065.19-139065.133" - wire $ternary$libresoc.v:139065$5748_Y + wire $ternary$libresoc.v:139059$5743_Y + attribute \src "libresoc.v:139060.19-139060.134" + wire $ternary$libresoc.v:139060$5744_Y + attribute \src "libresoc.v:139061.19-139061.135" + wire $ternary$libresoc.v:139061$5745_Y + attribute \src "libresoc.v:139062.19-139062.133" + wire $ternary$libresoc.v:139062$5746_Y + attribute \src "libresoc.v:139063.19-139063.134" + wire $ternary$libresoc.v:139063$5747_Y + attribute \src "libresoc.v:139064.19-139064.133" + wire $ternary$libresoc.v:139064$5748_Y + attribute \src "libresoc.v:139066.19-139066.134" + wire $ternary$libresoc.v:139066$5750_Y attribute \src "libresoc.v:139067.19-139067.134" - wire $ternary$libresoc.v:139067$5750_Y - attribute \src "libresoc.v:139068.19-139068.134" - wire $ternary$libresoc.v:139068$5751_Y - attribute \src "libresoc.v:139069.19-139069.133" - wire $ternary$libresoc.v:139069$5752_Y + wire $ternary$libresoc.v:139067$5751_Y + attribute \src "libresoc.v:139068.19-139068.133" + wire $ternary$libresoc.v:139068$5752_Y + attribute \src "libresoc.v:139069.19-139069.134" + wire $ternary$libresoc.v:139069$5753_Y attribute \src "libresoc.v:139070.19-139070.134" - wire $ternary$libresoc.v:139070$5753_Y - attribute \src "libresoc.v:139071.19-139071.134" - wire $ternary$libresoc.v:139071$5754_Y - attribute \src "libresoc.v:139072.19-139072.133" - wire $ternary$libresoc.v:139072$5755_Y + wire $ternary$libresoc.v:139070$5754_Y + attribute \src "libresoc.v:139071.19-139071.133" + wire $ternary$libresoc.v:139071$5755_Y + attribute \src "libresoc.v:139072.19-139072.134" + wire $ternary$libresoc.v:139072$5756_Y attribute \src "libresoc.v:139073.19-139073.134" - wire $ternary$libresoc.v:139073$5756_Y - attribute \src "libresoc.v:139074.19-139074.134" - wire $ternary$libresoc.v:139074$5757_Y - attribute \src "libresoc.v:139075.19-139075.133" - wire $ternary$libresoc.v:139075$5758_Y - attribute \src "libresoc.v:139076.19-139076.134" - wire $ternary$libresoc.v:139076$5759_Y - attribute \src "libresoc.v:139078.19-139078.134" - wire $ternary$libresoc.v:139078$5761_Y - attribute \src "libresoc.v:139079.19-139079.133" - wire $ternary$libresoc.v:139079$5762_Y + wire $ternary$libresoc.v:139073$5757_Y + attribute \src "libresoc.v:139074.19-139074.133" + wire $ternary$libresoc.v:139074$5758_Y + attribute \src "libresoc.v:139075.19-139075.134" + wire $ternary$libresoc.v:139075$5759_Y + attribute \src "libresoc.v:139077.19-139077.134" + wire $ternary$libresoc.v:139077$5761_Y + attribute \src "libresoc.v:139078.19-139078.133" + wire $ternary$libresoc.v:139078$5762_Y + attribute \src "libresoc.v:139079.19-139079.134" + wire $ternary$libresoc.v:139079$5763_Y attribute \src "libresoc.v:139080.19-139080.134" - wire $ternary$libresoc.v:139080$5763_Y - attribute \src "libresoc.v:139081.19-139081.134" - wire $ternary$libresoc.v:139081$5764_Y - attribute \src "libresoc.v:139082.19-139082.133" - wire $ternary$libresoc.v:139082$5765_Y - attribute \src "libresoc.v:139083.19-139083.134" - wire $ternary$libresoc.v:139083$5766_Y - attribute \src "libresoc.v:139084.19-139084.135" - wire $ternary$libresoc.v:139084$5767_Y - attribute \src "libresoc.v:139085.19-139085.134" - wire $ternary$libresoc.v:139085$5768_Y + wire $ternary$libresoc.v:139080$5764_Y + attribute \src "libresoc.v:139081.19-139081.133" + wire $ternary$libresoc.v:139081$5765_Y + attribute \src "libresoc.v:139082.19-139082.134" + wire $ternary$libresoc.v:139082$5766_Y + attribute \src "libresoc.v:139083.19-139083.135" + wire $ternary$libresoc.v:139083$5767_Y + attribute \src "libresoc.v:139084.19-139084.134" + wire $ternary$libresoc.v:139084$5768_Y + attribute \src "libresoc.v:139085.19-139085.135" + wire $ternary$libresoc.v:139085$5769_Y attribute \src "libresoc.v:139086.19-139086.135" - wire $ternary$libresoc.v:139086$5769_Y - attribute \src "libresoc.v:139087.19-139087.135" - wire $ternary$libresoc.v:139087$5770_Y - attribute \src "libresoc.v:139089.19-139089.134" - wire $ternary$libresoc.v:139089$5772_Y - attribute \src "libresoc.v:139090.19-139090.135" - wire $ternary$libresoc.v:139090$5773_Y + wire $ternary$libresoc.v:139086$5770_Y + attribute \src "libresoc.v:139088.19-139088.134" + wire $ternary$libresoc.v:139088$5772_Y + attribute \src "libresoc.v:139089.19-139089.135" + wire $ternary$libresoc.v:139089$5773_Y + attribute \src "libresoc.v:139090.19-139090.133" + wire $ternary$libresoc.v:139090$5774_Y attribute \src "libresoc.v:139091.19-139091.133" - wire $ternary$libresoc.v:139091$5774_Y + wire $ternary$libresoc.v:139091$5775_Y attribute \src "libresoc.v:139092.19-139092.133" - wire $ternary$libresoc.v:139092$5775_Y + wire $ternary$libresoc.v:139092$5776_Y attribute \src "libresoc.v:139093.19-139093.133" - wire $ternary$libresoc.v:139093$5776_Y + wire $ternary$libresoc.v:139093$5777_Y attribute \src "libresoc.v:139094.19-139094.133" - wire $ternary$libresoc.v:139094$5777_Y + wire $ternary$libresoc.v:139094$5778_Y attribute \src "libresoc.v:139095.19-139095.133" - wire $ternary$libresoc.v:139095$5778_Y + wire $ternary$libresoc.v:139095$5779_Y attribute \src "libresoc.v:139096.19-139096.133" - wire $ternary$libresoc.v:139096$5779_Y + wire $ternary$libresoc.v:139096$5780_Y attribute \src "libresoc.v:139097.19-139097.133" - wire $ternary$libresoc.v:139097$5780_Y - attribute \src "libresoc.v:139098.19-139098.133" - wire $ternary$libresoc.v:139098$5781_Y + wire $ternary$libresoc.v:139097$5781_Y + attribute \src "libresoc.v:139099.19-139099.133" + wire $ternary$libresoc.v:139099$5783_Y attribute \src "libresoc.v:139100.19-139100.133" - wire $ternary$libresoc.v:139100$5783_Y - attribute \src "libresoc.v:139101.19-139101.133" - wire $ternary$libresoc.v:139101$5784_Y + wire $ternary$libresoc.v:139100$5784_Y + attribute \src "libresoc.v:139101.19-139101.134" + wire $ternary$libresoc.v:139101$5785_Y attribute \src "libresoc.v:139102.19-139102.134" - wire $ternary$libresoc.v:139102$5785_Y - attribute \src "libresoc.v:139103.19-139103.134" - wire $ternary$libresoc.v:139103$5786_Y - attribute \src "libresoc.v:139104.19-139104.135" - wire $ternary$libresoc.v:139104$5787_Y - attribute \src "libresoc.v:139105.19-139105.133" - wire $ternary$libresoc.v:139105$5788_Y + wire $ternary$libresoc.v:139102$5786_Y + attribute \src "libresoc.v:139103.19-139103.135" + wire $ternary$libresoc.v:139103$5787_Y + attribute \src "libresoc.v:139104.19-139104.133" + wire $ternary$libresoc.v:139104$5788_Y + attribute \src "libresoc.v:139105.19-139105.135" + wire $ternary$libresoc.v:139105$5789_Y attribute \src "libresoc.v:139106.19-139106.135" - wire $ternary$libresoc.v:139106$5789_Y - attribute \src "libresoc.v:139107.19-139107.135" - wire $ternary$libresoc.v:139107$5790_Y + wire $ternary$libresoc.v:139106$5790_Y + attribute \src "libresoc.v:139107.19-139107.134" + wire $ternary$libresoc.v:139107$5791_Y attribute \src "libresoc.v:139108.19-139108.134" - wire $ternary$libresoc.v:139108$5791_Y - attribute \src "libresoc.v:139109.19-139109.134" - wire $ternary$libresoc.v:139109$5792_Y + wire $ternary$libresoc.v:139108$5792_Y + attribute \src "libresoc.v:139110.19-139110.134" + wire $ternary$libresoc.v:139110$5794_Y attribute \src "libresoc.v:139111.19-139111.134" - wire $ternary$libresoc.v:139111$5794_Y + wire $ternary$libresoc.v:139111$5795_Y attribute \src "libresoc.v:139112.19-139112.134" - wire $ternary$libresoc.v:139112$5795_Y + wire $ternary$libresoc.v:139112$5796_Y attribute \src "libresoc.v:139113.19-139113.134" - wire $ternary$libresoc.v:139113$5796_Y - attribute \src "libresoc.v:139114.19-139114.134" - wire $ternary$libresoc.v:139114$5797_Y - attribute \src "libresoc.v:139115.19-139115.135" - wire $ternary$libresoc.v:139115$5798_Y - attribute \src "libresoc.v:139116.19-139116.134" - wire $ternary$libresoc.v:139116$5799_Y + wire $ternary$libresoc.v:139113$5797_Y + attribute \src "libresoc.v:139114.19-139114.135" + wire $ternary$libresoc.v:139114$5798_Y + attribute \src "libresoc.v:139115.19-139115.134" + wire $ternary$libresoc.v:139115$5799_Y + attribute \src "libresoc.v:139116.19-139116.135" + wire $ternary$libresoc.v:139116$5800_Y attribute \src "libresoc.v:139117.19-139117.135" - wire $ternary$libresoc.v:139117$5800_Y - attribute \src "libresoc.v:139118.19-139118.135" - wire $ternary$libresoc.v:139118$5801_Y - attribute \src "libresoc.v:139119.19-139119.134" - wire $ternary$libresoc.v:139119$5802_Y - attribute \src "libresoc.v:139120.19-139120.135" - wire $ternary$libresoc.v:139120$5803_Y - attribute \src "libresoc.v:139122.19-139122.136" - wire $ternary$libresoc.v:139122$5805_Y - attribute \src "libresoc.v:139123.19-139123.135" - wire $ternary$libresoc.v:139123$5806_Y + wire $ternary$libresoc.v:139117$5801_Y + attribute \src "libresoc.v:139118.19-139118.134" + wire $ternary$libresoc.v:139118$5802_Y + attribute \src "libresoc.v:139119.19-139119.135" + wire $ternary$libresoc.v:139119$5803_Y + attribute \src "libresoc.v:139121.19-139121.136" + wire $ternary$libresoc.v:139121$5805_Y + attribute \src "libresoc.v:139122.19-139122.135" + wire $ternary$libresoc.v:139122$5806_Y + attribute \src "libresoc.v:139123.19-139123.136" + wire $ternary$libresoc.v:139123$5807_Y attribute \src "libresoc.v:139124.19-139124.136" - wire $ternary$libresoc.v:139124$5807_Y - attribute \src "libresoc.v:139125.19-139125.136" - wire $ternary$libresoc.v:139125$5808_Y - attribute \src "libresoc.v:139126.19-139126.135" - wire $ternary$libresoc.v:139126$5809_Y + wire $ternary$libresoc.v:139124$5808_Y + attribute \src "libresoc.v:139125.19-139125.135" + wire $ternary$libresoc.v:139125$5809_Y + attribute \src "libresoc.v:139126.19-139126.136" + wire $ternary$libresoc.v:139126$5810_Y attribute \src "libresoc.v:139127.19-139127.136" - wire $ternary$libresoc.v:139127$5810_Y - attribute \src "libresoc.v:139128.19-139128.136" - wire $ternary$libresoc.v:139128$5811_Y - attribute \src "libresoc.v:139129.19-139129.135" - wire $ternary$libresoc.v:139129$5812_Y + wire $ternary$libresoc.v:139127$5811_Y + attribute \src "libresoc.v:139128.19-139128.135" + wire $ternary$libresoc.v:139128$5812_Y + attribute \src "libresoc.v:139129.19-139129.136" + wire $ternary$libresoc.v:139129$5813_Y attribute \src "libresoc.v:139130.19-139130.136" - wire $ternary$libresoc.v:139130$5813_Y - attribute \src "libresoc.v:139131.19-139131.136" - wire $ternary$libresoc.v:139131$5814_Y - attribute \src "libresoc.v:139133.19-139133.135" - wire $ternary$libresoc.v:139133$5816_Y + wire $ternary$libresoc.v:139130$5814_Y + attribute \src "libresoc.v:139132.19-139132.135" + wire $ternary$libresoc.v:139132$5816_Y + attribute \src "libresoc.v:139133.19-139133.136" + wire $ternary$libresoc.v:139133$5817_Y attribute \src "libresoc.v:139134.19-139134.136" - wire $ternary$libresoc.v:139134$5817_Y - attribute \src "libresoc.v:139135.19-139135.136" - wire $ternary$libresoc.v:139135$5818_Y - attribute \src "libresoc.v:139136.19-139136.135" - wire $ternary$libresoc.v:139136$5819_Y + wire $ternary$libresoc.v:139134$5818_Y + attribute \src "libresoc.v:139135.19-139135.135" + wire $ternary$libresoc.v:139135$5819_Y + attribute \src "libresoc.v:139136.19-139136.136" + wire $ternary$libresoc.v:139136$5820_Y attribute \src "libresoc.v:139137.19-139137.136" - wire $ternary$libresoc.v:139137$5820_Y - attribute \src "libresoc.v:139138.19-139138.136" - wire $ternary$libresoc.v:139138$5821_Y - attribute \src "libresoc.v:139139.19-139139.135" - wire $ternary$libresoc.v:139139$5822_Y - attribute \src "libresoc.v:139140.19-139140.136" - wire $ternary$libresoc.v:139140$5823_Y + wire $ternary$libresoc.v:139137$5821_Y + attribute \src "libresoc.v:139138.19-139138.135" + wire $ternary$libresoc.v:139138$5822_Y + attribute \src "libresoc.v:139139.19-139139.136" + wire $ternary$libresoc.v:139139$5823_Y + attribute \src "libresoc.v:139226.18-139226.130" + wire $ternary$libresoc.v:139226$5911_Y attribute \src "libresoc.v:139227.18-139227.130" - wire $ternary$libresoc.v:139227$5911_Y + wire $ternary$libresoc.v:139227$5912_Y attribute \src "libresoc.v:139228.18-139228.130" - wire $ternary$libresoc.v:139228$5912_Y - attribute \src "libresoc.v:139229.18-139229.130" - wire $ternary$libresoc.v:139229$5913_Y - attribute \src "libresoc.v:139230.18-139230.131" - wire $ternary$libresoc.v:139230$5914_Y - attribute \src "libresoc.v:139232.18-139232.130" - wire $ternary$libresoc.v:139232$5916_Y + wire $ternary$libresoc.v:139228$5913_Y + attribute \src "libresoc.v:139229.18-139229.131" + wire $ternary$libresoc.v:139229$5914_Y + attribute \src "libresoc.v:139231.18-139231.130" + wire $ternary$libresoc.v:139231$5916_Y + attribute \src "libresoc.v:139232.18-139232.131" + wire $ternary$libresoc.v:139232$5917_Y attribute \src "libresoc.v:139233.18-139233.131" - wire $ternary$libresoc.v:139233$5917_Y - attribute \src "libresoc.v:139234.18-139234.131" - wire $ternary$libresoc.v:139234$5918_Y - attribute \src "libresoc.v:139235.18-139235.130" - wire $ternary$libresoc.v:139235$5919_Y - attribute \src "libresoc.v:139236.18-139236.131" - wire $ternary$libresoc.v:139236$5920_Y + wire $ternary$libresoc.v:139233$5918_Y + attribute \src "libresoc.v:139234.18-139234.130" + wire $ternary$libresoc.v:139234$5919_Y + attribute \src "libresoc.v:139235.18-139235.131" + wire $ternary$libresoc.v:139235$5920_Y + attribute \src "libresoc.v:139236.18-139236.132" + wire $ternary$libresoc.v:139236$5921_Y attribute \src "libresoc.v:139237.18-139237.132" - wire $ternary$libresoc.v:139237$5921_Y - attribute \src "libresoc.v:139238.18-139238.132" - wire $ternary$libresoc.v:139238$5922_Y + wire $ternary$libresoc.v:139237$5922_Y + attribute \src "libresoc.v:139238.18-139238.133" + wire $ternary$libresoc.v:139238$5923_Y attribute \src "libresoc.v:139239.18-139239.133" - wire $ternary$libresoc.v:139239$5923_Y - attribute \src "libresoc.v:139240.18-139240.133" - wire $ternary$libresoc.v:139240$5924_Y - attribute \src "libresoc.v:139241.18-139241.132" - wire $ternary$libresoc.v:139241$5925_Y + wire $ternary$libresoc.v:139239$5924_Y + attribute \src "libresoc.v:139240.18-139240.132" + wire $ternary$libresoc.v:139240$5925_Y + attribute \src "libresoc.v:139242.18-139242.133" + wire $ternary$libresoc.v:139242$5927_Y attribute \src "libresoc.v:139243.18-139243.133" - wire $ternary$libresoc.v:139243$5927_Y - attribute \src "libresoc.v:139244.18-139244.133" - wire $ternary$libresoc.v:139244$5928_Y - attribute \src "libresoc.v:139245.18-139245.132" - wire $ternary$libresoc.v:139245$5929_Y + wire $ternary$libresoc.v:139243$5928_Y + attribute \src "libresoc.v:139244.18-139244.132" + wire $ternary$libresoc.v:139244$5929_Y + attribute \src "libresoc.v:139245.18-139245.133" + wire $ternary$libresoc.v:139245$5930_Y attribute \src "libresoc.v:139246.18-139246.133" - wire $ternary$libresoc.v:139246$5930_Y - attribute \src "libresoc.v:139247.18-139247.133" - wire $ternary$libresoc.v:139247$5931_Y - attribute \src "libresoc.v:139248.18-139248.132" - wire $ternary$libresoc.v:139248$5932_Y + wire $ternary$libresoc.v:139246$5931_Y + attribute \src "libresoc.v:139247.18-139247.132" + wire $ternary$libresoc.v:139247$5932_Y + attribute \src "libresoc.v:139248.18-139248.133" + wire $ternary$libresoc.v:139248$5933_Y attribute \src "libresoc.v:139249.18-139249.133" - wire $ternary$libresoc.v:139249$5933_Y - attribute \src "libresoc.v:139250.18-139250.133" - wire $ternary$libresoc.v:139250$5934_Y - attribute \src "libresoc.v:139251.18-139251.132" - wire $ternary$libresoc.v:139251$5935_Y - attribute \src "libresoc.v:139252.18-139252.133" - wire $ternary$libresoc.v:139252$5936_Y + wire $ternary$libresoc.v:139249$5934_Y + attribute \src "libresoc.v:139250.18-139250.132" + wire $ternary$libresoc.v:139250$5935_Y + attribute \src "libresoc.v:139251.18-139251.133" + wire $ternary$libresoc.v:139251$5936_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" @@ -218939,13 +218939,13 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 325 \TAP_bus__tck + wire input 324 \TAP_bus__tck attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 163 \TAP_bus__tdi + wire input 162 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire output 316 \TAP_bus__tdo + wire output 315 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 326 \TAP_bus__tms + wire input 325 \TAP_bus__tms attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" wire \TAP_tdo attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" @@ -218969,7 +218969,7 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" wire \_irblock_tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 327 \clk + wire input 326 \clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire input 6 \dmi0__ack_o attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" @@ -219045,17 +219045,17 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \dmi0_datasr_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 164 \eint_0__core__i + wire output 163 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 11 \eint_0__pad__i + wire input 10 \eint_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 165 \eint_1__core__i + wire output 164 \eint_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 12 \eint_1__pad__i + wire input 11 \eint_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 166 \eint_2__core__i + wire output 165 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 13 \eint_2__pad__i + wire input 12 \eint_2__pad__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" @@ -219065,197 +219065,197 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \gpio_e10__core__i + wire output 172 \gpio_e10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 21 \gpio_e10__core__o + wire input 20 \gpio_e10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 22 \gpio_e10__core__oe + wire input 21 \gpio_e10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 20 \gpio_e10__pad__i + wire input 19 \gpio_e10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \gpio_e10__pad__o + wire output 173 \gpio_e10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \gpio_e10__pad__oe + wire output 174 \gpio_e10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 176 \gpio_e11__core__i + wire output 175 \gpio_e11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 24 \gpio_e11__core__o + wire input 23 \gpio_e11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 25 \gpio_e11__core__oe + wire input 24 \gpio_e11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 23 \gpio_e11__pad__i + wire input 22 \gpio_e11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 177 \gpio_e11__pad__o + wire output 176 \gpio_e11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 178 \gpio_e11__pad__oe + wire output 177 \gpio_e11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \gpio_e12__core__i + wire output 178 \gpio_e12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 27 \gpio_e12__core__o + wire input 26 \gpio_e12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 28 \gpio_e12__core__oe + wire input 27 \gpio_e12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 26 \gpio_e12__pad__i + wire input 25 \gpio_e12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \gpio_e12__pad__o + wire output 179 \gpio_e12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \gpio_e12__pad__oe + wire output 180 \gpio_e12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_e13__core__i + wire output 181 \gpio_e13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 30 \gpio_e13__core__o + wire input 29 \gpio_e13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 31 \gpio_e13__core__oe + wire input 30 \gpio_e13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 29 \gpio_e13__pad__i + wire input 28 \gpio_e13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_e13__pad__o + wire output 182 \gpio_e13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_e13__pad__oe + wire output 183 \gpio_e13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_e14__core__i + wire output 184 \gpio_e14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 33 \gpio_e14__core__o + wire input 32 \gpio_e14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 34 \gpio_e14__core__oe + wire input 33 \gpio_e14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 32 \gpio_e14__pad__i + wire input 31 \gpio_e14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_e14__pad__o + wire output 185 \gpio_e14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_e14__pad__oe + wire output 186 \gpio_e14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_e15__core__i + wire output 187 \gpio_e15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 36 \gpio_e15__core__o + wire input 35 \gpio_e15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 37 \gpio_e15__core__oe + wire input 36 \gpio_e15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 35 \gpio_e15__pad__i + wire input 34 \gpio_e15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_e15__pad__o + wire output 188 \gpio_e15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_e15__pad__oe + wire output 189 \gpio_e15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 167 \gpio_e8__core__i + wire output 166 \gpio_e8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 15 \gpio_e8__core__o + wire input 14 \gpio_e8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 16 \gpio_e8__core__oe + wire input 15 \gpio_e8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 14 \gpio_e8__pad__i + wire input 13 \gpio_e8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 168 \gpio_e8__pad__o + wire output 167 \gpio_e8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 169 \gpio_e8__pad__oe + wire output 168 \gpio_e8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 170 \gpio_e9__core__i + wire output 169 \gpio_e9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 18 \gpio_e9__core__o + wire input 17 \gpio_e9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 19 \gpio_e9__core__oe + wire input 18 \gpio_e9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 17 \gpio_e9__pad__i + wire input 16 \gpio_e9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 171 \gpio_e9__pad__o + wire output 170 \gpio_e9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 172 \gpio_e9__pad__oe + wire output 171 \gpio_e9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_s0__core__i + wire output 190 \gpio_s0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 39 \gpio_s0__core__o + wire input 38 \gpio_s0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 40 \gpio_s0__core__oe + wire input 39 \gpio_s0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 38 \gpio_s0__pad__i + wire input 37 \gpio_s0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \gpio_s0__pad__o + wire output 191 \gpio_s0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \gpio_s0__pad__oe + wire output 192 \gpio_s0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \gpio_s1__core__i + wire output 193 \gpio_s1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 42 \gpio_s1__core__o + wire input 41 \gpio_s1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 43 \gpio_s1__core__oe + wire input 42 \gpio_s1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 41 \gpio_s1__pad__i + wire input 40 \gpio_s1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \gpio_s1__pad__o + wire output 194 \gpio_s1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \gpio_s1__pad__oe + wire output 195 \gpio_s1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \gpio_s2__core__i + wire output 196 \gpio_s2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 45 \gpio_s2__core__o + wire input 44 \gpio_s2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 46 \gpio_s2__core__oe + wire input 45 \gpio_s2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 44 \gpio_s2__pad__i + wire input 43 \gpio_s2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \gpio_s2__pad__o + wire output 197 \gpio_s2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \gpio_s2__pad__oe + wire output 198 \gpio_s2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \gpio_s3__core__i + wire output 199 \gpio_s3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 48 \gpio_s3__core__o + wire input 47 \gpio_s3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 49 \gpio_s3__core__oe + wire input 48 \gpio_s3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 47 \gpio_s3__pad__i + wire input 46 \gpio_s3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \gpio_s3__pad__o + wire output 200 \gpio_s3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \gpio_s3__pad__oe + wire output 201 \gpio_s3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \gpio_s4__core__i + wire output 202 \gpio_s4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 51 \gpio_s4__core__o + wire input 50 \gpio_s4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 52 \gpio_s4__core__oe + wire input 51 \gpio_s4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 50 \gpio_s4__pad__i + wire input 49 \gpio_s4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \gpio_s4__pad__o + wire output 203 \gpio_s4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \gpio_s4__pad__oe + wire output 204 \gpio_s4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \gpio_s5__core__i + wire output 205 \gpio_s5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 54 \gpio_s5__core__o + wire input 53 \gpio_s5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 55 \gpio_s5__core__oe + wire input 54 \gpio_s5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 53 \gpio_s5__pad__i + wire input 52 \gpio_s5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \gpio_s5__pad__o + wire output 206 \gpio_s5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \gpio_s5__pad__oe + wire output 207 \gpio_s5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \gpio_s6__core__i + wire output 208 \gpio_s6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 57 \gpio_s6__core__o + wire input 56 \gpio_s6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 58 \gpio_s6__core__oe + wire input 57 \gpio_s6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 56 \gpio_s6__pad__i + wire input 55 \gpio_s6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \gpio_s6__pad__o + wire output 209 \gpio_s6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \gpio_s6__pad__oe + wire output 210 \gpio_s6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \gpio_s7__core__i + wire output 211 \gpio_s7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 60 \gpio_s7__core__o + wire input 59 \gpio_s7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 61 \gpio_s7__core__oe + wire input 60 \gpio_s7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 59 \gpio_s7__pad__i + wire input 58 \gpio_s7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \gpio_s7__pad__o + wire output 212 \gpio_s7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \gpio_s7__pad__oe + wire output 213 \gpio_s7__pad__oe attribute \src "libresoc.v:137576.7-137576.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" @@ -219277,25 +219277,25 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" wire \io_update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 323 \jtag_wb__ack + wire input 322 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 317 \jtag_wb__adr + wire width 29 output 316 \jtag_wb__adr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 29 \jtag_wb__adr$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 319 \jtag_wb__cyc + wire output 318 \jtag_wb__cyc attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 324 \jtag_wb__dat_r + wire width 64 input 323 \jtag_wb__dat_r attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 322 \jtag_wb__dat_w + wire width 64 output 321 \jtag_wb__dat_w attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 64 \jtag_wb__dat_w$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 318 \jtag_wb__sel + wire output 317 \jtag_wb__sel attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 320 \jtag_wb__stb + wire output 319 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 321 \jtag_wb__we + wire output 320 \jtag_wb__we attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" wire width 29 \jtag_wb_addrsr__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" @@ -219355,53 +219355,53 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \jtag_wb_datasr_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 62 \mspi0_clk__core__o + wire input 61 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \mspi0_clk__pad__o + wire output 214 \mspi0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 63 \mspi0_cs_n__core__o + wire input 62 \mspi0_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \mspi0_cs_n__pad__o + wire output 215 \mspi0_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \mspi0_miso__core__i + wire output 217 \mspi0_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 65 \mspi0_miso__pad__i + wire input 64 \mspi0_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 64 \mspi0_mosi__core__o + wire input 63 \mspi0_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \mspi0_mosi__pad__o + wire output 216 \mspi0_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 66 \mspi1_clk__core__o + wire input 65 \mspi1_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \mspi1_clk__pad__o + wire output 218 \mspi1_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 67 \mspi1_cs_n__core__o + wire input 66 \mspi1_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \mspi1_cs_n__pad__o + wire output 219 \mspi1_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \mspi1_miso__core__i + wire output 221 \mspi1_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 69 \mspi1_miso__pad__i + wire input 68 \mspi1_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 68 \mspi1_mosi__core__o + wire input 67 \mspi1_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \mspi1_mosi__pad__o + wire output 220 \mspi1_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 73 \mtwi_scl__core__o + wire input 72 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \mtwi_scl__pad__o + wire output 225 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \mtwi_sda__core__i + wire output 222 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 71 \mtwi_sda__core__o + wire input 70 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 72 \mtwi_sda__core__oe + wire input 71 \mtwi_sda__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 70 \mtwi_sda__pad__i + wire input 69 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \mtwi_sda__pad__o + wire output 223 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \mtwi_sda__pad__oe + wire output 224 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" wire \negjtag_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" @@ -219411,363 +219411,363 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire \posjtag_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 74 \pwm_0__core__o + wire input 73 \pwm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \pwm_0__pad__o + wire output 226 \pwm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 75 \pwm_1__core__o + wire input 74 \pwm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \pwm_1__pad__o + wire output 227 \pwm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 79 \sd0_clk__core__o + wire input 78 \sd0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \sd0_clk__pad__o + wire output 231 \sd0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \sd0_cmd__core__i + wire output 228 \sd0_cmd__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 77 \sd0_cmd__core__o + wire input 76 \sd0_cmd__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 78 \sd0_cmd__core__oe + wire input 77 \sd0_cmd__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 76 \sd0_cmd__pad__i + wire input 75 \sd0_cmd__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \sd0_cmd__pad__o + wire output 229 \sd0_cmd__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \sd0_cmd__pad__oe + wire output 230 \sd0_cmd__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \sd0_data0__core__i + wire output 232 \sd0_data0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 81 \sd0_data0__core__o + wire input 80 \sd0_data0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 82 \sd0_data0__core__oe + wire input 81 \sd0_data0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 80 \sd0_data0__pad__i + wire input 79 \sd0_data0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \sd0_data0__pad__o + wire output 233 \sd0_data0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \sd0_data0__pad__oe + wire output 234 \sd0_data0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sd0_data1__core__i + wire output 235 \sd0_data1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 84 \sd0_data1__core__o + wire input 83 \sd0_data1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 85 \sd0_data1__core__oe + wire input 84 \sd0_data1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 83 \sd0_data1__pad__i + wire input 82 \sd0_data1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \sd0_data1__pad__o + wire output 236 \sd0_data1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \sd0_data1__pad__oe + wire output 237 \sd0_data1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \sd0_data2__core__i + wire output 238 \sd0_data2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 87 \sd0_data2__core__o + wire input 86 \sd0_data2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 88 \sd0_data2__core__oe + wire input 87 \sd0_data2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 86 \sd0_data2__pad__i + wire input 85 \sd0_data2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \sd0_data2__pad__o + wire output 239 \sd0_data2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \sd0_data2__pad__oe + wire output 240 \sd0_data2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sd0_data3__core__i + wire output 241 \sd0_data3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 90 \sd0_data3__core__o + wire input 89 \sd0_data3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 91 \sd0_data3__core__oe + wire input 90 \sd0_data3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 89 \sd0_data3__pad__i + wire input 88 \sd0_data3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \sd0_data3__pad__o + wire output 242 \sd0_data3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sd0_data3__pad__oe + wire output 243 \sd0_data3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 117 \sdr_a_0__core__o + wire input 116 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_a_0__pad__o + wire output 269 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 135 \sdr_a_10__core__o + wire input 134 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 288 \sdr_a_10__pad__o + wire output 287 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \sdr_a_11__core__o + wire input 135 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_a_11__pad__o + wire output 288 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 137 \sdr_a_12__core__o + wire input 136 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_a_12__pad__o + wire output 289 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 118 \sdr_a_1__core__o + wire input 117 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_a_1__pad__o + wire output 270 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 119 \sdr_a_2__core__o + wire input 118 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_a_2__pad__o + wire output 271 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 120 \sdr_a_3__core__o + wire input 119 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_a_3__pad__o + wire output 272 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 121 \sdr_a_4__core__o + wire input 120 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_a_4__pad__o + wire output 273 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 122 \sdr_a_5__core__o + wire input 121 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_a_5__pad__o + wire output 274 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 123 \sdr_a_6__core__o + wire input 122 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 276 \sdr_a_6__pad__o + wire output 275 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 124 \sdr_a_7__core__o + wire input 123 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_a_7__pad__o + wire output 276 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 125 \sdr_a_8__core__o + wire input 124 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_a_8__pad__o + wire output 277 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 126 \sdr_a_9__core__o + wire input 125 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_a_9__pad__o + wire output 278 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 127 \sdr_ba_0__core__o + wire input 126 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_ba_0__pad__o + wire output 279 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 128 \sdr_ba_1__core__o + wire input 127 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_ba_1__pad__o + wire output 280 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 132 \sdr_cas_n__core__o + wire input 131 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_cas_n__pad__o + wire output 284 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 130 \sdr_cke__core__o + wire input 129 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_cke__pad__o + wire output 282 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \sdr_clock__core__o + wire input 128 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 282 \sdr_clock__pad__o + wire output 281 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 134 \sdr_cs_n__core__o + wire input 133 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_cs_n__pad__o + wire output 286 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 92 \sdr_dm_0__core__o + wire input 91 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sdr_dm_0__pad__o + wire output 244 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \sdr_dm_1__core__o + wire input 137 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_dm_1__pad__o + wire output 290 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sdr_dq_0__core__i + wire output 245 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 94 \sdr_dq_0__core__o + wire input 93 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 95 \sdr_dq_0__core__oe + wire input 94 \sdr_dq_0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 93 \sdr_dq_0__pad__i + wire input 92 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sdr_dq_0__pad__o + wire output 246 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sdr_dq_0__pad__oe + wire output 247 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_dq_10__core__i + wire output 297 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 146 \sdr_dq_10__core__o + wire input 145 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \sdr_dq_10__core__oe + wire input 146 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \sdr_dq_10__pad__i + wire input 144 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_dq_10__pad__o + wire output 298 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 300 \sdr_dq_10__pad__oe + wire output 299 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_dq_11__core__i + wire output 300 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 149 \sdr_dq_11__core__o + wire input 148 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sdr_dq_11__core__oe + wire input 149 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 148 \sdr_dq_11__pad__i + wire input 147 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_dq_11__pad__o + wire output 301 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_dq_11__pad__oe + wire output 302 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_dq_12__core__i + wire output 303 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dq_12__core__o + wire input 151 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dq_12__core__oe + wire input 152 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sdr_dq_12__pad__i + wire input 150 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_dq_12__pad__o + wire output 304 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 306 \sdr_dq_12__pad__oe + wire output 305 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dq_13__core__i + wire output 306 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sdr_dq_13__core__o + wire input 154 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 156 \sdr_dq_13__core__oe + wire input 155 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 154 \sdr_dq_13__pad__i + wire input 153 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dq_13__pad__o + wire output 307 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_13__pad__oe + wire output 308 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_14__core__i + wire output 309 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sdr_dq_14__core__o + wire input 157 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sdr_dq_14__core__oe + wire input 158 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 157 \sdr_dq_14__pad__i + wire input 156 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_14__pad__o + wire output 310 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 312 \sdr_dq_14__pad__oe + wire output 311 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_15__core__i + wire output 312 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 161 \sdr_dq_15__core__o + wire input 160 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 162 \sdr_dq_15__core__oe + wire input 161 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sdr_dq_15__pad__i + wire input 159 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_15__pad__o + wire output 313 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_15__pad__oe + wire output 314 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sdr_dq_1__core__i + wire output 248 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 97 \sdr_dq_1__core__o + wire input 96 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 98 \sdr_dq_1__core__oe + wire input 97 \sdr_dq_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 96 \sdr_dq_1__pad__i + wire input 95 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sdr_dq_1__pad__o + wire output 249 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sdr_dq_1__pad__oe + wire output 250 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sdr_dq_2__core__i + wire output 251 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 100 \sdr_dq_2__core__o + wire input 99 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 101 \sdr_dq_2__core__oe + wire input 100 \sdr_dq_2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 99 \sdr_dq_2__pad__i + wire input 98 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sdr_dq_2__pad__o + wire output 252 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_dq_2__pad__oe + wire output 253 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sdr_dq_3__core__i + wire output 254 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 103 \sdr_dq_3__core__o + wire input 102 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 104 \sdr_dq_3__core__oe + wire input 103 \sdr_dq_3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 102 \sdr_dq_3__pad__i + wire input 101 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sdr_dq_3__pad__o + wire output 255 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sdr_dq_3__pad__oe + wire output 256 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_dq_4__core__i + wire output 257 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 106 \sdr_dq_4__core__o + wire input 105 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 107 \sdr_dq_4__core__oe + wire input 106 \sdr_dq_4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 105 \sdr_dq_4__pad__i + wire input 104 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sdr_dq_4__pad__o + wire output 258 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dq_4__pad__oe + wire output 259 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_5__core__i + wire output 260 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 109 \sdr_dq_5__core__o + wire input 108 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 110 \sdr_dq_5__core__oe + wire input 109 \sdr_dq_5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 108 \sdr_dq_5__pad__i + wire input 107 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_5__pad__o + wire output 261 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_5__pad__oe + wire output 262 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_6__core__i + wire output 263 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 112 \sdr_dq_6__core__o + wire input 111 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 113 \sdr_dq_6__core__oe + wire input 112 \sdr_dq_6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 111 \sdr_dq_6__pad__i + wire input 110 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_6__pad__o + wire output 264 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_6__pad__oe + wire output 265 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_7__core__i + wire output 266 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 115 \sdr_dq_7__core__o + wire input 114 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 116 \sdr_dq_7__core__oe + wire input 115 \sdr_dq_7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 114 \sdr_dq_7__pad__i + wire input 113 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_7__pad__o + wire output 267 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_dq_7__pad__oe + wire output 268 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_dq_8__core__i + wire output 291 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \sdr_dq_8__core__o + wire input 139 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 141 \sdr_dq_8__core__oe + wire input 140 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \sdr_dq_8__pad__i + wire input 138 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_dq_8__pad__o + wire output 292 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 294 \sdr_dq_8__pad__oe + wire output 293 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_dq_9__core__i + wire output 294 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \sdr_dq_9__core__o + wire input 142 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 144 \sdr_dq_9__core__oe + wire input 143 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 142 \sdr_dq_9__pad__i + wire input 141 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_dq_9__pad__o + wire output 295 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_dq_9__pad__oe + wire output 296 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \sdr_ras_n__core__o + wire input 130 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_ras_n__pad__o + wire output 283 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \sdr_we_n__core__o + wire input 132 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_we_n__pad__o + wire output 285 \sdr_we_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" wire width 3 \sr0__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" @@ -219827,19 +219827,19 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \sr5_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" - wire output 9 \wb_dcache_en + wire output 8 \wb_dcache_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire \wb_dcache_en$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" - wire output 10 \wb_icache_en + wire output 9 \wb_icache_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire \wb_icache_en$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" - wire output 8 \wb_sram_en + wire \wb_sram_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" wire \wb_sram_en$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - cell $add $add$libresoc.v:139217$5900 + cell $add $add$libresoc.v:139216$5900 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -219847,10 +219847,10 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:139217$5900_Y + connect \Y $add$libresoc.v:139216$5900_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - cell $add $add$libresoc.v:139218$5901 + cell $add $add$libresoc.v:139217$5901 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -219858,10 +219858,10 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:139218$5901_Y + connect \Y $add$libresoc.v:139217$5901_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - cell $add $add$libresoc.v:139225$5909 + cell $add $add$libresoc.v:139224$5909 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -219869,10 +219869,10 @@ module \jtag parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:139225$5909_Y + connect \Y $add$libresoc.v:139224$5909_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - cell $add $add$libresoc.v:139226$5910 + cell $add $add$libresoc.v:139225$5910 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -219880,10 +219880,10 @@ module \jtag parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:139226$5910_Y + connect \Y $add$libresoc.v:139225$5910_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" - cell $and $and$libresoc.v:139043$5726 + cell $and $and$libresoc.v:139042$5726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219891,10 +219891,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$15 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139043$5726_Y + connect \Y $and$libresoc.v:139042$5726_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:139110$5793 + cell $and $and$libresoc.v:139109$5793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219902,10 +219902,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$27 - connect \Y $and$libresoc.v:139110$5793_Y + connect \Y $and$libresoc.v:139109$5793_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" - cell $and $and$libresoc.v:139121$5804 + cell $and $and$libresoc.v:139120$5804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219913,10 +219913,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$29 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139121$5804_Y + connect \Y $and$libresoc.v:139120$5804_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:139147$5830 + cell $and $and$libresoc.v:139146$5830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219924,10 +219924,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$363 - connect \Y $and$libresoc.v:139147$5830_Y + connect \Y $and$libresoc.v:139146$5830_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139150$5833 + cell $and $and$libresoc.v:139149$5833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219935,10 +219935,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$369 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139150$5833_Y + connect \Y $and$libresoc.v:139149$5833_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139152$5835 + cell $and $and$libresoc.v:139151$5835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219946,10 +219946,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$373 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139152$5835_Y + connect \Y $and$libresoc.v:139151$5835_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139155$5838 + cell $and $and$libresoc.v:139154$5838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219957,10 +219957,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$377 connect \B \_fsm_update - connect \Y $and$libresoc.v:139155$5838_Y + connect \Y $and$libresoc.v:139154$5838_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139157$5840 + cell $and $and$libresoc.v:139156$5840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219968,10 +219968,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_update_core_prev connect \B \$381 - connect \Y $and$libresoc.v:139157$5840_Y + connect \Y $and$libresoc.v:139156$5840_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139160$5843 + cell $and $and$libresoc.v:139159$5843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219979,10 +219979,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$387 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139160$5843_Y + connect \Y $and$libresoc.v:139159$5843_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139162$5845 + cell $and $and$libresoc.v:139161$5845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219990,10 +219990,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$391 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139162$5845_Y + connect \Y $and$libresoc.v:139161$5845_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139164$5847 + cell $and $and$libresoc.v:139163$5847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220001,10 +220001,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$395 connect \B \_fsm_update - connect \Y $and$libresoc.v:139164$5847_Y + connect \Y $and$libresoc.v:139163$5847_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139168$5851 + cell $and $and$libresoc.v:139167$5851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220012,10 +220012,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core_prev connect \B \$399 - connect \Y $and$libresoc.v:139168$5851_Y + connect \Y $and$libresoc.v:139167$5851_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139172$5855 + cell $and $and$libresoc.v:139171$5855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220023,10 +220023,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$407 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139172$5855_Y + connect \Y $and$libresoc.v:139171$5855_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139174$5857 + cell $and $and$libresoc.v:139173$5857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220034,10 +220034,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$411 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139174$5857_Y + connect \Y $and$libresoc.v:139173$5857_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139176$5859 + cell $and $and$libresoc.v:139175$5859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220045,10 +220045,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$415 connect \B \_fsm_update - connect \Y $and$libresoc.v:139176$5859_Y + connect \Y $and$libresoc.v:139175$5859_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139179$5862 + cell $and $and$libresoc.v:139178$5862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220056,10 +220056,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core_prev connect \B \$419 - connect \Y $and$libresoc.v:139179$5862_Y + connect \Y $and$libresoc.v:139178$5862_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139182$5865 + cell $and $and$libresoc.v:139181$5865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220067,10 +220067,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$425 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139182$5865_Y + connect \Y $and$libresoc.v:139181$5865_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139184$5867 + cell $and $and$libresoc.v:139183$5867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220078,10 +220078,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$429 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139184$5867_Y + connect \Y $and$libresoc.v:139183$5867_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139186$5869 + cell $and $and$libresoc.v:139185$5869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220089,10 +220089,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$433 connect \B \_fsm_update - connect \Y $and$libresoc.v:139186$5869_Y + connect \Y $and$libresoc.v:139185$5869_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:139188$5871 + cell $and $and$libresoc.v:139187$5871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220100,10 +220100,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$41 - connect \Y $and$libresoc.v:139188$5871_Y + connect \Y $and$libresoc.v:139187$5871_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139189$5872 + cell $and $and$libresoc.v:139188$5872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220111,10 +220111,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core_prev connect \B \$437 - connect \Y $and$libresoc.v:139189$5872_Y + connect \Y $and$libresoc.v:139188$5872_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139193$5876 + cell $and $and$libresoc.v:139192$5876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220122,10 +220122,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$445 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139193$5876_Y + connect \Y $and$libresoc.v:139192$5876_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139195$5878 + cell $and $and$libresoc.v:139194$5878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220133,10 +220133,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$449 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139195$5878_Y + connect \Y $and$libresoc.v:139194$5878_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139197$5880 + cell $and $and$libresoc.v:139196$5880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220144,10 +220144,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$453 connect \B \_fsm_update - connect \Y $and$libresoc.v:139197$5880_Y + connect \Y $and$libresoc.v:139196$5880_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" - cell $and $and$libresoc.v:139199$5882 + cell $and $and$libresoc.v:139198$5882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220155,10 +220155,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$43 connect \B \_fsm_update - connect \Y $and$libresoc.v:139199$5882_Y + connect \Y $and$libresoc.v:139198$5882_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139200$5883 + cell $and $and$libresoc.v:139199$5883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220166,10 +220166,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core_prev connect \B \$457 - connect \Y $and$libresoc.v:139200$5883_Y + connect \Y $and$libresoc.v:139199$5883_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139203$5886 + cell $and $and$libresoc.v:139202$5886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220177,10 +220177,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$463 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139203$5886_Y + connect \Y $and$libresoc.v:139202$5886_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139205$5888 + cell $and $and$libresoc.v:139204$5888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220188,10 +220188,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$467 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139205$5888_Y + connect \Y $and$libresoc.v:139204$5888_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139207$5890 + cell $and $and$libresoc.v:139206$5890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220199,10 +220199,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$471 connect \B \_fsm_update - connect \Y $and$libresoc.v:139207$5890_Y + connect \Y $and$libresoc.v:139206$5890_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139209$5892 + cell $and $and$libresoc.v:139208$5892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220210,10 +220210,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_update_core_prev connect \B \$475 - connect \Y $and$libresoc.v:139209$5892_Y + connect \Y $and$libresoc.v:139208$5892_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $and $and$libresoc.v:139242$5926 + cell $and $and$libresoc.v:139241$5926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220221,10 +220221,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$5 - connect \Y $and$libresoc.v:139242$5926_Y + connect \Y $and$libresoc.v:139241$5926_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:138999$5682 + cell $eq $eq$libresoc.v:138998$5682 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220232,10 +220232,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1111 - connect \Y $eq$libresoc.v:138999$5682_Y + connect \Y $eq$libresoc.v:138998$5682_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139010$5693 + cell $eq $eq$libresoc.v:139009$5693 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220243,10 +220243,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139010$5693_Y + connect \Y $eq$libresoc.v:139009$5693_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139021$5704 + cell $eq $eq$libresoc.v:139020$5704 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220254,10 +220254,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139021$5704_Y + connect \Y $eq$libresoc.v:139020$5704_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:139054$5737 + cell $eq $eq$libresoc.v:139053$5737 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220265,10 +220265,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'1 - connect \Y $eq$libresoc.v:139054$5737_Y + connect \Y $eq$libresoc.v:139053$5737_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139055$5738 + cell $eq $eq$libresoc.v:139054$5738 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220276,10 +220276,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139055$5738_Y + connect \Y $eq$libresoc.v:139054$5738_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139066$5749 + cell $eq $eq$libresoc.v:139065$5749 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220287,10 +220287,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139066$5749_Y + connect \Y $eq$libresoc.v:139065$5749_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:139088$5771 + cell $eq $eq$libresoc.v:139087$5771 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220298,10 +220298,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139088$5771_Y + connect \Y $eq$libresoc.v:139087$5771_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139132$5815 + cell $eq $eq$libresoc.v:139131$5815 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220309,10 +220309,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139132$5815_Y + connect \Y $eq$libresoc.v:139131$5815_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139141$5824 + cell $eq $eq$libresoc.v:139140$5824 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220320,10 +220320,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139141$5824_Y + connect \Y $eq$libresoc.v:139140$5824_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139142$5825 + cell $eq $eq$libresoc.v:139141$5825 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220331,10 +220331,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139142$5825_Y + connect \Y $eq$libresoc.v:139141$5825_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139143$5826 + cell $eq $eq$libresoc.v:139142$5826 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220342,10 +220342,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139143$5826_Y + connect \Y $eq$libresoc.v:139142$5826_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:139145$5828 + cell $eq $eq$libresoc.v:139144$5828 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220353,10 +220353,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139145$5828_Y + connect \Y $eq$libresoc.v:139144$5828_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139148$5831 + cell $eq $eq$libresoc.v:139147$5831 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220364,10 +220364,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'100 - connect \Y $eq$libresoc.v:139148$5831_Y + connect \Y $eq$libresoc.v:139147$5831_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139158$5841 + cell $eq $eq$libresoc.v:139157$5841 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220375,10 +220375,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'101 - connect \Y $eq$libresoc.v:139158$5841_Y + connect \Y $eq$libresoc.v:139157$5841_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:139165$5848 + cell $eq $eq$libresoc.v:139164$5848 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220386,10 +220386,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1111 - connect \Y $eq$libresoc.v:139165$5848_Y + connect \Y $eq$libresoc.v:139164$5848_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:139166$5849 + cell $eq $eq$libresoc.v:139165$5849 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220397,10 +220397,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139166$5849_Y + connect \Y $eq$libresoc.v:139165$5849_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139169$5852 + cell $eq $eq$libresoc.v:139168$5852 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220408,10 +220408,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'110 - connect \Y $eq$libresoc.v:139169$5852_Y + connect \Y $eq$libresoc.v:139168$5852_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139170$5853 + cell $eq $eq$libresoc.v:139169$5853 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220419,10 +220419,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'111 - connect \Y $eq$libresoc.v:139170$5853_Y + connect \Y $eq$libresoc.v:139169$5853_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139180$5863 + cell $eq $eq$libresoc.v:139179$5863 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220430,10 +220430,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1000 - connect \Y $eq$libresoc.v:139180$5863_Y + connect \Y $eq$libresoc.v:139179$5863_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139190$5873 + cell $eq $eq$libresoc.v:139189$5873 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220441,10 +220441,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1001 - connect \Y $eq$libresoc.v:139190$5873_Y + connect \Y $eq$libresoc.v:139189$5873_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139191$5874 + cell $eq $eq$libresoc.v:139190$5874 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220452,10 +220452,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1010 - connect \Y $eq$libresoc.v:139191$5874_Y + connect \Y $eq$libresoc.v:139190$5874_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139201$5884 + cell $eq $eq$libresoc.v:139200$5884 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220463,10 +220463,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1011 - connect \Y $eq$libresoc.v:139201$5884_Y + connect \Y $eq$libresoc.v:139200$5884_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" - cell $eq $eq$libresoc.v:139210$5893 + cell $eq $eq$libresoc.v:139209$5893 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220474,10 +220474,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139210$5893_Y + connect \Y $eq$libresoc.v:139209$5893_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $eq $eq$libresoc.v:139211$5894 + cell $eq $eq$libresoc.v:139210$5894 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220485,10 +220485,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'0 - connect \Y $eq$libresoc.v:139211$5894_Y + connect \Y $eq$libresoc.v:139210$5894_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:139213$5896 + cell $eq $eq$libresoc.v:139212$5896 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220496,10 +220496,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'1 - connect \Y $eq$libresoc.v:139213$5896_Y + connect \Y $eq$libresoc.v:139212$5896_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:139214$5897 + cell $eq $eq$libresoc.v:139213$5897 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220507,10 +220507,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:139214$5897_Y + connect \Y $eq$libresoc.v:139213$5897_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - cell $eq $eq$libresoc.v:139216$5899 + cell $eq $eq$libresoc.v:139215$5899 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220518,10 +220518,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:139216$5899_Y + connect \Y $eq$libresoc.v:139215$5899_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" - cell $eq $eq$libresoc.v:139220$5904 + cell $eq $eq$libresoc.v:139219$5904 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220529,10 +220529,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139220$5904_Y + connect \Y $eq$libresoc.v:139219$5904_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:139221$5905 + cell $eq $eq$libresoc.v:139220$5905 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220540,10 +220540,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state$499 connect \B 1'1 - connect \Y $eq$libresoc.v:139221$5905_Y + connect \Y $eq$libresoc.v:139220$5905_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:139222$5906 + cell $eq $eq$libresoc.v:139221$5906 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220551,10 +220551,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state$499 connect \B 2'10 - connect \Y $eq$libresoc.v:139222$5906_Y + connect \Y $eq$libresoc.v:139221$5906_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - cell $eq $eq$libresoc.v:139224$5908 + cell $eq $eq$libresoc.v:139223$5908 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220562,18 +220562,18 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state$499 connect \B 2'10 - connect \Y $eq$libresoc.v:139224$5908_Y + connect \Y $eq$libresoc.v:139223$5908_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $extend$libresoc.v:139219$5902 + cell $pos $extend$libresoc.v:139218$5902 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \dmi0__addr_i - connect \Y $extend$libresoc.v:139219$5902_Y + connect \Y $extend$libresoc.v:139218$5902_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139149$5832 + cell $ne $ne$libresoc.v:139148$5832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220581,10 +220581,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139149$5832_Y + connect \Y $ne$libresoc.v:139148$5832_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139151$5834 + cell $ne $ne$libresoc.v:139150$5834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220592,10 +220592,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139151$5834_Y + connect \Y $ne$libresoc.v:139150$5834_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139153$5836 + cell $ne $ne$libresoc.v:139152$5836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220603,10 +220603,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139153$5836_Y + connect \Y $ne$libresoc.v:139152$5836_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139159$5842 + cell $ne $ne$libresoc.v:139158$5842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220614,10 +220614,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139159$5842_Y + connect \Y $ne$libresoc.v:139158$5842_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139161$5844 + cell $ne $ne$libresoc.v:139160$5844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220625,10 +220625,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139161$5844_Y + connect \Y $ne$libresoc.v:139160$5844_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139163$5846 + cell $ne $ne$libresoc.v:139162$5846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220636,10 +220636,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139163$5846_Y + connect \Y $ne$libresoc.v:139162$5846_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139171$5854 + cell $ne $ne$libresoc.v:139170$5854 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220647,10 +220647,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139171$5854_Y + connect \Y $ne$libresoc.v:139170$5854_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139173$5856 + cell $ne $ne$libresoc.v:139172$5856 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220658,10 +220658,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139173$5856_Y + connect \Y $ne$libresoc.v:139172$5856_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139175$5858 + cell $ne $ne$libresoc.v:139174$5858 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220669,10 +220669,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139175$5858_Y + connect \Y $ne$libresoc.v:139174$5858_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139181$5864 + cell $ne $ne$libresoc.v:139180$5864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220680,10 +220680,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139181$5864_Y + connect \Y $ne$libresoc.v:139180$5864_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139183$5866 + cell $ne $ne$libresoc.v:139182$5866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220691,10 +220691,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139183$5866_Y + connect \Y $ne$libresoc.v:139182$5866_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139185$5868 + cell $ne $ne$libresoc.v:139184$5868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220702,10 +220702,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139185$5868_Y + connect \Y $ne$libresoc.v:139184$5868_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139192$5875 + cell $ne $ne$libresoc.v:139191$5875 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220713,10 +220713,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139192$5875_Y + connect \Y $ne$libresoc.v:139191$5875_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139194$5877 + cell $ne $ne$libresoc.v:139193$5877 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220724,10 +220724,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139194$5877_Y + connect \Y $ne$libresoc.v:139193$5877_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139196$5879 + cell $ne $ne$libresoc.v:139195$5879 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220735,10 +220735,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139196$5879_Y + connect \Y $ne$libresoc.v:139195$5879_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139202$5885 + cell $ne $ne$libresoc.v:139201$5885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220746,10 +220746,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139202$5885_Y + connect \Y $ne$libresoc.v:139201$5885_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139204$5887 + cell $ne $ne$libresoc.v:139203$5887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220757,10 +220757,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139204$5887_Y + connect \Y $ne$libresoc.v:139203$5887_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139206$5889 + cell $ne $ne$libresoc.v:139205$5889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220768,66 +220768,66 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139206$5889_Y + connect \Y $ne$libresoc.v:139205$5889_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139156$5839 + cell $not $not$libresoc.v:139155$5839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_update_core - connect \Y $not$libresoc.v:139156$5839_Y + connect \Y $not$libresoc.v:139155$5839_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139167$5850 + cell $not $not$libresoc.v:139166$5850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core - connect \Y $not$libresoc.v:139167$5850_Y + connect \Y $not$libresoc.v:139166$5850_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139178$5861 + cell $not $not$libresoc.v:139177$5861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core - connect \Y $not$libresoc.v:139178$5861_Y + connect \Y $not$libresoc.v:139177$5861_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139187$5870 + cell $not $not$libresoc.v:139186$5870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core - connect \Y $not$libresoc.v:139187$5870_Y + connect \Y $not$libresoc.v:139186$5870_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139198$5881 + cell $not $not$libresoc.v:139197$5881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core - connect \Y $not$libresoc.v:139198$5881_Y + connect \Y $not$libresoc.v:139197$5881_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139208$5891 + cell $not $not$libresoc.v:139207$5891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr5_update_core - connect \Y $not$libresoc.v:139208$5891_Y + connect \Y $not$libresoc.v:139207$5891_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $not $not$libresoc.v:139212$5895 + cell $not $not$libresoc.v:139211$5895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$480 - connect \Y $not$libresoc.v:139212$5895_Y + connect \Y $not$libresoc.v:139211$5895_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:139032$5715 + cell $or $or$libresoc.v:139031$5715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220835,10 +220835,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$11 connect \B \$13 - connect \Y $or$libresoc.v:139032$5715_Y + connect \Y $or$libresoc.v:139031$5715_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:139077$5760 + cell $or $or$libresoc.v:139076$5760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220846,10 +220846,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$19 connect \B \$21 - connect \Y $or$libresoc.v:139077$5760_Y + connect \Y $or$libresoc.v:139076$5760_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:139099$5782 + cell $or $or$libresoc.v:139098$5782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220857,10 +220857,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $or$libresoc.v:139099$5782_Y + connect \Y $or$libresoc.v:139098$5782_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:139144$5827 + cell $or $or$libresoc.v:139143$5827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220868,10 +220868,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$355 connect \B \$357 - connect \Y $or$libresoc.v:139144$5827_Y + connect \Y $or$libresoc.v:139143$5827_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:139146$5829 + cell $or $or$libresoc.v:139145$5829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220879,10 +220879,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$359 connect \B \$361 - connect \Y $or$libresoc.v:139146$5829_Y + connect \Y $or$libresoc.v:139145$5829_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:139154$5837 + cell $or $or$libresoc.v:139153$5837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220890,10 +220890,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:139154$5837_Y + connect \Y $or$libresoc.v:139153$5837_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:139177$5860 + cell $or $or$libresoc.v:139176$5860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220901,10 +220901,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:139177$5860_Y + connect \Y $or$libresoc.v:139176$5860_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $or $or$libresoc.v:139215$5898 + cell $or $or$libresoc.v:139214$5898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220912,10 +220912,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$483 connect \B \$485 - connect \Y $or$libresoc.v:139215$5898_Y + connect \Y $or$libresoc.v:139214$5898_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $or $or$libresoc.v:139223$5907 + cell $or $or$libresoc.v:139222$5907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220923,10 +220923,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$500 connect \B \$502 - connect \Y $or$libresoc.v:139223$5907_Y + connect \Y $or$libresoc.v:139222$5907_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $or $or$libresoc.v:139231$5915 + cell $or $or$libresoc.v:139230$5915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220934,1234 +220934,1234 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $or$libresoc.v:139231$5915_Y + connect \Y $or$libresoc.v:139230$5915_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $pos$libresoc.v:139219$5903 + cell $pos $pos$libresoc.v:139218$5903 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:139219$5902_Y - connect \Y $pos$libresoc.v:139219$5903_Y + connect \A $extend$libresoc.v:139218$5902_Y + connect \Y $pos$libresoc.v:139218$5903_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139000$5683 + cell $mux $ternary$libresoc.v:138999$5683 parameter \WIDTH 1 connect \A \gpio_e15__pad__i connect \B \io_bd [24] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139000$5683_Y + connect \Y $ternary$libresoc.v:138999$5683_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139001$5684 + cell $mux $ternary$libresoc.v:139000$5684 parameter \WIDTH 1 connect \A \gpio_e15__core__o connect \B \io_bd [25] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139001$5684_Y + connect \Y $ternary$libresoc.v:139000$5684_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139002$5685 + cell $mux $ternary$libresoc.v:139001$5685 parameter \WIDTH 1 connect \A \gpio_e15__core__oe connect \B \io_bd [26] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139002$5685_Y + connect \Y $ternary$libresoc.v:139001$5685_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139003$5686 + cell $mux $ternary$libresoc.v:139002$5686 parameter \WIDTH 1 connect \A \gpio_s0__pad__i connect \B \io_bd [27] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139003$5686_Y + connect \Y $ternary$libresoc.v:139002$5686_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139004$5687 + cell $mux $ternary$libresoc.v:139003$5687 parameter \WIDTH 1 connect \A \gpio_s0__core__o connect \B \io_bd [28] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139004$5687_Y + connect \Y $ternary$libresoc.v:139003$5687_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139005$5688 + cell $mux $ternary$libresoc.v:139004$5688 parameter \WIDTH 1 connect \A \gpio_s0__core__oe connect \B \io_bd [29] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139005$5688_Y + connect \Y $ternary$libresoc.v:139004$5688_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139006$5689 + cell $mux $ternary$libresoc.v:139005$5689 parameter \WIDTH 1 connect \A \gpio_s1__pad__i connect \B \io_bd [30] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139006$5689_Y + connect \Y $ternary$libresoc.v:139005$5689_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139007$5690 + cell $mux $ternary$libresoc.v:139006$5690 parameter \WIDTH 1 connect \A \gpio_s1__core__o connect \B \io_bd [31] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139007$5690_Y + connect \Y $ternary$libresoc.v:139006$5690_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139008$5691 + cell $mux $ternary$libresoc.v:139007$5691 parameter \WIDTH 1 connect \A \gpio_s1__core__oe connect \B \io_bd [32] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139008$5691_Y + connect \Y $ternary$libresoc.v:139007$5691_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139009$5692 + cell $mux $ternary$libresoc.v:139008$5692 parameter \WIDTH 1 connect \A \gpio_s2__pad__i connect \B \io_bd [33] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139009$5692_Y + connect \Y $ternary$libresoc.v:139008$5692_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139011$5694 + cell $mux $ternary$libresoc.v:139010$5694 parameter \WIDTH 1 connect \A \gpio_s2__core__o connect \B \io_bd [34] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139011$5694_Y + connect \Y $ternary$libresoc.v:139010$5694_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139012$5695 + cell $mux $ternary$libresoc.v:139011$5695 parameter \WIDTH 1 connect \A \gpio_s2__core__oe connect \B \io_bd [35] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139012$5695_Y + connect \Y $ternary$libresoc.v:139011$5695_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139013$5696 + cell $mux $ternary$libresoc.v:139012$5696 parameter \WIDTH 1 connect \A \gpio_s3__pad__i connect \B \io_bd [36] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139013$5696_Y + connect \Y $ternary$libresoc.v:139012$5696_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139014$5697 + cell $mux $ternary$libresoc.v:139013$5697 parameter \WIDTH 1 connect \A \gpio_s3__core__o connect \B \io_bd [37] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139014$5697_Y + connect \Y $ternary$libresoc.v:139013$5697_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139015$5698 + cell $mux $ternary$libresoc.v:139014$5698 parameter \WIDTH 1 connect \A \gpio_s3__core__oe connect \B \io_bd [38] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139015$5698_Y + connect \Y $ternary$libresoc.v:139014$5698_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139016$5699 + cell $mux $ternary$libresoc.v:139015$5699 parameter \WIDTH 1 connect \A \gpio_s4__pad__i connect \B \io_bd [39] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139016$5699_Y + connect \Y $ternary$libresoc.v:139015$5699_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139017$5700 + cell $mux $ternary$libresoc.v:139016$5700 parameter \WIDTH 1 connect \A \gpio_s4__core__o connect \B \io_bd [40] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139017$5700_Y + connect \Y $ternary$libresoc.v:139016$5700_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139018$5701 + cell $mux $ternary$libresoc.v:139017$5701 parameter \WIDTH 1 connect \A \gpio_s4__core__oe connect \B \io_bd [41] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139018$5701_Y + connect \Y $ternary$libresoc.v:139017$5701_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139019$5702 + cell $mux $ternary$libresoc.v:139018$5702 parameter \WIDTH 1 connect \A \gpio_s5__pad__i connect \B \io_bd [42] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139019$5702_Y + connect \Y $ternary$libresoc.v:139018$5702_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139020$5703 + cell $mux $ternary$libresoc.v:139019$5703 parameter \WIDTH 1 connect \A \gpio_s5__core__o connect \B \io_bd [43] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139020$5703_Y + connect \Y $ternary$libresoc.v:139019$5703_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139022$5705 + cell $mux $ternary$libresoc.v:139021$5705 parameter \WIDTH 1 connect \A \gpio_s5__core__oe connect \B \io_bd [44] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139022$5705_Y + connect \Y $ternary$libresoc.v:139021$5705_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139023$5706 + cell $mux $ternary$libresoc.v:139022$5706 parameter \WIDTH 1 connect \A \gpio_s6__pad__i connect \B \io_bd [45] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139023$5706_Y + connect \Y $ternary$libresoc.v:139022$5706_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139024$5707 + cell $mux $ternary$libresoc.v:139023$5707 parameter \WIDTH 1 connect \A \gpio_s6__core__o connect \B \io_bd [46] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139024$5707_Y + connect \Y $ternary$libresoc.v:139023$5707_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139025$5708 + cell $mux $ternary$libresoc.v:139024$5708 parameter \WIDTH 1 connect \A \gpio_s6__core__oe connect \B \io_bd [47] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139025$5708_Y + connect \Y $ternary$libresoc.v:139024$5708_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139026$5709 + cell $mux $ternary$libresoc.v:139025$5709 parameter \WIDTH 1 connect \A \gpio_s7__pad__i connect \B \io_bd [48] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139026$5709_Y + connect \Y $ternary$libresoc.v:139025$5709_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139027$5710 + cell $mux $ternary$libresoc.v:139026$5710 parameter \WIDTH 1 connect \A \gpio_s7__core__o connect \B \io_bd [49] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139027$5710_Y + connect \Y $ternary$libresoc.v:139026$5710_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139028$5711 + cell $mux $ternary$libresoc.v:139027$5711 parameter \WIDTH 1 connect \A \gpio_s7__core__oe connect \B \io_bd [50] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139028$5711_Y + connect \Y $ternary$libresoc.v:139027$5711_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139029$5712 + cell $mux $ternary$libresoc.v:139028$5712 parameter \WIDTH 1 connect \A \mspi0_clk__core__o connect \B \io_bd [51] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139029$5712_Y + connect \Y $ternary$libresoc.v:139028$5712_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139030$5713 + cell $mux $ternary$libresoc.v:139029$5713 parameter \WIDTH 1 connect \A \mspi0_cs_n__core__o connect \B \io_bd [52] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139030$5713_Y + connect \Y $ternary$libresoc.v:139029$5713_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139031$5714 + cell $mux $ternary$libresoc.v:139030$5714 parameter \WIDTH 1 connect \A \mspi0_mosi__core__o connect \B \io_bd [53] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139031$5714_Y + connect \Y $ternary$libresoc.v:139030$5714_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139033$5716 + cell $mux $ternary$libresoc.v:139032$5716 parameter \WIDTH 1 connect \A \mspi0_miso__pad__i connect \B \io_bd [54] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139033$5716_Y + connect \Y $ternary$libresoc.v:139032$5716_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139034$5717 + cell $mux $ternary$libresoc.v:139033$5717 parameter \WIDTH 1 connect \A \mspi1_clk__core__o connect \B \io_bd [55] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139034$5717_Y + connect \Y $ternary$libresoc.v:139033$5717_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139035$5718 + cell $mux $ternary$libresoc.v:139034$5718 parameter \WIDTH 1 connect \A \mspi1_cs_n__core__o connect \B \io_bd [56] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139035$5718_Y + connect \Y $ternary$libresoc.v:139034$5718_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139036$5719 + cell $mux $ternary$libresoc.v:139035$5719 parameter \WIDTH 1 connect \A \mspi1_mosi__core__o connect \B \io_bd [57] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139036$5719_Y + connect \Y $ternary$libresoc.v:139035$5719_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139037$5720 + cell $mux $ternary$libresoc.v:139036$5720 parameter \WIDTH 1 connect \A \mspi1_miso__pad__i connect \B \io_bd [58] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139037$5720_Y + connect \Y $ternary$libresoc.v:139036$5720_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139038$5721 + cell $mux $ternary$libresoc.v:139037$5721 parameter \WIDTH 1 connect \A \mtwi_sda__pad__i connect \B \io_bd [59] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139038$5721_Y + connect \Y $ternary$libresoc.v:139037$5721_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139039$5722 + cell $mux $ternary$libresoc.v:139038$5722 parameter \WIDTH 1 connect \A \mtwi_sda__core__o connect \B \io_bd [60] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139039$5722_Y + connect \Y $ternary$libresoc.v:139038$5722_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139040$5723 + cell $mux $ternary$libresoc.v:139039$5723 parameter \WIDTH 1 connect \A \mtwi_sda__core__oe connect \B \io_bd [61] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139040$5723_Y + connect \Y $ternary$libresoc.v:139039$5723_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139041$5724 + cell $mux $ternary$libresoc.v:139040$5724 parameter \WIDTH 1 connect \A \mtwi_scl__core__o connect \B \io_bd [62] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139041$5724_Y + connect \Y $ternary$libresoc.v:139040$5724_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139042$5725 + cell $mux $ternary$libresoc.v:139041$5725 parameter \WIDTH 1 connect \A \pwm_0__core__o connect \B \io_bd [63] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139042$5725_Y + connect \Y $ternary$libresoc.v:139041$5725_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139044$5727 + cell $mux $ternary$libresoc.v:139043$5727 parameter \WIDTH 1 connect \A \pwm_1__core__o connect \B \io_bd [64] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139044$5727_Y + connect \Y $ternary$libresoc.v:139043$5727_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139045$5728 + cell $mux $ternary$libresoc.v:139044$5728 parameter \WIDTH 1 connect \A \sd0_cmd__pad__i connect \B \io_bd [65] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139045$5728_Y + connect \Y $ternary$libresoc.v:139044$5728_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139046$5729 + cell $mux $ternary$libresoc.v:139045$5729 parameter \WIDTH 1 connect \A \sd0_cmd__core__o connect \B \io_bd [66] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139046$5729_Y + connect \Y $ternary$libresoc.v:139045$5729_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139047$5730 + cell $mux $ternary$libresoc.v:139046$5730 parameter \WIDTH 1 connect \A \sd0_cmd__core__oe connect \B \io_bd [67] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139047$5730_Y + connect \Y $ternary$libresoc.v:139046$5730_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139048$5731 + cell $mux $ternary$libresoc.v:139047$5731 parameter \WIDTH 1 connect \A \sd0_clk__core__o connect \B \io_bd [68] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139048$5731_Y + connect \Y $ternary$libresoc.v:139047$5731_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139049$5732 + cell $mux $ternary$libresoc.v:139048$5732 parameter \WIDTH 1 connect \A \sd0_data0__pad__i connect \B \io_bd [69] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139049$5732_Y + connect \Y $ternary$libresoc.v:139048$5732_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139050$5733 + cell $mux $ternary$libresoc.v:139049$5733 parameter \WIDTH 1 connect \A \sd0_data0__core__o connect \B \io_bd [70] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139050$5733_Y + connect \Y $ternary$libresoc.v:139049$5733_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139051$5734 + cell $mux $ternary$libresoc.v:139050$5734 parameter \WIDTH 1 connect \A \sd0_data0__core__oe connect \B \io_bd [71] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139051$5734_Y + connect \Y $ternary$libresoc.v:139050$5734_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139052$5735 + cell $mux $ternary$libresoc.v:139051$5735 parameter \WIDTH 1 connect \A \sd0_data1__pad__i connect \B \io_bd [72] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139052$5735_Y + connect \Y $ternary$libresoc.v:139051$5735_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139053$5736 + cell $mux $ternary$libresoc.v:139052$5736 parameter \WIDTH 1 connect \A \sd0_data1__core__o connect \B \io_bd [73] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139053$5736_Y + connect \Y $ternary$libresoc.v:139052$5736_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139056$5739 + cell $mux $ternary$libresoc.v:139055$5739 parameter \WIDTH 1 connect \A \sd0_data1__core__oe connect \B \io_bd [74] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139056$5739_Y + connect \Y $ternary$libresoc.v:139055$5739_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139057$5740 + cell $mux $ternary$libresoc.v:139056$5740 parameter \WIDTH 1 connect \A \sd0_data2__pad__i connect \B \io_bd [75] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139057$5740_Y + connect \Y $ternary$libresoc.v:139056$5740_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139058$5741 + cell $mux $ternary$libresoc.v:139057$5741 parameter \WIDTH 1 connect \A \sd0_data2__core__o connect \B \io_bd [76] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139058$5741_Y + connect \Y $ternary$libresoc.v:139057$5741_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139059$5742 + cell $mux $ternary$libresoc.v:139058$5742 parameter \WIDTH 1 connect \A \sd0_data2__core__oe connect \B \io_bd [77] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139059$5742_Y + connect \Y $ternary$libresoc.v:139058$5742_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139060$5743 + cell $mux $ternary$libresoc.v:139059$5743 parameter \WIDTH 1 connect \A \sd0_data3__pad__i connect \B \io_bd [78] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139060$5743_Y + connect \Y $ternary$libresoc.v:139059$5743_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139061$5744 + cell $mux $ternary$libresoc.v:139060$5744 parameter \WIDTH 1 connect \A \sd0_data3__core__o connect \B \io_bd [79] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139061$5744_Y + connect \Y $ternary$libresoc.v:139060$5744_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139062$5745 + cell $mux $ternary$libresoc.v:139061$5745 parameter \WIDTH 1 connect \A \sd0_data3__core__oe connect \B \io_bd [80] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139062$5745_Y + connect \Y $ternary$libresoc.v:139061$5745_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139063$5746 + cell $mux $ternary$libresoc.v:139062$5746 parameter \WIDTH 1 connect \A \sdr_dm_0__core__o connect \B \io_bd [81] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139063$5746_Y + connect \Y $ternary$libresoc.v:139062$5746_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139064$5747 + cell $mux $ternary$libresoc.v:139063$5747 parameter \WIDTH 1 connect \A \sdr_dq_0__pad__i connect \B \io_bd [82] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139064$5747_Y + connect \Y $ternary$libresoc.v:139063$5747_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139065$5748 + cell $mux $ternary$libresoc.v:139064$5748 parameter \WIDTH 1 connect \A \sdr_dq_0__core__o connect \B \io_bd [83] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139065$5748_Y + connect \Y $ternary$libresoc.v:139064$5748_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139067$5750 + cell $mux $ternary$libresoc.v:139066$5750 parameter \WIDTH 1 connect \A \sdr_dq_0__core__oe connect \B \io_bd [84] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139067$5750_Y + connect \Y $ternary$libresoc.v:139066$5750_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139068$5751 + cell $mux $ternary$libresoc.v:139067$5751 parameter \WIDTH 1 connect \A \sdr_dq_1__pad__i connect \B \io_bd [85] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139068$5751_Y + connect \Y $ternary$libresoc.v:139067$5751_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139069$5752 + cell $mux $ternary$libresoc.v:139068$5752 parameter \WIDTH 1 connect \A \sdr_dq_1__core__o connect \B \io_bd [86] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139069$5752_Y + connect \Y $ternary$libresoc.v:139068$5752_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139070$5753 + cell $mux $ternary$libresoc.v:139069$5753 parameter \WIDTH 1 connect \A \sdr_dq_1__core__oe connect \B \io_bd [87] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139070$5753_Y + connect \Y $ternary$libresoc.v:139069$5753_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139071$5754 + cell $mux $ternary$libresoc.v:139070$5754 parameter \WIDTH 1 connect \A \sdr_dq_2__pad__i connect \B \io_bd [88] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139071$5754_Y + connect \Y $ternary$libresoc.v:139070$5754_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139072$5755 + cell $mux $ternary$libresoc.v:139071$5755 parameter \WIDTH 1 connect \A \sdr_dq_2__core__o connect \B \io_bd [89] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139072$5755_Y + connect \Y $ternary$libresoc.v:139071$5755_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139073$5756 + cell $mux $ternary$libresoc.v:139072$5756 parameter \WIDTH 1 connect \A \sdr_dq_2__core__oe connect \B \io_bd [90] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139073$5756_Y + connect \Y $ternary$libresoc.v:139072$5756_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139074$5757 + cell $mux $ternary$libresoc.v:139073$5757 parameter \WIDTH 1 connect \A \sdr_dq_3__pad__i connect \B \io_bd [91] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139074$5757_Y + connect \Y $ternary$libresoc.v:139073$5757_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139075$5758 + cell $mux $ternary$libresoc.v:139074$5758 parameter \WIDTH 1 connect \A \sdr_dq_3__core__o connect \B \io_bd [92] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139075$5758_Y + connect \Y $ternary$libresoc.v:139074$5758_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139076$5759 + cell $mux $ternary$libresoc.v:139075$5759 parameter \WIDTH 1 connect \A \sdr_dq_3__core__oe connect \B \io_bd [93] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139076$5759_Y + connect \Y $ternary$libresoc.v:139075$5759_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139078$5761 + cell $mux $ternary$libresoc.v:139077$5761 parameter \WIDTH 1 connect \A \sdr_dq_4__pad__i connect \B \io_bd [94] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139078$5761_Y + connect \Y $ternary$libresoc.v:139077$5761_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139079$5762 + cell $mux $ternary$libresoc.v:139078$5762 parameter \WIDTH 1 connect \A \sdr_dq_4__core__o connect \B \io_bd [95] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139079$5762_Y + connect \Y $ternary$libresoc.v:139078$5762_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139080$5763 + cell $mux $ternary$libresoc.v:139079$5763 parameter \WIDTH 1 connect \A \sdr_dq_4__core__oe connect \B \io_bd [96] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139080$5763_Y + connect \Y $ternary$libresoc.v:139079$5763_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139081$5764 + cell $mux $ternary$libresoc.v:139080$5764 parameter \WIDTH 1 connect \A \sdr_dq_5__pad__i connect \B \io_bd [97] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139081$5764_Y + connect \Y $ternary$libresoc.v:139080$5764_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139082$5765 + cell $mux $ternary$libresoc.v:139081$5765 parameter \WIDTH 1 connect \A \sdr_dq_5__core__o connect \B \io_bd [98] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139082$5765_Y + connect \Y $ternary$libresoc.v:139081$5765_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139083$5766 + cell $mux $ternary$libresoc.v:139082$5766 parameter \WIDTH 1 connect \A \sdr_dq_5__core__oe connect \B \io_bd [99] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139083$5766_Y + connect \Y $ternary$libresoc.v:139082$5766_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139084$5767 + cell $mux $ternary$libresoc.v:139083$5767 parameter \WIDTH 1 connect \A \sdr_dq_6__pad__i connect \B \io_bd [100] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139084$5767_Y + connect \Y $ternary$libresoc.v:139083$5767_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139085$5768 + cell $mux $ternary$libresoc.v:139084$5768 parameter \WIDTH 1 connect \A \sdr_dq_6__core__o connect \B \io_bd [101] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139085$5768_Y + connect \Y $ternary$libresoc.v:139084$5768_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139086$5769 + cell $mux $ternary$libresoc.v:139085$5769 parameter \WIDTH 1 connect \A \sdr_dq_6__core__oe connect \B \io_bd [102] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139086$5769_Y + connect \Y $ternary$libresoc.v:139085$5769_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139087$5770 + cell $mux $ternary$libresoc.v:139086$5770 parameter \WIDTH 1 connect \A \sdr_dq_7__pad__i connect \B \io_bd [103] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139087$5770_Y + connect \Y $ternary$libresoc.v:139086$5770_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139089$5772 + cell $mux $ternary$libresoc.v:139088$5772 parameter \WIDTH 1 connect \A \sdr_dq_7__core__o connect \B \io_bd [104] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139089$5772_Y + connect \Y $ternary$libresoc.v:139088$5772_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139090$5773 + cell $mux $ternary$libresoc.v:139089$5773 parameter \WIDTH 1 connect \A \sdr_dq_7__core__oe connect \B \io_bd [105] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139090$5773_Y + connect \Y $ternary$libresoc.v:139089$5773_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139091$5774 + cell $mux $ternary$libresoc.v:139090$5774 parameter \WIDTH 1 connect \A \sdr_a_0__core__o connect \B \io_bd [106] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139091$5774_Y + connect \Y $ternary$libresoc.v:139090$5774_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139092$5775 + cell $mux $ternary$libresoc.v:139091$5775 parameter \WIDTH 1 connect \A \sdr_a_1__core__o connect \B \io_bd [107] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139092$5775_Y + connect \Y $ternary$libresoc.v:139091$5775_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139093$5776 + cell $mux $ternary$libresoc.v:139092$5776 parameter \WIDTH 1 connect \A \sdr_a_2__core__o connect \B \io_bd [108] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139093$5776_Y + connect \Y $ternary$libresoc.v:139092$5776_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139094$5777 + cell $mux $ternary$libresoc.v:139093$5777 parameter \WIDTH 1 connect \A \sdr_a_3__core__o connect \B \io_bd [109] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139094$5777_Y + connect \Y $ternary$libresoc.v:139093$5777_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139095$5778 + cell $mux $ternary$libresoc.v:139094$5778 parameter \WIDTH 1 connect \A \sdr_a_4__core__o connect \B \io_bd [110] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139095$5778_Y + connect \Y $ternary$libresoc.v:139094$5778_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139096$5779 + cell $mux $ternary$libresoc.v:139095$5779 parameter \WIDTH 1 connect \A \sdr_a_5__core__o connect \B \io_bd [111] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139096$5779_Y + connect \Y $ternary$libresoc.v:139095$5779_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139097$5780 + cell $mux $ternary$libresoc.v:139096$5780 parameter \WIDTH 1 connect \A \sdr_a_6__core__o connect \B \io_bd [112] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139097$5780_Y + connect \Y $ternary$libresoc.v:139096$5780_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139098$5781 + cell $mux $ternary$libresoc.v:139097$5781 parameter \WIDTH 1 connect \A \sdr_a_7__core__o connect \B \io_bd [113] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139098$5781_Y + connect \Y $ternary$libresoc.v:139097$5781_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139100$5783 + cell $mux $ternary$libresoc.v:139099$5783 parameter \WIDTH 1 connect \A \sdr_a_8__core__o connect \B \io_bd [114] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139100$5783_Y + connect \Y $ternary$libresoc.v:139099$5783_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139101$5784 + cell $mux $ternary$libresoc.v:139100$5784 parameter \WIDTH 1 connect \A \sdr_a_9__core__o connect \B \io_bd [115] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139101$5784_Y + connect \Y $ternary$libresoc.v:139100$5784_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139102$5785 + cell $mux $ternary$libresoc.v:139101$5785 parameter \WIDTH 1 connect \A \sdr_ba_0__core__o connect \B \io_bd [116] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139102$5785_Y + connect \Y $ternary$libresoc.v:139101$5785_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139103$5786 + cell $mux $ternary$libresoc.v:139102$5786 parameter \WIDTH 1 connect \A \sdr_ba_1__core__o connect \B \io_bd [117] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139103$5786_Y + connect \Y $ternary$libresoc.v:139102$5786_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139104$5787 + cell $mux $ternary$libresoc.v:139103$5787 parameter \WIDTH 1 connect \A \sdr_clock__core__o connect \B \io_bd [118] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139104$5787_Y + connect \Y $ternary$libresoc.v:139103$5787_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139105$5788 + cell $mux $ternary$libresoc.v:139104$5788 parameter \WIDTH 1 connect \A \sdr_cke__core__o connect \B \io_bd [119] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139105$5788_Y + connect \Y $ternary$libresoc.v:139104$5788_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139106$5789 + cell $mux $ternary$libresoc.v:139105$5789 parameter \WIDTH 1 connect \A \sdr_ras_n__core__o connect \B \io_bd [120] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139106$5789_Y + connect \Y $ternary$libresoc.v:139105$5789_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139107$5790 + cell $mux $ternary$libresoc.v:139106$5790 parameter \WIDTH 1 connect \A \sdr_cas_n__core__o connect \B \io_bd [121] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139107$5790_Y + connect \Y $ternary$libresoc.v:139106$5790_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139108$5791 + cell $mux $ternary$libresoc.v:139107$5791 parameter \WIDTH 1 connect \A \sdr_we_n__core__o connect \B \io_bd [122] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139108$5791_Y + connect \Y $ternary$libresoc.v:139107$5791_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139109$5792 + cell $mux $ternary$libresoc.v:139108$5792 parameter \WIDTH 1 connect \A \sdr_cs_n__core__o connect \B \io_bd [123] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139109$5792_Y + connect \Y $ternary$libresoc.v:139108$5792_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139111$5794 + cell $mux $ternary$libresoc.v:139110$5794 parameter \WIDTH 1 connect \A \sdr_a_10__core__o connect \B \io_bd [124] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139111$5794_Y + connect \Y $ternary$libresoc.v:139110$5794_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139112$5795 + cell $mux $ternary$libresoc.v:139111$5795 parameter \WIDTH 1 connect \A \sdr_a_11__core__o connect \B \io_bd [125] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139112$5795_Y + connect \Y $ternary$libresoc.v:139111$5795_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139113$5796 + cell $mux $ternary$libresoc.v:139112$5796 parameter \WIDTH 1 connect \A \sdr_a_12__core__o connect \B \io_bd [126] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139113$5796_Y + connect \Y $ternary$libresoc.v:139112$5796_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139114$5797 + cell $mux $ternary$libresoc.v:139113$5797 parameter \WIDTH 1 connect \A \sdr_dm_1__core__o connect \B \io_bd [127] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139114$5797_Y + connect \Y $ternary$libresoc.v:139113$5797_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139115$5798 + cell $mux $ternary$libresoc.v:139114$5798 parameter \WIDTH 1 connect \A \sdr_dq_8__pad__i connect \B \io_bd [128] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139115$5798_Y + connect \Y $ternary$libresoc.v:139114$5798_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139116$5799 + cell $mux $ternary$libresoc.v:139115$5799 parameter \WIDTH 1 connect \A \sdr_dq_8__core__o connect \B \io_bd [129] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139116$5799_Y + connect \Y $ternary$libresoc.v:139115$5799_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139117$5800 + cell $mux $ternary$libresoc.v:139116$5800 parameter \WIDTH 1 connect \A \sdr_dq_8__core__oe connect \B \io_bd [130] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139117$5800_Y + connect \Y $ternary$libresoc.v:139116$5800_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139118$5801 + cell $mux $ternary$libresoc.v:139117$5801 parameter \WIDTH 1 connect \A \sdr_dq_9__pad__i connect \B \io_bd [131] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139118$5801_Y + connect \Y $ternary$libresoc.v:139117$5801_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139119$5802 + cell $mux $ternary$libresoc.v:139118$5802 parameter \WIDTH 1 connect \A \sdr_dq_9__core__o connect \B \io_bd [132] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139119$5802_Y + connect \Y $ternary$libresoc.v:139118$5802_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139120$5803 + cell $mux $ternary$libresoc.v:139119$5803 parameter \WIDTH 1 connect \A \sdr_dq_9__core__oe connect \B \io_bd [133] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139120$5803_Y + connect \Y $ternary$libresoc.v:139119$5803_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139122$5805 + cell $mux $ternary$libresoc.v:139121$5805 parameter \WIDTH 1 connect \A \sdr_dq_10__pad__i connect \B \io_bd [134] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139122$5805_Y + connect \Y $ternary$libresoc.v:139121$5805_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139123$5806 + cell $mux $ternary$libresoc.v:139122$5806 parameter \WIDTH 1 connect \A \sdr_dq_10__core__o connect \B \io_bd [135] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139123$5806_Y + connect \Y $ternary$libresoc.v:139122$5806_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139124$5807 + cell $mux $ternary$libresoc.v:139123$5807 parameter \WIDTH 1 connect \A \sdr_dq_10__core__oe connect \B \io_bd [136] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139124$5807_Y + connect \Y $ternary$libresoc.v:139123$5807_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139125$5808 + cell $mux $ternary$libresoc.v:139124$5808 parameter \WIDTH 1 connect \A \sdr_dq_11__pad__i connect \B \io_bd [137] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139125$5808_Y + connect \Y $ternary$libresoc.v:139124$5808_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139126$5809 + cell $mux $ternary$libresoc.v:139125$5809 parameter \WIDTH 1 connect \A \sdr_dq_11__core__o connect \B \io_bd [138] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139126$5809_Y + connect \Y $ternary$libresoc.v:139125$5809_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139127$5810 + cell $mux $ternary$libresoc.v:139126$5810 parameter \WIDTH 1 connect \A \sdr_dq_11__core__oe connect \B \io_bd [139] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139127$5810_Y + connect \Y $ternary$libresoc.v:139126$5810_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139128$5811 + cell $mux $ternary$libresoc.v:139127$5811 parameter \WIDTH 1 connect \A \sdr_dq_12__pad__i connect \B \io_bd [140] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139128$5811_Y + connect \Y $ternary$libresoc.v:139127$5811_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139129$5812 + cell $mux $ternary$libresoc.v:139128$5812 parameter \WIDTH 1 connect \A \sdr_dq_12__core__o connect \B \io_bd [141] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139129$5812_Y + connect \Y $ternary$libresoc.v:139128$5812_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139130$5813 + cell $mux $ternary$libresoc.v:139129$5813 parameter \WIDTH 1 connect \A \sdr_dq_12__core__oe connect \B \io_bd [142] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139130$5813_Y + connect \Y $ternary$libresoc.v:139129$5813_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139131$5814 + cell $mux $ternary$libresoc.v:139130$5814 parameter \WIDTH 1 connect \A \sdr_dq_13__pad__i connect \B \io_bd [143] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139131$5814_Y + connect \Y $ternary$libresoc.v:139130$5814_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139133$5816 + cell $mux $ternary$libresoc.v:139132$5816 parameter \WIDTH 1 connect \A \sdr_dq_13__core__o connect \B \io_bd [144] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139133$5816_Y + connect \Y $ternary$libresoc.v:139132$5816_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139134$5817 + cell $mux $ternary$libresoc.v:139133$5817 parameter \WIDTH 1 connect \A \sdr_dq_13__core__oe connect \B \io_bd [145] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139134$5817_Y + connect \Y $ternary$libresoc.v:139133$5817_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139135$5818 + cell $mux $ternary$libresoc.v:139134$5818 parameter \WIDTH 1 connect \A \sdr_dq_14__pad__i connect \B \io_bd [146] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139135$5818_Y + connect \Y $ternary$libresoc.v:139134$5818_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139136$5819 + cell $mux $ternary$libresoc.v:139135$5819 parameter \WIDTH 1 connect \A \sdr_dq_14__core__o connect \B \io_bd [147] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139136$5819_Y + connect \Y $ternary$libresoc.v:139135$5819_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139137$5820 + cell $mux $ternary$libresoc.v:139136$5820 parameter \WIDTH 1 connect \A \sdr_dq_14__core__oe connect \B \io_bd [148] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139137$5820_Y + connect \Y $ternary$libresoc.v:139136$5820_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139138$5821 + cell $mux $ternary$libresoc.v:139137$5821 parameter \WIDTH 1 connect \A \sdr_dq_15__pad__i connect \B \io_bd [149] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139138$5821_Y + connect \Y $ternary$libresoc.v:139137$5821_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139139$5822 + cell $mux $ternary$libresoc.v:139138$5822 parameter \WIDTH 1 connect \A \sdr_dq_15__core__o connect \B \io_bd [150] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139139$5822_Y + connect \Y $ternary$libresoc.v:139138$5822_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139140$5823 + cell $mux $ternary$libresoc.v:139139$5823 parameter \WIDTH 1 connect \A \sdr_dq_15__core__oe connect \B \io_bd [151] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139140$5823_Y + connect \Y $ternary$libresoc.v:139139$5823_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139227$5911 + cell $mux $ternary$libresoc.v:139226$5911 parameter \WIDTH 1 connect \A \eint_0__pad__i connect \B \io_bd [0] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139227$5911_Y + connect \Y $ternary$libresoc.v:139226$5911_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139228$5912 + cell $mux $ternary$libresoc.v:139227$5912 parameter \WIDTH 1 connect \A \eint_1__pad__i connect \B \io_bd [1] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139228$5912_Y + connect \Y $ternary$libresoc.v:139227$5912_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139229$5913 + cell $mux $ternary$libresoc.v:139228$5913 parameter \WIDTH 1 connect \A \eint_2__pad__i connect \B \io_bd [2] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139229$5913_Y + connect \Y $ternary$libresoc.v:139228$5913_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139230$5914 + cell $mux $ternary$libresoc.v:139229$5914 parameter \WIDTH 1 connect \A \gpio_e8__pad__i connect \B \io_bd [3] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139230$5914_Y + connect \Y $ternary$libresoc.v:139229$5914_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139232$5916 + cell $mux $ternary$libresoc.v:139231$5916 parameter \WIDTH 1 connect \A \gpio_e8__core__o connect \B \io_bd [4] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139232$5916_Y + connect \Y $ternary$libresoc.v:139231$5916_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139233$5917 + cell $mux $ternary$libresoc.v:139232$5917 parameter \WIDTH 1 connect \A \gpio_e8__core__oe connect \B \io_bd [5] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139233$5917_Y + connect \Y $ternary$libresoc.v:139232$5917_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139234$5918 + cell $mux $ternary$libresoc.v:139233$5918 parameter \WIDTH 1 connect \A \gpio_e9__pad__i connect \B \io_bd [6] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139234$5918_Y + connect \Y $ternary$libresoc.v:139233$5918_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139235$5919 + cell $mux $ternary$libresoc.v:139234$5919 parameter \WIDTH 1 connect \A \gpio_e9__core__o connect \B \io_bd [7] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139235$5919_Y + connect \Y $ternary$libresoc.v:139234$5919_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139236$5920 + cell $mux $ternary$libresoc.v:139235$5920 parameter \WIDTH 1 connect \A \gpio_e9__core__oe connect \B \io_bd [8] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139236$5920_Y + connect \Y $ternary$libresoc.v:139235$5920_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139237$5921 + cell $mux $ternary$libresoc.v:139236$5921 parameter \WIDTH 1 connect \A \gpio_e10__pad__i connect \B \io_bd [9] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139237$5921_Y + connect \Y $ternary$libresoc.v:139236$5921_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139238$5922 + cell $mux $ternary$libresoc.v:139237$5922 parameter \WIDTH 1 connect \A \gpio_e10__core__o connect \B \io_bd [10] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139238$5922_Y + connect \Y $ternary$libresoc.v:139237$5922_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139239$5923 + cell $mux $ternary$libresoc.v:139238$5923 parameter \WIDTH 1 connect \A \gpio_e10__core__oe connect \B \io_bd [11] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139239$5923_Y + connect \Y $ternary$libresoc.v:139238$5923_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139240$5924 + cell $mux $ternary$libresoc.v:139239$5924 parameter \WIDTH 1 connect \A \gpio_e11__pad__i connect \B \io_bd [12] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139240$5924_Y + connect \Y $ternary$libresoc.v:139239$5924_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139241$5925 + cell $mux $ternary$libresoc.v:139240$5925 parameter \WIDTH 1 connect \A \gpio_e11__core__o connect \B \io_bd [13] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139241$5925_Y + connect \Y $ternary$libresoc.v:139240$5925_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139243$5927 + cell $mux $ternary$libresoc.v:139242$5927 parameter \WIDTH 1 connect \A \gpio_e11__core__oe connect \B \io_bd [14] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139243$5927_Y + connect \Y $ternary$libresoc.v:139242$5927_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139244$5928 + cell $mux $ternary$libresoc.v:139243$5928 parameter \WIDTH 1 connect \A \gpio_e12__pad__i connect \B \io_bd [15] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139244$5928_Y + connect \Y $ternary$libresoc.v:139243$5928_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139245$5929 + cell $mux $ternary$libresoc.v:139244$5929 parameter \WIDTH 1 connect \A \gpio_e12__core__o connect \B \io_bd [16] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139245$5929_Y + connect \Y $ternary$libresoc.v:139244$5929_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139246$5930 + cell $mux $ternary$libresoc.v:139245$5930 parameter \WIDTH 1 connect \A \gpio_e12__core__oe connect \B \io_bd [17] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139246$5930_Y + connect \Y $ternary$libresoc.v:139245$5930_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139247$5931 + cell $mux $ternary$libresoc.v:139246$5931 parameter \WIDTH 1 connect \A \gpio_e13__pad__i connect \B \io_bd [18] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139247$5931_Y + connect \Y $ternary$libresoc.v:139246$5931_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139248$5932 + cell $mux $ternary$libresoc.v:139247$5932 parameter \WIDTH 1 connect \A \gpio_e13__core__o connect \B \io_bd [19] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139248$5932_Y + connect \Y $ternary$libresoc.v:139247$5932_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139249$5933 + cell $mux $ternary$libresoc.v:139248$5933 parameter \WIDTH 1 connect \A \gpio_e13__core__oe connect \B \io_bd [20] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139249$5933_Y + connect \Y $ternary$libresoc.v:139248$5933_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139250$5934 + cell $mux $ternary$libresoc.v:139249$5934 parameter \WIDTH 1 connect \A \gpio_e14__pad__i connect \B \io_bd [21] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139250$5934_Y + connect \Y $ternary$libresoc.v:139249$5934_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139251$5935 + cell $mux $ternary$libresoc.v:139250$5935 parameter \WIDTH 1 connect \A \gpio_e14__core__o connect \B \io_bd [22] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139251$5935_Y + connect \Y $ternary$libresoc.v:139250$5935_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139252$5936 + cell $mux $ternary$libresoc.v:139251$5936 parameter \WIDTH 1 connect \A \gpio_e14__core__oe connect \B \io_bd [23] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139252$5936_Y + connect \Y $ternary$libresoc.v:139251$5936_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:139327.8-139339.4" + attribute \src "libresoc.v:139326.8-139338.4" cell \_fsm \_fsm connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tms \TAP_bus__tms @@ -222176,7 +222176,7 @@ module \jtag connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:139340.12-139350.4" + attribute \src "libresoc.v:139339.12-139349.4" cell \_idblock \_idblock connect \TAP_bus__tdi \TAP_bus__tdi connect \TAP_id_tdo \_idblock_TAP_id_tdo @@ -222189,7 +222189,7 @@ module \jtag connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:139351.12-139361.4" + attribute \src "libresoc.v:139350.12-139360.4" cell \_irblock \_irblock connect \TAP_bus__tdi \TAP_bus__tdi connect \capture \_fsm_capture @@ -222497,281 +222497,281 @@ module \jtag sync init update \wb_icache_en $1\wb_icache_en[0:0] end - attribute \src "libresoc.v:138996.7-138996.24" - process $proc$libresoc.v:138996$6170 + attribute \src "libresoc.v:138995.7-138995.24" + process $proc$libresoc.v:138995$6170 assign { } { } assign $1\wb_sram_en[0:0] 1'1 sync always sync init update \wb_sram_en $1\wb_sram_en[0:0] end - attribute \src "libresoc.v:139253.3-139254.41" - process $proc$libresoc.v:139253$5937 + attribute \src "libresoc.v:139252.3-139253.41" + process $proc$libresoc.v:139252$5937 assign { } { } assign $0\wb_icache_en[0:0] \wb_icache_en$next sync posedge \clk update \wb_icache_en $0\wb_icache_en[0:0] end - attribute \src "libresoc.v:139255.3-139256.41" - process $proc$libresoc.v:139255$5938 + attribute \src "libresoc.v:139254.3-139255.41" + process $proc$libresoc.v:139254$5938 assign { } { } assign $0\wb_dcache_en[0:0] \wb_dcache_en$next sync posedge \clk update \wb_dcache_en $0\wb_dcache_en[0:0] end - attribute \src "libresoc.v:139257.3-139258.37" - process $proc$libresoc.v:139257$5939 + attribute \src "libresoc.v:139256.3-139257.37" + process $proc$libresoc.v:139256$5939 assign { } { } assign $0\wb_sram_en[0:0] \wb_sram_en$next sync posedge \clk update \wb_sram_en $0\wb_sram_en[0:0] end - attribute \src "libresoc.v:139259.3-139260.45" - process $proc$libresoc.v:139259$5940 + attribute \src "libresoc.v:139258.3-139259.45" + process $proc$libresoc.v:139258$5940 assign { } { } assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next sync posedge \clk update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:139261.3-139262.35" - process $proc$libresoc.v:139261$5941 + attribute \src "libresoc.v:139260.3-139261.35" + process $proc$libresoc.v:139260$5941 assign { } { } assign $0\dmi0__din[63:0] \dmi0__din$next sync posedge \clk update \dmi0__din $0\dmi0__din[63:0] end - attribute \src "libresoc.v:139263.3-139264.45" - process $proc$libresoc.v:139263$5942 + attribute \src "libresoc.v:139262.3-139263.45" + process $proc$libresoc.v:139262$5942 assign { } { } assign $0\fsm_state$499[2:0]$5943 \fsm_state$499$next sync posedge \clk update \fsm_state$499 $0\fsm_state$499[2:0]$5943 end - attribute \src "libresoc.v:139265.3-139266.41" - process $proc$libresoc.v:139265$5944 + attribute \src "libresoc.v:139264.3-139265.41" + process $proc$libresoc.v:139264$5944 assign { } { } assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next sync posedge \clk update \dmi0__addr_i $0\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:139267.3-139268.51" - process $proc$libresoc.v:139267$5945 + attribute \src "libresoc.v:139266.3-139267.51" + process $proc$libresoc.v:139266$5945 assign { } { } assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next sync posedge \clk update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:139269.3-139270.45" - process $proc$libresoc.v:139269$5946 + attribute \src "libresoc.v:139268.3-139269.45" + process $proc$libresoc.v:139268$5946 assign { } { } assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next sync posedge \clk update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:139271.3-139272.35" - process $proc$libresoc.v:139271$5947 + attribute \src "libresoc.v:139270.3-139271.35" + process $proc$libresoc.v:139270$5947 assign { } { } assign $0\fsm_state[2:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[2:0] end - attribute \src "libresoc.v:139273.3-139274.41" - process $proc$libresoc.v:139273$5948 + attribute \src "libresoc.v:139272.3-139273.41" + process $proc$libresoc.v:139272$5948 assign { } { } assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next sync posedge \clk update \jtag_wb__adr $0\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:139275.3-139276.31" - process $proc$libresoc.v:139275$5949 + attribute \src "libresoc.v:139274.3-139275.31" + process $proc$libresoc.v:139274$5949 assign { } { } assign $0\sr5_reg[2:0] \sr5_reg$next sync posedge \posjtag_clk update \sr5_reg $0\sr5_reg[2:0] end - attribute \src "libresoc.v:139277.3-139278.31" - process $proc$libresoc.v:139277$5950 + attribute \src "libresoc.v:139276.3-139277.31" + process $proc$libresoc.v:139276$5950 assign { } { } assign $0\sr5__oe[0:0] \sr5__oe$next sync posedge \clk update \sr5__oe $0\sr5__oe[0:0] end - attribute \src "libresoc.v:139279.3-139280.57" - process $proc$libresoc.v:139279$5951 + attribute \src "libresoc.v:139278.3-139279.57" + process $proc$libresoc.v:139278$5951 assign { } { } assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next sync posedge \clk update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] end - attribute \src "libresoc.v:139281.3-139282.47" - process $proc$libresoc.v:139281$5952 + attribute \src "libresoc.v:139280.3-139281.47" + process $proc$libresoc.v:139280$5952 assign { } { } assign $0\sr5_update_core[0:0] \sr5_update_core$next sync posedge \clk update \sr5_update_core $0\sr5_update_core[0:0] end - attribute \src "libresoc.v:139283.3-139284.47" - process $proc$libresoc.v:139283$5953 + attribute \src "libresoc.v:139282.3-139283.47" + process $proc$libresoc.v:139282$5953 assign { } { } assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next sync posedge \posjtag_clk update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:139285.3-139286.47" - process $proc$libresoc.v:139285$5954 + attribute \src "libresoc.v:139284.3-139285.47" + process $proc$libresoc.v:139284$5954 assign { } { } assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next sync posedge \clk update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:139287.3-139288.73" - process $proc$libresoc.v:139287$5955 + attribute \src "libresoc.v:139286.3-139287.73" + process $proc$libresoc.v:139286$5955 assign { } { } assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next sync posedge \clk update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:139289.3-139290.63" - process $proc$libresoc.v:139289$5956 + attribute \src "libresoc.v:139288.3-139289.63" + process $proc$libresoc.v:139288$5956 assign { } { } assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next sync posedge \clk update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:139291.3-139292.47" - process $proc$libresoc.v:139291$5957 + attribute \src "libresoc.v:139290.3-139291.47" + process $proc$libresoc.v:139290$5957 assign { } { } assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next sync posedge \posjtag_clk update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:139293.3-139294.47" - process $proc$libresoc.v:139293$5958 + attribute \src "libresoc.v:139292.3-139293.47" + process $proc$libresoc.v:139292$5958 assign { } { } assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next sync posedge \clk update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:139295.3-139296.73" - process $proc$libresoc.v:139295$5959 + attribute \src "libresoc.v:139294.3-139295.73" + process $proc$libresoc.v:139294$5959 assign { } { } assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next sync posedge \clk update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:139297.3-139298.63" - process $proc$libresoc.v:139297$5960 + attribute \src "libresoc.v:139296.3-139297.63" + process $proc$libresoc.v:139296$5960 assign { } { } assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next sync posedge \clk update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:139299.3-139300.53" - process $proc$libresoc.v:139299$5961 + attribute \src "libresoc.v:139298.3-139299.53" + process $proc$libresoc.v:139298$5961 assign { } { } assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next sync posedge \posjtag_clk update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] end - attribute \src "libresoc.v:139301.3-139302.53" - process $proc$libresoc.v:139301$5962 + attribute \src "libresoc.v:139300.3-139301.53" + process $proc$libresoc.v:139300$5962 assign { } { } assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next sync posedge \clk update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:139303.3-139304.79" - process $proc$libresoc.v:139303$5963 + attribute \src "libresoc.v:139302.3-139303.79" + process $proc$libresoc.v:139302$5963 assign { } { } assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next sync posedge \clk update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:139305.3-139306.69" - process $proc$libresoc.v:139305$5964 + attribute \src "libresoc.v:139304.3-139305.69" + process $proc$libresoc.v:139304$5964 assign { } { } assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next sync posedge \clk update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:139307.3-139308.53" - process $proc$libresoc.v:139307$5965 + attribute \src "libresoc.v:139306.3-139307.53" + process $proc$libresoc.v:139306$5965 assign { } { } assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next sync posedge \posjtag_clk update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:139309.3-139310.53" - process $proc$libresoc.v:139309$5966 + attribute \src "libresoc.v:139308.3-139309.53" + process $proc$libresoc.v:139308$5966 assign { } { } assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next sync posedge \clk update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:139311.3-139312.79" - process $proc$libresoc.v:139311$5967 + attribute \src "libresoc.v:139310.3-139311.79" + process $proc$libresoc.v:139310$5967 assign { } { } assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next sync posedge \clk update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:139313.3-139314.69" - process $proc$libresoc.v:139313$5968 + attribute \src "libresoc.v:139312.3-139313.69" + process $proc$libresoc.v:139312$5968 assign { } { } assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next sync posedge \clk update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:139315.3-139316.31" - process $proc$libresoc.v:139315$5969 + attribute \src "libresoc.v:139314.3-139315.31" + process $proc$libresoc.v:139314$5969 assign { } { } assign $0\sr0_reg[2:0] \sr0_reg$next sync posedge \posjtag_clk update \sr0_reg $0\sr0_reg[2:0] end - attribute \src "libresoc.v:139317.3-139318.31" - process $proc$libresoc.v:139317$5970 + attribute \src "libresoc.v:139316.3-139317.31" + process $proc$libresoc.v:139316$5970 assign { } { } assign $0\sr0__oe[0:0] \sr0__oe$next sync posedge \clk update \sr0__oe $0\sr0__oe[0:0] end - attribute \src "libresoc.v:139319.3-139320.57" - process $proc$libresoc.v:139319$5971 + attribute \src "libresoc.v:139318.3-139319.57" + process $proc$libresoc.v:139318$5971 assign { } { } assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next sync posedge \clk update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:139321.3-139322.47" - process $proc$libresoc.v:139321$5972 + attribute \src "libresoc.v:139320.3-139321.47" + process $proc$libresoc.v:139320$5972 assign { } { } assign $0\sr0_update_core[0:0] \sr0_update_core$next sync posedge \clk update \sr0_update_core $0\sr0_update_core[0:0] end - attribute \src "libresoc.v:139323.3-139324.27" - process $proc$libresoc.v:139323$5973 + attribute \src "libresoc.v:139322.3-139323.27" + process $proc$libresoc.v:139322$5973 assign { } { } assign $0\io_bd[151:0] \io_bd$next sync negedge \negjtag_clk update \io_bd $0\io_bd[151:0] end - attribute \src "libresoc.v:139325.3-139326.27" - process $proc$libresoc.v:139325$5974 + attribute \src "libresoc.v:139324.3-139325.27" + process $proc$libresoc.v:139324$5974 assign { } { } assign $0\io_sr[151:0] \io_sr$next sync posedge \posjtag_clk update \io_sr $0\io_sr[151:0] end - attribute \src "libresoc.v:139362.3-139377.6" - process $proc$libresoc.v:139362$5975 + attribute \src "libresoc.v:139361.3-139376.6" + process $proc$libresoc.v:139361$5975 assign { } { } assign { } { } assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] - attribute \src "libresoc.v:139363.5-139363.29" + attribute \src "libresoc.v:139362.5-139362.29" switch \initial - attribute \src "libresoc.v:139363.9-139363.17" + attribute \src "libresoc.v:139362.9-139362.17" case 1'1 case end @@ -222795,14 +222795,14 @@ module \jtag sync always update \TAP_tdo $0\TAP_tdo[0:0] end - attribute \src "libresoc.v:139378.3-139386.6" - process $proc$libresoc.v:139378$5976 + attribute \src "libresoc.v:139377.3-139385.6" + process $proc$libresoc.v:139377$5976 assign { } { } assign { } { } assign $0\sr0_update_core$next[0:0]$5977 $1\sr0_update_core$next[0:0]$5978 - attribute \src "libresoc.v:139379.5-139379.29" + attribute \src "libresoc.v:139378.5-139378.29" switch \initial - attribute \src "libresoc.v:139379.9-139379.17" + attribute \src "libresoc.v:139378.9-139378.17" case 1'1 case end @@ -222818,14 +222818,14 @@ module \jtag sync always update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5977 end - attribute \src "libresoc.v:139387.3-139395.6" - process $proc$libresoc.v:139387$5979 + attribute \src "libresoc.v:139386.3-139394.6" + process $proc$libresoc.v:139386$5979 assign { } { } assign { } { } assign $0\sr0_update_core_prev$next[0:0]$5980 $1\sr0_update_core_prev$next[0:0]$5981 - attribute \src "libresoc.v:139388.5-139388.29" + attribute \src "libresoc.v:139387.5-139387.29" switch \initial - attribute \src "libresoc.v:139388.9-139388.17" + attribute \src "libresoc.v:139387.9-139387.17" case 1'1 case end @@ -222841,14 +222841,14 @@ module \jtag sync always update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5980 end - attribute \src "libresoc.v:139396.3-139412.6" - process $proc$libresoc.v:139396$5982 + attribute \src "libresoc.v:139395.3-139411.6" + process $proc$libresoc.v:139395$5982 assign { } { } assign { } { } assign $0\sr0__oe$next[0:0]$5983 $2\sr0__oe$next[0:0]$5985 - attribute \src "libresoc.v:139397.5-139397.29" + attribute \src "libresoc.v:139396.5-139396.29" switch \initial - attribute \src "libresoc.v:139397.9-139397.17" + attribute \src "libresoc.v:139396.9-139396.17" case 1'1 case end @@ -222875,16 +222875,16 @@ module \jtag sync always update \sr0__oe$next $0\sr0__oe$next[0:0]$5983 end - attribute \src "libresoc.v:139413.3-139433.6" - process $proc$libresoc.v:139413$5986 + attribute \src "libresoc.v:139412.3-139432.6" + process $proc$libresoc.v:139412$5986 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sr0_reg$next[2:0]$5987 $3\sr0_reg$next[2:0]$5990 - attribute \src "libresoc.v:139414.5-139414.29" + attribute \src "libresoc.v:139413.5-139413.29" switch \initial - attribute \src "libresoc.v:139414.9-139414.17" + attribute \src "libresoc.v:139413.9-139413.17" case 1'1 case end @@ -222918,14 +222918,14 @@ module \jtag sync always update \sr0_reg$next $0\sr0_reg$next[2:0]$5987 end - attribute \src "libresoc.v:139434.3-139442.6" - process $proc$libresoc.v:139434$5991 + attribute \src "libresoc.v:139433.3-139441.6" + process $proc$libresoc.v:139433$5991 assign { } { } assign { } { } assign $0\jtag_wb_addrsr_update_core$next[0:0]$5992 $1\jtag_wb_addrsr_update_core$next[0:0]$5993 - attribute \src "libresoc.v:139435.5-139435.29" + attribute \src "libresoc.v:139434.5-139434.29" switch \initial - attribute \src "libresoc.v:139435.9-139435.17" + attribute \src "libresoc.v:139434.9-139434.17" case 1'1 case end @@ -222941,14 +222941,14 @@ module \jtag sync always update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5992 end - attribute \src "libresoc.v:139443.3-139451.6" - process $proc$libresoc.v:139443$5994 + attribute \src "libresoc.v:139442.3-139450.6" + process $proc$libresoc.v:139442$5994 assign { } { } assign { } { } assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 - attribute \src "libresoc.v:139444.5-139444.29" + attribute \src "libresoc.v:139443.5-139443.29" switch \initial - attribute \src "libresoc.v:139444.9-139444.17" + attribute \src "libresoc.v:139443.9-139443.17" case 1'1 case end @@ -222964,14 +222964,14 @@ module \jtag sync always update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 end - attribute \src "libresoc.v:139452.3-139468.6" - process $proc$libresoc.v:139452$5997 + attribute \src "libresoc.v:139451.3-139467.6" + process $proc$libresoc.v:139451$5997 assign { } { } assign { } { } assign $0\jtag_wb_addrsr__oe$next[0:0]$5998 $2\jtag_wb_addrsr__oe$next[0:0]$6000 - attribute \src "libresoc.v:139453.5-139453.29" + attribute \src "libresoc.v:139452.5-139452.29" switch \initial - attribute \src "libresoc.v:139453.9-139453.17" + attribute \src "libresoc.v:139452.9-139452.17" case 1'1 case end @@ -222998,16 +222998,16 @@ module \jtag sync always update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5998 end - attribute \src "libresoc.v:139469.3-139489.6" - process $proc$libresoc.v:139469$6001 + attribute \src "libresoc.v:139468.3-139488.6" + process $proc$libresoc.v:139468$6001 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\jtag_wb_addrsr_reg$next[28:0]$6002 $3\jtag_wb_addrsr_reg$next[28:0]$6005 - attribute \src "libresoc.v:139470.5-139470.29" + attribute \src "libresoc.v:139469.5-139469.29" switch \initial - attribute \src "libresoc.v:139470.9-139470.17" + attribute \src "libresoc.v:139469.9-139469.17" case 1'1 case end @@ -223041,14 +223041,14 @@ module \jtag sync always update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$6002 end - attribute \src "libresoc.v:139490.3-139498.6" - process $proc$libresoc.v:139490$6006 + attribute \src "libresoc.v:139489.3-139497.6" + process $proc$libresoc.v:139489$6006 assign { } { } assign { } { } assign $0\jtag_wb_datasr_update_core$next[0:0]$6007 $1\jtag_wb_datasr_update_core$next[0:0]$6008 - attribute \src "libresoc.v:139491.5-139491.29" + attribute \src "libresoc.v:139490.5-139490.29" switch \initial - attribute \src "libresoc.v:139491.9-139491.17" + attribute \src "libresoc.v:139490.9-139490.17" case 1'1 case end @@ -223064,14 +223064,14 @@ module \jtag sync always update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$6007 end - attribute \src "libresoc.v:139499.3-139507.6" - process $proc$libresoc.v:139499$6009 + attribute \src "libresoc.v:139498.3-139506.6" + process $proc$libresoc.v:139498$6009 assign { } { } assign { } { } assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 - attribute \src "libresoc.v:139500.5-139500.29" + attribute \src "libresoc.v:139499.5-139499.29" switch \initial - attribute \src "libresoc.v:139500.9-139500.17" + attribute \src "libresoc.v:139499.9-139499.17" case 1'1 case end @@ -223087,14 +223087,14 @@ module \jtag sync always update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 end - attribute \src "libresoc.v:139508.3-139524.6" - process $proc$libresoc.v:139508$6012 + attribute \src "libresoc.v:139507.3-139523.6" + process $proc$libresoc.v:139507$6012 assign { } { } assign { } { } assign $0\jtag_wb_datasr__oe$next[1:0]$6013 $2\jtag_wb_datasr__oe$next[1:0]$6015 - attribute \src "libresoc.v:139509.5-139509.29" + attribute \src "libresoc.v:139508.5-139508.29" switch \initial - attribute \src "libresoc.v:139509.9-139509.17" + attribute \src "libresoc.v:139508.9-139508.17" case 1'1 case end @@ -223121,16 +223121,16 @@ module \jtag sync always update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$6013 end - attribute \src "libresoc.v:139525.3-139545.6" - process $proc$libresoc.v:139525$6016 + attribute \src "libresoc.v:139524.3-139544.6" + process $proc$libresoc.v:139524$6016 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\jtag_wb_datasr_reg$next[63:0]$6017 $3\jtag_wb_datasr_reg$next[63:0]$6020 - attribute \src "libresoc.v:139526.5-139526.29" + attribute \src "libresoc.v:139525.5-139525.29" switch \initial - attribute \src "libresoc.v:139526.9-139526.17" + attribute \src "libresoc.v:139525.9-139525.17" case 1'1 case end @@ -223164,14 +223164,14 @@ module \jtag sync always update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$6017 end - attribute \src "libresoc.v:139546.3-139554.6" - process $proc$libresoc.v:139546$6021 + attribute \src "libresoc.v:139545.3-139553.6" + process $proc$libresoc.v:139545$6021 assign { } { } assign { } { } assign $0\dmi0_addrsr_update_core$next[0:0]$6022 $1\dmi0_addrsr_update_core$next[0:0]$6023 - attribute \src "libresoc.v:139547.5-139547.29" + attribute \src "libresoc.v:139546.5-139546.29" switch \initial - attribute \src "libresoc.v:139547.9-139547.17" + attribute \src "libresoc.v:139546.9-139546.17" case 1'1 case end @@ -223187,14 +223187,14 @@ module \jtag sync always update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$6022 end - attribute \src "libresoc.v:139555.3-139563.6" - process $proc$libresoc.v:139555$6024 + attribute \src "libresoc.v:139554.3-139562.6" + process $proc$libresoc.v:139554$6024 assign { } { } assign { } { } assign $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 - attribute \src "libresoc.v:139556.5-139556.29" + attribute \src "libresoc.v:139555.5-139555.29" switch \initial - attribute \src "libresoc.v:139556.9-139556.17" + attribute \src "libresoc.v:139555.9-139555.17" case 1'1 case end @@ -223210,14 +223210,14 @@ module \jtag sync always update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 end - attribute \src "libresoc.v:139564.3-139580.6" - process $proc$libresoc.v:139564$6027 + attribute \src "libresoc.v:139563.3-139579.6" + process $proc$libresoc.v:139563$6027 assign { } { } assign { } { } assign $0\dmi0_addrsr__oe$next[0:0]$6028 $2\dmi0_addrsr__oe$next[0:0]$6030 - attribute \src "libresoc.v:139565.5-139565.29" + attribute \src "libresoc.v:139564.5-139564.29" switch \initial - attribute \src "libresoc.v:139565.9-139565.17" + attribute \src "libresoc.v:139564.9-139564.17" case 1'1 case end @@ -223244,16 +223244,16 @@ module \jtag sync always update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$6028 end - attribute \src "libresoc.v:139581.3-139601.6" - process $proc$libresoc.v:139581$6031 + attribute \src "libresoc.v:139580.3-139600.6" + process $proc$libresoc.v:139580$6031 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\dmi0_addrsr_reg$next[7:0]$6032 $3\dmi0_addrsr_reg$next[7:0]$6035 - attribute \src "libresoc.v:139582.5-139582.29" + attribute \src "libresoc.v:139581.5-139581.29" switch \initial - attribute \src "libresoc.v:139582.9-139582.17" + attribute \src "libresoc.v:139581.9-139581.17" case 1'1 case end @@ -223287,14 +223287,14 @@ module \jtag sync always update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$6032 end - attribute \src "libresoc.v:139602.3-139610.6" - process $proc$libresoc.v:139602$6036 + attribute \src "libresoc.v:139601.3-139609.6" + process $proc$libresoc.v:139601$6036 assign { } { } assign { } { } assign $0\dmi0_datasr_update_core$next[0:0]$6037 $1\dmi0_datasr_update_core$next[0:0]$6038 - attribute \src "libresoc.v:139603.5-139603.29" + attribute \src "libresoc.v:139602.5-139602.29" switch \initial - attribute \src "libresoc.v:139603.9-139603.17" + attribute \src "libresoc.v:139602.9-139602.17" case 1'1 case end @@ -223310,14 +223310,14 @@ module \jtag sync always update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$6037 end - attribute \src "libresoc.v:139611.3-139619.6" - process $proc$libresoc.v:139611$6039 + attribute \src "libresoc.v:139610.3-139618.6" + process $proc$libresoc.v:139610$6039 assign { } { } assign { } { } assign $0\dmi0_datasr_update_core_prev$next[0:0]$6040 $1\dmi0_datasr_update_core_prev$next[0:0]$6041 - attribute \src "libresoc.v:139612.5-139612.29" + attribute \src "libresoc.v:139611.5-139611.29" switch \initial - attribute \src "libresoc.v:139612.9-139612.17" + attribute \src "libresoc.v:139611.9-139611.17" case 1'1 case end @@ -223333,14 +223333,14 @@ module \jtag sync always update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$6040 end - attribute \src "libresoc.v:139620.3-139636.6" - process $proc$libresoc.v:139620$6042 + attribute \src "libresoc.v:139619.3-139635.6" + process $proc$libresoc.v:139619$6042 assign { } { } assign { } { } assign $0\dmi0_datasr__oe$next[1:0]$6043 $2\dmi0_datasr__oe$next[1:0]$6045 - attribute \src "libresoc.v:139621.5-139621.29" + attribute \src "libresoc.v:139620.5-139620.29" switch \initial - attribute \src "libresoc.v:139621.9-139621.17" + attribute \src "libresoc.v:139620.9-139620.17" case 1'1 case end @@ -223367,16 +223367,16 @@ module \jtag sync always update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$6043 end - attribute \src "libresoc.v:139637.3-139657.6" - process $proc$libresoc.v:139637$6046 + attribute \src "libresoc.v:139636.3-139656.6" + process $proc$libresoc.v:139636$6046 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\dmi0_datasr_reg$next[63:0]$6047 $3\dmi0_datasr_reg$next[63:0]$6050 - attribute \src "libresoc.v:139638.5-139638.29" + attribute \src "libresoc.v:139637.5-139637.29" switch \initial - attribute \src "libresoc.v:139638.9-139638.17" + attribute \src "libresoc.v:139637.9-139637.17" case 1'1 case end @@ -223410,14 +223410,14 @@ module \jtag sync always update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$6047 end - attribute \src "libresoc.v:139658.3-139666.6" - process $proc$libresoc.v:139658$6051 + attribute \src "libresoc.v:139657.3-139665.6" + process $proc$libresoc.v:139657$6051 assign { } { } assign { } { } assign $0\sr5_update_core$next[0:0]$6052 $1\sr5_update_core$next[0:0]$6053 - attribute \src "libresoc.v:139659.5-139659.29" + attribute \src "libresoc.v:139658.5-139658.29" switch \initial - attribute \src "libresoc.v:139659.9-139659.17" + attribute \src "libresoc.v:139658.9-139658.17" case 1'1 case end @@ -223433,14 +223433,14 @@ module \jtag sync always update \sr5_update_core$next $0\sr5_update_core$next[0:0]$6052 end - attribute \src "libresoc.v:139667.3-139675.6" - process $proc$libresoc.v:139667$6054 + attribute \src "libresoc.v:139666.3-139674.6" + process $proc$libresoc.v:139666$6054 assign { } { } assign { } { } assign $0\sr5_update_core_prev$next[0:0]$6055 $1\sr5_update_core_prev$next[0:0]$6056 - attribute \src "libresoc.v:139668.5-139668.29" + attribute \src "libresoc.v:139667.5-139667.29" switch \initial - attribute \src "libresoc.v:139668.9-139668.17" + attribute \src "libresoc.v:139667.9-139667.17" case 1'1 case end @@ -223456,14 +223456,14 @@ module \jtag sync always update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$6055 end - attribute \src "libresoc.v:139676.3-139692.6" - process $proc$libresoc.v:139676$6057 + attribute \src "libresoc.v:139675.3-139691.6" + process $proc$libresoc.v:139675$6057 assign { } { } assign { } { } assign $0\sr5__oe$next[0:0]$6058 $2\sr5__oe$next[0:0]$6060 - attribute \src "libresoc.v:139677.5-139677.29" + attribute \src "libresoc.v:139676.5-139676.29" switch \initial - attribute \src "libresoc.v:139677.9-139677.17" + attribute \src "libresoc.v:139676.9-139676.17" case 1'1 case end @@ -223490,16 +223490,16 @@ module \jtag sync always update \sr5__oe$next $0\sr5__oe$next[0:0]$6058 end - attribute \src "libresoc.v:139693.3-139713.6" - process $proc$libresoc.v:139693$6061 + attribute \src "libresoc.v:139692.3-139712.6" + process $proc$libresoc.v:139692$6061 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\sr5_reg$next[2:0]$6062 $3\sr5_reg$next[2:0]$6065 - attribute \src "libresoc.v:139694.5-139694.29" + attribute \src "libresoc.v:139693.5-139693.29" switch \initial - attribute \src "libresoc.v:139694.9-139694.17" + attribute \src "libresoc.v:139693.9-139693.17" case 1'1 case end @@ -223533,13 +223533,13 @@ module \jtag sync always update \sr5_reg$next $0\sr5_reg$next[2:0]$6062 end - attribute \src "libresoc.v:139714.3-139740.6" - process $proc$libresoc.v:139714$6066 + attribute \src "libresoc.v:139713.3-139739.6" + process $proc$libresoc.v:139713$6066 assign { } { } assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:139715.5-139715.29" + attribute \src "libresoc.v:139714.5-139714.29" switch \initial - attribute \src "libresoc.v:139715.9-139715.17" + attribute \src "libresoc.v:139714.9-139714.17" case 1'1 case end @@ -223577,15 +223577,15 @@ module \jtag sync always update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] end - attribute \src "libresoc.v:139741.3-139773.6" - process $proc$libresoc.v:139741$6067 + attribute \src "libresoc.v:139740.3-139772.6" + process $proc$libresoc.v:139740$6067 assign { } { } assign { } { } assign { } { } assign $0\jtag_wb__adr$next[28:0]$6068 $4\jtag_wb__adr$next[28:0]$6072 - attribute \src "libresoc.v:139742.5-139742.29" + attribute \src "libresoc.v:139741.5-139741.29" switch \initial - attribute \src "libresoc.v:139742.9-139742.17" + attribute \src "libresoc.v:139741.9-139741.17" case 1'1 case end @@ -223636,15 +223636,15 @@ module \jtag sync always update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6068 end - attribute \src "libresoc.v:139774.3-139826.6" - process $proc$libresoc.v:139774$6073 + attribute \src "libresoc.v:139773.3-139825.6" + process $proc$libresoc.v:139773$6073 assign { } { } assign { } { } assign { } { } assign $0\fsm_state$next[2:0]$6074 $5\fsm_state$next[2:0]$6079 - attribute \src "libresoc.v:139775.5-139775.29" + attribute \src "libresoc.v:139774.5-139774.29" switch \initial - attribute \src "libresoc.v:139775.9-139775.17" + attribute \src "libresoc.v:139774.9-139774.17" case 1'1 case end @@ -223720,15 +223720,15 @@ module \jtag sync always update \fsm_state$next $0\fsm_state$next[2:0]$6074 end - attribute \src "libresoc.v:139827.3-139853.6" - process $proc$libresoc.v:139827$6080 + attribute \src "libresoc.v:139826.3-139852.6" + process $proc$libresoc.v:139826$6080 assign { } { } assign { } { } assign { } { } assign $0\jtag_wb__dat_w$next[63:0]$6081 $3\jtag_wb__dat_w$next[63:0]$6084 - attribute \src "libresoc.v:139828.5-139828.29" + attribute \src "libresoc.v:139827.5-139827.29" switch \initial - attribute \src "libresoc.v:139828.9-139828.17" + attribute \src "libresoc.v:139827.9-139827.17" case 1'1 case end @@ -223768,15 +223768,15 @@ module \jtag sync always update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6081 end - attribute \src "libresoc.v:139854.3-139874.6" - process $proc$libresoc.v:139854$6085 + attribute \src "libresoc.v:139853.3-139873.6" + process $proc$libresoc.v:139853$6085 assign { } { } assign { } { } assign { } { } assign $0\jtag_wb_datasr__i$next[63:0]$6086 $3\jtag_wb_datasr__i$next[63:0]$6089 - attribute \src "libresoc.v:139855.5-139855.29" + attribute \src "libresoc.v:139854.5-139854.29" switch \initial - attribute \src "libresoc.v:139855.9-139855.17" + attribute \src "libresoc.v:139854.9-139854.17" case 1'1 case end @@ -223810,15 +223810,15 @@ module \jtag sync always update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6086 end - attribute \src "libresoc.v:139875.3-139907.6" - process $proc$libresoc.v:139875$6090 + attribute \src "libresoc.v:139874.3-139906.6" + process $proc$libresoc.v:139874$6090 assign { } { } assign { } { } assign { } { } assign $0\dmi0__addr_i$next[3:0]$6091 $4\dmi0__addr_i$next[3:0]$6095 - attribute \src "libresoc.v:139876.5-139876.29" + attribute \src "libresoc.v:139875.5-139875.29" switch \initial - attribute \src "libresoc.v:139876.9-139876.17" + attribute \src "libresoc.v:139875.9-139875.17" case 1'1 case end @@ -223869,15 +223869,15 @@ module \jtag sync always update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6091 end - attribute \src "libresoc.v:139908.3-139960.6" - process $proc$libresoc.v:139908$6096 + attribute \src "libresoc.v:139907.3-139959.6" + process $proc$libresoc.v:139907$6096 assign { } { } assign { } { } assign { } { } assign $0\fsm_state$499$next[2:0]$6097 $5\fsm_state$499$next[2:0]$6102 - attribute \src "libresoc.v:139909.5-139909.29" + attribute \src "libresoc.v:139908.5-139908.29" switch \initial - attribute \src "libresoc.v:139909.9-139909.17" + attribute \src "libresoc.v:139908.9-139908.17" case 1'1 case end @@ -223953,15 +223953,15 @@ module \jtag sync always update \fsm_state$499$next $0\fsm_state$499$next[2:0]$6097 end - attribute \src "libresoc.v:139961.3-139987.6" - process $proc$libresoc.v:139961$6103 + attribute \src "libresoc.v:139960.3-139986.6" + process $proc$libresoc.v:139960$6103 assign { } { } assign { } { } assign { } { } assign $0\dmi0__din$next[63:0]$6104 $3\dmi0__din$next[63:0]$6107 - attribute \src "libresoc.v:139962.5-139962.29" + attribute \src "libresoc.v:139961.5-139961.29" switch \initial - attribute \src "libresoc.v:139962.9-139962.17" + attribute \src "libresoc.v:139961.9-139961.17" case 1'1 case end @@ -224001,15 +224001,15 @@ module \jtag sync always update \dmi0__din$next $0\dmi0__din$next[63:0]$6104 end - attribute \src "libresoc.v:139988.3-140008.6" - process $proc$libresoc.v:139988$6108 + attribute \src "libresoc.v:139987.3-140007.6" + process $proc$libresoc.v:139987$6108 assign { } { } assign { } { } assign { } { } assign $0\dmi0_datasr__i$next[63:0]$6109 $3\dmi0_datasr__i$next[63:0]$6112 - attribute \src "libresoc.v:139989.5-139989.29" + attribute \src "libresoc.v:139988.5-139988.29" switch \initial - attribute \src "libresoc.v:139989.9-139989.17" + attribute \src "libresoc.v:139988.9-139988.17" case 1'1 case end @@ -224043,8 +224043,8 @@ module \jtag sync always update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6109 end - attribute \src "libresoc.v:140009.3-140029.6" - process $proc$libresoc.v:140009$6113 + attribute \src "libresoc.v:140008.3-140028.6" + process $proc$libresoc.v:140008$6113 assign { } { } assign { } { } assign { } { } @@ -224057,9 +224057,9 @@ module \jtag assign $0\wb_dcache_en$next[0:0]$6114 $2\wb_dcache_en$next[0:0]$6120 assign $0\wb_icache_en$next[0:0]$6115 $2\wb_icache_en$next[0:0]$6121 assign $0\wb_sram_en$next[0:0]$6116 $2\wb_sram_en$next[0:0]$6122 - attribute \src "libresoc.v:140010.5-140010.29" + attribute \src "libresoc.v:140009.5-140009.29" switch \initial - attribute \src "libresoc.v:140010.9-140010.17" + attribute \src "libresoc.v:140009.9-140009.17" case 1'1 case end @@ -224096,14 +224096,14 @@ module \jtag update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6115 update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6116 end - attribute \src "libresoc.v:140030.3-140039.6" - process $proc$libresoc.v:140030$6123 + attribute \src "libresoc.v:140029.3-140038.6" + process $proc$libresoc.v:140029$6123 assign { } { } assign { } { } assign $0\sr5__i[2:0] $1\sr5__i[2:0] - attribute \src "libresoc.v:140031.5-140031.29" + attribute \src "libresoc.v:140030.5-140030.29" switch \initial - attribute \src "libresoc.v:140031.9-140031.17" + attribute \src "libresoc.v:140030.9-140030.17" case 1'1 case end @@ -224119,15 +224119,15 @@ module \jtag sync always update \sr5__i $0\sr5__i[2:0] end - attribute \src "libresoc.v:140040.3-140057.6" - process $proc$libresoc.v:140040$6124 + attribute \src "libresoc.v:140039.3-140056.6" + process $proc$libresoc.v:140039$6124 assign { } { } assign { } { } assign { } { } assign $0\io_sr$next[151:0]$6125 $2\io_sr$next[151:0]$6127 - attribute \src "libresoc.v:140041.5-140041.29" + attribute \src "libresoc.v:140040.5-140040.29" switch \initial - attribute \src "libresoc.v:140041.9-140041.17" + attribute \src "libresoc.v:140040.9-140040.17" case 1'1 case end @@ -224156,15 +224156,15 @@ module \jtag sync always update \io_sr$next $0\io_sr$next[151:0]$6125 end - attribute \src "libresoc.v:140058.3-140078.6" - process $proc$libresoc.v:140058$6128 + attribute \src "libresoc.v:140057.3-140077.6" + process $proc$libresoc.v:140057$6128 assign { } { } assign { } { } assign { } { } assign $0\io_bd$next[151:0]$6129 $2\io_bd$next[151:0]$6131 - attribute \src "libresoc.v:140059.5-140059.29" + attribute \src "libresoc.v:140058.5-140058.29" switch \initial - attribute \src "libresoc.v:140059.9-140059.17" + attribute \src "libresoc.v:140058.9-140058.17" case 1'1 case end @@ -224195,260 +224195,260 @@ module \jtag sync always update \io_bd$next $0\io_bd$next[151:0]$6129 end - connect \$9 $eq$libresoc.v:138999$5682_Y - connect \$99 $ternary$libresoc.v:139000$5683_Y - connect \$101 $ternary$libresoc.v:139001$5684_Y - connect \$103 $ternary$libresoc.v:139002$5685_Y - connect \$105 $ternary$libresoc.v:139003$5686_Y - connect \$107 $ternary$libresoc.v:139004$5687_Y - connect \$109 $ternary$libresoc.v:139005$5688_Y - connect \$111 $ternary$libresoc.v:139006$5689_Y - connect \$113 $ternary$libresoc.v:139007$5690_Y - connect \$115 $ternary$libresoc.v:139008$5691_Y - connect \$117 $ternary$libresoc.v:139009$5692_Y - connect \$11 $eq$libresoc.v:139010$5693_Y - connect \$119 $ternary$libresoc.v:139011$5694_Y - connect \$121 $ternary$libresoc.v:139012$5695_Y - connect \$123 $ternary$libresoc.v:139013$5696_Y - connect \$125 $ternary$libresoc.v:139014$5697_Y - connect \$127 $ternary$libresoc.v:139015$5698_Y - connect \$129 $ternary$libresoc.v:139016$5699_Y - connect \$131 $ternary$libresoc.v:139017$5700_Y - connect \$133 $ternary$libresoc.v:139018$5701_Y - connect \$135 $ternary$libresoc.v:139019$5702_Y - connect \$137 $ternary$libresoc.v:139020$5703_Y - connect \$13 $eq$libresoc.v:139021$5704_Y - connect \$139 $ternary$libresoc.v:139022$5705_Y - connect \$141 $ternary$libresoc.v:139023$5706_Y - connect \$143 $ternary$libresoc.v:139024$5707_Y - connect \$145 $ternary$libresoc.v:139025$5708_Y - connect \$147 $ternary$libresoc.v:139026$5709_Y - connect \$149 $ternary$libresoc.v:139027$5710_Y - connect \$151 $ternary$libresoc.v:139028$5711_Y - connect \$153 $ternary$libresoc.v:139029$5712_Y - connect \$155 $ternary$libresoc.v:139030$5713_Y - connect \$157 $ternary$libresoc.v:139031$5714_Y - connect \$15 $or$libresoc.v:139032$5715_Y - connect \$159 $ternary$libresoc.v:139033$5716_Y - connect \$161 $ternary$libresoc.v:139034$5717_Y - connect \$163 $ternary$libresoc.v:139035$5718_Y - connect \$165 $ternary$libresoc.v:139036$5719_Y - connect \$167 $ternary$libresoc.v:139037$5720_Y - connect \$169 $ternary$libresoc.v:139038$5721_Y - connect \$171 $ternary$libresoc.v:139039$5722_Y - connect \$173 $ternary$libresoc.v:139040$5723_Y - connect \$175 $ternary$libresoc.v:139041$5724_Y - connect \$177 $ternary$libresoc.v:139042$5725_Y - connect \$17 $and$libresoc.v:139043$5726_Y - connect \$179 $ternary$libresoc.v:139044$5727_Y - connect \$181 $ternary$libresoc.v:139045$5728_Y - connect \$183 $ternary$libresoc.v:139046$5729_Y - connect \$185 $ternary$libresoc.v:139047$5730_Y - connect \$187 $ternary$libresoc.v:139048$5731_Y - connect \$189 $ternary$libresoc.v:139049$5732_Y - connect \$191 $ternary$libresoc.v:139050$5733_Y - connect \$193 $ternary$libresoc.v:139051$5734_Y - connect \$195 $ternary$libresoc.v:139052$5735_Y - connect \$197 $ternary$libresoc.v:139053$5736_Y - connect \$1 $eq$libresoc.v:139054$5737_Y - connect \$19 $eq$libresoc.v:139055$5738_Y - connect \$199 $ternary$libresoc.v:139056$5739_Y - connect \$201 $ternary$libresoc.v:139057$5740_Y - connect \$203 $ternary$libresoc.v:139058$5741_Y - connect \$205 $ternary$libresoc.v:139059$5742_Y - connect \$207 $ternary$libresoc.v:139060$5743_Y - connect \$209 $ternary$libresoc.v:139061$5744_Y - connect \$211 $ternary$libresoc.v:139062$5745_Y - connect \$213 $ternary$libresoc.v:139063$5746_Y - connect \$215 $ternary$libresoc.v:139064$5747_Y - connect \$217 $ternary$libresoc.v:139065$5748_Y - connect \$21 $eq$libresoc.v:139066$5749_Y - connect \$219 $ternary$libresoc.v:139067$5750_Y - connect \$221 $ternary$libresoc.v:139068$5751_Y - connect \$223 $ternary$libresoc.v:139069$5752_Y - connect \$225 $ternary$libresoc.v:139070$5753_Y - connect \$227 $ternary$libresoc.v:139071$5754_Y - connect \$229 $ternary$libresoc.v:139072$5755_Y - connect \$231 $ternary$libresoc.v:139073$5756_Y - connect \$233 $ternary$libresoc.v:139074$5757_Y - connect \$235 $ternary$libresoc.v:139075$5758_Y - connect \$237 $ternary$libresoc.v:139076$5759_Y - connect \$23 $or$libresoc.v:139077$5760_Y - connect \$239 $ternary$libresoc.v:139078$5761_Y - connect \$241 $ternary$libresoc.v:139079$5762_Y - connect \$243 $ternary$libresoc.v:139080$5763_Y - connect \$245 $ternary$libresoc.v:139081$5764_Y - connect \$247 $ternary$libresoc.v:139082$5765_Y - connect \$249 $ternary$libresoc.v:139083$5766_Y - connect \$251 $ternary$libresoc.v:139084$5767_Y - connect \$253 $ternary$libresoc.v:139085$5768_Y - connect \$255 $ternary$libresoc.v:139086$5769_Y - connect \$257 $ternary$libresoc.v:139087$5770_Y - connect \$25 $eq$libresoc.v:139088$5771_Y - connect \$259 $ternary$libresoc.v:139089$5772_Y - connect \$261 $ternary$libresoc.v:139090$5773_Y - connect \$263 $ternary$libresoc.v:139091$5774_Y - connect \$265 $ternary$libresoc.v:139092$5775_Y - connect \$267 $ternary$libresoc.v:139093$5776_Y - connect \$269 $ternary$libresoc.v:139094$5777_Y - connect \$271 $ternary$libresoc.v:139095$5778_Y - connect \$273 $ternary$libresoc.v:139096$5779_Y - connect \$275 $ternary$libresoc.v:139097$5780_Y - connect \$277 $ternary$libresoc.v:139098$5781_Y - connect \$27 $or$libresoc.v:139099$5782_Y - connect \$279 $ternary$libresoc.v:139100$5783_Y - connect \$281 $ternary$libresoc.v:139101$5784_Y - connect \$283 $ternary$libresoc.v:139102$5785_Y - connect \$285 $ternary$libresoc.v:139103$5786_Y - connect \$287 $ternary$libresoc.v:139104$5787_Y - connect \$289 $ternary$libresoc.v:139105$5788_Y - connect \$291 $ternary$libresoc.v:139106$5789_Y - connect \$293 $ternary$libresoc.v:139107$5790_Y - connect \$295 $ternary$libresoc.v:139108$5791_Y - connect \$297 $ternary$libresoc.v:139109$5792_Y - connect \$29 $and$libresoc.v:139110$5793_Y - connect \$299 $ternary$libresoc.v:139111$5794_Y - connect \$301 $ternary$libresoc.v:139112$5795_Y - connect \$303 $ternary$libresoc.v:139113$5796_Y - connect \$305 $ternary$libresoc.v:139114$5797_Y - connect \$307 $ternary$libresoc.v:139115$5798_Y - connect \$309 $ternary$libresoc.v:139116$5799_Y - connect \$311 $ternary$libresoc.v:139117$5800_Y - connect \$313 $ternary$libresoc.v:139118$5801_Y - connect \$315 $ternary$libresoc.v:139119$5802_Y - connect \$317 $ternary$libresoc.v:139120$5803_Y - connect \$31 $and$libresoc.v:139121$5804_Y - connect \$319 $ternary$libresoc.v:139122$5805_Y - connect \$321 $ternary$libresoc.v:139123$5806_Y - connect \$323 $ternary$libresoc.v:139124$5807_Y - connect \$325 $ternary$libresoc.v:139125$5808_Y - connect \$327 $ternary$libresoc.v:139126$5809_Y - connect \$329 $ternary$libresoc.v:139127$5810_Y - connect \$331 $ternary$libresoc.v:139128$5811_Y - connect \$333 $ternary$libresoc.v:139129$5812_Y - connect \$335 $ternary$libresoc.v:139130$5813_Y - connect \$337 $ternary$libresoc.v:139131$5814_Y - connect \$33 $eq$libresoc.v:139132$5815_Y - connect \$339 $ternary$libresoc.v:139133$5816_Y - connect \$341 $ternary$libresoc.v:139134$5817_Y - connect \$343 $ternary$libresoc.v:139135$5818_Y - connect \$345 $ternary$libresoc.v:139136$5819_Y - connect \$347 $ternary$libresoc.v:139137$5820_Y - connect \$349 $ternary$libresoc.v:139138$5821_Y - connect \$351 $ternary$libresoc.v:139139$5822_Y - connect \$353 $ternary$libresoc.v:139140$5823_Y - connect \$355 $eq$libresoc.v:139141$5824_Y - connect \$357 $eq$libresoc.v:139142$5825_Y - connect \$35 $eq$libresoc.v:139143$5826_Y - connect \$359 $or$libresoc.v:139144$5827_Y - connect \$361 $eq$libresoc.v:139145$5828_Y - connect \$363 $or$libresoc.v:139146$5829_Y - connect \$365 $and$libresoc.v:139147$5830_Y - connect \$367 $eq$libresoc.v:139148$5831_Y - connect \$369 $ne$libresoc.v:139149$5832_Y - connect \$371 $and$libresoc.v:139150$5833_Y - connect \$373 $ne$libresoc.v:139151$5834_Y - connect \$375 $and$libresoc.v:139152$5835_Y - connect \$377 $ne$libresoc.v:139153$5836_Y - connect \$37 $or$libresoc.v:139154$5837_Y - connect \$379 $and$libresoc.v:139155$5838_Y - connect \$381 $not$libresoc.v:139156$5839_Y - connect \$383 $and$libresoc.v:139157$5840_Y - connect \$385 $eq$libresoc.v:139158$5841_Y - connect \$387 $ne$libresoc.v:139159$5842_Y - connect \$389 $and$libresoc.v:139160$5843_Y - connect \$391 $ne$libresoc.v:139161$5844_Y - connect \$393 $and$libresoc.v:139162$5845_Y - connect \$395 $ne$libresoc.v:139163$5846_Y - connect \$397 $and$libresoc.v:139164$5847_Y - connect \$3 $eq$libresoc.v:139165$5848_Y - connect \$39 $eq$libresoc.v:139166$5849_Y - connect \$399 $not$libresoc.v:139167$5850_Y - connect \$401 $and$libresoc.v:139168$5851_Y - connect \$403 $eq$libresoc.v:139169$5852_Y - connect \$405 $eq$libresoc.v:139170$5853_Y - connect \$407 $ne$libresoc.v:139171$5854_Y - connect \$409 $and$libresoc.v:139172$5855_Y - connect \$411 $ne$libresoc.v:139173$5856_Y - connect \$413 $and$libresoc.v:139174$5857_Y - connect \$415 $ne$libresoc.v:139175$5858_Y - connect \$417 $and$libresoc.v:139176$5859_Y - connect \$41 $or$libresoc.v:139177$5860_Y - connect \$419 $not$libresoc.v:139178$5861_Y - connect \$421 $and$libresoc.v:139179$5862_Y - connect \$423 $eq$libresoc.v:139180$5863_Y - connect \$425 $ne$libresoc.v:139181$5864_Y - connect \$427 $and$libresoc.v:139182$5865_Y - connect \$429 $ne$libresoc.v:139183$5866_Y - connect \$431 $and$libresoc.v:139184$5867_Y - connect \$433 $ne$libresoc.v:139185$5868_Y - connect \$435 $and$libresoc.v:139186$5869_Y - connect \$437 $not$libresoc.v:139187$5870_Y - connect \$43 $and$libresoc.v:139188$5871_Y - connect \$439 $and$libresoc.v:139189$5872_Y - connect \$441 $eq$libresoc.v:139190$5873_Y - connect \$443 $eq$libresoc.v:139191$5874_Y - connect \$445 $ne$libresoc.v:139192$5875_Y - connect \$447 $and$libresoc.v:139193$5876_Y - connect \$449 $ne$libresoc.v:139194$5877_Y - connect \$451 $and$libresoc.v:139195$5878_Y - connect \$453 $ne$libresoc.v:139196$5879_Y - connect \$455 $and$libresoc.v:139197$5880_Y - connect \$457 $not$libresoc.v:139198$5881_Y - connect \$45 $and$libresoc.v:139199$5882_Y - connect \$459 $and$libresoc.v:139200$5883_Y - connect \$461 $eq$libresoc.v:139201$5884_Y - connect \$463 $ne$libresoc.v:139202$5885_Y - connect \$465 $and$libresoc.v:139203$5886_Y - connect \$467 $ne$libresoc.v:139204$5887_Y - connect \$469 $and$libresoc.v:139205$5888_Y - connect \$471 $ne$libresoc.v:139206$5889_Y - connect \$473 $and$libresoc.v:139207$5890_Y - connect \$475 $not$libresoc.v:139208$5891_Y - connect \$477 $and$libresoc.v:139209$5892_Y - connect \$47 $eq$libresoc.v:139210$5893_Y - connect \$480 $eq$libresoc.v:139211$5894_Y - connect \$479 $not$libresoc.v:139212$5895_Y - connect \$483 $eq$libresoc.v:139213$5896_Y - connect \$485 $eq$libresoc.v:139214$5897_Y - connect \$487 $or$libresoc.v:139215$5898_Y - connect \$489 $eq$libresoc.v:139216$5899_Y - connect \$492 $add$libresoc.v:139217$5900_Y - connect \$495 $add$libresoc.v:139218$5901_Y - connect \$497 $pos$libresoc.v:139219$5903_Y - connect \$49 $eq$libresoc.v:139220$5904_Y - connect \$500 $eq$libresoc.v:139221$5905_Y - connect \$502 $eq$libresoc.v:139222$5906_Y - connect \$504 $or$libresoc.v:139223$5907_Y - connect \$506 $eq$libresoc.v:139224$5908_Y - connect \$509 $add$libresoc.v:139225$5909_Y - connect \$512 $add$libresoc.v:139226$5910_Y - connect \$51 $ternary$libresoc.v:139227$5911_Y - connect \$53 $ternary$libresoc.v:139228$5912_Y - connect \$55 $ternary$libresoc.v:139229$5913_Y - connect \$57 $ternary$libresoc.v:139230$5914_Y - connect \$5 $or$libresoc.v:139231$5915_Y - connect \$59 $ternary$libresoc.v:139232$5916_Y - connect \$61 $ternary$libresoc.v:139233$5917_Y - connect \$63 $ternary$libresoc.v:139234$5918_Y - connect \$65 $ternary$libresoc.v:139235$5919_Y - connect \$67 $ternary$libresoc.v:139236$5920_Y - connect \$69 $ternary$libresoc.v:139237$5921_Y - connect \$71 $ternary$libresoc.v:139238$5922_Y - connect \$73 $ternary$libresoc.v:139239$5923_Y - connect \$75 $ternary$libresoc.v:139240$5924_Y - connect \$77 $ternary$libresoc.v:139241$5925_Y - connect \$7 $and$libresoc.v:139242$5926_Y - connect \$79 $ternary$libresoc.v:139243$5927_Y - connect \$81 $ternary$libresoc.v:139244$5928_Y - connect \$83 $ternary$libresoc.v:139245$5929_Y - connect \$85 $ternary$libresoc.v:139246$5930_Y - connect \$87 $ternary$libresoc.v:139247$5931_Y - connect \$89 $ternary$libresoc.v:139248$5932_Y - connect \$91 $ternary$libresoc.v:139249$5933_Y - connect \$93 $ternary$libresoc.v:139250$5934_Y - connect \$95 $ternary$libresoc.v:139251$5935_Y - connect \$97 $ternary$libresoc.v:139252$5936_Y + connect \$9 $eq$libresoc.v:138998$5682_Y + connect \$99 $ternary$libresoc.v:138999$5683_Y + connect \$101 $ternary$libresoc.v:139000$5684_Y + connect \$103 $ternary$libresoc.v:139001$5685_Y + connect \$105 $ternary$libresoc.v:139002$5686_Y + connect \$107 $ternary$libresoc.v:139003$5687_Y + connect \$109 $ternary$libresoc.v:139004$5688_Y + connect \$111 $ternary$libresoc.v:139005$5689_Y + connect \$113 $ternary$libresoc.v:139006$5690_Y + connect \$115 $ternary$libresoc.v:139007$5691_Y + connect \$117 $ternary$libresoc.v:139008$5692_Y + connect \$11 $eq$libresoc.v:139009$5693_Y + connect \$119 $ternary$libresoc.v:139010$5694_Y + connect \$121 $ternary$libresoc.v:139011$5695_Y + connect \$123 $ternary$libresoc.v:139012$5696_Y + connect \$125 $ternary$libresoc.v:139013$5697_Y + connect \$127 $ternary$libresoc.v:139014$5698_Y + connect \$129 $ternary$libresoc.v:139015$5699_Y + connect \$131 $ternary$libresoc.v:139016$5700_Y + connect \$133 $ternary$libresoc.v:139017$5701_Y + connect \$135 $ternary$libresoc.v:139018$5702_Y + connect \$137 $ternary$libresoc.v:139019$5703_Y + connect \$13 $eq$libresoc.v:139020$5704_Y + connect \$139 $ternary$libresoc.v:139021$5705_Y + connect \$141 $ternary$libresoc.v:139022$5706_Y + connect \$143 $ternary$libresoc.v:139023$5707_Y + connect \$145 $ternary$libresoc.v:139024$5708_Y + connect \$147 $ternary$libresoc.v:139025$5709_Y + connect \$149 $ternary$libresoc.v:139026$5710_Y + connect \$151 $ternary$libresoc.v:139027$5711_Y + connect \$153 $ternary$libresoc.v:139028$5712_Y + connect \$155 $ternary$libresoc.v:139029$5713_Y + connect \$157 $ternary$libresoc.v:139030$5714_Y + connect \$15 $or$libresoc.v:139031$5715_Y + connect \$159 $ternary$libresoc.v:139032$5716_Y + connect \$161 $ternary$libresoc.v:139033$5717_Y + connect \$163 $ternary$libresoc.v:139034$5718_Y + connect \$165 $ternary$libresoc.v:139035$5719_Y + connect \$167 $ternary$libresoc.v:139036$5720_Y + connect \$169 $ternary$libresoc.v:139037$5721_Y + connect \$171 $ternary$libresoc.v:139038$5722_Y + connect \$173 $ternary$libresoc.v:139039$5723_Y + connect \$175 $ternary$libresoc.v:139040$5724_Y + connect \$177 $ternary$libresoc.v:139041$5725_Y + connect \$17 $and$libresoc.v:139042$5726_Y + connect \$179 $ternary$libresoc.v:139043$5727_Y + connect \$181 $ternary$libresoc.v:139044$5728_Y + connect \$183 $ternary$libresoc.v:139045$5729_Y + connect \$185 $ternary$libresoc.v:139046$5730_Y + connect \$187 $ternary$libresoc.v:139047$5731_Y + connect \$189 $ternary$libresoc.v:139048$5732_Y + connect \$191 $ternary$libresoc.v:139049$5733_Y + connect \$193 $ternary$libresoc.v:139050$5734_Y + connect \$195 $ternary$libresoc.v:139051$5735_Y + connect \$197 $ternary$libresoc.v:139052$5736_Y + connect \$1 $eq$libresoc.v:139053$5737_Y + connect \$19 $eq$libresoc.v:139054$5738_Y + connect \$199 $ternary$libresoc.v:139055$5739_Y + connect \$201 $ternary$libresoc.v:139056$5740_Y + connect \$203 $ternary$libresoc.v:139057$5741_Y + connect \$205 $ternary$libresoc.v:139058$5742_Y + connect \$207 $ternary$libresoc.v:139059$5743_Y + connect \$209 $ternary$libresoc.v:139060$5744_Y + connect \$211 $ternary$libresoc.v:139061$5745_Y + connect \$213 $ternary$libresoc.v:139062$5746_Y + connect \$215 $ternary$libresoc.v:139063$5747_Y + connect \$217 $ternary$libresoc.v:139064$5748_Y + connect \$21 $eq$libresoc.v:139065$5749_Y + connect \$219 $ternary$libresoc.v:139066$5750_Y + connect \$221 $ternary$libresoc.v:139067$5751_Y + connect \$223 $ternary$libresoc.v:139068$5752_Y + connect \$225 $ternary$libresoc.v:139069$5753_Y + connect \$227 $ternary$libresoc.v:139070$5754_Y + connect \$229 $ternary$libresoc.v:139071$5755_Y + connect \$231 $ternary$libresoc.v:139072$5756_Y + connect \$233 $ternary$libresoc.v:139073$5757_Y + connect \$235 $ternary$libresoc.v:139074$5758_Y + connect \$237 $ternary$libresoc.v:139075$5759_Y + connect \$23 $or$libresoc.v:139076$5760_Y + connect \$239 $ternary$libresoc.v:139077$5761_Y + connect \$241 $ternary$libresoc.v:139078$5762_Y + connect \$243 $ternary$libresoc.v:139079$5763_Y + connect \$245 $ternary$libresoc.v:139080$5764_Y + connect \$247 $ternary$libresoc.v:139081$5765_Y + connect \$249 $ternary$libresoc.v:139082$5766_Y + connect \$251 $ternary$libresoc.v:139083$5767_Y + connect \$253 $ternary$libresoc.v:139084$5768_Y + connect \$255 $ternary$libresoc.v:139085$5769_Y + connect \$257 $ternary$libresoc.v:139086$5770_Y + connect \$25 $eq$libresoc.v:139087$5771_Y + connect \$259 $ternary$libresoc.v:139088$5772_Y + connect \$261 $ternary$libresoc.v:139089$5773_Y + connect \$263 $ternary$libresoc.v:139090$5774_Y + connect \$265 $ternary$libresoc.v:139091$5775_Y + connect \$267 $ternary$libresoc.v:139092$5776_Y + connect \$269 $ternary$libresoc.v:139093$5777_Y + connect \$271 $ternary$libresoc.v:139094$5778_Y + connect \$273 $ternary$libresoc.v:139095$5779_Y + connect \$275 $ternary$libresoc.v:139096$5780_Y + connect \$277 $ternary$libresoc.v:139097$5781_Y + connect \$27 $or$libresoc.v:139098$5782_Y + connect \$279 $ternary$libresoc.v:139099$5783_Y + connect \$281 $ternary$libresoc.v:139100$5784_Y + connect \$283 $ternary$libresoc.v:139101$5785_Y + connect \$285 $ternary$libresoc.v:139102$5786_Y + connect \$287 $ternary$libresoc.v:139103$5787_Y + connect \$289 $ternary$libresoc.v:139104$5788_Y + connect \$291 $ternary$libresoc.v:139105$5789_Y + connect \$293 $ternary$libresoc.v:139106$5790_Y + connect \$295 $ternary$libresoc.v:139107$5791_Y + connect \$297 $ternary$libresoc.v:139108$5792_Y + connect \$29 $and$libresoc.v:139109$5793_Y + connect \$299 $ternary$libresoc.v:139110$5794_Y + connect \$301 $ternary$libresoc.v:139111$5795_Y + connect \$303 $ternary$libresoc.v:139112$5796_Y + connect \$305 $ternary$libresoc.v:139113$5797_Y + connect \$307 $ternary$libresoc.v:139114$5798_Y + connect \$309 $ternary$libresoc.v:139115$5799_Y + connect \$311 $ternary$libresoc.v:139116$5800_Y + connect \$313 $ternary$libresoc.v:139117$5801_Y + connect \$315 $ternary$libresoc.v:139118$5802_Y + connect \$317 $ternary$libresoc.v:139119$5803_Y + connect \$31 $and$libresoc.v:139120$5804_Y + connect \$319 $ternary$libresoc.v:139121$5805_Y + connect \$321 $ternary$libresoc.v:139122$5806_Y + connect \$323 $ternary$libresoc.v:139123$5807_Y + connect \$325 $ternary$libresoc.v:139124$5808_Y + connect \$327 $ternary$libresoc.v:139125$5809_Y + connect \$329 $ternary$libresoc.v:139126$5810_Y + connect \$331 $ternary$libresoc.v:139127$5811_Y + connect \$333 $ternary$libresoc.v:139128$5812_Y + connect \$335 $ternary$libresoc.v:139129$5813_Y + connect \$337 $ternary$libresoc.v:139130$5814_Y + connect \$33 $eq$libresoc.v:139131$5815_Y + connect \$339 $ternary$libresoc.v:139132$5816_Y + connect \$341 $ternary$libresoc.v:139133$5817_Y + connect \$343 $ternary$libresoc.v:139134$5818_Y + connect \$345 $ternary$libresoc.v:139135$5819_Y + connect \$347 $ternary$libresoc.v:139136$5820_Y + connect \$349 $ternary$libresoc.v:139137$5821_Y + connect \$351 $ternary$libresoc.v:139138$5822_Y + connect \$353 $ternary$libresoc.v:139139$5823_Y + connect \$355 $eq$libresoc.v:139140$5824_Y + connect \$357 $eq$libresoc.v:139141$5825_Y + connect \$35 $eq$libresoc.v:139142$5826_Y + connect \$359 $or$libresoc.v:139143$5827_Y + connect \$361 $eq$libresoc.v:139144$5828_Y + connect \$363 $or$libresoc.v:139145$5829_Y + connect \$365 $and$libresoc.v:139146$5830_Y + connect \$367 $eq$libresoc.v:139147$5831_Y + connect \$369 $ne$libresoc.v:139148$5832_Y + connect \$371 $and$libresoc.v:139149$5833_Y + connect \$373 $ne$libresoc.v:139150$5834_Y + connect \$375 $and$libresoc.v:139151$5835_Y + connect \$377 $ne$libresoc.v:139152$5836_Y + connect \$37 $or$libresoc.v:139153$5837_Y + connect \$379 $and$libresoc.v:139154$5838_Y + connect \$381 $not$libresoc.v:139155$5839_Y + connect \$383 $and$libresoc.v:139156$5840_Y + connect \$385 $eq$libresoc.v:139157$5841_Y + connect \$387 $ne$libresoc.v:139158$5842_Y + connect \$389 $and$libresoc.v:139159$5843_Y + connect \$391 $ne$libresoc.v:139160$5844_Y + connect \$393 $and$libresoc.v:139161$5845_Y + connect \$395 $ne$libresoc.v:139162$5846_Y + connect \$397 $and$libresoc.v:139163$5847_Y + connect \$3 $eq$libresoc.v:139164$5848_Y + connect \$39 $eq$libresoc.v:139165$5849_Y + connect \$399 $not$libresoc.v:139166$5850_Y + connect \$401 $and$libresoc.v:139167$5851_Y + connect \$403 $eq$libresoc.v:139168$5852_Y + connect \$405 $eq$libresoc.v:139169$5853_Y + connect \$407 $ne$libresoc.v:139170$5854_Y + connect \$409 $and$libresoc.v:139171$5855_Y + connect \$411 $ne$libresoc.v:139172$5856_Y + connect \$413 $and$libresoc.v:139173$5857_Y + connect \$415 $ne$libresoc.v:139174$5858_Y + connect \$417 $and$libresoc.v:139175$5859_Y + connect \$41 $or$libresoc.v:139176$5860_Y + connect \$419 $not$libresoc.v:139177$5861_Y + connect \$421 $and$libresoc.v:139178$5862_Y + connect \$423 $eq$libresoc.v:139179$5863_Y + connect \$425 $ne$libresoc.v:139180$5864_Y + connect \$427 $and$libresoc.v:139181$5865_Y + connect \$429 $ne$libresoc.v:139182$5866_Y + connect \$431 $and$libresoc.v:139183$5867_Y + connect \$433 $ne$libresoc.v:139184$5868_Y + connect \$435 $and$libresoc.v:139185$5869_Y + connect \$437 $not$libresoc.v:139186$5870_Y + connect \$43 $and$libresoc.v:139187$5871_Y + connect \$439 $and$libresoc.v:139188$5872_Y + connect \$441 $eq$libresoc.v:139189$5873_Y + connect \$443 $eq$libresoc.v:139190$5874_Y + connect \$445 $ne$libresoc.v:139191$5875_Y + connect \$447 $and$libresoc.v:139192$5876_Y + connect \$449 $ne$libresoc.v:139193$5877_Y + connect \$451 $and$libresoc.v:139194$5878_Y + connect \$453 $ne$libresoc.v:139195$5879_Y + connect \$455 $and$libresoc.v:139196$5880_Y + connect \$457 $not$libresoc.v:139197$5881_Y + connect \$45 $and$libresoc.v:139198$5882_Y + connect \$459 $and$libresoc.v:139199$5883_Y + connect \$461 $eq$libresoc.v:139200$5884_Y + connect \$463 $ne$libresoc.v:139201$5885_Y + connect \$465 $and$libresoc.v:139202$5886_Y + connect \$467 $ne$libresoc.v:139203$5887_Y + connect \$469 $and$libresoc.v:139204$5888_Y + connect \$471 $ne$libresoc.v:139205$5889_Y + connect \$473 $and$libresoc.v:139206$5890_Y + connect \$475 $not$libresoc.v:139207$5891_Y + connect \$477 $and$libresoc.v:139208$5892_Y + connect \$47 $eq$libresoc.v:139209$5893_Y + connect \$480 $eq$libresoc.v:139210$5894_Y + connect \$479 $not$libresoc.v:139211$5895_Y + connect \$483 $eq$libresoc.v:139212$5896_Y + connect \$485 $eq$libresoc.v:139213$5897_Y + connect \$487 $or$libresoc.v:139214$5898_Y + connect \$489 $eq$libresoc.v:139215$5899_Y + connect \$492 $add$libresoc.v:139216$5900_Y + connect \$495 $add$libresoc.v:139217$5901_Y + connect \$497 $pos$libresoc.v:139218$5903_Y + connect \$49 $eq$libresoc.v:139219$5904_Y + connect \$500 $eq$libresoc.v:139220$5905_Y + connect \$502 $eq$libresoc.v:139221$5906_Y + connect \$504 $or$libresoc.v:139222$5907_Y + connect \$506 $eq$libresoc.v:139223$5908_Y + connect \$509 $add$libresoc.v:139224$5909_Y + connect \$512 $add$libresoc.v:139225$5910_Y + connect \$51 $ternary$libresoc.v:139226$5911_Y + connect \$53 $ternary$libresoc.v:139227$5912_Y + connect \$55 $ternary$libresoc.v:139228$5913_Y + connect \$57 $ternary$libresoc.v:139229$5914_Y + connect \$5 $or$libresoc.v:139230$5915_Y + connect \$59 $ternary$libresoc.v:139231$5916_Y + connect \$61 $ternary$libresoc.v:139232$5917_Y + connect \$63 $ternary$libresoc.v:139233$5918_Y + connect \$65 $ternary$libresoc.v:139234$5919_Y + connect \$67 $ternary$libresoc.v:139235$5920_Y + connect \$69 $ternary$libresoc.v:139236$5921_Y + connect \$71 $ternary$libresoc.v:139237$5922_Y + connect \$73 $ternary$libresoc.v:139238$5923_Y + connect \$75 $ternary$libresoc.v:139239$5924_Y + connect \$77 $ternary$libresoc.v:139240$5925_Y + connect \$7 $and$libresoc.v:139241$5926_Y + connect \$79 $ternary$libresoc.v:139242$5927_Y + connect \$81 $ternary$libresoc.v:139243$5928_Y + connect \$83 $ternary$libresoc.v:139244$5929_Y + connect \$85 $ternary$libresoc.v:139245$5930_Y + connect \$87 $ternary$libresoc.v:139246$5931_Y + connect \$89 $ternary$libresoc.v:139247$5932_Y + connect \$91 $ternary$libresoc.v:139248$5933_Y + connect \$93 $ternary$libresoc.v:139249$5934_Y + connect \$95 $ternary$libresoc.v:139250$5935_Y + connect \$97 $ternary$libresoc.v:139251$5936_Y connect \$491 \$492 connect \$494 \$495 connect \$508 \$509 @@ -224653,7 +224653,7 @@ module \jtag connect \_idblock_id_bypass \$9 connect \_idblock_select_id \$7 end -attribute \src "libresoc.v:140286.1-140475.10" +attribute \src "libresoc.v:140285.1-140474.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0" attribute \generator "nMigen" @@ -224763,7 +224763,7 @@ module \l0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire input 21 \wb_dcache_en attribute \module_not_derived 1 - attribute \src "libresoc.v:140391.12-140425.4" + attribute \src "libresoc.v:140390.12-140424.4" cell \l0$130 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -224800,7 +224800,7 @@ module \l0 connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:140426.9-140448.4" + attribute \src "libresoc.v:140425.9-140447.4" cell \lsmem \lsmem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -224825,7 +224825,7 @@ module \l0 connect \x_valid_i \pimem_x_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:140449.9-140473.4" + attribute \src "libresoc.v:140448.9-140472.4" cell \pimem \pimem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -224853,145 +224853,145 @@ module \l0 end connect \pimem_ldst_port0_exc_$signal 1'0 end -attribute \src "libresoc.v:140479.1-140887.10" +attribute \src "libresoc.v:140478.1-140886.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0" attribute \generator "nMigen" module \l0$130 - attribute \src "libresoc.v:140742.3-140756.6" + attribute \src "libresoc.v:140741.3-140755.6" wire $0\idx_l$23$next[0:0]$6210 - attribute \src "libresoc.v:140642.3-140643.35" + attribute \src "libresoc.v:140641.3-140642.35" wire $0\idx_l$23[0:0]$6177 - attribute \src "libresoc.v:140500.7-140500.24" + attribute \src "libresoc.v:140499.7-140499.24" wire $0\idx_l$23[0:0]$6232 - attribute \src "libresoc.v:140797.3-140806.6" + attribute \src "libresoc.v:140796.3-140805.6" wire $0\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:140787.3-140796.6" + attribute \src "libresoc.v:140786.3-140795.6" wire $0\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:140480.7-140480.20" + attribute \src "libresoc.v:140479.7-140479.20" wire $0\initial[0:0] - attribute \src "libresoc.v:140663.3-140672.6" + attribute \src "libresoc.v:140662.3-140671.6" wire width 48 $0\ldst_port0_addr_i$12[47:0]$6179 - attribute \src "libresoc.v:140673.3-140682.6" + attribute \src "libresoc.v:140672.3-140681.6" wire $0\ldst_port0_addr_i_ok$13[0:0]$6182 - attribute \src "libresoc.v:140715.3-140724.6" + attribute \src "libresoc.v:140714.3-140723.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:140705.3-140714.6" + attribute \src "libresoc.v:140704.3-140713.6" wire $0\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:140777.3-140786.6" + attribute \src "libresoc.v:140776.3-140785.6" wire $0\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:140852.3-140861.6" + attribute \src "libresoc.v:140851.3-140860.6" wire width 4 $0\ldst_port0_data_len$11[3:0]$6227 - attribute \src "libresoc.v:140725.3-140741.6" + attribute \src "libresoc.v:140724.3-140740.6" wire $0\ldst_port0_exc_$signal$1[0:0]$6194 - attribute \src "libresoc.v:140725.3-140741.6" + attribute \src "libresoc.v:140724.3-140740.6" wire $0\ldst_port0_exc_$signal$2[0:0]$6195 - attribute \src "libresoc.v:140725.3-140741.6" + attribute \src "libresoc.v:140724.3-140740.6" wire $0\ldst_port0_exc_$signal$3[0:0]$6196 - attribute \src "libresoc.v:140725.3-140741.6" + attribute \src "libresoc.v:140724.3-140740.6" wire $0\ldst_port0_exc_$signal$4[0:0]$6197 - attribute \src "libresoc.v:140725.3-140741.6" + attribute \src "libresoc.v:140724.3-140740.6" wire $0\ldst_port0_exc_$signal$5[0:0]$6198 - attribute \src "libresoc.v:140725.3-140741.6" + attribute \src "libresoc.v:140724.3-140740.6" wire $0\ldst_port0_exc_$signal$6[0:0]$6199 - attribute \src "libresoc.v:140725.3-140741.6" + attribute \src "libresoc.v:140724.3-140740.6" wire $0\ldst_port0_exc_$signal$7[0:0]$6200 - attribute \src "libresoc.v:140725.3-140741.6" + attribute \src "libresoc.v:140724.3-140740.6" wire $0\ldst_port0_exc_$signal[0:0]$6193 - attribute \src "libresoc.v:140862.3-140871.6" + attribute \src "libresoc.v:140861.3-140870.6" wire $0\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:140832.3-140841.6" + attribute \src "libresoc.v:140831.3-140840.6" wire $0\ldst_port0_is_ld_i$8[0:0]$6221 - attribute \src "libresoc.v:140842.3-140851.6" + attribute \src "libresoc.v:140841.3-140850.6" wire $0\ldst_port0_is_st_i$9[0:0]$6224 - attribute \src "libresoc.v:140694.3-140704.6" + attribute \src "libresoc.v:140693.3-140703.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:140694.3-140704.6" + attribute \src "libresoc.v:140693.3-140703.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:140767.3-140776.6" + attribute \src "libresoc.v:140766.3-140775.6" wire $0\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:140757.3-140766.6" + attribute \src "libresoc.v:140756.3-140765.6" wire $0\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:140683.3-140693.6" + attribute \src "libresoc.v:140682.3-140692.6" wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6185 - attribute \src "libresoc.v:140683.3-140693.6" + attribute \src "libresoc.v:140682.3-140692.6" wire $0\ldst_port0_st_data_i_ok$17[0:0]$6186 - attribute \src "libresoc.v:140640.3-140641.36" + attribute \src "libresoc.v:140639.3-140640.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:140822.3-140831.6" + attribute \src "libresoc.v:140821.3-140830.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:140807.3-140821.6" + attribute \src "libresoc.v:140806.3-140820.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:140742.3-140756.6" + attribute \src "libresoc.v:140741.3-140755.6" wire $1\idx_l$23$next[0:0]$6211 - attribute \src "libresoc.v:140797.3-140806.6" + attribute \src "libresoc.v:140796.3-140805.6" wire $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:140787.3-140796.6" + attribute \src "libresoc.v:140786.3-140795.6" wire $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:140663.3-140672.6" + attribute \src "libresoc.v:140662.3-140671.6" wire width 48 $1\ldst_port0_addr_i$12[47:0]$6180 - attribute \src "libresoc.v:140673.3-140682.6" + attribute \src "libresoc.v:140672.3-140681.6" wire $1\ldst_port0_addr_i_ok$13[0:0]$6183 - attribute \src "libresoc.v:140715.3-140724.6" + attribute \src "libresoc.v:140714.3-140723.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:140705.3-140714.6" + attribute \src "libresoc.v:140704.3-140713.6" wire $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:140777.3-140786.6" + attribute \src "libresoc.v:140776.3-140785.6" wire $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:140852.3-140861.6" + attribute \src "libresoc.v:140851.3-140860.6" wire width 4 $1\ldst_port0_data_len$11[3:0]$6228 - attribute \src "libresoc.v:140725.3-140741.6" + attribute \src "libresoc.v:140724.3-140740.6" wire $1\ldst_port0_exc_$signal$1[0:0]$6202 - attribute \src "libresoc.v:140725.3-140741.6" + attribute \src "libresoc.v:140724.3-140740.6" wire $1\ldst_port0_exc_$signal$2[0:0]$6203 - attribute \src "libresoc.v:140725.3-140741.6" + attribute \src "libresoc.v:140724.3-140740.6" wire $1\ldst_port0_exc_$signal$3[0:0]$6204 - attribute \src "libresoc.v:140725.3-140741.6" + attribute \src "libresoc.v:140724.3-140740.6" wire $1\ldst_port0_exc_$signal$4[0:0]$6205 - attribute \src "libresoc.v:140725.3-140741.6" + attribute \src "libresoc.v:140724.3-140740.6" wire $1\ldst_port0_exc_$signal$5[0:0]$6206 - attribute \src "libresoc.v:140725.3-140741.6" + attribute \src "libresoc.v:140724.3-140740.6" wire $1\ldst_port0_exc_$signal$6[0:0]$6207 - attribute \src "libresoc.v:140725.3-140741.6" + attribute \src "libresoc.v:140724.3-140740.6" wire $1\ldst_port0_exc_$signal$7[0:0]$6208 - attribute \src "libresoc.v:140725.3-140741.6" + attribute \src "libresoc.v:140724.3-140740.6" wire $1\ldst_port0_exc_$signal[0:0]$6201 - attribute \src "libresoc.v:140862.3-140871.6" + attribute \src "libresoc.v:140861.3-140870.6" wire $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:140832.3-140841.6" + attribute \src "libresoc.v:140831.3-140840.6" wire $1\ldst_port0_is_ld_i$8[0:0]$6222 - attribute \src "libresoc.v:140842.3-140851.6" + attribute \src "libresoc.v:140841.3-140850.6" wire $1\ldst_port0_is_st_i$9[0:0]$6225 - attribute \src "libresoc.v:140694.3-140704.6" + attribute \src "libresoc.v:140693.3-140703.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:140694.3-140704.6" + attribute \src "libresoc.v:140693.3-140703.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:140767.3-140776.6" + attribute \src "libresoc.v:140766.3-140775.6" wire $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:140757.3-140766.6" + attribute \src "libresoc.v:140756.3-140765.6" wire $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:140683.3-140693.6" + attribute \src "libresoc.v:140682.3-140692.6" wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6187 - attribute \src "libresoc.v:140683.3-140693.6" + attribute \src "libresoc.v:140682.3-140692.6" wire $1\ldst_port0_st_data_i_ok$17[0:0]$6188 - attribute \src "libresoc.v:140627.7-140627.25" + attribute \src "libresoc.v:140626.7-140626.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:140822.3-140831.6" + attribute \src "libresoc.v:140821.3-140830.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:140807.3-140821.6" + attribute \src "libresoc.v:140806.3-140820.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:140742.3-140756.6" + attribute \src "libresoc.v:140741.3-140755.6" wire $2\idx_l$23$next[0:0]$6212 - attribute \src "libresoc.v:140807.3-140821.6" + attribute \src "libresoc.v:140806.3-140820.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:140638.18-140638.103" - wire $not$libresoc.v:140638$6173_Y - attribute \src "libresoc.v:140639.18-140639.118" - wire $not$libresoc.v:140639$6174_Y - attribute \src "libresoc.v:140636.18-140636.134" - wire $or$libresoc.v:140636$6171_Y - attribute \src "libresoc.v:140637.18-140637.120" - wire $ternary$libresoc.v:140637$6172_Y + attribute \src "libresoc.v:140637.18-140637.103" + wire $not$libresoc.v:140637$6173_Y + attribute \src "libresoc.v:140638.18-140638.118" + wire $not$libresoc.v:140638$6174_Y + attribute \src "libresoc.v:140635.18-140635.134" + wire $or$libresoc.v:140635$6171_Y + attribute \src "libresoc.v:140636.18-140636.120" + wire $ternary$libresoc.v:140636$6172_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" wire \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" @@ -225020,7 +225020,7 @@ module \l0$130 wire \idx_l_r_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \idx_l_s_idx_l - attribute \src "libresoc.v:140480.7-140480.15" + attribute \src "libresoc.v:140479.7-140479.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 96 input 6 \ldst_port0_addr_i @@ -225131,23 +225131,23 @@ module \l0$130 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \reset_l_s_reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - cell $not $not$libresoc.v:140638$6173 + cell $not $not$libresoc.v:140637$6173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pick_n - connect \Y $not$libresoc.v:140638$6173_Y + connect \Y $not$libresoc.v:140637$6173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - cell $not $not$libresoc.v:140639$6174 + cell $not $not$libresoc.v:140638$6174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o$10 - connect \Y $not$libresoc.v:140639$6174_Y + connect \Y $not$libresoc.v:140638$6174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - cell $or $or$libresoc.v:140636$6171 + cell $or $or$libresoc.v:140635$6171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225155,18 +225155,18 @@ module \l0$130 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:140636$6171_Y + connect \Y $or$libresoc.v:140635$6171_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:140637$6172 + cell $mux $ternary$libresoc.v:140636$6172 parameter \WIDTH 1 connect \A \idx_l$23 connect \B \pick_o connect \S \idx_l_q_idx_l - connect \Y $ternary$libresoc.v:140637$6172_Y + connect \Y $ternary$libresoc.v:140636$6172_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:140644.9-140650.4" + attribute \src "libresoc.v:140643.9-140649.4" cell \idx_l \idx_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225175,14 +225175,14 @@ module \l0$130 connect \s_idx_l \idx_l_s_idx_l end attribute \module_not_derived 1 - attribute \src "libresoc.v:140651.8-140655.4" + attribute \src "libresoc.v:140650.8-140654.4" cell \pick \pick connect \i \pick_i connect \n \pick_n connect \o \pick_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:140656.17-140662.4" + attribute \src "libresoc.v:140655.17-140661.4" cell \reset_l$131 \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225190,52 +225190,52 @@ module \l0$130 connect \r_reset \reset_l_r_reset connect \s_reset \reset_l_s_reset end - attribute \src "libresoc.v:140480.7-140480.20" - process $proc$libresoc.v:140480$6230 + attribute \src "libresoc.v:140479.7-140479.20" + process $proc$libresoc.v:140479$6230 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:140500.7-140500.24" - process $proc$libresoc.v:140500$6231 + attribute \src "libresoc.v:140499.7-140499.24" + process $proc$libresoc.v:140499$6231 assign { } { } assign $0\idx_l$23[0:0]$6232 1'0 sync always sync init update \idx_l$23 $0\idx_l$23[0:0]$6232 end - attribute \src "libresoc.v:140627.7-140627.25" - process $proc$libresoc.v:140627$6233 + attribute \src "libresoc.v:140626.7-140626.25" + process $proc$libresoc.v:140626$6233 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:140640.3-140641.36" - process $proc$libresoc.v:140640$6175 + attribute \src "libresoc.v:140639.3-140640.36" + process $proc$libresoc.v:140639$6175 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end - attribute \src "libresoc.v:140642.3-140643.35" - process $proc$libresoc.v:140642$6176 + attribute \src "libresoc.v:140641.3-140642.35" + process $proc$libresoc.v:140641$6176 assign { } { } assign $0\idx_l$23[0:0]$6177 \idx_l$23$next sync posedge \coresync_clk update \idx_l$23 $0\idx_l$23[0:0]$6177 end - attribute \src "libresoc.v:140663.3-140672.6" - process $proc$libresoc.v:140663$6178 + attribute \src "libresoc.v:140662.3-140671.6" + process $proc$libresoc.v:140662$6178 assign { } { } assign { } { } assign $0\ldst_port0_addr_i$12[47:0]$6179 $1\ldst_port0_addr_i$12[47:0]$6180 - attribute \src "libresoc.v:140664.5-140664.29" + attribute \src "libresoc.v:140663.5-140663.29" switch \initial - attribute \src "libresoc.v:140664.9-140664.17" + attribute \src "libresoc.v:140663.9-140663.17" case 1'1 case end @@ -225251,14 +225251,14 @@ module \l0$130 sync always update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6179 end - attribute \src "libresoc.v:140673.3-140682.6" - process $proc$libresoc.v:140673$6181 + attribute \src "libresoc.v:140672.3-140681.6" + process $proc$libresoc.v:140672$6181 assign { } { } assign { } { } assign $0\ldst_port0_addr_i_ok$13[0:0]$6182 $1\ldst_port0_addr_i_ok$13[0:0]$6183 - attribute \src "libresoc.v:140674.5-140674.29" + attribute \src "libresoc.v:140673.5-140673.29" switch \initial - attribute \src "libresoc.v:140674.9-140674.17" + attribute \src "libresoc.v:140673.9-140673.17" case 1'1 case end @@ -225274,17 +225274,17 @@ module \l0$130 sync always update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6182 end - attribute \src "libresoc.v:140683.3-140693.6" - process $proc$libresoc.v:140683$6184 + attribute \src "libresoc.v:140682.3-140692.6" + process $proc$libresoc.v:140682$6184 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_st_data_i$18[63:0]$6185 $1\ldst_port0_st_data_i$18[63:0]$6187 assign $0\ldst_port0_st_data_i_ok$17[0:0]$6186 $1\ldst_port0_st_data_i_ok$17[0:0]$6188 - attribute \src "libresoc.v:140684.5-140684.29" + attribute \src "libresoc.v:140683.5-140683.29" switch \initial - attribute \src "libresoc.v:140684.9-140684.17" + attribute \src "libresoc.v:140683.9-140683.17" case 1'1 case end @@ -225303,17 +225303,17 @@ module \l0$130 update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6185 update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6186 end - attribute \src "libresoc.v:140694.3-140704.6" - process $proc$libresoc.v:140694$6189 + attribute \src "libresoc.v:140693.3-140703.6" + process $proc$libresoc.v:140693$6189 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:140695.5-140695.29" + attribute \src "libresoc.v:140694.5-140694.29" switch \initial - attribute \src "libresoc.v:140695.9-140695.17" + attribute \src "libresoc.v:140694.9-140694.17" case 1'1 case end @@ -225332,14 +225332,14 @@ module \l0$130 update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:140705.3-140714.6" - process $proc$libresoc.v:140705$6190 + attribute \src "libresoc.v:140704.3-140713.6" + process $proc$libresoc.v:140704$6190 assign { } { } assign { } { } assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:140706.5-140706.29" + attribute \src "libresoc.v:140705.5-140705.29" switch \initial - attribute \src "libresoc.v:140706.9-140706.17" + attribute \src "libresoc.v:140705.9-140705.17" case 1'1 case end @@ -225355,14 +225355,14 @@ module \l0$130 sync always update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] end - attribute \src "libresoc.v:140715.3-140724.6" - process $proc$libresoc.v:140715$6191 + attribute \src "libresoc.v:140714.3-140723.6" + process $proc$libresoc.v:140714$6191 assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:140716.5-140716.29" + attribute \src "libresoc.v:140715.5-140715.29" switch \initial - attribute \src "libresoc.v:140716.9-140716.17" + attribute \src "libresoc.v:140715.9-140715.17" case 1'1 case end @@ -225378,8 +225378,8 @@ module \l0$130 sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:140725.3-140741.6" - process $proc$libresoc.v:140725$6192 + attribute \src "libresoc.v:140724.3-140740.6" + process $proc$libresoc.v:140724$6192 assign { } { } assign { } { } assign { } { } @@ -225404,9 +225404,9 @@ module \l0$130 assign $0\ldst_port0_exc_$signal$5[0:0]$6198 $1\ldst_port0_exc_$signal$5[0:0]$6206 assign $0\ldst_port0_exc_$signal$6[0:0]$6199 $1\ldst_port0_exc_$signal$6[0:0]$6207 assign $0\ldst_port0_exc_$signal$7[0:0]$6200 $1\ldst_port0_exc_$signal$7[0:0]$6208 - attribute \src "libresoc.v:140726.5-140726.29" + attribute \src "libresoc.v:140725.5-140725.29" switch \initial - attribute \src "libresoc.v:140726.9-140726.17" + attribute \src "libresoc.v:140725.9-140725.17" case 1'1 case end @@ -225443,15 +225443,15 @@ module \l0$130 update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6199 update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6200 end - attribute \src "libresoc.v:140742.3-140756.6" - process $proc$libresoc.v:140742$6209 + attribute \src "libresoc.v:140741.3-140755.6" + process $proc$libresoc.v:140741$6209 assign { } { } assign { } { } assign { } { } assign $0\idx_l$23$next[0:0]$6210 $2\idx_l$23$next[0:0]$6212 - attribute \src "libresoc.v:140743.5-140743.29" + attribute \src "libresoc.v:140742.5-140742.29" switch \initial - attribute \src "libresoc.v:140743.9-140743.17" + attribute \src "libresoc.v:140742.9-140742.17" case 1'1 case end @@ -225476,14 +225476,14 @@ module \l0$130 sync always update \idx_l$23$next $0\idx_l$23$next[0:0]$6210 end - attribute \src "libresoc.v:140757.3-140766.6" - process $proc$libresoc.v:140757$6213 + attribute \src "libresoc.v:140756.3-140765.6" + process $proc$libresoc.v:140756$6213 assign { } { } assign { } { } assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:140758.5-140758.29" + attribute \src "libresoc.v:140757.5-140757.29" switch \initial - attribute \src "libresoc.v:140758.9-140758.17" + attribute \src "libresoc.v:140757.9-140757.17" case 1'1 case end @@ -225499,14 +225499,14 @@ module \l0$130 sync always update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0] end - attribute \src "libresoc.v:140767.3-140776.6" - process $proc$libresoc.v:140767$6214 + attribute \src "libresoc.v:140766.3-140775.6" + process $proc$libresoc.v:140766$6214 assign { } { } assign { } { } assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:140768.5-140768.29" + attribute \src "libresoc.v:140767.5-140767.29" switch \initial - attribute \src "libresoc.v:140768.9-140768.17" + attribute \src "libresoc.v:140767.9-140767.17" case 1'1 case end @@ -225522,14 +225522,14 @@ module \l0$130 sync always update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0] end - attribute \src "libresoc.v:140777.3-140786.6" - process $proc$libresoc.v:140777$6215 + attribute \src "libresoc.v:140776.3-140785.6" + process $proc$libresoc.v:140776$6215 assign { } { } assign { } { } assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:140778.5-140778.29" + attribute \src "libresoc.v:140777.5-140777.29" switch \initial - attribute \src "libresoc.v:140778.9-140778.17" + attribute \src "libresoc.v:140777.9-140777.17" case 1'1 case end @@ -225545,14 +225545,14 @@ module \l0$130 sync always update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0] end - attribute \src "libresoc.v:140787.3-140796.6" - process $proc$libresoc.v:140787$6216 + attribute \src "libresoc.v:140786.3-140795.6" + process $proc$libresoc.v:140786$6216 assign { } { } assign { } { } assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:140788.5-140788.29" + attribute \src "libresoc.v:140787.5-140787.29" switch \initial - attribute \src "libresoc.v:140788.9-140788.17" + attribute \src "libresoc.v:140787.9-140787.17" case 1'1 case end @@ -225568,14 +225568,14 @@ module \l0$130 sync always update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] end - attribute \src "libresoc.v:140797.3-140806.6" - process $proc$libresoc.v:140797$6217 + attribute \src "libresoc.v:140796.3-140805.6" + process $proc$libresoc.v:140796$6217 assign { } { } assign { } { } assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:140798.5-140798.29" + attribute \src "libresoc.v:140797.5-140797.29" switch \initial - attribute \src "libresoc.v:140798.9-140798.17" + attribute \src "libresoc.v:140797.9-140797.17" case 1'1 case end @@ -225591,14 +225591,14 @@ module \l0$130 sync always update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] end - attribute \src "libresoc.v:140807.3-140821.6" - process $proc$libresoc.v:140807$6218 + attribute \src "libresoc.v:140806.3-140820.6" + process $proc$libresoc.v:140806$6218 assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:140808.5-140808.29" + attribute \src "libresoc.v:140807.5-140807.29" switch \initial - attribute \src "libresoc.v:140808.9-140808.17" + attribute \src "libresoc.v:140807.9-140807.17" case 1'1 case end @@ -225623,14 +225623,14 @@ module \l0$130 sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:140822.3-140831.6" - process $proc$libresoc.v:140822$6219 + attribute \src "libresoc.v:140821.3-140830.6" + process $proc$libresoc.v:140821$6219 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:140823.5-140823.29" + attribute \src "libresoc.v:140822.5-140822.29" switch \initial - attribute \src "libresoc.v:140823.9-140823.17" + attribute \src "libresoc.v:140822.9-140822.17" case 1'1 case end @@ -225646,14 +225646,14 @@ module \l0$130 sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:140832.3-140841.6" - process $proc$libresoc.v:140832$6220 + attribute \src "libresoc.v:140831.3-140840.6" + process $proc$libresoc.v:140831$6220 assign { } { } assign { } { } assign $0\ldst_port0_is_ld_i$8[0:0]$6221 $1\ldst_port0_is_ld_i$8[0:0]$6222 - attribute \src "libresoc.v:140833.5-140833.29" + attribute \src "libresoc.v:140832.5-140832.29" switch \initial - attribute \src "libresoc.v:140833.9-140833.17" + attribute \src "libresoc.v:140832.9-140832.17" case 1'1 case end @@ -225669,14 +225669,14 @@ module \l0$130 sync always update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6221 end - attribute \src "libresoc.v:140842.3-140851.6" - process $proc$libresoc.v:140842$6223 + attribute \src "libresoc.v:140841.3-140850.6" + process $proc$libresoc.v:140841$6223 assign { } { } assign { } { } assign $0\ldst_port0_is_st_i$9[0:0]$6224 $1\ldst_port0_is_st_i$9[0:0]$6225 - attribute \src "libresoc.v:140843.5-140843.29" + attribute \src "libresoc.v:140842.5-140842.29" switch \initial - attribute \src "libresoc.v:140843.9-140843.17" + attribute \src "libresoc.v:140842.9-140842.17" case 1'1 case end @@ -225692,14 +225692,14 @@ module \l0$130 sync always update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6224 end - attribute \src "libresoc.v:140852.3-140861.6" - process $proc$libresoc.v:140852$6226 + attribute \src "libresoc.v:140851.3-140860.6" + process $proc$libresoc.v:140851$6226 assign { } { } assign { } { } assign $0\ldst_port0_data_len$11[3:0]$6227 $1\ldst_port0_data_len$11[3:0]$6228 - attribute \src "libresoc.v:140853.5-140853.29" + attribute \src "libresoc.v:140852.5-140852.29" switch \initial - attribute \src "libresoc.v:140853.9-140853.17" + attribute \src "libresoc.v:140852.9-140852.17" case 1'1 case end @@ -225715,14 +225715,14 @@ module \l0$130 sync always update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6227 end - attribute \src "libresoc.v:140862.3-140871.6" - process $proc$libresoc.v:140862$6229 + attribute \src "libresoc.v:140861.3-140870.6" + process $proc$libresoc.v:140861$6229 assign { } { } assign { } { } assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:140863.5-140863.29" + attribute \src "libresoc.v:140862.5-140862.29" switch \initial - attribute \src "libresoc.v:140863.9-140863.17" + attribute \src "libresoc.v:140862.9-140862.17" case 1'1 case end @@ -225738,10 +225738,10 @@ module \l0$130 sync always update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] end - connect \$20 $or$libresoc.v:140636$6171_Y - connect \$24 $ternary$libresoc.v:140637$6172_Y - connect \$26 $not$libresoc.v:140638$6173_Y - connect \$28 $not$libresoc.v:140639$6174_Y + connect \$20 $or$libresoc.v:140635$6171_Y + connect \$24 $ternary$libresoc.v:140636$6172_Y + connect \$26 $not$libresoc.v:140637$6173_Y + connect \$28 $not$libresoc.v:140638$6174_Y connect \$22 \$24 connect \$32 \ldst_port0_addr_i connect \ldst_port0_go_die_i$30 1'0 @@ -225758,37 +225758,37 @@ module \l0$130 connect \reset_delay$next \reset_l_q_reset connect \pick_i \$20 end -attribute \src "libresoc.v:140891.1-140949.10" +attribute \src "libresoc.v:140890.1-140948.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active" attribute \generator "nMigen" module \ld_active - attribute \src "libresoc.v:140892.7-140892.20" + attribute \src "libresoc.v:140891.7-140891.20" wire $0\initial[0:0] - attribute \src "libresoc.v:140937.3-140945.6" + attribute \src "libresoc.v:140936.3-140944.6" wire $0\q_int$next[0:0]$6244 - attribute \src "libresoc.v:140935.3-140936.27" + attribute \src "libresoc.v:140934.3-140935.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:140937.3-140945.6" + attribute \src "libresoc.v:140936.3-140944.6" wire $1\q_int$next[0:0]$6245 - attribute \src "libresoc.v:140914.7-140914.19" + attribute \src "libresoc.v:140913.7-140913.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:140927.17-140927.96" - wire $and$libresoc.v:140927$6234_Y - attribute \src "libresoc.v:140932.17-140932.96" - wire $and$libresoc.v:140932$6239_Y - attribute \src "libresoc.v:140929.18-140929.99" - wire $not$libresoc.v:140929$6236_Y - attribute \src "libresoc.v:140931.17-140931.98" - wire $not$libresoc.v:140931$6238_Y - attribute \src "libresoc.v:140934.17-140934.98" - wire $not$libresoc.v:140934$6241_Y - attribute \src "libresoc.v:140928.18-140928.104" - wire $or$libresoc.v:140928$6235_Y - attribute \src "libresoc.v:140930.18-140930.105" - wire $or$libresoc.v:140930$6237_Y - attribute \src "libresoc.v:140933.17-140933.103" - wire $or$libresoc.v:140933$6240_Y + attribute \src "libresoc.v:140926.17-140926.96" + wire $and$libresoc.v:140926$6234_Y + attribute \src "libresoc.v:140931.17-140931.96" + wire $and$libresoc.v:140931$6239_Y + attribute \src "libresoc.v:140928.18-140928.99" + wire $not$libresoc.v:140928$6236_Y + attribute \src "libresoc.v:140930.17-140930.98" + wire $not$libresoc.v:140930$6238_Y + attribute \src "libresoc.v:140933.17-140933.98" + wire $not$libresoc.v:140933$6241_Y + attribute \src "libresoc.v:140927.18-140927.104" + wire $or$libresoc.v:140927$6235_Y + attribute \src "libresoc.v:140929.18-140929.105" + wire $or$libresoc.v:140929$6237_Y + attribute \src "libresoc.v:140932.17-140932.103" + wire $or$libresoc.v:140932$6240_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -225809,7 +225809,7 @@ module \ld_active wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:140892.7-140892.15" + attribute \src "libresoc.v:140891.7-140891.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -225826,7 +225826,7 @@ module \ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:140927$6234 + cell $and $and$libresoc.v:140926$6234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225834,10 +225834,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:140927$6234_Y + connect \Y $and$libresoc.v:140926$6234_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:140932$6239 + cell $and $and$libresoc.v:140931$6239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225845,34 +225845,34 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:140932$6239_Y + connect \Y $and$libresoc.v:140931$6239_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:140929$6236 + cell $not $not$libresoc.v:140928$6236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_ld_active - connect \Y $not$libresoc.v:140929$6236_Y + connect \Y $not$libresoc.v:140928$6236_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:140931$6238 + cell $not $not$libresoc.v:140930$6238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:140931$6238_Y + connect \Y $not$libresoc.v:140930$6238_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:140934$6241 + cell $not $not$libresoc.v:140933$6241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:140934$6241_Y + connect \Y $not$libresoc.v:140933$6241_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:140928$6235 + cell $or $or$libresoc.v:140927$6235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225880,10 +225880,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_ld_active - connect \Y $or$libresoc.v:140928$6235_Y + connect \Y $or$libresoc.v:140927$6235_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:140930$6237 + cell $or $or$libresoc.v:140929$6237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225891,10 +225891,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_ld_active connect \B \q_int - connect \Y $or$libresoc.v:140930$6237_Y + connect \Y $or$libresoc.v:140929$6237_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:140933$6240 + cell $or $or$libresoc.v:140932$6240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225902,39 +225902,39 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_ld_active - connect \Y $or$libresoc.v:140933$6240_Y + connect \Y $or$libresoc.v:140932$6240_Y end - attribute \src "libresoc.v:140892.7-140892.20" - process $proc$libresoc.v:140892$6246 + attribute \src "libresoc.v:140891.7-140891.20" + process $proc$libresoc.v:140891$6246 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:140914.7-140914.19" - process $proc$libresoc.v:140914$6247 + attribute \src "libresoc.v:140913.7-140913.19" + process $proc$libresoc.v:140913$6247 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:140935.3-140936.27" - process $proc$libresoc.v:140935$6242 + attribute \src "libresoc.v:140934.3-140935.27" + process $proc$libresoc.v:140934$6242 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:140937.3-140945.6" - process $proc$libresoc.v:140937$6243 + attribute \src "libresoc.v:140936.3-140944.6" + process $proc$libresoc.v:140936$6243 assign { } { } assign { } { } assign $0\q_int$next[0:0]$6244 $1\q_int$next[0:0]$6245 - attribute \src "libresoc.v:140938.5-140938.29" + attribute \src "libresoc.v:140937.5-140937.29" switch \initial - attribute \src "libresoc.v:140938.9-140938.17" + attribute \src "libresoc.v:140937.9-140937.17" case 1'1 case end @@ -225950,565 +225950,565 @@ module \ld_active sync always update \q_int$next $0\q_int$next[0:0]$6244 end - connect \$9 $and$libresoc.v:140927$6234_Y - connect \$11 $or$libresoc.v:140928$6235_Y - connect \$13 $not$libresoc.v:140929$6236_Y - connect \$15 $or$libresoc.v:140930$6237_Y - connect \$1 $not$libresoc.v:140931$6238_Y - connect \$3 $and$libresoc.v:140932$6239_Y - connect \$5 $or$libresoc.v:140933$6240_Y - connect \$7 $not$libresoc.v:140934$6241_Y + connect \$9 $and$libresoc.v:140926$6234_Y + connect \$11 $or$libresoc.v:140927$6235_Y + connect \$13 $not$libresoc.v:140928$6236_Y + connect \$15 $or$libresoc.v:140929$6237_Y + connect \$1 $not$libresoc.v:140930$6238_Y + connect \$3 $and$libresoc.v:140931$6239_Y + connect \$5 $or$libresoc.v:140932$6240_Y + connect \$7 $not$libresoc.v:140933$6241_Y connect \qlq_ld_active \$15 connect \qn_ld_active \$13 connect \q_ld_active \$11 end -attribute \src "libresoc.v:140953.1-142316.10" +attribute \src "libresoc.v:140952.1-142315.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0" attribute \generator "nMigen" module \ldst0 - attribute \src "libresoc.v:141971.3-141979.6" + attribute \src "libresoc.v:141970.3-141978.6" wire $0\adr_l_r_adr$next[0:0]$6390 - attribute \src "libresoc.v:141853.3-141854.39" + attribute \src "libresoc.v:141852.3-141853.39" wire $0\adr_l_r_adr[0:0] - attribute \src "libresoc.v:141799.3-141800.21" + attribute \src "libresoc.v:141798.3-141799.21" wire $0\alu_ok[0:0] - attribute \src "libresoc.v:142136.3-142145.6" + attribute \src "libresoc.v:142135.3-142144.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:142146.3-142155.6" + attribute \src "libresoc.v:142145.3-142154.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:142126.3-142135.6" + attribute \src "libresoc.v:142125.3-142134.6" wire width 64 $0\ea_r$next[63:0]$6478 - attribute \src "libresoc.v:141801.3-141802.25" + attribute \src "libresoc.v:141800.3-141801.25" wire width 64 $0\ea_r[63:0] - attribute \src "libresoc.v:140954.7-140954.20" + attribute \src "libresoc.v:140953.7-140953.20" wire $0\initial[0:0] - attribute \src "libresoc.v:142201.3-142220.6" + attribute \src "libresoc.v:142200.3-142219.6" wire width 64 $0\ldd_o[63:0] - attribute \src "libresoc.v:142165.3-142188.6" + attribute \src "libresoc.v:142164.3-142187.6" wire width 64 $0\lddata_r[63:0] - attribute \src "libresoc.v:142068.3-142077.6" + attribute \src "libresoc.v:142067.3-142076.6" wire width 64 $0\ldo_r$next[63:0]$6463 - attribute \src "libresoc.v:141809.3-141810.27" + attribute \src "libresoc.v:141808.3-141809.27" wire width 64 $0\ldo_r[63:0] - attribute \src "libresoc.v:141797.3-141798.33" + attribute \src "libresoc.v:141796.3-141797.33" wire width 96 $0\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:142156.3-142164.6" + attribute \src "libresoc.v:142155.3-142163.6" wire $0\ldst_port0_addr_i_ok$next[0:0]$6483 - attribute \src "libresoc.v:141795.3-141796.57" + attribute \src "libresoc.v:141794.3-141795.57" wire $0\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:142245.3-142256.6" + attribute \src "libresoc.v:142244.3-142255.6" wire width 64 $0\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:142016.3-142024.6" + attribute \src "libresoc.v:142015.3-142023.6" wire $0\lsd_l_r_lsd$next[0:0]$6405 - attribute \src "libresoc.v:141843.3-141844.39" + attribute \src "libresoc.v:141842.3-141843.39" wire $0\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:141944.3-141952.6" + attribute \src "libresoc.v:141943.3-141951.6" wire $0\opc_l_r_opc$next[0:0]$6381 - attribute \src "libresoc.v:141859.3-141860.39" + attribute \src "libresoc.v:141858.3-141859.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:141935.3-141943.6" + attribute \src "libresoc.v:141934.3-141942.6" wire $0\opc_l_s_opc$next[0:0]$6378 - attribute \src "libresoc.v:141861.3-141862.39" + attribute \src "libresoc.v:141860.3-141861.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $0\oper_r__byte_reverse$next[0:0]$6408 - attribute \src "libresoc.v:141835.3-141836.57" + attribute \src "libresoc.v:141834.3-141835.57" wire $0\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 4 $0\oper_r__data_len$next[3:0]$6409 - attribute \src "libresoc.v:141833.3-141834.49" + attribute \src "libresoc.v:141832.3-141833.49" wire width 4 $0\oper_r__data_len[3:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 14 $0\oper_r__fn_unit$next[13:0]$6410 - attribute \src "libresoc.v:141813.3-141814.47" + attribute \src "libresoc.v:141812.3-141813.47" wire width 14 $0\oper_r__fn_unit[13:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 64 $0\oper_r__imm_data__data$next[63:0]$6411 - attribute \src "libresoc.v:141815.3-141816.61" + attribute \src "libresoc.v:141814.3-141815.61" wire width 64 $0\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $0\oper_r__imm_data__ok$next[0:0]$6412 - attribute \src "libresoc.v:141817.3-141818.57" + attribute \src "libresoc.v:141816.3-141817.57" wire $0\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 32 $0\oper_r__insn$next[31:0]$6413 - attribute \src "libresoc.v:141841.3-141842.41" + attribute \src "libresoc.v:141840.3-141841.41" wire width 32 $0\oper_r__insn[31:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 7 $0\oper_r__insn_type$next[6:0]$6414 - attribute \src "libresoc.v:141811.3-141812.51" + attribute \src "libresoc.v:141810.3-141811.51" wire width 7 $0\oper_r__insn_type[6:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $0\oper_r__is_32bit$next[0:0]$6415 - attribute \src "libresoc.v:141829.3-141830.49" + attribute \src "libresoc.v:141828.3-141829.49" wire $0\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $0\oper_r__is_signed$next[0:0]$6416 - attribute \src "libresoc.v:141831.3-141832.51" + attribute \src "libresoc.v:141830.3-141831.51" wire $0\oper_r__is_signed[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 2 $0\oper_r__ldst_mode$next[1:0]$6417 - attribute \src "libresoc.v:141839.3-141840.51" + attribute \src "libresoc.v:141838.3-141839.51" wire width 2 $0\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $0\oper_r__oe__oe$next[0:0]$6418 - attribute \src "libresoc.v:141825.3-141826.45" + attribute \src "libresoc.v:141824.3-141825.45" wire $0\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $0\oper_r__oe__ok$next[0:0]$6419 - attribute \src "libresoc.v:141827.3-141828.45" + attribute \src "libresoc.v:141826.3-141827.45" wire $0\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $0\oper_r__rc__ok$next[0:0]$6420 - attribute \src "libresoc.v:141823.3-141824.45" + attribute \src "libresoc.v:141822.3-141823.45" wire $0\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $0\oper_r__rc__rc$next[0:0]$6421 - attribute \src "libresoc.v:141821.3-141822.45" + attribute \src "libresoc.v:141820.3-141821.45" wire $0\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $0\oper_r__sign_extend$next[0:0]$6422 - attribute \src "libresoc.v:141837.3-141838.55" + attribute \src "libresoc.v:141836.3-141837.55" wire $0\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $0\oper_r__zero_a$next[0:0]$6423 - attribute \src "libresoc.v:141819.3-141820.45" + attribute \src "libresoc.v:141818.3-141819.45" wire $0\oper_r__zero_a[0:0] - attribute \src "libresoc.v:141863.3-141864.28" + attribute \src "libresoc.v:141862.3-141863.28" wire $0\p_st_go[0:0] - attribute \src "libresoc.v:142189.3-142200.6" + attribute \src "libresoc.v:142188.3-142199.6" wire width 64 $0\revnorev[63:0] - attribute \src "libresoc.v:141962.3-141970.6" + attribute \src "libresoc.v:141961.3-141969.6" wire width 3 $0\src_l_r_src$next[2:0]$6387 - attribute \src "libresoc.v:141855.3-141856.39" + attribute \src "libresoc.v:141854.3-141855.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:141953.3-141961.6" + attribute \src "libresoc.v:141952.3-141960.6" wire width 3 $0\src_l_s_src$next[2:0]$6384 - attribute \src "libresoc.v:141857.3-141858.39" + attribute \src "libresoc.v:141856.3-141857.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:142078.3-142093.6" + attribute \src "libresoc.v:142077.3-142092.6" wire width 64 $0\src_r0$next[63:0]$6466 - attribute \src "libresoc.v:141807.3-141808.29" + attribute \src "libresoc.v:141806.3-141807.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:142094.3-142109.6" + attribute \src "libresoc.v:142093.3-142108.6" wire width 64 $0\src_r1$next[63:0]$6470 - attribute \src "libresoc.v:141805.3-141806.29" + attribute \src "libresoc.v:141804.3-141805.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:142110.3-142125.6" + attribute \src "libresoc.v:142109.3-142124.6" wire width 64 $0\src_r2$next[63:0]$6474 - attribute \src "libresoc.v:141803.3-141804.29" + attribute \src "libresoc.v:141802.3-141803.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:142221.3-142244.6" + attribute \src "libresoc.v:142220.3-142243.6" wire width 64 $0\stdata_r[63:0] - attribute \src "libresoc.v:142007.3-142015.6" + attribute \src "libresoc.v:142006.3-142014.6" wire $0\sto_l_r_sto$next[0:0]$6402 - attribute \src "libresoc.v:141845.3-141846.39" + attribute \src "libresoc.v:141844.3-141845.39" wire $0\sto_l_r_sto[0:0] - attribute \src "libresoc.v:141998.3-142006.6" + attribute \src "libresoc.v:141997.3-142005.6" wire $0\upd_l_r_upd$next[0:0]$6399 - attribute \src "libresoc.v:141847.3-141848.39" + attribute \src "libresoc.v:141846.3-141847.39" wire $0\upd_l_r_upd[0:0] - attribute \src "libresoc.v:141989.3-141997.6" + attribute \src "libresoc.v:141988.3-141996.6" wire $0\upd_l_s_upd$next[0:0]$6396 - attribute \src "libresoc.v:141849.3-141850.39" + attribute \src "libresoc.v:141848.3-141849.39" wire $0\upd_l_s_upd[0:0] - attribute \src "libresoc.v:141980.3-141988.6" + attribute \src "libresoc.v:141979.3-141987.6" wire $0\wri_l_r_wri$next[0:0]$6393 - attribute \src "libresoc.v:141851.3-141852.39" + attribute \src "libresoc.v:141850.3-141851.39" wire $0\wri_l_r_wri[0:0] - attribute \src "libresoc.v:141971.3-141979.6" + attribute \src "libresoc.v:141970.3-141978.6" wire $1\adr_l_r_adr$next[0:0]$6391 - attribute \src "libresoc.v:141150.7-141150.25" + attribute \src "libresoc.v:141149.7-141149.25" wire $1\adr_l_r_adr[0:0] - attribute \src "libresoc.v:141164.7-141164.20" + attribute \src "libresoc.v:141163.7-141163.20" wire $1\alu_ok[0:0] - attribute \src "libresoc.v:142136.3-142145.6" + attribute \src "libresoc.v:142135.3-142144.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:142146.3-142155.6" + attribute \src "libresoc.v:142145.3-142154.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:142126.3-142135.6" + attribute \src "libresoc.v:142125.3-142134.6" wire width 64 $1\ea_r$next[63:0]$6479 - attribute \src "libresoc.v:141210.14-141210.41" + attribute \src "libresoc.v:141209.14-141209.41" wire width 64 $1\ea_r[63:0] - attribute \src "libresoc.v:142201.3-142220.6" + attribute \src "libresoc.v:142200.3-142219.6" wire width 64 $1\ldd_o[63:0] - attribute \src "libresoc.v:142165.3-142188.6" + attribute \src "libresoc.v:142164.3-142187.6" wire width 64 $1\lddata_r[63:0] - attribute \src "libresoc.v:142068.3-142077.6" + attribute \src "libresoc.v:142067.3-142076.6" wire width 64 $1\ldo_r$next[63:0]$6464 - attribute \src "libresoc.v:141240.14-141240.42" + attribute \src "libresoc.v:141239.14-141239.42" wire width 64 $1\ldo_r[63:0] - attribute \src "libresoc.v:141245.14-141245.62" + attribute \src "libresoc.v:141244.14-141244.62" wire width 96 $1\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:142156.3-142164.6" + attribute \src "libresoc.v:142155.3-142163.6" wire $1\ldst_port0_addr_i_ok$next[0:0]$6484 - attribute \src "libresoc.v:141250.7-141250.34" + attribute \src "libresoc.v:141249.7-141249.34" wire $1\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:142245.3-142256.6" + attribute \src "libresoc.v:142244.3-142255.6" wire width 64 $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:142016.3-142024.6" + attribute \src "libresoc.v:142015.3-142023.6" wire $1\lsd_l_r_lsd$next[0:0]$6406 - attribute \src "libresoc.v:141299.7-141299.25" + attribute \src "libresoc.v:141298.7-141298.25" wire $1\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:141944.3-141952.6" + attribute \src "libresoc.v:141943.3-141951.6" wire $1\opc_l_r_opc$next[0:0]$6382 - attribute \src "libresoc.v:141313.7-141313.25" + attribute \src "libresoc.v:141312.7-141312.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:141935.3-141943.6" + attribute \src "libresoc.v:141934.3-141942.6" wire $1\opc_l_s_opc$next[0:0]$6379 - attribute \src "libresoc.v:141317.7-141317.25" + attribute \src "libresoc.v:141316.7-141316.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $1\oper_r__byte_reverse$next[0:0]$6424 - attribute \src "libresoc.v:141448.7-141448.34" + attribute \src "libresoc.v:141447.7-141447.34" wire $1\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 4 $1\oper_r__data_len$next[3:0]$6425 - attribute \src "libresoc.v:141452.13-141452.36" + attribute \src "libresoc.v:141451.13-141451.36" wire width 4 $1\oper_r__data_len[3:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 14 $1\oper_r__fn_unit$next[13:0]$6426 - attribute \src "libresoc.v:141471.14-141471.40" + attribute \src "libresoc.v:141470.14-141470.40" wire width 14 $1\oper_r__fn_unit[13:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 64 $1\oper_r__imm_data__data$next[63:0]$6427 - attribute \src "libresoc.v:141475.14-141475.59" + attribute \src "libresoc.v:141474.14-141474.59" wire width 64 $1\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $1\oper_r__imm_data__ok$next[0:0]$6428 - attribute \src "libresoc.v:141479.7-141479.34" + attribute \src "libresoc.v:141478.7-141478.34" wire $1\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 32 $1\oper_r__insn$next[31:0]$6429 - attribute \src "libresoc.v:141483.14-141483.34" + attribute \src "libresoc.v:141482.14-141482.34" wire width 32 $1\oper_r__insn[31:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 7 $1\oper_r__insn_type$next[6:0]$6430 - attribute \src "libresoc.v:141562.13-141562.38" + attribute \src "libresoc.v:141561.13-141561.38" wire width 7 $1\oper_r__insn_type[6:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $1\oper_r__is_32bit$next[0:0]$6431 - attribute \src "libresoc.v:141566.7-141566.30" + attribute \src "libresoc.v:141565.7-141565.30" wire $1\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $1\oper_r__is_signed$next[0:0]$6432 - attribute \src "libresoc.v:141570.7-141570.31" + attribute \src "libresoc.v:141569.7-141569.31" wire $1\oper_r__is_signed[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 2 $1\oper_r__ldst_mode$next[1:0]$6433 - attribute \src "libresoc.v:141579.13-141579.37" + attribute \src "libresoc.v:141578.13-141578.37" wire width 2 $1\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $1\oper_r__oe__oe$next[0:0]$6434 - attribute \src "libresoc.v:141583.7-141583.28" + attribute \src "libresoc.v:141582.7-141582.28" wire $1\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $1\oper_r__oe__ok$next[0:0]$6435 - attribute \src "libresoc.v:141587.7-141587.28" + attribute \src "libresoc.v:141586.7-141586.28" wire $1\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $1\oper_r__rc__ok$next[0:0]$6436 - attribute \src "libresoc.v:141591.7-141591.28" + attribute \src "libresoc.v:141590.7-141590.28" wire $1\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $1\oper_r__rc__rc$next[0:0]$6437 - attribute \src "libresoc.v:141595.7-141595.28" + attribute \src "libresoc.v:141594.7-141594.28" wire $1\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $1\oper_r__sign_extend$next[0:0]$6438 - attribute \src "libresoc.v:141599.7-141599.33" + attribute \src "libresoc.v:141598.7-141598.33" wire $1\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $1\oper_r__zero_a$next[0:0]$6439 - attribute \src "libresoc.v:141603.7-141603.28" + attribute \src "libresoc.v:141602.7-141602.28" wire $1\oper_r__zero_a[0:0] - attribute \src "libresoc.v:141607.7-141607.21" + attribute \src "libresoc.v:141606.7-141606.21" wire $1\p_st_go[0:0] - attribute \src "libresoc.v:142189.3-142200.6" + attribute \src "libresoc.v:142188.3-142199.6" wire width 64 $1\revnorev[63:0] - attribute \src "libresoc.v:141962.3-141970.6" + attribute \src "libresoc.v:141961.3-141969.6" wire width 3 $1\src_l_r_src$next[2:0]$6388 - attribute \src "libresoc.v:141649.13-141649.31" + attribute \src "libresoc.v:141648.13-141648.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:141953.3-141961.6" + attribute \src "libresoc.v:141952.3-141960.6" wire width 3 $1\src_l_s_src$next[2:0]$6385 - attribute \src "libresoc.v:141653.13-141653.31" + attribute \src "libresoc.v:141652.13-141652.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:142078.3-142093.6" + attribute \src "libresoc.v:142077.3-142092.6" wire width 64 $1\src_r0$next[63:0]$6467 - attribute \src "libresoc.v:141657.14-141657.43" + attribute \src "libresoc.v:141656.14-141656.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:142094.3-142109.6" + attribute \src "libresoc.v:142093.3-142108.6" wire width 64 $1\src_r1$next[63:0]$6471 - attribute \src "libresoc.v:141661.14-141661.43" + attribute \src "libresoc.v:141660.14-141660.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:142110.3-142125.6" + attribute \src "libresoc.v:142109.3-142124.6" wire width 64 $1\src_r2$next[63:0]$6475 - attribute \src "libresoc.v:141665.14-141665.43" + attribute \src "libresoc.v:141664.14-141664.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:142221.3-142244.6" + attribute \src "libresoc.v:142220.3-142243.6" wire width 64 $1\stdata_r[63:0] - attribute \src "libresoc.v:142007.3-142015.6" + attribute \src "libresoc.v:142006.3-142014.6" wire $1\sto_l_r_sto$next[0:0]$6403 - attribute \src "libresoc.v:141675.7-141675.25" + attribute \src "libresoc.v:141674.7-141674.25" wire $1\sto_l_r_sto[0:0] - attribute \src "libresoc.v:141998.3-142006.6" + attribute \src "libresoc.v:141997.3-142005.6" wire $1\upd_l_r_upd$next[0:0]$6400 - attribute \src "libresoc.v:141685.7-141685.25" + attribute \src "libresoc.v:141684.7-141684.25" wire $1\upd_l_r_upd[0:0] - attribute \src "libresoc.v:141989.3-141997.6" + attribute \src "libresoc.v:141988.3-141996.6" wire $1\upd_l_s_upd$next[0:0]$6397 - attribute \src "libresoc.v:141689.7-141689.25" + attribute \src "libresoc.v:141688.7-141688.25" wire $1\upd_l_s_upd[0:0] - attribute \src "libresoc.v:141980.3-141988.6" + attribute \src "libresoc.v:141979.3-141987.6" wire $1\wri_l_r_wri$next[0:0]$6394 - attribute \src "libresoc.v:141699.7-141699.25" + attribute \src "libresoc.v:141698.7-141698.25" wire $1\wri_l_r_wri[0:0] - attribute \src "libresoc.v:142201.3-142220.6" + attribute \src "libresoc.v:142200.3-142219.6" wire width 64 $2\ldd_o[63:0] - attribute \src "libresoc.v:142165.3-142188.6" + attribute \src "libresoc.v:142164.3-142187.6" wire width 64 $2\lddata_r[63:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $2\oper_r__byte_reverse$next[0:0]$6440 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 4 $2\oper_r__data_len$next[3:0]$6441 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 14 $2\oper_r__fn_unit$next[13:0]$6442 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 64 $2\oper_r__imm_data__data$next[63:0]$6443 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $2\oper_r__imm_data__ok$next[0:0]$6444 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 32 $2\oper_r__insn$next[31:0]$6445 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 7 $2\oper_r__insn_type$next[6:0]$6446 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $2\oper_r__is_32bit$next[0:0]$6447 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $2\oper_r__is_signed$next[0:0]$6448 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 2 $2\oper_r__ldst_mode$next[1:0]$6449 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $2\oper_r__oe__oe$next[0:0]$6450 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $2\oper_r__oe__ok$next[0:0]$6451 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $2\oper_r__rc__ok$next[0:0]$6452 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $2\oper_r__rc__rc$next[0:0]$6453 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $2\oper_r__sign_extend$next[0:0]$6454 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $2\oper_r__zero_a$next[0:0]$6455 - attribute \src "libresoc.v:142078.3-142093.6" + attribute \src "libresoc.v:142077.3-142092.6" wire width 64 $2\src_r0$next[63:0]$6468 - attribute \src "libresoc.v:142094.3-142109.6" + attribute \src "libresoc.v:142093.3-142108.6" wire width 64 $2\src_r1$next[63:0]$6472 - attribute \src "libresoc.v:142110.3-142125.6" + attribute \src "libresoc.v:142109.3-142124.6" wire width 64 $2\src_r2$next[63:0]$6476 - attribute \src "libresoc.v:142221.3-142244.6" + attribute \src "libresoc.v:142220.3-142243.6" wire width 64 $2\stdata_r[63:0] - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire width 64 $3\oper_r__imm_data__data$next[63:0]$6456 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $3\oper_r__imm_data__ok$next[0:0]$6457 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $3\oper_r__oe__oe$next[0:0]$6458 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $3\oper_r__oe__ok$next[0:0]$6459 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $3\oper_r__rc__ok$next[0:0]$6460 - attribute \src "libresoc.v:142025.3-142067.6" + attribute \src "libresoc.v:142024.3-142066.6" wire $3\oper_r__rc__rc$next[0:0]$6461 - attribute \src "libresoc.v:141781.18-141781.124" - wire width 65 $add$libresoc.v:141781$6328_Y - attribute \src "libresoc.v:141704.19-141704.118" - wire $and$libresoc.v:141704$6248_Y - attribute \src "libresoc.v:141705.19-141705.125" - wire $and$libresoc.v:141705$6249_Y - attribute \src "libresoc.v:141706.19-141706.120" - wire $and$libresoc.v:141706$6250_Y - attribute \src "libresoc.v:141707.19-141707.125" - wire $and$libresoc.v:141707$6251_Y - attribute \src "libresoc.v:141708.19-141708.118" - wire $and$libresoc.v:141708$6252_Y - attribute \src "libresoc.v:141710.19-141710.119" - wire $and$libresoc.v:141710$6254_Y + attribute \src "libresoc.v:141780.18-141780.124" + wire width 65 $add$libresoc.v:141780$6328_Y + attribute \src "libresoc.v:141703.19-141703.118" + wire $and$libresoc.v:141703$6248_Y + attribute \src "libresoc.v:141704.19-141704.125" + wire $and$libresoc.v:141704$6249_Y + attribute \src "libresoc.v:141705.19-141705.120" + wire $and$libresoc.v:141705$6250_Y + attribute \src "libresoc.v:141706.19-141706.125" + wire $and$libresoc.v:141706$6251_Y + attribute \src "libresoc.v:141707.19-141707.118" + wire $and$libresoc.v:141707$6252_Y + attribute \src "libresoc.v:141709.19-141709.119" + wire $and$libresoc.v:141709$6254_Y + attribute \src "libresoc.v:141710.19-141710.123" + wire $and$libresoc.v:141710$6255_Y attribute \src "libresoc.v:141711.19-141711.123" - wire $and$libresoc.v:141711$6255_Y - attribute \src "libresoc.v:141712.19-141712.123" - wire $and$libresoc.v:141712$6256_Y - attribute \src "libresoc.v:141713.19-141713.120" - wire $and$libresoc.v:141713$6257_Y - attribute \src "libresoc.v:141714.19-141714.123" - wire $and$libresoc.v:141714$6258_Y - attribute \src "libresoc.v:141715.19-141715.119" - wire $and$libresoc.v:141715$6259_Y - attribute \src "libresoc.v:141716.19-141716.123" - wire $and$libresoc.v:141716$6260_Y - attribute \src "libresoc.v:141717.19-141717.125" - wire $and$libresoc.v:141717$6261_Y - attribute \src "libresoc.v:141719.19-141719.116" - wire $and$libresoc.v:141719$6263_Y - attribute \src "libresoc.v:141721.19-141721.120" - wire $and$libresoc.v:141721$6265_Y - attribute \src "libresoc.v:141722.19-141722.123" - wire $and$libresoc.v:141722$6266_Y - attribute \src "libresoc.v:141726.19-141726.125" - wire $and$libresoc.v:141726$6270_Y - attribute \src "libresoc.v:141727.19-141727.123" - wire $and$libresoc.v:141727$6271_Y - attribute \src "libresoc.v:141732.19-141732.116" - wire $and$libresoc.v:141732$6276_Y - attribute \src "libresoc.v:141734.19-141734.116" - wire $and$libresoc.v:141734$6278_Y - attribute \src "libresoc.v:141737.19-141737.118" - wire $and$libresoc.v:141737$6281_Y - attribute \src "libresoc.v:141739.19-141739.125" - wire $and$libresoc.v:141739$6283_Y - attribute \src "libresoc.v:141742.19-141742.160" - wire width 3 $and$libresoc.v:141742$6286_Y + wire $and$libresoc.v:141711$6256_Y + attribute \src "libresoc.v:141712.19-141712.120" + wire $and$libresoc.v:141712$6257_Y + attribute \src "libresoc.v:141713.19-141713.123" + wire $and$libresoc.v:141713$6258_Y + attribute \src "libresoc.v:141714.19-141714.119" + wire $and$libresoc.v:141714$6259_Y + attribute \src "libresoc.v:141715.19-141715.123" + wire $and$libresoc.v:141715$6260_Y + attribute \src "libresoc.v:141716.19-141716.125" + wire $and$libresoc.v:141716$6261_Y + attribute \src "libresoc.v:141718.19-141718.116" + wire $and$libresoc.v:141718$6263_Y + attribute \src "libresoc.v:141720.19-141720.120" + wire $and$libresoc.v:141720$6265_Y + attribute \src "libresoc.v:141721.19-141721.123" + wire $and$libresoc.v:141721$6266_Y + attribute \src "libresoc.v:141725.19-141725.125" + wire $and$libresoc.v:141725$6270_Y + attribute \src "libresoc.v:141726.19-141726.123" + wire $and$libresoc.v:141726$6271_Y + attribute \src "libresoc.v:141731.19-141731.116" + wire $and$libresoc.v:141731$6276_Y + attribute \src "libresoc.v:141733.19-141733.116" + wire $and$libresoc.v:141733$6278_Y + attribute \src "libresoc.v:141736.19-141736.118" + wire $and$libresoc.v:141736$6281_Y + attribute \src "libresoc.v:141738.19-141738.125" + wire $and$libresoc.v:141738$6283_Y + attribute \src "libresoc.v:141741.19-141741.160" + wire width 3 $and$libresoc.v:141741$6286_Y + attribute \src "libresoc.v:141742.19-141742.122" + wire $and$libresoc.v:141742$6287_Y attribute \src "libresoc.v:141743.19-141743.122" - wire $and$libresoc.v:141743$6287_Y - attribute \src "libresoc.v:141744.19-141744.122" - wire $and$libresoc.v:141744$6288_Y - attribute \src "libresoc.v:141746.19-141746.122" - wire $and$libresoc.v:141746$6291_Y + wire $and$libresoc.v:141743$6288_Y + attribute \src "libresoc.v:141745.19-141745.122" + wire $and$libresoc.v:141745$6291_Y + attribute \src "libresoc.v:141757.18-141757.123" + wire $and$libresoc.v:141757$6305_Y attribute \src "libresoc.v:141758.18-141758.123" - wire $and$libresoc.v:141758$6305_Y - attribute \src "libresoc.v:141759.18-141759.123" - wire $and$libresoc.v:141759$6306_Y - attribute \src "libresoc.v:141761.18-141761.114" - wire $and$libresoc.v:141761$6308_Y - attribute \src "libresoc.v:141763.18-141763.113" - wire $and$libresoc.v:141763$6310_Y - attribute \src "libresoc.v:141766.18-141766.113" - wire $and$libresoc.v:141766$6313_Y - attribute \src "libresoc.v:141770.18-141770.113" - wire $and$libresoc.v:141770$6317_Y - attribute \src "libresoc.v:141773.18-141773.119" - wire $and$libresoc.v:141773$6320_Y - attribute \src "libresoc.v:141782.18-141782.150" - wire width 3 $and$libresoc.v:141782$6329_Y - attribute \src "libresoc.v:141784.18-141784.113" - wire width 3 $and$libresoc.v:141784$6331_Y - attribute \src "libresoc.v:141786.18-141786.113" - wire width 3 $and$libresoc.v:141786$6333_Y - attribute \src "libresoc.v:141787.18-141787.127" - wire $and$libresoc.v:141787$6334_Y - attribute \src "libresoc.v:141788.18-141788.117" - wire $and$libresoc.v:141788$6335_Y - attribute \src "libresoc.v:141793.18-141793.117" - wire $and$libresoc.v:141793$6340_Y - attribute \src "libresoc.v:141718.19-141718.127" - wire $eq$libresoc.v:141718$6262_Y - attribute \src "libresoc.v:141738.19-141738.127" - wire $eq$libresoc.v:141738$6282_Y - attribute \src "libresoc.v:141740.19-141740.127" - wire $eq$libresoc.v:141740$6284_Y - attribute \src "libresoc.v:141751.19-141751.126" - wire $eq$libresoc.v:141751$6297_Y + wire $and$libresoc.v:141758$6306_Y + attribute \src "libresoc.v:141760.18-141760.114" + wire $and$libresoc.v:141760$6308_Y + attribute \src "libresoc.v:141762.18-141762.113" + wire $and$libresoc.v:141762$6310_Y + attribute \src "libresoc.v:141765.18-141765.113" + wire $and$libresoc.v:141765$6313_Y + attribute \src "libresoc.v:141769.18-141769.113" + wire $and$libresoc.v:141769$6317_Y + attribute \src "libresoc.v:141772.18-141772.119" + wire $and$libresoc.v:141772$6320_Y + attribute \src "libresoc.v:141781.18-141781.150" + wire width 3 $and$libresoc.v:141781$6329_Y + attribute \src "libresoc.v:141783.18-141783.113" + wire width 3 $and$libresoc.v:141783$6331_Y + attribute \src "libresoc.v:141785.18-141785.113" + wire width 3 $and$libresoc.v:141785$6333_Y + attribute \src "libresoc.v:141786.18-141786.127" + wire $and$libresoc.v:141786$6334_Y + attribute \src "libresoc.v:141787.18-141787.117" + wire $and$libresoc.v:141787$6335_Y + attribute \src "libresoc.v:141792.18-141792.117" + wire $and$libresoc.v:141792$6340_Y + attribute \src "libresoc.v:141717.19-141717.127" + wire $eq$libresoc.v:141717$6262_Y + attribute \src "libresoc.v:141737.19-141737.127" + wire $eq$libresoc.v:141737$6282_Y + attribute \src "libresoc.v:141739.19-141739.127" + wire $eq$libresoc.v:141739$6284_Y + attribute \src "libresoc.v:141750.19-141750.126" + wire $eq$libresoc.v:141750$6297_Y + attribute \src "libresoc.v:141755.18-141755.127" + wire $eq$libresoc.v:141755$6303_Y attribute \src "libresoc.v:141756.18-141756.127" - wire $eq$libresoc.v:141756$6303_Y - attribute \src "libresoc.v:141757.18-141757.127" - wire $eq$libresoc.v:141757$6304_Y - attribute \src "libresoc.v:141765.18-141765.126" - wire $eq$libresoc.v:141765$6312_Y - attribute \src "libresoc.v:141769.18-141769.126" - wire $eq$libresoc.v:141769$6316_Y - attribute \src "libresoc.v:141745.19-141745.110" - wire width 96 $extend$libresoc.v:141745$6289_Y - attribute \src "libresoc.v:141747.19-141747.116" - wire width 64 $extend$libresoc.v:141747$6292_Y - attribute \src "libresoc.v:141752.19-141752.102" - wire width 64 $extend$libresoc.v:141752$6298_Y - attribute \src "libresoc.v:141730.19-141730.109" - wire $not$libresoc.v:141730$6274_Y - attribute \src "libresoc.v:141735.19-141735.121" - wire $not$libresoc.v:141735$6279_Y - attribute \src "libresoc.v:141760.18-141760.112" - wire $not$libresoc.v:141760$6307_Y - attribute \src "libresoc.v:141762.18-141762.110" - wire $not$libresoc.v:141762$6309_Y - attribute \src "libresoc.v:141764.18-141764.120" - wire $not$libresoc.v:141764$6311_Y - attribute \src "libresoc.v:141768.18-141768.120" - wire $not$libresoc.v:141768$6315_Y - attribute \src "libresoc.v:141783.18-141783.143" - wire width 2 $not$libresoc.v:141783$6330_Y - attribute \src "libresoc.v:141785.18-141785.115" - wire width 3 $not$libresoc.v:141785$6332_Y - attribute \src "libresoc.v:141792.18-141792.107" - wire $not$libresoc.v:141792$6339_Y - attribute \src "libresoc.v:141794.18-141794.118" - wire $not$libresoc.v:141794$6341_Y - attribute \src "libresoc.v:141709.18-141709.124" - wire $or$libresoc.v:141709$6253_Y - attribute \src "libresoc.v:141720.18-141720.129" - wire $or$libresoc.v:141720$6264_Y - attribute \src "libresoc.v:141723.19-141723.123" - wire $or$libresoc.v:141723$6267_Y + wire $eq$libresoc.v:141756$6304_Y + attribute \src "libresoc.v:141764.18-141764.126" + wire $eq$libresoc.v:141764$6312_Y + attribute \src "libresoc.v:141768.18-141768.126" + wire $eq$libresoc.v:141768$6316_Y + attribute \src "libresoc.v:141744.19-141744.110" + wire width 96 $extend$libresoc.v:141744$6289_Y + attribute \src "libresoc.v:141746.19-141746.116" + wire width 64 $extend$libresoc.v:141746$6292_Y + attribute \src "libresoc.v:141751.19-141751.102" + wire width 64 $extend$libresoc.v:141751$6298_Y + attribute \src "libresoc.v:141729.19-141729.109" + wire $not$libresoc.v:141729$6274_Y + attribute \src "libresoc.v:141734.19-141734.121" + wire $not$libresoc.v:141734$6279_Y + attribute \src "libresoc.v:141759.18-141759.112" + wire $not$libresoc.v:141759$6307_Y + attribute \src "libresoc.v:141761.18-141761.110" + wire $not$libresoc.v:141761$6309_Y + attribute \src "libresoc.v:141763.18-141763.120" + wire $not$libresoc.v:141763$6311_Y + attribute \src "libresoc.v:141767.18-141767.120" + wire $not$libresoc.v:141767$6315_Y + attribute \src "libresoc.v:141782.18-141782.143" + wire width 2 $not$libresoc.v:141782$6330_Y + attribute \src "libresoc.v:141784.18-141784.115" + wire width 3 $not$libresoc.v:141784$6332_Y + attribute \src "libresoc.v:141791.18-141791.107" + wire $not$libresoc.v:141791$6339_Y + attribute \src "libresoc.v:141793.18-141793.118" + wire $not$libresoc.v:141793$6341_Y + attribute \src "libresoc.v:141708.18-141708.124" + wire $or$libresoc.v:141708$6253_Y + attribute \src "libresoc.v:141719.18-141719.129" + wire $or$libresoc.v:141719$6264_Y + attribute \src "libresoc.v:141722.19-141722.123" + wire $or$libresoc.v:141722$6267_Y + attribute \src "libresoc.v:141723.19-141723.125" + wire $or$libresoc.v:141723$6268_Y attribute \src "libresoc.v:141724.19-141724.125" - wire $or$libresoc.v:141724$6268_Y - attribute \src "libresoc.v:141725.19-141725.125" - wire $or$libresoc.v:141725$6269_Y - attribute \src "libresoc.v:141728.19-141728.132" - wire $or$libresoc.v:141728$6272_Y - attribute \src "libresoc.v:141729.19-141729.126" - wire $or$libresoc.v:141729$6273_Y - attribute \src "libresoc.v:141731.18-141731.129" - wire $or$libresoc.v:141731$6275_Y - attribute \src "libresoc.v:141733.19-141733.125" - wire $or$libresoc.v:141733$6277_Y - attribute \src "libresoc.v:141736.19-141736.119" - wire $or$libresoc.v:141736$6280_Y - attribute \src "libresoc.v:141741.18-141741.126" - wire $or$libresoc.v:141741$6285_Y - attribute \src "libresoc.v:141749.18-141749.156" - wire width 3 $or$libresoc.v:141749$6295_Y - attribute \src "libresoc.v:141755.18-141755.126" - wire $or$libresoc.v:141755$6302_Y - attribute \src "libresoc.v:141767.18-141767.116" - wire $or$libresoc.v:141767$6314_Y - attribute \src "libresoc.v:141771.18-141771.116" - wire $or$libresoc.v:141771$6318_Y - attribute \src "libresoc.v:141772.18-141772.127" - wire width 2 $or$libresoc.v:141772$6319_Y + wire $or$libresoc.v:141724$6269_Y + attribute \src "libresoc.v:141727.19-141727.132" + wire $or$libresoc.v:141727$6272_Y + attribute \src "libresoc.v:141728.19-141728.126" + wire $or$libresoc.v:141728$6273_Y + attribute \src "libresoc.v:141730.18-141730.129" + wire $or$libresoc.v:141730$6275_Y + attribute \src "libresoc.v:141732.19-141732.125" + wire $or$libresoc.v:141732$6277_Y + attribute \src "libresoc.v:141735.19-141735.119" + wire $or$libresoc.v:141735$6280_Y + attribute \src "libresoc.v:141740.18-141740.126" + wire $or$libresoc.v:141740$6285_Y + attribute \src "libresoc.v:141748.18-141748.156" + wire width 3 $or$libresoc.v:141748$6295_Y + attribute \src "libresoc.v:141754.18-141754.126" + wire $or$libresoc.v:141754$6302_Y + attribute \src "libresoc.v:141766.18-141766.116" + wire $or$libresoc.v:141766$6314_Y + attribute \src "libresoc.v:141770.18-141770.116" + wire $or$libresoc.v:141770$6318_Y + attribute \src "libresoc.v:141771.18-141771.127" + wire width 2 $or$libresoc.v:141771$6319_Y + attribute \src "libresoc.v:141773.18-141773.118" + wire $or$libresoc.v:141773$6321_Y attribute \src "libresoc.v:141774.18-141774.118" - wire $or$libresoc.v:141774$6321_Y - attribute \src "libresoc.v:141775.18-141775.118" - wire $or$libresoc.v:141775$6322_Y - attribute \src "libresoc.v:141776.18-141776.114" - wire $or$libresoc.v:141776$6323_Y - attribute \src "libresoc.v:141789.17-141789.124" - wire $or$libresoc.v:141789$6336_Y - attribute \src "libresoc.v:141790.18-141790.132" - wire $or$libresoc.v:141790$6337_Y - attribute \src "libresoc.v:141791.18-141791.134" - wire $or$libresoc.v:141791$6338_Y - attribute \src "libresoc.v:141745.19-141745.110" - wire width 96 $pos$libresoc.v:141745$6290_Y - attribute \src "libresoc.v:141747.19-141747.116" - wire width 64 $pos$libresoc.v:141747$6293_Y - attribute \src "libresoc.v:141748.19-141748.148" - wire width 64 $pos$libresoc.v:141748$6294_Y - attribute \src "libresoc.v:141750.19-141750.206" - wire width 64 $pos$libresoc.v:141750$6296_Y - attribute \src "libresoc.v:141752.19-141752.102" - wire width 64 $pos$libresoc.v:141752$6299_Y - attribute \src "libresoc.v:141753.19-141753.120" - wire width 64 $pos$libresoc.v:141753$6300_Y - attribute \src "libresoc.v:141754.19-141754.150" - wire width 64 $pos$libresoc.v:141754$6301_Y - attribute \src "libresoc.v:141777.18-141777.107" - wire width 64 $ternary$libresoc.v:141777$6324_Y - attribute \src "libresoc.v:141778.18-141778.112" - wire width 64 $ternary$libresoc.v:141778$6325_Y - attribute \src "libresoc.v:141779.18-141779.147" - wire width 64 $ternary$libresoc.v:141779$6326_Y - attribute \src "libresoc.v:141780.18-141780.155" - wire width 64 $ternary$libresoc.v:141780$6327_Y + wire $or$libresoc.v:141774$6322_Y + attribute \src "libresoc.v:141775.18-141775.114" + wire $or$libresoc.v:141775$6323_Y + attribute \src "libresoc.v:141788.17-141788.124" + wire $or$libresoc.v:141788$6336_Y + attribute \src "libresoc.v:141789.18-141789.132" + wire $or$libresoc.v:141789$6337_Y + attribute \src "libresoc.v:141790.18-141790.134" + wire $or$libresoc.v:141790$6338_Y + attribute \src "libresoc.v:141744.19-141744.110" + wire width 96 $pos$libresoc.v:141744$6290_Y + attribute \src "libresoc.v:141746.19-141746.116" + wire width 64 $pos$libresoc.v:141746$6293_Y + attribute \src "libresoc.v:141747.19-141747.148" + wire width 64 $pos$libresoc.v:141747$6294_Y + attribute \src "libresoc.v:141749.19-141749.206" + wire width 64 $pos$libresoc.v:141749$6296_Y + attribute \src "libresoc.v:141751.19-141751.102" + wire width 64 $pos$libresoc.v:141751$6299_Y + attribute \src "libresoc.v:141752.19-141752.120" + wire width 64 $pos$libresoc.v:141752$6300_Y + attribute \src "libresoc.v:141753.19-141753.150" + wire width 64 $pos$libresoc.v:141753$6301_Y + attribute \src "libresoc.v:141776.18-141776.107" + wire width 64 $ternary$libresoc.v:141776$6324_Y + attribute \src "libresoc.v:141777.18-141777.112" + wire width 64 $ternary$libresoc.v:141777$6325_Y + attribute \src "libresoc.v:141778.18-141778.147" + wire width 64 $ternary$libresoc.v:141778$6326_Y + attribute \src "libresoc.v:141779.18-141779.155" + wire width 64 $ternary$libresoc.v:141779$6327_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" @@ -226783,7 +226783,7 @@ module \ldst0 wire \exc_$signal$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \exc_$signal$185 - attribute \src "libresoc.v:140954.7-140954.15" + attribute \src "libresoc.v:140953.7-140953.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" wire \ld_o @@ -227258,7 +227258,7 @@ module \ldst0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \wri_l_s_wri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" - cell $add $add$libresoc.v:141781$6328 + cell $add $add$libresoc.v:141780$6328 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -227266,10 +227266,10 @@ module \ldst0 parameter \Y_WIDTH 65 connect \A \src1_or_z connect \B \src2_or_imm - connect \Y $add$libresoc.v:141781$6328_Y + connect \Y $add$libresoc.v:141780$6328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $and $and$libresoc.v:141704$6248 + cell $and $and$libresoc.v:141703$6248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227277,10 +227277,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \$98 - connect \Y $and$libresoc.v:141704$6248_Y + connect \Y $and$libresoc.v:141703$6248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:141705$6249 + cell $and $and$libresoc.v:141704$6249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227288,10 +227288,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \adr_l_q_adr - connect \Y $and$libresoc.v:141705$6249_Y + connect \Y $and$libresoc.v:141704$6249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:141706$6250 + cell $and $and$libresoc.v:141705$6250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227299,10 +227299,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$102 connect \B \cu_busy_o - connect \Y $and$libresoc.v:141706$6250_Y + connect \Y $and$libresoc.v:141705$6250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:141707$6251 + cell $and $and$libresoc.v:141706$6251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227310,10 +227310,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \sto_l_q_sto connect \B \cu_busy_o - connect \Y $and$libresoc.v:141707$6251_Y + connect \Y $and$libresoc.v:141706$6251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:141708$6252 + cell $and $and$libresoc.v:141707$6252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227321,10 +227321,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$106 connect \B \rd_done - connect \Y $and$libresoc.v:141708$6252_Y + connect \Y $and$libresoc.v:141707$6252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:141710$6254 + cell $and $and$libresoc.v:141709$6254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227332,10 +227332,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$108 connect \B \op_is_st - connect \Y $and$libresoc.v:141710$6254_Y + connect \Y $and$libresoc.v:141709$6254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" - cell $and $and$libresoc.v:141711$6255 + cell $and $and$libresoc.v:141710$6255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227343,10 +227343,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$110 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:141711$6255_Y + connect \Y $and$libresoc.v:141710$6255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:141712$6256 + cell $and $and$libresoc.v:141711$6256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227354,10 +227354,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rd_done connect \B \wri_l_q_wri - connect \Y $and$libresoc.v:141712$6256_Y + connect \Y $and$libresoc.v:141711$6256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:141713$6257 + cell $and $and$libresoc.v:141712$6257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227365,10 +227365,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$114 connect \B \cu_busy_o - connect \Y $and$libresoc.v:141713$6257_Y + connect \Y $and$libresoc.v:141712$6257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:141714$6258 + cell $and $and$libresoc.v:141713$6258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227376,10 +227376,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$116 connect \B \lod_l_qn_lod - connect \Y $and$libresoc.v:141714$6258_Y + connect \Y $and$libresoc.v:141713$6258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:141715$6259 + cell $and $and$libresoc.v:141714$6259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227387,10 +227387,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$118 connect \B \op_is_ld - connect \Y $and$libresoc.v:141715$6259_Y + connect \Y $and$libresoc.v:141714$6259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:141716$6260 + cell $and $and$libresoc.v:141715$6260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227398,10 +227398,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$120 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:141716$6260_Y + connect \Y $and$libresoc.v:141715$6260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:141717$6261 + cell $and $and$libresoc.v:141716$6261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227409,10 +227409,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \upd_l_q_upd connect \B \cu_busy_o - connect \Y $and$libresoc.v:141717$6261_Y + connect \Y $and$libresoc.v:141716$6261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:141719$6263 + cell $and $and$libresoc.v:141718$6263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227420,10 +227420,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$124 connect \B \$126 - connect \Y $and$libresoc.v:141719$6263_Y + connect \Y $and$libresoc.v:141718$6263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:141721$6265 + cell $and $and$libresoc.v:141720$6265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227431,10 +227431,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$128 connect \B \alu_valid - connect \Y $and$libresoc.v:141721$6265_Y + connect \Y $and$libresoc.v:141720$6265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:141722$6266 + cell $and $and$libresoc.v:141721$6266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227442,10 +227442,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$130 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:141722$6266_Y + connect \Y $and$libresoc.v:141721$6266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:141726$6270 + cell $and $and$libresoc.v:141725$6270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227453,10 +227453,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rst_l_q_rst connect \B \cu_busy_o - connect \Y $and$libresoc.v:141726$6270_Y + connect \Y $and$libresoc.v:141725$6270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:141727$6271 + cell $and $and$libresoc.v:141726$6271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227464,10 +227464,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$140 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:141727$6271_Y + connect \Y $and$libresoc.v:141726$6271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:141732$6276 + cell $and $and$libresoc.v:141731$6276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227475,10 +227475,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$142 connect \B \$144 - connect \Y $and$libresoc.v:141732$6276_Y + connect \Y $and$libresoc.v:141731$6276_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $and $and$libresoc.v:141734$6278 + cell $and $and$libresoc.v:141733$6278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227486,10 +227486,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$150 connect \B \$152 - connect \Y $and$libresoc.v:141734$6278_Y + connect \Y $and$libresoc.v:141733$6278_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $and $and$libresoc.v:141737$6281 + cell $and $and$libresoc.v:141736$6281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227497,10 +227497,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$158 - connect \Y $and$libresoc.v:141737$6281_Y + connect \Y $and$libresoc.v:141736$6281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" - cell $and $and$libresoc.v:141739$6283 + cell $and $and$libresoc.v:141738$6283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227508,10 +227508,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$162 connect \B \cu_wr__go_i [1] - connect \Y $and$libresoc.v:141739$6283_Y + connect \Y $and$libresoc.v:141738$6283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" - cell $and $and$libresoc.v:141742$6286 + cell $and $and$libresoc.v:141741$6286 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -227519,10 +227519,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A { \cu_busy_o \cu_busy_o \cu_busy_o } connect \B { 1'0 \$167 \op_is_ld } - connect \Y $and$libresoc.v:141742$6286_Y + connect \Y $and$libresoc.v:141741$6286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" - cell $and $and$libresoc.v:141743$6287 + cell $and $and$libresoc.v:141742$6287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227530,10 +227530,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_busy_o - connect \Y $and$libresoc.v:141743$6287_Y + connect \Y $and$libresoc.v:141742$6287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" - cell $and $and$libresoc.v:141744$6288 + cell $and $and$libresoc.v:141743$6288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227541,10 +227541,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_busy_o - connect \Y $and$libresoc.v:141744$6288_Y + connect \Y $and$libresoc.v:141743$6288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" - cell $and $and$libresoc.v:141746$6291 + cell $and $and$libresoc.v:141745$6291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227552,10 +227552,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \lsd_l_q_lsd - connect \Y $and$libresoc.v:141746$6291_Y + connect \Y $and$libresoc.v:141745$6291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" - cell $and $and$libresoc.v:141758$6305 + cell $and $and$libresoc.v:141757$6305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227563,10 +227563,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_ad__go_i - connect \Y $and$libresoc.v:141758$6305_Y + connect \Y $and$libresoc.v:141757$6305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" - cell $and $and$libresoc.v:141759$6306 + cell $and $and$libresoc.v:141758$6306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227574,10 +227574,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_st__go_i - connect \Y $and$libresoc.v:141759$6306_Y + connect \Y $and$libresoc.v:141758$6306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:141761$6308 + cell $and $and$libresoc.v:141760$6308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227585,10 +227585,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \$30 - connect \Y $and$libresoc.v:141761$6308_Y + connect \Y $and$libresoc.v:141760$6308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:141763$6310 + cell $and $and$libresoc.v:141762$6310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227596,10 +227596,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $and$libresoc.v:141763$6310_Y + connect \Y $and$libresoc.v:141762$6310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:141766$6313 + cell $and $and$libresoc.v:141765$6313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227607,10 +227607,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$41 - connect \Y $and$libresoc.v:141766$6313_Y + connect \Y $and$libresoc.v:141765$6313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:141770$6317 + cell $and $and$libresoc.v:141769$6317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227618,10 +227618,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$47 connect \B \$49 - connect \Y $and$libresoc.v:141770$6317_Y + connect \Y $and$libresoc.v:141769$6317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" - cell $and $and$libresoc.v:141773$6320 + cell $and $and$libresoc.v:141772$6320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227629,10 +227629,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \addr_ok connect \B \op_is_st - connect \Y $and$libresoc.v:141773$6320_Y + connect \Y $and$libresoc.v:141772$6320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:141782$6329 + cell $and $and$libresoc.v:141781$6329 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -227640,10 +227640,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:141782$6329_Y + connect \Y $and$libresoc.v:141781$6329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:141784$6331 + cell $and $and$libresoc.v:141783$6331 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -227651,10 +227651,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \$76 connect \B \$78 - connect \Y $and$libresoc.v:141784$6331_Y + connect \Y $and$libresoc.v:141783$6331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:141786$6333 + cell $and $and$libresoc.v:141785$6333 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -227662,10 +227662,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \$80 connect \B \$82 - connect \Y $and$libresoc.v:141786$6333_Y + connect \Y $and$libresoc.v:141785$6333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:141787$6334 + cell $and $and$libresoc.v:141786$6334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227673,10 +227673,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \src_l_q_src [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:141787$6334_Y + connect \Y $and$libresoc.v:141786$6334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:141788$6335 + cell $and $and$libresoc.v:141787$6335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227684,10 +227684,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$86 connect \B \op_is_st - connect \Y $and$libresoc.v:141788$6335_Y + connect \Y $and$libresoc.v:141787$6335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $and $and$libresoc.v:141793$6340 + cell $and $and$libresoc.v:141792$6340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227695,10 +227695,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$92 - connect \Y $and$libresoc.v:141793$6340_Y + connect \Y $and$libresoc.v:141792$6340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:141718$6262 + cell $eq $eq$libresoc.v:141717$6262 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227706,10 +227706,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:141718$6262_Y + connect \Y $eq$libresoc.v:141717$6262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:141738$6282 + cell $eq $eq$libresoc.v:141737$6282 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227717,10 +227717,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:141738$6282_Y + connect \Y $eq$libresoc.v:141737$6282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:141740$6284 + cell $eq $eq$libresoc.v:141739$6284 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227728,10 +227728,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:141740$6284_Y + connect \Y $eq$libresoc.v:141739$6284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" - cell $eq $eq$libresoc.v:141751$6297 + cell $eq $eq$libresoc.v:141750$6297 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -227739,10 +227739,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:141751$6297_Y + connect \Y $eq$libresoc.v:141750$6297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" - cell $eq $eq$libresoc.v:141756$6303 + cell $eq $eq$libresoc.v:141755$6303 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227750,10 +227750,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100110 - connect \Y $eq$libresoc.v:141756$6303_Y + connect \Y $eq$libresoc.v:141755$6303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$libresoc.v:141757$6304 + cell $eq $eq$libresoc.v:141756$6304 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227761,10 +227761,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100101 - connect \Y $eq$libresoc.v:141757$6304_Y + connect \Y $eq$libresoc.v:141756$6304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:141765$6312 + cell $eq $eq$libresoc.v:141764$6312 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227772,10 +227772,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:141765$6312_Y + connect \Y $eq$libresoc.v:141764$6312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:141769$6316 + cell $eq $eq$libresoc.v:141768$6316 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227783,114 +227783,114 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:141769$6316_Y + connect \Y $eq$libresoc.v:141768$6316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $extend$libresoc.v:141745$6289 + cell $pos $extend$libresoc.v:141744$6289 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 96 connect \A \addr_r - connect \Y $extend$libresoc.v:141745$6289_Y + connect \Y $extend$libresoc.v:141744$6289_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $extend$libresoc.v:141747$6292 + cell $pos $extend$libresoc.v:141746$6292 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \ldst_port0_ld_data_o [7:0] - connect \Y $extend$libresoc.v:141747$6292_Y + connect \Y $extend$libresoc.v:141746$6292_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $extend$libresoc.v:141752$6298 + cell $pos $extend$libresoc.v:141751$6298 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \src_r2 [7:0] - connect \Y $extend$libresoc.v:141752$6298_Y + connect \Y $extend$libresoc.v:141751$6298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $not $not$libresoc.v:141730$6274 + cell $not $not$libresoc.v:141729$6274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$147 - connect \Y $not$libresoc.v:141730$6274_Y + connect \Y $not$libresoc.v:141729$6274_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $not $not$libresoc.v:141735$6279 + cell $not $not$libresoc.v:141734$6279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:141735$6279_Y + connect \Y $not$libresoc.v:141734$6279_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:141760$6307 + cell $not $not$libresoc.v:141759$6307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_valid - connect \Y $not$libresoc.v:141760$6307_Y + connect \Y $not$libresoc.v:141759$6307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:141762$6309 + cell $not $not$libresoc.v:141761$6309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rda_any - connect \Y $not$libresoc.v:141762$6309_Y + connect \Y $not$libresoc.v:141761$6309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:141764$6311 + cell $not $not$libresoc.v:141763$6311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:141764$6311_Y + connect \Y $not$libresoc.v:141763$6311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:141768$6315 + cell $not $not$libresoc.v:141767$6315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:141768$6315_Y + connect \Y $not$libresoc.v:141767$6315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:141783$6330 + cell $not $not$libresoc.v:141782$6330 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A { \oper_r__imm_data__ok \oper_r__zero_a } - connect \Y $not$libresoc.v:141783$6330_Y + connect \Y $not$libresoc.v:141782$6330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:141785$6332 + cell $not $not$libresoc.v:141784$6332 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:141785$6332_Y + connect \Y $not$libresoc.v:141784$6332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $not $not$libresoc.v:141792$6339 + cell $not $not$libresoc.v:141791$6339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$93 - connect \Y $not$libresoc.v:141792$6339_Y + connect \Y $not$libresoc.v:141791$6339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $not $not$libresoc.v:141794$6341 + cell $not $not$libresoc.v:141793$6341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [2] - connect \Y $not$libresoc.v:141794$6341_Y + connect \Y $not$libresoc.v:141793$6341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" - cell $or $or$libresoc.v:141709$6253 + cell $or $or$libresoc.v:141708$6253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227898,10 +227898,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_done_o connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141709$6253_Y + connect \Y $or$libresoc.v:141708$6253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" - cell $or $or$libresoc.v:141720$6264 + cell $or $or$libresoc.v:141719$6264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227909,10 +227909,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141720$6264_Y + connect \Y $or$libresoc.v:141719$6264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:141723$6267 + cell $or $or$libresoc.v:141722$6267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227920,10 +227920,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \p_st_go - connect \Y $or$libresoc.v:141723$6267_Y + connect \Y $or$libresoc.v:141722$6267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:141724$6268 + cell $or $or$libresoc.v:141723$6268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227931,10 +227931,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$134 connect \B \cu_wr__go_i [0] - connect \Y $or$libresoc.v:141724$6268_Y + connect \Y $or$libresoc.v:141723$6268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:141725$6269 + cell $or $or$libresoc.v:141724$6269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227942,10 +227942,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$136 connect \B \cu_wr__go_i [1] - connect \Y $or$libresoc.v:141725$6269_Y + connect \Y $or$libresoc.v:141724$6269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:141728$6272 + cell $or $or$libresoc.v:141727$6272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227953,10 +227953,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o connect \B \cu_wr__rel_o [0] - connect \Y $or$libresoc.v:141728$6272_Y + connect \Y $or$libresoc.v:141727$6272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:141729$6273 + cell $or $or$libresoc.v:141728$6273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227964,10 +227964,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$145 connect \B \cu_wr__rel_o [1] - connect \Y $or$libresoc.v:141729$6273_Y + connect \Y $or$libresoc.v:141728$6273_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" - cell $or $or$libresoc.v:141731$6275 + cell $or $or$libresoc.v:141730$6275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227975,10 +227975,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141731$6275_Y + connect \Y $or$libresoc.v:141730$6275_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $or $or$libresoc.v:141733$6277 + cell $or $or$libresoc.v:141732$6277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227986,10 +227986,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \lod_l_qn_lod connect \B \op_is_st - connect \Y $or$libresoc.v:141733$6277_Y + connect \Y $or$libresoc.v:141732$6277_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $or $or$libresoc.v:141736$6280 + cell $or $or$libresoc.v:141735$6280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227997,10 +227997,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$156 connect \B \op_is_ld - connect \Y $or$libresoc.v:141736$6280_Y + connect \Y $or$libresoc.v:141735$6280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" - cell $or $or$libresoc.v:141741$6285 + cell $or $or$libresoc.v:141740$6285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228008,10 +228008,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141741$6285_Y + connect \Y $or$libresoc.v:141740$6285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" - cell $or $or$libresoc.v:141749$6295 + cell $or $or$libresoc.v:141748$6295 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -228019,10 +228019,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:141749$6295_Y + connect \Y $or$libresoc.v:141748$6295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" - cell $or $or$libresoc.v:141755$6302 + cell $or $or$libresoc.v:141754$6302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228030,10 +228030,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_ad__go_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141755$6302_Y + connect \Y $or$libresoc.v:141754$6302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:141767$6314 + cell $or $or$libresoc.v:141766$6314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228041,10 +228041,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$43 - connect \Y $or$libresoc.v:141767$6314_Y + connect \Y $or$libresoc.v:141766$6314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:141771$6318 + cell $or $or$libresoc.v:141770$6318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228052,10 +228052,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$51 - connect \Y $or$libresoc.v:141771$6318_Y + connect \Y $or$libresoc.v:141770$6318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" - cell $or $or$libresoc.v:141772$6319 + cell $or $or$libresoc.v:141771$6319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228063,10 +228063,10 @@ module \ldst0 parameter \Y_WIDTH 2 connect \A \reset_w connect \B { \$45 \$53 } - connect \Y $or$libresoc.v:141772$6319_Y + connect \Y $or$libresoc.v:141771$6319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" - cell $or $or$libresoc.v:141774$6321 + cell $or $or$libresoc.v:141773$6321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228074,10 +228074,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:141774$6321_Y + connect \Y $or$libresoc.v:141773$6321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:141775$6322 + cell $or $or$libresoc.v:141774$6322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228085,10 +228085,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:141775$6322_Y + connect \Y $or$libresoc.v:141774$6322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:141776$6323 + cell $or $or$libresoc.v:141775$6323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228096,10 +228096,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$61 connect \B \ld_ok - connect \Y $or$libresoc.v:141776$6323_Y + connect \Y $or$libresoc.v:141775$6323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" - cell $or $or$libresoc.v:141789$6336 + cell $or $or$libresoc.v:141788$6336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228107,10 +228107,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141789$6336_Y + connect \Y $or$libresoc.v:141788$6336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" - cell $or $or$libresoc.v:141790$6337 + cell $or $or$libresoc.v:141789$6337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228118,10 +228118,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__go_i [0] connect \B \cu_rd__go_i [1] - connect \Y $or$libresoc.v:141790$6337_Y + connect \Y $or$libresoc.v:141789$6337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $or $or$libresoc.v:141791$6338 + cell $or $or$libresoc.v:141790$6338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228129,98 +228129,98 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [0] connect \B \cu_rd__rel_o [1] - connect \Y $or$libresoc.v:141791$6338_Y + connect \Y $or$libresoc.v:141790$6338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $pos$libresoc.v:141745$6290 + cell $pos $pos$libresoc.v:141744$6290 parameter \A_SIGNED 0 parameter \A_WIDTH 96 parameter \Y_WIDTH 96 - connect \A $extend$libresoc.v:141745$6289_Y - connect \Y $pos$libresoc.v:141745$6290_Y + connect \A $extend$libresoc.v:141744$6289_Y + connect \Y $pos$libresoc.v:141744$6290_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141747$6293 + cell $pos $pos$libresoc.v:141746$6293 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:141747$6292_Y - connect \Y $pos$libresoc.v:141747$6293_Y + connect \A $extend$libresoc.v:141746$6292_Y + connect \Y $pos$libresoc.v:141746$6293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141748$6294 + cell $pos $pos$libresoc.v:141747$6294 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } - connect \Y $pos$libresoc.v:141748$6294_Y + connect \Y $pos$libresoc.v:141747$6294_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141750$6296 + cell $pos $pos$libresoc.v:141749$6296 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } - connect \Y $pos$libresoc.v:141750$6296_Y + connect \Y $pos$libresoc.v:141749$6296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141752$6299 + cell $pos $pos$libresoc.v:141751$6299 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:141752$6298_Y - connect \Y $pos$libresoc.v:141752$6299_Y + connect \A $extend$libresoc.v:141751$6298_Y + connect \Y $pos$libresoc.v:141751$6299_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141753$6300 + cell $pos $pos$libresoc.v:141752$6300 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } - connect \Y $pos$libresoc.v:141753$6300_Y + connect \Y $pos$libresoc.v:141752$6300_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141754$6301 + cell $pos $pos$libresoc.v:141753$6301 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } - connect \Y $pos$libresoc.v:141754$6301_Y + connect \Y $pos$libresoc.v:141753$6301_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:141777$6324 + cell $mux $ternary$libresoc.v:141776$6324 parameter \WIDTH 64 connect \A \ldo_r connect \B \ldd_o connect \S \ld_ok - connect \Y $ternary$libresoc.v:141777$6324_Y + connect \Y $ternary$libresoc.v:141776$6324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:141778$6325 + cell $mux $ternary$libresoc.v:141777$6325 parameter \WIDTH 64 connect \A \ea_r connect \B \alu_o connect \S \alu_l_q_alu - connect \Y $ternary$libresoc.v:141778$6325_Y + connect \Y $ternary$libresoc.v:141777$6325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" - cell $mux $ternary$libresoc.v:141779$6326 + cell $mux $ternary$libresoc.v:141778$6326 parameter \WIDTH 64 connect \A \src_r0 connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \oper_r__zero_a - connect \Y $ternary$libresoc.v:141779$6326_Y + connect \Y $ternary$libresoc.v:141778$6326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" - cell $mux $ternary$libresoc.v:141780$6327 + cell $mux $ternary$libresoc.v:141779$6327 parameter \WIDTH 64 connect \A \src_r1 connect \B \oper_r__imm_data__data connect \S \oper_r__imm_data__ok - connect \Y $ternary$libresoc.v:141780$6327_Y + connect \Y $ternary$libresoc.v:141779$6327_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:141865.9-141871.4" + attribute \src "libresoc.v:141864.9-141870.4" cell \adr_l \adr_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228229,7 +228229,7 @@ module \ldst0 connect \s_adr \adr_l_s_adr end attribute \module_not_derived 1 - attribute \src "libresoc.v:141872.15-141878.4" + attribute \src "libresoc.v:141871.15-141877.4" cell \alu_l$128 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228238,7 +228238,7 @@ module \ldst0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:141879.9-141885.4" + attribute \src "libresoc.v:141878.9-141884.4" cell \lod_l \lod_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228247,7 +228247,7 @@ module \ldst0 connect \s_lod \lod_l_s_lod end attribute \module_not_derived 1 - attribute \src "libresoc.v:141886.9-141892.4" + attribute \src "libresoc.v:141885.9-141891.4" cell \lsd_l \lsd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228256,7 +228256,7 @@ module \ldst0 connect \s_lsd \lsd_l_s_lsd end attribute \module_not_derived 1 - attribute \src "libresoc.v:141893.15-141899.4" + attribute \src "libresoc.v:141892.15-141898.4" cell \opc_l$126 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228265,7 +228265,7 @@ module \ldst0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:141900.15-141906.4" + attribute \src "libresoc.v:141899.15-141905.4" cell \rst_l$129 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228274,7 +228274,7 @@ module \ldst0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:141907.15-141913.4" + attribute \src "libresoc.v:141906.15-141912.4" cell \src_l$127 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228283,7 +228283,7 @@ module \ldst0 connect \s_src \src_l_s_src end attribute \module_not_derived 1 - attribute \src "libresoc.v:141914.9-141920.4" + attribute \src "libresoc.v:141913.9-141919.4" cell \sto_l \sto_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228292,7 +228292,7 @@ module \ldst0 connect \s_sto \sto_l_s_sto end attribute \module_not_derived 1 - attribute \src "libresoc.v:141921.9-141927.4" + attribute \src "libresoc.v:141920.9-141926.4" cell \upd_l \upd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228301,7 +228301,7 @@ module \ldst0 connect \s_upd \upd_l_s_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:141928.9-141934.4" + attribute \src "libresoc.v:141927.9-141933.4" cell \wri_l \wri_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228309,547 +228309,547 @@ module \ldst0 connect \r_wri \wri_l_r_wri connect \s_wri \wri_l_s_wri end - attribute \src "libresoc.v:140954.7-140954.20" - process $proc$libresoc.v:140954$6490 + attribute \src "libresoc.v:140953.7-140953.20" + process $proc$libresoc.v:140953$6490 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:141150.7-141150.25" - process $proc$libresoc.v:141150$6491 + attribute \src "libresoc.v:141149.7-141149.25" + process $proc$libresoc.v:141149$6491 assign { } { } assign $1\adr_l_r_adr[0:0] 1'1 sync always sync init update \adr_l_r_adr $1\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:141164.7-141164.20" - process $proc$libresoc.v:141164$6492 + attribute \src "libresoc.v:141163.7-141163.20" + process $proc$libresoc.v:141163$6492 assign { } { } assign $1\alu_ok[0:0] 1'0 sync always sync init update \alu_ok $1\alu_ok[0:0] end - attribute \src "libresoc.v:141210.14-141210.41" - process $proc$libresoc.v:141210$6493 + attribute \src "libresoc.v:141209.14-141209.41" + process $proc$libresoc.v:141209$6493 assign { } { } assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ea_r $1\ea_r[63:0] end - attribute \src "libresoc.v:141240.14-141240.42" - process $proc$libresoc.v:141240$6494 + attribute \src "libresoc.v:141239.14-141239.42" + process $proc$libresoc.v:141239$6494 assign { } { } assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldo_r $1\ldo_r[63:0] end - attribute \src "libresoc.v:141245.14-141245.62" - process $proc$libresoc.v:141245$6495 + attribute \src "libresoc.v:141244.14-141244.62" + process $proc$libresoc.v:141244$6495 assign { } { } assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:141250.7-141250.34" - process $proc$libresoc.v:141250$6496 + attribute \src "libresoc.v:141249.7-141249.34" + process $proc$libresoc.v:141249$6496 assign { } { } assign $1\ldst_port0_addr_i_ok[0:0] 1'0 sync always sync init update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:141299.7-141299.25" - process $proc$libresoc.v:141299$6497 + attribute \src "libresoc.v:141298.7-141298.25" + process $proc$libresoc.v:141298$6497 assign { } { } assign $1\lsd_l_r_lsd[0:0] 1'1 sync always sync init update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:141313.7-141313.25" - process $proc$libresoc.v:141313$6498 + attribute \src "libresoc.v:141312.7-141312.25" + process $proc$libresoc.v:141312$6498 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:141317.7-141317.25" - process $proc$libresoc.v:141317$6499 + attribute \src "libresoc.v:141316.7-141316.25" + process $proc$libresoc.v:141316$6499 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:141448.7-141448.34" - process $proc$libresoc.v:141448$6500 + attribute \src "libresoc.v:141447.7-141447.34" + process $proc$libresoc.v:141447$6500 assign { } { } assign $1\oper_r__byte_reverse[0:0] 1'0 sync always sync init update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:141452.13-141452.36" - process $proc$libresoc.v:141452$6501 + attribute \src "libresoc.v:141451.13-141451.36" + process $proc$libresoc.v:141451$6501 assign { } { } assign $1\oper_r__data_len[3:0] 4'0000 sync always sync init update \oper_r__data_len $1\oper_r__data_len[3:0] end - attribute \src "libresoc.v:141471.14-141471.40" - process $proc$libresoc.v:141471$6502 + attribute \src "libresoc.v:141470.14-141470.40" + process $proc$libresoc.v:141470$6502 assign { } { } assign $1\oper_r__fn_unit[13:0] 14'00000000000000 sync always sync init update \oper_r__fn_unit $1\oper_r__fn_unit[13:0] end - attribute \src "libresoc.v:141475.14-141475.59" - process $proc$libresoc.v:141475$6503 + attribute \src "libresoc.v:141474.14-141474.59" + process $proc$libresoc.v:141474$6503 assign { } { } assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:141479.7-141479.34" - process $proc$libresoc.v:141479$6504 + attribute \src "libresoc.v:141478.7-141478.34" + process $proc$libresoc.v:141478$6504 assign { } { } assign $1\oper_r__imm_data__ok[0:0] 1'0 sync always sync init update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:141483.14-141483.34" - process $proc$libresoc.v:141483$6505 + attribute \src "libresoc.v:141482.14-141482.34" + process $proc$libresoc.v:141482$6505 assign { } { } assign $1\oper_r__insn[31:0] 0 sync always sync init update \oper_r__insn $1\oper_r__insn[31:0] end - attribute \src "libresoc.v:141562.13-141562.38" - process $proc$libresoc.v:141562$6506 + attribute \src "libresoc.v:141561.13-141561.38" + process $proc$libresoc.v:141561$6506 assign { } { } assign $1\oper_r__insn_type[6:0] 7'0000000 sync always sync init update \oper_r__insn_type $1\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:141566.7-141566.30" - process $proc$libresoc.v:141566$6507 + attribute \src "libresoc.v:141565.7-141565.30" + process $proc$libresoc.v:141565$6507 assign { } { } assign $1\oper_r__is_32bit[0:0] 1'0 sync always sync init update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:141570.7-141570.31" - process $proc$libresoc.v:141570$6508 + attribute \src "libresoc.v:141569.7-141569.31" + process $proc$libresoc.v:141569$6508 assign { } { } assign $1\oper_r__is_signed[0:0] 1'0 sync always sync init update \oper_r__is_signed $1\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:141579.13-141579.37" - process $proc$libresoc.v:141579$6509 + attribute \src "libresoc.v:141578.13-141578.37" + process $proc$libresoc.v:141578$6509 assign { } { } assign $1\oper_r__ldst_mode[1:0] 2'00 sync always sync init update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:141583.7-141583.28" - process $proc$libresoc.v:141583$6510 + attribute \src "libresoc.v:141582.7-141582.28" + process $proc$libresoc.v:141582$6510 assign { } { } assign $1\oper_r__oe__oe[0:0] 1'0 sync always sync init update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:141587.7-141587.28" - process $proc$libresoc.v:141587$6511 + attribute \src "libresoc.v:141586.7-141586.28" + process $proc$libresoc.v:141586$6511 assign { } { } assign $1\oper_r__oe__ok[0:0] 1'0 sync always sync init update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:141591.7-141591.28" - process $proc$libresoc.v:141591$6512 + attribute \src "libresoc.v:141590.7-141590.28" + process $proc$libresoc.v:141590$6512 assign { } { } assign $1\oper_r__rc__ok[0:0] 1'0 sync always sync init update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:141595.7-141595.28" - process $proc$libresoc.v:141595$6513 + attribute \src "libresoc.v:141594.7-141594.28" + process $proc$libresoc.v:141594$6513 assign { } { } assign $1\oper_r__rc__rc[0:0] 1'0 sync always sync init update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:141599.7-141599.33" - process $proc$libresoc.v:141599$6514 + attribute \src "libresoc.v:141598.7-141598.33" + process $proc$libresoc.v:141598$6514 assign { } { } assign $1\oper_r__sign_extend[0:0] 1'0 sync always sync init update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:141603.7-141603.28" - process $proc$libresoc.v:141603$6515 + attribute \src "libresoc.v:141602.7-141602.28" + process $proc$libresoc.v:141602$6515 assign { } { } assign $1\oper_r__zero_a[0:0] 1'0 sync always sync init update \oper_r__zero_a $1\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:141607.7-141607.21" - process $proc$libresoc.v:141607$6516 + attribute \src "libresoc.v:141606.7-141606.21" + process $proc$libresoc.v:141606$6516 assign { } { } assign $1\p_st_go[0:0] 1'0 sync always sync init update \p_st_go $1\p_st_go[0:0] end - attribute \src "libresoc.v:141649.13-141649.31" - process $proc$libresoc.v:141649$6517 + attribute \src "libresoc.v:141648.13-141648.31" + process $proc$libresoc.v:141648$6517 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:141653.13-141653.31" - process $proc$libresoc.v:141653$6518 + attribute \src "libresoc.v:141652.13-141652.31" + process $proc$libresoc.v:141652$6518 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:141657.14-141657.43" - process $proc$libresoc.v:141657$6519 + attribute \src "libresoc.v:141656.14-141656.43" + process $proc$libresoc.v:141656$6519 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:141661.14-141661.43" - process $proc$libresoc.v:141661$6520 + attribute \src "libresoc.v:141660.14-141660.43" + process $proc$libresoc.v:141660$6520 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:141665.14-141665.43" - process $proc$libresoc.v:141665$6521 + attribute \src "libresoc.v:141664.14-141664.43" + process $proc$libresoc.v:141664$6521 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:141675.7-141675.25" - process $proc$libresoc.v:141675$6522 + attribute \src "libresoc.v:141674.7-141674.25" + process $proc$libresoc.v:141674$6522 assign { } { } assign $1\sto_l_r_sto[0:0] 1'1 sync always sync init update \sto_l_r_sto $1\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:141685.7-141685.25" - process $proc$libresoc.v:141685$6523 + attribute \src "libresoc.v:141684.7-141684.25" + process $proc$libresoc.v:141684$6523 assign { } { } assign $1\upd_l_r_upd[0:0] 1'1 sync always sync init update \upd_l_r_upd $1\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:141689.7-141689.25" - process $proc$libresoc.v:141689$6524 + attribute \src "libresoc.v:141688.7-141688.25" + process $proc$libresoc.v:141688$6524 assign { } { } assign $1\upd_l_s_upd[0:0] 1'0 sync always sync init update \upd_l_s_upd $1\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:141699.7-141699.25" - process $proc$libresoc.v:141699$6525 + attribute \src "libresoc.v:141698.7-141698.25" + process $proc$libresoc.v:141698$6525 assign { } { } assign $1\wri_l_r_wri[0:0] 1'1 sync always sync init update \wri_l_r_wri $1\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:141795.3-141796.57" - process $proc$libresoc.v:141795$6342 + attribute \src "libresoc.v:141794.3-141795.57" + process $proc$libresoc.v:141794$6342 assign { } { } assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next sync posedge \coresync_clk update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:141797.3-141798.33" - process $proc$libresoc.v:141797$6343 + attribute \src "libresoc.v:141796.3-141797.33" + process $proc$libresoc.v:141796$6343 assign { } { } assign $0\ldst_port0_addr_i[95:0] \$175 sync posedge \coresync_clk update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:141799.3-141800.21" - process $proc$libresoc.v:141799$6344 + attribute \src "libresoc.v:141798.3-141799.21" + process $proc$libresoc.v:141798$6344 assign { } { } assign $0\alu_ok[0:0] \$96 sync posedge \coresync_clk update \alu_ok $0\alu_ok[0:0] end - attribute \src "libresoc.v:141801.3-141802.25" - process $proc$libresoc.v:141801$6345 + attribute \src "libresoc.v:141800.3-141801.25" + process $proc$libresoc.v:141800$6345 assign { } { } assign $0\ea_r[63:0] \ea_r$next sync posedge \coresync_clk update \ea_r $0\ea_r[63:0] end - attribute \src "libresoc.v:141803.3-141804.29" - process $proc$libresoc.v:141803$6346 + attribute \src "libresoc.v:141802.3-141803.29" + process $proc$libresoc.v:141802$6346 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:141805.3-141806.29" - process $proc$libresoc.v:141805$6347 + attribute \src "libresoc.v:141804.3-141805.29" + process $proc$libresoc.v:141804$6347 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:141807.3-141808.29" - process $proc$libresoc.v:141807$6348 + attribute \src "libresoc.v:141806.3-141807.29" + process $proc$libresoc.v:141806$6348 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:141809.3-141810.27" - process $proc$libresoc.v:141809$6349 + attribute \src "libresoc.v:141808.3-141809.27" + process $proc$libresoc.v:141808$6349 assign { } { } assign $0\ldo_r[63:0] \ldo_r$next sync posedge \coresync_clk update \ldo_r $0\ldo_r[63:0] end - attribute \src "libresoc.v:141811.3-141812.51" - process $proc$libresoc.v:141811$6350 + attribute \src "libresoc.v:141810.3-141811.51" + process $proc$libresoc.v:141810$6350 assign { } { } assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next sync posedge \coresync_clk update \oper_r__insn_type $0\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:141813.3-141814.47" - process $proc$libresoc.v:141813$6351 + attribute \src "libresoc.v:141812.3-141813.47" + process $proc$libresoc.v:141812$6351 assign { } { } assign $0\oper_r__fn_unit[13:0] \oper_r__fn_unit$next sync posedge \coresync_clk update \oper_r__fn_unit $0\oper_r__fn_unit[13:0] end - attribute \src "libresoc.v:141815.3-141816.61" - process $proc$libresoc.v:141815$6352 + attribute \src "libresoc.v:141814.3-141815.61" + process $proc$libresoc.v:141814$6352 assign { } { } assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next sync posedge \coresync_clk update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:141817.3-141818.57" - process $proc$libresoc.v:141817$6353 + attribute \src "libresoc.v:141816.3-141817.57" + process $proc$libresoc.v:141816$6353 assign { } { } assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next sync posedge \coresync_clk update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:141819.3-141820.45" - process $proc$libresoc.v:141819$6354 + attribute \src "libresoc.v:141818.3-141819.45" + process $proc$libresoc.v:141818$6354 assign { } { } assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next sync posedge \coresync_clk update \oper_r__zero_a $0\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:141821.3-141822.45" - process $proc$libresoc.v:141821$6355 + attribute \src "libresoc.v:141820.3-141821.45" + process $proc$libresoc.v:141820$6355 assign { } { } assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next sync posedge \coresync_clk update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:141823.3-141824.45" - process $proc$libresoc.v:141823$6356 + attribute \src "libresoc.v:141822.3-141823.45" + process $proc$libresoc.v:141822$6356 assign { } { } assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next sync posedge \coresync_clk update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:141825.3-141826.45" - process $proc$libresoc.v:141825$6357 + attribute \src "libresoc.v:141824.3-141825.45" + process $proc$libresoc.v:141824$6357 assign { } { } assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next sync posedge \coresync_clk update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:141827.3-141828.45" - process $proc$libresoc.v:141827$6358 + attribute \src "libresoc.v:141826.3-141827.45" + process $proc$libresoc.v:141826$6358 assign { } { } assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next sync posedge \coresync_clk update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:141829.3-141830.49" - process $proc$libresoc.v:141829$6359 + attribute \src "libresoc.v:141828.3-141829.49" + process $proc$libresoc.v:141828$6359 assign { } { } assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next sync posedge \coresync_clk update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:141831.3-141832.51" - process $proc$libresoc.v:141831$6360 + attribute \src "libresoc.v:141830.3-141831.51" + process $proc$libresoc.v:141830$6360 assign { } { } assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next sync posedge \coresync_clk update \oper_r__is_signed $0\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:141833.3-141834.49" - process $proc$libresoc.v:141833$6361 + attribute \src "libresoc.v:141832.3-141833.49" + process $proc$libresoc.v:141832$6361 assign { } { } assign $0\oper_r__data_len[3:0] \oper_r__data_len$next sync posedge \coresync_clk update \oper_r__data_len $0\oper_r__data_len[3:0] end - attribute \src "libresoc.v:141835.3-141836.57" - process $proc$libresoc.v:141835$6362 + attribute \src "libresoc.v:141834.3-141835.57" + process $proc$libresoc.v:141834$6362 assign { } { } assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next sync posedge \coresync_clk update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:141837.3-141838.55" - process $proc$libresoc.v:141837$6363 + attribute \src "libresoc.v:141836.3-141837.55" + process $proc$libresoc.v:141836$6363 assign { } { } assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next sync posedge \coresync_clk update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:141839.3-141840.51" - process $proc$libresoc.v:141839$6364 + attribute \src "libresoc.v:141838.3-141839.51" + process $proc$libresoc.v:141838$6364 assign { } { } assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next sync posedge \coresync_clk update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:141841.3-141842.41" - process $proc$libresoc.v:141841$6365 + attribute \src "libresoc.v:141840.3-141841.41" + process $proc$libresoc.v:141840$6365 assign { } { } assign $0\oper_r__insn[31:0] \oper_r__insn$next sync posedge \coresync_clk update \oper_r__insn $0\oper_r__insn[31:0] end - attribute \src "libresoc.v:141843.3-141844.39" - process $proc$libresoc.v:141843$6366 + attribute \src "libresoc.v:141842.3-141843.39" + process $proc$libresoc.v:141842$6366 assign { } { } assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next sync posedge \coresync_clk update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:141845.3-141846.39" - process $proc$libresoc.v:141845$6367 + attribute \src "libresoc.v:141844.3-141845.39" + process $proc$libresoc.v:141844$6367 assign { } { } assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next sync posedge \coresync_clk update \sto_l_r_sto $0\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:141847.3-141848.39" - process $proc$libresoc.v:141847$6368 + attribute \src "libresoc.v:141846.3-141847.39" + process $proc$libresoc.v:141846$6368 assign { } { } assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next sync posedge \coresync_clk update \upd_l_r_upd $0\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:141849.3-141850.39" - process $proc$libresoc.v:141849$6369 + attribute \src "libresoc.v:141848.3-141849.39" + process $proc$libresoc.v:141848$6369 assign { } { } assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next sync posedge \coresync_clk update \upd_l_s_upd $0\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:141851.3-141852.39" - process $proc$libresoc.v:141851$6370 + attribute \src "libresoc.v:141850.3-141851.39" + process $proc$libresoc.v:141850$6370 assign { } { } assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next sync posedge \coresync_clk update \wri_l_r_wri $0\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:141853.3-141854.39" - process $proc$libresoc.v:141853$6371 + attribute \src "libresoc.v:141852.3-141853.39" + process $proc$libresoc.v:141852$6371 assign { } { } assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next sync posedge \coresync_clk update \adr_l_r_adr $0\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:141855.3-141856.39" - process $proc$libresoc.v:141855$6372 + attribute \src "libresoc.v:141854.3-141855.39" + process $proc$libresoc.v:141854$6372 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:141857.3-141858.39" - process $proc$libresoc.v:141857$6373 + attribute \src "libresoc.v:141856.3-141857.39" + process $proc$libresoc.v:141856$6373 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:141859.3-141860.39" - process $proc$libresoc.v:141859$6374 + attribute \src "libresoc.v:141858.3-141859.39" + process $proc$libresoc.v:141858$6374 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:141861.3-141862.39" - process $proc$libresoc.v:141861$6375 + attribute \src "libresoc.v:141860.3-141861.39" + process $proc$libresoc.v:141860$6375 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:141863.3-141864.28" - process $proc$libresoc.v:141863$6376 + attribute \src "libresoc.v:141862.3-141863.28" + process $proc$libresoc.v:141862$6376 assign { } { } assign $0\p_st_go[0:0] \cu_st__go_i sync posedge \coresync_clk update \p_st_go $0\p_st_go[0:0] end - attribute \src "libresoc.v:141935.3-141943.6" - process $proc$libresoc.v:141935$6377 + attribute \src "libresoc.v:141934.3-141942.6" + process $proc$libresoc.v:141934$6377 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$6378 $1\opc_l_s_opc$next[0:0]$6379 - attribute \src "libresoc.v:141936.5-141936.29" + attribute \src "libresoc.v:141935.5-141935.29" switch \initial - attribute \src "libresoc.v:141936.9-141936.17" + attribute \src "libresoc.v:141935.9-141935.17" case 1'1 case end @@ -228865,14 +228865,14 @@ module \ldst0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6378 end - attribute \src "libresoc.v:141944.3-141952.6" - process $proc$libresoc.v:141944$6380 + attribute \src "libresoc.v:141943.3-141951.6" + process $proc$libresoc.v:141943$6380 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$6381 $1\opc_l_r_opc$next[0:0]$6382 - attribute \src "libresoc.v:141945.5-141945.29" + attribute \src "libresoc.v:141944.5-141944.29" switch \initial - attribute \src "libresoc.v:141945.9-141945.17" + attribute \src "libresoc.v:141944.9-141944.17" case 1'1 case end @@ -228888,14 +228888,14 @@ module \ldst0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6381 end - attribute \src "libresoc.v:141953.3-141961.6" - process $proc$libresoc.v:141953$6383 + attribute \src "libresoc.v:141952.3-141960.6" + process $proc$libresoc.v:141952$6383 assign { } { } assign { } { } assign $0\src_l_s_src$next[2:0]$6384 $1\src_l_s_src$next[2:0]$6385 - attribute \src "libresoc.v:141954.5-141954.29" + attribute \src "libresoc.v:141953.5-141953.29" switch \initial - attribute \src "libresoc.v:141954.9-141954.17" + attribute \src "libresoc.v:141953.9-141953.17" case 1'1 case end @@ -228911,14 +228911,14 @@ module \ldst0 sync always update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6384 end - attribute \src "libresoc.v:141962.3-141970.6" - process $proc$libresoc.v:141962$6386 + attribute \src "libresoc.v:141961.3-141969.6" + process $proc$libresoc.v:141961$6386 assign { } { } assign { } { } assign $0\src_l_r_src$next[2:0]$6387 $1\src_l_r_src$next[2:0]$6388 - attribute \src "libresoc.v:141963.5-141963.29" + attribute \src "libresoc.v:141962.5-141962.29" switch \initial - attribute \src "libresoc.v:141963.9-141963.17" + attribute \src "libresoc.v:141962.9-141962.17" case 1'1 case end @@ -228934,14 +228934,14 @@ module \ldst0 sync always update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6387 end - attribute \src "libresoc.v:141971.3-141979.6" - process $proc$libresoc.v:141971$6389 + attribute \src "libresoc.v:141970.3-141978.6" + process $proc$libresoc.v:141970$6389 assign { } { } assign { } { } assign $0\adr_l_r_adr$next[0:0]$6390 $1\adr_l_r_adr$next[0:0]$6391 - attribute \src "libresoc.v:141972.5-141972.29" + attribute \src "libresoc.v:141971.5-141971.29" switch \initial - attribute \src "libresoc.v:141972.9-141972.17" + attribute \src "libresoc.v:141971.9-141971.17" case 1'1 case end @@ -228957,14 +228957,14 @@ module \ldst0 sync always update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6390 end - attribute \src "libresoc.v:141980.3-141988.6" - process $proc$libresoc.v:141980$6392 + attribute \src "libresoc.v:141979.3-141987.6" + process $proc$libresoc.v:141979$6392 assign { } { } assign { } { } assign $0\wri_l_r_wri$next[0:0]$6393 $1\wri_l_r_wri$next[0:0]$6394 - attribute \src "libresoc.v:141981.5-141981.29" + attribute \src "libresoc.v:141980.5-141980.29" switch \initial - attribute \src "libresoc.v:141981.9-141981.17" + attribute \src "libresoc.v:141980.9-141980.17" case 1'1 case end @@ -228980,14 +228980,14 @@ module \ldst0 sync always update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6393 end - attribute \src "libresoc.v:141989.3-141997.6" - process $proc$libresoc.v:141989$6395 + attribute \src "libresoc.v:141988.3-141996.6" + process $proc$libresoc.v:141988$6395 assign { } { } assign { } { } assign $0\upd_l_s_upd$next[0:0]$6396 $1\upd_l_s_upd$next[0:0]$6397 - attribute \src "libresoc.v:141990.5-141990.29" + attribute \src "libresoc.v:141989.5-141989.29" switch \initial - attribute \src "libresoc.v:141990.9-141990.17" + attribute \src "libresoc.v:141989.9-141989.17" case 1'1 case end @@ -229003,14 +229003,14 @@ module \ldst0 sync always update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6396 end - attribute \src "libresoc.v:141998.3-142006.6" - process $proc$libresoc.v:141998$6398 + attribute \src "libresoc.v:141997.3-142005.6" + process $proc$libresoc.v:141997$6398 assign { } { } assign { } { } assign $0\upd_l_r_upd$next[0:0]$6399 $1\upd_l_r_upd$next[0:0]$6400 - attribute \src "libresoc.v:141999.5-141999.29" + attribute \src "libresoc.v:141998.5-141998.29" switch \initial - attribute \src "libresoc.v:141999.9-141999.17" + attribute \src "libresoc.v:141998.9-141998.17" case 1'1 case end @@ -229026,14 +229026,14 @@ module \ldst0 sync always update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6399 end - attribute \src "libresoc.v:142007.3-142015.6" - process $proc$libresoc.v:142007$6401 + attribute \src "libresoc.v:142006.3-142014.6" + process $proc$libresoc.v:142006$6401 assign { } { } assign { } { } assign $0\sto_l_r_sto$next[0:0]$6402 $1\sto_l_r_sto$next[0:0]$6403 - attribute \src "libresoc.v:142008.5-142008.29" + attribute \src "libresoc.v:142007.5-142007.29" switch \initial - attribute \src "libresoc.v:142008.9-142008.17" + attribute \src "libresoc.v:142007.9-142007.17" case 1'1 case end @@ -229049,14 +229049,14 @@ module \ldst0 sync always update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6402 end - attribute \src "libresoc.v:142016.3-142024.6" - process $proc$libresoc.v:142016$6404 + attribute \src "libresoc.v:142015.3-142023.6" + process $proc$libresoc.v:142015$6404 assign { } { } assign { } { } assign $0\lsd_l_r_lsd$next[0:0]$6405 $1\lsd_l_r_lsd$next[0:0]$6406 - attribute \src "libresoc.v:142017.5-142017.29" + attribute \src "libresoc.v:142016.5-142016.29" switch \initial - attribute \src "libresoc.v:142017.9-142017.17" + attribute \src "libresoc.v:142016.9-142016.17" case 1'1 case end @@ -229072,8 +229072,8 @@ module \ldst0 sync always update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6405 end - attribute \src "libresoc.v:142025.3-142067.6" - process $proc$libresoc.v:142025$6407 + attribute \src "libresoc.v:142024.3-142066.6" + process $proc$libresoc.v:142024$6407 assign { } { } assign { } { } assign { } { } @@ -229144,9 +229144,9 @@ module \ldst0 assign $0\oper_r__oe__ok$next[0:0]$6419 $3\oper_r__oe__ok$next[0:0]$6459 assign $0\oper_r__rc__ok$next[0:0]$6420 $3\oper_r__rc__ok$next[0:0]$6460 assign $0\oper_r__rc__rc$next[0:0]$6421 $3\oper_r__rc__rc$next[0:0]$6461 - attribute \src "libresoc.v:142026.5-142026.29" + attribute \src "libresoc.v:142025.5-142025.29" switch \initial - attribute \src "libresoc.v:142026.9-142026.17" + attribute \src "libresoc.v:142025.9-142025.17" case 1'1 case end @@ -229270,14 +229270,14 @@ module \ldst0 update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6422 update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6423 end - attribute \src "libresoc.v:142068.3-142077.6" - process $proc$libresoc.v:142068$6462 + attribute \src "libresoc.v:142067.3-142076.6" + process $proc$libresoc.v:142067$6462 assign { } { } assign { } { } assign $0\ldo_r$next[63:0]$6463 $1\ldo_r$next[63:0]$6464 - attribute \src "libresoc.v:142069.5-142069.29" + attribute \src "libresoc.v:142068.5-142068.29" switch \initial - attribute \src "libresoc.v:142069.9-142069.17" + attribute \src "libresoc.v:142068.9-142068.17" case 1'1 case end @@ -229293,15 +229293,15 @@ module \ldst0 sync always update \ldo_r$next $0\ldo_r$next[63:0]$6463 end - attribute \src "libresoc.v:142078.3-142093.6" - process $proc$libresoc.v:142078$6465 + attribute \src "libresoc.v:142077.3-142092.6" + process $proc$libresoc.v:142077$6465 assign { } { } assign { } { } assign { } { } assign $0\src_r0$next[63:0]$6466 $2\src_r0$next[63:0]$6468 - attribute \src "libresoc.v:142079.5-142079.29" + attribute \src "libresoc.v:142078.5-142078.29" switch \initial - attribute \src "libresoc.v:142079.9-142079.17" + attribute \src "libresoc.v:142078.9-142078.17" case 1'1 case end @@ -229326,15 +229326,15 @@ module \ldst0 sync always update \src_r0$next $0\src_r0$next[63:0]$6466 end - attribute \src "libresoc.v:142094.3-142109.6" - process $proc$libresoc.v:142094$6469 + attribute \src "libresoc.v:142093.3-142108.6" + process $proc$libresoc.v:142093$6469 assign { } { } assign { } { } assign { } { } assign $0\src_r1$next[63:0]$6470 $2\src_r1$next[63:0]$6472 - attribute \src "libresoc.v:142095.5-142095.29" + attribute \src "libresoc.v:142094.5-142094.29" switch \initial - attribute \src "libresoc.v:142095.9-142095.17" + attribute \src "libresoc.v:142094.9-142094.17" case 1'1 case end @@ -229359,15 +229359,15 @@ module \ldst0 sync always update \src_r1$next $0\src_r1$next[63:0]$6470 end - attribute \src "libresoc.v:142110.3-142125.6" - process $proc$libresoc.v:142110$6473 + attribute \src "libresoc.v:142109.3-142124.6" + process $proc$libresoc.v:142109$6473 assign { } { } assign { } { } assign { } { } assign $0\src_r2$next[63:0]$6474 $2\src_r2$next[63:0]$6476 - attribute \src "libresoc.v:142111.5-142111.29" + attribute \src "libresoc.v:142110.5-142110.29" switch \initial - attribute \src "libresoc.v:142111.9-142111.17" + attribute \src "libresoc.v:142110.9-142110.17" case 1'1 case end @@ -229392,14 +229392,14 @@ module \ldst0 sync always update \src_r2$next $0\src_r2$next[63:0]$6474 end - attribute \src "libresoc.v:142126.3-142135.6" - process $proc$libresoc.v:142126$6477 + attribute \src "libresoc.v:142125.3-142134.6" + process $proc$libresoc.v:142125$6477 assign { } { } assign { } { } assign $0\ea_r$next[63:0]$6478 $1\ea_r$next[63:0]$6479 - attribute \src "libresoc.v:142127.5-142127.29" + attribute \src "libresoc.v:142126.5-142126.29" switch \initial - attribute \src "libresoc.v:142127.9-142127.17" + attribute \src "libresoc.v:142126.9-142126.17" case 1'1 case end @@ -229415,14 +229415,14 @@ module \ldst0 sync always update \ea_r$next $0\ea_r$next[63:0]$6478 end - attribute \src "libresoc.v:142136.3-142145.6" - process $proc$libresoc.v:142136$6480 + attribute \src "libresoc.v:142135.3-142144.6" + process $proc$libresoc.v:142135$6480 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:142137.5-142137.29" + attribute \src "libresoc.v:142136.5-142136.29" switch \initial - attribute \src "libresoc.v:142137.9-142137.17" + attribute \src "libresoc.v:142136.9-142136.17" case 1'1 case end @@ -229438,14 +229438,14 @@ module \ldst0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:142146.3-142155.6" - process $proc$libresoc.v:142146$6481 + attribute \src "libresoc.v:142145.3-142154.6" + process $proc$libresoc.v:142145$6481 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:142147.5-142147.29" + attribute \src "libresoc.v:142146.5-142146.29" switch \initial - attribute \src "libresoc.v:142147.9-142147.17" + attribute \src "libresoc.v:142146.9-142146.17" case 1'1 case end @@ -229461,14 +229461,14 @@ module \ldst0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:142156.3-142164.6" - process $proc$libresoc.v:142156$6482 + attribute \src "libresoc.v:142155.3-142163.6" + process $proc$libresoc.v:142155$6482 assign { } { } assign { } { } assign $0\ldst_port0_addr_i_ok$next[0:0]$6483 $1\ldst_port0_addr_i_ok$next[0:0]$6484 - attribute \src "libresoc.v:142157.5-142157.29" + attribute \src "libresoc.v:142156.5-142156.29" switch \initial - attribute \src "libresoc.v:142157.9-142157.17" + attribute \src "libresoc.v:142156.9-142156.17" case 1'1 case end @@ -229484,14 +229484,14 @@ module \ldst0 sync always update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6483 end - attribute \src "libresoc.v:142165.3-142188.6" - process $proc$libresoc.v:142165$6485 + attribute \src "libresoc.v:142164.3-142187.6" + process $proc$libresoc.v:142164$6485 assign { } { } assign { } { } assign $0\lddata_r[63:0] $1\lddata_r[63:0] - attribute \src "libresoc.v:142166.5-142166.29" + attribute \src "libresoc.v:142165.5-142165.29" switch \initial - attribute \src "libresoc.v:142166.9-142166.17" + attribute \src "libresoc.v:142165.9-142165.17" case 1'1 case end @@ -229528,13 +229528,13 @@ module \ldst0 sync always update \lddata_r $0\lddata_r[63:0] end - attribute \src "libresoc.v:142189.3-142200.6" - process $proc$libresoc.v:142189$6486 + attribute \src "libresoc.v:142188.3-142199.6" + process $proc$libresoc.v:142188$6486 assign { } { } assign $0\revnorev[63:0] $1\revnorev[63:0] - attribute \src "libresoc.v:142190.5-142190.29" + attribute \src "libresoc.v:142189.5-142189.29" switch \initial - attribute \src "libresoc.v:142190.9-142190.17" + attribute \src "libresoc.v:142189.9-142189.17" case 1'1 case end @@ -229552,13 +229552,13 @@ module \ldst0 sync always update \revnorev $0\revnorev[63:0] end - attribute \src "libresoc.v:142201.3-142220.6" - process $proc$libresoc.v:142201$6487 + attribute \src "libresoc.v:142200.3-142219.6" + process $proc$libresoc.v:142200$6487 assign { } { } assign $0\ldd_o[63:0] $1\ldd_o[63:0] - attribute \src "libresoc.v:142202.5-142202.29" + attribute \src "libresoc.v:142201.5-142201.29" switch \initial - attribute \src "libresoc.v:142202.9-142202.17" + attribute \src "libresoc.v:142201.9-142201.17" case 1'1 case end @@ -229587,14 +229587,14 @@ module \ldst0 sync always update \ldd_o $0\ldd_o[63:0] end - attribute \src "libresoc.v:142221.3-142244.6" - process $proc$libresoc.v:142221$6488 + attribute \src "libresoc.v:142220.3-142243.6" + process $proc$libresoc.v:142220$6488 assign { } { } assign { } { } assign $0\stdata_r[63:0] $1\stdata_r[63:0] - attribute \src "libresoc.v:142222.5-142222.29" + attribute \src "libresoc.v:142221.5-142221.29" switch \initial - attribute \src "libresoc.v:142222.9-142222.17" + attribute \src "libresoc.v:142221.9-142221.17" case 1'1 case end @@ -229631,13 +229631,13 @@ module \ldst0 sync always update \stdata_r $0\stdata_r[63:0] end - attribute \src "libresoc.v:142245.3-142256.6" - process $proc$libresoc.v:142245$6489 + attribute \src "libresoc.v:142244.3-142255.6" + process $proc$libresoc.v:142244$6489 assign { } { } assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:142246.5-142246.29" + attribute \src "libresoc.v:142245.5-142245.29" switch \initial - attribute \src "libresoc.v:142246.9-142246.17" + attribute \src "libresoc.v:142245.9-142245.17" case 1'1 case end @@ -229655,97 +229655,97 @@ module \ldst0 sync always update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] end - connect \$100 $and$libresoc.v:141704$6248_Y - connect \$102 $and$libresoc.v:141705$6249_Y - connect \$104 $and$libresoc.v:141706$6250_Y - connect \$106 $and$libresoc.v:141707$6251_Y - connect \$108 $and$libresoc.v:141708$6252_Y - connect \$10 $or$libresoc.v:141709$6253_Y - connect \$110 $and$libresoc.v:141710$6254_Y - connect \$112 $and$libresoc.v:141711$6255_Y - connect \$114 $and$libresoc.v:141712$6256_Y - connect \$116 $and$libresoc.v:141713$6257_Y - connect \$118 $and$libresoc.v:141714$6258_Y - connect \$120 $and$libresoc.v:141715$6259_Y - connect \$122 $and$libresoc.v:141716$6260_Y - connect \$124 $and$libresoc.v:141717$6261_Y - connect \$126 $eq$libresoc.v:141718$6262_Y - connect \$128 $and$libresoc.v:141719$6263_Y - connect \$12 $or$libresoc.v:141720$6264_Y - connect \$130 $and$libresoc.v:141721$6265_Y - connect \$132 $and$libresoc.v:141722$6266_Y - connect \$134 $or$libresoc.v:141723$6267_Y - connect \$136 $or$libresoc.v:141724$6268_Y - connect \$138 $or$libresoc.v:141725$6269_Y - connect \$140 $and$libresoc.v:141726$6270_Y - connect \$142 $and$libresoc.v:141727$6271_Y - connect \$145 $or$libresoc.v:141728$6272_Y - connect \$147 $or$libresoc.v:141729$6273_Y - connect \$144 $not$libresoc.v:141730$6274_Y - connect \$14 $or$libresoc.v:141731$6275_Y - connect \$150 $and$libresoc.v:141732$6276_Y - connect \$152 $or$libresoc.v:141733$6277_Y - connect \$154 $and$libresoc.v:141734$6278_Y - connect \$156 $not$libresoc.v:141735$6279_Y - connect \$158 $or$libresoc.v:141736$6280_Y - connect \$160 $and$libresoc.v:141737$6281_Y - connect \$162 $eq$libresoc.v:141738$6282_Y - connect \$164 $and$libresoc.v:141739$6283_Y - connect \$167 $eq$libresoc.v:141740$6284_Y - connect \$16 $or$libresoc.v:141741$6285_Y - connect \$169 $and$libresoc.v:141742$6286_Y - connect \$171 $and$libresoc.v:141743$6287_Y - connect \$173 $and$libresoc.v:141744$6288_Y - connect \$175 $pos$libresoc.v:141745$6290_Y - connect \$177 $and$libresoc.v:141746$6291_Y - connect \$186 $pos$libresoc.v:141747$6293_Y - connect \$188 $pos$libresoc.v:141748$6294_Y - connect \$18 $or$libresoc.v:141749$6295_Y - connect \$190 $pos$libresoc.v:141750$6296_Y - connect \$192 $eq$libresoc.v:141751$6297_Y - connect \$194 $pos$libresoc.v:141752$6299_Y - connect \$196 $pos$libresoc.v:141753$6300_Y - connect \$198 $pos$libresoc.v:141754$6301_Y - connect \$20 $or$libresoc.v:141755$6302_Y - connect \$22 $eq$libresoc.v:141756$6303_Y - connect \$24 $eq$libresoc.v:141757$6304_Y - connect \$26 $and$libresoc.v:141758$6305_Y - connect \$28 $and$libresoc.v:141759$6306_Y - connect \$30 $not$libresoc.v:141760$6307_Y - connect \$32 $and$libresoc.v:141761$6308_Y - connect \$34 $not$libresoc.v:141762$6309_Y - connect \$36 $and$libresoc.v:141763$6310_Y - connect \$39 $not$libresoc.v:141764$6311_Y - connect \$41 $eq$libresoc.v:141765$6312_Y - connect \$43 $and$libresoc.v:141766$6313_Y - connect \$45 $or$libresoc.v:141767$6314_Y - connect \$47 $not$libresoc.v:141768$6315_Y - connect \$49 $eq$libresoc.v:141769$6316_Y - connect \$51 $and$libresoc.v:141770$6317_Y - connect \$53 $or$libresoc.v:141771$6318_Y - connect \$55 $or$libresoc.v:141772$6319_Y - connect \$57 $and$libresoc.v:141773$6320_Y - connect \$59 $or$libresoc.v:141774$6321_Y - connect \$61 $or$libresoc.v:141775$6322_Y - connect \$63 $or$libresoc.v:141776$6323_Y - connect \$65 $ternary$libresoc.v:141777$6324_Y - connect \$67 $ternary$libresoc.v:141778$6325_Y - connect \$69 $ternary$libresoc.v:141779$6326_Y - connect \$71 $ternary$libresoc.v:141780$6327_Y - connect \$74 $add$libresoc.v:141781$6328_Y - connect \$76 $and$libresoc.v:141782$6329_Y - connect \$78 $not$libresoc.v:141783$6330_Y - connect \$80 $and$libresoc.v:141784$6331_Y - connect \$82 $not$libresoc.v:141785$6332_Y - connect \$84 $and$libresoc.v:141786$6333_Y - connect \$86 $and$libresoc.v:141787$6334_Y - connect \$88 $and$libresoc.v:141788$6335_Y - connect \$8 $or$libresoc.v:141789$6336_Y - connect \$90 $or$libresoc.v:141790$6337_Y - connect \$93 $or$libresoc.v:141791$6338_Y - connect \$92 $not$libresoc.v:141792$6339_Y - connect \$96 $and$libresoc.v:141793$6340_Y - connect \$98 $not$libresoc.v:141794$6341_Y + connect \$100 $and$libresoc.v:141703$6248_Y + connect \$102 $and$libresoc.v:141704$6249_Y + connect \$104 $and$libresoc.v:141705$6250_Y + connect \$106 $and$libresoc.v:141706$6251_Y + connect \$108 $and$libresoc.v:141707$6252_Y + connect \$10 $or$libresoc.v:141708$6253_Y + connect \$110 $and$libresoc.v:141709$6254_Y + connect \$112 $and$libresoc.v:141710$6255_Y + connect \$114 $and$libresoc.v:141711$6256_Y + connect \$116 $and$libresoc.v:141712$6257_Y + connect \$118 $and$libresoc.v:141713$6258_Y + connect \$120 $and$libresoc.v:141714$6259_Y + connect \$122 $and$libresoc.v:141715$6260_Y + connect \$124 $and$libresoc.v:141716$6261_Y + connect \$126 $eq$libresoc.v:141717$6262_Y + connect \$128 $and$libresoc.v:141718$6263_Y + connect \$12 $or$libresoc.v:141719$6264_Y + connect \$130 $and$libresoc.v:141720$6265_Y + connect \$132 $and$libresoc.v:141721$6266_Y + connect \$134 $or$libresoc.v:141722$6267_Y + connect \$136 $or$libresoc.v:141723$6268_Y + connect \$138 $or$libresoc.v:141724$6269_Y + connect \$140 $and$libresoc.v:141725$6270_Y + connect \$142 $and$libresoc.v:141726$6271_Y + connect \$145 $or$libresoc.v:141727$6272_Y + connect \$147 $or$libresoc.v:141728$6273_Y + connect \$144 $not$libresoc.v:141729$6274_Y + connect \$14 $or$libresoc.v:141730$6275_Y + connect \$150 $and$libresoc.v:141731$6276_Y + connect \$152 $or$libresoc.v:141732$6277_Y + connect \$154 $and$libresoc.v:141733$6278_Y + connect \$156 $not$libresoc.v:141734$6279_Y + connect \$158 $or$libresoc.v:141735$6280_Y + connect \$160 $and$libresoc.v:141736$6281_Y + connect \$162 $eq$libresoc.v:141737$6282_Y + connect \$164 $and$libresoc.v:141738$6283_Y + connect \$167 $eq$libresoc.v:141739$6284_Y + connect \$16 $or$libresoc.v:141740$6285_Y + connect \$169 $and$libresoc.v:141741$6286_Y + connect \$171 $and$libresoc.v:141742$6287_Y + connect \$173 $and$libresoc.v:141743$6288_Y + connect \$175 $pos$libresoc.v:141744$6290_Y + connect \$177 $and$libresoc.v:141745$6291_Y + connect \$186 $pos$libresoc.v:141746$6293_Y + connect \$188 $pos$libresoc.v:141747$6294_Y + connect \$18 $or$libresoc.v:141748$6295_Y + connect \$190 $pos$libresoc.v:141749$6296_Y + connect \$192 $eq$libresoc.v:141750$6297_Y + connect \$194 $pos$libresoc.v:141751$6299_Y + connect \$196 $pos$libresoc.v:141752$6300_Y + connect \$198 $pos$libresoc.v:141753$6301_Y + connect \$20 $or$libresoc.v:141754$6302_Y + connect \$22 $eq$libresoc.v:141755$6303_Y + connect \$24 $eq$libresoc.v:141756$6304_Y + connect \$26 $and$libresoc.v:141757$6305_Y + connect \$28 $and$libresoc.v:141758$6306_Y + connect \$30 $not$libresoc.v:141759$6307_Y + connect \$32 $and$libresoc.v:141760$6308_Y + connect \$34 $not$libresoc.v:141761$6309_Y + connect \$36 $and$libresoc.v:141762$6310_Y + connect \$39 $not$libresoc.v:141763$6311_Y + connect \$41 $eq$libresoc.v:141764$6312_Y + connect \$43 $and$libresoc.v:141765$6313_Y + connect \$45 $or$libresoc.v:141766$6314_Y + connect \$47 $not$libresoc.v:141767$6315_Y + connect \$49 $eq$libresoc.v:141768$6316_Y + connect \$51 $and$libresoc.v:141769$6317_Y + connect \$53 $or$libresoc.v:141770$6318_Y + connect \$55 $or$libresoc.v:141771$6319_Y + connect \$57 $and$libresoc.v:141772$6320_Y + connect \$59 $or$libresoc.v:141773$6321_Y + connect \$61 $or$libresoc.v:141774$6322_Y + connect \$63 $or$libresoc.v:141775$6323_Y + connect \$65 $ternary$libresoc.v:141776$6324_Y + connect \$67 $ternary$libresoc.v:141777$6325_Y + connect \$69 $ternary$libresoc.v:141778$6326_Y + connect \$71 $ternary$libresoc.v:141779$6327_Y + connect \$74 $add$libresoc.v:141780$6328_Y + connect \$76 $and$libresoc.v:141781$6329_Y + connect \$78 $not$libresoc.v:141782$6330_Y + connect \$80 $and$libresoc.v:141783$6331_Y + connect \$82 $not$libresoc.v:141784$6332_Y + connect \$84 $and$libresoc.v:141785$6333_Y + connect \$86 $and$libresoc.v:141786$6334_Y + connect \$88 $and$libresoc.v:141787$6335_Y + connect \$8 $or$libresoc.v:141788$6336_Y + connect \$90 $or$libresoc.v:141789$6337_Y + connect \$93 $or$libresoc.v:141790$6338_Y + connect \$92 $not$libresoc.v:141791$6339_Y + connect \$96 $and$libresoc.v:141792$6340_Y + connect \$98 $not$libresoc.v:141793$6341_Y connect \$38 \$55 connect \$73 \$74 connect \$166 \$169 @@ -229806,271 +229806,271 @@ module \ldst0 connect \reset_o \$10 connect \reset_i \$8 end -attribute \src "libresoc.v:142320.1-142907.10" +attribute \src "libresoc.v:142319.1-142906.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" attribute \generator "nMigen" module \left_mask - attribute \src "libresoc.v:142321.7-142321.20" + attribute \src "libresoc.v:142320.7-142320.20" wire $0\initial[0:0] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $10\mask[9:9] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $11\mask[10:10] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $12\mask[11:11] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $13\mask[12:12] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $14\mask[13:13] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $15\mask[14:14] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $16\mask[15:15] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $17\mask[16:16] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $18\mask[17:17] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $19\mask[18:18] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $1\mask[0:0] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $20\mask[19:19] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $21\mask[20:20] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $22\mask[21:21] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $23\mask[22:22] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $24\mask[23:23] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $25\mask[24:24] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $26\mask[25:25] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $27\mask[26:26] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $28\mask[27:27] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $29\mask[28:28] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $2\mask[1:1] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $30\mask[29:29] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $31\mask[30:30] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $32\mask[31:31] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $33\mask[32:32] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $34\mask[33:33] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $35\mask[34:34] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $36\mask[35:35] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $37\mask[36:36] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $38\mask[37:37] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $39\mask[38:38] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $3\mask[2:2] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $40\mask[39:39] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $41\mask[40:40] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $42\mask[41:41] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $43\mask[42:42] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $44\mask[43:43] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $45\mask[44:44] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $46\mask[45:45] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $47\mask[46:46] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $48\mask[47:47] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $49\mask[48:48] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $4\mask[3:3] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $50\mask[49:49] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $51\mask[50:50] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $52\mask[51:51] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $53\mask[52:52] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $54\mask[53:53] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $55\mask[54:54] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $56\mask[55:55] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $57\mask[56:56] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $58\mask[57:57] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $59\mask[58:58] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $5\mask[4:4] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $60\mask[59:59] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $61\mask[60:60] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $62\mask[61:61] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $63\mask[62:62] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $64\mask[63:63] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $6\mask[5:5] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $7\mask[6:6] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $8\mask[7:7] - attribute \src "libresoc.v:142519.3-142906.6" + attribute \src "libresoc.v:142518.3-142905.6" wire $9\mask[8:8] - attribute \src "libresoc.v:142455.17-142455.96" - wire $gt$libresoc.v:142455$6526_Y - attribute \src "libresoc.v:142456.18-142456.98" - wire $gt$libresoc.v:142456$6527_Y + attribute \src "libresoc.v:142454.17-142454.96" + wire $gt$libresoc.v:142454$6526_Y + attribute \src "libresoc.v:142455.18-142455.98" + wire $gt$libresoc.v:142455$6527_Y + attribute \src "libresoc.v:142456.19-142456.99" + wire $gt$libresoc.v:142456$6528_Y attribute \src "libresoc.v:142457.19-142457.99" - wire $gt$libresoc.v:142457$6528_Y + wire $gt$libresoc.v:142457$6529_Y attribute \src "libresoc.v:142458.19-142458.99" - wire $gt$libresoc.v:142458$6529_Y + wire $gt$libresoc.v:142458$6530_Y attribute \src "libresoc.v:142459.19-142459.99" - wire $gt$libresoc.v:142459$6530_Y + wire $gt$libresoc.v:142459$6531_Y attribute \src "libresoc.v:142460.19-142460.99" - wire $gt$libresoc.v:142460$6531_Y + wire $gt$libresoc.v:142460$6532_Y attribute \src "libresoc.v:142461.19-142461.99" - wire $gt$libresoc.v:142461$6532_Y + wire $gt$libresoc.v:142461$6533_Y attribute \src "libresoc.v:142462.19-142462.99" - wire $gt$libresoc.v:142462$6533_Y + wire $gt$libresoc.v:142462$6534_Y attribute \src "libresoc.v:142463.19-142463.99" - wire $gt$libresoc.v:142463$6534_Y + wire $gt$libresoc.v:142463$6535_Y attribute \src "libresoc.v:142464.19-142464.99" - wire $gt$libresoc.v:142464$6535_Y - attribute \src "libresoc.v:142465.19-142465.99" - wire $gt$libresoc.v:142465$6536_Y - attribute \src "libresoc.v:142466.18-142466.97" - wire $gt$libresoc.v:142466$6537_Y + wire $gt$libresoc.v:142464$6536_Y + attribute \src "libresoc.v:142465.18-142465.97" + wire $gt$libresoc.v:142465$6537_Y + attribute \src "libresoc.v:142466.19-142466.99" + wire $gt$libresoc.v:142466$6538_Y attribute \src "libresoc.v:142467.19-142467.99" - wire $gt$libresoc.v:142467$6538_Y + wire $gt$libresoc.v:142467$6539_Y attribute \src "libresoc.v:142468.19-142468.99" - wire $gt$libresoc.v:142468$6539_Y + wire $gt$libresoc.v:142468$6540_Y attribute \src "libresoc.v:142469.19-142469.99" - wire $gt$libresoc.v:142469$6540_Y + wire $gt$libresoc.v:142469$6541_Y attribute \src "libresoc.v:142470.19-142470.99" - wire $gt$libresoc.v:142470$6541_Y - attribute \src "libresoc.v:142471.19-142471.99" - wire $gt$libresoc.v:142471$6542_Y + wire $gt$libresoc.v:142470$6542_Y + attribute \src "libresoc.v:142471.18-142471.97" + wire $gt$libresoc.v:142471$6543_Y attribute \src "libresoc.v:142472.18-142472.97" - wire $gt$libresoc.v:142472$6543_Y + wire $gt$libresoc.v:142472$6544_Y attribute \src "libresoc.v:142473.18-142473.97" - wire $gt$libresoc.v:142473$6544_Y - attribute \src "libresoc.v:142474.18-142474.97" - wire $gt$libresoc.v:142474$6545_Y - attribute \src "libresoc.v:142475.17-142475.96" - wire $gt$libresoc.v:142475$6546_Y + wire $gt$libresoc.v:142473$6545_Y + attribute \src "libresoc.v:142474.17-142474.96" + wire $gt$libresoc.v:142474$6546_Y + attribute \src "libresoc.v:142475.18-142475.97" + wire $gt$libresoc.v:142475$6547_Y attribute \src "libresoc.v:142476.18-142476.97" - wire $gt$libresoc.v:142476$6547_Y + wire $gt$libresoc.v:142476$6548_Y attribute \src "libresoc.v:142477.18-142477.97" - wire $gt$libresoc.v:142477$6548_Y + wire $gt$libresoc.v:142477$6549_Y attribute \src "libresoc.v:142478.18-142478.97" - wire $gt$libresoc.v:142478$6549_Y + wire $gt$libresoc.v:142478$6550_Y attribute \src "libresoc.v:142479.18-142479.97" - wire $gt$libresoc.v:142479$6550_Y + wire $gt$libresoc.v:142479$6551_Y attribute \src "libresoc.v:142480.18-142480.97" - wire $gt$libresoc.v:142480$6551_Y + wire $gt$libresoc.v:142480$6552_Y attribute \src "libresoc.v:142481.18-142481.97" - wire $gt$libresoc.v:142481$6552_Y - attribute \src "libresoc.v:142482.18-142482.97" - wire $gt$libresoc.v:142482$6553_Y + wire $gt$libresoc.v:142481$6553_Y + attribute \src "libresoc.v:142482.18-142482.98" + wire $gt$libresoc.v:142482$6554_Y attribute \src "libresoc.v:142483.18-142483.98" - wire $gt$libresoc.v:142483$6554_Y + wire $gt$libresoc.v:142483$6555_Y attribute \src "libresoc.v:142484.18-142484.98" - wire $gt$libresoc.v:142484$6555_Y - attribute \src "libresoc.v:142485.18-142485.98" - wire $gt$libresoc.v:142485$6556_Y - attribute \src "libresoc.v:142486.17-142486.96" - wire $gt$libresoc.v:142486$6557_Y + wire $gt$libresoc.v:142484$6556_Y + attribute \src "libresoc.v:142485.17-142485.96" + wire $gt$libresoc.v:142485$6557_Y + attribute \src "libresoc.v:142486.18-142486.98" + wire $gt$libresoc.v:142486$6558_Y attribute \src "libresoc.v:142487.18-142487.98" - wire $gt$libresoc.v:142487$6558_Y + wire $gt$libresoc.v:142487$6559_Y attribute \src "libresoc.v:142488.18-142488.98" - wire $gt$libresoc.v:142488$6559_Y + wire $gt$libresoc.v:142488$6560_Y attribute \src "libresoc.v:142489.18-142489.98" - wire $gt$libresoc.v:142489$6560_Y + wire $gt$libresoc.v:142489$6561_Y attribute \src "libresoc.v:142490.18-142490.98" - wire $gt$libresoc.v:142490$6561_Y + wire $gt$libresoc.v:142490$6562_Y attribute \src "libresoc.v:142491.18-142491.98" - wire $gt$libresoc.v:142491$6562_Y + wire $gt$libresoc.v:142491$6563_Y attribute \src "libresoc.v:142492.18-142492.98" - wire $gt$libresoc.v:142492$6563_Y + wire $gt$libresoc.v:142492$6564_Y attribute \src "libresoc.v:142493.18-142493.98" - wire $gt$libresoc.v:142493$6564_Y + wire $gt$libresoc.v:142493$6565_Y attribute \src "libresoc.v:142494.18-142494.98" - wire $gt$libresoc.v:142494$6565_Y + wire $gt$libresoc.v:142494$6566_Y attribute \src "libresoc.v:142495.18-142495.98" - wire $gt$libresoc.v:142495$6566_Y - attribute \src "libresoc.v:142496.18-142496.98" - wire $gt$libresoc.v:142496$6567_Y - attribute \src "libresoc.v:142497.17-142497.96" - wire $gt$libresoc.v:142497$6568_Y + wire $gt$libresoc.v:142495$6567_Y + attribute \src "libresoc.v:142496.17-142496.96" + wire $gt$libresoc.v:142496$6568_Y + attribute \src "libresoc.v:142497.18-142497.98" + wire $gt$libresoc.v:142497$6569_Y attribute \src "libresoc.v:142498.18-142498.98" - wire $gt$libresoc.v:142498$6569_Y + wire $gt$libresoc.v:142498$6570_Y attribute \src "libresoc.v:142499.18-142499.98" - wire $gt$libresoc.v:142499$6570_Y + wire $gt$libresoc.v:142499$6571_Y attribute \src "libresoc.v:142500.18-142500.98" - wire $gt$libresoc.v:142500$6571_Y + wire $gt$libresoc.v:142500$6572_Y attribute \src "libresoc.v:142501.18-142501.98" - wire $gt$libresoc.v:142501$6572_Y + wire $gt$libresoc.v:142501$6573_Y attribute \src "libresoc.v:142502.18-142502.98" - wire $gt$libresoc.v:142502$6573_Y + wire $gt$libresoc.v:142502$6574_Y attribute \src "libresoc.v:142503.18-142503.98" - wire $gt$libresoc.v:142503$6574_Y + wire $gt$libresoc.v:142503$6575_Y attribute \src "libresoc.v:142504.18-142504.98" - wire $gt$libresoc.v:142504$6575_Y + wire $gt$libresoc.v:142504$6576_Y attribute \src "libresoc.v:142505.18-142505.98" - wire $gt$libresoc.v:142505$6576_Y + wire $gt$libresoc.v:142505$6577_Y attribute \src "libresoc.v:142506.18-142506.98" - wire $gt$libresoc.v:142506$6577_Y - attribute \src "libresoc.v:142507.18-142507.98" - wire $gt$libresoc.v:142507$6578_Y - attribute \src "libresoc.v:142508.17-142508.96" - wire $gt$libresoc.v:142508$6579_Y + wire $gt$libresoc.v:142506$6578_Y + attribute \src "libresoc.v:142507.17-142507.96" + wire $gt$libresoc.v:142507$6579_Y + attribute \src "libresoc.v:142508.18-142508.98" + wire $gt$libresoc.v:142508$6580_Y attribute \src "libresoc.v:142509.18-142509.98" - wire $gt$libresoc.v:142509$6580_Y + wire $gt$libresoc.v:142509$6581_Y attribute \src "libresoc.v:142510.18-142510.98" - wire $gt$libresoc.v:142510$6581_Y + wire $gt$libresoc.v:142510$6582_Y attribute \src "libresoc.v:142511.18-142511.98" - wire $gt$libresoc.v:142511$6582_Y + wire $gt$libresoc.v:142511$6583_Y attribute \src "libresoc.v:142512.18-142512.98" - wire $gt$libresoc.v:142512$6583_Y + wire $gt$libresoc.v:142512$6584_Y attribute \src "libresoc.v:142513.18-142513.98" - wire $gt$libresoc.v:142513$6584_Y + wire $gt$libresoc.v:142513$6585_Y attribute \src "libresoc.v:142514.18-142514.98" - wire $gt$libresoc.v:142514$6585_Y + wire $gt$libresoc.v:142514$6586_Y attribute \src "libresoc.v:142515.18-142515.98" - wire $gt$libresoc.v:142515$6586_Y + wire $gt$libresoc.v:142515$6587_Y attribute \src "libresoc.v:142516.18-142516.98" - wire $gt$libresoc.v:142516$6587_Y + wire $gt$libresoc.v:142516$6588_Y attribute \src "libresoc.v:142517.18-142517.98" - wire $gt$libresoc.v:142517$6588_Y - attribute \src "libresoc.v:142518.18-142518.98" - wire $gt$libresoc.v:142518$6589_Y + wire $gt$libresoc.v:142517$6589_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" @@ -230199,14 +230199,14 @@ module \left_mask wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 - attribute \src "libresoc.v:142321.7-142321.15" + attribute \src "libresoc.v:142320.7-142320.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142455$6526 + cell $gt $gt$libresoc.v:142454$6526 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230214,10 +230214,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:142455$6526_Y + connect \Y $gt$libresoc.v:142454$6526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142456$6527 + cell $gt $gt$libresoc.v:142455$6527 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230225,10 +230225,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:142456$6527_Y + connect \Y $gt$libresoc.v:142455$6527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142457$6528 + cell $gt $gt$libresoc.v:142456$6528 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230236,10 +230236,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:142457$6528_Y + connect \Y $gt$libresoc.v:142456$6528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142458$6529 + cell $gt $gt$libresoc.v:142457$6529 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230247,10 +230247,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:142458$6529_Y + connect \Y $gt$libresoc.v:142457$6529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142459$6530 + cell $gt $gt$libresoc.v:142458$6530 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230258,10 +230258,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:142459$6530_Y + connect \Y $gt$libresoc.v:142458$6530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142460$6531 + cell $gt $gt$libresoc.v:142459$6531 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230269,10 +230269,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:142460$6531_Y + connect \Y $gt$libresoc.v:142459$6531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142461$6532 + cell $gt $gt$libresoc.v:142460$6532 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230280,10 +230280,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:142461$6532_Y + connect \Y $gt$libresoc.v:142460$6532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142462$6533 + cell $gt $gt$libresoc.v:142461$6533 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230291,10 +230291,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:142462$6533_Y + connect \Y $gt$libresoc.v:142461$6533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142463$6534 + cell $gt $gt$libresoc.v:142462$6534 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230302,10 +230302,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:142463$6534_Y + connect \Y $gt$libresoc.v:142462$6534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142464$6535 + cell $gt $gt$libresoc.v:142463$6535 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230313,10 +230313,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:142464$6535_Y + connect \Y $gt$libresoc.v:142463$6535_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142465$6536 + cell $gt $gt$libresoc.v:142464$6536 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230324,10 +230324,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:142465$6536_Y + connect \Y $gt$libresoc.v:142464$6536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142466$6537 + cell $gt $gt$libresoc.v:142465$6537 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230335,10 +230335,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:142466$6537_Y + connect \Y $gt$libresoc.v:142465$6537_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142467$6538 + cell $gt $gt$libresoc.v:142466$6538 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230346,10 +230346,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:142467$6538_Y + connect \Y $gt$libresoc.v:142466$6538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142468$6539 + cell $gt $gt$libresoc.v:142467$6539 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230357,10 +230357,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:142468$6539_Y + connect \Y $gt$libresoc.v:142467$6539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142469$6540 + cell $gt $gt$libresoc.v:142468$6540 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230368,10 +230368,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:142469$6540_Y + connect \Y $gt$libresoc.v:142468$6540_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142470$6541 + cell $gt $gt$libresoc.v:142469$6541 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230379,10 +230379,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:142470$6541_Y + connect \Y $gt$libresoc.v:142469$6541_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142471$6542 + cell $gt $gt$libresoc.v:142470$6542 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230390,10 +230390,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:142471$6542_Y + connect \Y $gt$libresoc.v:142470$6542_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142472$6543 + cell $gt $gt$libresoc.v:142471$6543 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230401,10 +230401,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:142472$6543_Y + connect \Y $gt$libresoc.v:142471$6543_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142473$6544 + cell $gt $gt$libresoc.v:142472$6544 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230412,10 +230412,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:142473$6544_Y + connect \Y $gt$libresoc.v:142472$6544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142474$6545 + cell $gt $gt$libresoc.v:142473$6545 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230423,10 +230423,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:142474$6545_Y + connect \Y $gt$libresoc.v:142473$6545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142475$6546 + cell $gt $gt$libresoc.v:142474$6546 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230434,10 +230434,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:142475$6546_Y + connect \Y $gt$libresoc.v:142474$6546_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142476$6547 + cell $gt $gt$libresoc.v:142475$6547 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230445,10 +230445,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:142476$6547_Y + connect \Y $gt$libresoc.v:142475$6547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142477$6548 + cell $gt $gt$libresoc.v:142476$6548 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230456,10 +230456,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:142477$6548_Y + connect \Y $gt$libresoc.v:142476$6548_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142478$6549 + cell $gt $gt$libresoc.v:142477$6549 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230467,10 +230467,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:142478$6549_Y + connect \Y $gt$libresoc.v:142477$6549_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142479$6550 + cell $gt $gt$libresoc.v:142478$6550 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230478,10 +230478,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:142479$6550_Y + connect \Y $gt$libresoc.v:142478$6550_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142480$6551 + cell $gt $gt$libresoc.v:142479$6551 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230489,10 +230489,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:142480$6551_Y + connect \Y $gt$libresoc.v:142479$6551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142481$6552 + cell $gt $gt$libresoc.v:142480$6552 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230500,10 +230500,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:142481$6552_Y + connect \Y $gt$libresoc.v:142480$6552_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142482$6553 + cell $gt $gt$libresoc.v:142481$6553 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230511,10 +230511,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:142482$6553_Y + connect \Y $gt$libresoc.v:142481$6553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142483$6554 + cell $gt $gt$libresoc.v:142482$6554 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230522,10 +230522,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:142483$6554_Y + connect \Y $gt$libresoc.v:142482$6554_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142484$6555 + cell $gt $gt$libresoc.v:142483$6555 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230533,10 +230533,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:142484$6555_Y + connect \Y $gt$libresoc.v:142483$6555_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142485$6556 + cell $gt $gt$libresoc.v:142484$6556 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230544,10 +230544,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:142485$6556_Y + connect \Y $gt$libresoc.v:142484$6556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142486$6557 + cell $gt $gt$libresoc.v:142485$6557 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230555,10 +230555,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:142486$6557_Y + connect \Y $gt$libresoc.v:142485$6557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142487$6558 + cell $gt $gt$libresoc.v:142486$6558 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230566,10 +230566,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:142487$6558_Y + connect \Y $gt$libresoc.v:142486$6558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142488$6559 + cell $gt $gt$libresoc.v:142487$6559 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230577,10 +230577,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:142488$6559_Y + connect \Y $gt$libresoc.v:142487$6559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142489$6560 + cell $gt $gt$libresoc.v:142488$6560 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230588,10 +230588,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:142489$6560_Y + connect \Y $gt$libresoc.v:142488$6560_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142490$6561 + cell $gt $gt$libresoc.v:142489$6561 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230599,10 +230599,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:142490$6561_Y + connect \Y $gt$libresoc.v:142489$6561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142491$6562 + cell $gt $gt$libresoc.v:142490$6562 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230610,10 +230610,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:142491$6562_Y + connect \Y $gt$libresoc.v:142490$6562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142492$6563 + cell $gt $gt$libresoc.v:142491$6563 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230621,10 +230621,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:142492$6563_Y + connect \Y $gt$libresoc.v:142491$6563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142493$6564 + cell $gt $gt$libresoc.v:142492$6564 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230632,10 +230632,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:142493$6564_Y + connect \Y $gt$libresoc.v:142492$6564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142494$6565 + cell $gt $gt$libresoc.v:142493$6565 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230643,10 +230643,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:142494$6565_Y + connect \Y $gt$libresoc.v:142493$6565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142495$6566 + cell $gt $gt$libresoc.v:142494$6566 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230654,10 +230654,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:142495$6566_Y + connect \Y $gt$libresoc.v:142494$6566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142496$6567 + cell $gt $gt$libresoc.v:142495$6567 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230665,10 +230665,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:142496$6567_Y + connect \Y $gt$libresoc.v:142495$6567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142497$6568 + cell $gt $gt$libresoc.v:142496$6568 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230676,10 +230676,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:142497$6568_Y + connect \Y $gt$libresoc.v:142496$6568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142498$6569 + cell $gt $gt$libresoc.v:142497$6569 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230687,10 +230687,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:142498$6569_Y + connect \Y $gt$libresoc.v:142497$6569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142499$6570 + cell $gt $gt$libresoc.v:142498$6570 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230698,10 +230698,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:142499$6570_Y + connect \Y $gt$libresoc.v:142498$6570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142500$6571 + cell $gt $gt$libresoc.v:142499$6571 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230709,10 +230709,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:142500$6571_Y + connect \Y $gt$libresoc.v:142499$6571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142501$6572 + cell $gt $gt$libresoc.v:142500$6572 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230720,10 +230720,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:142501$6572_Y + connect \Y $gt$libresoc.v:142500$6572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142502$6573 + cell $gt $gt$libresoc.v:142501$6573 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230731,10 +230731,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:142502$6573_Y + connect \Y $gt$libresoc.v:142501$6573_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142503$6574 + cell $gt $gt$libresoc.v:142502$6574 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230742,10 +230742,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:142503$6574_Y + connect \Y $gt$libresoc.v:142502$6574_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142504$6575 + cell $gt $gt$libresoc.v:142503$6575 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230753,10 +230753,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:142504$6575_Y + connect \Y $gt$libresoc.v:142503$6575_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142505$6576 + cell $gt $gt$libresoc.v:142504$6576 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230764,10 +230764,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:142505$6576_Y + connect \Y $gt$libresoc.v:142504$6576_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142506$6577 + cell $gt $gt$libresoc.v:142505$6577 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230775,10 +230775,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:142506$6577_Y + connect \Y $gt$libresoc.v:142505$6577_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142507$6578 + cell $gt $gt$libresoc.v:142506$6578 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230786,10 +230786,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:142507$6578_Y + connect \Y $gt$libresoc.v:142506$6578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142508$6579 + cell $gt $gt$libresoc.v:142507$6579 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230797,10 +230797,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:142508$6579_Y + connect \Y $gt$libresoc.v:142507$6579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142509$6580 + cell $gt $gt$libresoc.v:142508$6580 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230808,10 +230808,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:142509$6580_Y + connect \Y $gt$libresoc.v:142508$6580_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142510$6581 + cell $gt $gt$libresoc.v:142509$6581 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230819,10 +230819,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:142510$6581_Y + connect \Y $gt$libresoc.v:142509$6581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142511$6582 + cell $gt $gt$libresoc.v:142510$6582 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230830,10 +230830,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:142511$6582_Y + connect \Y $gt$libresoc.v:142510$6582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142512$6583 + cell $gt $gt$libresoc.v:142511$6583 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230841,10 +230841,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:142512$6583_Y + connect \Y $gt$libresoc.v:142511$6583_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142513$6584 + cell $gt $gt$libresoc.v:142512$6584 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230852,10 +230852,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:142513$6584_Y + connect \Y $gt$libresoc.v:142512$6584_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142514$6585 + cell $gt $gt$libresoc.v:142513$6585 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230863,10 +230863,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:142514$6585_Y + connect \Y $gt$libresoc.v:142513$6585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142515$6586 + cell $gt $gt$libresoc.v:142514$6586 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230874,10 +230874,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:142515$6586_Y + connect \Y $gt$libresoc.v:142514$6586_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142516$6587 + cell $gt $gt$libresoc.v:142515$6587 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230885,10 +230885,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:142516$6587_Y + connect \Y $gt$libresoc.v:142515$6587_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142517$6588 + cell $gt $gt$libresoc.v:142516$6588 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230896,10 +230896,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:142517$6588_Y + connect \Y $gt$libresoc.v:142516$6588_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142518$6589 + cell $gt $gt$libresoc.v:142517$6589 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230907,18 +230907,18 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:142518$6589_Y + connect \Y $gt$libresoc.v:142517$6589_Y end - attribute \src "libresoc.v:142321.7-142321.20" - process $proc$libresoc.v:142321$6591 + attribute \src "libresoc.v:142320.7-142320.20" + process $proc$libresoc.v:142320$6591 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:142519.3-142906.6" - process $proc$libresoc.v:142519$6590 + attribute \src "libresoc.v:142518.3-142905.6" + process $proc$libresoc.v:142518$6590 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -230985,9 +230985,9 @@ module \left_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:142520.5-142520.29" + attribute \src "libresoc.v:142519.5-142519.29" switch \initial - attribute \src "libresoc.v:142520.9-142520.17" + attribute \src "libresoc.v:142519.9-142519.17" case 1'1 case end @@ -231570,86 +231570,86 @@ module \left_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:142455$6526_Y - connect \$99 $gt$libresoc.v:142456$6527_Y - connect \$101 $gt$libresoc.v:142457$6528_Y - connect \$103 $gt$libresoc.v:142458$6529_Y - connect \$105 $gt$libresoc.v:142459$6530_Y - connect \$107 $gt$libresoc.v:142460$6531_Y - connect \$109 $gt$libresoc.v:142461$6532_Y - connect \$111 $gt$libresoc.v:142462$6533_Y - connect \$113 $gt$libresoc.v:142463$6534_Y - connect \$115 $gt$libresoc.v:142464$6535_Y - connect \$117 $gt$libresoc.v:142465$6536_Y - connect \$11 $gt$libresoc.v:142466$6537_Y - connect \$119 $gt$libresoc.v:142467$6538_Y - connect \$121 $gt$libresoc.v:142468$6539_Y - connect \$123 $gt$libresoc.v:142469$6540_Y - connect \$125 $gt$libresoc.v:142470$6541_Y - connect \$127 $gt$libresoc.v:142471$6542_Y - connect \$13 $gt$libresoc.v:142472$6543_Y - connect \$15 $gt$libresoc.v:142473$6544_Y - connect \$17 $gt$libresoc.v:142474$6545_Y - connect \$1 $gt$libresoc.v:142475$6546_Y - connect \$19 $gt$libresoc.v:142476$6547_Y - connect \$21 $gt$libresoc.v:142477$6548_Y - connect \$23 $gt$libresoc.v:142478$6549_Y - connect \$25 $gt$libresoc.v:142479$6550_Y - connect \$27 $gt$libresoc.v:142480$6551_Y - connect \$29 $gt$libresoc.v:142481$6552_Y - connect \$31 $gt$libresoc.v:142482$6553_Y - connect \$33 $gt$libresoc.v:142483$6554_Y - connect \$35 $gt$libresoc.v:142484$6555_Y - connect \$37 $gt$libresoc.v:142485$6556_Y - connect \$3 $gt$libresoc.v:142486$6557_Y - connect \$39 $gt$libresoc.v:142487$6558_Y - connect \$41 $gt$libresoc.v:142488$6559_Y - connect \$43 $gt$libresoc.v:142489$6560_Y - connect \$45 $gt$libresoc.v:142490$6561_Y - connect \$47 $gt$libresoc.v:142491$6562_Y - connect \$49 $gt$libresoc.v:142492$6563_Y - connect \$51 $gt$libresoc.v:142493$6564_Y - connect \$53 $gt$libresoc.v:142494$6565_Y - connect \$55 $gt$libresoc.v:142495$6566_Y - connect \$57 $gt$libresoc.v:142496$6567_Y - connect \$5 $gt$libresoc.v:142497$6568_Y - connect \$59 $gt$libresoc.v:142498$6569_Y - connect \$61 $gt$libresoc.v:142499$6570_Y - connect \$63 $gt$libresoc.v:142500$6571_Y - connect \$65 $gt$libresoc.v:142501$6572_Y - connect \$67 $gt$libresoc.v:142502$6573_Y - connect \$69 $gt$libresoc.v:142503$6574_Y - connect \$71 $gt$libresoc.v:142504$6575_Y - connect \$73 $gt$libresoc.v:142505$6576_Y - connect \$75 $gt$libresoc.v:142506$6577_Y - connect \$77 $gt$libresoc.v:142507$6578_Y - connect \$7 $gt$libresoc.v:142508$6579_Y - connect \$79 $gt$libresoc.v:142509$6580_Y - connect \$81 $gt$libresoc.v:142510$6581_Y - connect \$83 $gt$libresoc.v:142511$6582_Y - connect \$85 $gt$libresoc.v:142512$6583_Y - connect \$87 $gt$libresoc.v:142513$6584_Y - connect \$89 $gt$libresoc.v:142514$6585_Y - connect \$91 $gt$libresoc.v:142515$6586_Y - connect \$93 $gt$libresoc.v:142516$6587_Y - connect \$95 $gt$libresoc.v:142517$6588_Y - connect \$97 $gt$libresoc.v:142518$6589_Y + connect \$9 $gt$libresoc.v:142454$6526_Y + connect \$99 $gt$libresoc.v:142455$6527_Y + connect \$101 $gt$libresoc.v:142456$6528_Y + connect \$103 $gt$libresoc.v:142457$6529_Y + connect \$105 $gt$libresoc.v:142458$6530_Y + connect \$107 $gt$libresoc.v:142459$6531_Y + connect \$109 $gt$libresoc.v:142460$6532_Y + connect \$111 $gt$libresoc.v:142461$6533_Y + connect \$113 $gt$libresoc.v:142462$6534_Y + connect \$115 $gt$libresoc.v:142463$6535_Y + connect \$117 $gt$libresoc.v:142464$6536_Y + connect \$11 $gt$libresoc.v:142465$6537_Y + connect \$119 $gt$libresoc.v:142466$6538_Y + connect \$121 $gt$libresoc.v:142467$6539_Y + connect \$123 $gt$libresoc.v:142468$6540_Y + connect \$125 $gt$libresoc.v:142469$6541_Y + connect \$127 $gt$libresoc.v:142470$6542_Y + connect \$13 $gt$libresoc.v:142471$6543_Y + connect \$15 $gt$libresoc.v:142472$6544_Y + connect \$17 $gt$libresoc.v:142473$6545_Y + connect \$1 $gt$libresoc.v:142474$6546_Y + connect \$19 $gt$libresoc.v:142475$6547_Y + connect \$21 $gt$libresoc.v:142476$6548_Y + connect \$23 $gt$libresoc.v:142477$6549_Y + connect \$25 $gt$libresoc.v:142478$6550_Y + connect \$27 $gt$libresoc.v:142479$6551_Y + connect \$29 $gt$libresoc.v:142480$6552_Y + connect \$31 $gt$libresoc.v:142481$6553_Y + connect \$33 $gt$libresoc.v:142482$6554_Y + connect \$35 $gt$libresoc.v:142483$6555_Y + connect \$37 $gt$libresoc.v:142484$6556_Y + connect \$3 $gt$libresoc.v:142485$6557_Y + connect \$39 $gt$libresoc.v:142486$6558_Y + connect \$41 $gt$libresoc.v:142487$6559_Y + connect \$43 $gt$libresoc.v:142488$6560_Y + connect \$45 $gt$libresoc.v:142489$6561_Y + connect \$47 $gt$libresoc.v:142490$6562_Y + connect \$49 $gt$libresoc.v:142491$6563_Y + connect \$51 $gt$libresoc.v:142492$6564_Y + connect \$53 $gt$libresoc.v:142493$6565_Y + connect \$55 $gt$libresoc.v:142494$6566_Y + connect \$57 $gt$libresoc.v:142495$6567_Y + connect \$5 $gt$libresoc.v:142496$6568_Y + connect \$59 $gt$libresoc.v:142497$6569_Y + connect \$61 $gt$libresoc.v:142498$6570_Y + connect \$63 $gt$libresoc.v:142499$6571_Y + connect \$65 $gt$libresoc.v:142500$6572_Y + connect \$67 $gt$libresoc.v:142501$6573_Y + connect \$69 $gt$libresoc.v:142502$6574_Y + connect \$71 $gt$libresoc.v:142503$6575_Y + connect \$73 $gt$libresoc.v:142504$6576_Y + connect \$75 $gt$libresoc.v:142505$6577_Y + connect \$77 $gt$libresoc.v:142506$6578_Y + connect \$7 $gt$libresoc.v:142507$6579_Y + connect \$79 $gt$libresoc.v:142508$6580_Y + connect \$81 $gt$libresoc.v:142509$6581_Y + connect \$83 $gt$libresoc.v:142510$6582_Y + connect \$85 $gt$libresoc.v:142511$6583_Y + connect \$87 $gt$libresoc.v:142512$6584_Y + connect \$89 $gt$libresoc.v:142513$6585_Y + connect \$91 $gt$libresoc.v:142514$6586_Y + connect \$93 $gt$libresoc.v:142515$6587_Y + connect \$95 $gt$libresoc.v:142516$6588_Y + connect \$97 $gt$libresoc.v:142517$6589_Y end -attribute \src "libresoc.v:142911.1-142940.10" +attribute \src "libresoc.v:142910.1-142939.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.lenexp" attribute \generator "nMigen" module \lenexp - attribute \src "libresoc.v:142935.17-142935.101" - wire width 64 $extend$libresoc.v:142935$6595_Y - attribute \src "libresoc.v:142935.17-142935.101" - wire width 64 $pos$libresoc.v:142935$6596_Y - attribute \src "libresoc.v:142932.17-142932.111" - wire width 20 $sshl$libresoc.v:142932$6592_Y - attribute \src "libresoc.v:142934.17-142934.113" - wire width 32 $sshl$libresoc.v:142934$6594_Y - attribute \src "libresoc.v:142933.17-142933.107" - wire width 21 $sub$libresoc.v:142933$6593_Y + attribute \src "libresoc.v:142934.17-142934.101" + wire width 64 $extend$libresoc.v:142934$6595_Y + attribute \src "libresoc.v:142934.17-142934.101" + wire width 64 $pos$libresoc.v:142934$6596_Y + attribute \src "libresoc.v:142931.17-142931.111" + wire width 20 $sshl$libresoc.v:142931$6592_Y + attribute \src "libresoc.v:142933.17-142933.113" + wire width 32 $sshl$libresoc.v:142933$6594_Y + attribute \src "libresoc.v:142932.17-142932.107" + wire width 21 $sub$libresoc.v:142932$6593_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" wire width 21 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" @@ -231671,23 +231671,23 @@ module \lenexp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" wire width 176 output 3 \rexp_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $extend$libresoc.v:142935$6595 + cell $pos $extend$libresoc.v:142934$6595 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$7 - connect \Y $extend$libresoc.v:142935$6595_Y + connect \Y $extend$libresoc.v:142934$6595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $pos$libresoc.v:142935$6596 + cell $pos $pos$libresoc.v:142934$6596 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:142935$6595_Y - connect \Y $pos$libresoc.v:142935$6596_Y + connect \A $extend$libresoc.v:142934$6595_Y + connect \Y $pos$libresoc.v:142934$6596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sshl $sshl$libresoc.v:142932$6592 + cell $sshl $sshl$libresoc.v:142931$6592 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -231695,10 +231695,10 @@ module \lenexp parameter \Y_WIDTH 20 connect \A 5'00001 connect \B \len_i - connect \Y $sshl$libresoc.v:142932$6592_Y + connect \Y $sshl$libresoc.v:142931$6592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $sshl $sshl$libresoc.v:142934$6594 + cell $sshl $sshl$libresoc.v:142933$6594 parameter \A_SIGNED 0 parameter \A_WIDTH 17 parameter \B_SIGNED 0 @@ -231706,10 +231706,10 @@ module \lenexp parameter \Y_WIDTH 32 connect \A \binlen connect \B \addr_i - connect \Y $sshl$libresoc.v:142934$6594_Y + connect \Y $sshl$libresoc.v:142933$6594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sub $sub$libresoc.v:142933$6593 + cell $sub $sub$libresoc.v:142932$6593 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -231717,48 +231717,48 @@ module \lenexp parameter \Y_WIDTH 21 connect \A \$2 connect \B 1'1 - connect \Y $sub$libresoc.v:142933$6593_Y + connect \Y $sub$libresoc.v:142932$6593_Y end - connect \$2 $sshl$libresoc.v:142932$6592_Y - connect \$4 $sub$libresoc.v:142933$6593_Y - connect \$7 $sshl$libresoc.v:142934$6594_Y - connect \$6 $pos$libresoc.v:142935$6596_Y + connect \$2 $sshl$libresoc.v:142931$6592_Y + connect \$4 $sub$libresoc.v:142932$6593_Y + connect \$7 $sshl$libresoc.v:142933$6594_Y + connect \$6 $pos$libresoc.v:142934$6596_Y connect \$1 \$4 connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } connect \lexp_o \$6 connect \binlen \$4 [16:0] end -attribute \src "libresoc.v:142944.1-143002.10" +attribute \src "libresoc.v:142943.1-143001.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l" attribute \generator "nMigen" module \lod_l - attribute \src "libresoc.v:142945.7-142945.20" + attribute \src "libresoc.v:142944.7-142944.20" wire $0\initial[0:0] - attribute \src "libresoc.v:142990.3-142998.6" + attribute \src "libresoc.v:142989.3-142997.6" wire $0\q_int$next[0:0]$6607 - attribute \src "libresoc.v:142988.3-142989.27" + attribute \src "libresoc.v:142987.3-142988.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:142990.3-142998.6" + attribute \src "libresoc.v:142989.3-142997.6" wire $1\q_int$next[0:0]$6608 - attribute \src "libresoc.v:142967.7-142967.19" + attribute \src "libresoc.v:142966.7-142966.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:142980.17-142980.96" - wire $and$libresoc.v:142980$6597_Y - attribute \src "libresoc.v:142985.17-142985.96" - wire $and$libresoc.v:142985$6602_Y - attribute \src "libresoc.v:142982.18-142982.93" - wire $not$libresoc.v:142982$6599_Y - attribute \src "libresoc.v:142984.17-142984.92" - wire $not$libresoc.v:142984$6601_Y - attribute \src "libresoc.v:142987.17-142987.92" - wire $not$libresoc.v:142987$6604_Y - attribute \src "libresoc.v:142981.18-142981.98" - wire $or$libresoc.v:142981$6598_Y - attribute \src "libresoc.v:142983.18-142983.99" - wire $or$libresoc.v:142983$6600_Y - attribute \src "libresoc.v:142986.17-142986.97" - wire $or$libresoc.v:142986$6603_Y + attribute \src "libresoc.v:142979.17-142979.96" + wire $and$libresoc.v:142979$6597_Y + attribute \src "libresoc.v:142984.17-142984.96" + wire $and$libresoc.v:142984$6602_Y + attribute \src "libresoc.v:142981.18-142981.93" + wire $not$libresoc.v:142981$6599_Y + attribute \src "libresoc.v:142983.17-142983.92" + wire $not$libresoc.v:142983$6601_Y + attribute \src "libresoc.v:142986.17-142986.92" + wire $not$libresoc.v:142986$6604_Y + attribute \src "libresoc.v:142980.18-142980.98" + wire $or$libresoc.v:142980$6598_Y + attribute \src "libresoc.v:142982.18-142982.99" + wire $or$libresoc.v:142982$6600_Y + attribute \src "libresoc.v:142985.17-142985.97" + wire $or$libresoc.v:142985$6603_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -231779,7 +231779,7 @@ module \lod_l wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:142945.7-142945.15" + attribute \src "libresoc.v:142944.7-142944.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -231796,7 +231796,7 @@ module \lod_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:142980$6597 + cell $and $and$libresoc.v:142979$6597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231804,10 +231804,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:142980$6597_Y + connect \Y $and$libresoc.v:142979$6597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:142985$6602 + cell $and $and$libresoc.v:142984$6602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231815,34 +231815,34 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:142985$6602_Y + connect \Y $and$libresoc.v:142984$6602_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:142982$6599 + cell $not $not$libresoc.v:142981$6599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lod - connect \Y $not$libresoc.v:142982$6599_Y + connect \Y $not$libresoc.v:142981$6599_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:142984$6601 + cell $not $not$libresoc.v:142983$6601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:142984$6601_Y + connect \Y $not$libresoc.v:142983$6601_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:142987$6604 + cell $not $not$libresoc.v:142986$6604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:142987$6604_Y + connect \Y $not$libresoc.v:142986$6604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:142981$6598 + cell $or $or$libresoc.v:142980$6598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231850,10 +231850,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lod - connect \Y $or$libresoc.v:142981$6598_Y + connect \Y $or$libresoc.v:142980$6598_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:142983$6600 + cell $or $or$libresoc.v:142982$6600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231861,10 +231861,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_lod connect \B \q_int - connect \Y $or$libresoc.v:142983$6600_Y + connect \Y $or$libresoc.v:142982$6600_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:142986$6603 + cell $or $or$libresoc.v:142985$6603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231872,39 +231872,39 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lod - connect \Y $or$libresoc.v:142986$6603_Y + connect \Y $or$libresoc.v:142985$6603_Y end - attribute \src "libresoc.v:142945.7-142945.20" - process $proc$libresoc.v:142945$6609 + attribute \src "libresoc.v:142944.7-142944.20" + process $proc$libresoc.v:142944$6609 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:142967.7-142967.19" - process $proc$libresoc.v:142967$6610 + attribute \src "libresoc.v:142966.7-142966.19" + process $proc$libresoc.v:142966$6610 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:142988.3-142989.27" - process $proc$libresoc.v:142988$6605 + attribute \src "libresoc.v:142987.3-142988.27" + process $proc$libresoc.v:142987$6605 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:142990.3-142998.6" - process $proc$libresoc.v:142990$6606 + attribute \src "libresoc.v:142989.3-142997.6" + process $proc$libresoc.v:142989$6606 assign { } { } assign { } { } assign $0\q_int$next[0:0]$6607 $1\q_int$next[0:0]$6608 - attribute \src "libresoc.v:142991.5-142991.29" + attribute \src "libresoc.v:142990.5-142990.29" switch \initial - attribute \src "libresoc.v:142991.9-142991.17" + attribute \src "libresoc.v:142990.9-142990.17" case 1'1 case end @@ -231920,487 +231920,487 @@ module \lod_l sync always update \q_int$next $0\q_int$next[0:0]$6607 end - connect \$9 $and$libresoc.v:142980$6597_Y - connect \$11 $or$libresoc.v:142981$6598_Y - connect \$13 $not$libresoc.v:142982$6599_Y - connect \$15 $or$libresoc.v:142983$6600_Y - connect \$1 $not$libresoc.v:142984$6601_Y - connect \$3 $and$libresoc.v:142985$6602_Y - connect \$5 $or$libresoc.v:142986$6603_Y - connect \$7 $not$libresoc.v:142987$6604_Y + connect \$9 $and$libresoc.v:142979$6597_Y + connect \$11 $or$libresoc.v:142980$6598_Y + connect \$13 $not$libresoc.v:142981$6599_Y + connect \$15 $or$libresoc.v:142982$6600_Y + connect \$1 $not$libresoc.v:142983$6601_Y + connect \$3 $and$libresoc.v:142984$6602_Y + connect \$5 $or$libresoc.v:142985$6603_Y + connect \$7 $not$libresoc.v:142986$6604_Y connect \qlq_lod \$15 connect \qn_lod \$13 connect \q_lod \$11 end -attribute \src "libresoc.v:143006.1-144126.10" +attribute \src "libresoc.v:143005.1-144125.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0" attribute \generator "nMigen" module \logical0 - attribute \src "libresoc.v:143751.3-143752.24" + attribute \src "libresoc.v:143750.3-143751.24" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:143749.3-143750.44" + attribute \src "libresoc.v:143748.3-143749.44" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:144056.3-144064.6" + attribute \src "libresoc.v:144055.3-144063.6" wire $0\alu_l_r_alu$next[0:0]$6811 - attribute \src "libresoc.v:143673.3-143674.39" + attribute \src "libresoc.v:143672.3-143673.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6740 - attribute \src "libresoc.v:143723.3-143724.83" + attribute \src "libresoc.v:143722.3-143723.83" wire width 4 $0\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire width 14 $0\alu_logical0_logical_op__fn_unit$next[13:0]$6741 - attribute \src "libresoc.v:143693.3-143694.81" + attribute \src "libresoc.v:143692.3-143693.81" wire width 14 $0\alu_logical0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6742 - attribute \src "libresoc.v:143695.3-143696.95" + attribute \src "libresoc.v:143694.3-143695.95" wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6743 - attribute \src "libresoc.v:143697.3-143698.91" + attribute \src "libresoc.v:143696.3-143697.91" wire $0\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6744 - attribute \src "libresoc.v:143711.3-143712.89" + attribute \src "libresoc.v:143710.3-143711.89" wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6745 - attribute \src "libresoc.v:143725.3-143726.75" + attribute \src "libresoc.v:143724.3-143725.75" wire width 32 $0\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6746 - attribute \src "libresoc.v:143691.3-143692.85" + attribute \src "libresoc.v:143690.3-143691.85" wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6747 - attribute \src "libresoc.v:143707.3-143708.85" + attribute \src "libresoc.v:143706.3-143707.85" wire $0\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6748 - attribute \src "libresoc.v:143713.3-143714.87" + attribute \src "libresoc.v:143712.3-143713.87" wire $0\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6749 - attribute \src "libresoc.v:143719.3-143720.83" + attribute \src "libresoc.v:143718.3-143719.83" wire $0\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6750 - attribute \src "libresoc.v:143721.3-143722.85" + attribute \src "libresoc.v:143720.3-143721.85" wire $0\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6751 - attribute \src "libresoc.v:143703.3-143704.79" + attribute \src "libresoc.v:143702.3-143703.79" wire $0\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6752 - attribute \src "libresoc.v:143705.3-143706.79" + attribute \src "libresoc.v:143704.3-143705.79" wire $0\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6753 - attribute \src "libresoc.v:143717.3-143718.91" + attribute \src "libresoc.v:143716.3-143717.91" wire $0\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6754 - attribute \src "libresoc.v:143701.3-143702.79" + attribute \src "libresoc.v:143700.3-143701.79" wire $0\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6755 - attribute \src "libresoc.v:143699.3-143700.79" + attribute \src "libresoc.v:143698.3-143699.79" wire $0\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6756 - attribute \src "libresoc.v:143715.3-143716.85" + attribute \src "libresoc.v:143714.3-143715.85" wire $0\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6757 - attribute \src "libresoc.v:143709.3-143710.79" + attribute \src "libresoc.v:143708.3-143709.79" wire $0\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:144047.3-144055.6" + attribute \src "libresoc.v:144046.3-144054.6" wire $0\alui_l_r_alui$next[0:0]$6808 - attribute \src "libresoc.v:143675.3-143676.43" + attribute \src "libresoc.v:143674.3-143675.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:143973.3-143994.6" + attribute \src "libresoc.v:143972.3-143993.6" wire width 64 $0\data_r0__o$next[63:0]$6783 - attribute \src "libresoc.v:143687.3-143688.37" + attribute \src "libresoc.v:143686.3-143687.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:143973.3-143994.6" + attribute \src "libresoc.v:143972.3-143993.6" wire $0\data_r0__o_ok$next[0:0]$6784 - attribute \src "libresoc.v:143689.3-143690.43" + attribute \src "libresoc.v:143688.3-143689.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:143995.3-144016.6" + attribute \src "libresoc.v:143994.3-144015.6" wire width 4 $0\data_r1__cr_a$next[3:0]$6791 - attribute \src "libresoc.v:143683.3-143684.43" + attribute \src "libresoc.v:143682.3-143683.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:143995.3-144016.6" + attribute \src "libresoc.v:143994.3-144015.6" wire $0\data_r1__cr_a_ok$next[0:0]$6792 - attribute \src "libresoc.v:143685.3-143686.49" + attribute \src "libresoc.v:143684.3-143685.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:144065.3-144074.6" + attribute \src "libresoc.v:144064.3-144073.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:144075.3-144084.6" + attribute \src "libresoc.v:144074.3-144083.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:143007.7-143007.20" + attribute \src "libresoc.v:143006.7-143006.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143889.3-143897.6" + attribute \src "libresoc.v:143888.3-143896.6" wire $0\opc_l_r_opc$next[0:0]$6725 - attribute \src "libresoc.v:143735.3-143736.39" + attribute \src "libresoc.v:143734.3-143735.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:143880.3-143888.6" + attribute \src "libresoc.v:143879.3-143887.6" wire $0\opc_l_s_opc$next[0:0]$6722 - attribute \src "libresoc.v:143737.3-143738.39" + attribute \src "libresoc.v:143736.3-143737.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:144085.3-144093.6" + attribute \src "libresoc.v:144084.3-144092.6" wire width 2 $0\prev_wr_go$next[1:0]$6816 - attribute \src "libresoc.v:143747.3-143748.37" + attribute \src "libresoc.v:143746.3-143747.37" wire width 2 $0\prev_wr_go[1:0] - attribute \src "libresoc.v:143834.3-143843.6" + attribute \src "libresoc.v:143833.3-143842.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:143925.3-143933.6" + attribute \src "libresoc.v:143924.3-143932.6" wire width 2 $0\req_l_r_req$next[1:0]$6737 - attribute \src "libresoc.v:143727.3-143728.39" + attribute \src "libresoc.v:143726.3-143727.39" wire width 2 $0\req_l_r_req[1:0] - attribute \src "libresoc.v:143916.3-143924.6" + attribute \src "libresoc.v:143915.3-143923.6" wire width 2 $0\req_l_s_req$next[1:0]$6734 - attribute \src "libresoc.v:143729.3-143730.39" + attribute \src "libresoc.v:143728.3-143729.39" wire width 2 $0\req_l_s_req[1:0] - attribute \src "libresoc.v:143853.3-143861.6" + attribute \src "libresoc.v:143852.3-143860.6" wire $0\rok_l_r_rdok$next[0:0]$6713 - attribute \src "libresoc.v:143743.3-143744.41" + attribute \src "libresoc.v:143742.3-143743.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:143844.3-143852.6" + attribute \src "libresoc.v:143843.3-143851.6" wire $0\rok_l_s_rdok$next[0:0]$6710 - attribute \src "libresoc.v:143745.3-143746.41" + attribute \src "libresoc.v:143744.3-143745.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:143871.3-143879.6" + attribute \src "libresoc.v:143870.3-143878.6" wire $0\rst_l_r_rst$next[0:0]$6719 - attribute \src "libresoc.v:143739.3-143740.39" + attribute \src "libresoc.v:143738.3-143739.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:143862.3-143870.6" + attribute \src "libresoc.v:143861.3-143869.6" wire $0\rst_l_s_rst$next[0:0]$6716 - attribute \src "libresoc.v:143741.3-143742.39" + attribute \src "libresoc.v:143740.3-143741.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:143907.3-143915.6" + attribute \src "libresoc.v:143906.3-143914.6" wire width 3 $0\src_l_r_src$next[2:0]$6731 - attribute \src "libresoc.v:143731.3-143732.39" + attribute \src "libresoc.v:143730.3-143731.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:143898.3-143906.6" + attribute \src "libresoc.v:143897.3-143905.6" wire width 3 $0\src_l_s_src$next[2:0]$6728 - attribute \src "libresoc.v:143733.3-143734.39" + attribute \src "libresoc.v:143732.3-143733.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:144017.3-144026.6" + attribute \src "libresoc.v:144016.3-144025.6" wire width 64 $0\src_r0$next[63:0]$6799 - attribute \src "libresoc.v:143681.3-143682.29" + attribute \src "libresoc.v:143680.3-143681.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:144027.3-144036.6" + attribute \src "libresoc.v:144026.3-144035.6" wire width 64 $0\src_r1$next[63:0]$6802 - attribute \src "libresoc.v:143679.3-143680.29" + attribute \src "libresoc.v:143678.3-143679.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:144037.3-144046.6" + attribute \src "libresoc.v:144036.3-144045.6" wire $0\src_r2$next[0:0]$6805 - attribute \src "libresoc.v:143677.3-143678.29" + attribute \src "libresoc.v:143676.3-143677.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:143125.7-143125.24" + attribute \src "libresoc.v:143124.7-143124.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:143135.7-143135.26" + attribute \src "libresoc.v:143134.7-143134.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:144056.3-144064.6" + attribute \src "libresoc.v:144055.3-144063.6" wire $1\alu_l_r_alu$next[0:0]$6812 - attribute \src "libresoc.v:143143.7-143143.25" + attribute \src "libresoc.v:143142.7-143142.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6758 - attribute \src "libresoc.v:143151.13-143151.53" + attribute \src "libresoc.v:143150.13-143150.53" wire width 4 $1\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire width 14 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 - attribute \src "libresoc.v:143170.14-143170.57" + attribute \src "libresoc.v:143169.14-143169.57" wire width 14 $1\alu_logical0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 - attribute \src "libresoc.v:143174.14-143174.76" + attribute \src "libresoc.v:143173.14-143173.76" wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 - attribute \src "libresoc.v:143178.7-143178.51" + attribute \src "libresoc.v:143177.7-143177.51" wire $1\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 - attribute \src "libresoc.v:143186.13-143186.56" + attribute \src "libresoc.v:143185.13-143185.56" wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6763 - attribute \src "libresoc.v:143190.14-143190.51" + attribute \src "libresoc.v:143189.14-143189.51" wire width 32 $1\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 - attribute \src "libresoc.v:143269.13-143269.55" + attribute \src "libresoc.v:143268.13-143268.55" wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 - attribute \src "libresoc.v:143273.7-143273.48" + attribute \src "libresoc.v:143272.7-143272.48" wire $1\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 - attribute \src "libresoc.v:143277.7-143277.49" + attribute \src "libresoc.v:143276.7-143276.49" wire $1\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 - attribute \src "libresoc.v:143281.7-143281.47" + attribute \src "libresoc.v:143280.7-143280.47" wire $1\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 - attribute \src "libresoc.v:143285.7-143285.48" + attribute \src "libresoc.v:143284.7-143284.48" wire $1\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 - attribute \src "libresoc.v:143289.7-143289.45" + attribute \src "libresoc.v:143288.7-143288.45" wire $1\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 - attribute \src "libresoc.v:143293.7-143293.45" + attribute \src "libresoc.v:143292.7-143292.45" wire $1\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 - attribute \src "libresoc.v:143297.7-143297.51" + attribute \src "libresoc.v:143296.7-143296.51" wire $1\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 - attribute \src "libresoc.v:143301.7-143301.45" + attribute \src "libresoc.v:143300.7-143300.45" wire $1\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 - attribute \src "libresoc.v:143305.7-143305.45" + attribute \src "libresoc.v:143304.7-143304.45" wire $1\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 - attribute \src "libresoc.v:143309.7-143309.48" + attribute \src "libresoc.v:143308.7-143308.48" wire $1\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 - attribute \src "libresoc.v:143313.7-143313.45" + attribute \src "libresoc.v:143312.7-143312.45" wire $1\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:144047.3-144055.6" + attribute \src "libresoc.v:144046.3-144054.6" wire $1\alui_l_r_alui$next[0:0]$6809 - attribute \src "libresoc.v:143339.7-143339.27" + attribute \src "libresoc.v:143338.7-143338.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:143973.3-143994.6" + attribute \src "libresoc.v:143972.3-143993.6" wire width 64 $1\data_r0__o$next[63:0]$6785 - attribute \src "libresoc.v:143373.14-143373.47" + attribute \src "libresoc.v:143372.14-143372.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:143973.3-143994.6" + attribute \src "libresoc.v:143972.3-143993.6" wire $1\data_r0__o_ok$next[0:0]$6786 - attribute \src "libresoc.v:143377.7-143377.27" + attribute \src "libresoc.v:143376.7-143376.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:143995.3-144016.6" + attribute \src "libresoc.v:143994.3-144015.6" wire width 4 $1\data_r1__cr_a$next[3:0]$6793 - attribute \src "libresoc.v:143381.13-143381.33" + attribute \src "libresoc.v:143380.13-143380.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:143995.3-144016.6" + attribute \src "libresoc.v:143994.3-144015.6" wire $1\data_r1__cr_a_ok$next[0:0]$6794 - attribute \src "libresoc.v:143385.7-143385.30" + attribute \src "libresoc.v:143384.7-143384.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:144065.3-144074.6" + attribute \src "libresoc.v:144064.3-144073.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:144075.3-144084.6" + attribute \src "libresoc.v:144074.3-144083.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:143889.3-143897.6" + attribute \src "libresoc.v:143888.3-143896.6" wire $1\opc_l_r_opc$next[0:0]$6726 - attribute \src "libresoc.v:143399.7-143399.25" + attribute \src "libresoc.v:143398.7-143398.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:143880.3-143888.6" + attribute \src "libresoc.v:143879.3-143887.6" wire $1\opc_l_s_opc$next[0:0]$6723 - attribute \src "libresoc.v:143403.7-143403.25" + attribute \src "libresoc.v:143402.7-143402.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:144085.3-144093.6" + attribute \src "libresoc.v:144084.3-144092.6" wire width 2 $1\prev_wr_go$next[1:0]$6817 - attribute \src "libresoc.v:143537.13-143537.30" + attribute \src "libresoc.v:143536.13-143536.30" wire width 2 $1\prev_wr_go[1:0] - attribute \src "libresoc.v:143834.3-143843.6" + attribute \src "libresoc.v:143833.3-143842.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:143925.3-143933.6" + attribute \src "libresoc.v:143924.3-143932.6" wire width 2 $1\req_l_r_req$next[1:0]$6738 - attribute \src "libresoc.v:143545.13-143545.31" + attribute \src "libresoc.v:143544.13-143544.31" wire width 2 $1\req_l_r_req[1:0] - attribute \src "libresoc.v:143916.3-143924.6" + attribute \src "libresoc.v:143915.3-143923.6" wire width 2 $1\req_l_s_req$next[1:0]$6735 - attribute \src "libresoc.v:143549.13-143549.31" + attribute \src "libresoc.v:143548.13-143548.31" wire width 2 $1\req_l_s_req[1:0] - attribute \src "libresoc.v:143853.3-143861.6" + attribute \src "libresoc.v:143852.3-143860.6" wire $1\rok_l_r_rdok$next[0:0]$6714 - attribute \src "libresoc.v:143561.7-143561.26" + attribute \src "libresoc.v:143560.7-143560.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:143844.3-143852.6" + attribute \src "libresoc.v:143843.3-143851.6" wire $1\rok_l_s_rdok$next[0:0]$6711 - attribute \src "libresoc.v:143565.7-143565.26" + attribute \src "libresoc.v:143564.7-143564.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:143871.3-143879.6" + attribute \src "libresoc.v:143870.3-143878.6" wire $1\rst_l_r_rst$next[0:0]$6720 - attribute \src "libresoc.v:143569.7-143569.25" + attribute \src "libresoc.v:143568.7-143568.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:143862.3-143870.6" + attribute \src "libresoc.v:143861.3-143869.6" wire $1\rst_l_s_rst$next[0:0]$6717 - attribute \src "libresoc.v:143573.7-143573.25" + attribute \src "libresoc.v:143572.7-143572.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:143907.3-143915.6" + attribute \src "libresoc.v:143906.3-143914.6" wire width 3 $1\src_l_r_src$next[2:0]$6732 - attribute \src "libresoc.v:143587.13-143587.31" + attribute \src "libresoc.v:143586.13-143586.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:143898.3-143906.6" + attribute \src "libresoc.v:143897.3-143905.6" wire width 3 $1\src_l_s_src$next[2:0]$6729 - attribute \src "libresoc.v:143591.13-143591.31" + attribute \src "libresoc.v:143590.13-143590.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:144017.3-144026.6" + attribute \src "libresoc.v:144016.3-144025.6" wire width 64 $1\src_r0$next[63:0]$6800 - attribute \src "libresoc.v:143599.14-143599.43" + attribute \src "libresoc.v:143598.14-143598.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:144027.3-144036.6" + attribute \src "libresoc.v:144026.3-144035.6" wire width 64 $1\src_r1$next[63:0]$6803 - attribute \src "libresoc.v:143603.14-143603.43" + attribute \src "libresoc.v:143602.14-143602.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:144037.3-144046.6" + attribute \src "libresoc.v:144036.3-144045.6" wire $1\src_r2$next[0:0]$6806 - attribute \src "libresoc.v:143607.7-143607.20" + attribute \src "libresoc.v:143606.7-143606.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 - attribute \src "libresoc.v:143934.3-143972.6" + attribute \src "libresoc.v:143933.3-143971.6" wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 - attribute \src "libresoc.v:143973.3-143994.6" + attribute \src "libresoc.v:143972.3-143993.6" wire width 64 $2\data_r0__o$next[63:0]$6787 - attribute \src "libresoc.v:143973.3-143994.6" + attribute \src "libresoc.v:143972.3-143993.6" wire $2\data_r0__o_ok$next[0:0]$6788 - attribute \src "libresoc.v:143995.3-144016.6" + attribute \src "libresoc.v:143994.3-144015.6" wire width 4 $2\data_r1__cr_a$next[3:0]$6795 - attribute \src "libresoc.v:143995.3-144016.6" + attribute \src "libresoc.v:143994.3-144015.6" wire $2\data_r1__cr_a_ok$next[0:0]$6796 - attribute \src "libresoc.v:143973.3-143994.6" + attribute \src "libresoc.v:143972.3-143993.6" wire $3\data_r0__o_ok$next[0:0]$6789 - attribute \src "libresoc.v:143995.3-144016.6" + attribute \src "libresoc.v:143994.3-144015.6" wire $3\data_r1__cr_a_ok$next[0:0]$6797 - attribute \src "libresoc.v:143616.17-143616.109" - wire $and$libresoc.v:143616$6611_Y - attribute \src "libresoc.v:143617.18-143617.130" - wire width 3 $and$libresoc.v:143617$6612_Y - attribute \src "libresoc.v:143619.19-143619.114" - wire width 3 $and$libresoc.v:143619$6614_Y + attribute \src "libresoc.v:143615.17-143615.109" + wire $and$libresoc.v:143615$6611_Y + attribute \src "libresoc.v:143616.18-143616.130" + wire width 3 $and$libresoc.v:143616$6612_Y + attribute \src "libresoc.v:143618.19-143618.114" + wire width 3 $and$libresoc.v:143618$6614_Y + attribute \src "libresoc.v:143619.19-143619.125" + wire $and$libresoc.v:143619$6615_Y attribute \src "libresoc.v:143620.19-143620.125" - wire $and$libresoc.v:143620$6615_Y - attribute \src "libresoc.v:143621.19-143621.125" - wire $and$libresoc.v:143621$6616_Y - attribute \src "libresoc.v:143622.19-143622.133" - wire width 2 $and$libresoc.v:143622$6617_Y - attribute \src "libresoc.v:143623.19-143623.121" - wire width 2 $and$libresoc.v:143623$6618_Y + wire $and$libresoc.v:143620$6616_Y + attribute \src "libresoc.v:143621.19-143621.133" + wire width 2 $and$libresoc.v:143621$6617_Y + attribute \src "libresoc.v:143622.19-143622.121" + wire width 2 $and$libresoc.v:143622$6618_Y + attribute \src "libresoc.v:143623.19-143623.127" + wire $and$libresoc.v:143623$6619_Y attribute \src "libresoc.v:143624.19-143624.127" - wire $and$libresoc.v:143624$6619_Y - attribute \src "libresoc.v:143625.19-143625.127" - wire $and$libresoc.v:143625$6620_Y - attribute \src "libresoc.v:143627.18-143627.98" - wire $and$libresoc.v:143627$6622_Y - attribute \src "libresoc.v:143629.18-143629.100" - wire $and$libresoc.v:143629$6624_Y - attribute \src "libresoc.v:143630.17-143630.123" - wire $and$libresoc.v:143630$6625_Y - attribute \src "libresoc.v:143631.18-143631.138" - wire width 2 $and$libresoc.v:143631$6626_Y - attribute \src "libresoc.v:143633.18-143633.119" - wire width 2 $and$libresoc.v:143633$6628_Y - attribute \src "libresoc.v:143636.18-143636.116" - wire $and$libresoc.v:143636$6631_Y - attribute \src "libresoc.v:143641.18-143641.113" - wire $and$libresoc.v:143641$6636_Y - attribute \src "libresoc.v:143642.18-143642.125" - wire width 2 $and$libresoc.v:143642$6637_Y - attribute \src "libresoc.v:143644.18-143644.112" - wire $and$libresoc.v:143644$6639_Y + wire $and$libresoc.v:143624$6620_Y + attribute \src "libresoc.v:143626.18-143626.98" + wire $and$libresoc.v:143626$6622_Y + attribute \src "libresoc.v:143628.18-143628.100" + wire $and$libresoc.v:143628$6624_Y + attribute \src "libresoc.v:143629.17-143629.123" + wire $and$libresoc.v:143629$6625_Y + attribute \src "libresoc.v:143630.18-143630.138" + wire width 2 $and$libresoc.v:143630$6626_Y + attribute \src "libresoc.v:143632.18-143632.119" + wire width 2 $and$libresoc.v:143632$6628_Y + attribute \src "libresoc.v:143635.18-143635.116" + wire $and$libresoc.v:143635$6631_Y + attribute \src "libresoc.v:143640.18-143640.113" + wire $and$libresoc.v:143640$6636_Y + attribute \src "libresoc.v:143641.18-143641.125" + wire width 2 $and$libresoc.v:143641$6637_Y + attribute \src "libresoc.v:143643.18-143643.112" + wire $and$libresoc.v:143643$6639_Y + attribute \src "libresoc.v:143646.18-143646.130" + wire $and$libresoc.v:143646$6642_Y attribute \src "libresoc.v:143647.18-143647.130" - wire $and$libresoc.v:143647$6642_Y - attribute \src "libresoc.v:143648.18-143648.130" - wire $and$libresoc.v:143648$6643_Y - attribute \src "libresoc.v:143649.18-143649.117" - wire $and$libresoc.v:143649$6644_Y - attribute \src "libresoc.v:143654.18-143654.134" - wire $and$libresoc.v:143654$6649_Y - attribute \src "libresoc.v:143655.18-143655.124" - wire width 2 $and$libresoc.v:143655$6650_Y - attribute \src "libresoc.v:143658.18-143658.116" - wire $and$libresoc.v:143658$6653_Y - attribute \src "libresoc.v:143659.18-143659.119" - wire $and$libresoc.v:143659$6654_Y - attribute \src "libresoc.v:143668.18-143668.138" - wire $and$libresoc.v:143668$6663_Y - attribute \src "libresoc.v:143669.18-143669.136" - wire $and$libresoc.v:143669$6664_Y - attribute \src "libresoc.v:143670.18-143670.149" - wire width 3 $and$libresoc.v:143670$6665_Y - attribute \src "libresoc.v:143643.18-143643.113" - wire $eq$libresoc.v:143643$6638_Y - attribute \src "libresoc.v:143645.18-143645.119" - wire $eq$libresoc.v:143645$6640_Y - attribute \src "libresoc.v:143618.19-143618.115" - wire width 3 $not$libresoc.v:143618$6613_Y - attribute \src "libresoc.v:143626.18-143626.97" - wire $not$libresoc.v:143626$6621_Y - attribute \src "libresoc.v:143628.18-143628.99" - wire $not$libresoc.v:143628$6623_Y - attribute \src "libresoc.v:143632.18-143632.113" - wire width 2 $not$libresoc.v:143632$6627_Y - attribute \src "libresoc.v:143635.18-143635.106" - wire $not$libresoc.v:143635$6630_Y - attribute \src "libresoc.v:143640.18-143640.124" - wire $not$libresoc.v:143640$6635_Y - attribute \src "libresoc.v:143646.17-143646.113" - wire width 3 $not$libresoc.v:143646$6641_Y - attribute \src "libresoc.v:143671.18-143671.133" - wire $not$libresoc.v:143671$6666_Y - attribute \src "libresoc.v:143672.18-143672.139" - wire $not$libresoc.v:143672$6667_Y - attribute \src "libresoc.v:143639.18-143639.112" - wire $or$libresoc.v:143639$6634_Y - attribute \src "libresoc.v:143650.18-143650.122" - wire $or$libresoc.v:143650$6645_Y - attribute \src "libresoc.v:143651.18-143651.124" - wire $or$libresoc.v:143651$6646_Y - attribute \src "libresoc.v:143652.18-143652.142" - wire width 2 $or$libresoc.v:143652$6647_Y - attribute \src "libresoc.v:143653.18-143653.155" - wire width 3 $or$libresoc.v:143653$6648_Y - attribute \src "libresoc.v:143656.18-143656.120" - wire width 2 $or$libresoc.v:143656$6651_Y - attribute \src "libresoc.v:143657.17-143657.117" - wire width 3 $or$libresoc.v:143657$6652_Y - attribute \src "libresoc.v:143663.17-143663.104" - wire $reduce_and$libresoc.v:143663$6658_Y + wire $and$libresoc.v:143647$6643_Y + attribute \src "libresoc.v:143648.18-143648.117" + wire $and$libresoc.v:143648$6644_Y + attribute \src "libresoc.v:143653.18-143653.134" + wire $and$libresoc.v:143653$6649_Y + attribute \src "libresoc.v:143654.18-143654.124" + wire width 2 $and$libresoc.v:143654$6650_Y + attribute \src "libresoc.v:143657.18-143657.116" + wire $and$libresoc.v:143657$6653_Y + attribute \src "libresoc.v:143658.18-143658.119" + wire $and$libresoc.v:143658$6654_Y + attribute \src "libresoc.v:143667.18-143667.138" + wire $and$libresoc.v:143667$6663_Y + attribute \src "libresoc.v:143668.18-143668.136" + wire $and$libresoc.v:143668$6664_Y + attribute \src "libresoc.v:143669.18-143669.149" + wire width 3 $and$libresoc.v:143669$6665_Y + attribute \src "libresoc.v:143642.18-143642.113" + wire $eq$libresoc.v:143642$6638_Y + attribute \src "libresoc.v:143644.18-143644.119" + wire $eq$libresoc.v:143644$6640_Y + attribute \src "libresoc.v:143617.19-143617.115" + wire width 3 $not$libresoc.v:143617$6613_Y + attribute \src "libresoc.v:143625.18-143625.97" + wire $not$libresoc.v:143625$6621_Y + attribute \src "libresoc.v:143627.18-143627.99" + wire $not$libresoc.v:143627$6623_Y + attribute \src "libresoc.v:143631.18-143631.113" + wire width 2 $not$libresoc.v:143631$6627_Y attribute \src "libresoc.v:143634.18-143634.106" - wire $reduce_or$libresoc.v:143634$6629_Y - attribute \src "libresoc.v:143637.18-143637.113" - wire $reduce_or$libresoc.v:143637$6632_Y + wire $not$libresoc.v:143634$6630_Y + attribute \src "libresoc.v:143639.18-143639.124" + wire $not$libresoc.v:143639$6635_Y + attribute \src "libresoc.v:143645.17-143645.113" + wire width 3 $not$libresoc.v:143645$6641_Y + attribute \src "libresoc.v:143670.18-143670.133" + wire $not$libresoc.v:143670$6666_Y + attribute \src "libresoc.v:143671.18-143671.139" + wire $not$libresoc.v:143671$6667_Y attribute \src "libresoc.v:143638.18-143638.112" - wire $reduce_or$libresoc.v:143638$6633_Y - attribute \src "libresoc.v:143660.18-143660.162" - wire $ternary$libresoc.v:143660$6655_Y - attribute \src "libresoc.v:143661.18-143661.163" - wire width 64 $ternary$libresoc.v:143661$6656_Y - attribute \src "libresoc.v:143662.18-143662.168" - wire $ternary$libresoc.v:143662$6657_Y - attribute \src "libresoc.v:143664.18-143664.188" - wire width 64 $ternary$libresoc.v:143664$6659_Y - attribute \src "libresoc.v:143665.18-143665.115" - wire width 64 $ternary$libresoc.v:143665$6660_Y - attribute \src "libresoc.v:143666.18-143666.125" - wire width 64 $ternary$libresoc.v:143666$6661_Y - attribute \src "libresoc.v:143667.18-143667.118" - wire $ternary$libresoc.v:143667$6662_Y + wire $or$libresoc.v:143638$6634_Y + attribute \src "libresoc.v:143649.18-143649.122" + wire $or$libresoc.v:143649$6645_Y + attribute \src "libresoc.v:143650.18-143650.124" + wire $or$libresoc.v:143650$6646_Y + attribute \src "libresoc.v:143651.18-143651.142" + wire width 2 $or$libresoc.v:143651$6647_Y + attribute \src "libresoc.v:143652.18-143652.155" + wire width 3 $or$libresoc.v:143652$6648_Y + attribute \src "libresoc.v:143655.18-143655.120" + wire width 2 $or$libresoc.v:143655$6651_Y + attribute \src "libresoc.v:143656.17-143656.117" + wire width 3 $or$libresoc.v:143656$6652_Y + attribute \src "libresoc.v:143662.17-143662.104" + wire $reduce_and$libresoc.v:143662$6658_Y + attribute \src "libresoc.v:143633.18-143633.106" + wire $reduce_or$libresoc.v:143633$6629_Y + attribute \src "libresoc.v:143636.18-143636.113" + wire $reduce_or$libresoc.v:143636$6632_Y + attribute \src "libresoc.v:143637.18-143637.112" + wire $reduce_or$libresoc.v:143637$6633_Y + attribute \src "libresoc.v:143659.18-143659.162" + wire $ternary$libresoc.v:143659$6655_Y + attribute \src "libresoc.v:143660.18-143660.163" + wire width 64 $ternary$libresoc.v:143660$6656_Y + attribute \src "libresoc.v:143661.18-143661.168" + wire $ternary$libresoc.v:143661$6657_Y + attribute \src "libresoc.v:143663.18-143663.188" + wire width 64 $ternary$libresoc.v:143663$6659_Y + attribute \src "libresoc.v:143664.18-143664.115" + wire width 64 $ternary$libresoc.v:143664$6660_Y + attribute \src "libresoc.v:143665.18-143665.125" + wire width 64 $ternary$libresoc.v:143665$6661_Y + attribute \src "libresoc.v:143666.18-143666.118" + wire $ternary$libresoc.v:143666$6662_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -232785,7 +232785,7 @@ module \logical0 wire width 64 output 31 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 33 \dest2_o - attribute \src "libresoc.v:143007.7-143007.15" + attribute \src "libresoc.v:143006.7-143006.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 28 \o_ok @@ -233010,7 +233010,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:143616$6611 + cell $and $and$libresoc.v:143615$6611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233018,10 +233018,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:143616$6611_Y + connect \Y $and$libresoc.v:143615$6611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:143617$6612 + cell $and $and$libresoc.v:143616$6612 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -233029,10 +233029,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$93 connect \B { 1'1 \$97 \$95 } - connect \Y $and$libresoc.v:143617$6612_Y + connect \Y $and$libresoc.v:143616$6612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:143619$6614 + cell $and $and$libresoc.v:143618$6614 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -233040,10 +233040,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$99 connect \B \$101 - connect \Y $and$libresoc.v:143619$6614_Y + connect \Y $and$libresoc.v:143618$6614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:143620$6615 + cell $and $and$libresoc.v:143619$6615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233051,10 +233051,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:143620$6615_Y + connect \Y $and$libresoc.v:143619$6615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:143621$6616 + cell $and $and$libresoc.v:143620$6616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233062,10 +233062,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:143621$6616_Y + connect \Y $and$libresoc.v:143620$6616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:143622$6617 + cell $and $and$libresoc.v:143621$6617 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233073,10 +233073,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B { \$105 \$107 } - connect \Y $and$libresoc.v:143622$6617_Y + connect \Y $and$libresoc.v:143621$6617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:143623$6618 + cell $and $and$libresoc.v:143622$6618 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233084,10 +233084,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \$109 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:143623$6618_Y + connect \Y $and$libresoc.v:143622$6618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:143624$6619 + cell $and $and$libresoc.v:143623$6619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233095,10 +233095,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:143624$6619_Y + connect \Y $and$libresoc.v:143623$6619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:143625$6620 + cell $and $and$libresoc.v:143624$6620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233106,10 +233106,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:143625$6620_Y + connect \Y $and$libresoc.v:143624$6620_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:143627$6622 + cell $and $and$libresoc.v:143626$6622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233117,10 +233117,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$11 - connect \Y $and$libresoc.v:143627$6622_Y + connect \Y $and$libresoc.v:143626$6622_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:143629$6624 + cell $and $and$libresoc.v:143628$6624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233128,10 +233128,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$15 - connect \Y $and$libresoc.v:143629$6624_Y + connect \Y $and$libresoc.v:143628$6624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:143630$6625 + cell $and $and$libresoc.v:143629$6625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233139,10 +233139,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:143630$6625_Y + connect \Y $and$libresoc.v:143629$6625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:143631$6626 + cell $and $and$libresoc.v:143630$6626 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233150,10 +233150,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:143631$6626_Y + connect \Y $and$libresoc.v:143630$6626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:143633$6628 + cell $and $and$libresoc.v:143632$6628 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233161,10 +233161,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__rel_o connect \B \$23 - connect \Y $and$libresoc.v:143633$6628_Y + connect \Y $and$libresoc.v:143632$6628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:143636$6631 + cell $and $and$libresoc.v:143635$6631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233172,10 +233172,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$21 - connect \Y $and$libresoc.v:143636$6631_Y + connect \Y $and$libresoc.v:143635$6631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:143641$6636 + cell $and $and$libresoc.v:143640$6636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233183,10 +233183,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$37 - connect \Y $and$libresoc.v:143641$6636_Y + connect \Y $and$libresoc.v:143640$6636_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:143642$6637 + cell $and $and$libresoc.v:143641$6637 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233194,10 +233194,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:143642$6637_Y + connect \Y $and$libresoc.v:143641$6637_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:143644$6639 + cell $and $and$libresoc.v:143643$6639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233205,10 +233205,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$43 - connect \Y $and$libresoc.v:143644$6639_Y + connect \Y $and$libresoc.v:143643$6639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:143647$6642 + cell $and $and$libresoc.v:143646$6642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233216,10 +233216,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$47 connect \B \alu_logical0_n_ready_i - connect \Y $and$libresoc.v:143647$6642_Y + connect \Y $and$libresoc.v:143646$6642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:143648$6643 + cell $and $and$libresoc.v:143647$6643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233227,10 +233227,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_logical0_n_valid_o - connect \Y $and$libresoc.v:143648$6643_Y + connect \Y $and$libresoc.v:143647$6643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:143649$6644 + cell $and $and$libresoc.v:143648$6644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233238,10 +233238,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \cu_busy_o - connect \Y $and$libresoc.v:143649$6644_Y + connect \Y $and$libresoc.v:143648$6644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:143654$6649 + cell $and $and$libresoc.v:143653$6649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233249,10 +233249,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:143654$6649_Y + connect \Y $and$libresoc.v:143653$6649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:143655$6650 + cell $and $and$libresoc.v:143654$6650 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233260,10 +233260,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:143655$6650_Y + connect \Y $and$libresoc.v:143654$6650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:143658$6653 + cell $and $and$libresoc.v:143657$6653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233271,10 +233271,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:143658$6653_Y + connect \Y $and$libresoc.v:143657$6653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:143659$6654 + cell $and $and$libresoc.v:143658$6654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233282,10 +233282,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:143659$6654_Y + connect \Y $and$libresoc.v:143658$6654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:143668$6663 + cell $and $and$libresoc.v:143667$6663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233293,10 +233293,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:143668$6663_Y + connect \Y $and$libresoc.v:143667$6663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:143669$6664 + cell $and $and$libresoc.v:143668$6664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233304,10 +233304,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:143669$6664_Y + connect \Y $and$libresoc.v:143668$6664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:143670$6665 + cell $and $and$libresoc.v:143669$6665 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -233315,10 +233315,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:143670$6665_Y + connect \Y $and$libresoc.v:143669$6665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:143643$6638 + cell $eq $eq$libresoc.v:143642$6638 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233326,10 +233326,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$41 connect \B 1'0 - connect \Y $eq$libresoc.v:143643$6638_Y + connect \Y $eq$libresoc.v:143642$6638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:143645$6640 + cell $eq $eq$libresoc.v:143644$6640 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233337,82 +233337,82 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:143645$6640_Y + connect \Y $eq$libresoc.v:143644$6640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:143618$6613 + cell $not $not$libresoc.v:143617$6613 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:143618$6613_Y + connect \Y $not$libresoc.v:143617$6613_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:143626$6621 + cell $not $not$libresoc.v:143625$6621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:143626$6621_Y + connect \Y $not$libresoc.v:143625$6621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:143628$6623 + cell $not $not$libresoc.v:143627$6623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:143628$6623_Y + connect \Y $not$libresoc.v:143627$6623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:143632$6627 + cell $not $not$libresoc.v:143631$6627 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:143632$6627_Y + connect \Y $not$libresoc.v:143631$6627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:143635$6630 + cell $not $not$libresoc.v:143634$6630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 - connect \Y $not$libresoc.v:143635$6630_Y + connect \Y $not$libresoc.v:143634$6630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:143640$6635 + cell $not $not$libresoc.v:143639$6635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_ready_i - connect \Y $not$libresoc.v:143640$6635_Y + connect \Y $not$libresoc.v:143639$6635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:143646$6641 + cell $not $not$libresoc.v:143645$6641 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:143646$6641_Y + connect \Y $not$libresoc.v:143645$6641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:143671$6666 + cell $not $not$libresoc.v:143670$6666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__zero_a - connect \Y $not$libresoc.v:143671$6666_Y + connect \Y $not$libresoc.v:143670$6666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:143672$6667 + cell $not $not$libresoc.v:143671$6667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:143672$6667_Y + connect \Y $not$libresoc.v:143671$6667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:143639$6634 + cell $or $or$libresoc.v:143638$6634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233420,10 +233420,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $or$libresoc.v:143639$6634_Y + connect \Y $or$libresoc.v:143638$6634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:143650$6645 + cell $or $or$libresoc.v:143649$6645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233431,10 +233431,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:143650$6645_Y + connect \Y $or$libresoc.v:143649$6645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:143651$6646 + cell $or $or$libresoc.v:143650$6646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233442,10 +233442,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:143651$6646_Y + connect \Y $or$libresoc.v:143650$6646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:143652$6647 + cell $or $or$libresoc.v:143651$6647 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233453,10 +233453,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:143652$6647_Y + connect \Y $or$libresoc.v:143651$6647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:143653$6648 + cell $or $or$libresoc.v:143652$6648 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -233464,10 +233464,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:143653$6648_Y + connect \Y $or$libresoc.v:143652$6648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:143656$6651 + cell $or $or$libresoc.v:143655$6651 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233475,10 +233475,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:143656$6651_Y + connect \Y $or$libresoc.v:143655$6651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:143657$6652 + cell $or $or$libresoc.v:143656$6652 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -233486,98 +233486,98 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$4 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:143657$6652_Y + connect \Y $or$libresoc.v:143656$6652_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:143663$6658 + cell $reduce_and $reduce_and$libresoc.v:143662$6658 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$6 - connect \Y $reduce_and$libresoc.v:143663$6658_Y + connect \Y $reduce_and$libresoc.v:143662$6658_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:143634$6629 + cell $reduce_or $reduce_or$libresoc.v:143633$6629 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \$25 - connect \Y $reduce_or$libresoc.v:143634$6629_Y + connect \Y $reduce_or$libresoc.v:143633$6629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:143637$6632 + cell $reduce_or $reduce_or$libresoc.v:143636$6632 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:143637$6632_Y + connect \Y $reduce_or$libresoc.v:143636$6632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:143638$6633 + cell $reduce_or $reduce_or$libresoc.v:143637$6633 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:143638$6633_Y + connect \Y $reduce_or$libresoc.v:143637$6633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:143660$6655 + cell $mux $ternary$libresoc.v:143659$6655 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:143660$6655_Y + connect \Y $ternary$libresoc.v:143659$6655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:143661$6656 + cell $mux $ternary$libresoc.v:143660$6656 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:143661$6656_Y + connect \Y $ternary$libresoc.v:143660$6656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:143662$6657 + cell $mux $ternary$libresoc.v:143661$6657 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:143662$6657_Y + connect \Y $ternary$libresoc.v:143661$6657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:143664$6659 + cell $mux $ternary$libresoc.v:143663$6659 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_logical0_logical_op__imm_data__data connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:143664$6659_Y + connect \Y $ternary$libresoc.v:143663$6659_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:143665$6660 + cell $mux $ternary$libresoc.v:143664$6660 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:143665$6660_Y + connect \Y $ternary$libresoc.v:143664$6660_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:143666$6661 + cell $mux $ternary$libresoc.v:143665$6661 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$80 connect \S \src_sel$77 - connect \Y $ternary$libresoc.v:143666$6661_Y + connect \Y $ternary$libresoc.v:143665$6661_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:143667$6662 + cell $mux $ternary$libresoc.v:143666$6662 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:143667$6662_Y + connect \Y $ternary$libresoc.v:143666$6662_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:143753.14-143759.4" + attribute \src "libresoc.v:143752.14-143758.4" cell \alu_l$61 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233586,7 +233586,7 @@ module \logical0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:143760.16-143792.4" + attribute \src "libresoc.v:143759.16-143791.4" cell \alu_logical0 \alu_logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233621,7 +233621,7 @@ module \logical0 connect \xer_so \alu_logical0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:143793.15-143799.4" + attribute \src "libresoc.v:143792.15-143798.4" cell \alui_l$60 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233630,7 +233630,7 @@ module \logical0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:143800.14-143806.4" + attribute \src "libresoc.v:143799.14-143805.4" cell \opc_l$56 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233639,7 +233639,7 @@ module \logical0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:143807.14-143813.4" + attribute \src "libresoc.v:143806.14-143812.4" cell \req_l$57 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233648,7 +233648,7 @@ module \logical0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:143814.14-143820.4" + attribute \src "libresoc.v:143813.14-143819.4" cell \rok_l$59 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233657,7 +233657,7 @@ module \logical0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:143821.14-143826.4" + attribute \src "libresoc.v:143820.14-143825.4" cell \rst_l$58 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233665,7 +233665,7 @@ module \logical0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:143827.14-143833.4" + attribute \src "libresoc.v:143826.14-143832.4" cell \src_l$55 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233673,622 +233673,622 @@ module \logical0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:143007.7-143007.20" - process $proc$libresoc.v:143007$6818 + attribute \src "libresoc.v:143006.7-143006.20" + process $proc$libresoc.v:143006$6818 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143125.7-143125.24" - process $proc$libresoc.v:143125$6819 + attribute \src "libresoc.v:143124.7-143124.24" + process $proc$libresoc.v:143124$6819 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:143135.7-143135.26" - process $proc$libresoc.v:143135$6820 + attribute \src "libresoc.v:143134.7-143134.26" + process $proc$libresoc.v:143134$6820 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:143143.7-143143.25" - process $proc$libresoc.v:143143$6821 + attribute \src "libresoc.v:143142.7-143142.25" + process $proc$libresoc.v:143142$6821 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:143151.13-143151.53" - process $proc$libresoc.v:143151$6822 + attribute \src "libresoc.v:143150.13-143150.53" + process $proc$libresoc.v:143150$6822 assign { } { } assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:143170.14-143170.57" - process $proc$libresoc.v:143170$6823 + attribute \src "libresoc.v:143169.14-143169.57" + process $proc$libresoc.v:143169$6823 assign { } { } assign $1\alu_logical0_logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:143174.14-143174.76" - process $proc$libresoc.v:143174$6824 + attribute \src "libresoc.v:143173.14-143173.76" + process $proc$libresoc.v:143173$6824 assign { } { } assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:143178.7-143178.51" - process $proc$libresoc.v:143178$6825 + attribute \src "libresoc.v:143177.7-143177.51" + process $proc$libresoc.v:143177$6825 assign { } { } assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:143186.13-143186.56" - process $proc$libresoc.v:143186$6826 + attribute \src "libresoc.v:143185.13-143185.56" + process $proc$libresoc.v:143185$6826 assign { } { } assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:143190.14-143190.51" - process $proc$libresoc.v:143190$6827 + attribute \src "libresoc.v:143189.14-143189.51" + process $proc$libresoc.v:143189$6827 assign { } { } assign $1\alu_logical0_logical_op__insn[31:0] 0 sync always sync init update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:143269.13-143269.55" - process $proc$libresoc.v:143269$6828 + attribute \src "libresoc.v:143268.13-143268.55" + process $proc$libresoc.v:143268$6828 assign { } { } assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:143273.7-143273.48" - process $proc$libresoc.v:143273$6829 + attribute \src "libresoc.v:143272.7-143272.48" + process $proc$libresoc.v:143272$6829 assign { } { } assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:143277.7-143277.49" - process $proc$libresoc.v:143277$6830 + attribute \src "libresoc.v:143276.7-143276.49" + process $proc$libresoc.v:143276$6830 assign { } { } assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:143281.7-143281.47" - process $proc$libresoc.v:143281$6831 + attribute \src "libresoc.v:143280.7-143280.47" + process $proc$libresoc.v:143280$6831 assign { } { } assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:143285.7-143285.48" - process $proc$libresoc.v:143285$6832 + attribute \src "libresoc.v:143284.7-143284.48" + process $proc$libresoc.v:143284$6832 assign { } { } assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:143289.7-143289.45" - process $proc$libresoc.v:143289$6833 + attribute \src "libresoc.v:143288.7-143288.45" + process $proc$libresoc.v:143288$6833 assign { } { } assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:143293.7-143293.45" - process $proc$libresoc.v:143293$6834 + attribute \src "libresoc.v:143292.7-143292.45" + process $proc$libresoc.v:143292$6834 assign { } { } assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:143297.7-143297.51" - process $proc$libresoc.v:143297$6835 + attribute \src "libresoc.v:143296.7-143296.51" + process $proc$libresoc.v:143296$6835 assign { } { } assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:143301.7-143301.45" - process $proc$libresoc.v:143301$6836 + attribute \src "libresoc.v:143300.7-143300.45" + process $proc$libresoc.v:143300$6836 assign { } { } assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:143305.7-143305.45" - process $proc$libresoc.v:143305$6837 + attribute \src "libresoc.v:143304.7-143304.45" + process $proc$libresoc.v:143304$6837 assign { } { } assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:143309.7-143309.48" - process $proc$libresoc.v:143309$6838 + attribute \src "libresoc.v:143308.7-143308.48" + process $proc$libresoc.v:143308$6838 assign { } { } assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:143313.7-143313.45" - process $proc$libresoc.v:143313$6839 + attribute \src "libresoc.v:143312.7-143312.45" + process $proc$libresoc.v:143312$6839 assign { } { } assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:143339.7-143339.27" - process $proc$libresoc.v:143339$6840 + attribute \src "libresoc.v:143338.7-143338.27" + process $proc$libresoc.v:143338$6840 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:143373.14-143373.47" - process $proc$libresoc.v:143373$6841 + attribute \src "libresoc.v:143372.14-143372.47" + process $proc$libresoc.v:143372$6841 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:143377.7-143377.27" - process $proc$libresoc.v:143377$6842 + attribute \src "libresoc.v:143376.7-143376.27" + process $proc$libresoc.v:143376$6842 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:143381.13-143381.33" - process $proc$libresoc.v:143381$6843 + attribute \src "libresoc.v:143380.13-143380.33" + process $proc$libresoc.v:143380$6843 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:143385.7-143385.30" - process $proc$libresoc.v:143385$6844 + attribute \src "libresoc.v:143384.7-143384.30" + process $proc$libresoc.v:143384$6844 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:143399.7-143399.25" - process $proc$libresoc.v:143399$6845 + attribute \src "libresoc.v:143398.7-143398.25" + process $proc$libresoc.v:143398$6845 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:143403.7-143403.25" - process $proc$libresoc.v:143403$6846 + attribute \src "libresoc.v:143402.7-143402.25" + process $proc$libresoc.v:143402$6846 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:143537.13-143537.30" - process $proc$libresoc.v:143537$6847 + attribute \src "libresoc.v:143536.13-143536.30" + process $proc$libresoc.v:143536$6847 assign { } { } assign $1\prev_wr_go[1:0] 2'00 sync always sync init update \prev_wr_go $1\prev_wr_go[1:0] end - attribute \src "libresoc.v:143545.13-143545.31" - process $proc$libresoc.v:143545$6848 + attribute \src "libresoc.v:143544.13-143544.31" + process $proc$libresoc.v:143544$6848 assign { } { } assign $1\req_l_r_req[1:0] 2'11 sync always sync init update \req_l_r_req $1\req_l_r_req[1:0] end - attribute \src "libresoc.v:143549.13-143549.31" - process $proc$libresoc.v:143549$6849 + attribute \src "libresoc.v:143548.13-143548.31" + process $proc$libresoc.v:143548$6849 assign { } { } assign $1\req_l_s_req[1:0] 2'00 sync always sync init update \req_l_s_req $1\req_l_s_req[1:0] end - attribute \src "libresoc.v:143561.7-143561.26" - process $proc$libresoc.v:143561$6850 + attribute \src "libresoc.v:143560.7-143560.26" + process $proc$libresoc.v:143560$6850 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:143565.7-143565.26" - process $proc$libresoc.v:143565$6851 + attribute \src "libresoc.v:143564.7-143564.26" + process $proc$libresoc.v:143564$6851 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:143569.7-143569.25" - process $proc$libresoc.v:143569$6852 + attribute \src "libresoc.v:143568.7-143568.25" + process $proc$libresoc.v:143568$6852 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:143573.7-143573.25" - process $proc$libresoc.v:143573$6853 + attribute \src "libresoc.v:143572.7-143572.25" + process $proc$libresoc.v:143572$6853 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:143587.13-143587.31" - process $proc$libresoc.v:143587$6854 + attribute \src "libresoc.v:143586.13-143586.31" + process $proc$libresoc.v:143586$6854 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:143591.13-143591.31" - process $proc$libresoc.v:143591$6855 + attribute \src "libresoc.v:143590.13-143590.31" + process $proc$libresoc.v:143590$6855 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:143599.14-143599.43" - process $proc$libresoc.v:143599$6856 + attribute \src "libresoc.v:143598.14-143598.43" + process $proc$libresoc.v:143598$6856 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:143603.14-143603.43" - process $proc$libresoc.v:143603$6857 + attribute \src "libresoc.v:143602.14-143602.43" + process $proc$libresoc.v:143602$6857 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:143607.7-143607.20" - process $proc$libresoc.v:143607$6858 + attribute \src "libresoc.v:143606.7-143606.20" + process $proc$libresoc.v:143606$6858 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:143673.3-143674.39" - process $proc$libresoc.v:143673$6668 + attribute \src "libresoc.v:143672.3-143673.39" + process $proc$libresoc.v:143672$6668 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:143675.3-143676.43" - process $proc$libresoc.v:143675$6669 + attribute \src "libresoc.v:143674.3-143675.43" + process $proc$libresoc.v:143674$6669 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:143677.3-143678.29" - process $proc$libresoc.v:143677$6670 + attribute \src "libresoc.v:143676.3-143677.29" + process $proc$libresoc.v:143676$6670 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:143679.3-143680.29" - process $proc$libresoc.v:143679$6671 + attribute \src "libresoc.v:143678.3-143679.29" + process $proc$libresoc.v:143678$6671 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:143681.3-143682.29" - process $proc$libresoc.v:143681$6672 + attribute \src "libresoc.v:143680.3-143681.29" + process $proc$libresoc.v:143680$6672 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:143683.3-143684.43" - process $proc$libresoc.v:143683$6673 + attribute \src "libresoc.v:143682.3-143683.43" + process $proc$libresoc.v:143682$6673 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:143685.3-143686.49" - process $proc$libresoc.v:143685$6674 + attribute \src "libresoc.v:143684.3-143685.49" + process $proc$libresoc.v:143684$6674 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:143687.3-143688.37" - process $proc$libresoc.v:143687$6675 + attribute \src "libresoc.v:143686.3-143687.37" + process $proc$libresoc.v:143686$6675 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:143689.3-143690.43" - process $proc$libresoc.v:143689$6676 + attribute \src "libresoc.v:143688.3-143689.43" + process $proc$libresoc.v:143688$6676 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:143691.3-143692.85" - process $proc$libresoc.v:143691$6677 + attribute \src "libresoc.v:143690.3-143691.85" + process $proc$libresoc.v:143690$6677 assign { } { } assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:143693.3-143694.81" - process $proc$libresoc.v:143693$6678 + attribute \src "libresoc.v:143692.3-143693.81" + process $proc$libresoc.v:143692$6678 assign { } { } assign $0\alu_logical0_logical_op__fn_unit[13:0] \alu_logical0_logical_op__fn_unit$next sync posedge \coresync_clk update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:143695.3-143696.95" - process $proc$libresoc.v:143695$6679 + attribute \src "libresoc.v:143694.3-143695.95" + process $proc$libresoc.v:143694$6679 assign { } { } assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:143697.3-143698.91" - process $proc$libresoc.v:143697$6680 + attribute \src "libresoc.v:143696.3-143697.91" + process $proc$libresoc.v:143696$6680 assign { } { } assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:143699.3-143700.79" - process $proc$libresoc.v:143699$6681 + attribute \src "libresoc.v:143698.3-143699.79" + process $proc$libresoc.v:143698$6681 assign { } { } assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:143701.3-143702.79" - process $proc$libresoc.v:143701$6682 + attribute \src "libresoc.v:143700.3-143701.79" + process $proc$libresoc.v:143700$6682 assign { } { } assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:143703.3-143704.79" - process $proc$libresoc.v:143703$6683 + attribute \src "libresoc.v:143702.3-143703.79" + process $proc$libresoc.v:143702$6683 assign { } { } assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:143705.3-143706.79" - process $proc$libresoc.v:143705$6684 + attribute \src "libresoc.v:143704.3-143705.79" + process $proc$libresoc.v:143704$6684 assign { } { } assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:143707.3-143708.85" - process $proc$libresoc.v:143707$6685 + attribute \src "libresoc.v:143706.3-143707.85" + process $proc$libresoc.v:143706$6685 assign { } { } assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:143709.3-143710.79" - process $proc$libresoc.v:143709$6686 + attribute \src "libresoc.v:143708.3-143709.79" + process $proc$libresoc.v:143708$6686 assign { } { } assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:143711.3-143712.89" - process $proc$libresoc.v:143711$6687 + attribute \src "libresoc.v:143710.3-143711.89" + process $proc$libresoc.v:143710$6687 assign { } { } assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:143713.3-143714.87" - process $proc$libresoc.v:143713$6688 + attribute \src "libresoc.v:143712.3-143713.87" + process $proc$libresoc.v:143712$6688 assign { } { } assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:143715.3-143716.85" - process $proc$libresoc.v:143715$6689 + attribute \src "libresoc.v:143714.3-143715.85" + process $proc$libresoc.v:143714$6689 assign { } { } assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:143717.3-143718.91" - process $proc$libresoc.v:143717$6690 + attribute \src "libresoc.v:143716.3-143717.91" + process $proc$libresoc.v:143716$6690 assign { } { } assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:143719.3-143720.83" - process $proc$libresoc.v:143719$6691 + attribute \src "libresoc.v:143718.3-143719.83" + process $proc$libresoc.v:143718$6691 assign { } { } assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:143721.3-143722.85" - process $proc$libresoc.v:143721$6692 + attribute \src "libresoc.v:143720.3-143721.85" + process $proc$libresoc.v:143720$6692 assign { } { } assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:143723.3-143724.83" - process $proc$libresoc.v:143723$6693 + attribute \src "libresoc.v:143722.3-143723.83" + process $proc$libresoc.v:143722$6693 assign { } { } assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next sync posedge \coresync_clk update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:143725.3-143726.75" - process $proc$libresoc.v:143725$6694 + attribute \src "libresoc.v:143724.3-143725.75" + process $proc$libresoc.v:143724$6694 assign { } { } assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:143727.3-143728.39" - process $proc$libresoc.v:143727$6695 + attribute \src "libresoc.v:143726.3-143727.39" + process $proc$libresoc.v:143726$6695 assign { } { } assign $0\req_l_r_req[1:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[1:0] end - attribute \src "libresoc.v:143729.3-143730.39" - process $proc$libresoc.v:143729$6696 + attribute \src "libresoc.v:143728.3-143729.39" + process $proc$libresoc.v:143728$6696 assign { } { } assign $0\req_l_s_req[1:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[1:0] end - attribute \src "libresoc.v:143731.3-143732.39" - process $proc$libresoc.v:143731$6697 + attribute \src "libresoc.v:143730.3-143731.39" + process $proc$libresoc.v:143730$6697 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:143733.3-143734.39" - process $proc$libresoc.v:143733$6698 + attribute \src "libresoc.v:143732.3-143733.39" + process $proc$libresoc.v:143732$6698 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:143735.3-143736.39" - process $proc$libresoc.v:143735$6699 + attribute \src "libresoc.v:143734.3-143735.39" + process $proc$libresoc.v:143734$6699 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:143737.3-143738.39" - process $proc$libresoc.v:143737$6700 + attribute \src "libresoc.v:143736.3-143737.39" + process $proc$libresoc.v:143736$6700 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:143739.3-143740.39" - process $proc$libresoc.v:143739$6701 + attribute \src "libresoc.v:143738.3-143739.39" + process $proc$libresoc.v:143738$6701 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:143741.3-143742.39" - process $proc$libresoc.v:143741$6702 + attribute \src "libresoc.v:143740.3-143741.39" + process $proc$libresoc.v:143740$6702 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:143743.3-143744.41" - process $proc$libresoc.v:143743$6703 + attribute \src "libresoc.v:143742.3-143743.41" + process $proc$libresoc.v:143742$6703 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:143745.3-143746.41" - process $proc$libresoc.v:143745$6704 + attribute \src "libresoc.v:143744.3-143745.41" + process $proc$libresoc.v:143744$6704 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:143747.3-143748.37" - process $proc$libresoc.v:143747$6705 + attribute \src "libresoc.v:143746.3-143747.37" + process $proc$libresoc.v:143746$6705 assign { } { } assign $0\prev_wr_go[1:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[1:0] end - attribute \src "libresoc.v:143749.3-143750.44" - process $proc$libresoc.v:143749$6706 + attribute \src "libresoc.v:143748.3-143749.44" + process $proc$libresoc.v:143748$6706 assign { } { } assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:143751.3-143752.24" - process $proc$libresoc.v:143751$6707 + attribute \src "libresoc.v:143750.3-143751.24" + process $proc$libresoc.v:143750$6707 assign { } { } assign $0\all_rd_dly[0:0] \$9 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:143834.3-143843.6" - process $proc$libresoc.v:143834$6708 + attribute \src "libresoc.v:143833.3-143842.6" + process $proc$libresoc.v:143833$6708 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:143835.5-143835.29" + attribute \src "libresoc.v:143834.5-143834.29" switch \initial - attribute \src "libresoc.v:143835.9-143835.17" + attribute \src "libresoc.v:143834.9-143834.17" case 1'1 case end @@ -234304,14 +234304,14 @@ module \logical0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:143844.3-143852.6" - process $proc$libresoc.v:143844$6709 + attribute \src "libresoc.v:143843.3-143851.6" + process $proc$libresoc.v:143843$6709 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$6710 $1\rok_l_s_rdok$next[0:0]$6711 - attribute \src "libresoc.v:143845.5-143845.29" + attribute \src "libresoc.v:143844.5-143844.29" switch \initial - attribute \src "libresoc.v:143845.9-143845.17" + attribute \src "libresoc.v:143844.9-143844.17" case 1'1 case end @@ -234327,14 +234327,14 @@ module \logical0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6710 end - attribute \src "libresoc.v:143853.3-143861.6" - process $proc$libresoc.v:143853$6712 + attribute \src "libresoc.v:143852.3-143860.6" + process $proc$libresoc.v:143852$6712 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$6713 $1\rok_l_r_rdok$next[0:0]$6714 - attribute \src "libresoc.v:143854.5-143854.29" + attribute \src "libresoc.v:143853.5-143853.29" switch \initial - attribute \src "libresoc.v:143854.9-143854.17" + attribute \src "libresoc.v:143853.9-143853.17" case 1'1 case end @@ -234350,14 +234350,14 @@ module \logical0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6713 end - attribute \src "libresoc.v:143862.3-143870.6" - process $proc$libresoc.v:143862$6715 + attribute \src "libresoc.v:143861.3-143869.6" + process $proc$libresoc.v:143861$6715 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$6716 $1\rst_l_s_rst$next[0:0]$6717 - attribute \src "libresoc.v:143863.5-143863.29" + attribute \src "libresoc.v:143862.5-143862.29" switch \initial - attribute \src "libresoc.v:143863.9-143863.17" + attribute \src "libresoc.v:143862.9-143862.17" case 1'1 case end @@ -234373,14 +234373,14 @@ module \logical0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6716 end - attribute \src "libresoc.v:143871.3-143879.6" - process $proc$libresoc.v:143871$6718 + attribute \src "libresoc.v:143870.3-143878.6" + process $proc$libresoc.v:143870$6718 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$6719 $1\rst_l_r_rst$next[0:0]$6720 - attribute \src "libresoc.v:143872.5-143872.29" + attribute \src "libresoc.v:143871.5-143871.29" switch \initial - attribute \src "libresoc.v:143872.9-143872.17" + attribute \src "libresoc.v:143871.9-143871.17" case 1'1 case end @@ -234396,14 +234396,14 @@ module \logical0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6719 end - attribute \src "libresoc.v:143880.3-143888.6" - process $proc$libresoc.v:143880$6721 + attribute \src "libresoc.v:143879.3-143887.6" + process $proc$libresoc.v:143879$6721 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$6722 $1\opc_l_s_opc$next[0:0]$6723 - attribute \src "libresoc.v:143881.5-143881.29" + attribute \src "libresoc.v:143880.5-143880.29" switch \initial - attribute \src "libresoc.v:143881.9-143881.17" + attribute \src "libresoc.v:143880.9-143880.17" case 1'1 case end @@ -234419,14 +234419,14 @@ module \logical0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6722 end - attribute \src "libresoc.v:143889.3-143897.6" - process $proc$libresoc.v:143889$6724 + attribute \src "libresoc.v:143888.3-143896.6" + process $proc$libresoc.v:143888$6724 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$6725 $1\opc_l_r_opc$next[0:0]$6726 - attribute \src "libresoc.v:143890.5-143890.29" + attribute \src "libresoc.v:143889.5-143889.29" switch \initial - attribute \src "libresoc.v:143890.9-143890.17" + attribute \src "libresoc.v:143889.9-143889.17" case 1'1 case end @@ -234442,14 +234442,14 @@ module \logical0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6725 end - attribute \src "libresoc.v:143898.3-143906.6" - process $proc$libresoc.v:143898$6727 + attribute \src "libresoc.v:143897.3-143905.6" + process $proc$libresoc.v:143897$6727 assign { } { } assign { } { } assign $0\src_l_s_src$next[2:0]$6728 $1\src_l_s_src$next[2:0]$6729 - attribute \src "libresoc.v:143899.5-143899.29" + attribute \src "libresoc.v:143898.5-143898.29" switch \initial - attribute \src "libresoc.v:143899.9-143899.17" + attribute \src "libresoc.v:143898.9-143898.17" case 1'1 case end @@ -234465,14 +234465,14 @@ module \logical0 sync always update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6728 end - attribute \src "libresoc.v:143907.3-143915.6" - process $proc$libresoc.v:143907$6730 + attribute \src "libresoc.v:143906.3-143914.6" + process $proc$libresoc.v:143906$6730 assign { } { } assign { } { } assign $0\src_l_r_src$next[2:0]$6731 $1\src_l_r_src$next[2:0]$6732 - attribute \src "libresoc.v:143908.5-143908.29" + attribute \src "libresoc.v:143907.5-143907.29" switch \initial - attribute \src "libresoc.v:143908.9-143908.17" + attribute \src "libresoc.v:143907.9-143907.17" case 1'1 case end @@ -234488,14 +234488,14 @@ module \logical0 sync always update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6731 end - attribute \src "libresoc.v:143916.3-143924.6" - process $proc$libresoc.v:143916$6733 + attribute \src "libresoc.v:143915.3-143923.6" + process $proc$libresoc.v:143915$6733 assign { } { } assign { } { } assign $0\req_l_s_req$next[1:0]$6734 $1\req_l_s_req$next[1:0]$6735 - attribute \src "libresoc.v:143917.5-143917.29" + attribute \src "libresoc.v:143916.5-143916.29" switch \initial - attribute \src "libresoc.v:143917.9-143917.17" + attribute \src "libresoc.v:143916.9-143916.17" case 1'1 case end @@ -234511,14 +234511,14 @@ module \logical0 sync always update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6734 end - attribute \src "libresoc.v:143925.3-143933.6" - process $proc$libresoc.v:143925$6736 + attribute \src "libresoc.v:143924.3-143932.6" + process $proc$libresoc.v:143924$6736 assign { } { } assign { } { } assign $0\req_l_r_req$next[1:0]$6737 $1\req_l_r_req$next[1:0]$6738 - attribute \src "libresoc.v:143926.5-143926.29" + attribute \src "libresoc.v:143925.5-143925.29" switch \initial - attribute \src "libresoc.v:143926.9-143926.17" + attribute \src "libresoc.v:143925.9-143925.17" case 1'1 case end @@ -234534,8 +234534,8 @@ module \logical0 sync always update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6737 end - attribute \src "libresoc.v:143934.3-143972.6" - process $proc$libresoc.v:143934$6739 + attribute \src "libresoc.v:143933.3-143971.6" + process $proc$libresoc.v:143933$6739 assign { } { } assign { } { } assign { } { } @@ -234596,9 +234596,9 @@ module \logical0 assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6752 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6754 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6755 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 - attribute \src "libresoc.v:143935.5-143935.29" + attribute \src "libresoc.v:143934.5-143934.29" switch \initial - attribute \src "libresoc.v:143935.9-143935.17" + attribute \src "libresoc.v:143934.9-143934.17" case 1'1 case end @@ -234689,8 +234689,8 @@ module \logical0 update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6756 update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6757 end - attribute \src "libresoc.v:143973.3-143994.6" - process $proc$libresoc.v:143973$6782 + attribute \src "libresoc.v:143972.3-143993.6" + process $proc$libresoc.v:143972$6782 assign { } { } assign { } { } assign { } { } @@ -234700,9 +234700,9 @@ module \logical0 assign $0\data_r0__o$next[63:0]$6783 $2\data_r0__o$next[63:0]$6787 assign { } { } assign $0\data_r0__o_ok$next[0:0]$6784 $3\data_r0__o_ok$next[0:0]$6789 - attribute \src "libresoc.v:143974.5-143974.29" + attribute \src "libresoc.v:143973.5-143973.29" switch \initial - attribute \src "libresoc.v:143974.9-143974.17" + attribute \src "libresoc.v:143973.9-143973.17" case 1'1 case end @@ -234741,8 +234741,8 @@ module \logical0 update \data_r0__o$next $0\data_r0__o$next[63:0]$6783 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6784 end - attribute \src "libresoc.v:143995.3-144016.6" - process $proc$libresoc.v:143995$6790 + attribute \src "libresoc.v:143994.3-144015.6" + process $proc$libresoc.v:143994$6790 assign { } { } assign { } { } assign { } { } @@ -234752,9 +234752,9 @@ module \logical0 assign $0\data_r1__cr_a$next[3:0]$6791 $2\data_r1__cr_a$next[3:0]$6795 assign { } { } assign $0\data_r1__cr_a_ok$next[0:0]$6792 $3\data_r1__cr_a_ok$next[0:0]$6797 - attribute \src "libresoc.v:143996.5-143996.29" + attribute \src "libresoc.v:143995.5-143995.29" switch \initial - attribute \src "libresoc.v:143996.9-143996.17" + attribute \src "libresoc.v:143995.9-143995.17" case 1'1 case end @@ -234793,14 +234793,14 @@ module \logical0 update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6791 update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6792 end - attribute \src "libresoc.v:144017.3-144026.6" - process $proc$libresoc.v:144017$6798 + attribute \src "libresoc.v:144016.3-144025.6" + process $proc$libresoc.v:144016$6798 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$6799 $1\src_r0$next[63:0]$6800 - attribute \src "libresoc.v:144018.5-144018.29" + attribute \src "libresoc.v:144017.5-144017.29" switch \initial - attribute \src "libresoc.v:144018.9-144018.17" + attribute \src "libresoc.v:144017.9-144017.17" case 1'1 case end @@ -234816,14 +234816,14 @@ module \logical0 sync always update \src_r0$next $0\src_r0$next[63:0]$6799 end - attribute \src "libresoc.v:144027.3-144036.6" - process $proc$libresoc.v:144027$6801 + attribute \src "libresoc.v:144026.3-144035.6" + process $proc$libresoc.v:144026$6801 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$6802 $1\src_r1$next[63:0]$6803 - attribute \src "libresoc.v:144028.5-144028.29" + attribute \src "libresoc.v:144027.5-144027.29" switch \initial - attribute \src "libresoc.v:144028.9-144028.17" + attribute \src "libresoc.v:144027.9-144027.17" case 1'1 case end @@ -234839,14 +234839,14 @@ module \logical0 sync always update \src_r1$next $0\src_r1$next[63:0]$6802 end - attribute \src "libresoc.v:144037.3-144046.6" - process $proc$libresoc.v:144037$6804 + attribute \src "libresoc.v:144036.3-144045.6" + process $proc$libresoc.v:144036$6804 assign { } { } assign { } { } assign $0\src_r2$next[0:0]$6805 $1\src_r2$next[0:0]$6806 - attribute \src "libresoc.v:144038.5-144038.29" + attribute \src "libresoc.v:144037.5-144037.29" switch \initial - attribute \src "libresoc.v:144038.9-144038.17" + attribute \src "libresoc.v:144037.9-144037.17" case 1'1 case end @@ -234862,14 +234862,14 @@ module \logical0 sync always update \src_r2$next $0\src_r2$next[0:0]$6805 end - attribute \src "libresoc.v:144047.3-144055.6" - process $proc$libresoc.v:144047$6807 + attribute \src "libresoc.v:144046.3-144054.6" + process $proc$libresoc.v:144046$6807 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$6808 $1\alui_l_r_alui$next[0:0]$6809 - attribute \src "libresoc.v:144048.5-144048.29" + attribute \src "libresoc.v:144047.5-144047.29" switch \initial - attribute \src "libresoc.v:144048.9-144048.17" + attribute \src "libresoc.v:144047.9-144047.17" case 1'1 case end @@ -234885,14 +234885,14 @@ module \logical0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6808 end - attribute \src "libresoc.v:144056.3-144064.6" - process $proc$libresoc.v:144056$6810 + attribute \src "libresoc.v:144055.3-144063.6" + process $proc$libresoc.v:144055$6810 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$6811 $1\alu_l_r_alu$next[0:0]$6812 - attribute \src "libresoc.v:144057.5-144057.29" + attribute \src "libresoc.v:144056.5-144056.29" switch \initial - attribute \src "libresoc.v:144057.9-144057.17" + attribute \src "libresoc.v:144056.9-144056.17" case 1'1 case end @@ -234908,14 +234908,14 @@ module \logical0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6811 end - attribute \src "libresoc.v:144065.3-144074.6" - process $proc$libresoc.v:144065$6813 + attribute \src "libresoc.v:144064.3-144073.6" + process $proc$libresoc.v:144064$6813 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:144066.5-144066.29" + attribute \src "libresoc.v:144065.5-144065.29" switch \initial - attribute \src "libresoc.v:144066.9-144066.17" + attribute \src "libresoc.v:144065.9-144065.17" case 1'1 case end @@ -234931,14 +234931,14 @@ module \logical0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:144075.3-144084.6" - process $proc$libresoc.v:144075$6814 + attribute \src "libresoc.v:144074.3-144083.6" + process $proc$libresoc.v:144074$6814 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:144076.5-144076.29" + attribute \src "libresoc.v:144075.5-144075.29" switch \initial - attribute \src "libresoc.v:144076.9-144076.17" + attribute \src "libresoc.v:144075.9-144075.17" case 1'1 case end @@ -234954,14 +234954,14 @@ module \logical0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:144085.3-144093.6" - process $proc$libresoc.v:144085$6815 + attribute \src "libresoc.v:144084.3-144092.6" + process $proc$libresoc.v:144084$6815 assign { } { } assign { } { } assign $0\prev_wr_go$next[1:0]$6816 $1\prev_wr_go$next[1:0]$6817 - attribute \src "libresoc.v:144086.5-144086.29" + attribute \src "libresoc.v:144085.5-144085.29" switch \initial - attribute \src "libresoc.v:144086.9-144086.17" + attribute \src "libresoc.v:144085.9-144085.17" case 1'1 case end @@ -234977,63 +234977,63 @@ module \logical0 sync always update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6816 end - connect \$9 $and$libresoc.v:143616$6611_Y - connect \$99 $and$libresoc.v:143617$6612_Y - connect \$101 $not$libresoc.v:143618$6613_Y - connect \$103 $and$libresoc.v:143619$6614_Y - connect \$105 $and$libresoc.v:143620$6615_Y - connect \$107 $and$libresoc.v:143621$6616_Y - connect \$109 $and$libresoc.v:143622$6617_Y - connect \$111 $and$libresoc.v:143623$6618_Y - connect \$113 $and$libresoc.v:143624$6619_Y - connect \$115 $and$libresoc.v:143625$6620_Y - connect \$11 $not$libresoc.v:143626$6621_Y - connect \$13 $and$libresoc.v:143627$6622_Y - connect \$15 $not$libresoc.v:143628$6623_Y - connect \$17 $and$libresoc.v:143629$6624_Y - connect \$1 $and$libresoc.v:143630$6625_Y - connect \$19 $and$libresoc.v:143631$6626_Y - connect \$23 $not$libresoc.v:143632$6627_Y - connect \$25 $and$libresoc.v:143633$6628_Y - connect \$22 $reduce_or$libresoc.v:143634$6629_Y - connect \$21 $not$libresoc.v:143635$6630_Y - connect \$29 $and$libresoc.v:143636$6631_Y - connect \$31 $reduce_or$libresoc.v:143637$6632_Y - connect \$33 $reduce_or$libresoc.v:143638$6633_Y - connect \$35 $or$libresoc.v:143639$6634_Y - connect \$37 $not$libresoc.v:143640$6635_Y - connect \$39 $and$libresoc.v:143641$6636_Y - connect \$41 $and$libresoc.v:143642$6637_Y - connect \$43 $eq$libresoc.v:143643$6638_Y - connect \$45 $and$libresoc.v:143644$6639_Y - connect \$47 $eq$libresoc.v:143645$6640_Y - connect \$4 $not$libresoc.v:143646$6641_Y - connect \$49 $and$libresoc.v:143647$6642_Y - connect \$51 $and$libresoc.v:143648$6643_Y - connect \$53 $and$libresoc.v:143649$6644_Y - connect \$55 $or$libresoc.v:143650$6645_Y - connect \$57 $or$libresoc.v:143651$6646_Y - connect \$59 $or$libresoc.v:143652$6647_Y - connect \$61 $or$libresoc.v:143653$6648_Y - connect \$63 $and$libresoc.v:143654$6649_Y - connect \$65 $and$libresoc.v:143655$6650_Y - connect \$67 $or$libresoc.v:143656$6651_Y - connect \$6 $or$libresoc.v:143657$6652_Y - connect \$69 $and$libresoc.v:143658$6653_Y - connect \$71 $and$libresoc.v:143659$6654_Y - connect \$73 $ternary$libresoc.v:143660$6655_Y - connect \$75 $ternary$libresoc.v:143661$6656_Y - connect \$78 $ternary$libresoc.v:143662$6657_Y - connect \$3 $reduce_and$libresoc.v:143663$6658_Y - connect \$81 $ternary$libresoc.v:143664$6659_Y - connect \$83 $ternary$libresoc.v:143665$6660_Y - connect \$85 $ternary$libresoc.v:143666$6661_Y - connect \$87 $ternary$libresoc.v:143667$6662_Y - connect \$89 $and$libresoc.v:143668$6663_Y - connect \$91 $and$libresoc.v:143669$6664_Y - connect \$93 $and$libresoc.v:143670$6665_Y - connect \$95 $not$libresoc.v:143671$6666_Y - connect \$97 $not$libresoc.v:143672$6667_Y + connect \$9 $and$libresoc.v:143615$6611_Y + connect \$99 $and$libresoc.v:143616$6612_Y + connect \$101 $not$libresoc.v:143617$6613_Y + connect \$103 $and$libresoc.v:143618$6614_Y + connect \$105 $and$libresoc.v:143619$6615_Y + connect \$107 $and$libresoc.v:143620$6616_Y + connect \$109 $and$libresoc.v:143621$6617_Y + connect \$111 $and$libresoc.v:143622$6618_Y + connect \$113 $and$libresoc.v:143623$6619_Y + connect \$115 $and$libresoc.v:143624$6620_Y + connect \$11 $not$libresoc.v:143625$6621_Y + connect \$13 $and$libresoc.v:143626$6622_Y + connect \$15 $not$libresoc.v:143627$6623_Y + connect \$17 $and$libresoc.v:143628$6624_Y + connect \$1 $and$libresoc.v:143629$6625_Y + connect \$19 $and$libresoc.v:143630$6626_Y + connect \$23 $not$libresoc.v:143631$6627_Y + connect \$25 $and$libresoc.v:143632$6628_Y + connect \$22 $reduce_or$libresoc.v:143633$6629_Y + connect \$21 $not$libresoc.v:143634$6630_Y + connect \$29 $and$libresoc.v:143635$6631_Y + connect \$31 $reduce_or$libresoc.v:143636$6632_Y + connect \$33 $reduce_or$libresoc.v:143637$6633_Y + connect \$35 $or$libresoc.v:143638$6634_Y + connect \$37 $not$libresoc.v:143639$6635_Y + connect \$39 $and$libresoc.v:143640$6636_Y + connect \$41 $and$libresoc.v:143641$6637_Y + connect \$43 $eq$libresoc.v:143642$6638_Y + connect \$45 $and$libresoc.v:143643$6639_Y + connect \$47 $eq$libresoc.v:143644$6640_Y + connect \$4 $not$libresoc.v:143645$6641_Y + connect \$49 $and$libresoc.v:143646$6642_Y + connect \$51 $and$libresoc.v:143647$6643_Y + connect \$53 $and$libresoc.v:143648$6644_Y + connect \$55 $or$libresoc.v:143649$6645_Y + connect \$57 $or$libresoc.v:143650$6646_Y + connect \$59 $or$libresoc.v:143651$6647_Y + connect \$61 $or$libresoc.v:143652$6648_Y + connect \$63 $and$libresoc.v:143653$6649_Y + connect \$65 $and$libresoc.v:143654$6650_Y + connect \$67 $or$libresoc.v:143655$6651_Y + connect \$6 $or$libresoc.v:143656$6652_Y + connect \$69 $and$libresoc.v:143657$6653_Y + connect \$71 $and$libresoc.v:143658$6654_Y + connect \$73 $ternary$libresoc.v:143659$6655_Y + connect \$75 $ternary$libresoc.v:143660$6656_Y + connect \$78 $ternary$libresoc.v:143661$6657_Y + connect \$3 $reduce_and$libresoc.v:143662$6658_Y + connect \$81 $ternary$libresoc.v:143663$6659_Y + connect \$83 $ternary$libresoc.v:143664$6660_Y + connect \$85 $ternary$libresoc.v:143665$6661_Y + connect \$87 $ternary$libresoc.v:143666$6662_Y + connect \$89 $and$libresoc.v:143667$6663_Y + connect \$91 $and$libresoc.v:143668$6664_Y + connect \$93 $and$libresoc.v:143669$6665_Y + connect \$95 $not$libresoc.v:143670$6666_Y + connect \$97 $not$libresoc.v:143671$6667_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$111 @@ -235067,243 +235067,243 @@ module \logical0 connect \all_rd_dly$next \all_rd connect \all_rd \$9 end -attribute \src "libresoc.v:144130.1-145521.10" +attribute \src "libresoc.v:144129.1-145520.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" attribute \generator "nMigen" module \logical_pipe1 - attribute \src "libresoc.v:145460.3-145478.6" + attribute \src "libresoc.v:145459.3-145477.6" wire width 4 $0\cr_a$next[3:0]$6943 - attribute \src "libresoc.v:145220.3-145221.25" + attribute \src "libresoc.v:145219.3-145220.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:145460.3-145478.6" + attribute \src "libresoc.v:145459.3-145477.6" wire $0\cr_a_ok$next[0:0]$6944 - attribute \src "libresoc.v:145222.3-145223.31" + attribute \src "libresoc.v:145221.3-145222.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:144131.7-144131.20" + attribute \src "libresoc.v:144130.7-144130.20" wire $0\initial[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire width 4 $0\logical_op__data_len$next[3:0]$6894 - attribute \src "libresoc.v:145260.3-145261.57" + attribute \src "libresoc.v:145259.3-145260.57" wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire width 14 $0\logical_op__fn_unit$next[13:0]$6895 - attribute \src "libresoc.v:145230.3-145231.55" + attribute \src "libresoc.v:145229.3-145230.55" wire width 14 $0\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire width 64 $0\logical_op__imm_data__data$next[63:0]$6896 - attribute \src "libresoc.v:145232.3-145233.69" + attribute \src "libresoc.v:145231.3-145232.69" wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $0\logical_op__imm_data__ok$next[0:0]$6897 - attribute \src "libresoc.v:145234.3-145235.65" + attribute \src "libresoc.v:145233.3-145234.65" wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire width 2 $0\logical_op__input_carry$next[1:0]$6898 - attribute \src "libresoc.v:145248.3-145249.63" + attribute \src "libresoc.v:145247.3-145248.63" wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire width 32 $0\logical_op__insn$next[31:0]$6899 - attribute \src "libresoc.v:145262.3-145263.49" + attribute \src "libresoc.v:145261.3-145262.49" wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire width 7 $0\logical_op__insn_type$next[6:0]$6900 - attribute \src "libresoc.v:145228.3-145229.59" + attribute \src "libresoc.v:145227.3-145228.59" wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $0\logical_op__invert_in$next[0:0]$6901 - attribute \src "libresoc.v:145244.3-145245.59" + attribute \src "libresoc.v:145243.3-145244.59" wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $0\logical_op__invert_out$next[0:0]$6902 - attribute \src "libresoc.v:145250.3-145251.61" + attribute \src "libresoc.v:145249.3-145250.61" wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $0\logical_op__is_32bit$next[0:0]$6903 - attribute \src "libresoc.v:145256.3-145257.57" + attribute \src "libresoc.v:145255.3-145256.57" wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $0\logical_op__is_signed$next[0:0]$6904 - attribute \src "libresoc.v:145258.3-145259.59" + attribute \src "libresoc.v:145257.3-145258.59" wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $0\logical_op__oe__oe$next[0:0]$6905 - attribute \src "libresoc.v:145240.3-145241.53" + attribute \src "libresoc.v:145239.3-145240.53" wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $0\logical_op__oe__ok$next[0:0]$6906 - attribute \src "libresoc.v:145242.3-145243.53" + attribute \src "libresoc.v:145241.3-145242.53" wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $0\logical_op__output_carry$next[0:0]$6907 - attribute \src "libresoc.v:145254.3-145255.65" + attribute \src "libresoc.v:145253.3-145254.65" wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $0\logical_op__rc__ok$next[0:0]$6908 - attribute \src "libresoc.v:145238.3-145239.53" + attribute \src "libresoc.v:145237.3-145238.53" wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $0\logical_op__rc__rc$next[0:0]$6909 - attribute \src "libresoc.v:145236.3-145237.53" + attribute \src "libresoc.v:145235.3-145236.53" wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $0\logical_op__write_cr0$next[0:0]$6910 - attribute \src "libresoc.v:145252.3-145253.59" + attribute \src "libresoc.v:145251.3-145252.59" wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $0\logical_op__zero_a$next[0:0]$6911 - attribute \src "libresoc.v:145246.3-145247.53" + attribute \src "libresoc.v:145245.3-145246.53" wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:145386.3-145398.6" + attribute \src "libresoc.v:145385.3-145397.6" wire width 2 $0\muxid$next[1:0]$6891 - attribute \src "libresoc.v:145264.3-145265.27" + attribute \src "libresoc.v:145263.3-145264.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:145441.3-145459.6" + attribute \src "libresoc.v:145440.3-145458.6" wire width 64 $0\o$next[63:0]$6937 - attribute \src "libresoc.v:145224.3-145225.19" + attribute \src "libresoc.v:145223.3-145224.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:145441.3-145459.6" + attribute \src "libresoc.v:145440.3-145458.6" wire $0\o_ok$next[0:0]$6938 - attribute \src "libresoc.v:145226.3-145227.25" + attribute \src "libresoc.v:145225.3-145226.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:145368.3-145385.6" + attribute \src "libresoc.v:145367.3-145384.6" wire $0\r_busy$next[0:0]$6887 - attribute \src "libresoc.v:145266.3-145267.29" + attribute \src "libresoc.v:145265.3-145266.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:145479.3-145497.6" + attribute \src "libresoc.v:145478.3-145496.6" wire $0\xer_so$next[0:0]$6949 - attribute \src "libresoc.v:145216.3-145217.29" + attribute \src "libresoc.v:145215.3-145216.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:145479.3-145497.6" + attribute \src "libresoc.v:145478.3-145496.6" wire $0\xer_so_ok$next[0:0]$6950 - attribute \src "libresoc.v:145218.3-145219.35" + attribute \src "libresoc.v:145217.3-145218.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:145460.3-145478.6" + attribute \src "libresoc.v:145459.3-145477.6" wire width 4 $1\cr_a$next[3:0]$6945 - attribute \src "libresoc.v:144140.13-144140.24" + attribute \src "libresoc.v:144139.13-144139.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:145460.3-145478.6" + attribute \src "libresoc.v:145459.3-145477.6" wire $1\cr_a_ok$next[0:0]$6946 - attribute \src "libresoc.v:144149.7-144149.21" + attribute \src "libresoc.v:144148.7-144148.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire width 4 $1\logical_op__data_len$next[3:0]$6912 - attribute \src "libresoc.v:144434.13-144434.40" + attribute \src "libresoc.v:144433.13-144433.40" wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire width 14 $1\logical_op__fn_unit$next[13:0]$6913 - attribute \src "libresoc.v:144458.14-144458.44" + attribute \src "libresoc.v:144457.14-144457.44" wire width 14 $1\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire width 64 $1\logical_op__imm_data__data$next[63:0]$6914 - attribute \src "libresoc.v:144497.14-144497.63" + attribute \src "libresoc.v:144496.14-144496.63" wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $1\logical_op__imm_data__ok$next[0:0]$6915 - attribute \src "libresoc.v:144506.7-144506.38" + attribute \src "libresoc.v:144505.7-144505.38" wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire width 2 $1\logical_op__input_carry$next[1:0]$6916 - attribute \src "libresoc.v:144519.13-144519.43" + attribute \src "libresoc.v:144518.13-144518.43" wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire width 32 $1\logical_op__insn$next[31:0]$6917 - attribute \src "libresoc.v:144536.14-144536.38" + attribute \src "libresoc.v:144535.14-144535.38" wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire width 7 $1\logical_op__insn_type$next[6:0]$6918 - attribute \src "libresoc.v:144620.13-144620.42" + attribute \src "libresoc.v:144619.13-144619.42" wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $1\logical_op__invert_in$next[0:0]$6919 - attribute \src "libresoc.v:144779.7-144779.35" + attribute \src "libresoc.v:144778.7-144778.35" wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $1\logical_op__invert_out$next[0:0]$6920 - attribute \src "libresoc.v:144788.7-144788.36" + attribute \src "libresoc.v:144787.7-144787.36" wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $1\logical_op__is_32bit$next[0:0]$6921 - attribute \src "libresoc.v:144797.7-144797.34" + attribute \src "libresoc.v:144796.7-144796.34" wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $1\logical_op__is_signed$next[0:0]$6922 - attribute \src "libresoc.v:144806.7-144806.35" + attribute \src "libresoc.v:144805.7-144805.35" wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $1\logical_op__oe__oe$next[0:0]$6923 - attribute \src "libresoc.v:144815.7-144815.32" + attribute \src "libresoc.v:144814.7-144814.32" wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $1\logical_op__oe__ok$next[0:0]$6924 - attribute \src "libresoc.v:144824.7-144824.32" + attribute \src "libresoc.v:144823.7-144823.32" wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $1\logical_op__output_carry$next[0:0]$6925 - attribute \src "libresoc.v:144833.7-144833.38" + attribute \src "libresoc.v:144832.7-144832.38" wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $1\logical_op__rc__ok$next[0:0]$6926 - attribute \src "libresoc.v:144842.7-144842.32" + attribute \src "libresoc.v:144841.7-144841.32" wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $1\logical_op__rc__rc$next[0:0]$6927 - attribute \src "libresoc.v:144851.7-144851.32" + attribute \src "libresoc.v:144850.7-144850.32" wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $1\logical_op__write_cr0$next[0:0]$6928 - attribute \src "libresoc.v:144860.7-144860.35" + attribute \src "libresoc.v:144859.7-144859.35" wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $1\logical_op__zero_a$next[0:0]$6929 - attribute \src "libresoc.v:144869.7-144869.32" + attribute \src "libresoc.v:144868.7-144868.32" wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:145386.3-145398.6" + attribute \src "libresoc.v:145385.3-145397.6" wire width 2 $1\muxid$next[1:0]$6892 - attribute \src "libresoc.v:145154.13-145154.25" + attribute \src "libresoc.v:145153.13-145153.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:145441.3-145459.6" + attribute \src "libresoc.v:145440.3-145458.6" wire width 64 $1\o$next[63:0]$6939 - attribute \src "libresoc.v:145169.14-145169.38" + attribute \src "libresoc.v:145168.14-145168.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:145441.3-145459.6" + attribute \src "libresoc.v:145440.3-145458.6" wire $1\o_ok$next[0:0]$6940 - attribute \src "libresoc.v:145176.7-145176.18" + attribute \src "libresoc.v:145175.7-145175.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:145368.3-145385.6" + attribute \src "libresoc.v:145367.3-145384.6" wire $1\r_busy$next[0:0]$6888 - attribute \src "libresoc.v:145190.7-145190.20" + attribute \src "libresoc.v:145189.7-145189.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:145479.3-145497.6" + attribute \src "libresoc.v:145478.3-145496.6" wire $1\xer_so$next[0:0]$6951 - attribute \src "libresoc.v:145199.7-145199.20" + attribute \src "libresoc.v:145198.7-145198.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:145479.3-145497.6" + attribute \src "libresoc.v:145478.3-145496.6" wire $1\xer_so_ok$next[0:0]$6952 - attribute \src "libresoc.v:145208.7-145208.23" + attribute \src "libresoc.v:145207.7-145207.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:145460.3-145478.6" + attribute \src "libresoc.v:145459.3-145477.6" wire $2\cr_a_ok$next[0:0]$6947 - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire width 64 $2\logical_op__imm_data__data$next[63:0]$6930 - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $2\logical_op__imm_data__ok$next[0:0]$6931 - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $2\logical_op__oe__oe$next[0:0]$6932 - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $2\logical_op__oe__ok$next[0:0]$6933 - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $2\logical_op__rc__ok$next[0:0]$6934 - attribute \src "libresoc.v:145399.3-145440.6" + attribute \src "libresoc.v:145398.3-145439.6" wire $2\logical_op__rc__rc$next[0:0]$6935 - attribute \src "libresoc.v:145441.3-145459.6" + attribute \src "libresoc.v:145440.3-145458.6" wire $2\o_ok$next[0:0]$6941 - attribute \src "libresoc.v:145368.3-145385.6" + attribute \src "libresoc.v:145367.3-145384.6" wire $2\r_busy$next[0:0]$6889 - attribute \src "libresoc.v:145479.3-145497.6" + attribute \src "libresoc.v:145478.3-145496.6" wire $2\xer_so_ok$next[0:0]$6953 - attribute \src "libresoc.v:145215.18-145215.118" - wire $and$libresoc.v:145215$6859_Y + attribute \src "libresoc.v:145214.18-145214.118" + wire $and$libresoc.v:145214$6859_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" @@ -235326,7 +235326,7 @@ module \logical_pipe1 wire \cr_a_ok$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:144131.7-144131.15" + attribute \src "libresoc.v:144130.7-144130.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len @@ -236365,7 +236365,7 @@ module \logical_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:145215$6859 + cell $and $and$libresoc.v:145214$6859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236373,10 +236373,10 @@ module \logical_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$63 connect \B \p_ready_o - connect \Y $and$libresoc.v:145215$6859_Y + connect \Y $and$libresoc.v:145214$6859_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:145268.14-145313.4" + attribute \src "libresoc.v:145267.14-145312.4" cell \input$50 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$38 @@ -236424,7 +236424,7 @@ module \logical_pipe1 connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:145314.13-145359.4" + attribute \src "libresoc.v:145313.13-145358.4" cell \main$51 \main connect \logical_op__data_len \main_logical_op__data_len connect \logical_op__data_len$18 \main_logical_op__data_len$60 @@ -236472,424 +236472,424 @@ module \logical_pipe1 connect \xer_so$20 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:145360.10-145363.4" + attribute \src "libresoc.v:145359.10-145362.4" cell \n$49 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:145364.10-145367.4" + attribute \src "libresoc.v:145363.10-145366.4" cell \p$48 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:144131.7-144131.20" - process $proc$libresoc.v:144131$6954 + attribute \src "libresoc.v:144130.7-144130.20" + process $proc$libresoc.v:144130$6954 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:144140.13-144140.24" - process $proc$libresoc.v:144140$6955 + attribute \src "libresoc.v:144139.13-144139.24" + process $proc$libresoc.v:144139$6955 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:144149.7-144149.21" - process $proc$libresoc.v:144149$6956 + attribute \src "libresoc.v:144148.7-144148.21" + process $proc$libresoc.v:144148$6956 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:144434.13-144434.40" - process $proc$libresoc.v:144434$6957 + attribute \src "libresoc.v:144433.13-144433.40" + process $proc$libresoc.v:144433$6957 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:144458.14-144458.44" - process $proc$libresoc.v:144458$6958 + attribute \src "libresoc.v:144457.14-144457.44" + process $proc$libresoc.v:144457$6958 assign { } { } assign $1\logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:144497.14-144497.63" - process $proc$libresoc.v:144497$6959 + attribute \src "libresoc.v:144496.14-144496.63" + process $proc$libresoc.v:144496$6959 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:144506.7-144506.38" - process $proc$libresoc.v:144506$6960 + attribute \src "libresoc.v:144505.7-144505.38" + process $proc$libresoc.v:144505$6960 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:144519.13-144519.43" - process $proc$libresoc.v:144519$6961 + attribute \src "libresoc.v:144518.13-144518.43" + process $proc$libresoc.v:144518$6961 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:144536.14-144536.38" - process $proc$libresoc.v:144536$6962 + attribute \src "libresoc.v:144535.14-144535.38" + process $proc$libresoc.v:144535$6962 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:144620.13-144620.42" - process $proc$libresoc.v:144620$6963 + attribute \src "libresoc.v:144619.13-144619.42" + process $proc$libresoc.v:144619$6963 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:144779.7-144779.35" - process $proc$libresoc.v:144779$6964 + attribute \src "libresoc.v:144778.7-144778.35" + process $proc$libresoc.v:144778$6964 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:144788.7-144788.36" - process $proc$libresoc.v:144788$6965 + attribute \src "libresoc.v:144787.7-144787.36" + process $proc$libresoc.v:144787$6965 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:144797.7-144797.34" - process $proc$libresoc.v:144797$6966 + attribute \src "libresoc.v:144796.7-144796.34" + process $proc$libresoc.v:144796$6966 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:144806.7-144806.35" - process $proc$libresoc.v:144806$6967 + attribute \src "libresoc.v:144805.7-144805.35" + process $proc$libresoc.v:144805$6967 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:144815.7-144815.32" - process $proc$libresoc.v:144815$6968 + attribute \src "libresoc.v:144814.7-144814.32" + process $proc$libresoc.v:144814$6968 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:144824.7-144824.32" - process $proc$libresoc.v:144824$6969 + attribute \src "libresoc.v:144823.7-144823.32" + process $proc$libresoc.v:144823$6969 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:144833.7-144833.38" - process $proc$libresoc.v:144833$6970 + attribute \src "libresoc.v:144832.7-144832.38" + process $proc$libresoc.v:144832$6970 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:144842.7-144842.32" - process $proc$libresoc.v:144842$6971 + attribute \src "libresoc.v:144841.7-144841.32" + process $proc$libresoc.v:144841$6971 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:144851.7-144851.32" - process $proc$libresoc.v:144851$6972 + attribute \src "libresoc.v:144850.7-144850.32" + process $proc$libresoc.v:144850$6972 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:144860.7-144860.35" - process $proc$libresoc.v:144860$6973 + attribute \src "libresoc.v:144859.7-144859.35" + process $proc$libresoc.v:144859$6973 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:144869.7-144869.32" - process $proc$libresoc.v:144869$6974 + attribute \src "libresoc.v:144868.7-144868.32" + process $proc$libresoc.v:144868$6974 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:145154.13-145154.25" - process $proc$libresoc.v:145154$6975 + attribute \src "libresoc.v:145153.13-145153.25" + process $proc$libresoc.v:145153$6975 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:145169.14-145169.38" - process $proc$libresoc.v:145169$6976 + attribute \src "libresoc.v:145168.14-145168.38" + process $proc$libresoc.v:145168$6976 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:145176.7-145176.18" - process $proc$libresoc.v:145176$6977 + attribute \src "libresoc.v:145175.7-145175.18" + process $proc$libresoc.v:145175$6977 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:145190.7-145190.20" - process $proc$libresoc.v:145190$6978 + attribute \src "libresoc.v:145189.7-145189.20" + process $proc$libresoc.v:145189$6978 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:145199.7-145199.20" - process $proc$libresoc.v:145199$6979 + attribute \src "libresoc.v:145198.7-145198.20" + process $proc$libresoc.v:145198$6979 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:145208.7-145208.23" - process $proc$libresoc.v:145208$6980 + attribute \src "libresoc.v:145207.7-145207.23" + process $proc$libresoc.v:145207$6980 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:145216.3-145217.29" - process $proc$libresoc.v:145216$6860 + attribute \src "libresoc.v:145215.3-145216.29" + process $proc$libresoc.v:145215$6860 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:145218.3-145219.35" - process $proc$libresoc.v:145218$6861 + attribute \src "libresoc.v:145217.3-145218.35" + process $proc$libresoc.v:145217$6861 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:145220.3-145221.25" - process $proc$libresoc.v:145220$6862 + attribute \src "libresoc.v:145219.3-145220.25" + process $proc$libresoc.v:145219$6862 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:145222.3-145223.31" - process $proc$libresoc.v:145222$6863 + attribute \src "libresoc.v:145221.3-145222.31" + process $proc$libresoc.v:145221$6863 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:145224.3-145225.19" - process $proc$libresoc.v:145224$6864 + attribute \src "libresoc.v:145223.3-145224.19" + process $proc$libresoc.v:145223$6864 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:145226.3-145227.25" - process $proc$libresoc.v:145226$6865 + attribute \src "libresoc.v:145225.3-145226.25" + process $proc$libresoc.v:145225$6865 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:145228.3-145229.59" - process $proc$libresoc.v:145228$6866 + attribute \src "libresoc.v:145227.3-145228.59" + process $proc$libresoc.v:145227$6866 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:145230.3-145231.55" - process $proc$libresoc.v:145230$6867 + attribute \src "libresoc.v:145229.3-145230.55" + process $proc$libresoc.v:145229$6867 assign { } { } assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next sync posedge \coresync_clk update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:145232.3-145233.69" - process $proc$libresoc.v:145232$6868 + attribute \src "libresoc.v:145231.3-145232.69" + process $proc$libresoc.v:145231$6868 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:145234.3-145235.65" - process $proc$libresoc.v:145234$6869 + attribute \src "libresoc.v:145233.3-145234.65" + process $proc$libresoc.v:145233$6869 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:145236.3-145237.53" - process $proc$libresoc.v:145236$6870 + attribute \src "libresoc.v:145235.3-145236.53" + process $proc$libresoc.v:145235$6870 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:145238.3-145239.53" - process $proc$libresoc.v:145238$6871 + attribute \src "libresoc.v:145237.3-145238.53" + process $proc$libresoc.v:145237$6871 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:145240.3-145241.53" - process $proc$libresoc.v:145240$6872 + attribute \src "libresoc.v:145239.3-145240.53" + process $proc$libresoc.v:145239$6872 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:145242.3-145243.53" - process $proc$libresoc.v:145242$6873 + attribute \src "libresoc.v:145241.3-145242.53" + process $proc$libresoc.v:145241$6873 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:145244.3-145245.59" - process $proc$libresoc.v:145244$6874 + attribute \src "libresoc.v:145243.3-145244.59" + process $proc$libresoc.v:145243$6874 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:145246.3-145247.53" - process $proc$libresoc.v:145246$6875 + attribute \src "libresoc.v:145245.3-145246.53" + process $proc$libresoc.v:145245$6875 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:145248.3-145249.63" - process $proc$libresoc.v:145248$6876 + attribute \src "libresoc.v:145247.3-145248.63" + process $proc$libresoc.v:145247$6876 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:145250.3-145251.61" - process $proc$libresoc.v:145250$6877 + attribute \src "libresoc.v:145249.3-145250.61" + process $proc$libresoc.v:145249$6877 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:145252.3-145253.59" - process $proc$libresoc.v:145252$6878 + attribute \src "libresoc.v:145251.3-145252.59" + process $proc$libresoc.v:145251$6878 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:145254.3-145255.65" - process $proc$libresoc.v:145254$6879 + attribute \src "libresoc.v:145253.3-145254.65" + process $proc$libresoc.v:145253$6879 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:145256.3-145257.57" - process $proc$libresoc.v:145256$6880 + attribute \src "libresoc.v:145255.3-145256.57" + process $proc$libresoc.v:145255$6880 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:145258.3-145259.59" - process $proc$libresoc.v:145258$6881 + attribute \src "libresoc.v:145257.3-145258.59" + process $proc$libresoc.v:145257$6881 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:145260.3-145261.57" - process $proc$libresoc.v:145260$6882 + attribute \src "libresoc.v:145259.3-145260.57" + process $proc$libresoc.v:145259$6882 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:145262.3-145263.49" - process $proc$libresoc.v:145262$6883 + attribute \src "libresoc.v:145261.3-145262.49" + process $proc$libresoc.v:145261$6883 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:145264.3-145265.27" - process $proc$libresoc.v:145264$6884 + attribute \src "libresoc.v:145263.3-145264.27" + process $proc$libresoc.v:145263$6884 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:145266.3-145267.29" - process $proc$libresoc.v:145266$6885 + attribute \src "libresoc.v:145265.3-145266.29" + process $proc$libresoc.v:145265$6885 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:145368.3-145385.6" - process $proc$libresoc.v:145368$6886 + attribute \src "libresoc.v:145367.3-145384.6" + process $proc$libresoc.v:145367$6886 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$6887 $2\r_busy$next[0:0]$6889 - attribute \src "libresoc.v:145369.5-145369.29" + attribute \src "libresoc.v:145368.5-145368.29" switch \initial - attribute \src "libresoc.v:145369.9-145369.17" + attribute \src "libresoc.v:145368.9-145368.17" case 1'1 case end @@ -236918,14 +236918,14 @@ module \logical_pipe1 sync always update \r_busy$next $0\r_busy$next[0:0]$6887 end - attribute \src "libresoc.v:145386.3-145398.6" - process $proc$libresoc.v:145386$6890 + attribute \src "libresoc.v:145385.3-145397.6" + process $proc$libresoc.v:145385$6890 assign { } { } assign { } { } assign $0\muxid$next[1:0]$6891 $1\muxid$next[1:0]$6892 - attribute \src "libresoc.v:145387.5-145387.29" + attribute \src "libresoc.v:145386.5-145386.29" switch \initial - attribute \src "libresoc.v:145387.9-145387.17" + attribute \src "libresoc.v:145386.9-145386.17" case 1'1 case end @@ -236945,8 +236945,8 @@ module \logical_pipe1 sync always update \muxid$next $0\muxid$next[1:0]$6891 end - attribute \src "libresoc.v:145399.3-145440.6" - process $proc$libresoc.v:145399$6893 + attribute \src "libresoc.v:145398.3-145439.6" + process $proc$libresoc.v:145398$6893 assign { } { } assign { } { } assign { } { } @@ -237007,9 +237007,9 @@ module \logical_pipe1 assign $0\logical_op__oe__ok$next[0:0]$6906 $2\logical_op__oe__ok$next[0:0]$6933 assign $0\logical_op__rc__ok$next[0:0]$6908 $2\logical_op__rc__ok$next[0:0]$6934 assign $0\logical_op__rc__rc$next[0:0]$6909 $2\logical_op__rc__rc$next[0:0]$6935 - attribute \src "libresoc.v:145400.5-145400.29" + attribute \src "libresoc.v:145399.5-145399.29" switch \initial - attribute \src "libresoc.v:145400.9-145400.17" + attribute \src "libresoc.v:145399.9-145399.17" case 1'1 case end @@ -237121,8 +237121,8 @@ module \logical_pipe1 update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6910 update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6911 end - attribute \src "libresoc.v:145441.3-145459.6" - process $proc$libresoc.v:145441$6936 + attribute \src "libresoc.v:145440.3-145458.6" + process $proc$libresoc.v:145440$6936 assign { } { } assign { } { } assign { } { } @@ -237130,9 +237130,9 @@ module \logical_pipe1 assign $0\o$next[63:0]$6937 $1\o$next[63:0]$6939 assign { } { } assign $0\o_ok$next[0:0]$6938 $2\o_ok$next[0:0]$6941 - attribute \src "libresoc.v:145442.5-145442.29" + attribute \src "libresoc.v:145441.5-145441.29" switch \initial - attribute \src "libresoc.v:145442.9-145442.17" + attribute \src "libresoc.v:145441.9-145441.17" case 1'1 case end @@ -237165,8 +237165,8 @@ module \logical_pipe1 update \o$next $0\o$next[63:0]$6937 update \o_ok$next $0\o_ok$next[0:0]$6938 end - attribute \src "libresoc.v:145460.3-145478.6" - process $proc$libresoc.v:145460$6942 + attribute \src "libresoc.v:145459.3-145477.6" + process $proc$libresoc.v:145459$6942 assign { } { } assign { } { } assign { } { } @@ -237174,9 +237174,9 @@ module \logical_pipe1 assign $0\cr_a$next[3:0]$6943 $1\cr_a$next[3:0]$6945 assign { } { } assign $0\cr_a_ok$next[0:0]$6944 $2\cr_a_ok$next[0:0]$6947 - attribute \src "libresoc.v:145461.5-145461.29" + attribute \src "libresoc.v:145460.5-145460.29" switch \initial - attribute \src "libresoc.v:145461.9-145461.17" + attribute \src "libresoc.v:145460.9-145460.17" case 1'1 case end @@ -237209,8 +237209,8 @@ module \logical_pipe1 update \cr_a$next $0\cr_a$next[3:0]$6943 update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6944 end - attribute \src "libresoc.v:145479.3-145497.6" - process $proc$libresoc.v:145479$6948 + attribute \src "libresoc.v:145478.3-145496.6" + process $proc$libresoc.v:145478$6948 assign { } { } assign { } { } assign { } { } @@ -237218,9 +237218,9 @@ module \logical_pipe1 assign $0\xer_so$next[0:0]$6949 $1\xer_so$next[0:0]$6951 assign { } { } assign $0\xer_so_ok$next[0:0]$6950 $2\xer_so_ok$next[0:0]$6953 - attribute \src "libresoc.v:145480.5-145480.29" + attribute \src "libresoc.v:145479.5-145479.29" switch \initial - attribute \src "libresoc.v:145480.9-145480.17" + attribute \src "libresoc.v:145479.9-145479.17" case 1'1 case end @@ -237253,7 +237253,7 @@ module \logical_pipe1 update \xer_so$next $0\xer_so$next[0:0]$6949 update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6950 end - connect \$64 $and$libresoc.v:145215$6859_Y + connect \$64 $and$libresoc.v:145214$6859_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 @@ -237278,225 +237278,225 @@ module \logical_pipe1 connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:145525.1-146558.10" +attribute \src "libresoc.v:145524.1-146557.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" attribute \generator "nMigen" module \logical_pipe2 - attribute \src "libresoc.v:146525.3-146543.6" + attribute \src "libresoc.v:146524.3-146542.6" wire width 4 $0\cr_a$22$next[3:0]$7086 - attribute \src "libresoc.v:146329.3-146330.33" + attribute \src "libresoc.v:146328.3-146329.33" wire width 4 $0\cr_a$22[3:0]$6983 - attribute \src "libresoc.v:145537.13-145537.29" + attribute \src "libresoc.v:145536.13-145536.29" wire width 4 $0\cr_a$22[3:0]$7093 - attribute \src "libresoc.v:146525.3-146543.6" + attribute \src "libresoc.v:146524.3-146542.6" wire $0\cr_a_ok$23$next[0:0]$7087 - attribute \src "libresoc.v:146331.3-146332.39" + attribute \src "libresoc.v:146330.3-146331.39" wire $0\cr_a_ok$23[0:0]$6985 - attribute \src "libresoc.v:145546.7-145546.26" + attribute \src "libresoc.v:145545.7-145545.26" wire $0\cr_a_ok$23[0:0]$7095 - attribute \src "libresoc.v:145526.7-145526.20" + attribute \src "libresoc.v:145525.7-145525.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire width 4 $0\logical_op__data_len$18$next[3:0]$7037 - attribute \src "libresoc.v:146369.3-146370.65" + attribute \src "libresoc.v:146368.3-146369.65" wire width 4 $0\logical_op__data_len$18[3:0]$7023 - attribute \src "libresoc.v:145557.13-145557.45" + attribute \src "libresoc.v:145556.13-145556.45" wire width 4 $0\logical_op__data_len$18[3:0]$7097 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire width 14 $0\logical_op__fn_unit$3$next[13:0]$7038 - attribute \src "libresoc.v:146339.3-146340.61" + attribute \src "libresoc.v:146338.3-146339.61" wire width 14 $0\logical_op__fn_unit$3[13:0]$6993 - attribute \src "libresoc.v:145596.14-145596.48" + attribute \src "libresoc.v:145595.14-145595.48" wire width 14 $0\logical_op__fn_unit$3[13:0]$7099 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$7039 - attribute \src "libresoc.v:146341.3-146342.75" + attribute \src "libresoc.v:146340.3-146341.75" wire width 64 $0\logical_op__imm_data__data$4[63:0]$6995 - attribute \src "libresoc.v:145620.14-145620.67" + attribute \src "libresoc.v:145619.14-145619.67" wire width 64 $0\logical_op__imm_data__data$4[63:0]$7101 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $0\logical_op__imm_data__ok$5$next[0:0]$7040 - attribute \src "libresoc.v:146343.3-146344.71" + attribute \src "libresoc.v:146342.3-146343.71" wire $0\logical_op__imm_data__ok$5[0:0]$6997 - attribute \src "libresoc.v:145629.7-145629.42" + attribute \src "libresoc.v:145628.7-145628.42" wire $0\logical_op__imm_data__ok$5[0:0]$7103 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire width 2 $0\logical_op__input_carry$12$next[1:0]$7041 - attribute \src "libresoc.v:146357.3-146358.71" + attribute \src "libresoc.v:146356.3-146357.71" wire width 2 $0\logical_op__input_carry$12[1:0]$7011 - attribute \src "libresoc.v:145646.13-145646.48" + attribute \src "libresoc.v:145645.13-145645.48" wire width 2 $0\logical_op__input_carry$12[1:0]$7105 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire width 32 $0\logical_op__insn$19$next[31:0]$7042 - attribute \src "libresoc.v:146371.3-146372.57" + attribute \src "libresoc.v:146370.3-146371.57" wire width 32 $0\logical_op__insn$19[31:0]$7025 - attribute \src "libresoc.v:145659.14-145659.43" + attribute \src "libresoc.v:145658.14-145658.43" wire width 32 $0\logical_op__insn$19[31:0]$7107 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire width 7 $0\logical_op__insn_type$2$next[6:0]$7043 - attribute \src "libresoc.v:146337.3-146338.65" + attribute \src "libresoc.v:146336.3-146337.65" wire width 7 $0\logical_op__insn_type$2[6:0]$6991 - attribute \src "libresoc.v:145818.13-145818.46" + attribute \src "libresoc.v:145817.13-145817.46" wire width 7 $0\logical_op__insn_type$2[6:0]$7109 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $0\logical_op__invert_in$10$next[0:0]$7044 - attribute \src "libresoc.v:146353.3-146354.67" + attribute \src "libresoc.v:146352.3-146353.67" wire $0\logical_op__invert_in$10[0:0]$7007 - attribute \src "libresoc.v:145902.7-145902.40" + attribute \src "libresoc.v:145901.7-145901.40" wire $0\logical_op__invert_in$10[0:0]$7111 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $0\logical_op__invert_out$13$next[0:0]$7045 - attribute \src "libresoc.v:146359.3-146360.69" + attribute \src "libresoc.v:146358.3-146359.69" wire $0\logical_op__invert_out$13[0:0]$7013 - attribute \src "libresoc.v:145911.7-145911.41" + attribute \src "libresoc.v:145910.7-145910.41" wire $0\logical_op__invert_out$13[0:0]$7113 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $0\logical_op__is_32bit$16$next[0:0]$7046 - attribute \src "libresoc.v:146365.3-146366.65" + attribute \src "libresoc.v:146364.3-146365.65" wire $0\logical_op__is_32bit$16[0:0]$7019 - attribute \src "libresoc.v:145920.7-145920.39" + attribute \src "libresoc.v:145919.7-145919.39" wire $0\logical_op__is_32bit$16[0:0]$7115 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $0\logical_op__is_signed$17$next[0:0]$7047 - attribute \src "libresoc.v:146367.3-146368.67" + attribute \src "libresoc.v:146366.3-146367.67" wire $0\logical_op__is_signed$17[0:0]$7021 - attribute \src "libresoc.v:145929.7-145929.40" + attribute \src "libresoc.v:145928.7-145928.40" wire $0\logical_op__is_signed$17[0:0]$7117 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $0\logical_op__oe__oe$8$next[0:0]$7048 - attribute \src "libresoc.v:146349.3-146350.59" + attribute \src "libresoc.v:146348.3-146349.59" wire $0\logical_op__oe__oe$8[0:0]$7003 - attribute \src "libresoc.v:145940.7-145940.36" + attribute \src "libresoc.v:145939.7-145939.36" wire $0\logical_op__oe__oe$8[0:0]$7119 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $0\logical_op__oe__ok$9$next[0:0]$7049 - attribute \src "libresoc.v:146351.3-146352.59" + attribute \src "libresoc.v:146350.3-146351.59" wire $0\logical_op__oe__ok$9[0:0]$7005 - attribute \src "libresoc.v:145949.7-145949.36" + attribute \src "libresoc.v:145948.7-145948.36" wire $0\logical_op__oe__ok$9[0:0]$7121 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $0\logical_op__output_carry$15$next[0:0]$7050 - attribute \src "libresoc.v:146363.3-146364.73" + attribute \src "libresoc.v:146362.3-146363.73" wire $0\logical_op__output_carry$15[0:0]$7017 - attribute \src "libresoc.v:145956.7-145956.43" + attribute \src "libresoc.v:145955.7-145955.43" wire $0\logical_op__output_carry$15[0:0]$7123 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $0\logical_op__rc__ok$7$next[0:0]$7051 - attribute \src "libresoc.v:146347.3-146348.59" + attribute \src "libresoc.v:146346.3-146347.59" wire $0\logical_op__rc__ok$7[0:0]$7001 - attribute \src "libresoc.v:145967.7-145967.36" + attribute \src "libresoc.v:145966.7-145966.36" wire $0\logical_op__rc__ok$7[0:0]$7125 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $0\logical_op__rc__rc$6$next[0:0]$7052 - attribute \src "libresoc.v:146345.3-146346.59" + attribute \src "libresoc.v:146344.3-146345.59" wire $0\logical_op__rc__rc$6[0:0]$6999 - attribute \src "libresoc.v:145976.7-145976.36" + attribute \src "libresoc.v:145975.7-145975.36" wire $0\logical_op__rc__rc$6[0:0]$7127 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $0\logical_op__write_cr0$14$next[0:0]$7053 - attribute \src "libresoc.v:146361.3-146362.67" + attribute \src "libresoc.v:146360.3-146361.67" wire $0\logical_op__write_cr0$14[0:0]$7015 - attribute \src "libresoc.v:145983.7-145983.40" + attribute \src "libresoc.v:145982.7-145982.40" wire $0\logical_op__write_cr0$14[0:0]$7129 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $0\logical_op__zero_a$11$next[0:0]$7054 - attribute \src "libresoc.v:146355.3-146356.61" + attribute \src "libresoc.v:146354.3-146355.61" wire $0\logical_op__zero_a$11[0:0]$7009 - attribute \src "libresoc.v:145992.7-145992.37" + attribute \src "libresoc.v:145991.7-145991.37" wire $0\logical_op__zero_a$11[0:0]$7131 - attribute \src "libresoc.v:146451.3-146463.6" + attribute \src "libresoc.v:146450.3-146462.6" wire width 2 $0\muxid$1$next[1:0]$7034 - attribute \src "libresoc.v:146373.3-146374.33" + attribute \src "libresoc.v:146372.3-146373.33" wire width 2 $0\muxid$1[1:0]$7027 - attribute \src "libresoc.v:146001.13-146001.29" + attribute \src "libresoc.v:146000.13-146000.29" wire width 2 $0\muxid$1[1:0]$7133 - attribute \src "libresoc.v:146506.3-146524.6" + attribute \src "libresoc.v:146505.3-146523.6" wire width 64 $0\o$20$next[63:0]$7080 - attribute \src "libresoc.v:146333.3-146334.27" + attribute \src "libresoc.v:146332.3-146333.27" wire width 64 $0\o$20[63:0]$6987 - attribute \src "libresoc.v:146016.14-146016.43" + attribute \src "libresoc.v:146015.14-146015.43" wire width 64 $0\o$20[63:0]$7135 - attribute \src "libresoc.v:146506.3-146524.6" + attribute \src "libresoc.v:146505.3-146523.6" wire $0\o_ok$21$next[0:0]$7081 - attribute \src "libresoc.v:146335.3-146336.33" + attribute \src "libresoc.v:146334.3-146335.33" wire $0\o_ok$21[0:0]$6989 - attribute \src "libresoc.v:146025.7-146025.23" + attribute \src "libresoc.v:146024.7-146024.23" wire $0\o_ok$21[0:0]$7137 - attribute \src "libresoc.v:146433.3-146450.6" + attribute \src "libresoc.v:146432.3-146449.6" wire $0\r_busy$next[0:0]$7030 - attribute \src "libresoc.v:146375.3-146376.29" + attribute \src "libresoc.v:146374.3-146375.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:146525.3-146543.6" + attribute \src "libresoc.v:146524.3-146542.6" wire width 4 $1\cr_a$22$next[3:0]$7088 - attribute \src "libresoc.v:146525.3-146543.6" + attribute \src "libresoc.v:146524.3-146542.6" wire $1\cr_a_ok$23$next[0:0]$7089 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire width 4 $1\logical_op__data_len$18$next[3:0]$7055 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire width 14 $1\logical_op__fn_unit$3$next[13:0]$7056 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$7057 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $1\logical_op__imm_data__ok$5$next[0:0]$7058 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire width 2 $1\logical_op__input_carry$12$next[1:0]$7059 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire width 32 $1\logical_op__insn$19$next[31:0]$7060 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire width 7 $1\logical_op__insn_type$2$next[6:0]$7061 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $1\logical_op__invert_in$10$next[0:0]$7062 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $1\logical_op__invert_out$13$next[0:0]$7063 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $1\logical_op__is_32bit$16$next[0:0]$7064 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $1\logical_op__is_signed$17$next[0:0]$7065 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $1\logical_op__oe__oe$8$next[0:0]$7066 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $1\logical_op__oe__ok$9$next[0:0]$7067 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $1\logical_op__output_carry$15$next[0:0]$7068 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $1\logical_op__rc__ok$7$next[0:0]$7069 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $1\logical_op__rc__rc$6$next[0:0]$7070 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $1\logical_op__write_cr0$14$next[0:0]$7071 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $1\logical_op__zero_a$11$next[0:0]$7072 - attribute \src "libresoc.v:146451.3-146463.6" + attribute \src "libresoc.v:146450.3-146462.6" wire width 2 $1\muxid$1$next[1:0]$7035 - attribute \src "libresoc.v:146506.3-146524.6" + attribute \src "libresoc.v:146505.3-146523.6" wire width 64 $1\o$20$next[63:0]$7082 - attribute \src "libresoc.v:146506.3-146524.6" + attribute \src "libresoc.v:146505.3-146523.6" wire $1\o_ok$21$next[0:0]$7083 - attribute \src "libresoc.v:146433.3-146450.6" + attribute \src "libresoc.v:146432.3-146449.6" wire $1\r_busy$next[0:0]$7031 - attribute \src "libresoc.v:146319.7-146319.20" + attribute \src "libresoc.v:146318.7-146318.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:146525.3-146543.6" + attribute \src "libresoc.v:146524.3-146542.6" wire $2\cr_a_ok$23$next[0:0]$7090 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7073 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $2\logical_op__imm_data__ok$5$next[0:0]$7074 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $2\logical_op__oe__oe$8$next[0:0]$7075 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $2\logical_op__oe__ok$9$next[0:0]$7076 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $2\logical_op__rc__ok$7$next[0:0]$7077 - attribute \src "libresoc.v:146464.3-146505.6" + attribute \src "libresoc.v:146463.3-146504.6" wire $2\logical_op__rc__rc$6$next[0:0]$7078 - attribute \src "libresoc.v:146506.3-146524.6" + attribute \src "libresoc.v:146505.3-146523.6" wire $2\o_ok$21$next[0:0]$7084 - attribute \src "libresoc.v:146433.3-146450.6" + attribute \src "libresoc.v:146432.3-146449.6" wire $2\r_busy$next[0:0]$7032 - attribute \src "libresoc.v:146328.18-146328.118" - wire $and$libresoc.v:146328$6981_Y + attribute \src "libresoc.v:146327.18-146327.118" + wire $and$libresoc.v:146327$6981_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$49 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" @@ -237521,7 +237521,7 @@ module \logical_pipe2 wire \cr_a_ok$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$73 - attribute \src "libresoc.v:145526.7-145526.15" + attribute \src "libresoc.v:145525.7-145525.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -238278,7 +238278,7 @@ module \logical_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:146328$6981 + cell $and $and$libresoc.v:146327$6981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238286,16 +238286,16 @@ module \logical_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$48 connect \B \p_ready_o - connect \Y $and$libresoc.v:146328$6981_Y + connect \Y $and$libresoc.v:146327$6981_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:146377.10-146380.4" + attribute \src "libresoc.v:146376.10-146379.4" cell \n$53 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:146381.15-146428.4" + attribute \src "libresoc.v:146380.15-146427.4" cell \output$54 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$45 @@ -238345,388 +238345,388 @@ module \logical_pipe2 connect \xer_so \output_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:146429.10-146432.4" + attribute \src "libresoc.v:146428.10-146431.4" cell \p$52 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:145526.7-145526.20" - process $proc$libresoc.v:145526$7091 + attribute \src "libresoc.v:145525.7-145525.20" + process $proc$libresoc.v:145525$7091 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:145537.13-145537.29" - process $proc$libresoc.v:145537$7092 + attribute \src "libresoc.v:145536.13-145536.29" + process $proc$libresoc.v:145536$7092 assign { } { } assign $0\cr_a$22[3:0]$7093 4'0000 sync always sync init update \cr_a$22 $0\cr_a$22[3:0]$7093 end - attribute \src "libresoc.v:145546.7-145546.26" - process $proc$libresoc.v:145546$7094 + attribute \src "libresoc.v:145545.7-145545.26" + process $proc$libresoc.v:145545$7094 assign { } { } assign $0\cr_a_ok$23[0:0]$7095 1'0 sync always sync init update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7095 end - attribute \src "libresoc.v:145557.13-145557.45" - process $proc$libresoc.v:145557$7096 + attribute \src "libresoc.v:145556.13-145556.45" + process $proc$libresoc.v:145556$7096 assign { } { } assign $0\logical_op__data_len$18[3:0]$7097 4'0000 sync always sync init update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7097 end - attribute \src "libresoc.v:145596.14-145596.48" - process $proc$libresoc.v:145596$7098 + attribute \src "libresoc.v:145595.14-145595.48" + process $proc$libresoc.v:145595$7098 assign { } { } assign $0\logical_op__fn_unit$3[13:0]$7099 14'00000000000000 sync always sync init update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$7099 end - attribute \src "libresoc.v:145620.14-145620.67" - process $proc$libresoc.v:145620$7100 + attribute \src "libresoc.v:145619.14-145619.67" + process $proc$libresoc.v:145619$7100 assign { } { } assign $0\logical_op__imm_data__data$4[63:0]$7101 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7101 end - attribute \src "libresoc.v:145629.7-145629.42" - process $proc$libresoc.v:145629$7102 + attribute \src "libresoc.v:145628.7-145628.42" + process $proc$libresoc.v:145628$7102 assign { } { } assign $0\logical_op__imm_data__ok$5[0:0]$7103 1'0 sync always sync init update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7103 end - attribute \src "libresoc.v:145646.13-145646.48" - process $proc$libresoc.v:145646$7104 + attribute \src "libresoc.v:145645.13-145645.48" + process $proc$libresoc.v:145645$7104 assign { } { } assign $0\logical_op__input_carry$12[1:0]$7105 2'00 sync always sync init update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7105 end - attribute \src "libresoc.v:145659.14-145659.43" - process $proc$libresoc.v:145659$7106 + attribute \src "libresoc.v:145658.14-145658.43" + process $proc$libresoc.v:145658$7106 assign { } { } assign $0\logical_op__insn$19[31:0]$7107 0 sync always sync init update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7107 end - attribute \src "libresoc.v:145818.13-145818.46" - process $proc$libresoc.v:145818$7108 + attribute \src "libresoc.v:145817.13-145817.46" + process $proc$libresoc.v:145817$7108 assign { } { } assign $0\logical_op__insn_type$2[6:0]$7109 7'0000000 sync always sync init update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7109 end - attribute \src "libresoc.v:145902.7-145902.40" - process $proc$libresoc.v:145902$7110 + attribute \src "libresoc.v:145901.7-145901.40" + process $proc$libresoc.v:145901$7110 assign { } { } assign $0\logical_op__invert_in$10[0:0]$7111 1'0 sync always sync init update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7111 end - attribute \src "libresoc.v:145911.7-145911.41" - process $proc$libresoc.v:145911$7112 + attribute \src "libresoc.v:145910.7-145910.41" + process $proc$libresoc.v:145910$7112 assign { } { } assign $0\logical_op__invert_out$13[0:0]$7113 1'0 sync always sync init update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7113 end - attribute \src "libresoc.v:145920.7-145920.39" - process $proc$libresoc.v:145920$7114 + attribute \src "libresoc.v:145919.7-145919.39" + process $proc$libresoc.v:145919$7114 assign { } { } assign $0\logical_op__is_32bit$16[0:0]$7115 1'0 sync always sync init update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7115 end - attribute \src "libresoc.v:145929.7-145929.40" - process $proc$libresoc.v:145929$7116 + attribute \src "libresoc.v:145928.7-145928.40" + process $proc$libresoc.v:145928$7116 assign { } { } assign $0\logical_op__is_signed$17[0:0]$7117 1'0 sync always sync init update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7117 end - attribute \src "libresoc.v:145940.7-145940.36" - process $proc$libresoc.v:145940$7118 + attribute \src "libresoc.v:145939.7-145939.36" + process $proc$libresoc.v:145939$7118 assign { } { } assign $0\logical_op__oe__oe$8[0:0]$7119 1'0 sync always sync init update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7119 end - attribute \src "libresoc.v:145949.7-145949.36" - process $proc$libresoc.v:145949$7120 + attribute \src "libresoc.v:145948.7-145948.36" + process $proc$libresoc.v:145948$7120 assign { } { } assign $0\logical_op__oe__ok$9[0:0]$7121 1'0 sync always sync init update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7121 end - attribute \src "libresoc.v:145956.7-145956.43" - process $proc$libresoc.v:145956$7122 + attribute \src "libresoc.v:145955.7-145955.43" + process $proc$libresoc.v:145955$7122 assign { } { } assign $0\logical_op__output_carry$15[0:0]$7123 1'0 sync always sync init update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7123 end - attribute \src "libresoc.v:145967.7-145967.36" - process $proc$libresoc.v:145967$7124 + attribute \src "libresoc.v:145966.7-145966.36" + process $proc$libresoc.v:145966$7124 assign { } { } assign $0\logical_op__rc__ok$7[0:0]$7125 1'0 sync always sync init update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7125 end - attribute \src "libresoc.v:145976.7-145976.36" - process $proc$libresoc.v:145976$7126 + attribute \src "libresoc.v:145975.7-145975.36" + process $proc$libresoc.v:145975$7126 assign { } { } assign $0\logical_op__rc__rc$6[0:0]$7127 1'0 sync always sync init update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7127 end - attribute \src "libresoc.v:145983.7-145983.40" - process $proc$libresoc.v:145983$7128 + attribute \src "libresoc.v:145982.7-145982.40" + process $proc$libresoc.v:145982$7128 assign { } { } assign $0\logical_op__write_cr0$14[0:0]$7129 1'0 sync always sync init update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7129 end - attribute \src "libresoc.v:145992.7-145992.37" - process $proc$libresoc.v:145992$7130 + attribute \src "libresoc.v:145991.7-145991.37" + process $proc$libresoc.v:145991$7130 assign { } { } assign $0\logical_op__zero_a$11[0:0]$7131 1'0 sync always sync init update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7131 end - attribute \src "libresoc.v:146001.13-146001.29" - process $proc$libresoc.v:146001$7132 + attribute \src "libresoc.v:146000.13-146000.29" + process $proc$libresoc.v:146000$7132 assign { } { } assign $0\muxid$1[1:0]$7133 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$7133 end - attribute \src "libresoc.v:146016.14-146016.43" - process $proc$libresoc.v:146016$7134 + attribute \src "libresoc.v:146015.14-146015.43" + process $proc$libresoc.v:146015$7134 assign { } { } assign $0\o$20[63:0]$7135 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o$20 $0\o$20[63:0]$7135 end - attribute \src "libresoc.v:146025.7-146025.23" - process $proc$libresoc.v:146025$7136 + attribute \src "libresoc.v:146024.7-146024.23" + process $proc$libresoc.v:146024$7136 assign { } { } assign $0\o_ok$21[0:0]$7137 1'0 sync always sync init update \o_ok$21 $0\o_ok$21[0:0]$7137 end - attribute \src "libresoc.v:146319.7-146319.20" - process $proc$libresoc.v:146319$7138 + attribute \src "libresoc.v:146318.7-146318.20" + process $proc$libresoc.v:146318$7138 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:146329.3-146330.33" - process $proc$libresoc.v:146329$6982 + attribute \src "libresoc.v:146328.3-146329.33" + process $proc$libresoc.v:146328$6982 assign { } { } assign $0\cr_a$22[3:0]$6983 \cr_a$22$next sync posedge \coresync_clk update \cr_a$22 $0\cr_a$22[3:0]$6983 end - attribute \src "libresoc.v:146331.3-146332.39" - process $proc$libresoc.v:146331$6984 + attribute \src "libresoc.v:146330.3-146331.39" + process $proc$libresoc.v:146330$6984 assign { } { } assign $0\cr_a_ok$23[0:0]$6985 \cr_a_ok$23$next sync posedge \coresync_clk update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6985 end - attribute \src "libresoc.v:146333.3-146334.27" - process $proc$libresoc.v:146333$6986 + attribute \src "libresoc.v:146332.3-146333.27" + process $proc$libresoc.v:146332$6986 assign { } { } assign $0\o$20[63:0]$6987 \o$20$next sync posedge \coresync_clk update \o$20 $0\o$20[63:0]$6987 end - attribute \src "libresoc.v:146335.3-146336.33" - process $proc$libresoc.v:146335$6988 + attribute \src "libresoc.v:146334.3-146335.33" + process $proc$libresoc.v:146334$6988 assign { } { } assign $0\o_ok$21[0:0]$6989 \o_ok$21$next sync posedge \coresync_clk update \o_ok$21 $0\o_ok$21[0:0]$6989 end - attribute \src "libresoc.v:146337.3-146338.65" - process $proc$libresoc.v:146337$6990 + attribute \src "libresoc.v:146336.3-146337.65" + process $proc$libresoc.v:146336$6990 assign { } { } assign $0\logical_op__insn_type$2[6:0]$6991 \logical_op__insn_type$2$next sync posedge \coresync_clk update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6991 end - attribute \src "libresoc.v:146339.3-146340.61" - process $proc$libresoc.v:146339$6992 + attribute \src "libresoc.v:146338.3-146339.61" + process $proc$libresoc.v:146338$6992 assign { } { } assign $0\logical_op__fn_unit$3[13:0]$6993 \logical_op__fn_unit$3$next sync posedge \coresync_clk update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$6993 end - attribute \src "libresoc.v:146341.3-146342.75" - process $proc$libresoc.v:146341$6994 + attribute \src "libresoc.v:146340.3-146341.75" + process $proc$libresoc.v:146340$6994 assign { } { } assign $0\logical_op__imm_data__data$4[63:0]$6995 \logical_op__imm_data__data$4$next sync posedge \coresync_clk update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6995 end - attribute \src "libresoc.v:146343.3-146344.71" - process $proc$libresoc.v:146343$6996 + attribute \src "libresoc.v:146342.3-146343.71" + process $proc$libresoc.v:146342$6996 assign { } { } assign $0\logical_op__imm_data__ok$5[0:0]$6997 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6997 end - attribute \src "libresoc.v:146345.3-146346.59" - process $proc$libresoc.v:146345$6998 + attribute \src "libresoc.v:146344.3-146345.59" + process $proc$libresoc.v:146344$6998 assign { } { } assign $0\logical_op__rc__rc$6[0:0]$6999 \logical_op__rc__rc$6$next sync posedge \coresync_clk update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6999 end - attribute \src "libresoc.v:146347.3-146348.59" - process $proc$libresoc.v:146347$7000 + attribute \src "libresoc.v:146346.3-146347.59" + process $proc$libresoc.v:146346$7000 assign { } { } assign $0\logical_op__rc__ok$7[0:0]$7001 \logical_op__rc__ok$7$next sync posedge \coresync_clk update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7001 end - attribute \src "libresoc.v:146349.3-146350.59" - process $proc$libresoc.v:146349$7002 + attribute \src "libresoc.v:146348.3-146349.59" + process $proc$libresoc.v:146348$7002 assign { } { } assign $0\logical_op__oe__oe$8[0:0]$7003 \logical_op__oe__oe$8$next sync posedge \coresync_clk update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7003 end - attribute \src "libresoc.v:146351.3-146352.59" - process $proc$libresoc.v:146351$7004 + attribute \src "libresoc.v:146350.3-146351.59" + process $proc$libresoc.v:146350$7004 assign { } { } assign $0\logical_op__oe__ok$9[0:0]$7005 \logical_op__oe__ok$9$next sync posedge \coresync_clk update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7005 end - attribute \src "libresoc.v:146353.3-146354.67" - process $proc$libresoc.v:146353$7006 + attribute \src "libresoc.v:146352.3-146353.67" + process $proc$libresoc.v:146352$7006 assign { } { } assign $0\logical_op__invert_in$10[0:0]$7007 \logical_op__invert_in$10$next sync posedge \coresync_clk update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7007 end - attribute \src "libresoc.v:146355.3-146356.61" - process $proc$libresoc.v:146355$7008 + attribute \src "libresoc.v:146354.3-146355.61" + process $proc$libresoc.v:146354$7008 assign { } { } assign $0\logical_op__zero_a$11[0:0]$7009 \logical_op__zero_a$11$next sync posedge \coresync_clk update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7009 end - attribute \src "libresoc.v:146357.3-146358.71" - process $proc$libresoc.v:146357$7010 + attribute \src "libresoc.v:146356.3-146357.71" + process $proc$libresoc.v:146356$7010 assign { } { } assign $0\logical_op__input_carry$12[1:0]$7011 \logical_op__input_carry$12$next sync posedge \coresync_clk update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7011 end - attribute \src "libresoc.v:146359.3-146360.69" - process $proc$libresoc.v:146359$7012 + attribute \src "libresoc.v:146358.3-146359.69" + process $proc$libresoc.v:146358$7012 assign { } { } assign $0\logical_op__invert_out$13[0:0]$7013 \logical_op__invert_out$13$next sync posedge \coresync_clk update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7013 end - attribute \src "libresoc.v:146361.3-146362.67" - process $proc$libresoc.v:146361$7014 + attribute \src "libresoc.v:146360.3-146361.67" + process $proc$libresoc.v:146360$7014 assign { } { } assign $0\logical_op__write_cr0$14[0:0]$7015 \logical_op__write_cr0$14$next sync posedge \coresync_clk update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7015 end - attribute \src "libresoc.v:146363.3-146364.73" - process $proc$libresoc.v:146363$7016 + attribute \src "libresoc.v:146362.3-146363.73" + process $proc$libresoc.v:146362$7016 assign { } { } assign $0\logical_op__output_carry$15[0:0]$7017 \logical_op__output_carry$15$next sync posedge \coresync_clk update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7017 end - attribute \src "libresoc.v:146365.3-146366.65" - process $proc$libresoc.v:146365$7018 + attribute \src "libresoc.v:146364.3-146365.65" + process $proc$libresoc.v:146364$7018 assign { } { } assign $0\logical_op__is_32bit$16[0:0]$7019 \logical_op__is_32bit$16$next sync posedge \coresync_clk update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7019 end - attribute \src "libresoc.v:146367.3-146368.67" - process $proc$libresoc.v:146367$7020 + attribute \src "libresoc.v:146366.3-146367.67" + process $proc$libresoc.v:146366$7020 assign { } { } assign $0\logical_op__is_signed$17[0:0]$7021 \logical_op__is_signed$17$next sync posedge \coresync_clk update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7021 end - attribute \src "libresoc.v:146369.3-146370.65" - process $proc$libresoc.v:146369$7022 + attribute \src "libresoc.v:146368.3-146369.65" + process $proc$libresoc.v:146368$7022 assign { } { } assign $0\logical_op__data_len$18[3:0]$7023 \logical_op__data_len$18$next sync posedge \coresync_clk update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7023 end - attribute \src "libresoc.v:146371.3-146372.57" - process $proc$libresoc.v:146371$7024 + attribute \src "libresoc.v:146370.3-146371.57" + process $proc$libresoc.v:146370$7024 assign { } { } assign $0\logical_op__insn$19[31:0]$7025 \logical_op__insn$19$next sync posedge \coresync_clk update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7025 end - attribute \src "libresoc.v:146373.3-146374.33" - process $proc$libresoc.v:146373$7026 + attribute \src "libresoc.v:146372.3-146373.33" + process $proc$libresoc.v:146372$7026 assign { } { } assign $0\muxid$1[1:0]$7027 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$7027 end - attribute \src "libresoc.v:146375.3-146376.29" - process $proc$libresoc.v:146375$7028 + attribute \src "libresoc.v:146374.3-146375.29" + process $proc$libresoc.v:146374$7028 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:146433.3-146450.6" - process $proc$libresoc.v:146433$7029 + attribute \src "libresoc.v:146432.3-146449.6" + process $proc$libresoc.v:146432$7029 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$7030 $2\r_busy$next[0:0]$7032 - attribute \src "libresoc.v:146434.5-146434.29" + attribute \src "libresoc.v:146433.5-146433.29" switch \initial - attribute \src "libresoc.v:146434.9-146434.17" + attribute \src "libresoc.v:146433.9-146433.17" case 1'1 case end @@ -238755,14 +238755,14 @@ module \logical_pipe2 sync always update \r_busy$next $0\r_busy$next[0:0]$7030 end - attribute \src "libresoc.v:146451.3-146463.6" - process $proc$libresoc.v:146451$7033 + attribute \src "libresoc.v:146450.3-146462.6" + process $proc$libresoc.v:146450$7033 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$7034 $1\muxid$1$next[1:0]$7035 - attribute \src "libresoc.v:146452.5-146452.29" + attribute \src "libresoc.v:146451.5-146451.29" switch \initial - attribute \src "libresoc.v:146452.9-146452.17" + attribute \src "libresoc.v:146451.9-146451.17" case 1'1 case end @@ -238782,8 +238782,8 @@ module \logical_pipe2 sync always update \muxid$1$next $0\muxid$1$next[1:0]$7034 end - attribute \src "libresoc.v:146464.3-146505.6" - process $proc$libresoc.v:146464$7036 + attribute \src "libresoc.v:146463.3-146504.6" + process $proc$libresoc.v:146463$7036 assign { } { } assign { } { } assign { } { } @@ -238844,9 +238844,9 @@ module \logical_pipe2 assign $0\logical_op__oe__ok$9$next[0:0]$7049 $2\logical_op__oe__ok$9$next[0:0]$7076 assign $0\logical_op__rc__ok$7$next[0:0]$7051 $2\logical_op__rc__ok$7$next[0:0]$7077 assign $0\logical_op__rc__rc$6$next[0:0]$7052 $2\logical_op__rc__rc$6$next[0:0]$7078 - attribute \src "libresoc.v:146465.5-146465.29" + attribute \src "libresoc.v:146464.5-146464.29" switch \initial - attribute \src "libresoc.v:146465.9-146465.17" + attribute \src "libresoc.v:146464.9-146464.17" case 1'1 case end @@ -238958,8 +238958,8 @@ module \logical_pipe2 update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$7053 update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$7054 end - attribute \src "libresoc.v:146506.3-146524.6" - process $proc$libresoc.v:146506$7079 + attribute \src "libresoc.v:146505.3-146523.6" + process $proc$libresoc.v:146505$7079 assign { } { } assign { } { } assign { } { } @@ -238967,9 +238967,9 @@ module \logical_pipe2 assign $0\o$20$next[63:0]$7080 $1\o$20$next[63:0]$7082 assign { } { } assign $0\o_ok$21$next[0:0]$7081 $2\o_ok$21$next[0:0]$7084 - attribute \src "libresoc.v:146507.5-146507.29" + attribute \src "libresoc.v:146506.5-146506.29" switch \initial - attribute \src "libresoc.v:146507.9-146507.17" + attribute \src "libresoc.v:146506.9-146506.17" case 1'1 case end @@ -239002,8 +239002,8 @@ module \logical_pipe2 update \o$20$next $0\o$20$next[63:0]$7080 update \o_ok$21$next $0\o_ok$21$next[0:0]$7081 end - attribute \src "libresoc.v:146525.3-146543.6" - process $proc$libresoc.v:146525$7085 + attribute \src "libresoc.v:146524.3-146542.6" + process $proc$libresoc.v:146524$7085 assign { } { } assign { } { } assign { } { } @@ -239011,9 +239011,9 @@ module \logical_pipe2 assign $0\cr_a$22$next[3:0]$7086 $1\cr_a$22$next[3:0]$7088 assign { } { } assign $0\cr_a_ok$23$next[0:0]$7087 $2\cr_a_ok$23$next[0:0]$7090 - attribute \src "libresoc.v:146526.5-146526.29" + attribute \src "libresoc.v:146525.5-146525.29" switch \initial - attribute \src "libresoc.v:146526.9-146526.17" + attribute \src "libresoc.v:146525.9-146525.17" case 1'1 case end @@ -239046,7 +239046,7 @@ module \logical_pipe2 update \cr_a$22$next $0\cr_a$22$next[3:0]$7086 update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7087 end - connect \$49 $and$libresoc.v:146328$6981_Y + connect \$49 $and$libresoc.v:146327$6981_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } @@ -239062,784 +239062,624 @@ module \logical_pipe2 connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_muxid \muxid end -attribute \src "ls180.v:4.1-11017.10" +attribute \src "ls180.v:4.1-10688.10" attribute \cells_not_processed 1 module \ls180 - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2894 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2895 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2896 - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2897 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2898 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2899 - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2900 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2901 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2902 - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2903 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2904 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2905 - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2906 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2907 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2908 - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2909 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2910 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2911 - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2912 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2913 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2914 - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2915 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2916 - attribute \src "ls180.v:10353.1-10371.4" - wire width 64 $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2917 - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2920 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2921 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2922 - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2923 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2924 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2925 - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2926 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2927 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2928 - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2929 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2930 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2931 - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2932 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2933 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2934 - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2935 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2936 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2937 - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2938 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2939 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2940 - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2941 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2942 - attribute \src "ls180.v:10381.1-10399.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2943 - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2946 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2947 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2948 - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2949 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2950 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2951 - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2952 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2953 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2954 - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2955 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2956 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2957 - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2958 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2959 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2960 - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2961 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2962 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2963 - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2964 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2965 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2966 - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2967 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2968 - attribute \src "ls180.v:10409.1-10427.4" - wire width 64 $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2969 - attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2972 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2973 - attribute \src "ls180.v:10437.1-10455.4" - wire width 64 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$0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3040 - attribute \src "ls180.v:10535.1-10539.4" - wire width 3 $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3045 - attribute \src "ls180.v:10535.1-10539.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3046 - attribute \src "ls180.v:10535.1-10539.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3047 - attribute \src "ls180.v:10550.1-10554.4" - wire width 4 $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3052 - attribute \src "ls180.v:10550.1-10554.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3053 - attribute \src "ls180.v:10550.1-10554.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3054 - attribute \src "ls180.v:10567.1-10571.4" - wire width 4 $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3059 - attribute \src "ls180.v:10567.1-10571.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3060 - attribute \src "ls180.v:10567.1-10571.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3061 - attribute \src "ls180.v:10583.1-10587.4" - wire width 5 $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3066 - attribute \src "ls180.v:10583.1-10587.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3067 - attribute \src "ls180.v:10583.1-10587.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3068 - attribute \src "ls180.v:10597.1-10601.4" - wire width 5 $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3073 - attribute \src "ls180.v:10597.1-10601.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3074 - attribute \src "ls180.v:10597.1-10601.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3075 - attribute \src "ls180.v:3402.1-3495.4" + attribute \src "ls180.v:10144.1-10162.4" + wire width 4 $0$memwr$\mem$ls180.v:10146$1_ADDR[3:0]$2744 + attribute \src "ls180.v:10144.1-10162.4" + wire width 64 $0$memwr$\mem$ls180.v:10146$1_DATA[63:0]$2745 + attribute \src "ls180.v:10144.1-10162.4" + wire width 64 $0$memwr$\mem$ls180.v:10146$1_EN[63:0]$2746 + attribute \src "ls180.v:10144.1-10162.4" + wire width 4 $0$memwr$\mem$ls180.v:10148$2_ADDR[3:0]$2747 + attribute \src "ls180.v:10144.1-10162.4" + wire width 64 $0$memwr$\mem$ls180.v:10148$2_DATA[63:0]$2748 + attribute \src "ls180.v:10144.1-10162.4" + wire width 64 $0$memwr$\mem$ls180.v:10148$2_EN[63:0]$2749 + attribute \src "ls180.v:10144.1-10162.4" + wire width 4 $0$memwr$\mem$ls180.v:10150$3_ADDR[3:0]$2750 + attribute \src "ls180.v:10144.1-10162.4" + wire width 64 $0$memwr$\mem$ls180.v:10150$3_DATA[63:0]$2751 + attribute \src "ls180.v:10144.1-10162.4" + wire width 64 $0$memwr$\mem$ls180.v:10150$3_EN[63:0]$2752 + attribute \src "ls180.v:10144.1-10162.4" + wire width 4 $0$memwr$\mem$ls180.v:10152$4_ADDR[3:0]$2753 + attribute \src "ls180.v:10144.1-10162.4" + wire width 64 $0$memwr$\mem$ls180.v:10152$4_DATA[63:0]$2754 + attribute \src "ls180.v:10144.1-10162.4" + wire width 64 $0$memwr$\mem$ls180.v:10152$4_EN[63:0]$2755 + attribute \src "ls180.v:10144.1-10162.4" + wire width 4 $0$memwr$\mem$ls180.v:10154$5_ADDR[3:0]$2756 + attribute \src "ls180.v:10144.1-10162.4" + wire width 64 $0$memwr$\mem$ls180.v:10154$5_DATA[63:0]$2757 + attribute \src "ls180.v:10144.1-10162.4" + wire width 64 $0$memwr$\mem$ls180.v:10154$5_EN[63:0]$2758 + attribute \src "ls180.v:10144.1-10162.4" + wire width 4 $0$memwr$\mem$ls180.v:10156$6_ADDR[3:0]$2759 + attribute \src "ls180.v:10144.1-10162.4" + wire width 64 $0$memwr$\mem$ls180.v:10156$6_DATA[63:0]$2760 + attribute \src "ls180.v:10144.1-10162.4" + wire width 64 $0$memwr$\mem$ls180.v:10156$6_EN[63:0]$2761 + attribute \src "ls180.v:10144.1-10162.4" + wire width 4 $0$memwr$\mem$ls180.v:10158$7_ADDR[3:0]$2762 + attribute \src "ls180.v:10144.1-10162.4" + wire width 64 $0$memwr$\mem$ls180.v:10158$7_DATA[63:0]$2763 + attribute \src "ls180.v:10144.1-10162.4" + wire width 64 $0$memwr$\mem$ls180.v:10158$7_EN[63:0]$2764 + attribute \src "ls180.v:10144.1-10162.4" + wire width 4 $0$memwr$\mem$ls180.v:10160$8_ADDR[3:0]$2765 + attribute \src "ls180.v:10144.1-10162.4" + wire width 64 $0$memwr$\mem$ls180.v:10160$8_DATA[63:0]$2766 + attribute \src "ls180.v:10144.1-10162.4" + wire width 64 $0$memwr$\mem$ls180.v:10160$8_EN[63:0]$2767 + attribute \src "ls180.v:10172.1-10190.4" + wire width 4 $0$memwr$\mem_1$ls180.v:10174$9_ADDR[3:0]$2770 + attribute \src "ls180.v:10172.1-10190.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10174$9_DATA[63:0]$2771 + attribute \src "ls180.v:10172.1-10190.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10174$9_EN[63:0]$2772 + attribute \src "ls180.v:10172.1-10190.4" + wire width 4 $0$memwr$\mem_1$ls180.v:10176$10_ADDR[3:0]$2773 + attribute \src "ls180.v:10172.1-10190.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10176$10_DATA[63:0]$2774 + attribute \src "ls180.v:10172.1-10190.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10176$10_EN[63:0]$2775 + attribute \src "ls180.v:10172.1-10190.4" + wire width 4 $0$memwr$\mem_1$ls180.v:10178$11_ADDR[3:0]$2776 + attribute \src "ls180.v:10172.1-10190.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10178$11_DATA[63:0]$2777 + attribute \src "ls180.v:10172.1-10190.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10178$11_EN[63:0]$2778 + attribute \src "ls180.v:10172.1-10190.4" + wire width 4 $0$memwr$\mem_1$ls180.v:10180$12_ADDR[3:0]$2779 + attribute \src "ls180.v:10172.1-10190.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10180$12_DATA[63:0]$2780 + attribute \src "ls180.v:10172.1-10190.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10180$12_EN[63:0]$2781 + attribute \src "ls180.v:10172.1-10190.4" + wire width 4 $0$memwr$\mem_1$ls180.v:10182$13_ADDR[3:0]$2782 + attribute \src "ls180.v:10172.1-10190.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10182$13_DATA[63:0]$2783 + attribute \src "ls180.v:10172.1-10190.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10182$13_EN[63:0]$2784 + attribute \src "ls180.v:10172.1-10190.4" + wire width 4 $0$memwr$\mem_1$ls180.v:10184$14_ADDR[3:0]$2785 + attribute \src "ls180.v:10172.1-10190.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10184$14_DATA[63:0]$2786 + attribute \src "ls180.v:10172.1-10190.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10184$14_EN[63:0]$2787 + attribute \src "ls180.v:10172.1-10190.4" + wire width 4 $0$memwr$\mem_1$ls180.v:10186$15_ADDR[3:0]$2788 + attribute \src "ls180.v:10172.1-10190.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10186$15_DATA[63:0]$2789 + attribute \src "ls180.v:10172.1-10190.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10186$15_EN[63:0]$2790 + attribute \src "ls180.v:10172.1-10190.4" + wire width 4 $0$memwr$\mem_1$ls180.v:10188$16_ADDR[3:0]$2791 + attribute \src "ls180.v:10172.1-10190.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10188$16_DATA[63:0]$2792 + attribute \src "ls180.v:10172.1-10190.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10188$16_EN[63:0]$2793 + attribute \src "ls180.v:10200.1-10204.4" + wire width 3 $0$memwr$\storage$ls180.v:10202$17_ADDR[2:0]$2796 + attribute \src "ls180.v:10200.1-10204.4" + wire width 25 $0$memwr$\storage$ls180.v:10202$17_DATA[24:0]$2797 + attribute \src "ls180.v:10200.1-10204.4" + wire width 25 $0$memwr$\storage$ls180.v:10202$17_EN[24:0]$2798 + attribute \src "ls180.v:10214.1-10218.4" + wire width 3 $0$memwr$\storage_1$ls180.v:10216$18_ADDR[2:0]$2803 + attribute \src "ls180.v:10214.1-10218.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10216$18_DATA[24:0]$2804 + attribute \src "ls180.v:10214.1-10218.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10216$18_EN[24:0]$2805 + attribute \src "ls180.v:10228.1-10232.4" + wire width 3 $0$memwr$\storage_2$ls180.v:10230$19_ADDR[2:0]$2810 + attribute \src "ls180.v:10228.1-10232.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10230$19_DATA[24:0]$2811 + attribute \src "ls180.v:10228.1-10232.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10230$19_EN[24:0]$2812 + attribute \src "ls180.v:10242.1-10246.4" + wire width 3 $0$memwr$\storage_3$ls180.v:10244$20_ADDR[2:0]$2817 + attribute \src "ls180.v:10242.1-10246.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10244$20_DATA[24:0]$2818 + attribute \src "ls180.v:10242.1-10246.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10244$20_EN[24:0]$2819 + attribute \src "ls180.v:10257.1-10261.4" + wire width 4 $0$memwr$\storage_4$ls180.v:10259$21_ADDR[3:0]$2824 + attribute \src "ls180.v:10257.1-10261.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10259$21_DATA[9:0]$2825 + attribute \src "ls180.v:10257.1-10261.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10259$21_EN[9:0]$2826 + attribute \src "ls180.v:10274.1-10278.4" + wire width 4 $0$memwr$\storage_5$ls180.v:10276$22_ADDR[3:0]$2831 + attribute \src "ls180.v:10274.1-10278.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10276$22_DATA[9:0]$2832 + attribute \src "ls180.v:10274.1-10278.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10276$22_EN[9:0]$2833 + attribute \src "ls180.v:10290.1-10294.4" + wire width 5 $0$memwr$\storage_6$ls180.v:10292$23_ADDR[4:0]$2838 + attribute \src "ls180.v:10290.1-10294.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10292$23_DATA[9:0]$2839 + attribute \src "ls180.v:10290.1-10294.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10292$23_EN[9:0]$2840 + attribute \src "ls180.v:10304.1-10308.4" + wire width 5 $0$memwr$\storage_7$ls180.v:10306$24_ADDR[4:0]$2845 + attribute \src "ls180.v:10304.1-10308.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10306$24_DATA[9:0]$2846 + attribute \src "ls180.v:10304.1-10308.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10306$24_EN[9:0]$2847 + attribute \src "ls180.v:3271.1-3364.4" wire width 3 $0\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:3559.1-3652.4" + attribute \src "ls180.v:3428.1-3521.4" wire width 3 $0\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:3716.1-3809.4" + attribute \src "ls180.v:3585.1-3678.4" wire width 3 $0\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:3873.1-3966.4" + attribute \src "ls180.v:3742.1-3835.4" wire width 3 $0\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:6791.1-6807.4" + attribute \src "ls180.v:6597.1-6613.4" wire $0\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:7012.1-7028.4" + attribute \src "ls180.v:6818.1-6834.4" wire $0\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:7029.1-7045.4" + attribute \src "ls180.v:6835.1-6851.4" wire $0\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:7097.1-7104.4" + attribute \src "ls180.v:6903.1-6910.4" wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:7105.1-7112.4" + attribute \src "ls180.v:6911.1-6918.4" wire $0\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:7113.1-7120.4" + attribute \src "ls180.v:6919.1-6926.4" wire $0\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:7121.1-7128.4" + attribute \src "ls180.v:6927.1-6934.4" wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:7129.1-7136.4" + attribute \src "ls180.v:6935.1-6942.4" wire $0\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:7137.1-7144.4" + attribute \src "ls180.v:6943.1-6950.4" wire $0\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:7145.1-7152.4" + attribute \src "ls180.v:6951.1-6958.4" wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:7153.1-7160.4" + attribute \src "ls180.v:6959.1-6966.4" wire $0\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:6808.1-6824.4" + attribute \src "ls180.v:6614.1-6630.4" wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:7161.1-7168.4" + attribute \src "ls180.v:6967.1-6974.4" wire $0\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:7169.1-7176.4" + attribute \src "ls180.v:6975.1-6982.4" wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:7177.1-7184.4" + attribute \src "ls180.v:6983.1-6990.4" wire $0\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:7185.1-7192.4" + attribute \src "ls180.v:6991.1-6998.4" wire $0\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:7193.1-7212.4" + attribute \src "ls180.v:6999.1-7018.4" wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:7213.1-7232.4" + attribute \src "ls180.v:7019.1-7038.4" wire width 64 $0\builder_comb_rhs_array_muxed25[63:0] - attribute \src "ls180.v:7233.1-7252.4" + attribute \src "ls180.v:7039.1-7058.4" wire width 8 $0\builder_comb_rhs_array_muxed26[7:0] - attribute \src "ls180.v:7253.1-7272.4" + attribute \src "ls180.v:7059.1-7078.4" wire $0\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:7273.1-7292.4" + attribute \src "ls180.v:7079.1-7098.4" wire $0\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:7293.1-7312.4" + attribute \src "ls180.v:7099.1-7118.4" wire $0\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:6825.1-6841.4" + attribute \src "ls180.v:6631.1-6647.4" wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:7313.1-7332.4" + attribute \src "ls180.v:7119.1-7138.4" wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:7333.1-7352.4" + attribute \src "ls180.v:7139.1-7158.4" wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:6842.1-6858.4" + attribute \src "ls180.v:6648.1-6664.4" wire $0\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:6859.1-6875.4" + attribute \src "ls180.v:6665.1-6681.4" wire $0\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:6876.1-6892.4" + attribute \src "ls180.v:6682.1-6698.4" wire $0\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:6944.1-6960.4" + attribute \src "ls180.v:6750.1-6766.4" wire $0\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:6961.1-6977.4" + attribute \src "ls180.v:6767.1-6783.4" wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:6978.1-6994.4" + attribute \src "ls180.v:6784.1-6800.4" wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:6995.1-7011.4" + attribute \src "ls180.v:6801.1-6817.4" wire $0\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:6893.1-6909.4" + attribute \src "ls180.v:6699.1-6715.4" wire $0\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:6910.1-6926.4" + attribute \src "ls180.v:6716.1-6732.4" wire $0\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:6927.1-6943.4" + attribute \src "ls180.v:6733.1-6749.4" wire $0\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:7046.1-7062.4" + attribute \src "ls180.v:6852.1-6868.4" wire $0\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:7063.1-7079.4" + attribute \src "ls180.v:6869.1-6885.4" wire $0\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:7080.1-7096.4" + attribute \src "ls180.v:6886.1-6902.4" wire $0\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:2906.1-2952.4" + attribute \src "ls180.v:2817.1-2863.4" wire $0\builder_converter0_next_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_converter0_state[0:0] - attribute \src "ls180.v:2966.1-3012.4" + attribute \src "ls180.v:2877.1-2923.4" wire $0\builder_converter1_next_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_converter1_state[0:0] - attribute \src "ls180.v:3026.1-3072.4" + attribute \src "ls180.v:2937.1-2983.4" wire $0\builder_converter2_next_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_converter2_state[0:0] - attribute \src "ls180.v:4219.1-4265.4" + attribute \src "ls180.v:4088.1-4134.4" wire $0\builder_converter_next_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_converter_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 20 $0\builder_count[19:0] - attribute \src "ls180.v:6031.1-6042.4" + attribute \src "ls180.v:5837.1-5848.4" wire $0\builder_error[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\builder_grant[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 14 $0\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:5848.1-5884.4" + attribute \src "ls180.v:5717.1-5753.4" wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:5848.1-5884.4" + attribute \src "ls180.v:5717.1-5753.4" wire $0\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1993.5-1993.55" + attribute \src "ls180.v:1904.5-1904.55" wire $0\builder_libresocsim_converted_interface_ack[0:0] - attribute \src "ls180.v:1989.12-1989.65" + attribute \src "ls180.v:1900.12-1900.65" wire width 64 $0\builder_libresocsim_converted_interface_dat_r[63:0] - attribute \src "ls180.v:1997.5-1997.55" + attribute \src "ls180.v:1908.5-1908.55" wire $0\builder_libresocsim_converted_interface_err[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:5848.1-5884.4" + attribute \src "ls180.v:5717.1-5753.4" wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:5848.1-5884.4" + attribute \src "ls180.v:5717.1-5753.4" wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_libresocsim_we[0:0] - attribute \src "ls180.v:5848.1-5884.4" + attribute \src "ls180.v:5717.1-5753.4" wire $0\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:5848.1-5884.4" + attribute \src "ls180.v:5717.1-5753.4" wire $0\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:5848.1-5884.4" + attribute \src "ls180.v:5717.1-5753.4" wire $0\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1979.12-1979.52" + attribute \src "ls180.v:1890.12-1890.52" wire width 30 $0\builder_libresocsim_wishbone_adr[29:0] - attribute \src "ls180.v:1983.5-1983.44" + attribute \src "ls180.v:1894.5-1894.44" wire $0\builder_libresocsim_wishbone_cyc[0:0] - attribute \src "ls180.v:5848.1-5884.4" + attribute \src "ls180.v:5717.1-5753.4" wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1980.12-1980.54" + attribute \src "ls180.v:1891.12-1891.54" wire width 32 $0\builder_libresocsim_wishbone_dat_w[31:0] - attribute \src "ls180.v:1982.11-1982.50" + attribute \src "ls180.v:1893.11-1893.50" wire width 4 $0\builder_libresocsim_wishbone_sel[3:0] - attribute \src "ls180.v:1984.5-1984.44" + attribute \src "ls180.v:1895.5-1895.44" wire $0\builder_libresocsim_wishbone_stb[0:0] - attribute \src "ls180.v:1986.5-1986.43" + attribute \src "ls180.v:1897.5-1897.43" wire $0\builder_libresocsim_wishbone_we[0:0] - attribute \src "ls180.v:1878.5-1878.27" + attribute \src "ls180.v:1789.5-1789.27" wire $0\builder_locked0[0:0] - attribute \src "ls180.v:1879.5-1879.27" + attribute \src "ls180.v:1790.5-1790.27" wire $0\builder_locked1[0:0] - attribute \src "ls180.v:1880.5-1880.27" + attribute \src "ls180.v:1791.5-1791.27" wire $0\builder_locked2[0:0] - attribute \src "ls180.v:1881.5-1881.27" + attribute \src "ls180.v:1792.5-1792.27" wire $0\builder_locked3[0:0] - attribute \src "ls180.v:4091.1-4163.4" + attribute \src "ls180.v:3960.1-4032.4" wire width 3 $0\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\builder_multiplexer_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:5848.1-5884.4" + attribute \src "ls180.v:5717.1-5753.4" wire width 2 $0\builder_next_state[1:0] - attribute \src "ls180.v:3308.1-3338.4" + attribute \src "ls180.v:3177.1-3207.4" wire width 2 $0\builder_refresher_next_state[1:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 2 $0\builder_refresher_state[1:0] - attribute \src "ls180.v:5646.1-5685.4" + attribute \src "ls180.v:5515.1-5554.4" wire width 2 $0\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 2 $0\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:5213.1-5292.4" + attribute \src "ls180.v:5082.1-5161.4" wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire width 3 $0\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:5705.1-5742.4" + attribute \src "ls180.v:5574.1-5611.4" wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:5743.1-5779.4" + attribute \src "ls180.v:5612.1-5648.4" wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:4888.1-4960.4" + attribute \src "ls180.v:4757.1-4829.4" wire width 3 $0\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:4733.1-4826.4" + attribute \src "ls180.v:4602.1-4695.4" wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:4623.1-4699.4" + attribute \src "ls180.v:4492.1-4568.4" wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:4860.1-4887.4" + attribute \src "ls180.v:4729.1-4756.4" wire $0\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:4994.1-5095.4" + attribute \src "ls180.v:4863.1-4964.4" wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:4589.1-4622.4" + attribute \src "ls180.v:4458.1-4491.4" wire $0\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:6031.1-6042.4" + attribute \src "ls180.v:5837.1-5848.4" wire $0\builder_shared_ack[0:0] - attribute \src "ls180.v:6031.1-6042.4" + attribute \src "ls180.v:5837.1-5848.4" wire width 32 $0\builder_shared_dat_r[31:0] - attribute \src "ls180.v:5909.1-5924.4" - wire width 13 $0\builder_slave_sel[12:0] - attribute \src "ls180.v:7705.1-10349.4" - wire width 13 $0\builder_slave_sel_r[12:0] - attribute \src "ls180.v:4420.1-4468.4" + attribute \src "ls180.v:5778.1-5786.4" + wire width 6 $0\builder_slave_sel[5:0] + attribute \src "ls180.v:7511.1-10140.4" + wire width 6 $0\builder_slave_sel_r[5:0] + attribute \src "ls180.v:4289.1-4337.4" wire width 2 $0\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 2 $0\builder_spimaster0_state[1:0] - attribute \src "ls180.v:4479.1-4527.4" + attribute \src "ls180.v:4348.1-4396.4" wire width 2 $0\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 2 $0\builder_spimaster1_state[1:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 2 $0\builder_state[1:0] - attribute \src "ls180.v:7472.1-7500.4" + attribute \src "ls180.v:7278.1-7306.4" wire $0\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:7501.1-7529.4" + attribute \src "ls180.v:7307.1-7335.4" wire $0\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:7353.1-7369.4" + attribute \src "ls180.v:7159.1-7175.4" wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:7370.1-7386.4" + attribute \src "ls180.v:7176.1-7192.4" wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:7387.1-7403.4" + attribute \src "ls180.v:7193.1-7209.4" wire $0\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:7404.1-7420.4" + attribute \src "ls180.v:7210.1-7226.4" wire $0\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:7421.1-7437.4" + attribute \src "ls180.v:7227.1-7243.4" wire $0\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:7438.1-7454.4" + attribute \src "ls180.v:7244.1-7260.4" wire $0\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:7455.1-7471.4" + attribute \src "ls180.v:7261.1-7277.4" wire $0\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:4399.1-4403.4" + attribute \src "ls180.v:4268.1-4272.4" wire width 16 $0\gpio_o[15:0] - attribute \src "ls180.v:4404.1-4408.4" + attribute \src "ls180.v:4273.1-4277.4" wire width 16 $0\gpio_oe[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_cmd_consumed[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_converter0_counter[0:0] - attribute \src "ls180.v:2906.1-2952.4" + attribute \src "ls180.v:2817.1-2863.4" wire $0\main_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:2906.1-2952.4" + attribute \src "ls180.v:2817.1-2863.4" wire $0\main_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 64 $0\main_converter0_dat_r[63:0] - attribute \src "ls180.v:2906.1-2952.4" + attribute \src "ls180.v:2817.1-2863.4" wire $0\main_converter0_skip[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_converter1_counter[0:0] - attribute \src "ls180.v:2966.1-3012.4" + attribute \src "ls180.v:2877.1-2923.4" wire $0\main_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:2966.1-3012.4" + attribute \src "ls180.v:2877.1-2923.4" wire $0\main_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 64 $0\main_converter1_dat_r[63:0] - attribute \src "ls180.v:2966.1-3012.4" + attribute \src "ls180.v:2877.1-2923.4" wire $0\main_converter1_skip[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_converter_counter[0:0] - attribute \src "ls180.v:4219.1-4265.4" + attribute \src "ls180.v:4088.1-4134.4" wire $0\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:4219.1-4265.4" + attribute \src "ls180.v:4088.1-4134.4" wire $0\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_converter_dat_r[31:0] - attribute \src "ls180.v:4219.1-4265.4" + attribute \src "ls180.v:4088.1-4134.4" wire $0\main_converter_skip[0:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire width 16 $0\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 24 $0\main_dummy[23:0] - attribute \src "ls180.v:1085.12-1085.53" + attribute \src "ls180.v:996.12-996.53" wire width 16 $0\main_gpiotristateasic0_oe_storage[15:0] - attribute \src "ls180.v:1087.12-1087.54" + attribute \src "ls180.v:998.12-998.54" wire width 16 $0\main_gpiotristateasic0_out_storage[15:0] - attribute \src "ls180.v:7587.1-7597.4" + attribute \src "ls180.v:7393.1-7403.4" wire width 16 $0\main_gpiotristateasic0_status[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_gpiotristateasic1_oe_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_gpiotristateasic1_oe_storage[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_gpiotristateasic1_out_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_gpiotristateasic1_out_storage[15:0] - attribute \src "ls180.v:7598.1-7608.4" + attribute \src "ls180.v:7404.1-7414.4" wire width 16 $0\main_gpiotristateasic1_status[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_i2c_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_i2c_storage[2:0] - attribute \src "ls180.v:7629.1-7631.4" + attribute \src "ls180.v:7435.1-7437.4" wire $0\main_int_rst[0:0] - attribute \src "ls180.v:1666.11-1666.41" + attribute \src "ls180.v:1577.11-1577.41" wire width 2 $0\main_interface0_bus_bte[1:0] - attribute \src "ls180.v:1665.11-1665.41" + attribute \src "ls180.v:1576.11-1576.41" wire width 3 $0\main_interface0_bus_cti[2:0] - attribute \src "ls180.v:2906.1-2952.4" + attribute \src "ls180.v:2817.1-2863.4" wire $0\main_interface0_converted_interface_ack[0:0] - attribute \src "ls180.v:319.5-319.51" + attribute \src "ls180.v:230.5-230.51" wire $0\main_interface0_converted_interface_err[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_interface0_ram_bus_ack[0:0] - attribute \src "ls180.v:259.5-259.39" - wire $0\main_interface0_ram_bus_err[0:0] - attribute \src "ls180.v:5705.1-5742.4" + attribute \src "ls180.v:5574.1-5611.4" wire width 32 $0\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1757.11-1757.41" + attribute \src "ls180.v:1668.11-1668.41" wire width 2 $0\main_interface1_bus_bte[1:0] - attribute \src "ls180.v:1756.11-1756.41" + attribute \src "ls180.v:1667.11-1667.41" wire width 3 $0\main_interface1_bus_cti[2:0] - attribute \src "ls180.v:5705.1-5742.4" + attribute \src "ls180.v:5574.1-5611.4" wire $0\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1749.12-1749.45" + attribute \src "ls180.v:1660.12-1660.45" wire width 64 $0\main_interface1_bus_dat_w[63:0] - attribute \src "ls180.v:5705.1-5742.4" + attribute \src "ls180.v:5574.1-5611.4" wire width 8 $0\main_interface1_bus_sel[7:0] - attribute \src "ls180.v:5705.1-5742.4" + attribute \src "ls180.v:5574.1-5611.4" wire $0\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:5705.1-5742.4" + attribute \src "ls180.v:5574.1-5611.4" wire $0\main_interface1_bus_we[0:0] - attribute \src "ls180.v:2966.1-3012.4" + attribute \src "ls180.v:2877.1-2923.4" wire $0\main_interface1_converted_interface_ack[0:0] - attribute \src "ls180.v:334.5-334.51" + attribute \src "ls180.v:245.5-245.51" wire $0\main_interface1_converted_interface_err[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_interface1_ram_bus_ack[0:0] - attribute \src "ls180.v:274.5-274.39" - wire $0\main_interface1_ram_bus_err[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_interface2_ram_bus_ack[0:0] - attribute \src "ls180.v:289.5-289.39" - wire $0\main_interface2_ram_bus_err[0:0] - attribute \src "ls180.v:7705.1-10349.4" - wire $0\main_interface3_ram_bus_ack[0:0] - attribute \src "ls180.v:304.5-304.39" - wire $0\main_interface3_ram_bus_err[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:171.12-171.74" + attribute \src "ls180.v:154.12-154.74" wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] - attribute \src "ls180.v:175.5-175.69" + attribute \src "ls180.v:128.5-128.69" wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - attribute \src "ls180.v:201.5-201.72" + attribute \src "ls180.v:132.5-132.72" wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - attribute \src "ls180.v:204.11-204.79" + attribute \src "ls180.v:135.11-135.79" wire width 4 $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] - attribute \src "ls180.v:189.12-189.78" + attribute \src "ls180.v:143.12-143.78" wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] attribute \src "ls180.v:75.11-75.52" wire width 2 $0\main_libresocsim_libresoc_dbus_bte[1:0] @@ -239849,1943 +239689,1927 @@ module \ls180 wire width 2 $0\main_libresocsim_libresoc_ibus_bte[1:0] attribute \src "ls180.v:85.11-85.52" wire width 3 $0\main_libresocsim_libresoc_ibus_cti[2:0] - attribute \src "ls180.v:2887.1-2892.4" + attribute \src "ls180.v:2798.1-2803.4" wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] attribute \src "ls180.v:115.11-115.55" wire width 2 $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] attribute \src "ls180.v:114.11-114.55" wire width 3 $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] - attribute \src "ls180.v:2906.1-2952.4" + attribute \src "ls180.v:2817.1-2863.4" wire width 30 $0\main_libresocsim_libresoc_xics_icp_adr[29:0] - attribute \src "ls180.v:2906.1-2952.4" + attribute \src "ls180.v:2817.1-2863.4" wire $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] - attribute \src "ls180.v:2894.1-2904.4" + attribute \src "ls180.v:2805.1-2815.4" wire width 32 $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] - attribute \src "ls180.v:2906.1-2952.4" + attribute \src "ls180.v:2817.1-2863.4" wire width 4 $0\main_libresocsim_libresoc_xics_icp_sel[3:0] - attribute \src "ls180.v:2906.1-2952.4" + attribute \src "ls180.v:2817.1-2863.4" wire $0\main_libresocsim_libresoc_xics_icp_stb[0:0] - attribute \src "ls180.v:2906.1-2952.4" + attribute \src "ls180.v:2817.1-2863.4" wire $0\main_libresocsim_libresoc_xics_icp_we[0:0] - attribute \src "ls180.v:2966.1-3012.4" + attribute \src "ls180.v:2877.1-2923.4" wire width 30 $0\main_libresocsim_libresoc_xics_ics_adr[29:0] - attribute \src "ls180.v:2966.1-3012.4" + attribute \src "ls180.v:2877.1-2923.4" wire $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] - attribute \src "ls180.v:2954.1-2964.4" + attribute \src "ls180.v:2865.1-2875.4" wire width 32 $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] - attribute \src "ls180.v:2966.1-3012.4" + attribute \src "ls180.v:2877.1-2923.4" wire width 4 $0\main_libresocsim_libresoc_xics_ics_sel[3:0] - attribute \src "ls180.v:2966.1-3012.4" + attribute \src "ls180.v:2877.1-2923.4" wire $0\main_libresocsim_libresoc_xics_ics_stb[0:0] - attribute \src "ls180.v:2966.1-3012.4" + attribute \src "ls180.v:2877.1-2923.4" wire $0\main_libresocsim_libresoc_xics_ics_we[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:217.5-217.40" + attribute \src "ls180.v:173.5-173.40" wire $0\main_libresocsim_ram_bus_err[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_libresocsim_value[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:3075.1-3085.4" + attribute \src "ls180.v:2986.1-2996.4" wire width 8 $0\main_libresocsim_we[7:0] - attribute \src "ls180.v:3091.1-3096.4" + attribute \src "ls180.v:3002.1-3007.4" wire $0\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:4219.1-4265.4" + attribute \src "ls180.v:4088.1-4134.4" wire width 30 $0\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:4219.1-4265.4" + attribute \src "ls180.v:4088.1-4134.4" wire $0\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:4207.1-4217.4" + attribute \src "ls180.v:4076.1-4086.4" wire width 16 $0\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:4219.1-4265.4" + attribute \src "ls180.v:4088.1-4134.4" wire width 2 $0\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:4219.1-4265.4" + attribute \src "ls180.v:4088.1-4134.4" wire $0\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:4219.1-4265.4" + attribute \src "ls180.v:4088.1-4134.4" wire $0\main_litedram_wb_we[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_pwm0_counter[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_pwm0_period_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_pwm0_width_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_pwm1_counter[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_pwm1_period_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_pwm1_width_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" + wire $0\main_ram_bus_ram_bus_ack[0:0] + attribute \src "ls180.v:215.5-215.36" + wire $0\main_ram_bus_ram_bus_err[0:0] + attribute \src "ls180.v:3011.1-3021.4" + wire width 8 $0\main_ram_we[7:0] + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_rddata_en[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdblock2mem_converter_demux[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 64 $0\main_sdblock2mem_converter_source_payload_data[63:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 4 $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 6 $0\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1690.5-1690.41" + attribute \src "ls180.v:1601.5-1601.41" wire $0\main_sdblock2mem_fifo_replace[0:0] - attribute \src "ls180.v:5613.1-5620.4" + attribute \src "ls180.v:5482.1-5489.4" wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:5646.1-5685.4" + attribute \src "ls180.v:5515.1-5554.4" wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:5646.1-5685.4" + attribute \src "ls180.v:5515.1-5554.4" wire width 64 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] - attribute \src "ls180.v:5646.1-5685.4" + attribute \src "ls180.v:5515.1-5554.4" wire $0\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:5646.1-5685.4" + attribute \src "ls180.v:5515.1-5554.4" wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:5646.1-5685.4" + attribute \src "ls180.v:5515.1-5554.4" wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:5646.1-5685.4" + attribute \src "ls180.v:5515.1-5554.4" wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:5646.1-5685.4" + attribute \src "ls180.v:5515.1-5554.4" wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 10 $0\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 128 $0\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1499.5-1499.34" + attribute \src "ls180.v:1410.5-1410.34" wire $0\main_sdcore_cmd_send_w[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:5301.1-5308.4" + attribute \src "ls180.v:5170.1-5177.4" wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:5357.1-5364.4" + attribute \src "ls180.v:5226.1-5233.4" wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:5311.1-5318.4" + attribute \src "ls180.v:5180.1-5187.4" wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:5367.1-5374.4" + attribute \src "ls180.v:5236.1-5243.4" wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:5321.1-5328.4" + attribute \src "ls180.v:5190.1-5197.4" wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:5377.1-5384.4" + attribute \src "ls180.v:5246.1-5253.4" wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:5331.1-5338.4" + attribute \src "ls180.v:5200.1-5207.4" wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:5387.1-5394.4" + attribute \src "ls180.v:5256.1-5263.4" wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:5346.1-5353.4" + attribute \src "ls180.v:5215.1-5222.4" wire $0\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1605.5-1605.50" + attribute \src "ls180.v:1516.5-1516.50" wire $0\main_sdcore_crc16_checker_source_first[0:0] - attribute \src "ls180.v:5340.1-5345.4" + attribute \src "ls180.v:5209.1-5214.4" wire $0\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:5293.1-5298.4" + attribute \src "ls180.v:5162.1-5167.4" wire $0\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:5213.1-5292.4" + attribute \src "ls180.v:5082.1-5161.4" wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:5213.1-5292.4" + attribute \src "ls180.v:5082.1-5161.4" wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:5175.1-5182.4" + attribute \src "ls180.v:5044.1-5051.4" wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:5185.1-5192.4" + attribute \src "ls180.v:5054.1-5061.4" wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:5195.1-5202.4" + attribute \src "ls180.v:5064.1-5071.4" wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:5205.1-5212.4" + attribute \src "ls180.v:5074.1-5081.4" wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:5213.1-5292.4" + attribute \src "ls180.v:5082.1-5161.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:5213.1-5292.4" + attribute \src "ls180.v:5082.1-5161.4" wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:5213.1-5292.4" + attribute \src "ls180.v:5082.1-5161.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:5213.1-5292.4" + attribute \src "ls180.v:5082.1-5161.4" wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:5213.1-5292.4" + attribute \src "ls180.v:5082.1-5161.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:5213.1-5292.4" + attribute \src "ls180.v:5082.1-5161.4" wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:5213.1-5292.4" + attribute \src "ls180.v:5082.1-5161.4" wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:5213.1-5292.4" + attribute \src "ls180.v:5082.1-5161.4" wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:5213.1-5292.4" + attribute \src "ls180.v:5082.1-5161.4" wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1562.5-1562.51" + attribute \src "ls180.v:1473.5-1473.51" wire $0\main_sdcore_crc16_inserter_source_first[0:0] - attribute \src "ls180.v:5213.1-5292.4" + attribute \src "ls180.v:5082.1-5161.4" wire $0\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:5213.1-5292.4" + attribute \src "ls180.v:5082.1-5161.4" wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:5213.1-5292.4" + attribute \src "ls180.v:5082.1-5161.4" wire $0\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:5153.1-5160.4" + attribute \src "ls180.v:5022.1-5029.4" wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_sdcore_data_count[31:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdcore_data_done[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdcore_data_error[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdmem2block_converter_mux[2:0] - attribute \src "ls180.v:5791.1-5819.4" + attribute \src "ls180.v:5660.1-5688.4" wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 64 $0\main_sdmem2block_dma_data[63:0] - attribute \src "ls180.v:5705.1-5742.4" + attribute \src "ls180.v:5574.1-5611.4" wire width 64 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] - attribute \src "ls180.v:5705.1-5742.4" + attribute \src "ls180.v:5574.1-5611.4" wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:5743.1-5779.4" + attribute \src "ls180.v:5612.1-5648.4" wire $0\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:5743.1-5779.4" + attribute \src "ls180.v:5612.1-5648.4" wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:5743.1-5779.4" + attribute \src "ls180.v:5612.1-5648.4" wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:5743.1-5779.4" + attribute \src "ls180.v:5612.1-5648.4" wire $0\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:5743.1-5779.4" + attribute \src "ls180.v:5612.1-5648.4" wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:5705.1-5742.4" + attribute \src "ls180.v:5574.1-5611.4" wire $0\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:5743.1-5779.4" + attribute \src "ls180.v:5612.1-5648.4" wire $0\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1770.5-1770.45" + attribute \src "ls180.v:1681.5-1681.45" wire $0\main_sdmem2block_dma_source_first[0:0] - attribute \src "ls180.v:5705.1-5742.4" + attribute \src "ls180.v:5574.1-5611.4" wire $0\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:5705.1-5742.4" + attribute \src "ls180.v:5574.1-5611.4" wire width 64 $0\main_sdmem2block_dma_source_payload_data[63:0] - attribute \src "ls180.v:5705.1-5742.4" + attribute \src "ls180.v:5574.1-5611.4" wire $0\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 5 $0\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 6 $0\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 5 $0\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1826.5-1826.41" + attribute \src "ls180.v:1737.5-1737.41" wire $0\main_sdmem2block_fifo_replace[0:0] - attribute \src "ls180.v:5833.1-5840.4" + attribute \src "ls180.v:5702.1-5709.4" wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:4559.1-4587.4" + attribute \src "ls180.v:4428.1-4456.4" wire $0\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 9 $0\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 9 $0\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1291.5-1291.53" + attribute \src "ls180.v:1202.5-1202.53" wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] - attribute \src "ls180.v:1292.5-1292.52" + attribute \src "ls180.v:1203.5-1203.52" wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1272.5-1272.46" + attribute \src "ls180.v:1183.5-1183.46" wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:4733.1-4826.4" + attribute \src "ls180.v:4602.1-4695.4" wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:4733.1-4826.4" + attribute \src "ls180.v:4602.1-4695.4" wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:4733.1-4826.4" + attribute \src "ls180.v:4602.1-4695.4" wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:4733.1-4826.4" + attribute \src "ls180.v:4602.1-4695.4" wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:4733.1-4826.4" + attribute \src "ls180.v:4602.1-4695.4" wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1245.5-1245.49" + attribute \src "ls180.v:1156.5-1156.49" wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1246.5-1246.48" + attribute \src "ls180.v:1157.5-1157.48" wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1247.5-1247.55" + attribute \src "ls180.v:1158.5-1158.55" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1249.5-1249.57" + attribute \src "ls180.v:1160.5-1160.57" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1250.5-1250.58" + attribute \src "ls180.v:1161.5-1161.58" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1252.11-1252.64" + attribute \src "ls180.v:1163.11-1163.64" wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1253.5-1253.59" + attribute \src "ls180.v:1164.5-1164.59" wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4733.1-4826.4" + attribute \src "ls180.v:4602.1-4695.4" wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4733.1-4826.4" + attribute \src "ls180.v:4602.1-4695.4" wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4733.1-4826.4" + attribute \src "ls180.v:4602.1-4695.4" wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1258.11-1258.57" + attribute \src "ls180.v:1169.11-1169.57" wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1259.5-1259.52" + attribute \src "ls180.v:1170.5-1170.52" wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:4733.1-4826.4" + attribute \src "ls180.v:4602.1-4695.4" wire $0\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:4733.1-4826.4" + attribute \src "ls180.v:4602.1-4695.4" wire $0\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:4733.1-4826.4" + attribute \src "ls180.v:4602.1-4695.4" wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:4733.1-4826.4" + attribute \src "ls180.v:4602.1-4695.4" wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:4733.1-4826.4" + attribute \src "ls180.v:4602.1-4695.4" wire $0\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:4733.1-4826.4" + attribute \src "ls180.v:4602.1-4695.4" wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:4733.1-4826.4" + attribute \src "ls180.v:4602.1-4695.4" wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:4623.1-4699.4" + attribute \src "ls180.v:4492.1-4568.4" wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:4623.1-4699.4" + attribute \src "ls180.v:4492.1-4568.4" wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:4623.1-4699.4" + attribute \src "ls180.v:4492.1-4568.4" wire $0\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:4623.1-4699.4" + attribute \src "ls180.v:4492.1-4568.4" wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4623.1-4699.4" + attribute \src "ls180.v:4492.1-4568.4" wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4623.1-4699.4" + attribute \src "ls180.v:4492.1-4568.4" wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1235.11-1235.57" + attribute \src "ls180.v:1146.11-1146.57" wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1236.5-1236.52" + attribute \src "ls180.v:1147.5-1147.52" wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:4623.1-4699.4" + attribute \src "ls180.v:4492.1-4568.4" wire $0\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 10 $0\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:4994.1-5095.4" + attribute \src "ls180.v:4863.1-4964.4" wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:4994.1-5095.4" + attribute \src "ls180.v:4863.1-4964.4" wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1447.5-1447.55" + attribute \src "ls180.v:1358.5-1358.55" wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] - attribute \src "ls180.v:1448.5-1448.54" + attribute \src "ls180.v:1359.5-1359.54" wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1428.5-1428.48" + attribute \src "ls180.v:1339.5-1339.48" wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:4994.1-5095.4" + attribute \src "ls180.v:4863.1-4964.4" wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:4994.1-5095.4" + attribute \src "ls180.v:4863.1-4964.4" wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:4994.1-5095.4" + attribute \src "ls180.v:4863.1-4964.4" wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1399.5-1399.50" + attribute \src "ls180.v:1310.5-1310.50" wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1400.5-1400.49" + attribute \src "ls180.v:1311.5-1311.49" wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1401.5-1401.56" + attribute \src "ls180.v:1312.5-1312.56" wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1403.5-1403.58" + attribute \src "ls180.v:1314.5-1314.58" wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1404.5-1404.59" + attribute \src "ls180.v:1315.5-1315.59" wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1406.11-1406.65" + attribute \src "ls180.v:1317.11-1317.65" wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1407.5-1407.60" + attribute \src "ls180.v:1318.5-1318.60" wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4994.1-5095.4" + attribute \src "ls180.v:4863.1-4964.4" wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1410.5-1410.51" + attribute \src "ls180.v:1321.5-1321.51" wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1411.5-1411.52" + attribute \src "ls180.v:1322.5-1322.52" wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1412.11-1412.58" + attribute \src "ls180.v:1323.11-1323.58" wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1413.5-1413.53" + attribute \src "ls180.v:1324.5-1324.53" wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:4994.1-5095.4" + attribute \src "ls180.v:4863.1-4964.4" wire $0\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1420.5-1420.41" + attribute \src "ls180.v:1331.5-1331.41" wire $0\main_sdphy_datar_source_first[0:0] - attribute \src "ls180.v:4994.1-5095.4" + attribute \src "ls180.v:4863.1-4964.4" wire $0\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:4994.1-5095.4" + attribute \src "ls180.v:4863.1-4964.4" wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:4994.1-5095.4" + attribute \src "ls180.v:4863.1-4964.4" wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:4994.1-5095.4" + attribute \src "ls180.v:4863.1-4964.4" wire $0\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:4994.1-5095.4" + attribute \src "ls180.v:4863.1-4964.4" wire $0\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:4994.1-5095.4" + attribute \src "ls180.v:4863.1-4964.4" wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:4994.1-5095.4" + attribute \src "ls180.v:4863.1-4964.4" wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:4888.1-4960.4" + attribute \src "ls180.v:4757.1-4829.4" wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:4888.1-4960.4" + attribute \src "ls180.v:4757.1-4829.4" wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1369.5-1369.54" + attribute \src "ls180.v:1280.5-1280.54" wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] - attribute \src "ls180.v:1370.5-1370.53" + attribute \src "ls180.v:1281.5-1281.53" wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1350.5-1350.47" + attribute \src "ls180.v:1261.5-1261.47" wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:4860.1-4887.4" + attribute \src "ls180.v:4729.1-4756.4" wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:4860.1-4887.4" + attribute \src "ls180.v:4729.1-4756.4" wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:4860.1-4887.4" + attribute \src "ls180.v:4729.1-4756.4" wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:4860.1-4887.4" + attribute \src "ls180.v:4729.1-4756.4" wire $0\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1337.5-1337.50" + attribute \src "ls180.v:1248.5-1248.50" wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1338.5-1338.49" + attribute \src "ls180.v:1249.5-1249.49" wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1339.5-1339.56" + attribute \src "ls180.v:1250.5-1250.56" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1340.5-1340.58" + attribute \src "ls180.v:1251.5-1251.58" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] - attribute \src "ls180.v:1341.5-1341.58" + attribute \src "ls180.v:1252.5-1252.58" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1342.5-1342.59" + attribute \src "ls180.v:1253.5-1253.59" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1343.11-1343.65" + attribute \src "ls180.v:1254.11-1254.65" wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] - attribute \src "ls180.v:1344.11-1344.65" + attribute \src "ls180.v:1255.11-1255.65" wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1345.5-1345.60" + attribute \src "ls180.v:1256.5-1256.60" wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:1335.5-1335.50" + attribute \src "ls180.v:1246.5-1246.50" wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] - attribute \src "ls180.v:4888.1-4960.4" + attribute \src "ls180.v:4757.1-4829.4" wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1324.5-1324.51" + attribute \src "ls180.v:1235.5-1235.51" wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1325.5-1325.52" + attribute \src "ls180.v:1236.5-1236.52" wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4888.1-4960.4" + attribute \src "ls180.v:4757.1-4829.4" wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4888.1-4960.4" + attribute \src "ls180.v:4757.1-4829.4" wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:4888.1-4960.4" + attribute \src "ls180.v:4757.1-4829.4" wire $0\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:5395.1-5585.4" + attribute \src "ls180.v:5264.1-5454.4" wire $0\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:4888.1-4960.4" + attribute \src "ls180.v:4757.1-4829.4" wire $0\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:4888.1-4960.4" + attribute \src "ls180.v:4757.1-4829.4" wire $0\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:4860.1-4887.4" + attribute \src "ls180.v:4729.1-4756.4" wire $0\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_sdphy_init_count[7:0] - attribute \src "ls180.v:4589.1-4622.4" + attribute \src "ls180.v:4458.1-4491.4" wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:4589.1-4622.4" + attribute \src "ls180.v:4458.1-4491.4" wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1217.5-1217.40" + attribute \src "ls180.v:1128.5-1128.40" wire $0\main_sdphy_init_initialize_w[0:0] - attribute \src "ls180.v:4589.1-4622.4" + attribute \src "ls180.v:4458.1-4491.4" wire $0\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4589.1-4622.4" + attribute \src "ls180.v:4458.1-4491.4" wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4589.1-4622.4" + attribute \src "ls180.v:4458.1-4491.4" wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4589.1-4622.4" + attribute \src "ls180.v:4458.1-4491.4" wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4589.1-4622.4" + attribute \src "ls180.v:4458.1-4491.4" wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire $0\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire width 4 $0\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_address_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 13 $0\main_sdram_address_storage[12:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 2 $0\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:3364.1-3371.4" + attribute \src "ls180.v:3233.1-3240.4" wire $0\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:539.5-539.64" + attribute \src "ls180.v:450.5-450.64" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:522.5-522.67" + attribute \src "ls180.v:433.5-433.67" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:523.5-523.66" + attribute \src "ls180.v:434.5-434.66" wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3386.1-3393.4" + attribute \src "ls180.v:3255.1-3262.4" wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3353.1-3360.4" + attribute \src "ls180.v:3222.1-3229.4" wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:3402.1-3495.4" + attribute \src "ls180.v:3271.1-3364.4" wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:3402.1-3495.4" + attribute \src "ls180.v:3271.1-3364.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3402.1-3495.4" + attribute \src "ls180.v:3271.1-3364.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3402.1-3495.4" + attribute \src "ls180.v:3271.1-3364.4" wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3402.1-3495.4" + attribute \src "ls180.v:3271.1-3364.4" wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:3402.1-3495.4" + attribute \src "ls180.v:3271.1-3364.4" wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:4051.1-4059.4" + attribute \src "ls180.v:3920.1-3928.4" wire $0\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:3402.1-3495.4" + attribute \src "ls180.v:3271.1-3364.4" wire $0\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:3402.1-3495.4" + attribute \src "ls180.v:3271.1-3364.4" wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:3402.1-3495.4" + attribute \src "ls180.v:3271.1-3364.4" wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:3402.1-3495.4" + attribute \src "ls180.v:3271.1-3364.4" wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 13 $0\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:3402.1-3495.4" + attribute \src "ls180.v:3271.1-3364.4" wire $0\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:3402.1-3495.4" + attribute \src "ls180.v:3271.1-3364.4" wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3402.1-3495.4" + attribute \src "ls180.v:3271.1-3364.4" wire $0\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:581.32-581.76" + attribute \src "ls180.v:492.32-492.76" wire $0\main_sdram_bankmachine0_trascon_ready[0:0] - attribute \src "ls180.v:579.32-579.75" + attribute \src "ls180.v:490.32-490.75" wire $0\main_sdram_bankmachine0_trccon_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:3521.1-3528.4" + attribute \src "ls180.v:3390.1-3397.4" wire $0\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:621.5-621.64" + attribute \src "ls180.v:532.5-532.64" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:604.5-604.67" + attribute \src "ls180.v:515.5-515.67" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:605.5-605.66" + attribute \src "ls180.v:516.5-516.66" wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3543.1-3550.4" + attribute \src "ls180.v:3412.1-3419.4" wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3510.1-3517.4" + attribute \src "ls180.v:3379.1-3386.4" wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:3559.1-3652.4" + attribute \src "ls180.v:3428.1-3521.4" wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:3559.1-3652.4" + attribute \src "ls180.v:3428.1-3521.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3559.1-3652.4" + attribute \src "ls180.v:3428.1-3521.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3559.1-3652.4" + attribute \src "ls180.v:3428.1-3521.4" wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3559.1-3652.4" + attribute \src "ls180.v:3428.1-3521.4" wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:3559.1-3652.4" + attribute \src "ls180.v:3428.1-3521.4" wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:4060.1-4068.4" + attribute \src "ls180.v:3929.1-3937.4" wire $0\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:3559.1-3652.4" + attribute \src "ls180.v:3428.1-3521.4" wire $0\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:3559.1-3652.4" + attribute \src "ls180.v:3428.1-3521.4" wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:3559.1-3652.4" + attribute \src "ls180.v:3428.1-3521.4" wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:3559.1-3652.4" + attribute \src "ls180.v:3428.1-3521.4" wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 13 $0\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:3559.1-3652.4" + attribute \src "ls180.v:3428.1-3521.4" wire $0\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:3559.1-3652.4" + attribute \src "ls180.v:3428.1-3521.4" wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3559.1-3652.4" + attribute \src "ls180.v:3428.1-3521.4" wire $0\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:663.32-663.76" + attribute \src "ls180.v:574.32-574.76" wire $0\main_sdram_bankmachine1_trascon_ready[0:0] - attribute \src "ls180.v:661.32-661.75" + attribute \src "ls180.v:572.32-572.75" wire $0\main_sdram_bankmachine1_trccon_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:3678.1-3685.4" + attribute \src "ls180.v:3547.1-3554.4" wire $0\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:703.5-703.64" + attribute \src "ls180.v:614.5-614.64" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:686.5-686.67" + attribute \src "ls180.v:597.5-597.67" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:687.5-687.66" + attribute \src "ls180.v:598.5-598.66" wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3700.1-3707.4" + attribute \src "ls180.v:3569.1-3576.4" wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3667.1-3674.4" + attribute \src "ls180.v:3536.1-3543.4" wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:3716.1-3809.4" + attribute \src "ls180.v:3585.1-3678.4" wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:3716.1-3809.4" + attribute \src "ls180.v:3585.1-3678.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3716.1-3809.4" + attribute \src "ls180.v:3585.1-3678.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3716.1-3809.4" + attribute \src "ls180.v:3585.1-3678.4" wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3716.1-3809.4" + attribute \src "ls180.v:3585.1-3678.4" wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:3716.1-3809.4" + attribute \src "ls180.v:3585.1-3678.4" wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:4069.1-4077.4" + attribute \src "ls180.v:3938.1-3946.4" wire $0\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:3716.1-3809.4" + attribute \src "ls180.v:3585.1-3678.4" wire $0\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:3716.1-3809.4" + attribute \src "ls180.v:3585.1-3678.4" wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:3716.1-3809.4" + attribute \src "ls180.v:3585.1-3678.4" wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:3716.1-3809.4" + attribute \src "ls180.v:3585.1-3678.4" wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 13 $0\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:3716.1-3809.4" + attribute \src "ls180.v:3585.1-3678.4" wire $0\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:3716.1-3809.4" + attribute \src "ls180.v:3585.1-3678.4" wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3716.1-3809.4" + attribute \src "ls180.v:3585.1-3678.4" wire $0\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:745.32-745.76" + attribute \src "ls180.v:656.32-656.76" wire $0\main_sdram_bankmachine2_trascon_ready[0:0] - attribute \src "ls180.v:743.32-743.75" + attribute \src "ls180.v:654.32-654.75" wire $0\main_sdram_bankmachine2_trccon_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:3835.1-3842.4" + attribute \src "ls180.v:3704.1-3711.4" wire $0\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:785.5-785.64" + attribute \src "ls180.v:696.5-696.64" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:768.5-768.67" + attribute \src "ls180.v:679.5-679.67" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:769.5-769.66" + attribute \src "ls180.v:680.5-680.66" wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3857.1-3864.4" + attribute \src "ls180.v:3726.1-3733.4" wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3824.1-3831.4" + attribute \src "ls180.v:3693.1-3700.4" wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:3873.1-3966.4" + attribute \src "ls180.v:3742.1-3835.4" wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:3873.1-3966.4" + attribute \src "ls180.v:3742.1-3835.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3873.1-3966.4" + attribute \src "ls180.v:3742.1-3835.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3873.1-3966.4" + attribute \src "ls180.v:3742.1-3835.4" wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3873.1-3966.4" + attribute \src "ls180.v:3742.1-3835.4" wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:3873.1-3966.4" + attribute \src "ls180.v:3742.1-3835.4" wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:4078.1-4086.4" + attribute \src "ls180.v:3947.1-3955.4" wire $0\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:3873.1-3966.4" + attribute \src "ls180.v:3742.1-3835.4" wire $0\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:3873.1-3966.4" + attribute \src "ls180.v:3742.1-3835.4" wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:3873.1-3966.4" + attribute \src "ls180.v:3742.1-3835.4" wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:3873.1-3966.4" + attribute \src "ls180.v:3742.1-3835.4" wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 13 $0\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:3873.1-3966.4" + attribute \src "ls180.v:3742.1-3835.4" wire $0\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:3873.1-3966.4" + attribute \src "ls180.v:3742.1-3835.4" wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3873.1-3966.4" + attribute \src "ls180.v:3742.1-3835.4" wire $0\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:827.32-827.76" + attribute \src "ls180.v:738.32-738.76" wire $0\main_sdram_bankmachine3_trascon_ready[0:0] - attribute \src "ls180.v:825.32-825.75" + attribute \src "ls180.v:736.32-736.75" wire $0\main_sdram_bankmachine3_trccon_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:4000.1-4005.4" + attribute \src "ls180.v:3869.1-3874.4" wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:4006.1-4011.4" + attribute \src "ls180.v:3875.1-3880.4" wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:4012.1-4017.4" + attribute \src "ls180.v:3881.1-3886.4" wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:835.5-835.43" + attribute \src "ls180.v:746.5-746.43" wire $0\main_sdram_choose_cmd_cmd_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 2 $0\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:3986.1-3992.4" + attribute \src "ls180.v:3855.1-3861.4" wire width 4 $0\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:833.5-833.48" + attribute \src "ls180.v:744.5-744.48" wire $0\main_sdram_choose_cmd_want_activates[0:0] - attribute \src "ls180.v:832.5-832.43" + attribute \src "ls180.v:743.5-743.43" wire $0\main_sdram_choose_cmd_want_cmds[0:0] - attribute \src "ls180.v:830.5-830.44" + attribute \src "ls180.v:741.5-741.44" wire $0\main_sdram_choose_cmd_want_reads[0:0] - attribute \src "ls180.v:831.5-831.45" + attribute \src "ls180.v:742.5-742.45" wire $0\main_sdram_choose_cmd_want_writes[0:0] - attribute \src "ls180.v:4033.1-4038.4" + attribute \src "ls180.v:3902.1-3907.4" wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:4039.1-4044.4" + attribute \src "ls180.v:3908.1-3913.4" wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:4045.1-4050.4" + attribute \src "ls180.v:3914.1-3919.4" wire $0\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:4091.1-4163.4" + attribute \src "ls180.v:3960.1-4032.4" wire $0\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 2 $0\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:4019.1-4025.4" + attribute \src "ls180.v:3888.1-3894.4" wire width 4 $0\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:4091.1-4163.4" + attribute \src "ls180.v:3960.1-4032.4" wire $0\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:4091.1-4163.4" + attribute \src "ls180.v:3960.1-4032.4" wire $0\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:4091.1-4163.4" + attribute \src "ls180.v:3960.1-4032.4" wire $0\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:3308.1-3338.4" + attribute \src "ls180.v:3177.1-3207.4" wire $0\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 13 $0\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 2 $0\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:483.5-483.42" + attribute \src "ls180.v:394.5-394.42" wire $0\main_sdram_cmd_payload_is_read[0:0] - attribute \src "ls180.v:484.5-484.43" + attribute \src "ls180.v:395.5-395.43" wire $0\main_sdram_cmd_payload_is_write[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:4091.1-4163.4" + attribute \src "ls180.v:3960.1-4032.4" wire $0\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:3308.1-3338.4" + attribute \src "ls180.v:3177.1-3207.4" wire $0\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:419.5-419.38" + attribute \src "ls180.v:330.5-330.38" wire $0\main_sdram_command_issue_w[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_command_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 6 $0\main_sdram_command_storage[5:0] - attribute \src "ls180.v:468.5-468.35" + attribute \src "ls180.v:379.5-379.35" wire $0\main_sdram_dfi_p0_act_n[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 13 $0\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 2 $0\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:4091.1-4163.4" + attribute \src "ls180.v:3960.1-4032.4" wire $0\main_sdram_en0[0:0] - attribute \src "ls180.v:4091.1-4163.4" + attribute \src "ls180.v:3960.1-4032.4" wire $0\main_sdram_en1[0:0] - attribute \src "ls180.v:4187.1-4200.4" + attribute \src "ls180.v:4056.1-4069.4" wire width 16 $0\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:4187.1-4200.4" + attribute \src "ls180.v:4056.1-4069.4" wire width 2 $0\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:369.5-369.36" + attribute \src "ls180.v:280.5-280.36" wire $0\main_sdram_inti_p0_act_n[0:0] - attribute \src "ls180.v:3249.1-3265.4" + attribute \src "ls180.v:3118.1-3134.4" wire $0\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:3249.1-3265.4" + attribute \src "ls180.v:3118.1-3134.4" wire $0\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:3249.1-3265.4" + attribute \src "ls180.v:3118.1-3134.4" wire $0\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire width 16 $0\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire $0\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:3249.1-3265.4" + attribute \src "ls180.v:3118.1-3134.4" wire $0\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire $0\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire width 13 $0\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire width 2 $0\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire $0\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire $0\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire $0\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire $0\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire $0\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire $0\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire $0\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire $0\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire width 16 $0\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire $0\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:866.12-866.36" + attribute \src "ls180.v:777.12-777.36" wire width 13 $0\main_sdram_nop_a[12:0] - attribute \src "ls180.v:867.11-867.35" + attribute \src "ls180.v:778.11-778.35" wire width 2 $0\main_sdram_nop_ba[1:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 4 $0\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:3308.1-3338.4" + attribute \src "ls180.v:3177.1-3207.4" wire $0\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire width 16 $0\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:3191.1-3245.4" + attribute \src "ls180.v:3060.1-3114.4" wire $0\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdram_status[15:0] - attribute \src "ls180.v:869.5-869.31" + attribute \src "ls180.v:780.5-780.31" wire $0\main_sdram_steerer0[0:0] - attribute \src "ls180.v:870.5-870.31" + attribute \src "ls180.v:781.5-781.31" wire $0\main_sdram_steerer1[0:0] - attribute \src "ls180.v:4091.1-4163.4" + attribute \src "ls180.v:3960.1-4032.4" wire width 2 $0\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 4 $0\main_sdram_storage[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:874.32-874.63" + attribute \src "ls180.v:785.32-785.63" wire $0\main_sdram_tfawcon_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 5 $0\main_sdram_time0[4:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 4 $0\main_sdram_time1[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 10 $0\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:872.32-872.63" + attribute \src "ls180.v:783.32-783.63" wire $0\main_sdram_trrdcon_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:3026.1-3072.4" + attribute \src "ls180.v:2937.1-2983.4" wire $0\main_socbushandler_converted_interface_ack[0:0] - attribute \src "ls180.v:921.5-921.54" + attribute \src "ls180.v:832.5-832.54" wire $0\main_socbushandler_converted_interface_err[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_socbushandler_counter[0:0] - attribute \src "ls180.v:3026.1-3072.4" + attribute \src "ls180.v:2937.1-2983.4" wire $0\main_socbushandler_counter_converter2_next_value[0:0] - attribute \src "ls180.v:3026.1-3072.4" + attribute \src "ls180.v:2937.1-2983.4" wire $0\main_socbushandler_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 64 $0\main_socbushandler_dat_r[63:0] - attribute \src "ls180.v:3026.1-3072.4" + attribute \src "ls180.v:2937.1-2983.4" wire $0\main_socbushandler_skip[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_spimaster11_storage[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_spimaster12_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_spimaster16_storage[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_spimaster17_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_spimaster1_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_spimaster1_storage[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_spimaster21_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_spimaster22_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_spimaster23_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_spimaster24_re[0:0] - attribute \src "ls180.v:4420.1-4468.4" + attribute \src "ls180.v:4289.1-4337.4" wire $0\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:4420.1-4468.4" + attribute \src "ls180.v:4289.1-4337.4" wire $0\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_spimaster27_count[2:0] - attribute \src "ls180.v:4420.1-4468.4" + attribute \src "ls180.v:4289.1-4337.4" wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:4420.1-4468.4" + attribute \src "ls180.v:4289.1-4337.4" wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:4420.1-4468.4" + attribute \src "ls180.v:4289.1-4337.4" wire $0\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:4420.1-4468.4" + attribute \src "ls180.v:4289.1-4337.4" wire $0\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:4420.1-4468.4" + attribute \src "ls180.v:4289.1-4337.4" wire $0\main_spimaster2_done[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:4420.1-4468.4" + attribute \src "ls180.v:4289.1-4337.4" wire $0\main_spimaster3_irq[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_spimaster5_miso[7:0] - attribute \src "ls180.v:1108.12-1108.47" + attribute \src "ls180.v:1019.12-1019.47" wire width 16 $0\main_spimaster8_clk_divider[15:0] - attribute \src "ls180.v:6556.1-6561.4" + attribute \src "ls180.v:6362.1-6367.4" wire $0\main_spimaster9_start[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:4479.1-4527.4" + attribute \src "ls180.v:4348.1-4396.4" wire $0\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 16 $0\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_spisdcard_count[2:0] - attribute \src "ls180.v:4479.1-4527.4" + attribute \src "ls180.v:4348.1-4396.4" wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:4479.1-4527.4" + attribute \src "ls180.v:4348.1-4396.4" wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:4479.1-4527.4" + attribute \src "ls180.v:4348.1-4396.4" wire $0\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:4479.1-4527.4" + attribute \src "ls180.v:4348.1-4396.4" wire $0\main_spisdcard_done0[0:0] - attribute \src "ls180.v:4479.1-4527.4" + attribute \src "ls180.v:4348.1-4396.4" wire $0\main_spisdcard_irq[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_spisdcard_miso[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:4479.1-4527.4" + attribute \src "ls180.v:4348.1-4396.4" wire $0\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:4479.1-4527.4" + attribute \src "ls180.v:4348.1-4396.4" wire $0\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 3 $0\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:6602.1-6607.4" + attribute \src "ls180.v:6408.1-6413.4" wire $0\main_spisdcard_start1[0:0] - attribute \src "ls180.v:3100.1-3110.4" - wire width 8 $0\main_sram0_we[7:0] - attribute \src "ls180.v:3114.1-3124.4" - wire width 8 $0\main_sram1_we[7:0] - attribute \src "ls180.v:3128.1-3138.4" - wire width 8 $0\main_sram2_we[7:0] - attribute \src "ls180.v:3142.1-3152.4" - wire width 8 $0\main_sram3_we[7:0] - attribute \src "ls180.v:4327.1-4331.4" + attribute \src "ls180.v:4196.1-4200.4" wire width 2 $0\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:4316.1-4320.4" + attribute \src "ls180.v:4185.1-4189.4" wire width 2 $0\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 2 $0\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_uart_phy_re[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 4 $0\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:957.5-957.38" + attribute \src "ls180.v:868.5-868.38" wire $0\main_uart_phy_source_first[0:0] - attribute \src "ls180.v:958.5-958.37" + attribute \src "ls180.v:869.5-869.37" wire $0\main_uart_phy_source_last[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 32 $0\main_uart_phy_storage[31:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 4 $0\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 8 $0\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:1084.5-1084.27" + attribute \src "ls180.v:995.5-995.27" wire $0\main_uart_reset[0:0] - attribute \src "ls180.v:4321.1-4326.4" + attribute \src "ls180.v:4190.1-4195.4" wire $0\main_uart_rx_clear[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 4 $0\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 5 $0\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 4 $0\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:1066.5-1066.37" + attribute \src "ls180.v:977.5-977.37" wire $0\main_uart_rx_fifo_replace[0:0] - attribute \src "ls180.v:4379.1-4386.4" + attribute \src "ls180.v:4248.1-4255.4" wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_uart_rx_pending[0:0] - attribute \src "ls180.v:4310.1-4315.4" + attribute \src "ls180.v:4179.1-4184.4" wire $0\main_uart_tx_clear[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 4 $0\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 5 $0\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 4 $0\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:1029.5-1029.37" + attribute \src "ls180.v:940.5-940.37" wire $0\main_uart_tx_fifo_replace[0:0] - attribute \src "ls180.v:1012.5-1012.40" + attribute \src "ls180.v:923.5-923.40" wire $0\main_uart_tx_fifo_sink_first[0:0] - attribute \src "ls180.v:1013.5-1013.39" + attribute \src "ls180.v:924.5-924.39" wire $0\main_uart_tx_fifo_sink_last[0:0] - attribute \src "ls180.v:4349.1-4356.4" + attribute \src "ls180.v:4218.1-4225.4" wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_uart_tx_pending[0:0] - attribute \src "ls180.v:4219.1-4265.4" + attribute \src "ls180.v:4088.1-4134.4" wire $0\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:3026.1-3072.4" + attribute \src "ls180.v:2937.1-2983.4" wire width 30 $0\main_wb_sdram_adr[29:0] - attribute \src "ls180.v:3026.1-3072.4" + attribute \src "ls180.v:2937.1-2983.4" wire $0\main_wb_sdram_cyc[0:0] - attribute \src "ls180.v:3014.1-3024.4" + attribute \src "ls180.v:2925.1-2935.4" wire width 32 $0\main_wb_sdram_dat_w[31:0] - attribute \src "ls180.v:3026.1-3072.4" + attribute \src "ls180.v:2937.1-2983.4" wire width 4 $0\main_wb_sdram_sel[3:0] - attribute \src "ls180.v:3026.1-3072.4" + attribute \src "ls180.v:2937.1-2983.4" wire $0\main_wb_sdram_stb[0:0] - attribute \src "ls180.v:3026.1-3072.4" + attribute \src "ls180.v:2937.1-2983.4" wire $0\main_wb_sdram_we[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\main_wdata_consumed[0:0] - attribute \src "ls180.v:10353.1-10371.4" - wire width 6 $0\memadr[5:0] - attribute \src "ls180.v:10381.1-10399.4" - wire width 6 $0\memadr_1[5:0] - attribute \src "ls180.v:10409.1-10427.4" - wire width 6 $0\memadr_2[5:0] - attribute \src "ls180.v:10437.1-10455.4" - wire width 6 $0\memadr_3[5:0] - attribute \src "ls180.v:10465.1-10483.4" - wire width 6 $0\memadr_4[5:0] - attribute \src "ls180.v:10493.1-10497.4" + attribute \src "ls180.v:10144.1-10162.4" + wire width 4 $0\memadr[3:0] + attribute \src "ls180.v:10172.1-10190.4" + wire width 4 $0\memadr_1[3:0] + attribute \src "ls180.v:10200.1-10204.4" wire width 25 $0\memdat[24:0] - attribute \src "ls180.v:10507.1-10511.4" + attribute \src "ls180.v:10214.1-10218.4" wire width 25 $0\memdat_1[24:0] - attribute \src "ls180.v:10521.1-10525.4" + attribute \src "ls180.v:10228.1-10232.4" wire width 25 $0\memdat_2[24:0] - attribute \src "ls180.v:10535.1-10539.4" + attribute \src "ls180.v:10242.1-10246.4" wire width 25 $0\memdat_3[24:0] - attribute \src "ls180.v:10550.1-10554.4" + attribute \src "ls180.v:10257.1-10261.4" wire width 10 $0\memdat_4[9:0] - attribute \src "ls180.v:10556.1-10559.4" + attribute \src "ls180.v:10263.1-10266.4" wire width 10 $0\memdat_5[9:0] - attribute \src "ls180.v:10567.1-10571.4" + attribute \src "ls180.v:10274.1-10278.4" wire width 10 $0\memdat_6[9:0] - attribute \src "ls180.v:10573.1-10576.4" + attribute \src "ls180.v:10280.1-10283.4" wire width 10 $0\memdat_7[9:0] - attribute \src "ls180.v:10583.1-10587.4" + attribute \src "ls180.v:10290.1-10294.4" wire width 10 $0\memdat_8[9:0] - attribute \src "ls180.v:10597.1-10601.4" + attribute \src "ls180.v:10304.1-10308.4" wire width 10 $0\memdat_9[9:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire width 2 $0\pwm[1:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire $0\sdcard_clk[0:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire $0\sdcard_cmd_o[0:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire $0\sdcard_cmd_oe[0:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire width 4 $0\sdcard_data_o[3:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire $0\sdcard_data_oe[0:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire width 13 $0\sdram_a[12:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire width 2 $0\sdram_ba[1:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire $0\sdram_cas_n[0:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire $0\sdram_cke[0:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire $0\sdram_clock[0:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire $0\sdram_cs_n[0:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire width 2 $0\sdram_dm[1:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire width 16 $0\sdram_dq_o[15:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire $0\sdram_dq_oe[0:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire $0\sdram_ras_n[0:0] - attribute \src "ls180.v:7633.1-7703.4" + attribute \src "ls180.v:7439.1-7509.4" wire $0\sdram_we_n[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\spimaster_clk[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\spimaster_cs_n[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\spimaster_mosi[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\spisdcard_clk[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\spisdcard_cs_n[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\spisdcard_mosi[0:0] - attribute \src "ls180.v:7705.1-10349.4" + attribute \src "ls180.v:7511.1-10140.4" wire $0\uart_tx[0:0] - attribute \src "ls180.v:1857.11-1857.49" + attribute \src "ls180.v:1768.11-1768.49" wire width 3 $1\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:1856.11-1856.44" + attribute \src "ls180.v:1767.11-1767.44" wire width 3 $1\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:1859.11-1859.49" + attribute \src "ls180.v:1770.11-1770.49" wire width 3 $1\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:1858.11-1858.44" + attribute \src "ls180.v:1769.11-1769.44" wire width 3 $1\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:1861.11-1861.49" + attribute \src "ls180.v:1772.11-1772.49" wire width 3 $1\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:1860.11-1860.44" + attribute \src "ls180.v:1771.11-1771.44" wire width 3 $1\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:1863.11-1863.49" + attribute \src "ls180.v:1774.11-1774.49" wire width 3 $1\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:1862.11-1862.44" + attribute \src "ls180.v:1773.11-1773.44" wire width 3 $1\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:2716.5-2716.41" + attribute \src "ls180.v:2627.5-2627.41" wire $1\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:2729.5-2729.42" + attribute \src "ls180.v:2640.5-2640.42" wire $1\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:2730.5-2730.42" + attribute \src "ls180.v:2641.5-2641.42" wire $1\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:2734.12-2734.50" + attribute \src "ls180.v:2645.12-2645.50" wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:2735.5-2735.42" + attribute \src "ls180.v:2646.5-2646.42" wire $1\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:2736.5-2736.42" + attribute \src "ls180.v:2647.5-2647.42" wire $1\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:2737.12-2737.50" + attribute \src "ls180.v:2648.12-2648.50" wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:2738.5-2738.42" + attribute \src "ls180.v:2649.5-2649.42" wire $1\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:2739.5-2739.42" + attribute \src "ls180.v:2650.5-2650.42" wire $1\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:2740.12-2740.50" + attribute \src "ls180.v:2651.12-2651.50" wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:2741.5-2741.42" + attribute \src "ls180.v:2652.5-2652.42" wire $1\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:2717.12-2717.49" + attribute \src "ls180.v:2628.12-2628.49" wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2742.5-2742.42" + attribute \src "ls180.v:2653.5-2653.42" wire $1\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:2743.12-2743.50" + attribute \src "ls180.v:2654.12-2654.50" wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:2744.5-2744.42" + attribute \src "ls180.v:2655.5-2655.42" wire $1\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:2745.5-2745.42" + attribute \src "ls180.v:2656.5-2656.42" wire $1\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:2746.12-2746.50" + attribute \src "ls180.v:2657.12-2657.50" wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:2747.12-2747.50" + attribute \src "ls180.v:2658.12-2658.50" wire width 64 $1\builder_comb_rhs_array_muxed25[63:0] - attribute \src "ls180.v:2748.11-2748.48" + attribute \src "ls180.v:2659.11-2659.48" wire width 8 $1\builder_comb_rhs_array_muxed26[7:0] - attribute \src "ls180.v:2749.5-2749.42" + attribute \src "ls180.v:2660.5-2660.42" wire $1\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:2750.5-2750.42" + attribute \src "ls180.v:2661.5-2661.42" wire $1\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:2751.5-2751.42" + attribute \src "ls180.v:2662.5-2662.42" wire $1\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:2718.11-2718.47" + attribute \src "ls180.v:2629.11-2629.47" wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:2752.11-2752.48" + attribute \src "ls180.v:2663.11-2663.48" wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:2753.11-2753.48" + attribute \src "ls180.v:2664.11-2664.48" wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:2719.5-2719.41" + attribute \src "ls180.v:2630.5-2630.41" wire $1\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2720.5-2720.41" + attribute \src "ls180.v:2631.5-2631.41" wire $1\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2721.5-2721.41" + attribute \src "ls180.v:2632.5-2632.41" wire $1\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2725.5-2725.41" + attribute \src "ls180.v:2636.5-2636.41" wire $1\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:2726.12-2726.49" + attribute \src "ls180.v:2637.12-2637.49" wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:2727.11-2727.47" + attribute \src "ls180.v:2638.11-2638.47" wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:2728.5-2728.41" + attribute \src "ls180.v:2639.5-2639.41" wire $1\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:2722.5-2722.39" + attribute \src "ls180.v:2633.5-2633.39" wire $1\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:2723.5-2723.39" + attribute \src "ls180.v:2634.5-2634.39" wire $1\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:2724.5-2724.39" + attribute \src "ls180.v:2635.5-2635.39" wire $1\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:2731.5-2731.39" + attribute \src "ls180.v:2642.5-2642.39" wire $1\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:2732.5-2732.39" + attribute \src "ls180.v:2643.5-2643.39" wire $1\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:2733.5-2733.39" + attribute \src "ls180.v:2644.5-2644.39" wire $1\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:1843.5-1843.41" + attribute \src "ls180.v:1754.5-1754.41" wire $1\builder_converter0_next_state[0:0] - attribute \src "ls180.v:1842.5-1842.36" + attribute \src "ls180.v:1753.5-1753.36" wire $1\builder_converter0_state[0:0] - attribute \src "ls180.v:1847.5-1847.41" + attribute \src "ls180.v:1758.5-1758.41" wire $1\builder_converter1_next_state[0:0] - attribute \src "ls180.v:1846.5-1846.36" + attribute \src "ls180.v:1757.5-1757.36" wire $1\builder_converter1_state[0:0] - attribute \src "ls180.v:1851.5-1851.41" + attribute \src "ls180.v:1762.5-1762.41" wire $1\builder_converter2_next_state[0:0] - attribute \src "ls180.v:1850.5-1850.36" + attribute \src "ls180.v:1761.5-1761.36" wire $1\builder_converter2_state[0:0] - attribute \src "ls180.v:1888.5-1888.40" + attribute \src "ls180.v:1799.5-1799.40" wire $1\builder_converter_next_state[0:0] - attribute \src "ls180.v:1887.5-1887.35" + attribute \src "ls180.v:1798.5-1798.35" wire $1\builder_converter_state[0:0] - attribute \src "ls180.v:2016.12-2016.39" + attribute \src "ls180.v:1927.12-1927.39" wire width 20 $1\builder_count[19:0] - attribute \src "ls180.v:2013.5-2013.25" + attribute \src "ls180.v:1924.5-1924.25" wire $1\builder_error[0:0] - attribute \src "ls180.v:2010.11-2010.31" + attribute \src "ls180.v:1921.11-1921.31" wire width 3 $1\builder_grant[2:0] - attribute \src "ls180.v:2020.11-2020.51" + attribute \src "ls180.v:1931.11-1931.51" wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2522.11-2522.52" + attribute \src "ls180.v:2433.11-2433.52" wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2555.11-2555.52" + attribute \src "ls180.v:2466.11-2466.52" wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2596.11-2596.52" + attribute \src "ls180.v:2507.11-2507.52" wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2661.11-2661.52" + attribute \src "ls180.v:2572.11-2572.52" wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2686.11-2686.52" + attribute \src "ls180.v:2597.11-2597.52" wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2061.11-2061.51" + attribute \src "ls180.v:1972.11-1972.51" wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2090.11-2090.51" + attribute \src "ls180.v:2001.11-2001.51" wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2103.11-2103.51" + attribute \src "ls180.v:2014.11-2014.51" wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2144.11-2144.51" + attribute \src "ls180.v:2055.11-2055.51" wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2185.11-2185.51" + attribute \src "ls180.v:2096.11-2096.51" wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2250.11-2250.51" + attribute \src "ls180.v:2161.11-2161.51" wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2383.11-2383.51" + attribute \src "ls180.v:2294.11-2294.51" wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2464.11-2464.51" + attribute \src "ls180.v:2375.11-2375.51" wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2481.11-2481.51" + attribute \src "ls180.v:2392.11-2392.51" wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1975.12-1975.43" + attribute \src "ls180.v:1886.12-1886.43" wire width 14 $1\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:2712.12-2712.55" + attribute \src "ls180.v:2623.12-2623.55" wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:2713.5-2713.50" + attribute \src "ls180.v:2624.5-2624.50" wire $1\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1977.11-1977.43" + attribute \src "ls180.v:1888.11-1888.43" wire width 8 $1\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:2710.11-2710.55" + attribute \src "ls180.v:2621.11-2621.55" wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:2711.5-2711.52" + attribute \src "ls180.v:2622.5-2622.52" wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:1976.5-1976.34" + attribute \src "ls180.v:1887.5-1887.34" wire $1\builder_libresocsim_we[0:0] - attribute \src "ls180.v:2714.5-2714.46" + attribute \src "ls180.v:2625.5-2625.46" wire $1\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:2715.5-2715.49" + attribute \src "ls180.v:2626.5-2626.49" wire $1\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:1985.5-1985.44" + attribute \src "ls180.v:1896.5-1896.44" wire $1\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1981.12-1981.54" + attribute \src "ls180.v:1892.12-1892.54" wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1865.11-1865.48" + attribute \src "ls180.v:1776.11-1776.48" wire width 3 $1\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:1864.11-1864.43" + attribute \src "ls180.v:1775.11-1775.43" wire width 3 $1\builder_multiplexer_state[2:0] - attribute \src "ls180.v:2819.32-2819.66" + attribute \src "ls180.v:2730.32-2730.66" wire $1\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:2820.32-2820.66" + attribute \src "ls180.v:2731.32-2731.66" wire $1\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:2839.32-2839.67" + attribute \src "ls180.v:2750.32-2750.67" wire $1\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:2840.32-2840.67" + attribute \src "ls180.v:2751.32-2751.67" wire $1\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:2841.32-2841.67" + attribute \src "ls180.v:2752.32-2752.67" wire $1\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:2842.32-2842.67" + attribute \src "ls180.v:2753.32-2753.67" wire $1\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:2843.32-2843.67" + attribute \src "ls180.v:2754.32-2754.67" wire $1\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:2844.32-2844.67" + attribute \src "ls180.v:2755.32-2755.67" wire $1\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:2845.32-2845.67" + attribute \src "ls180.v:2756.32-2756.67" wire $1\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:2846.32-2846.67" + attribute \src "ls180.v:2757.32-2757.67" wire $1\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:2847.32-2847.67" + attribute \src "ls180.v:2758.32-2758.67" wire $1\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:2848.32-2848.67" + attribute \src "ls180.v:2759.32-2759.67" wire $1\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:2849.32-2849.67" + attribute \src "ls180.v:2760.32-2760.67" wire $1\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:2850.32-2850.67" + attribute \src "ls180.v:2761.32-2761.67" wire $1\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:2851.32-2851.67" + attribute \src "ls180.v:2762.32-2762.67" wire $1\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:2852.32-2852.67" + attribute \src "ls180.v:2763.32-2763.67" wire $1\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:2821.32-2821.66" + attribute \src "ls180.v:2732.32-2732.66" wire $1\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:2822.32-2822.66" + attribute \src "ls180.v:2733.32-2733.66" wire $1\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:2823.32-2823.66" + attribute \src "ls180.v:2734.32-2734.66" wire $1\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:2824.32-2824.66" + attribute \src "ls180.v:2735.32-2735.66" wire $1\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:2825.32-2825.66" + attribute \src "ls180.v:2736.32-2736.66" wire $1\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:2826.32-2826.66" + attribute \src "ls180.v:2737.32-2737.66" wire $1\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:2827.32-2827.66" + attribute \src "ls180.v:2738.32-2738.66" wire $1\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:2828.32-2828.66" + attribute \src "ls180.v:2739.32-2739.66" wire $1\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:2829.32-2829.66" + attribute \src "ls180.v:2740.32-2740.66" wire $1\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:2830.32-2830.66" + attribute \src "ls180.v:2741.32-2741.66" wire $1\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:2831.32-2831.66" + attribute \src "ls180.v:2742.32-2742.66" wire $1\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:2832.32-2832.66" + attribute \src "ls180.v:2743.32-2743.66" wire $1\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:2833.32-2833.66" + attribute \src "ls180.v:2744.32-2744.66" wire $1\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:2834.32-2834.66" + attribute \src "ls180.v:2745.32-2745.66" wire $1\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:2835.32-2835.66" + attribute \src "ls180.v:2746.32-2746.66" wire $1\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:2836.32-2836.66" + attribute \src "ls180.v:2747.32-2747.66" wire $1\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:2837.32-2837.66" + attribute \src "ls180.v:2748.32-2748.66" wire $1\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:2838.32-2838.66" + attribute \src "ls180.v:2749.32-2749.66" wire $1\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:1883.5-1883.43" + attribute \src "ls180.v:1794.5-1794.43" wire $1\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:1884.5-1884.43" + attribute \src "ls180.v:1795.5-1795.43" wire $1\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:1885.5-1885.43" + attribute \src "ls180.v:1796.5-1796.43" wire $1\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:1886.5-1886.43" + attribute \src "ls180.v:1797.5-1797.43" wire $1\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:1882.5-1882.42" + attribute \src "ls180.v:1793.5-1793.42" wire $1\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:2709.11-2709.36" + attribute \src "ls180.v:2620.11-2620.36" wire width 2 $1\builder_next_state[1:0] - attribute \src "ls180.v:1855.11-1855.46" + attribute \src "ls180.v:1766.11-1766.46" wire width 2 $1\builder_refresher_next_state[1:0] - attribute \src "ls180.v:1854.11-1854.41" + attribute \src "ls180.v:1765.11-1765.41" wire width 2 $1\builder_refresher_state[1:0] - attribute \src "ls180.v:1964.11-1964.51" + attribute \src "ls180.v:1875.11-1875.51" wire width 2 $1\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:1963.11-1963.46" + attribute \src "ls180.v:1874.11-1874.46" wire width 2 $1\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:1932.5-1932.57" + attribute \src "ls180.v:1843.5-1843.57" wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:1931.5-1931.52" + attribute \src "ls180.v:1842.5-1842.52" wire $1\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:1944.11-1944.47" + attribute \src "ls180.v:1855.11-1855.47" wire width 3 $1\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:1943.11-1943.42" + attribute \src "ls180.v:1854.11-1854.42" wire width 3 $1\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:1968.5-1968.49" + attribute \src "ls180.v:1879.5-1879.49" wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:1967.5-1967.44" + attribute \src "ls180.v:1878.5-1878.44" wire $1\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:1972.11-1972.65" + attribute \src "ls180.v:1883.11-1883.65" wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:1971.11-1971.60" + attribute \src "ls180.v:1882.11-1882.60" wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:1920.11-1920.46" + attribute \src "ls180.v:1831.11-1831.46" wire width 3 $1\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:1919.11-1919.41" + attribute \src "ls180.v:1830.11-1830.41" wire width 3 $1\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:1908.11-1908.52" + attribute \src "ls180.v:1819.11-1819.52" wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:1907.11-1907.47" + attribute \src "ls180.v:1818.11-1818.47" wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:1904.11-1904.52" + attribute \src "ls180.v:1815.11-1815.52" wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:1903.11-1903.47" + attribute \src "ls180.v:1814.11-1814.47" wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:1916.5-1916.46" + attribute \src "ls180.v:1827.5-1827.46" wire $1\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:1915.5-1915.41" + attribute \src "ls180.v:1826.5-1826.41" wire $1\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:1924.11-1924.53" + attribute \src "ls180.v:1835.11-1835.53" wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:1923.11-1923.48" + attribute \src "ls180.v:1834.11-1834.48" wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:1900.5-1900.46" + attribute \src "ls180.v:1811.5-1811.46" wire $1\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:1899.5-1899.41" + attribute \src "ls180.v:1810.5-1810.41" wire $1\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:2004.5-2004.30" + attribute \src "ls180.v:1915.5-1915.30" wire $1\builder_shared_ack[0:0] - attribute \src "ls180.v:2000.12-2000.40" + attribute \src "ls180.v:1911.12-1911.40" wire width 32 $1\builder_shared_dat_r[31:0] - attribute \src "ls180.v:2011.12-2011.37" - wire width 13 $1\builder_slave_sel[12:0] - attribute \src "ls180.v:2012.12-2012.39" - wire width 13 $1\builder_slave_sel_r[12:0] - attribute \src "ls180.v:1892.11-1892.47" + attribute \src "ls180.v:1922.11-1922.35" + wire width 6 $1\builder_slave_sel[5:0] + attribute \src "ls180.v:1923.11-1923.37" + wire width 6 $1\builder_slave_sel_r[5:0] + attribute \src "ls180.v:1803.11-1803.47" wire width 2 $1\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:1891.11-1891.42" + attribute \src "ls180.v:1802.11-1802.42" wire width 2 $1\builder_spimaster0_state[1:0] - attribute \src "ls180.v:1896.11-1896.47" + attribute \src "ls180.v:1807.11-1807.47" wire width 2 $1\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:1895.11-1895.42" + attribute \src "ls180.v:1806.11-1806.42" wire width 2 $1\builder_spimaster1_state[1:0] - attribute \src "ls180.v:2708.11-2708.31" + attribute \src "ls180.v:2619.11-2619.31" wire width 2 $1\builder_state[1:0] - attribute \src "ls180.v:2761.5-2761.39" + attribute \src "ls180.v:2672.5-2672.39" wire $1\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:2762.5-2762.39" + attribute \src "ls180.v:2673.5-2673.39" wire $1\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:2754.11-2754.47" + attribute \src "ls180.v:2665.11-2665.47" wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:2755.12-2755.49" + attribute \src "ls180.v:2666.12-2666.49" wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2756.5-2756.41" + attribute \src "ls180.v:2667.5-2667.41" wire $1\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:2757.5-2757.41" + attribute \src "ls180.v:2668.5-2668.41" wire $1\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2758.5-2758.41" + attribute \src "ls180.v:2669.5-2669.41" wire $1\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2759.5-2759.41" + attribute \src "ls180.v:2670.5-2670.41" wire $1\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2760.5-2760.41" + attribute \src "ls180.v:2671.5-2671.41" wire $1\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:938.5-938.29" + attribute \src "ls180.v:849.5-849.29" wire $1\main_cmd_consumed[0:0] - attribute \src "ls180.v:321.5-321.35" + attribute \src "ls180.v:232.5-232.35" wire $1\main_converter0_counter[0:0] - attribute \src "ls180.v:1844.5-1844.57" + attribute \src "ls180.v:1755.5-1755.57" wire $1\main_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:1845.5-1845.60" + attribute \src "ls180.v:1756.5-1756.60" wire $1\main_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:323.12-323.41" + attribute \src "ls180.v:234.12-234.41" wire width 64 $1\main_converter0_dat_r[63:0] - attribute \src "ls180.v:320.5-320.32" + attribute \src "ls180.v:231.5-231.32" wire $1\main_converter0_skip[0:0] - attribute \src "ls180.v:336.5-336.35" + attribute \src "ls180.v:247.5-247.35" wire $1\main_converter1_counter[0:0] - attribute \src "ls180.v:1848.5-1848.57" + attribute \src "ls180.v:1759.5-1759.57" wire $1\main_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:1849.5-1849.60" + attribute \src "ls180.v:1760.5-1760.60" wire $1\main_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:338.12-338.41" + attribute \src "ls180.v:249.12-249.41" wire width 64 $1\main_converter1_dat_r[63:0] - attribute \src "ls180.v:335.5-335.32" + attribute \src "ls180.v:246.5-246.32" wire $1\main_converter1_skip[0:0] - attribute \src "ls180.v:935.5-935.34" + attribute \src "ls180.v:846.5-846.34" wire $1\main_converter_counter[0:0] - attribute \src "ls180.v:1889.5-1889.55" + attribute \src "ls180.v:1800.5-1800.55" wire $1\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:1890.5-1890.58" + attribute \src "ls180.v:1801.5-1801.58" wire $1\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:937.12-937.40" + attribute \src "ls180.v:848.12-848.40" wire width 32 $1\main_converter_dat_r[31:0] - attribute \src "ls180.v:934.5-934.31" + attribute \src "ls180.v:845.5-845.31" wire $1\main_converter_skip[0:0] - attribute \src "ls180.v:357.12-357.38" + attribute \src "ls180.v:268.12-268.38" wire width 16 $1\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:358.5-358.36" + attribute \src "ls180.v:269.5-269.36" wire $1\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:1175.12-1175.30" + attribute \src "ls180.v:1086.12-1086.30" wire width 24 $1\main_dummy[23:0] - attribute \src "ls180.v:1086.12-1086.49" + attribute \src "ls180.v:997.12-997.49" wire width 16 $1\main_gpiotristateasic0_status[15:0] - attribute \src "ls180.v:1092.5-1092.40" + attribute \src "ls180.v:1003.5-1003.40" wire $1\main_gpiotristateasic1_oe_re[0:0] - attribute \src "ls180.v:1091.12-1091.53" + attribute \src "ls180.v:1002.12-1002.53" wire width 16 $1\main_gpiotristateasic1_oe_storage[15:0] - attribute \src "ls180.v:1096.5-1096.41" + attribute \src "ls180.v:1007.5-1007.41" wire $1\main_gpiotristateasic1_out_re[0:0] - attribute \src "ls180.v:1095.12-1095.54" + attribute \src "ls180.v:1006.12-1006.54" wire width 16 $1\main_gpiotristateasic1_out_storage[15:0] - attribute \src "ls180.v:1093.12-1093.49" + attribute \src "ls180.v:1004.12-1004.49" wire width 16 $1\main_gpiotristateasic1_status[15:0] - attribute \src "ls180.v:1200.5-1200.23" + attribute \src "ls180.v:1111.5-1111.23" wire $1\main_i2c_re[0:0] - attribute \src "ls180.v:1199.11-1199.34" + attribute \src "ls180.v:1110.11-1110.34" wire width 3 $1\main_i2c_storage[2:0] - attribute \src "ls180.v:342.5-342.24" + attribute \src "ls180.v:253.5-253.24" wire $1\main_int_rst[0:0] - attribute \src "ls180.v:315.5-315.51" + attribute \src "ls180.v:226.5-226.51" wire $1\main_interface0_converted_interface_ack[0:0] - attribute \src "ls180.v:255.5-255.39" - wire $1\main_interface0_ram_bus_ack[0:0] - attribute \src "ls180.v:1748.12-1748.43" + attribute \src "ls180.v:1659.12-1659.43" wire width 32 $1\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1752.5-1752.35" + attribute \src "ls180.v:1663.5-1663.35" wire $1\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1751.11-1751.41" + attribute \src "ls180.v:1662.11-1662.41" wire width 8 $1\main_interface1_bus_sel[7:0] - attribute \src "ls180.v:1753.5-1753.35" + attribute \src "ls180.v:1664.5-1664.35" wire $1\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:1755.5-1755.34" + attribute \src "ls180.v:1666.5-1666.34" wire $1\main_interface1_bus_we[0:0] - attribute \src "ls180.v:330.5-330.51" + attribute \src "ls180.v:241.5-241.51" wire $1\main_interface1_converted_interface_ack[0:0] - attribute \src "ls180.v:270.5-270.39" - wire $1\main_interface1_ram_bus_ack[0:0] - attribute \src "ls180.v:285.5-285.39" - wire $1\main_interface2_ram_bus_ack[0:0] - attribute \src "ls180.v:300.5-300.39" - wire $1\main_interface3_ram_bus_ack[0:0] attribute \src "ls180.v:63.12-63.47" wire width 32 $1\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:227.5-227.34" + attribute \src "ls180.v:183.5-183.34" wire $1\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:226.5-226.39" + attribute \src "ls180.v:182.5-182.39" wire $1\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:247.5-247.44" + attribute \src "ls180.v:203.5-203.44" wire $1\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:246.5-246.49" + attribute \src "ls180.v:202.5-202.49" wire $1\main_libresocsim_eventmanager_storage[0:0] attribute \src "ls180.v:65.12-65.55" wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] @@ -241813,15 +241637,15 @@ module \ls180 wire $1\main_libresocsim_libresoc_xics_ics_stb[0:0] attribute \src "ls180.v:104.5-104.49" wire $1\main_libresocsim_libresoc_xics_ics_we[0:0] - attribute \src "ls180.v:223.5-223.36" + attribute \src "ls180.v:179.5-179.36" wire $1\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:222.12-222.49" + attribute \src "ls180.v:178.12-178.49" wire width 32 $1\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:213.5-213.40" + attribute \src "ls180.v:169.5-169.40" wire $1\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:225.5-225.38" + attribute \src "ls180.v:181.5-181.38" wire $1\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:224.12-224.51" + attribute \src "ls180.v:180.12-180.51" wire width 32 $1\main_libresocsim_reload_storage[31:0] attribute \src "ls180.v:56.5-56.37" wire $1\main_libresocsim_reset_re[0:0] @@ -241831,8760 +241655,8360 @@ module \ls180 wire $1\main_libresocsim_scratch_re[0:0] attribute \src "ls180.v:57.12-57.60" wire width 32 $1\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:229.5-229.44" + attribute \src "ls180.v:185.5-185.44" wire $1\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:228.5-228.49" + attribute \src "ls180.v:184.5-184.49" wire $1\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:248.12-248.42" + attribute \src "ls180.v:204.12-204.42" wire width 32 $1\main_libresocsim_value[31:0] - attribute \src "ls180.v:230.12-230.49" + attribute \src "ls180.v:186.12-186.49" wire width 32 $1\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:220.11-220.37" + attribute \src "ls180.v:176.11-176.37" wire width 8 $1\main_libresocsim_we[7:0] - attribute \src "ls180.v:236.5-236.39" + attribute \src "ls180.v:192.5-192.39" wire $1\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:237.5-237.45" + attribute \src "ls180.v:193.5-193.45" wire $1\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:234.5-234.41" + attribute \src "ls180.v:190.5-190.41" wire $1\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:926.12-926.40" + attribute \src "ls180.v:837.12-837.40" wire width 30 $1\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:930.5-930.32" + attribute \src "ls180.v:841.5-841.32" wire $1\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:927.12-927.42" + attribute \src "ls180.v:838.12-838.42" wire width 16 $1\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:929.11-929.38" + attribute \src "ls180.v:840.11-840.38" wire width 2 $1\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:931.5-931.32" + attribute \src "ls180.v:842.5-842.32" wire $1\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:933.5-933.31" + attribute \src "ls180.v:844.5-844.31" wire $1\main_litedram_wb_we[0:0] - attribute \src "ls180.v:1179.12-1179.37" + attribute \src "ls180.v:1090.12-1090.37" wire width 32 $1\main_pwm0_counter[31:0] - attribute \src "ls180.v:1181.5-1181.31" + attribute \src "ls180.v:1092.5-1092.31" wire $1\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:1180.5-1180.36" + attribute \src "ls180.v:1091.5-1091.36" wire $1\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:1185.5-1185.31" + attribute \src "ls180.v:1096.5-1096.31" wire $1\main_pwm0_period_re[0:0] - attribute \src "ls180.v:1184.12-1184.44" + attribute \src "ls180.v:1095.12-1095.44" wire width 32 $1\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:1183.5-1183.30" + attribute \src "ls180.v:1094.5-1094.30" wire $1\main_pwm0_width_re[0:0] - attribute \src "ls180.v:1182.12-1182.43" + attribute \src "ls180.v:1093.12-1093.43" wire width 32 $1\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:1189.12-1189.37" + attribute \src "ls180.v:1100.12-1100.37" wire width 32 $1\main_pwm1_counter[31:0] - attribute \src "ls180.v:1191.5-1191.31" + attribute \src "ls180.v:1102.5-1102.31" wire $1\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:1190.5-1190.36" + attribute \src "ls180.v:1101.5-1101.36" wire $1\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:1195.5-1195.31" + attribute \src "ls180.v:1106.5-1106.31" wire $1\main_pwm1_period_re[0:0] - attribute \src "ls180.v:1194.12-1194.44" + attribute \src "ls180.v:1105.12-1105.44" wire width 32 $1\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:1193.5-1193.30" + attribute \src "ls180.v:1104.5-1104.30" wire $1\main_pwm1_width_re[0:0] - attribute \src "ls180.v:1192.12-1192.43" + attribute \src "ls180.v:1103.12-1103.43" wire width 32 $1\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:359.11-359.32" + attribute \src "ls180.v:211.5-211.36" + wire $1\main_ram_bus_ram_bus_ack[0:0] + attribute \src "ls180.v:218.11-218.29" + wire width 8 $1\main_ram_we[7:0] + attribute \src "ls180.v:270.11-270.32" wire width 3 $1\main_rddata_en[2:0] - attribute \src "ls180.v:1717.11-1717.50" + attribute \src "ls180.v:1628.11-1628.50" wire width 3 $1\main_sdblock2mem_converter_demux[2:0] - attribute \src "ls180.v:1713.5-1713.51" + attribute \src "ls180.v:1624.5-1624.51" wire $1\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:1714.5-1714.50" + attribute \src "ls180.v:1625.5-1625.50" wire $1\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:1715.12-1715.66" + attribute \src "ls180.v:1626.12-1626.66" wire width 64 $1\main_sdblock2mem_converter_source_payload_data[63:0] - attribute \src "ls180.v:1716.11-1716.77" + attribute \src "ls180.v:1627.11-1627.77" wire width 4 $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1719.5-1719.49" + attribute \src "ls180.v:1630.5-1630.49" wire $1\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:1692.11-1692.47" + attribute \src "ls180.v:1603.11-1603.47" wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:1689.11-1689.45" + attribute \src "ls180.v:1600.11-1600.45" wire width 6 $1\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:1691.11-1691.47" + attribute \src "ls180.v:1602.11-1602.47" wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1693.11-1693.50" + attribute \src "ls180.v:1604.11-1604.50" wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1727.12-1727.62" + attribute \src "ls180.v:1638.12-1638.62" wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:1728.12-1728.60" + attribute \src "ls180.v:1639.12-1639.60" wire width 64 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] - attribute \src "ls180.v:1725.5-1725.45" + attribute \src "ls180.v:1636.5-1636.45" wire $1\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:1735.5-1735.54" + attribute \src "ls180.v:1646.5-1646.54" wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:1734.12-1734.67" + attribute \src "ls180.v:1645.12-1645.67" wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:1739.5-1739.56" + attribute \src "ls180.v:1650.5-1650.56" wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:1738.5-1738.61" + attribute \src "ls180.v:1649.5-1649.61" wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:1737.5-1737.56" + attribute \src "ls180.v:1648.5-1648.56" wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:1736.12-1736.69" + attribute \src "ls180.v:1647.12-1647.69" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:1743.5-1743.54" + attribute \src "ls180.v:1654.5-1654.54" wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:1742.5-1742.59" + attribute \src "ls180.v:1653.5-1653.59" wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:1745.12-1745.61" + attribute \src "ls180.v:1656.12-1656.61" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:1965.12-1965.87" + attribute \src "ls180.v:1876.12-1876.87" wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:1966.5-1966.82" + attribute \src "ls180.v:1877.5-1877.82" wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:1730.5-1730.57" + attribute \src "ls180.v:1641.5-1641.57" wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:1740.5-1740.53" + attribute \src "ls180.v:1651.5-1651.53" wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:1509.5-1509.38" + attribute \src "ls180.v:1420.5-1420.38" wire $1\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:1508.12-1508.51" + attribute \src "ls180.v:1419.12-1419.51" wire width 32 $1\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:1507.5-1507.39" + attribute \src "ls180.v:1418.5-1418.39" wire $1\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:1506.11-1506.51" + attribute \src "ls180.v:1417.11-1417.51" wire width 10 $1\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:1493.5-1493.39" + attribute \src "ls180.v:1404.5-1404.39" wire $1\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:1492.12-1492.52" + attribute \src "ls180.v:1403.12-1403.52" wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:1495.5-1495.38" + attribute \src "ls180.v:1406.5-1406.38" wire $1\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:1494.12-1494.51" + attribute \src "ls180.v:1405.12-1405.51" wire width 32 $1\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:1648.11-1648.39" + attribute \src "ls180.v:1559.11-1559.39" wire width 3 $1\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:1949.11-1949.62" + attribute \src "ls180.v:1860.11-1860.62" wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:1950.5-1950.59" + attribute \src "ls180.v:1861.5-1861.59" wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:1649.5-1649.32" + attribute \src "ls180.v:1560.5-1560.32" wire $1\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:1945.5-1945.55" + attribute \src "ls180.v:1856.5-1856.55" wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:1946.5-1946.58" + attribute \src "ls180.v:1857.5-1857.58" wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:1650.5-1650.33" + attribute \src "ls180.v:1561.5-1561.33" wire $1\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:1953.5-1953.56" + attribute \src "ls180.v:1864.5-1864.56" wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:1954.5-1954.59" + attribute \src "ls180.v:1865.5-1865.59" wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:1500.13-1500.53" + attribute \src "ls180.v:1411.13-1411.53" wire width 128 $1\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:1961.13-1961.76" + attribute \src "ls180.v:1872.13-1872.76" wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:1962.5-1962.69" + attribute \src "ls180.v:1873.5-1873.69" wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1651.5-1651.35" + attribute \src "ls180.v:1562.5-1562.35" wire $1\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:1955.5-1955.58" + attribute \src "ls180.v:1866.5-1866.58" wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:1956.5-1956.61" + attribute \src "ls180.v:1867.5-1867.61" wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:1609.11-1609.47" + attribute \src "ls180.v:1520.11-1520.47" wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:1615.5-1615.46" + attribute \src "ls180.v:1526.5-1526.46" wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:1614.12-1614.54" + attribute \src "ls180.v:1525.12-1525.54" wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:1610.12-1610.58" + attribute \src "ls180.v:1521.12-1521.58" wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:1622.5-1622.46" + attribute \src "ls180.v:1533.5-1533.46" wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:1621.12-1621.54" + attribute \src "ls180.v:1532.12-1532.54" wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:1617.12-1617.58" + attribute \src "ls180.v:1528.12-1528.58" wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:1629.5-1629.46" + attribute \src "ls180.v:1540.5-1540.46" wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:1628.12-1628.54" + attribute \src "ls180.v:1539.12-1539.54" wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:1624.12-1624.58" + attribute \src "ls180.v:1535.12-1535.58" wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:1636.5-1636.46" + attribute \src "ls180.v:1547.5-1547.46" wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:1635.12-1635.54" + attribute \src "ls180.v:1546.12-1546.54" wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:1631.12-1631.58" + attribute \src "ls180.v:1542.12-1542.58" wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:1638.12-1638.53" + attribute \src "ls180.v:1549.12-1549.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:1639.12-1639.53" + attribute \src "ls180.v:1550.12-1550.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:1640.12-1640.53" + attribute \src "ls180.v:1551.12-1551.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:1641.12-1641.53" + attribute \src "ls180.v:1552.12-1552.53" wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:1643.12-1643.51" + attribute \src "ls180.v:1554.12-1554.51" wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:1644.12-1644.51" + attribute \src "ls180.v:1555.12-1555.51" wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:1645.12-1645.51" + attribute \src "ls180.v:1556.12-1556.51" wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:1646.12-1646.51" + attribute \src "ls180.v:1557.12-1557.51" wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:1600.5-1600.48" + attribute \src "ls180.v:1511.5-1511.48" wire $1\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:1601.5-1601.47" + attribute \src "ls180.v:1512.5-1512.47" wire $1\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:1602.11-1602.61" + attribute \src "ls180.v:1513.11-1513.61" wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:1599.5-1599.48" + attribute \src "ls180.v:1510.5-1510.48" wire $1\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:1598.5-1598.48" + attribute \src "ls180.v:1509.5-1509.48" wire $1\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1603.5-1603.50" + attribute \src "ls180.v:1514.5-1514.50" wire $1\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:1608.11-1608.47" + attribute \src "ls180.v:1519.11-1519.47" wire width 8 $1\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:1642.5-1642.43" + attribute \src "ls180.v:1553.5-1553.43" wire $1\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:1565.11-1565.48" + attribute \src "ls180.v:1476.11-1476.48" wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:1941.11-1941.87" + attribute \src "ls180.v:1852.11-1852.87" wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:1942.5-1942.84" + attribute \src "ls180.v:1853.5-1853.84" wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:1570.12-1570.55" + attribute \src "ls180.v:1481.12-1481.55" wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:1566.12-1566.59" + attribute \src "ls180.v:1477.12-1477.59" wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:1577.12-1577.55" + attribute \src "ls180.v:1488.12-1488.55" wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:1573.12-1573.59" + attribute \src "ls180.v:1484.12-1484.59" wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:1584.12-1584.55" + attribute \src "ls180.v:1495.12-1495.55" wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:1580.12-1580.59" + attribute \src "ls180.v:1491.12-1491.59" wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:1591.12-1591.55" + attribute \src "ls180.v:1502.12-1502.55" wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:1587.12-1587.59" + attribute \src "ls180.v:1498.12-1498.59" wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:1594.12-1594.54" + attribute \src "ls180.v:1505.12-1505.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:1933.12-1933.93" + attribute \src "ls180.v:1844.12-1844.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:1934.5-1934.88" + attribute \src "ls180.v:1845.5-1845.88" wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:1595.12-1595.54" + attribute \src "ls180.v:1506.12-1506.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:1935.12-1935.93" + attribute \src "ls180.v:1846.12-1846.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:1936.5-1936.88" + attribute \src "ls180.v:1847.5-1847.88" wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:1596.12-1596.54" + attribute \src "ls180.v:1507.12-1507.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:1937.12-1937.93" + attribute \src "ls180.v:1848.12-1848.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:1938.5-1938.88" + attribute \src "ls180.v:1849.5-1849.88" wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:1597.12-1597.54" + attribute \src "ls180.v:1508.12-1508.54" wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:1939.12-1939.93" + attribute \src "ls180.v:1850.12-1850.93" wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:1940.5-1940.88" + attribute \src "ls180.v:1851.5-1851.88" wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:1556.5-1556.49" + attribute \src "ls180.v:1467.5-1467.49" wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1563.5-1563.50" + attribute \src "ls180.v:1474.5-1474.50" wire $1\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:1564.11-1564.64" + attribute \src "ls180.v:1475.11-1475.64" wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:1561.5-1561.51" + attribute \src "ls180.v:1472.5-1472.51" wire $1\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:1560.5-1560.51" + attribute \src "ls180.v:1471.5-1471.51" wire $1\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:1552.11-1552.47" + attribute \src "ls180.v:1463.11-1463.47" wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:1510.11-1510.51" + attribute \src "ls180.v:1421.11-1421.51" wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:1653.12-1653.42" + attribute \src "ls180.v:1564.12-1564.42" wire width 32 $1\main_sdcore_data_count[31:0] - attribute \src "ls180.v:1951.12-1951.65" + attribute \src "ls180.v:1862.12-1862.65" wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:1952.5-1952.60" + attribute \src "ls180.v:1863.5-1863.60" wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:1654.5-1654.33" + attribute \src "ls180.v:1565.5-1565.33" wire $1\main_sdcore_data_done[0:0] - attribute \src "ls180.v:1947.5-1947.56" + attribute \src "ls180.v:1858.5-1858.56" wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:1948.5-1948.59" + attribute \src "ls180.v:1859.5-1859.59" wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:1655.5-1655.34" + attribute \src "ls180.v:1566.5-1566.34" wire $1\main_sdcore_data_error[0:0] - attribute \src "ls180.v:1957.5-1957.57" + attribute \src "ls180.v:1868.5-1868.57" wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:1958.5-1958.60" + attribute \src "ls180.v:1869.5-1869.60" wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:1656.5-1656.36" + attribute \src "ls180.v:1567.5-1567.36" wire $1\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:1959.5-1959.59" + attribute \src "ls180.v:1870.5-1870.59" wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:1960.5-1960.62" + attribute \src "ls180.v:1871.5-1871.62" wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:1801.11-1801.48" + attribute \src "ls180.v:1712.11-1712.48" wire width 3 $1\main_sdmem2block_converter_mux[2:0] - attribute \src "ls180.v:1799.11-1799.64" + attribute \src "ls180.v:1710.11-1710.64" wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:1775.5-1775.40" + attribute \src "ls180.v:1686.5-1686.40" wire $1\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:1774.12-1774.53" + attribute \src "ls180.v:1685.12-1685.53" wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:1773.12-1773.45" + attribute \src "ls180.v:1684.12-1684.45" wire width 64 $1\main_sdmem2block_dma_data[63:0] - attribute \src "ls180.v:1969.12-1969.75" + attribute \src "ls180.v:1880.12-1880.75" wire width 64 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] - attribute \src "ls180.v:1970.5-1970.70" + attribute \src "ls180.v:1881.5-1881.70" wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1780.5-1780.44" + attribute \src "ls180.v:1691.5-1691.44" wire $1\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:1779.5-1779.42" + attribute \src "ls180.v:1690.5-1690.42" wire $1\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:1778.5-1778.47" + attribute \src "ls180.v:1689.5-1689.47" wire $1\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:1777.5-1777.42" + attribute \src "ls180.v:1688.5-1688.42" wire $1\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:1776.12-1776.55" + attribute \src "ls180.v:1687.12-1687.55" wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:1783.5-1783.40" + attribute \src "ls180.v:1694.5-1694.40" wire $1\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:1782.5-1782.45" + attribute \src "ls180.v:1693.5-1693.45" wire $1\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:1787.12-1787.47" + attribute \src "ls180.v:1698.12-1698.47" wire width 32 $1\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:1973.12-1973.87" + attribute \src "ls180.v:1884.12-1884.87" wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:1974.5-1974.82" + attribute \src "ls180.v:1885.5-1885.82" wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:1766.5-1766.42" + attribute \src "ls180.v:1677.5-1677.42" wire $1\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:1767.12-1767.61" + attribute \src "ls180.v:1678.12-1678.61" wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:1765.5-1765.43" + attribute \src "ls180.v:1676.5-1676.43" wire $1\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:1764.5-1764.43" + attribute \src "ls180.v:1675.5-1675.43" wire $1\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1771.5-1771.44" + attribute \src "ls180.v:1682.5-1682.44" wire $1\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:1772.12-1772.60" + attribute \src "ls180.v:1683.12-1683.60" wire width 64 $1\main_sdmem2block_dma_source_payload_data[63:0] - attribute \src "ls180.v:1768.5-1768.45" + attribute \src "ls180.v:1679.5-1679.45" wire $1\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:1828.11-1828.47" + attribute \src "ls180.v:1739.11-1739.47" wire width 5 $1\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:1825.11-1825.45" + attribute \src "ls180.v:1736.11-1736.45" wire width 6 $1\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:1827.11-1827.47" + attribute \src "ls180.v:1738.11-1738.47" wire width 5 $1\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1829.11-1829.50" + attribute \src "ls180.v:1740.11-1740.50" wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1209.5-1209.35" + attribute \src "ls180.v:1120.5-1120.35" wire $1\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:1212.5-1212.35" + attribute \src "ls180.v:1123.5-1123.35" wire $1\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:1213.5-1213.36" + attribute \src "ls180.v:1124.5-1124.36" wire $1\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:1211.11-1211.41" + attribute \src "ls180.v:1122.11-1122.41" wire width 9 $1\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:1207.5-1207.33" + attribute \src "ls180.v:1118.5-1118.33" wire $1\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:1206.11-1206.46" + attribute \src "ls180.v:1117.11-1117.46" wire width 9 $1\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:1315.5-1315.49" + attribute \src "ls180.v:1226.5-1226.49" wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:1316.5-1316.48" + attribute \src "ls180.v:1227.5-1227.48" wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:1317.11-1317.62" + attribute \src "ls180.v:1228.11-1228.62" wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1313.5-1313.49" + attribute \src "ls180.v:1224.5-1224.49" wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:1300.11-1300.54" + attribute \src "ls180.v:1211.11-1211.54" wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1296.5-1296.55" + attribute \src "ls180.v:1207.5-1207.55" wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:1297.5-1297.54" + attribute \src "ls180.v:1208.5-1208.54" wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:1298.11-1298.68" + attribute \src "ls180.v:1209.11-1209.68" wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1299.11-1299.81" + attribute \src "ls180.v:1210.11-1210.81" wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1302.5-1302.53" + attribute \src "ls180.v:1213.5-1213.53" wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1318.5-1318.38" + attribute \src "ls180.v:1229.5-1229.38" wire $1\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:1913.5-1913.66" + attribute \src "ls180.v:1824.5-1824.66" wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:1914.5-1914.69" + attribute \src "ls180.v:1825.5-1825.69" wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:1288.5-1288.36" + attribute \src "ls180.v:1199.5-1199.36" wire $1\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:1283.5-1283.53" + attribute \src "ls180.v:1194.5-1194.53" wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:1270.11-1270.39" + attribute \src "ls180.v:1181.11-1181.39" wire width 8 $1\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:1909.11-1909.67" + attribute \src "ls180.v:1820.11-1820.67" wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:1910.5-1910.64" + attribute \src "ls180.v:1821.5-1821.64" wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1255.5-1255.48" + attribute \src "ls180.v:1166.5-1166.48" wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1256.5-1256.50" + attribute \src "ls180.v:1167.5-1167.50" wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1257.5-1257.51" + attribute \src "ls180.v:1168.5-1168.51" wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1262.5-1262.37" + attribute \src "ls180.v:1173.5-1173.37" wire $1\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:1263.11-1263.53" + attribute \src "ls180.v:1174.11-1174.53" wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:1261.5-1261.38" + attribute \src "ls180.v:1172.5-1172.38" wire $1\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:1260.5-1260.38" + attribute \src "ls180.v:1171.5-1171.38" wire $1\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:1266.5-1266.39" + attribute \src "ls180.v:1177.5-1177.39" wire $1\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:1267.11-1267.53" + attribute \src "ls180.v:1178.11-1178.53" wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:1268.11-1268.55" + attribute \src "ls180.v:1179.11-1179.55" wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:1265.5-1265.40" + attribute \src "ls180.v:1176.5-1176.40" wire $1\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:1264.5-1264.40" + attribute \src "ls180.v:1175.5-1175.40" wire $1\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:1269.12-1269.48" + attribute \src "ls180.v:1180.12-1180.48" wire width 32 $1\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:1911.12-1911.71" + attribute \src "ls180.v:1822.12-1822.71" wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:1912.5-1912.66" + attribute \src "ls180.v:1823.5-1823.66" wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:1242.11-1242.39" + attribute \src "ls180.v:1153.11-1153.39" wire width 8 $1\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:1905.11-1905.66" + attribute \src "ls180.v:1816.11-1816.66" wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:1906.5-1906.63" + attribute \src "ls180.v:1817.5-1817.63" wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:1241.5-1241.32" + attribute \src "ls180.v:1152.5-1152.32" wire $1\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:1232.5-1232.48" + attribute \src "ls180.v:1143.5-1143.48" wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1233.5-1233.50" + attribute \src "ls180.v:1144.5-1144.50" wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1234.5-1234.51" + attribute \src "ls180.v:1145.5-1145.51" wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1239.5-1239.37" + attribute \src "ls180.v:1150.5-1150.37" wire $1\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:1240.11-1240.51" + attribute \src "ls180.v:1151.11-1151.51" wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:1238.5-1238.38" + attribute \src "ls180.v:1149.5-1149.38" wire $1\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:1237.5-1237.38" + attribute \src "ls180.v:1148.5-1148.38" wire $1\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:1426.11-1426.41" + attribute \src "ls180.v:1337.11-1337.41" wire width 10 $1\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:1925.11-1925.70" + attribute \src "ls180.v:1836.11-1836.70" wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:1926.5-1926.66" + attribute \src "ls180.v:1837.5-1837.66" wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:1471.5-1471.51" + attribute \src "ls180.v:1382.5-1382.51" wire $1\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:1472.5-1472.50" + attribute \src "ls180.v:1383.5-1383.50" wire $1\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:1473.11-1473.64" + attribute \src "ls180.v:1384.11-1384.64" wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:1469.5-1469.51" + attribute \src "ls180.v:1380.5-1380.51" wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:1456.5-1456.50" + attribute \src "ls180.v:1367.5-1367.50" wire $1\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1452.5-1452.57" + attribute \src "ls180.v:1363.5-1363.57" wire $1\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:1453.5-1453.56" + attribute \src "ls180.v:1364.5-1364.56" wire $1\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:1454.11-1454.70" + attribute \src "ls180.v:1365.11-1365.70" wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:1455.11-1455.83" + attribute \src "ls180.v:1366.11-1366.83" wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:1458.5-1458.55" + attribute \src "ls180.v:1369.5-1369.55" wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1474.5-1474.40" + attribute \src "ls180.v:1385.5-1385.40" wire $1\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:1929.5-1929.69" + attribute \src "ls180.v:1840.5-1840.69" wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:1930.5-1930.72" + attribute \src "ls180.v:1841.5-1841.72" wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:1444.5-1444.38" + attribute \src "ls180.v:1355.5-1355.38" wire $1\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:1439.5-1439.55" + attribute \src "ls180.v:1350.5-1350.55" wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1409.5-1409.49" + attribute \src "ls180.v:1320.5-1320.49" wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1416.5-1416.38" + attribute \src "ls180.v:1327.5-1327.38" wire $1\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:1417.11-1417.61" + attribute \src "ls180.v:1328.11-1328.61" wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:1415.5-1415.39" + attribute \src "ls180.v:1326.5-1326.39" wire $1\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:1414.5-1414.39" + attribute \src "ls180.v:1325.5-1325.39" wire $1\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1421.5-1421.40" + attribute \src "ls180.v:1332.5-1332.40" wire $1\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:1422.11-1422.54" + attribute \src "ls180.v:1333.11-1333.54" wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:1423.11-1423.56" + attribute \src "ls180.v:1334.11-1334.56" wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:1419.5-1419.41" + attribute \src "ls180.v:1330.5-1330.41" wire $1\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:1418.5-1418.41" + attribute \src "ls180.v:1329.5-1329.41" wire $1\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:1424.5-1424.33" + attribute \src "ls180.v:1335.5-1335.33" wire $1\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:1425.12-1425.49" + attribute \src "ls180.v:1336.12-1336.49" wire width 32 $1\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:1927.12-1927.73" + attribute \src "ls180.v:1838.12-1838.73" wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:1928.5-1928.68" + attribute \src "ls180.v:1839.5-1839.68" wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:1334.11-1334.40" + attribute \src "ls180.v:1245.11-1245.40" wire width 8 $1\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:1921.11-1921.61" + attribute \src "ls180.v:1832.11-1832.61" wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:1922.5-1922.58" + attribute \src "ls180.v:1833.5-1833.58" wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1393.5-1393.50" + attribute \src "ls180.v:1304.5-1304.50" wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:1394.5-1394.49" + attribute \src "ls180.v:1305.5-1305.49" wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:1395.11-1395.63" + attribute \src "ls180.v:1306.11-1306.63" wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1391.5-1391.50" + attribute \src "ls180.v:1302.5-1302.50" wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:1378.11-1378.55" + attribute \src "ls180.v:1289.11-1289.55" wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1374.5-1374.56" + attribute \src "ls180.v:1285.5-1285.56" wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:1375.5-1375.55" + attribute \src "ls180.v:1286.5-1286.55" wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:1376.11-1376.69" + attribute \src "ls180.v:1287.11-1287.69" wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1377.11-1377.82" + attribute \src "ls180.v:1288.11-1288.82" wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1380.5-1380.54" + attribute \src "ls180.v:1291.5-1291.54" wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1396.5-1396.39" + attribute \src "ls180.v:1307.5-1307.39" wire $1\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:1917.5-1917.66" + attribute \src "ls180.v:1828.5-1828.66" wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:1918.5-1918.69" + attribute \src "ls180.v:1829.5-1829.69" wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:1366.5-1366.37" + attribute \src "ls180.v:1277.5-1277.37" wire $1\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:1361.5-1361.54" + attribute \src "ls180.v:1272.5-1272.54" wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:1348.5-1348.34" + attribute \src "ls180.v:1259.5-1259.34" wire $1\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1323.5-1323.49" + attribute \src "ls180.v:1234.5-1234.49" wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1326.11-1326.58" + attribute \src "ls180.v:1237.11-1237.58" wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1327.5-1327.53" + attribute \src "ls180.v:1238.5-1238.53" wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1330.5-1330.39" + attribute \src "ls180.v:1241.5-1241.39" wire $1\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:1331.5-1331.38" + attribute \src "ls180.v:1242.5-1242.38" wire $1\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:1332.11-1332.52" + attribute \src "ls180.v:1243.11-1243.52" wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:1329.5-1329.39" + attribute \src "ls180.v:1240.5-1240.39" wire $1\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:1328.5-1328.39" + attribute \src "ls180.v:1239.5-1239.39" wire $1\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:1346.5-1346.34" + attribute \src "ls180.v:1257.5-1257.34" wire $1\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:1333.5-1333.33" + attribute \src "ls180.v:1244.5-1244.33" wire $1\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:1347.5-1347.34" + attribute \src "ls180.v:1258.5-1258.34" wire $1\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:1227.11-1227.39" + attribute \src "ls180.v:1138.11-1138.39" wire width 8 $1\main_sdphy_init_count[7:0] - attribute \src "ls180.v:1901.11-1901.66" + attribute \src "ls180.v:1812.11-1812.66" wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:1902.5-1902.63" + attribute \src "ls180.v:1813.5-1813.63" wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1222.5-1222.48" + attribute \src "ls180.v:1133.5-1133.48" wire $1\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1223.5-1223.50" + attribute \src "ls180.v:1134.5-1134.50" wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1224.5-1224.51" + attribute \src "ls180.v:1135.5-1135.51" wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1225.11-1225.57" + attribute \src "ls180.v:1136.11-1136.57" wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1226.5-1226.52" + attribute \src "ls180.v:1137.5-1137.52" wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1476.5-1476.35" + attribute \src "ls180.v:1387.5-1387.35" wire $1\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:1479.11-1479.42" + attribute \src "ls180.v:1390.11-1390.42" wire width 4 $1\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:421.5-421.33" + attribute \src "ls180.v:332.5-332.33" wire $1\main_sdram_address_re[0:0] - attribute \src "ls180.v:420.12-420.46" + attribute \src "ls180.v:331.12-331.46" wire width 13 $1\main_sdram_address_storage[12:0] - attribute \src "ls180.v:423.5-423.34" + attribute \src "ls180.v:334.5-334.34" wire $1\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:422.11-422.45" + attribute \src "ls180.v:333.11-333.45" wire width 2 $1\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:519.5-519.50" + attribute \src "ls180.v:430.5-430.50" wire $1\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:541.11-541.70" + attribute \src "ls180.v:452.11-452.70" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:538.11-538.68" + attribute \src "ls180.v:449.11-449.68" wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:540.11-540.70" + attribute \src "ls180.v:451.11-451.70" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:542.11-542.73" + attribute \src "ls180.v:453.11-453.73" wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:565.5-565.59" + attribute \src "ls180.v:476.5-476.59" wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:566.5-566.58" + attribute \src "ls180.v:477.5-477.58" wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:568.12-568.74" + attribute \src "ls180.v:479.12-479.74" wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:567.5-567.64" + attribute \src "ls180.v:478.5-478.64" wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:563.5-563.59" + attribute \src "ls180.v:474.5-474.59" wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:511.12-511.57" + attribute \src "ls180.v:422.12-422.57" wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:513.5-513.51" + attribute \src "ls180.v:424.5-424.51" wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:516.5-516.54" + attribute \src "ls180.v:427.5-427.54" wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:517.5-517.55" + attribute \src "ls180.v:428.5-428.55" wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:518.5-518.56" + attribute \src "ls180.v:429.5-429.56" wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:514.5-514.51" + attribute \src "ls180.v:425.5-425.51" wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:515.5-515.50" + attribute \src "ls180.v:426.5-426.50" wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:510.5-510.45" + attribute \src "ls180.v:421.5-421.45" wire $1\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:509.5-509.45" + attribute \src "ls180.v:420.5-420.45" wire $1\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:508.5-508.47" + attribute \src "ls180.v:419.5-419.47" wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:506.5-506.51" + attribute \src "ls180.v:417.5-417.51" wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:505.5-505.51" + attribute \src "ls180.v:416.5-416.51" wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:569.12-569.47" + attribute \src "ls180.v:480.12-480.47" wire width 13 $1\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:573.5-573.45" + attribute \src "ls180.v:484.5-484.45" wire $1\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:574.5-574.54" + attribute \src "ls180.v:485.5-485.54" wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:572.5-572.44" + attribute \src "ls180.v:483.5-483.44" wire $1\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:570.5-570.46" + attribute \src "ls180.v:481.5-481.46" wire $1\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:577.11-577.55" + attribute \src "ls180.v:488.11-488.55" wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:576.32-576.76" + attribute \src "ls180.v:487.32-487.76" wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:601.5-601.50" + attribute \src "ls180.v:512.5-512.50" wire $1\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:623.11-623.70" + attribute \src "ls180.v:534.11-534.70" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:620.11-620.68" + attribute \src "ls180.v:531.11-531.68" wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:622.11-622.70" + attribute \src "ls180.v:533.11-533.70" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:624.11-624.73" + attribute \src "ls180.v:535.11-535.73" wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:647.5-647.59" + attribute \src "ls180.v:558.5-558.59" wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:648.5-648.58" + attribute \src "ls180.v:559.5-559.58" wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:650.12-650.74" + attribute \src "ls180.v:561.12-561.74" wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:649.5-649.64" + attribute \src "ls180.v:560.5-560.64" wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:645.5-645.59" + attribute \src "ls180.v:556.5-556.59" wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:593.12-593.57" + attribute \src "ls180.v:504.12-504.57" wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:595.5-595.51" + attribute \src "ls180.v:506.5-506.51" wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:598.5-598.54" + attribute \src "ls180.v:509.5-509.54" wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:599.5-599.55" + attribute \src "ls180.v:510.5-510.55" wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:600.5-600.56" + attribute \src "ls180.v:511.5-511.56" wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:596.5-596.51" + attribute \src "ls180.v:507.5-507.51" wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:597.5-597.50" + attribute \src "ls180.v:508.5-508.50" wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:592.5-592.45" + attribute \src "ls180.v:503.5-503.45" wire $1\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:591.5-591.45" + attribute \src "ls180.v:502.5-502.45" wire $1\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:590.5-590.47" + attribute \src "ls180.v:501.5-501.47" wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:588.5-588.51" + attribute \src "ls180.v:499.5-499.51" wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:587.5-587.51" + attribute \src "ls180.v:498.5-498.51" wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:651.12-651.47" + attribute \src "ls180.v:562.12-562.47" wire width 13 $1\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:655.5-655.45" + attribute \src "ls180.v:566.5-566.45" wire $1\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:656.5-656.54" + attribute \src "ls180.v:567.5-567.54" wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:654.5-654.44" + attribute \src "ls180.v:565.5-565.44" wire $1\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:652.5-652.46" + attribute \src "ls180.v:563.5-563.46" wire $1\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:659.11-659.55" + attribute \src "ls180.v:570.11-570.55" wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:658.32-658.76" + attribute \src "ls180.v:569.32-569.76" wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:683.5-683.50" + attribute \src "ls180.v:594.5-594.50" wire $1\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:705.11-705.70" + attribute \src "ls180.v:616.11-616.70" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:702.11-702.68" + attribute \src "ls180.v:613.11-613.68" wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:704.11-704.70" + attribute \src "ls180.v:615.11-615.70" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:706.11-706.73" + attribute \src "ls180.v:617.11-617.73" wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:729.5-729.59" + attribute \src "ls180.v:640.5-640.59" wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:730.5-730.58" + attribute \src "ls180.v:641.5-641.58" wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:732.12-732.74" + attribute \src "ls180.v:643.12-643.74" wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:731.5-731.64" + attribute \src "ls180.v:642.5-642.64" wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:727.5-727.59" + attribute \src "ls180.v:638.5-638.59" wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:675.12-675.57" + attribute \src "ls180.v:586.12-586.57" wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:677.5-677.51" + attribute \src "ls180.v:588.5-588.51" wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:680.5-680.54" + attribute \src "ls180.v:591.5-591.54" wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:681.5-681.55" + attribute \src "ls180.v:592.5-592.55" wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:682.5-682.56" + attribute \src "ls180.v:593.5-593.56" wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:678.5-678.51" + attribute \src "ls180.v:589.5-589.51" wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:679.5-679.50" + attribute \src "ls180.v:590.5-590.50" wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:674.5-674.45" + attribute \src "ls180.v:585.5-585.45" wire $1\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:673.5-673.45" + attribute \src "ls180.v:584.5-584.45" wire $1\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:672.5-672.47" + attribute \src "ls180.v:583.5-583.47" wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:670.5-670.51" + attribute \src "ls180.v:581.5-581.51" wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:669.5-669.51" + attribute \src "ls180.v:580.5-580.51" wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:733.12-733.47" + attribute \src "ls180.v:644.12-644.47" wire width 13 $1\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:737.5-737.45" + attribute \src "ls180.v:648.5-648.45" wire $1\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:738.5-738.54" + attribute \src "ls180.v:649.5-649.54" wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:736.5-736.44" + attribute \src "ls180.v:647.5-647.44" wire $1\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:734.5-734.46" + attribute \src "ls180.v:645.5-645.46" wire $1\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:741.11-741.55" + attribute \src "ls180.v:652.11-652.55" wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:740.32-740.76" + attribute \src "ls180.v:651.32-651.76" wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:765.5-765.50" + attribute \src "ls180.v:676.5-676.50" wire $1\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:787.11-787.70" + attribute \src "ls180.v:698.11-698.70" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:784.11-784.68" + attribute \src "ls180.v:695.11-695.68" wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:786.11-786.70" + attribute \src "ls180.v:697.11-697.70" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:788.11-788.73" + attribute \src "ls180.v:699.11-699.73" wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:811.5-811.59" + attribute \src "ls180.v:722.5-722.59" wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:812.5-812.58" + attribute \src "ls180.v:723.5-723.58" wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:814.12-814.74" + attribute \src "ls180.v:725.12-725.74" wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:813.5-813.64" + attribute \src "ls180.v:724.5-724.64" wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:809.5-809.59" + attribute \src "ls180.v:720.5-720.59" wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:757.12-757.57" + attribute \src "ls180.v:668.12-668.57" wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:759.5-759.51" + attribute \src "ls180.v:670.5-670.51" wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:762.5-762.54" + attribute \src "ls180.v:673.5-673.54" wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:763.5-763.55" + attribute \src "ls180.v:674.5-674.55" wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:764.5-764.56" + attribute \src "ls180.v:675.5-675.56" wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:760.5-760.51" + attribute \src "ls180.v:671.5-671.51" wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:761.5-761.50" + attribute \src "ls180.v:672.5-672.50" wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:756.5-756.45" + attribute \src "ls180.v:667.5-667.45" wire $1\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:755.5-755.45" + attribute \src "ls180.v:666.5-666.45" wire $1\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:754.5-754.47" + attribute \src "ls180.v:665.5-665.47" wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:752.5-752.51" + attribute \src "ls180.v:663.5-663.51" wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:751.5-751.51" + attribute \src "ls180.v:662.5-662.51" wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:815.12-815.47" + attribute \src "ls180.v:726.12-726.47" wire width 13 $1\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:819.5-819.45" + attribute \src "ls180.v:730.5-730.45" wire $1\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:820.5-820.54" + attribute \src "ls180.v:731.5-731.54" wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:818.5-818.44" + attribute \src "ls180.v:729.5-729.44" wire $1\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:816.5-816.46" + attribute \src "ls180.v:727.5-727.46" wire $1\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:823.11-823.55" + attribute \src "ls180.v:734.11-734.55" wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:822.32-822.76" + attribute \src "ls180.v:733.32-733.76" wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:838.5-838.49" + attribute \src "ls180.v:749.5-749.49" wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:839.5-839.49" + attribute \src "ls180.v:750.5-750.49" wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:840.5-840.48" + attribute \src "ls180.v:751.5-751.48" wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:846.11-846.45" + attribute \src "ls180.v:757.11-757.45" wire width 2 $1\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:844.11-844.46" + attribute \src "ls180.v:755.11-755.46" wire width 4 $1\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:856.5-856.49" + attribute \src "ls180.v:767.5-767.49" wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:857.5-857.49" + attribute \src "ls180.v:768.5-768.49" wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:858.5-858.48" + attribute \src "ls180.v:769.5-769.48" wire $1\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:853.5-853.43" + attribute \src "ls180.v:764.5-764.43" wire $1\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:864.11-864.45" + attribute \src "ls180.v:775.11-775.45" wire width 2 $1\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:862.11-862.46" + attribute \src "ls180.v:773.11-773.46" wire width 4 $1\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:851.5-851.48" + attribute \src "ls180.v:762.5-762.48" wire $1\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:848.5-848.44" + attribute \src "ls180.v:759.5-759.44" wire $1\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:849.5-849.45" + attribute \src "ls180.v:760.5-760.45" wire $1\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:477.5-477.31" + attribute \src "ls180.v:388.5-388.31" wire $1\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:478.12-478.44" + attribute \src "ls180.v:389.12-389.44" wire width 13 $1\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:479.11-479.43" + attribute \src "ls180.v:390.11-390.43" wire width 2 $1\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:480.5-480.38" + attribute \src "ls180.v:391.5-391.38" wire $1\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:481.5-481.38" + attribute \src "ls180.v:392.5-392.38" wire $1\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:482.5-482.37" + attribute \src "ls180.v:393.5-393.37" wire $1\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:476.5-476.32" + attribute \src "ls180.v:387.5-387.32" wire $1\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:475.5-475.32" + attribute \src "ls180.v:386.5-386.32" wire $1\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:415.5-415.33" + attribute \src "ls180.v:326.5-326.33" wire $1\main_sdram_command_re[0:0] - attribute \src "ls180.v:414.11-414.44" + attribute \src "ls180.v:325.11-325.44" wire width 6 $1\main_sdram_command_storage[5:0] - attribute \src "ls180.v:459.12-459.45" + attribute \src "ls180.v:370.12-370.45" wire width 13 $1\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:460.11-460.40" + attribute \src "ls180.v:371.11-371.40" wire width 2 $1\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:461.5-461.35" + attribute \src "ls180.v:372.5-372.35" wire $1\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:462.5-462.34" + attribute \src "ls180.v:373.5-373.34" wire $1\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:463.5-463.35" + attribute \src "ls180.v:374.5-374.35" wire $1\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:472.5-472.39" + attribute \src "ls180.v:383.5-383.39" wire $1\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:464.5-464.34" + attribute \src "ls180.v:375.5-375.34" wire $1\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:470.5-470.39" + attribute \src "ls180.v:381.5-381.39" wire $1\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:883.5-883.26" + attribute \src "ls180.v:794.5-794.26" wire $1\main_sdram_en0[0:0] - attribute \src "ls180.v:886.5-886.26" + attribute \src "ls180.v:797.5-797.26" wire $1\main_sdram_en1[0:0] - attribute \src "ls180.v:456.12-456.46" + attribute \src "ls180.v:367.12-367.46" wire width 16 $1\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:457.11-457.47" + attribute \src "ls180.v:368.11-368.47" wire width 2 $1\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:362.5-362.36" + attribute \src "ls180.v:273.5-273.36" wire $1\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:363.5-363.35" + attribute \src "ls180.v:274.5-274.35" wire $1\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:364.5-364.36" + attribute \src "ls180.v:275.5-275.36" wire $1\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:374.12-374.45" + attribute \src "ls180.v:285.12-285.45" wire width 16 $1\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:375.5-375.43" + attribute \src "ls180.v:286.5-286.43" wire $1\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:365.5-365.35" + attribute \src "ls180.v:276.5-276.35" wire $1\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:401.5-401.38" + attribute \src "ls180.v:312.5-312.38" wire $1\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:392.12-392.48" + attribute \src "ls180.v:303.12-303.48" wire width 13 $1\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:393.11-393.43" + attribute \src "ls180.v:304.11-304.43" wire width 2 $1\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:394.5-394.38" + attribute \src "ls180.v:305.5-305.38" wire $1\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:398.5-398.36" + attribute \src "ls180.v:309.5-309.36" wire $1\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:395.5-395.37" + attribute \src "ls180.v:306.5-306.37" wire $1\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:399.5-399.36" + attribute \src "ls180.v:310.5-310.36" wire $1\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:396.5-396.38" + attribute \src "ls180.v:307.5-307.38" wire $1\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:405.5-405.42" + attribute \src "ls180.v:316.5-316.42" wire $1\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:400.5-400.40" + attribute \src "ls180.v:311.5-311.40" wire $1\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:397.5-397.37" + attribute \src "ls180.v:308.5-308.37" wire $1\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:402.12-402.47" + attribute \src "ls180.v:313.12-313.47" wire width 16 $1\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:403.5-403.42" + attribute \src "ls180.v:314.5-314.42" wire $1\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:404.11-404.50" + attribute \src "ls180.v:315.11-315.50" wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:493.5-493.38" + attribute \src "ls180.v:404.5-404.38" wire $1\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:492.5-492.38" + attribute \src "ls180.v:403.5-403.38" wire $1\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:413.5-413.25" + attribute \src "ls180.v:324.5-324.25" wire $1\main_sdram_re[0:0] - attribute \src "ls180.v:499.5-499.38" + attribute \src "ls180.v:410.5-410.38" wire $1\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:498.11-498.46" + attribute \src "ls180.v:409.11-409.46" wire width 4 $1\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:497.5-497.38" + attribute \src "ls180.v:408.5-408.38" wire $1\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:494.5-494.39" + attribute \src "ls180.v:405.5-405.39" wire $1\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:390.12-390.46" + attribute \src "ls180.v:301.12-301.46" wire width 16 $1\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:391.5-391.44" + attribute \src "ls180.v:302.5-302.44" wire $1\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:426.12-426.37" + attribute \src "ls180.v:337.12-337.37" wire width 16 $1\main_sdram_status[15:0] - attribute \src "ls180.v:868.11-868.40" + attribute \src "ls180.v:779.11-779.40" wire width 2 $1\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:412.11-412.36" + attribute \src "ls180.v:323.11-323.36" wire width 4 $1\main_sdram_storage[3:0] - attribute \src "ls180.v:877.5-877.36" + attribute \src "ls180.v:788.5-788.36" wire $1\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:876.32-876.63" + attribute \src "ls180.v:787.32-787.63" wire $1\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:885.11-885.34" + attribute \src "ls180.v:796.11-796.34" wire width 5 $1\main_sdram_time0[4:0] - attribute \src "ls180.v:888.11-888.34" + attribute \src "ls180.v:799.11-799.34" wire width 4 $1\main_sdram_time1[3:0] - attribute \src "ls180.v:490.11-490.44" + attribute \src "ls180.v:401.11-401.44" wire width 10 $1\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:880.11-880.42" + attribute \src "ls180.v:791.11-791.42" wire width 3 $1\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:879.32-879.63" + attribute \src "ls180.v:790.32-790.63" wire $1\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:425.5-425.32" + attribute \src "ls180.v:336.5-336.32" wire $1\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:424.12-424.45" + attribute \src "ls180.v:335.12-335.45" wire width 16 $1\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:917.5-917.54" + attribute \src "ls180.v:828.5-828.54" wire $1\main_socbushandler_converted_interface_ack[0:0] - attribute \src "ls180.v:923.5-923.38" + attribute \src "ls180.v:834.5-834.38" wire $1\main_socbushandler_counter[0:0] - attribute \src "ls180.v:1852.5-1852.60" + attribute \src "ls180.v:1763.5-1763.60" wire $1\main_socbushandler_counter_converter2_next_value[0:0] - attribute \src "ls180.v:1853.5-1853.63" + attribute \src "ls180.v:1764.5-1764.63" wire $1\main_socbushandler_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:925.12-925.44" + attribute \src "ls180.v:836.12-836.44" wire width 64 $1\main_socbushandler_dat_r[63:0] - attribute \src "ls180.v:922.5-922.35" + attribute \src "ls180.v:833.5-833.35" wire $1\main_socbushandler_skip[0:0] - attribute \src "ls180.v:1111.12-1111.44" + attribute \src "ls180.v:1022.12-1022.44" wire width 16 $1\main_spimaster11_storage[15:0] - attribute \src "ls180.v:1112.5-1112.31" + attribute \src "ls180.v:1023.5-1023.31" wire $1\main_spimaster12_re[0:0] - attribute \src "ls180.v:1116.11-1116.42" + attribute \src "ls180.v:1027.11-1027.42" wire width 8 $1\main_spimaster16_storage[7:0] - attribute \src "ls180.v:1117.5-1117.31" + attribute \src "ls180.v:1028.5-1028.31" wire $1\main_spimaster17_re[0:0] - attribute \src "ls180.v:1173.5-1173.30" + attribute \src "ls180.v:1084.5-1084.30" wire $1\main_spimaster1_re[0:0] - attribute \src "ls180.v:1172.12-1172.45" + attribute \src "ls180.v:1083.12-1083.45" wire width 16 $1\main_spimaster1_storage[15:0] - attribute \src "ls180.v:1121.5-1121.36" + attribute \src "ls180.v:1032.5-1032.36" wire $1\main_spimaster21_storage[0:0] - attribute \src "ls180.v:1122.5-1122.31" + attribute \src "ls180.v:1033.5-1033.31" wire $1\main_spimaster22_re[0:0] - attribute \src "ls180.v:1123.5-1123.36" + attribute \src "ls180.v:1034.5-1034.36" wire $1\main_spimaster23_storage[0:0] - attribute \src "ls180.v:1124.5-1124.31" + attribute \src "ls180.v:1035.5-1035.31" wire $1\main_spimaster24_re[0:0] - attribute \src "ls180.v:1125.5-1125.39" + attribute \src "ls180.v:1036.5-1036.39" wire $1\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:1126.5-1126.38" + attribute \src "ls180.v:1037.5-1037.38" wire $1\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:1127.11-1127.40" + attribute \src "ls180.v:1038.11-1038.40" wire width 3 $1\main_spimaster27_count[2:0] - attribute \src "ls180.v:1893.11-1893.62" + attribute \src "ls180.v:1804.11-1804.62" wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:1894.5-1894.59" + attribute \src "ls180.v:1805.5-1805.59" wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:1128.5-1128.39" + attribute \src "ls180.v:1039.5-1039.39" wire $1\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:1129.5-1129.39" + attribute \src "ls180.v:1040.5-1040.39" wire $1\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:1102.5-1102.32" + attribute \src "ls180.v:1013.5-1013.32" wire $1\main_spimaster2_done[0:0] - attribute \src "ls180.v:1130.12-1130.48" + attribute \src "ls180.v:1041.12-1041.48" wire width 16 $1\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:1133.11-1133.44" + attribute \src "ls180.v:1044.11-1044.44" wire width 8 $1\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:1134.11-1134.43" + attribute \src "ls180.v:1045.11-1045.43" wire width 3 $1\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:1135.11-1135.44" + attribute \src "ls180.v:1046.11-1046.44" wire width 8 $1\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:1103.5-1103.31" + attribute \src "ls180.v:1014.5-1014.31" wire $1\main_spimaster3_irq[0:0] - attribute \src "ls180.v:1105.11-1105.38" + attribute \src "ls180.v:1016.11-1016.38" wire width 8 $1\main_spimaster5_miso[7:0] - attribute \src "ls180.v:1109.5-1109.33" + attribute \src "ls180.v:1020.5-1020.33" wire $1\main_spimaster9_start[0:0] - attribute \src "ls180.v:1166.12-1166.47" + attribute \src "ls180.v:1077.12-1077.47" wire width 16 $1\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:1161.5-1161.37" + attribute \src "ls180.v:1072.5-1072.37" wire $1\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:1148.5-1148.37" + attribute \src "ls180.v:1059.5-1059.37" wire $1\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:1147.12-1147.50" + attribute \src "ls180.v:1058.12-1058.50" wire width 16 $1\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:1163.11-1163.38" + attribute \src "ls180.v:1074.11-1074.38" wire width 3 $1\main_spisdcard_count[2:0] - attribute \src "ls180.v:1897.11-1897.60" + attribute \src "ls180.v:1808.11-1808.60" wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:1898.5-1898.57" + attribute \src "ls180.v:1809.5-1809.57" wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:1162.5-1162.36" + attribute \src "ls180.v:1073.5-1073.36" wire $1\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:1158.5-1158.32" + attribute \src "ls180.v:1069.5-1069.32" wire $1\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:1157.5-1157.37" + attribute \src "ls180.v:1068.5-1068.37" wire $1\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:1138.5-1138.32" + attribute \src "ls180.v:1049.5-1049.32" wire $1\main_spisdcard_done0[0:0] - attribute \src "ls180.v:1139.5-1139.30" + attribute \src "ls180.v:1050.5-1050.30" wire $1\main_spisdcard_irq[0:0] - attribute \src "ls180.v:1160.5-1160.38" + attribute \src "ls180.v:1071.5-1071.38" wire $1\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:1159.5-1159.43" + attribute \src "ls180.v:1070.5-1070.43" wire $1\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:1141.11-1141.37" + attribute \src "ls180.v:1052.11-1052.37" wire width 8 $1\main_spisdcard_miso[7:0] - attribute \src "ls180.v:1171.11-1171.42" + attribute \src "ls180.v:1082.11-1082.42" wire width 8 $1\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:1165.5-1165.37" + attribute \src "ls180.v:1076.5-1076.37" wire $1\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:1169.11-1169.42" + attribute \src "ls180.v:1080.11-1080.42" wire width 8 $1\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:1164.5-1164.37" + attribute \src "ls180.v:1075.5-1075.37" wire $1\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:1153.5-1153.34" + attribute \src "ls180.v:1064.5-1064.34" wire $1\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:1170.11-1170.41" + attribute \src "ls180.v:1081.11-1081.41" wire width 3 $1\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:1152.11-1152.45" + attribute \src "ls180.v:1063.11-1063.45" wire width 8 $1\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:1145.5-1145.33" + attribute \src "ls180.v:1056.5-1056.33" wire $1\main_spisdcard_start1[0:0] - attribute \src "ls180.v:262.11-262.31" - wire width 8 $1\main_sram0_we[7:0] - attribute \src "ls180.v:277.11-277.31" - wire width 8 $1\main_sram1_we[7:0] - attribute \src "ls180.v:292.11-292.31" - wire width 8 $1\main_sram2_we[7:0] - attribute \src "ls180.v:307.11-307.31" - wire width 8 $1\main_sram3_we[7:0] - attribute \src "ls180.v:993.11-993.50" + attribute \src "ls180.v:904.11-904.50" wire width 2 $1\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:995.5-995.37" + attribute \src "ls180.v:906.5-906.37" wire $1\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:989.11-989.49" + attribute \src "ls180.v:900.11-900.49" wire width 2 $1\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:994.11-994.48" + attribute \src "ls180.v:905.11-905.48" wire width 2 $1\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:961.12-961.54" + attribute \src "ls180.v:872.12-872.54" wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:951.12-951.54" + attribute \src "ls180.v:862.12-862.54" wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:944.5-944.28" + attribute \src "ls180.v:855.5-855.28" wire $1\main_uart_phy_re[0:0] - attribute \src "ls180.v:965.11-965.43" + attribute \src "ls180.v:876.11-876.43" wire width 4 $1\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:966.5-966.33" + attribute \src "ls180.v:877.5-877.33" wire $1\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:963.5-963.30" + attribute \src "ls180.v:874.5-874.30" wire $1\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:964.11-964.38" + attribute \src "ls180.v:875.11-875.38" wire width 8 $1\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:946.5-946.36" + attribute \src "ls180.v:857.5-857.36" wire $1\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:959.11-959.51" + attribute \src "ls180.v:870.11-870.51" wire width 8 $1\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:955.5-955.38" + attribute \src "ls180.v:866.5-866.38" wire $1\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:943.12-943.47" + attribute \src "ls180.v:854.12-854.47" wire width 32 $1\main_uart_phy_storage[31:0] - attribute \src "ls180.v:953.11-953.43" + attribute \src "ls180.v:864.11-864.43" wire width 4 $1\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:954.5-954.33" + attribute \src "ls180.v:865.5-865.33" wire $1\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:952.11-952.38" + attribute \src "ls180.v:863.11-863.38" wire width 8 $1\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:960.5-960.39" + attribute \src "ls180.v:871.5-871.39" wire $1\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:950.5-950.39" + attribute \src "ls180.v:861.5-861.39" wire $1\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:984.5-984.30" + attribute \src "ls180.v:895.5-895.30" wire $1\main_uart_rx_clear[0:0] - attribute \src "ls180.v:1068.11-1068.43" + attribute \src "ls180.v:979.11-979.43" wire width 4 $1\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:1065.11-1065.42" + attribute \src "ls180.v:976.11-976.42" wire width 5 $1\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:1067.11-1067.43" + attribute \src "ls180.v:978.11-978.43" wire width 4 $1\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:1058.5-1058.38" + attribute \src "ls180.v:969.5-969.38" wire $1\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:1069.11-1069.46" + attribute \src "ls180.v:980.11-980.46" wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:985.5-985.36" + attribute \src "ls180.v:896.5-896.36" wire $1\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:982.5-982.32" + attribute \src "ls180.v:893.5-893.32" wire $1\main_uart_rx_pending[0:0] - attribute \src "ls180.v:979.5-979.30" + attribute \src "ls180.v:890.5-890.30" wire $1\main_uart_tx_clear[0:0] - attribute \src "ls180.v:1031.11-1031.43" + attribute \src "ls180.v:942.11-942.43" wire width 4 $1\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:1028.11-1028.42" + attribute \src "ls180.v:939.11-939.42" wire width 5 $1\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:1030.11-1030.43" + attribute \src "ls180.v:941.11-941.43" wire width 4 $1\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:1021.5-1021.38" + attribute \src "ls180.v:932.5-932.38" wire $1\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:1032.11-1032.46" + attribute \src "ls180.v:943.11-943.46" wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:980.5-980.36" + attribute \src "ls180.v:891.5-891.36" wire $1\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:977.5-977.32" + attribute \src "ls180.v:888.5-888.32" wire $1\main_uart_tx_pending[0:0] - attribute \src "ls180.v:909.5-909.29" + attribute \src "ls180.v:820.5-820.29" wire $1\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:903.12-903.37" + attribute \src "ls180.v:814.12-814.37" wire width 30 $1\main_wb_sdram_adr[29:0] - attribute \src "ls180.v:907.5-907.29" + attribute \src "ls180.v:818.5-818.29" wire $1\main_wb_sdram_cyc[0:0] - attribute \src "ls180.v:904.12-904.39" + attribute \src "ls180.v:815.12-815.39" wire width 32 $1\main_wb_sdram_dat_w[31:0] - attribute \src "ls180.v:906.11-906.35" + attribute \src "ls180.v:817.11-817.35" wire width 4 $1\main_wb_sdram_sel[3:0] - attribute \src "ls180.v:908.5-908.29" + attribute \src "ls180.v:819.5-819.29" wire $1\main_wb_sdram_stb[0:0] - attribute \src "ls180.v:910.5-910.28" + attribute \src "ls180.v:821.5-821.28" wire $1\main_wb_sdram_we[0:0] - attribute \src "ls180.v:939.5-939.31" + attribute \src "ls180.v:850.5-850.31" wire $1\main_wdata_consumed[0:0] - attribute \src "ls180.v:2935.56-2935.86" - wire $add$ls180.v:2935$58_Y - attribute \src "ls180.v:2995.56-2995.86" - wire $add$ls180.v:2995$69_Y - attribute \src "ls180.v:3055.59-3055.92" - wire $add$ls180.v:3055$80_Y - attribute \src "ls180.v:4248.54-4248.83" - wire $add$ls180.v:4248$685_Y - attribute \src "ls180.v:4348.36-4348.89" - wire width 5 $add$ls180.v:4348$731_Y - attribute \src "ls180.v:4378.36-4378.89" - wire width 5 $add$ls180.v:4378$742_Y - attribute \src "ls180.v:4444.54-4444.83" - wire width 3 $add$ls180.v:4444$757_Y - attribute \src "ls180.v:4503.52-4503.79" - wire width 3 $add$ls180.v:4503$765_Y - attribute \src "ls180.v:4607.58-4607.86" - wire width 8 $add$ls180.v:4607$793_Y - attribute \src "ls180.v:4664.58-4664.86" - wire width 8 $add$ls180.v:4664$796_Y - attribute \src "ls180.v:4681.58-4681.86" - wire width 8 $add$ls180.v:4681$798_Y - attribute \src "ls180.v:4774.59-4774.87" - wire width 8 $add$ls180.v:4774$815_Y - attribute \src "ls180.v:4799.59-4799.87" - wire width 8 $add$ls180.v:4799$818_Y - attribute \src "ls180.v:4921.53-4921.82" - wire width 8 $add$ls180.v:4921$835_Y - attribute \src "ls180.v:5032.65-5032.114" - wire width 10 $add$ls180.v:5032$849_Y - attribute \src "ls180.v:5037.62-5037.91" - wire width 10 $add$ls180.v:5037$852_Y - attribute \src "ls180.v:5063.61-5063.90" - wire width 10 $add$ls180.v:5063$855_Y - attribute \src "ls180.v:5267.80-5267.117" - wire width 3 $add$ls180.v:5267$1040_Y - attribute \src "ls180.v:5461.54-5461.82" - wire width 3 $add$ls180.v:5461$1115_Y - attribute \src "ls180.v:5513.55-5513.84" - wire width 32 $add$ls180.v:5513$1125_Y - attribute \src "ls180.v:5539.57-5539.86" - wire width 32 $add$ls180.v:5539$1133_Y - attribute \src "ls180.v:5660.51-5660.134" - wire width 32 $add$ls180.v:5660$1149_Y - attribute \src "ls180.v:5663.77-5663.125" - wire width 32 $add$ls180.v:5663$1151_Y - attribute \src "ls180.v:5756.50-5756.105" - wire width 32 $add$ls180.v:5756$1160_Y - attribute \src "ls180.v:5758.77-5758.111" - wire width 32 $add$ls180.v:5758$1161_Y - attribute \src "ls180.v:7765.36-7765.70" - wire width 32 $add$ls180.v:7765$2604_Y - attribute \src "ls180.v:7866.37-7866.72" - wire width 4 $add$ls180.v:7866$2637_Y - attribute \src "ls180.v:7883.60-7883.119" - wire width 3 $add$ls180.v:7883$2641_Y - attribute \src "ls180.v:7886.60-7886.119" - wire width 3 $add$ls180.v:7886$2642_Y - attribute \src "ls180.v:7890.59-7890.116" - wire width 4 $add$ls180.v:7890$2647_Y - attribute \src "ls180.v:7929.60-7929.119" - wire width 3 $add$ls180.v:7929$2657_Y - attribute \src "ls180.v:7932.60-7932.119" - wire width 3 $add$ls180.v:7932$2658_Y - attribute \src "ls180.v:7936.59-7936.116" - wire width 4 $add$ls180.v:7936$2663_Y - attribute \src "ls180.v:7975.60-7975.119" - wire width 3 $add$ls180.v:7975$2673_Y - attribute \src "ls180.v:7978.60-7978.119" - wire width 3 $add$ls180.v:7978$2674_Y - attribute \src "ls180.v:7982.59-7982.116" - wire width 4 $add$ls180.v:7982$2679_Y - attribute \src "ls180.v:8021.60-8021.119" - wire width 3 $add$ls180.v:8021$2689_Y - attribute \src "ls180.v:8024.60-8024.119" - wire width 3 $add$ls180.v:8024$2690_Y - attribute \src "ls180.v:8028.59-8028.116" - wire width 4 $add$ls180.v:8028$2695_Y - attribute \src "ls180.v:8258.34-8258.66" - wire width 4 $add$ls180.v:8258$2749_Y - attribute \src "ls180.v:8274.73-8274.131" - wire width 33 $add$ls180.v:8274$2752_Y - attribute \src "ls180.v:8287.34-8287.66" - wire width 4 $add$ls180.v:8287$2756_Y - attribute \src "ls180.v:8306.73-8306.131" - wire width 33 $add$ls180.v:8306$2759_Y - attribute \src "ls180.v:8332.33-8332.65" - wire width 4 $add$ls180.v:8332$2767_Y - attribute \src "ls180.v:8335.33-8335.65" - wire width 4 $add$ls180.v:8335$2768_Y - attribute \src "ls180.v:8339.33-8339.64" - wire width 5 $add$ls180.v:8339$2773_Y - attribute \src "ls180.v:8354.33-8354.65" - wire width 4 $add$ls180.v:8354$2778_Y - attribute \src "ls180.v:8357.33-8357.65" - wire width 4 $add$ls180.v:8357$2779_Y - attribute \src "ls180.v:8361.33-8361.64" - wire width 5 $add$ls180.v:8361$2784_Y - attribute \src "ls180.v:8382.35-8382.70" - wire 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$add$ls180.v:2906$45_Y + attribute \src "ls180.v:2966.59-2966.92" + wire $add$ls180.v:2966$56_Y + attribute \src "ls180.v:4117.54-4117.83" + wire $add$ls180.v:4117$586_Y + attribute \src "ls180.v:4217.36-4217.89" + wire width 5 $add$ls180.v:4217$632_Y + attribute \src "ls180.v:4247.36-4247.89" + wire width 5 $add$ls180.v:4247$643_Y + attribute \src "ls180.v:4313.54-4313.83" + wire width 3 $add$ls180.v:4313$658_Y + attribute \src "ls180.v:4372.52-4372.79" + wire width 3 $add$ls180.v:4372$666_Y + attribute \src "ls180.v:4476.58-4476.86" + wire width 8 $add$ls180.v:4476$694_Y + attribute \src "ls180.v:4533.58-4533.86" + wire width 8 $add$ls180.v:4533$697_Y + attribute \src "ls180.v:4550.58-4550.86" + wire width 8 $add$ls180.v:4550$699_Y + attribute \src "ls180.v:4643.59-4643.87" + wire width 8 $add$ls180.v:4643$716_Y + attribute \src "ls180.v:4668.59-4668.87" + wire width 8 $add$ls180.v:4668$719_Y + attribute \src "ls180.v:4790.53-4790.82" + wire width 8 $add$ls180.v:4790$736_Y + attribute \src "ls180.v:4901.65-4901.114" + wire width 10 $add$ls180.v:4901$750_Y + attribute \src "ls180.v:4906.62-4906.91" + wire width 10 $add$ls180.v:4906$753_Y + attribute \src "ls180.v:4932.61-4932.90" + wire width 10 $add$ls180.v:4932$756_Y + attribute \src "ls180.v:5136.80-5136.117" + wire width 3 $add$ls180.v:5136$941_Y + attribute \src "ls180.v:5330.54-5330.82" + wire width 3 $add$ls180.v:5330$1016_Y + attribute \src "ls180.v:5382.55-5382.84" + wire width 32 $add$ls180.v:5382$1026_Y + attribute \src "ls180.v:5408.57-5408.86" + wire width 32 $add$ls180.v:5408$1034_Y + attribute \src "ls180.v:5529.51-5529.134" + wire width 32 $add$ls180.v:5529$1050_Y + attribute \src "ls180.v:5532.77-5532.125" + wire width 32 $add$ls180.v:5532$1052_Y + attribute \src "ls180.v:5625.50-5625.105" + wire width 32 $add$ls180.v:5625$1061_Y + attribute \src "ls180.v:5627.77-5627.111" + wire width 32 $add$ls180.v:5627$1062_Y + attribute \src "ls180.v:7571.36-7571.70" + wire width 32 $add$ls180.v:7571$2463_Y + attribute \src "ls180.v:7660.37-7660.72" + wire width 4 $add$ls180.v:7660$2487_Y + attribute \src "ls180.v:7677.60-7677.119" + wire width 3 $add$ls180.v:7677$2491_Y + attribute \src "ls180.v:7680.60-7680.119" + wire width 3 $add$ls180.v:7680$2492_Y + attribute \src "ls180.v:7684.59-7684.116" + wire width 4 $add$ls180.v:7684$2497_Y + attribute \src "ls180.v:7723.60-7723.119" + wire width 3 $add$ls180.v:7723$2507_Y + attribute \src "ls180.v:7726.60-7726.119" + wire width 3 $add$ls180.v:7726$2508_Y + attribute \src "ls180.v:7730.59-7730.116" + wire width 4 $add$ls180.v:7730$2513_Y + attribute \src "ls180.v:7769.60-7769.119" + wire width 3 $add$ls180.v:7769$2523_Y + attribute \src "ls180.v:7772.60-7772.119" + wire width 3 $add$ls180.v:7772$2524_Y + attribute \src "ls180.v:7776.59-7776.116" + wire width 4 $add$ls180.v:7776$2529_Y + attribute \src "ls180.v:7815.60-7815.119" + wire width 3 $add$ls180.v:7815$2539_Y + attribute \src "ls180.v:7818.60-7818.119" + wire width 3 $add$ls180.v:7818$2540_Y + attribute \src "ls180.v:7822.59-7822.116" + wire width 4 $add$ls180.v:7822$2545_Y + attribute \src "ls180.v:8052.34-8052.66" + wire width 4 $add$ls180.v:8052$2599_Y + attribute \src "ls180.v:8068.73-8068.131" + wire width 33 $add$ls180.v:8068$2602_Y + attribute \src "ls180.v:8081.34-8081.66" + wire width 4 $add$ls180.v:8081$2606_Y + attribute \src "ls180.v:8100.73-8100.131" + wire width 33 $add$ls180.v:8100$2609_Y + attribute \src "ls180.v:8126.33-8126.65" + wire width 4 $add$ls180.v:8126$2617_Y + attribute \src "ls180.v:8129.33-8129.65" + wire width 4 $add$ls180.v:8129$2618_Y + attribute \src "ls180.v:8133.33-8133.64" + wire width 5 $add$ls180.v:8133$2623_Y + attribute \src "ls180.v:8148.33-8148.65" + wire width 4 $add$ls180.v:8148$2628_Y + attribute \src "ls180.v:8151.33-8151.65" + wire width 4 $add$ls180.v:8151$2629_Y + attribute \src "ls180.v:8155.33-8155.64" + wire width 5 $add$ls180.v:8155$2634_Y + attribute \src "ls180.v:8176.35-8176.70" + wire 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"ls180.v:6360.103-6360.148" + wire $eq$ls180.v:6360$2005_Y + attribute \src "ls180.v:6361.106-6361.151" + wire $eq$ls180.v:6361$2009_Y + attribute \src "ls180.v:6380.33-6380.79" + wire $eq$ls180.v:6380$2012_Y + attribute \src "ls180.v:6382.102-6382.147" + wire $eq$ls180.v:6382$2014_Y + attribute \src "ls180.v:6383.105-6383.150" + wire $eq$ls180.v:6383$2018_Y + attribute \src "ls180.v:6385.102-6385.147" + wire $eq$ls180.v:6385$2021_Y + attribute \src "ls180.v:6386.105-6386.150" + wire $eq$ls180.v:6386$2025_Y + attribute \src "ls180.v:6388.100-6388.145" + wire $eq$ls180.v:6388$2028_Y + attribute \src "ls180.v:6389.103-6389.148" + wire $eq$ls180.v:6389$2032_Y + attribute \src "ls180.v:6391.99-6391.144" + wire $eq$ls180.v:6391$2035_Y + attribute \src "ls180.v:6392.102-6392.147" + wire $eq$ls180.v:6392$2039_Y + attribute \src "ls180.v:6394.98-6394.143" + wire $eq$ls180.v:6394$2042_Y + attribute \src "ls180.v:6395.101-6395.146" + wire $eq$ls180.v:6395$2046_Y + attribute \src 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$eq$ls180.v:6535$2263_Y + attribute \src "ls180.v:6536.109-6536.154" + wire $eq$ls180.v:6536$2267_Y + attribute \src "ls180.v:6538.106-6538.151" + wire $eq$ls180.v:6538$2270_Y + attribute \src "ls180.v:6539.109-6539.154" + wire $eq$ls180.v:6539$2274_Y + attribute \src "ls180.v:6541.106-6541.151" + wire $eq$ls180.v:6541$2277_Y + attribute \src "ls180.v:6542.109-6542.154" + wire $eq$ls180.v:6542$2281_Y + attribute \src "ls180.v:6923.41-6923.81" + wire $eq$ls180.v:6923$2318_Y + attribute \src "ls180.v:6923.144-6923.177" + wire $eq$ls180.v:6923$2319_Y + attribute \src "ls180.v:6923.219-6923.252" + wire $eq$ls180.v:6923$2322_Y + attribute \src "ls180.v:6923.294-6923.327" + wire $eq$ls180.v:6923$2325_Y + attribute \src "ls180.v:6947.41-6947.81" + wire $eq$ls180.v:6947$2334_Y + attribute \src "ls180.v:6947.144-6947.177" + wire $eq$ls180.v:6947$2335_Y + attribute \src "ls180.v:6947.219-6947.252" + wire $eq$ls180.v:6947$2338_Y + attribute \src "ls180.v:6947.294-6947.327" + wire $eq$ls180.v:6947$2341_Y + attribute \src "ls180.v:6971.41-6971.81" + wire $eq$ls180.v:6971$2350_Y + attribute \src "ls180.v:6971.144-6971.177" + wire $eq$ls180.v:6971$2351_Y + attribute \src "ls180.v:6971.219-6971.252" + wire $eq$ls180.v:6971$2354_Y + attribute \src "ls180.v:6971.294-6971.327" + wire $eq$ls180.v:6971$2357_Y + attribute \src "ls180.v:6995.41-6995.81" + wire $eq$ls180.v:6995$2366_Y + attribute \src "ls180.v:6995.144-6995.177" + wire $eq$ls180.v:6995$2367_Y + attribute \src "ls180.v:6995.219-6995.252" + wire $eq$ls180.v:6995$2370_Y + attribute \src "ls180.v:6995.294-6995.327" + wire $eq$ls180.v:6995$2373_Y + attribute \src "ls180.v:7579.8-7579.38" + wire $eq$ls180.v:7579$2467_Y + attribute \src "ls180.v:7614.8-7614.42" + wire $eq$ls180.v:7614$2478_Y + attribute \src "ls180.v:7634.38-7634.74" + wire $eq$ls180.v:7634$2481_Y + attribute \src "ls180.v:7641.7-7641.43" + wire $eq$ls180.v:7641$2483_Y + attribute \src "ls180.v:7648.7-7648.43" + wire $eq$ls180.v:7648$2484_Y + attribute \src "ls180.v:7656.7-7656.43" + wire $eq$ls180.v:7656$2485_Y + attribute \src "ls180.v:7708.9-7708.54" + wire $eq$ls180.v:7708$2503_Y + attribute \src "ls180.v:7754.9-7754.54" + wire $eq$ls180.v:7754$2519_Y + attribute \src "ls180.v:7800.9-7800.54" + wire $eq$ls180.v:7800$2535_Y + attribute \src "ls180.v:7846.9-7846.54" + wire $eq$ls180.v:7846$2551_Y + attribute \src "ls180.v:7996.9-7996.41" + wire $eq$ls180.v:7996$2563_Y + attribute \src "ls180.v:8011.9-8011.41" + wire $eq$ls180.v:8011$2566_Y + attribute \src "ls180.v:8017.49-8017.82" + wire $eq$ls180.v:8017$2567_Y + attribute \src "ls180.v:8017.131-8017.164" + wire $eq$ls180.v:8017$2570_Y + attribute \src "ls180.v:8017.213-8017.246" + wire $eq$ls180.v:8017$2573_Y + attribute \src "ls180.v:8017.295-8017.328" + wire $eq$ls180.v:8017$2576_Y + attribute \src "ls180.v:8018.50-8018.83" + wire $eq$ls180.v:8018$2579_Y + attribute \src "ls180.v:8018.132-8018.165" + wire $eq$ls180.v:8018$2582_Y + attribute \src "ls180.v:8018.214-8018.247" + wire $eq$ls180.v:8018$2585_Y + attribute \src "ls180.v:8018.296-8018.329" + wire $eq$ls180.v:8018$2588_Y + attribute \src "ls180.v:8053.9-8053.42" + wire $eq$ls180.v:8053$2600_Y + attribute \src "ls180.v:8056.10-8056.43" + wire $eq$ls180.v:8056$2601_Y + attribute \src "ls180.v:8082.9-8082.42" + wire $eq$ls180.v:8082$2607_Y + attribute \src "ls180.v:8087.10-8087.43" + wire $eq$ls180.v:8087$2608_Y + attribute \src "ls180.v:8294.9-8294.53" + wire $eq$ls180.v:8294$2657_Y + attribute \src "ls180.v:8375.9-8375.54" + wire $eq$ls180.v:8375$2669_Y + attribute \src "ls180.v:8454.9-8454.55" + wire $eq$ls180.v:8454$2681_Y + attribute \src "ls180.v:8677.9-8677.49" + wire $eq$ls180.v:8677$2714_Y + attribute \src "ls180.v:8253.8-8253.54" + wire $ge$ls180.v:8253$2649_Y + attribute \src "ls180.v:8267.8-8267.54" + wire $ge$ls180.v:8267$2653_Y + attribute \src "ls180.v:5211.47-5211.83" + wire $gt$ls180.v:5211$965_Y + attribute \src "ls180.v:5217.7-5217.43" + wire $lt$ls180.v:5217$968_Y + attribute \src "ls180.v:8248.8-8248.43" + wire $lt$ls180.v:8248$2647_Y + attribute \src "ls180.v:8262.8-8262.43" + wire $lt$ls180.v:8262$2651_Y + attribute \src "ls180.v:10164.33-10164.36" + wire width 64 $memrd$\mem$ls180.v:10164$2768_DATA + attribute \src "ls180.v:10192.25-10192.30" + wire width 64 $memrd$\mem_1$ls180.v:10192$2794_DATA + attribute \src "ls180.v:10203.12-10203.19" + wire width 25 $memrd$\storage$ls180.v:10203$2799_DATA + attribute \src "ls180.v:10210.68-10210.75" + wire width 25 $memrd$\storage$ls180.v:10210$2801_DATA + attribute \src "ls180.v:10217.14-10217.23" + wire width 25 $memrd$\storage_1$ls180.v:10217$2806_DATA + attribute \src "ls180.v:10224.68-10224.77" + wire width 25 $memrd$\storage_1$ls180.v:10224$2808_DATA + attribute \src "ls180.v:10231.14-10231.23" + wire width 25 $memrd$\storage_2$ls180.v:10231$2813_DATA + attribute \src "ls180.v:10238.68-10238.77" + wire width 25 $memrd$\storage_2$ls180.v:10238$2815_DATA + attribute \src "ls180.v:10245.14-10245.23" + wire width 25 $memrd$\storage_3$ls180.v:10245$2820_DATA + attribute \src "ls180.v:10252.68-10252.77" + wire width 25 $memrd$\storage_3$ls180.v:10252$2822_DATA + attribute \src "ls180.v:10260.14-10260.23" + wire width 10 $memrd$\storage_4$ls180.v:10260$2827_DATA + attribute \src "ls180.v:10265.15-10265.24" + wire width 10 $memrd$\storage_4$ls180.v:10265$2829_DATA + attribute \src "ls180.v:10277.14-10277.23" + wire width 10 $memrd$\storage_5$ls180.v:10277$2834_DATA + attribute \src "ls180.v:10282.15-10282.24" + wire width 10 $memrd$\storage_5$ls180.v:10282$2836_DATA + attribute \src "ls180.v:10293.14-10293.23" + wire width 10 $memrd$\storage_6$ls180.v:10293$2841_DATA + attribute \src "ls180.v:10300.45-10300.54" + wire width 10 $memrd$\storage_6$ls180.v:10300$2843_DATA + attribute \src "ls180.v:10307.14-10307.23" + wire width 10 $memrd$\storage_7$ls180.v:10307$2848_DATA + attribute \src "ls180.v:10314.45-10314.54" + wire width 10 $memrd$\storage_7$ls180.v:10314$2850_DATA attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_2$ls180.v:10415$19_ADDR + wire width 4 $memwr$\mem$ls180.v:10146$1_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10415$19_DATA + wire width 64 $memwr$\mem$ls180.v:10146$1_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10415$19_EN + wire width 64 $memwr$\mem$ls180.v:10146$1_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_2$ls180.v:10417$20_ADDR + wire width 4 $memwr$\mem$ls180.v:10148$2_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10417$20_DATA + wire width 64 $memwr$\mem$ls180.v:10148$2_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10417$20_EN + wire width 64 $memwr$\mem$ls180.v:10148$2_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_2$ls180.v:10419$21_ADDR + wire width 4 $memwr$\mem$ls180.v:10150$3_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10419$21_DATA + wire width 64 $memwr$\mem$ls180.v:10150$3_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10419$21_EN + wire width 64 $memwr$\mem$ls180.v:10150$3_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_2$ls180.v:10421$22_ADDR + wire width 4 $memwr$\mem$ls180.v:10152$4_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10421$22_DATA + wire width 64 $memwr$\mem$ls180.v:10152$4_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10421$22_EN + wire width 64 $memwr$\mem$ls180.v:10152$4_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_2$ls180.v:10423$23_ADDR + wire width 4 $memwr$\mem$ls180.v:10154$5_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10423$23_DATA + wire width 64 $memwr$\mem$ls180.v:10154$5_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10423$23_EN + wire width 64 $memwr$\mem$ls180.v:10154$5_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_2$ls180.v:10425$24_ADDR + wire width 4 $memwr$\mem$ls180.v:10156$6_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10425$24_DATA + wire width 64 $memwr$\mem$ls180.v:10156$6_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_2$ls180.v:10425$24_EN + wire width 64 $memwr$\mem$ls180.v:10156$6_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10439$25_ADDR + wire width 4 $memwr$\mem$ls180.v:10158$7_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10439$25_DATA + wire width 64 $memwr$\mem$ls180.v:10158$7_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10439$25_EN + wire width 64 $memwr$\mem$ls180.v:10158$7_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10441$26_ADDR + wire width 4 $memwr$\mem$ls180.v:10160$8_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10441$26_DATA + wire width 64 $memwr$\mem$ls180.v:10160$8_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10441$26_EN + wire width 64 $memwr$\mem$ls180.v:10160$8_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10443$27_ADDR + wire width 4 $memwr$\mem_1$ls180.v:10174$9_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10443$27_DATA + wire width 64 $memwr$\mem_1$ls180.v:10174$9_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10443$27_EN + wire width 64 $memwr$\mem_1$ls180.v:10174$9_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10445$28_ADDR + wire width 4 $memwr$\mem_1$ls180.v:10176$10_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10445$28_DATA + wire width 64 $memwr$\mem_1$ls180.v:10176$10_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10445$28_EN + wire width 64 $memwr$\mem_1$ls180.v:10176$10_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10447$29_ADDR + wire width 4 $memwr$\mem_1$ls180.v:10178$11_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10447$29_DATA + wire width 64 $memwr$\mem_1$ls180.v:10178$11_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10447$29_EN + wire width 64 $memwr$\mem_1$ls180.v:10178$11_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10449$30_ADDR + wire width 4 $memwr$\mem_1$ls180.v:10180$12_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10449$30_DATA + wire width 64 $memwr$\mem_1$ls180.v:10180$12_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10449$30_EN + wire width 64 $memwr$\mem_1$ls180.v:10180$12_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10451$31_ADDR + wire width 4 $memwr$\mem_1$ls180.v:10182$13_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10451$31_DATA + wire width 64 $memwr$\mem_1$ls180.v:10182$13_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10451$31_EN + wire width 64 $memwr$\mem_1$ls180.v:10182$13_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_3$ls180.v:10453$32_ADDR + wire width 4 $memwr$\mem_1$ls180.v:10184$14_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10453$32_DATA + wire width 64 $memwr$\mem_1$ls180.v:10184$14_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_3$ls180.v:10453$32_EN + wire width 64 $memwr$\mem_1$ls180.v:10184$14_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10467$33_ADDR + wire width 4 $memwr$\mem_1$ls180.v:10186$15_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10467$33_DATA + wire width 64 $memwr$\mem_1$ls180.v:10186$15_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10467$33_EN + wire width 64 $memwr$\mem_1$ls180.v:10186$15_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10469$34_ADDR + wire width 4 $memwr$\mem_1$ls180.v:10188$16_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10469$34_DATA + wire width 64 $memwr$\mem_1$ls180.v:10188$16_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10469$34_EN + wire width 64 $memwr$\mem_1$ls180.v:10188$16_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10471$35_ADDR + wire width 3 $memwr$\storage$ls180.v:10202$17_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10471$35_DATA + wire width 25 $memwr$\storage$ls180.v:10202$17_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_4$ls180.v:10471$35_EN + wire width 25 $memwr$\storage$ls180.v:10202$17_EN attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem_4$ls180.v:10473$36_ADDR + wire width 3 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"ls180.v:5117.200-5117.272" - wire $xor$ls180.v:5117$873_Y - attribute \src "ls180.v:5117.160-5117.273" - wire $xor$ls180.v:5117$874_Y - attribute \src "ls180.v:5118.353-5118.425" - wire $xor$ls180.v:5118$875_Y - attribute \src "ls180.v:5118.200-5118.272" - wire $xor$ls180.v:5118$876_Y - attribute \src "ls180.v:5118.160-5118.273" - wire $xor$ls180.v:5118$877_Y - attribute \src "ls180.v:5119.353-5119.425" - wire $xor$ls180.v:5119$878_Y - attribute \src "ls180.v:5119.200-5119.272" - wire $xor$ls180.v:5119$879_Y - attribute \src "ls180.v:5119.160-5119.273" - wire $xor$ls180.v:5119$880_Y - attribute \src "ls180.v:5120.353-5120.425" - wire $xor$ls180.v:5120$881_Y - attribute \src "ls180.v:5120.200-5120.272" - wire $xor$ls180.v:5120$882_Y - attribute \src "ls180.v:5120.160-5120.273" - wire $xor$ls180.v:5120$883_Y - attribute \src "ls180.v:5121.353-5121.425" - wire $xor$ls180.v:5121$884_Y - attribute \src "ls180.v:5121.200-5121.272" - wire $xor$ls180.v:5121$885_Y - attribute \src "ls180.v:5121.160-5121.273" - wire $xor$ls180.v:5121$886_Y - attribute \src "ls180.v:5122.354-5122.426" - wire $xor$ls180.v:5122$887_Y - attribute \src "ls180.v:5122.201-5122.273" - wire $xor$ls180.v:5122$888_Y - attribute \src "ls180.v:5122.161-5122.274" - wire $xor$ls180.v:5122$889_Y - attribute \src "ls180.v:5123.361-5123.434" - wire $xor$ls180.v:5123$890_Y - attribute \src "ls180.v:5123.205-5123.278" - wire $xor$ls180.v:5123$891_Y - attribute \src "ls180.v:5123.164-5123.279" - wire $xor$ls180.v:5123$892_Y - attribute \src "ls180.v:5124.361-5124.434" - wire $xor$ls180.v:5124$893_Y - attribute \src "ls180.v:5124.205-5124.278" - wire $xor$ls180.v:5124$894_Y - attribute \src "ls180.v:5124.164-5124.279" - wire $xor$ls180.v:5124$895_Y - attribute \src "ls180.v:5125.361-5125.434" - wire $xor$ls180.v:5125$896_Y - attribute \src "ls180.v:5125.205-5125.278" - wire $xor$ls180.v:5125$897_Y - attribute \src "ls180.v:5125.164-5125.279" - wire $xor$ls180.v:5125$898_Y - attribute \src "ls180.v:5126.361-5126.434" - wire $xor$ls180.v:5126$899_Y - attribute \src "ls180.v:5126.205-5126.278" - wire $xor$ls180.v:5126$900_Y - attribute \src "ls180.v:5126.164-5126.279" - wire $xor$ls180.v:5126$901_Y - attribute \src "ls180.v:5127.361-5127.434" - wire $xor$ls180.v:5127$902_Y - attribute \src "ls180.v:5127.205-5127.278" - wire $xor$ls180.v:5127$903_Y - attribute \src "ls180.v:5127.164-5127.279" - wire $xor$ls180.v:5127$904_Y - attribute \src "ls180.v:5128.361-5128.434" - wire $xor$ls180.v:5128$905_Y - attribute \src "ls180.v:5128.205-5128.278" - wire $xor$ls180.v:5128$906_Y - attribute \src "ls180.v:5128.164-5128.279" - wire $xor$ls180.v:5128$907_Y - attribute \src "ls180.v:5129.361-5129.434" - wire $xor$ls180.v:5129$908_Y - attribute \src "ls180.v:5129.205-5129.278" - wire $xor$ls180.v:5129$909_Y - attribute \src "ls180.v:5129.164-5129.279" - wire $xor$ls180.v:5129$910_Y - attribute \src "ls180.v:5130.361-5130.434" - wire $xor$ls180.v:5130$911_Y - attribute \src "ls180.v:5130.205-5130.278" - wire $xor$ls180.v:5130$912_Y - attribute \src "ls180.v:5130.164-5130.279" - wire $xor$ls180.v:5130$913_Y - attribute \src "ls180.v:5131.361-5131.434" - wire $xor$ls180.v:5131$914_Y - attribute \src "ls180.v:5131.205-5131.278" - wire $xor$ls180.v:5131$915_Y - attribute \src "ls180.v:5131.164-5131.279" - wire $xor$ls180.v:5131$916_Y - attribute \src "ls180.v:5132.361-5132.434" - wire $xor$ls180.v:5132$917_Y - attribute \src "ls180.v:5132.205-5132.278" - wire $xor$ls180.v:5132$918_Y - attribute \src "ls180.v:5132.164-5132.279" - wire $xor$ls180.v:5132$919_Y - attribute \src "ls180.v:5133.361-5133.434" - wire $xor$ls180.v:5133$920_Y - attribute \src "ls180.v:5133.205-5133.278" - wire $xor$ls180.v:5133$921_Y - attribute \src "ls180.v:5133.164-5133.279" - wire $xor$ls180.v:5133$922_Y - attribute \src "ls180.v:5134.361-5134.434" - wire $xor$ls180.v:5134$923_Y - attribute \src "ls180.v:5134.205-5134.278" - wire $xor$ls180.v:5134$924_Y - attribute \src "ls180.v:5134.164-5134.279" - wire $xor$ls180.v:5134$925_Y - attribute \src "ls180.v:5135.361-5135.434" - wire $xor$ls180.v:5135$926_Y - attribute \src "ls180.v:5135.205-5135.278" - wire $xor$ls180.v:5135$927_Y - attribute \src "ls180.v:5135.164-5135.279" - wire $xor$ls180.v:5135$928_Y - attribute \src "ls180.v:5136.361-5136.434" - wire $xor$ls180.v:5136$929_Y - attribute \src "ls180.v:5136.205-5136.278" - wire $xor$ls180.v:5136$930_Y - attribute \src "ls180.v:5136.164-5136.279" - wire $xor$ls180.v:5136$931_Y - attribute \src "ls180.v:5137.361-5137.434" - wire $xor$ls180.v:5137$932_Y - attribute \src "ls180.v:5137.205-5137.278" - wire $xor$ls180.v:5137$933_Y - attribute \src "ls180.v:5137.164-5137.279" - wire $xor$ls180.v:5137$934_Y - attribute \src "ls180.v:5138.361-5138.434" - wire $xor$ls180.v:5138$935_Y - attribute \src "ls180.v:5138.205-5138.278" - wire $xor$ls180.v:5138$936_Y - attribute \src "ls180.v:5138.164-5138.279" - wire $xor$ls180.v:5138$937_Y - attribute \src "ls180.v:5139.361-5139.434" - wire $xor$ls180.v:5139$938_Y - attribute \src "ls180.v:5139.205-5139.278" - wire $xor$ls180.v:5139$939_Y - attribute \src "ls180.v:5139.164-5139.279" - wire $xor$ls180.v:5139$940_Y - attribute \src "ls180.v:5140.361-5140.434" - wire $xor$ls180.v:5140$941_Y - attribute \src "ls180.v:5140.205-5140.278" - wire $xor$ls180.v:5140$942_Y - attribute \src "ls180.v:5140.164-5140.279" - wire $xor$ls180.v:5140$943_Y - attribute \src "ls180.v:5141.361-5141.434" - wire $xor$ls180.v:5141$944_Y - attribute \src "ls180.v:5141.205-5141.278" - wire $xor$ls180.v:5141$945_Y - attribute \src "ls180.v:5141.164-5141.279" - wire $xor$ls180.v:5141$946_Y - attribute \src "ls180.v:5142.361-5142.434" - wire $xor$ls180.v:5142$947_Y - attribute \src "ls180.v:5142.205-5142.278" - wire $xor$ls180.v:5142$948_Y - attribute \src "ls180.v:5142.164-5142.279" - wire $xor$ls180.v:5142$949_Y - attribute \src "ls180.v:5143.360-5143.432" - wire $xor$ls180.v:5143$950_Y - attribute \src "ls180.v:5143.205-5143.277" - wire $xor$ls180.v:5143$951_Y - attribute \src "ls180.v:5143.164-5143.278" - wire $xor$ls180.v:5143$952_Y - attribute \src "ls180.v:5144.360-5144.432" - wire $xor$ls180.v:5144$953_Y - attribute \src "ls180.v:5144.205-5144.277" - wire $xor$ls180.v:5144$954_Y - attribute \src "ls180.v:5144.164-5144.278" - wire $xor$ls180.v:5144$955_Y - attribute \src "ls180.v:5145.360-5145.432" - wire $xor$ls180.v:5145$956_Y - attribute \src "ls180.v:5145.205-5145.277" - wire $xor$ls180.v:5145$957_Y - attribute \src "ls180.v:5145.164-5145.278" - wire $xor$ls180.v:5145$958_Y - attribute \src "ls180.v:5146.360-5146.432" - wire $xor$ls180.v:5146$959_Y - attribute \src "ls180.v:5146.205-5146.277" - wire $xor$ls180.v:5146$960_Y - attribute \src "ls180.v:5146.164-5146.278" - wire $xor$ls180.v:5146$961_Y - attribute \src "ls180.v:5147.360-5147.432" - wire $xor$ls180.v:5147$962_Y - attribute \src "ls180.v:5147.205-5147.277" - wire $xor$ls180.v:5147$963_Y - attribute \src "ls180.v:5147.164-5147.278" - wire $xor$ls180.v:5147$964_Y - attribute \src "ls180.v:5148.360-5148.432" - wire $xor$ls180.v:5148$965_Y - attribute \src "ls180.v:5148.205-5148.277" - wire $xor$ls180.v:5148$966_Y - attribute \src "ls180.v:5148.164-5148.278" - wire $xor$ls180.v:5148$967_Y - attribute \src "ls180.v:5149.360-5149.432" - wire $xor$ls180.v:5149$968_Y - attribute \src "ls180.v:5149.205-5149.277" - wire $xor$ls180.v:5149$969_Y - attribute \src "ls180.v:5149.164-5149.278" - wire $xor$ls180.v:5149$970_Y - attribute \src "ls180.v:5150.360-5150.432" - wire $xor$ls180.v:5150$971_Y - attribute \src "ls180.v:5150.205-5150.277" - wire $xor$ls180.v:5150$972_Y - attribute \src "ls180.v:5150.164-5150.278" - wire $xor$ls180.v:5150$973_Y - attribute \src "ls180.v:5151.360-5151.432" - wire $xor$ls180.v:5151$974_Y - attribute \src "ls180.v:5151.205-5151.277" - wire $xor$ls180.v:5151$975_Y - attribute \src "ls180.v:5151.164-5151.278" - wire $xor$ls180.v:5151$976_Y - attribute \src "ls180.v:5152.360-5152.432" - wire $xor$ls180.v:5152$977_Y - attribute \src "ls180.v:5152.205-5152.277" - wire $xor$ls180.v:5152$978_Y - attribute \src "ls180.v:5152.164-5152.278" - wire $xor$ls180.v:5152$979_Y - attribute \src "ls180.v:5173.899-5173.983" - wire $xor$ls180.v:5173$993_Y - attribute \src "ls180.v:5173.634-5173.718" - wire $xor$ls180.v:5173$994_Y - attribute \src "ls180.v:5173.588-5173.719" - wire $xor$ls180.v:5173$995_Y - attribute \src "ls180.v:5173.234-5173.318" - wire $xor$ls180.v:5173$996_Y - attribute \src "ls180.v:5173.187-5173.319" - wire $xor$ls180.v:5173$997_Y - attribute \src "ls180.v:5174.588-5174.719" - wire $xor$ls180.v:5174$1000_Y - attribute \src "ls180.v:5174.234-5174.318" - wire $xor$ls180.v:5174$1001_Y - attribute \src "ls180.v:5174.187-5174.319" - wire $xor$ls180.v:5174$1002_Y - attribute \src "ls180.v:5174.899-5174.983" - wire $xor$ls180.v:5174$998_Y - attribute \src "ls180.v:5174.634-5174.718" - wire $xor$ls180.v:5174$999_Y - attribute \src "ls180.v:5183.899-5183.983" - wire $xor$ls180.v:5183$1004_Y - attribute \src "ls180.v:5183.634-5183.718" - wire $xor$ls180.v:5183$1005_Y - attribute \src "ls180.v:5183.588-5183.719" - wire $xor$ls180.v:5183$1006_Y - attribute \src "ls180.v:5183.234-5183.318" - wire $xor$ls180.v:5183$1007_Y - attribute \src "ls180.v:5183.187-5183.319" - wire $xor$ls180.v:5183$1008_Y - attribute \src "ls180.v:5184.899-5184.983" - wire $xor$ls180.v:5184$1009_Y - attribute \src "ls180.v:5184.634-5184.718" - wire $xor$ls180.v:5184$1010_Y - attribute \src "ls180.v:5184.588-5184.719" - wire $xor$ls180.v:5184$1011_Y - attribute \src "ls180.v:5184.234-5184.318" - wire $xor$ls180.v:5184$1012_Y - attribute \src "ls180.v:5184.187-5184.319" - wire $xor$ls180.v:5184$1013_Y - attribute \src "ls180.v:5193.899-5193.983" - wire $xor$ls180.v:5193$1015_Y - attribute \src "ls180.v:5193.634-5193.718" - wire $xor$ls180.v:5193$1016_Y - attribute \src "ls180.v:5193.588-5193.719" - wire $xor$ls180.v:5193$1017_Y - attribute \src "ls180.v:5193.234-5193.318" - wire $xor$ls180.v:5193$1018_Y - attribute \src "ls180.v:5193.187-5193.319" - wire $xor$ls180.v:5193$1019_Y - attribute \src "ls180.v:5194.899-5194.983" - wire $xor$ls180.v:5194$1020_Y - attribute \src "ls180.v:5194.634-5194.718" - wire $xor$ls180.v:5194$1021_Y - attribute \src "ls180.v:5194.588-5194.719" - wire $xor$ls180.v:5194$1022_Y - attribute \src "ls180.v:5194.234-5194.318" - wire $xor$ls180.v:5194$1023_Y - attribute \src "ls180.v:5194.187-5194.319" - wire $xor$ls180.v:5194$1024_Y - attribute \src "ls180.v:5203.899-5203.983" - wire $xor$ls180.v:5203$1026_Y - attribute \src "ls180.v:5203.634-5203.718" - wire $xor$ls180.v:5203$1027_Y - attribute \src "ls180.v:5203.588-5203.719" - wire $xor$ls180.v:5203$1028_Y - attribute \src "ls180.v:5203.234-5203.318" - wire $xor$ls180.v:5203$1029_Y - attribute \src "ls180.v:5203.187-5203.319" - wire $xor$ls180.v:5203$1030_Y - attribute \src "ls180.v:5204.899-5204.983" - wire $xor$ls180.v:5204$1031_Y - attribute \src "ls180.v:5204.634-5204.718" - wire $xor$ls180.v:5204$1032_Y - attribute \src "ls180.v:5204.588-5204.719" - wire $xor$ls180.v:5204$1033_Y - attribute \src "ls180.v:5204.234-5204.318" - wire $xor$ls180.v:5204$1034_Y - attribute \src "ls180.v:5204.187-5204.319" - wire $xor$ls180.v:5204$1035_Y - attribute \src "ls180.v:5355.879-5355.961" - wire $xor$ls180.v:5355$1068_Y - attribute \src "ls180.v:5355.620-5355.702" - wire $xor$ls180.v:5355$1069_Y - attribute \src "ls180.v:5355.575-5355.703" - wire $xor$ls180.v:5355$1070_Y - attribute \src "ls180.v:5355.229-5355.311" - wire $xor$ls180.v:5355$1071_Y - attribute \src "ls180.v:5355.183-5355.312" - wire $xor$ls180.v:5355$1072_Y - attribute \src "ls180.v:5356.879-5356.961" - wire $xor$ls180.v:5356$1073_Y - attribute \src "ls180.v:5356.620-5356.702" - wire $xor$ls180.v:5356$1074_Y - attribute \src "ls180.v:5356.575-5356.703" - wire $xor$ls180.v:5356$1075_Y - attribute \src "ls180.v:5356.229-5356.311" - wire $xor$ls180.v:5356$1076_Y - attribute \src "ls180.v:5356.183-5356.312" - wire $xor$ls180.v:5356$1077_Y - attribute \src "ls180.v:5365.879-5365.961" - wire $xor$ls180.v:5365$1079_Y - attribute \src "ls180.v:5365.620-5365.702" - wire $xor$ls180.v:5365$1080_Y - attribute \src "ls180.v:5365.575-5365.703" - wire $xor$ls180.v:5365$1081_Y - attribute \src "ls180.v:5365.229-5365.311" - wire $xor$ls180.v:5365$1082_Y - attribute \src "ls180.v:5365.183-5365.312" - wire $xor$ls180.v:5365$1083_Y - attribute \src "ls180.v:5366.879-5366.961" - wire $xor$ls180.v:5366$1084_Y - attribute \src "ls180.v:5366.620-5366.702" - wire $xor$ls180.v:5366$1085_Y - attribute \src "ls180.v:5366.575-5366.703" - wire $xor$ls180.v:5366$1086_Y - attribute \src "ls180.v:5366.229-5366.311" - wire $xor$ls180.v:5366$1087_Y - attribute \src "ls180.v:5366.183-5366.312" - wire $xor$ls180.v:5366$1088_Y - attribute \src "ls180.v:5375.879-5375.961" - wire $xor$ls180.v:5375$1090_Y - attribute \src "ls180.v:5375.620-5375.702" - wire $xor$ls180.v:5375$1091_Y - attribute \src "ls180.v:5375.575-5375.703" - wire $xor$ls180.v:5375$1092_Y - attribute \src "ls180.v:5375.229-5375.311" - wire $xor$ls180.v:5375$1093_Y - attribute \src "ls180.v:5375.183-5375.312" - wire $xor$ls180.v:5375$1094_Y - attribute \src "ls180.v:5376.879-5376.961" - wire $xor$ls180.v:5376$1095_Y - attribute \src "ls180.v:5376.620-5376.702" - wire $xor$ls180.v:5376$1096_Y - attribute \src "ls180.v:5376.575-5376.703" - wire $xor$ls180.v:5376$1097_Y - attribute \src "ls180.v:5376.229-5376.311" - wire $xor$ls180.v:5376$1098_Y - attribute \src "ls180.v:5376.183-5376.312" - wire $xor$ls180.v:5376$1099_Y - attribute \src "ls180.v:5385.879-5385.961" - wire $xor$ls180.v:5385$1101_Y - attribute \src "ls180.v:5385.620-5385.702" - wire $xor$ls180.v:5385$1102_Y - attribute \src "ls180.v:5385.575-5385.703" - wire $xor$ls180.v:5385$1103_Y - attribute \src "ls180.v:5385.229-5385.311" - wire $xor$ls180.v:5385$1104_Y - attribute \src "ls180.v:5385.183-5385.312" - wire $xor$ls180.v:5385$1105_Y - attribute \src "ls180.v:5386.879-5386.961" - wire $xor$ls180.v:5386$1106_Y - attribute \src "ls180.v:5386.620-5386.702" - wire $xor$ls180.v:5386$1107_Y - attribute \src "ls180.v:5386.575-5386.703" - wire $xor$ls180.v:5386$1108_Y - attribute \src "ls180.v:5386.229-5386.311" - wire $xor$ls180.v:5386$1109_Y - attribute \src "ls180.v:5386.183-5386.312" - wire $xor$ls180.v:5386$1110_Y - attribute \src "ls180.v:1857.11-1857.42" + wire $not$ls180.v:6235$1808_Y + attribute \src "ls180.v:6238.68-6238.99" + wire $not$ls180.v:6238$1815_Y + attribute \src "ls180.v:6241.65-6241.96" + wire $not$ls180.v:6241$1822_Y + attribute \src "ls180.v:6244.66-6244.97" + wire $not$ls180.v:6244$1829_Y + attribute \src "ls180.v:6247.68-6247.99" + wire $not$ls180.v:6247$1836_Y + attribute \src "ls180.v:6250.68-6250.99" + wire $not$ls180.v:6250$1843_Y + attribute \src "ls180.v:6253.68-6253.99" + wire $not$ls180.v:6253$1850_Y + attribute \src "ls180.v:6256.68-6256.99" + wire $not$ls180.v:6256$1857_Y + attribute \src "ls180.v:6281.68-6281.99" + wire $not$ls180.v:6281$1865_Y + attribute \src "ls180.v:6284.73-6284.104" + wire $not$ls180.v:6284$1872_Y + attribute \src "ls180.v:6287.73-6287.104" + wire $not$ls180.v:6287$1879_Y + attribute \src "ls180.v:6290.66-6290.97" + wire $not$ls180.v:6290$1886_Y + attribute \src "ls180.v:6298.70-6298.101" + wire $not$ls180.v:6298$1894_Y + attribute \src "ls180.v:6301.74-6301.105" + wire $not$ls180.v:6301$1901_Y + attribute \src "ls180.v:6304.64-6304.95" + wire $not$ls180.v:6304$1908_Y + attribute \src "ls180.v:6307.74-6307.105" + wire $not$ls180.v:6307$1915_Y + attribute \src "ls180.v:6310.74-6310.105" + wire $not$ls180.v:6310$1922_Y + attribute \src "ls180.v:6313.75-6313.106" + wire $not$ls180.v:6313$1929_Y + attribute \src "ls180.v:6316.73-6316.104" + wire $not$ls180.v:6316$1936_Y + attribute \src "ls180.v:6319.73-6319.104" + wire $not$ls180.v:6319$1943_Y + attribute \src "ls180.v:6322.73-6322.104" + wire $not$ls180.v:6322$1950_Y + attribute \src "ls180.v:6325.73-6325.104" + wire $not$ls180.v:6325$1957_Y + attribute \src "ls180.v:6343.67-6343.99" + wire $not$ls180.v:6343$1965_Y + attribute \src "ls180.v:6346.67-6346.99" + wire $not$ls180.v:6346$1972_Y + attribute \src "ls180.v:6349.65-6349.97" + wire $not$ls180.v:6349$1979_Y + attribute \src "ls180.v:6352.64-6352.96" + wire $not$ls180.v:6352$1986_Y + attribute \src "ls180.v:6355.63-6355.95" + wire $not$ls180.v:6355$1993_Y + attribute \src "ls180.v:6358.62-6358.94" + wire $not$ls180.v:6358$2000_Y + attribute \src "ls180.v:6361.68-6361.100" + wire $not$ls180.v:6361$2007_Y + attribute \src "ls180.v:6383.67-6383.99" + wire $not$ls180.v:6383$2016_Y + attribute \src "ls180.v:6386.67-6386.99" + wire $not$ls180.v:6386$2023_Y + attribute \src "ls180.v:6389.65-6389.97" + wire $not$ls180.v:6389$2030_Y + attribute \src "ls180.v:6392.64-6392.96" + wire $not$ls180.v:6392$2037_Y + attribute \src "ls180.v:6395.63-6395.95" + wire $not$ls180.v:6395$2044_Y + attribute \src "ls180.v:6398.62-6398.94" + wire $not$ls180.v:6398$2051_Y + attribute \src "ls180.v:6401.68-6401.100" + wire $not$ls180.v:6401$2058_Y + attribute \src "ls180.v:6404.71-6404.103" + wire $not$ls180.v:6404$2065_Y + attribute \src "ls180.v:6407.71-6407.103" + wire $not$ls180.v:6407$2072_Y + attribute \src "ls180.v:6431.64-6431.96" + wire $not$ls180.v:6431$2081_Y + attribute \src "ls180.v:6434.64-6434.96" + wire $not$ls180.v:6434$2088_Y + attribute \src "ls180.v:6437.64-6437.96" + wire $not$ls180.v:6437$2095_Y + attribute \src "ls180.v:6440.64-6440.96" + wire $not$ls180.v:6440$2102_Y + attribute \src "ls180.v:6443.66-6443.98" + wire $not$ls180.v:6443$2109_Y + attribute \src "ls180.v:6446.66-6446.98" + wire $not$ls180.v:6446$2116_Y + attribute \src "ls180.v:6449.66-6449.98" + wire $not$ls180.v:6449$2123_Y + attribute \src "ls180.v:6452.66-6452.98" + wire $not$ls180.v:6452$2130_Y + attribute \src "ls180.v:6455.62-6455.94" + wire $not$ls180.v:6455$2137_Y + attribute \src "ls180.v:6458.72-6458.104" + wire $not$ls180.v:6458$2144_Y + attribute \src "ls180.v:6461.65-6461.97" + wire $not$ls180.v:6461$2151_Y + attribute \src "ls180.v:6464.65-6464.97" + wire $not$ls180.v:6464$2158_Y + attribute \src "ls180.v:6467.65-6467.97" + wire $not$ls180.v:6467$2165_Y + attribute \src "ls180.v:6470.65-6470.97" + wire $not$ls180.v:6470$2172_Y + attribute \src "ls180.v:6473.77-6473.109" + wire $not$ls180.v:6473$2179_Y + attribute \src "ls180.v:6476.78-6476.110" + wire $not$ls180.v:6476$2186_Y + attribute \src "ls180.v:6479.69-6479.101" + wire $not$ls180.v:6479$2193_Y + attribute \src "ls180.v:6499.55-6499.87" + wire $not$ls180.v:6499$2201_Y + attribute \src "ls180.v:6502.65-6502.97" + wire $not$ls180.v:6502$2208_Y + attribute \src "ls180.v:6505.66-6505.98" + wire $not$ls180.v:6505$2215_Y + attribute \src "ls180.v:6508.70-6508.102" + wire $not$ls180.v:6508$2222_Y + attribute \src "ls180.v:6511.71-6511.103" + wire $not$ls180.v:6511$2229_Y + attribute \src "ls180.v:6514.69-6514.101" + wire $not$ls180.v:6514$2236_Y + attribute \src "ls180.v:6517.66-6517.98" + wire $not$ls180.v:6517$2243_Y + attribute \src "ls180.v:6520.65-6520.97" + wire $not$ls180.v:6520$2250_Y + attribute \src "ls180.v:6533.71-6533.103" + wire $not$ls180.v:6533$2258_Y + attribute \src "ls180.v:6536.71-6536.103" + wire $not$ls180.v:6536$2265_Y + attribute \src "ls180.v:6539.71-6539.103" + wire $not$ls180.v:6539$2272_Y + attribute \src "ls180.v:6542.71-6542.103" + wire $not$ls180.v:6542$2279_Y + attribute \src "ls180.v:6923.86-6923.330" + wire $not$ls180.v:6923$2328_Y + attribute \src "ls180.v:6947.86-6947.330" + wire $not$ls180.v:6947$2344_Y + attribute \src "ls180.v:6971.86-6971.330" + wire $not$ls180.v:6971$2360_Y + attribute \src "ls180.v:6995.86-6995.330" + wire $not$ls180.v:6995$2376_Y + attribute \src "ls180.v:7496.18-7496.42" + wire $not$ls180.v:7496$2432_Y + attribute \src "ls180.v:7575.72-7575.101" + wire $not$ls180.v:7575$2465_Y + attribute \src "ls180.v:7594.8-7594.38" + wire $not$ls180.v:7594$2469_Y + attribute \src "ls180.v:7598.64-7598.89" + wire $not$ls180.v:7598$2472_Y + attribute \src "ls180.v:7606.32-7606.55" + wire $not$ls180.v:7606$2474_Y + attribute \src "ls180.v:7676.136-7676.189" + wire $not$ls180.v:7676$2489_Y + attribute \src "ls180.v:7682.136-7682.189" + wire $not$ls180.v:7682$2494_Y + attribute \src "ls180.v:7683.8-7683.61" + wire $not$ls180.v:7683$2496_Y + attribute \src "ls180.v:7691.8-7691.56" + wire $not$ls180.v:7691$2499_Y + attribute \src "ls180.v:7706.8-7706.46" + wire $not$ls180.v:7706$2501_Y + attribute \src "ls180.v:7722.136-7722.189" + wire $not$ls180.v:7722$2505_Y + attribute \src "ls180.v:7728.136-7728.189" + wire $not$ls180.v:7728$2510_Y + attribute \src "ls180.v:7729.8-7729.61" + wire $not$ls180.v:7729$2512_Y + attribute \src "ls180.v:7737.8-7737.56" + wire $not$ls180.v:7737$2515_Y + attribute \src "ls180.v:7752.8-7752.46" + wire $not$ls180.v:7752$2517_Y + attribute \src "ls180.v:7768.136-7768.189" + wire $not$ls180.v:7768$2521_Y + attribute \src "ls180.v:7774.136-7774.189" + wire $not$ls180.v:7774$2526_Y + attribute \src "ls180.v:7775.8-7775.61" + wire $not$ls180.v:7775$2528_Y + attribute \src "ls180.v:7783.8-7783.56" + wire $not$ls180.v:7783$2531_Y + attribute \src "ls180.v:7798.8-7798.46" + wire $not$ls180.v:7798$2533_Y + attribute \src "ls180.v:7814.136-7814.189" + wire $not$ls180.v:7814$2537_Y + attribute \src "ls180.v:7820.136-7820.189" + wire $not$ls180.v:7820$2542_Y + attribute \src "ls180.v:7821.8-7821.61" + wire $not$ls180.v:7821$2544_Y + attribute \src "ls180.v:7829.8-7829.56" + wire $not$ls180.v:7829$2547_Y + attribute \src "ls180.v:7844.8-7844.46" + wire $not$ls180.v:7844$2549_Y + attribute \src "ls180.v:7852.7-7852.22" + wire $not$ls180.v:7852$2552_Y + attribute \src "ls180.v:7855.8-7855.29" + wire $not$ls180.v:7855$2553_Y + attribute \src "ls180.v:7859.7-7859.22" + wire $not$ls180.v:7859$2555_Y + attribute \src "ls180.v:7862.8-7862.29" + wire $not$ls180.v:7862$2556_Y + attribute \src "ls180.v:7981.30-7981.60" + wire $not$ls180.v:7981$2558_Y + attribute \src "ls180.v:7982.30-7982.60" + wire $not$ls180.v:7982$2559_Y + attribute \src "ls180.v:7983.29-7983.59" + wire $not$ls180.v:7983$2560_Y + attribute \src "ls180.v:7994.8-7994.33" + wire $not$ls180.v:7994$2561_Y + attribute \src "ls180.v:8009.8-8009.33" + wire $not$ls180.v:8009$2564_Y + attribute \src "ls180.v:8045.36-8045.58" + wire $not$ls180.v:8045$2594_Y + attribute \src "ls180.v:8045.64-8045.89" + wire $not$ls180.v:8045$2596_Y + attribute \src "ls180.v:8074.7-8074.29" + wire $not$ls180.v:8074$2603_Y + attribute \src "ls180.v:8075.9-8075.26" + wire $not$ls180.v:8075$2604_Y + attribute \src "ls180.v:8108.8-8108.29" + wire $not$ls180.v:8108$2610_Y + attribute \src "ls180.v:8115.8-8115.29" + wire $not$ls180.v:8115$2612_Y + attribute \src "ls180.v:8125.80-8125.106" + wire $not$ls180.v:8125$2615_Y + attribute \src "ls180.v:8131.80-8131.106" + wire $not$ls180.v:8131$2620_Y + attribute \src "ls180.v:8132.8-8132.34" + wire $not$ls180.v:8132$2622_Y + attribute \src "ls180.v:8147.80-8147.106" + wire $not$ls180.v:8147$2626_Y + attribute \src "ls180.v:8153.80-8153.106" + wire $not$ls180.v:8153$2631_Y + attribute \src "ls180.v:8154.8-8154.34" + wire $not$ls180.v:8154$2633_Y + attribute \src "ls180.v:8185.22-8185.41" + wire $not$ls180.v:8185$2637_Y + attribute \src "ls180.v:8185.46-8185.73" + wire $not$ls180.v:8185$2638_Y + attribute \src "ls180.v:8220.22-8220.40" + wire $not$ls180.v:8220$2642_Y + attribute \src "ls180.v:8220.45-8220.70" + wire $not$ls180.v:8220$2643_Y + attribute \src "ls180.v:8274.7-8274.31" + wire $not$ls180.v:8274$2654_Y + attribute \src "ls180.v:8346.8-8346.46" + wire $not$ls180.v:8346$2666_Y + attribute \src "ls180.v:8427.8-8427.47" + wire $not$ls180.v:8427$2678_Y + attribute \src "ls180.v:8488.8-8488.48" + wire $not$ls180.v:8488$2690_Y + attribute \src "ls180.v:8658.88-8658.118" + wire $not$ls180.v:8658$2704_Y + attribute \src "ls180.v:8664.88-8664.118" + wire $not$ls180.v:8664$2709_Y + attribute \src "ls180.v:8665.8-8665.38" + wire $not$ls180.v:8665$2711_Y + attribute \src "ls180.v:8756.88-8756.118" + wire $not$ls180.v:8756$2726_Y + attribute \src "ls180.v:8762.88-8762.118" + wire $not$ls180.v:8762$2731_Y + attribute \src "ls180.v:8763.8-8763.38" + wire $not$ls180.v:8763$2733_Y + attribute \src "ls180.v:8783.9-8783.28" + wire $not$ls180.v:8783$2736_Y + attribute \src "ls180.v:8802.9-8802.28" + wire $not$ls180.v:8802$2737_Y + attribute \src "ls180.v:8821.9-8821.28" + wire $not$ls180.v:8821$2738_Y + attribute \src "ls180.v:8840.9-8840.28" + wire $not$ls180.v:8840$2739_Y + attribute \src "ls180.v:8859.9-8859.28" + wire $not$ls180.v:8859$2740_Y + attribute \src "ls180.v:8880.8-8880.21" + wire $not$ls180.v:8880$2741_Y + attribute \src "ls180.v:10416.8-10416.51" + wire $or$ls180.v:10416$2851_Y + attribute \src "ls180.v:2845.10-2845.71" + wire $or$ls180.v:2845$33_Y + attribute \src "ls180.v:2905.10-2905.71" + wire $or$ls180.v:2905$44_Y + attribute \src "ls180.v:2965.10-2965.53" + wire $or$ls180.v:2965$55_Y + attribute \src "ls180.v:3175.39-3175.105" + wire $or$ls180.v:3175$124_Y + attribute \src "ls180.v:3218.59-3218.140" + wire $or$ls180.v:3218$128_Y + attribute \src "ls180.v:3219.44-3219.151" + wire $or$ls180.v:3219$129_Y + attribute \src "ls180.v:3227.45-3227.170" + wire width 13 $or$ls180.v:3227$133_Y + attribute \src "ls180.v:3264.127-3264.245" + wire $or$ls180.v:3264$146_Y + attribute \src "ls180.v:3270.57-3270.157" + wire $or$ls180.v:3270$152_Y + attribute \src "ls180.v:3375.59-3375.140" + wire $or$ls180.v:3375$158_Y + attribute \src "ls180.v:3376.44-3376.151" + wire $or$ls180.v:3376$159_Y + attribute \src "ls180.v:3384.45-3384.170" + wire width 13 $or$ls180.v:3384$163_Y + attribute \src "ls180.v:3421.127-3421.245" + wire $or$ls180.v:3421$176_Y + attribute \src "ls180.v:3427.57-3427.157" + wire $or$ls180.v:3427$182_Y + attribute \src "ls180.v:3532.59-3532.140" + wire $or$ls180.v:3532$188_Y + attribute \src "ls180.v:3533.44-3533.151" + wire $or$ls180.v:3533$189_Y + attribute \src "ls180.v:3541.45-3541.170" + wire width 13 $or$ls180.v:3541$193_Y + attribute \src "ls180.v:3578.127-3578.245" + wire $or$ls180.v:3578$206_Y + attribute \src "ls180.v:3584.57-3584.157" + wire $or$ls180.v:3584$212_Y + attribute \src "ls180.v:3689.59-3689.140" + wire $or$ls180.v:3689$218_Y + attribute \src "ls180.v:3690.44-3690.151" + wire $or$ls180.v:3690$219_Y + attribute \src "ls180.v:3698.45-3698.170" + wire width 13 $or$ls180.v:3698$223_Y + attribute \src "ls180.v:3735.127-3735.245" + wire $or$ls180.v:3735$236_Y + attribute \src "ls180.v:3741.57-3741.157" + wire $or$ls180.v:3741$242_Y + attribute \src "ls180.v:3840.107-3840.193" + wire $or$ls180.v:3840$262_Y + attribute \src "ls180.v:3843.39-3843.204" + wire $or$ls180.v:3843$268_Y + attribute \src "ls180.v:3843.38-3843.289" + wire $or$ls180.v:3843$270_Y + attribute \src "ls180.v:3843.37-3843.374" + wire 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$xor$ls180.v:5042$895_Y + attribute \src "ls180.v:5042.588-5042.719" + wire $xor$ls180.v:5042$896_Y + attribute \src "ls180.v:5042.234-5042.318" + wire $xor$ls180.v:5042$897_Y + attribute \src "ls180.v:5042.187-5042.319" + wire $xor$ls180.v:5042$898_Y + attribute \src "ls180.v:5043.899-5043.983" + wire $xor$ls180.v:5043$899_Y + attribute \src "ls180.v:5043.634-5043.718" + wire $xor$ls180.v:5043$900_Y + attribute \src "ls180.v:5043.588-5043.719" + wire $xor$ls180.v:5043$901_Y + attribute \src "ls180.v:5043.234-5043.318" + wire $xor$ls180.v:5043$902_Y + attribute \src "ls180.v:5043.187-5043.319" + wire $xor$ls180.v:5043$903_Y + attribute \src "ls180.v:5052.899-5052.983" + wire $xor$ls180.v:5052$905_Y + attribute \src "ls180.v:5052.634-5052.718" + wire $xor$ls180.v:5052$906_Y + attribute \src "ls180.v:5052.588-5052.719" + wire $xor$ls180.v:5052$907_Y + attribute \src "ls180.v:5052.234-5052.318" + wire $xor$ls180.v:5052$908_Y + attribute \src "ls180.v:5052.187-5052.319" + wire $xor$ls180.v:5052$909_Y + attribute \src "ls180.v:5053.899-5053.983" + wire $xor$ls180.v:5053$910_Y + attribute \src "ls180.v:5053.634-5053.718" + wire $xor$ls180.v:5053$911_Y + attribute \src "ls180.v:5053.588-5053.719" + wire $xor$ls180.v:5053$912_Y + attribute \src "ls180.v:5053.234-5053.318" + wire $xor$ls180.v:5053$913_Y + attribute \src "ls180.v:5053.187-5053.319" + wire $xor$ls180.v:5053$914_Y + attribute \src "ls180.v:5062.899-5062.983" + wire $xor$ls180.v:5062$916_Y + attribute \src "ls180.v:5062.634-5062.718" + wire $xor$ls180.v:5062$917_Y + attribute \src "ls180.v:5062.588-5062.719" + wire $xor$ls180.v:5062$918_Y + attribute \src "ls180.v:5062.234-5062.318" + wire $xor$ls180.v:5062$919_Y + attribute \src "ls180.v:5062.187-5062.319" + wire $xor$ls180.v:5062$920_Y + attribute \src "ls180.v:5063.899-5063.983" + wire $xor$ls180.v:5063$921_Y + attribute \src "ls180.v:5063.634-5063.718" + wire $xor$ls180.v:5063$922_Y + attribute \src "ls180.v:5063.588-5063.719" + wire $xor$ls180.v:5063$923_Y + attribute \src "ls180.v:5063.234-5063.318" + wire $xor$ls180.v:5063$924_Y + attribute \src "ls180.v:5063.187-5063.319" + wire $xor$ls180.v:5063$925_Y + attribute \src "ls180.v:5072.899-5072.983" + wire $xor$ls180.v:5072$927_Y + attribute \src "ls180.v:5072.634-5072.718" + wire $xor$ls180.v:5072$928_Y + attribute \src "ls180.v:5072.588-5072.719" + wire $xor$ls180.v:5072$929_Y + attribute \src "ls180.v:5072.234-5072.318" + wire $xor$ls180.v:5072$930_Y + attribute \src "ls180.v:5072.187-5072.319" + wire $xor$ls180.v:5072$931_Y + attribute \src "ls180.v:5073.899-5073.983" + wire $xor$ls180.v:5073$932_Y + attribute \src "ls180.v:5073.634-5073.718" + wire $xor$ls180.v:5073$933_Y + attribute \src "ls180.v:5073.588-5073.719" + wire $xor$ls180.v:5073$934_Y + attribute \src "ls180.v:5073.234-5073.318" + wire $xor$ls180.v:5073$935_Y + attribute \src "ls180.v:5073.187-5073.319" + wire $xor$ls180.v:5073$936_Y + attribute \src "ls180.v:5224.879-5224.961" + wire $xor$ls180.v:5224$969_Y + attribute \src "ls180.v:5224.620-5224.702" + wire $xor$ls180.v:5224$970_Y + attribute \src "ls180.v:5224.575-5224.703" + wire $xor$ls180.v:5224$971_Y + attribute \src "ls180.v:5224.229-5224.311" + wire $xor$ls180.v:5224$972_Y + attribute \src "ls180.v:5224.183-5224.312" + wire $xor$ls180.v:5224$973_Y + attribute \src "ls180.v:5225.879-5225.961" + wire $xor$ls180.v:5225$974_Y + attribute \src "ls180.v:5225.620-5225.702" + wire $xor$ls180.v:5225$975_Y + attribute \src "ls180.v:5225.575-5225.703" + wire $xor$ls180.v:5225$976_Y + attribute \src "ls180.v:5225.229-5225.311" + wire $xor$ls180.v:5225$977_Y + attribute \src "ls180.v:5225.183-5225.312" + wire $xor$ls180.v:5225$978_Y + attribute \src "ls180.v:5234.879-5234.961" + wire $xor$ls180.v:5234$980_Y + attribute \src "ls180.v:5234.620-5234.702" + wire $xor$ls180.v:5234$981_Y + attribute \src "ls180.v:5234.575-5234.703" + wire $xor$ls180.v:5234$982_Y + attribute \src "ls180.v:5234.229-5234.311" + wire $xor$ls180.v:5234$983_Y + attribute \src "ls180.v:5234.183-5234.312" + wire $xor$ls180.v:5234$984_Y + attribute \src "ls180.v:5235.879-5235.961" + wire $xor$ls180.v:5235$985_Y + attribute \src "ls180.v:5235.620-5235.702" + wire $xor$ls180.v:5235$986_Y + attribute \src "ls180.v:5235.575-5235.703" + wire $xor$ls180.v:5235$987_Y + attribute \src "ls180.v:5235.229-5235.311" + wire $xor$ls180.v:5235$988_Y + attribute \src "ls180.v:5235.183-5235.312" + wire $xor$ls180.v:5235$989_Y + attribute \src "ls180.v:5244.879-5244.961" + wire $xor$ls180.v:5244$991_Y + attribute \src "ls180.v:5244.620-5244.702" + wire $xor$ls180.v:5244$992_Y + attribute \src "ls180.v:5244.575-5244.703" + wire $xor$ls180.v:5244$993_Y + attribute \src "ls180.v:5244.229-5244.311" + wire $xor$ls180.v:5244$994_Y + attribute \src "ls180.v:5244.183-5244.312" + wire $xor$ls180.v:5244$995_Y + attribute \src "ls180.v:5245.183-5245.312" + wire $xor$ls180.v:5245$1000_Y + attribute \src "ls180.v:5245.879-5245.961" + wire $xor$ls180.v:5245$996_Y + attribute \src "ls180.v:5245.620-5245.702" + wire $xor$ls180.v:5245$997_Y + attribute \src "ls180.v:5245.575-5245.703" + wire $xor$ls180.v:5245$998_Y + attribute \src "ls180.v:5245.229-5245.311" + wire $xor$ls180.v:5245$999_Y + attribute \src "ls180.v:5254.879-5254.961" + wire $xor$ls180.v:5254$1002_Y + attribute \src "ls180.v:5254.620-5254.702" + wire $xor$ls180.v:5254$1003_Y + attribute \src "ls180.v:5254.575-5254.703" + wire $xor$ls180.v:5254$1004_Y + attribute \src "ls180.v:5254.229-5254.311" + wire $xor$ls180.v:5254$1005_Y + attribute \src "ls180.v:5254.183-5254.312" + wire $xor$ls180.v:5254$1006_Y + attribute \src "ls180.v:5255.879-5255.961" + wire $xor$ls180.v:5255$1007_Y + attribute \src "ls180.v:5255.620-5255.702" + wire $xor$ls180.v:5255$1008_Y + attribute \src "ls180.v:5255.575-5255.703" + wire $xor$ls180.v:5255$1009_Y + attribute \src "ls180.v:5255.229-5255.311" + wire $xor$ls180.v:5255$1010_Y + attribute \src "ls180.v:5255.183-5255.312" + wire $xor$ls180.v:5255$1011_Y + attribute \src "ls180.v:1768.11-1768.42" wire width 3 \builder_bankmachine0_next_state - attribute \src "ls180.v:1856.11-1856.37" + attribute \src "ls180.v:1767.11-1767.37" wire width 3 \builder_bankmachine0_state - attribute \src "ls180.v:1859.11-1859.42" + attribute \src "ls180.v:1770.11-1770.42" wire width 3 \builder_bankmachine1_next_state - attribute \src "ls180.v:1858.11-1858.37" + attribute \src "ls180.v:1769.11-1769.37" wire width 3 \builder_bankmachine1_state - attribute \src "ls180.v:1861.11-1861.42" + attribute \src "ls180.v:1772.11-1772.42" wire width 3 \builder_bankmachine2_next_state - attribute \src "ls180.v:1860.11-1860.37" + attribute \src "ls180.v:1771.11-1771.37" wire width 3 \builder_bankmachine2_state - attribute \src "ls180.v:1863.11-1863.42" + attribute \src "ls180.v:1774.11-1774.42" wire width 3 \builder_bankmachine3_next_state - attribute \src "ls180.v:1862.11-1862.37" + attribute \src "ls180.v:1773.11-1773.37" wire width 3 \builder_bankmachine3_state - attribute \src "ls180.v:2716.5-2716.34" + attribute \src "ls180.v:2627.5-2627.34" wire \builder_comb_rhs_array_muxed0 - attribute \src "ls180.v:2717.12-2717.41" + attribute \src "ls180.v:2628.12-2628.41" wire width 13 \builder_comb_rhs_array_muxed1 - attribute \src "ls180.v:2729.5-2729.35" + attribute \src "ls180.v:2640.5-2640.35" wire \builder_comb_rhs_array_muxed10 - attribute \src "ls180.v:2730.5-2730.35" + attribute \src "ls180.v:2641.5-2641.35" wire \builder_comb_rhs_array_muxed11 - attribute \src "ls180.v:2734.12-2734.42" + attribute \src "ls180.v:2645.12-2645.42" wire width 22 \builder_comb_rhs_array_muxed12 - attribute \src "ls180.v:2735.5-2735.35" + attribute \src "ls180.v:2646.5-2646.35" wire \builder_comb_rhs_array_muxed13 - attribute \src "ls180.v:2736.5-2736.35" + attribute \src "ls180.v:2647.5-2647.35" wire \builder_comb_rhs_array_muxed14 - attribute \src "ls180.v:2737.12-2737.42" + attribute \src "ls180.v:2648.12-2648.42" wire width 22 \builder_comb_rhs_array_muxed15 - attribute \src "ls180.v:2738.5-2738.35" + attribute \src "ls180.v:2649.5-2649.35" wire \builder_comb_rhs_array_muxed16 - attribute \src "ls180.v:2739.5-2739.35" + attribute \src "ls180.v:2650.5-2650.35" wire \builder_comb_rhs_array_muxed17 - attribute \src "ls180.v:2740.12-2740.42" + attribute \src "ls180.v:2651.12-2651.42" wire width 22 \builder_comb_rhs_array_muxed18 - attribute \src "ls180.v:2741.5-2741.35" + attribute \src "ls180.v:2652.5-2652.35" wire \builder_comb_rhs_array_muxed19 - attribute \src "ls180.v:2718.11-2718.40" + attribute \src "ls180.v:2629.11-2629.40" wire width 2 \builder_comb_rhs_array_muxed2 - attribute \src "ls180.v:2742.5-2742.35" + attribute \src "ls180.v:2653.5-2653.35" wire \builder_comb_rhs_array_muxed20 - attribute \src "ls180.v:2743.12-2743.42" + attribute \src "ls180.v:2654.12-2654.42" wire width 22 \builder_comb_rhs_array_muxed21 - attribute \src "ls180.v:2744.5-2744.35" + attribute \src "ls180.v:2655.5-2655.35" wire \builder_comb_rhs_array_muxed22 - attribute \src "ls180.v:2745.5-2745.35" + attribute \src "ls180.v:2656.5-2656.35" wire \builder_comb_rhs_array_muxed23 - attribute \src "ls180.v:2746.12-2746.42" + attribute \src "ls180.v:2657.12-2657.42" wire width 32 \builder_comb_rhs_array_muxed24 - attribute \src "ls180.v:2747.12-2747.42" + attribute \src "ls180.v:2658.12-2658.42" wire width 64 \builder_comb_rhs_array_muxed25 - attribute \src "ls180.v:2748.11-2748.41" + attribute \src "ls180.v:2659.11-2659.41" wire width 8 \builder_comb_rhs_array_muxed26 - attribute \src "ls180.v:2749.5-2749.35" + attribute \src "ls180.v:2660.5-2660.35" wire \builder_comb_rhs_array_muxed27 - attribute \src "ls180.v:2750.5-2750.35" + attribute \src "ls180.v:2661.5-2661.35" wire \builder_comb_rhs_array_muxed28 - attribute \src "ls180.v:2751.5-2751.35" + attribute \src "ls180.v:2662.5-2662.35" wire \builder_comb_rhs_array_muxed29 - attribute \src "ls180.v:2719.5-2719.34" + attribute \src "ls180.v:2630.5-2630.34" wire \builder_comb_rhs_array_muxed3 - attribute \src "ls180.v:2752.11-2752.41" + attribute \src "ls180.v:2663.11-2663.41" wire width 3 \builder_comb_rhs_array_muxed30 - attribute \src "ls180.v:2753.11-2753.41" + attribute \src "ls180.v:2664.11-2664.41" wire width 2 \builder_comb_rhs_array_muxed31 - attribute \src "ls180.v:2720.5-2720.34" + attribute \src "ls180.v:2631.5-2631.34" wire \builder_comb_rhs_array_muxed4 - attribute \src "ls180.v:2721.5-2721.34" + attribute \src "ls180.v:2632.5-2632.34" wire \builder_comb_rhs_array_muxed5 - attribute \src "ls180.v:2725.5-2725.34" + attribute \src "ls180.v:2636.5-2636.34" wire \builder_comb_rhs_array_muxed6 - attribute \src "ls180.v:2726.12-2726.41" + attribute \src "ls180.v:2637.12-2637.41" wire width 13 \builder_comb_rhs_array_muxed7 - attribute \src "ls180.v:2727.11-2727.40" + attribute \src "ls180.v:2638.11-2638.40" wire width 2 \builder_comb_rhs_array_muxed8 - attribute \src "ls180.v:2728.5-2728.34" + attribute \src "ls180.v:2639.5-2639.34" wire \builder_comb_rhs_array_muxed9 - attribute \src "ls180.v:2722.5-2722.32" + attribute \src "ls180.v:2633.5-2633.32" wire \builder_comb_t_array_muxed0 - attribute \src "ls180.v:2723.5-2723.32" + attribute \src "ls180.v:2634.5-2634.32" wire \builder_comb_t_array_muxed1 - attribute \src "ls180.v:2724.5-2724.32" + attribute \src "ls180.v:2635.5-2635.32" wire \builder_comb_t_array_muxed2 - attribute \src "ls180.v:2731.5-2731.32" + attribute \src "ls180.v:2642.5-2642.32" wire \builder_comb_t_array_muxed3 - attribute \src "ls180.v:2732.5-2732.32" + attribute \src "ls180.v:2643.5-2643.32" wire \builder_comb_t_array_muxed4 - attribute \src "ls180.v:2733.5-2733.32" + attribute \src "ls180.v:2644.5-2644.32" wire \builder_comb_t_array_muxed5 - attribute \src "ls180.v:1843.5-1843.34" + attribute \src "ls180.v:1754.5-1754.34" wire \builder_converter0_next_state - attribute \src "ls180.v:1842.5-1842.29" + attribute \src "ls180.v:1753.5-1753.29" wire \builder_converter0_state - attribute \src "ls180.v:1847.5-1847.34" + attribute \src "ls180.v:1758.5-1758.34" wire \builder_converter1_next_state - attribute \src "ls180.v:1846.5-1846.29" + attribute \src "ls180.v:1757.5-1757.29" wire \builder_converter1_state - attribute \src "ls180.v:1851.5-1851.34" + attribute \src "ls180.v:1762.5-1762.34" wire \builder_converter2_next_state - attribute \src "ls180.v:1850.5-1850.29" + attribute \src "ls180.v:1761.5-1761.29" wire \builder_converter2_state - attribute \src "ls180.v:1888.5-1888.33" + attribute \src "ls180.v:1799.5-1799.33" wire \builder_converter_next_state - attribute \src "ls180.v:1887.5-1887.28" + attribute \src "ls180.v:1798.5-1798.28" wire \builder_converter_state - attribute \src "ls180.v:2016.12-2016.25" + attribute \src "ls180.v:1927.12-1927.25" wire width 20 \builder_count - attribute \src "ls180.v:2704.13-2704.41" + attribute \src "ls180.v:2615.13-2615.41" wire width 14 \builder_csr_interconnect_adr - attribute \src "ls180.v:2707.12-2707.42" + attribute \src "ls180.v:2618.12-2618.42" wire width 8 \builder_csr_interconnect_dat_r - attribute \src "ls180.v:2706.12-2706.42" + attribute \src "ls180.v:2617.12-2617.42" wire width 8 \builder_csr_interconnect_dat_w - attribute \src "ls180.v:2705.6-2705.33" + attribute \src "ls180.v:2616.6-2616.33" wire \builder_csr_interconnect_we - attribute \src "ls180.v:2054.12-2054.42" + attribute \src "ls180.v:1965.12-1965.42" wire width 8 \builder_csrbank0_bus_errors0_r - attribute \src "ls180.v:2053.6-2053.37" + attribute \src "ls180.v:1964.6-1964.37" wire \builder_csrbank0_bus_errors0_re - attribute \src "ls180.v:2056.12-2056.42" + attribute \src "ls180.v:1967.12-1967.42" wire width 8 \builder_csrbank0_bus_errors0_w - attribute \src "ls180.v:2055.6-2055.37" + attribute \src "ls180.v:1966.6-1966.37" wire \builder_csrbank0_bus_errors0_we - attribute \src "ls180.v:2050.12-2050.42" + attribute \src "ls180.v:1961.12-1961.42" wire width 8 \builder_csrbank0_bus_errors1_r - attribute \src "ls180.v:2049.6-2049.37" + attribute \src "ls180.v:1960.6-1960.37" wire \builder_csrbank0_bus_errors1_re - attribute \src "ls180.v:2052.12-2052.42" + attribute \src "ls180.v:1963.12-1963.42" wire width 8 \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:2051.6-2051.37" + attribute \src "ls180.v:1962.6-1962.37" wire \builder_csrbank0_bus_errors1_we - attribute \src "ls180.v:2046.12-2046.42" + attribute \src "ls180.v:1957.12-1957.42" wire width 8 \builder_csrbank0_bus_errors2_r - attribute \src "ls180.v:2045.6-2045.37" + attribute \src "ls180.v:1956.6-1956.37" wire \builder_csrbank0_bus_errors2_re - attribute \src "ls180.v:2048.12-2048.42" + attribute \src "ls180.v:1959.12-1959.42" wire width 8 \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:2047.6-2047.37" + attribute \src "ls180.v:1958.6-1958.37" wire \builder_csrbank0_bus_errors2_we - attribute \src "ls180.v:2042.12-2042.42" + attribute \src "ls180.v:1953.12-1953.42" wire width 8 \builder_csrbank0_bus_errors3_r - attribute \src "ls180.v:2041.6-2041.37" + attribute \src "ls180.v:1952.6-1952.37" wire \builder_csrbank0_bus_errors3_re - attribute \src "ls180.v:2044.12-2044.42" + attribute \src "ls180.v:1955.12-1955.42" wire width 8 \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:2043.6-2043.37" + attribute \src "ls180.v:1954.6-1954.37" wire \builder_csrbank0_bus_errors3_we - attribute \src "ls180.v:2022.6-2022.31" + attribute \src "ls180.v:1933.6-1933.31" wire \builder_csrbank0_reset0_r - attribute \src "ls180.v:2021.6-2021.32" + attribute \src "ls180.v:1932.6-1932.32" wire \builder_csrbank0_reset0_re - attribute \src "ls180.v:2024.6-2024.31" + attribute \src "ls180.v:1935.6-1935.31" wire \builder_csrbank0_reset0_w - attribute \src "ls180.v:2023.6-2023.32" + attribute \src "ls180.v:1934.6-1934.32" wire \builder_csrbank0_reset0_we - attribute \src "ls180.v:2038.12-2038.39" + attribute \src "ls180.v:1949.12-1949.39" wire width 8 \builder_csrbank0_scratch0_r - attribute \src "ls180.v:2037.6-2037.34" + attribute \src "ls180.v:1948.6-1948.34" wire \builder_csrbank0_scratch0_re - attribute \src "ls180.v:2040.12-2040.39" + attribute \src "ls180.v:1951.12-1951.39" wire width 8 \builder_csrbank0_scratch0_w - attribute \src "ls180.v:2039.6-2039.34" + attribute \src "ls180.v:1950.6-1950.34" wire \builder_csrbank0_scratch0_we - attribute \src "ls180.v:2034.12-2034.39" + attribute \src "ls180.v:1945.12-1945.39" wire width 8 \builder_csrbank0_scratch1_r - attribute \src "ls180.v:2033.6-2033.34" + attribute \src "ls180.v:1944.6-1944.34" wire \builder_csrbank0_scratch1_re - attribute \src "ls180.v:2036.12-2036.39" + attribute \src "ls180.v:1947.12-1947.39" wire width 8 \builder_csrbank0_scratch1_w - attribute \src "ls180.v:2035.6-2035.34" + attribute \src "ls180.v:1946.6-1946.34" wire \builder_csrbank0_scratch1_we - attribute \src "ls180.v:2030.12-2030.39" + attribute \src "ls180.v:1941.12-1941.39" wire width 8 \builder_csrbank0_scratch2_r - attribute \src "ls180.v:2029.6-2029.34" + attribute \src "ls180.v:1940.6-1940.34" wire \builder_csrbank0_scratch2_re - attribute \src "ls180.v:2032.12-2032.39" + attribute \src "ls180.v:1943.12-1943.39" wire width 8 \builder_csrbank0_scratch2_w - attribute \src "ls180.v:2031.6-2031.34" + attribute \src "ls180.v:1942.6-1942.34" wire \builder_csrbank0_scratch2_we - attribute \src "ls180.v:2026.12-2026.39" + attribute \src "ls180.v:1937.12-1937.39" wire width 8 \builder_csrbank0_scratch3_r - attribute \src "ls180.v:2025.6-2025.34" + attribute \src "ls180.v:1936.6-1936.34" wire \builder_csrbank0_scratch3_re - attribute \src "ls180.v:2028.12-2028.39" + attribute \src "ls180.v:1939.12-1939.39" wire width 8 \builder_csrbank0_scratch3_w - attribute \src "ls180.v:2027.6-2027.34" + attribute \src "ls180.v:1938.6-1938.34" wire \builder_csrbank0_scratch3_we - attribute \src "ls180.v:2057.6-2057.26" + attribute \src "ls180.v:1968.6-1968.26" wire \builder_csrbank0_sel - attribute \src "ls180.v:2528.12-2528.40" + attribute \src "ls180.v:2439.12-2439.40" wire width 8 \builder_csrbank10_control0_r - attribute \src "ls180.v:2527.6-2527.35" + attribute \src "ls180.v:2438.6-2438.35" wire \builder_csrbank10_control0_re - attribute \src "ls180.v:2530.12-2530.40" + attribute \src "ls180.v:2441.12-2441.40" wire width 8 \builder_csrbank10_control0_w - attribute \src "ls180.v:2529.6-2529.35" + attribute \src "ls180.v:2440.6-2440.35" wire \builder_csrbank10_control0_we - attribute \src "ls180.v:2524.12-2524.40" + attribute \src "ls180.v:2435.12-2435.40" wire width 8 \builder_csrbank10_control1_r - attribute \src "ls180.v:2523.6-2523.35" + attribute \src "ls180.v:2434.6-2434.35" wire \builder_csrbank10_control1_re - attribute \src "ls180.v:2526.12-2526.40" + attribute \src "ls180.v:2437.12-2437.40" wire width 8 \builder_csrbank10_control1_w - attribute \src "ls180.v:2525.6-2525.35" + attribute \src "ls180.v:2436.6-2436.35" wire \builder_csrbank10_control1_we - attribute \src "ls180.v:2544.6-2544.29" + attribute \src "ls180.v:2455.6-2455.29" wire \builder_csrbank10_cs0_r - attribute \src "ls180.v:2543.6-2543.30" + attribute \src "ls180.v:2454.6-2454.30" wire \builder_csrbank10_cs0_re - attribute \src "ls180.v:2546.6-2546.29" + attribute \src "ls180.v:2457.6-2457.29" wire \builder_csrbank10_cs0_w - attribute \src "ls180.v:2545.6-2545.30" + attribute \src "ls180.v:2456.6-2456.30" wire \builder_csrbank10_cs0_we - attribute \src "ls180.v:2548.6-2548.35" + attribute \src "ls180.v:2459.6-2459.35" wire \builder_csrbank10_loopback0_r - attribute \src "ls180.v:2547.6-2547.36" + attribute \src "ls180.v:2458.6-2458.36" wire \builder_csrbank10_loopback0_re - attribute \src "ls180.v:2550.6-2550.35" + attribute \src "ls180.v:2461.6-2461.35" wire \builder_csrbank10_loopback0_w - attribute \src "ls180.v:2549.6-2549.36" + attribute \src "ls180.v:2460.6-2460.36" wire \builder_csrbank10_loopback0_we - attribute \src "ls180.v:2540.12-2540.36" + attribute \src "ls180.v:2451.12-2451.36" wire width 8 \builder_csrbank10_miso_r - attribute \src "ls180.v:2539.6-2539.31" + attribute \src "ls180.v:2450.6-2450.31" wire \builder_csrbank10_miso_re - attribute \src "ls180.v:2542.12-2542.36" + attribute \src "ls180.v:2453.12-2453.36" wire width 8 \builder_csrbank10_miso_w - attribute \src "ls180.v:2541.6-2541.31" + attribute \src "ls180.v:2452.6-2452.31" wire \builder_csrbank10_miso_we - attribute \src "ls180.v:2536.12-2536.37" + attribute \src "ls180.v:2447.12-2447.37" wire width 8 \builder_csrbank10_mosi0_r - attribute \src "ls180.v:2535.6-2535.32" + attribute \src "ls180.v:2446.6-2446.32" wire \builder_csrbank10_mosi0_re - attribute \src "ls180.v:2538.12-2538.37" + attribute \src "ls180.v:2449.12-2449.37" wire width 8 \builder_csrbank10_mosi0_w - attribute \src "ls180.v:2537.6-2537.32" + attribute \src "ls180.v:2448.6-2448.32" wire \builder_csrbank10_mosi0_we - attribute \src "ls180.v:2551.6-2551.27" + attribute \src "ls180.v:2462.6-2462.27" wire \builder_csrbank10_sel - attribute \src "ls180.v:2532.6-2532.32" + attribute \src "ls180.v:2443.6-2443.32" wire \builder_csrbank10_status_r - attribute \src "ls180.v:2531.6-2531.33" + attribute \src "ls180.v:2442.6-2442.33" wire \builder_csrbank10_status_re - attribute \src "ls180.v:2534.6-2534.32" + attribute \src "ls180.v:2445.6-2445.32" wire \builder_csrbank10_status_w - attribute \src "ls180.v:2533.6-2533.33" + attribute \src "ls180.v:2444.6-2444.33" wire \builder_csrbank10_status_we - attribute \src "ls180.v:2589.12-2589.44" + attribute \src "ls180.v:2500.12-2500.44" wire width 8 \builder_csrbank11_clk_divider0_r - attribute \src "ls180.v:2588.6-2588.39" + attribute \src "ls180.v:2499.6-2499.39" wire \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:2591.12-2591.44" + attribute \src "ls180.v:2502.12-2502.44" wire width 8 \builder_csrbank11_clk_divider0_w - attribute \src "ls180.v:2590.6-2590.39" + attribute \src "ls180.v:2501.6-2501.39" wire \builder_csrbank11_clk_divider0_we - attribute \src "ls180.v:2585.12-2585.44" + attribute \src "ls180.v:2496.12-2496.44" wire width 8 \builder_csrbank11_clk_divider1_r - attribute \src "ls180.v:2584.6-2584.39" + attribute \src "ls180.v:2495.6-2495.39" wire \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:2587.12-2587.44" + attribute \src "ls180.v:2498.12-2498.44" wire width 8 \builder_csrbank11_clk_divider1_w - attribute \src "ls180.v:2586.6-2586.39" + attribute \src "ls180.v:2497.6-2497.39" wire \builder_csrbank11_clk_divider1_we - attribute \src "ls180.v:2561.12-2561.40" + attribute \src "ls180.v:2472.12-2472.40" wire width 8 \builder_csrbank11_control0_r - attribute \src "ls180.v:2560.6-2560.35" + attribute \src "ls180.v:2471.6-2471.35" wire \builder_csrbank11_control0_re - attribute \src "ls180.v:2563.12-2563.40" + attribute \src "ls180.v:2474.12-2474.40" wire width 8 \builder_csrbank11_control0_w - attribute \src "ls180.v:2562.6-2562.35" + attribute \src "ls180.v:2473.6-2473.35" wire \builder_csrbank11_control0_we - attribute \src "ls180.v:2557.12-2557.40" + attribute \src "ls180.v:2468.12-2468.40" wire width 8 \builder_csrbank11_control1_r - attribute \src "ls180.v:2556.6-2556.35" + attribute \src "ls180.v:2467.6-2467.35" wire \builder_csrbank11_control1_re - attribute \src "ls180.v:2559.12-2559.40" + attribute \src "ls180.v:2470.12-2470.40" wire width 8 \builder_csrbank11_control1_w - attribute \src "ls180.v:2558.6-2558.35" + attribute \src "ls180.v:2469.6-2469.35" wire \builder_csrbank11_control1_we - attribute \src "ls180.v:2577.6-2577.29" + attribute \src "ls180.v:2488.6-2488.29" wire \builder_csrbank11_cs0_r - attribute \src "ls180.v:2576.6-2576.30" + attribute \src "ls180.v:2487.6-2487.30" wire \builder_csrbank11_cs0_re - attribute \src "ls180.v:2579.6-2579.29" + attribute \src "ls180.v:2490.6-2490.29" wire \builder_csrbank11_cs0_w - attribute \src "ls180.v:2578.6-2578.30" + attribute \src "ls180.v:2489.6-2489.30" wire \builder_csrbank11_cs0_we - attribute \src "ls180.v:2581.6-2581.35" + attribute \src "ls180.v:2492.6-2492.35" wire \builder_csrbank11_loopback0_r - attribute \src "ls180.v:2580.6-2580.36" + attribute \src "ls180.v:2491.6-2491.36" wire \builder_csrbank11_loopback0_re - attribute \src "ls180.v:2583.6-2583.35" + attribute \src "ls180.v:2494.6-2494.35" wire \builder_csrbank11_loopback0_w - attribute \src "ls180.v:2582.6-2582.36" + attribute \src "ls180.v:2493.6-2493.36" wire \builder_csrbank11_loopback0_we - attribute \src "ls180.v:2573.12-2573.36" + attribute \src "ls180.v:2484.12-2484.36" wire width 8 \builder_csrbank11_miso_r - attribute \src "ls180.v:2572.6-2572.31" + attribute \src "ls180.v:2483.6-2483.31" wire \builder_csrbank11_miso_re - attribute \src "ls180.v:2575.12-2575.36" + attribute \src "ls180.v:2486.12-2486.36" wire width 8 \builder_csrbank11_miso_w - attribute \src "ls180.v:2574.6-2574.31" + attribute \src "ls180.v:2485.6-2485.31" wire \builder_csrbank11_miso_we - attribute \src "ls180.v:2569.12-2569.37" + attribute \src "ls180.v:2480.12-2480.37" wire width 8 \builder_csrbank11_mosi0_r - attribute \src "ls180.v:2568.6-2568.32" + attribute \src "ls180.v:2479.6-2479.32" wire \builder_csrbank11_mosi0_re - attribute \src "ls180.v:2571.12-2571.37" + attribute \src "ls180.v:2482.12-2482.37" wire width 8 \builder_csrbank11_mosi0_w - attribute \src "ls180.v:2570.6-2570.32" + attribute \src "ls180.v:2481.6-2481.32" wire \builder_csrbank11_mosi0_we - attribute \src "ls180.v:2592.6-2592.27" + attribute \src "ls180.v:2503.6-2503.27" wire \builder_csrbank11_sel - attribute \src "ls180.v:2565.6-2565.32" + attribute \src "ls180.v:2476.6-2476.32" wire \builder_csrbank11_status_r - attribute \src "ls180.v:2564.6-2564.33" + attribute \src "ls180.v:2475.6-2475.33" wire \builder_csrbank11_status_re - attribute \src "ls180.v:2567.6-2567.32" + attribute \src "ls180.v:2478.6-2478.32" wire \builder_csrbank11_status_w - attribute \src "ls180.v:2566.6-2566.33" + attribute \src "ls180.v:2477.6-2477.33" wire \builder_csrbank11_status_we - attribute \src "ls180.v:2630.6-2630.29" + attribute \src "ls180.v:2541.6-2541.29" wire \builder_csrbank12_en0_r - attribute \src "ls180.v:2629.6-2629.30" + attribute \src "ls180.v:2540.6-2540.30" wire \builder_csrbank12_en0_re - attribute \src "ls180.v:2632.6-2632.29" + attribute \src "ls180.v:2543.6-2543.29" wire \builder_csrbank12_en0_w - attribute \src "ls180.v:2631.6-2631.30" + attribute \src "ls180.v:2542.6-2542.30" wire \builder_csrbank12_en0_we - attribute \src "ls180.v:2654.6-2654.36" + attribute \src "ls180.v:2565.6-2565.36" wire \builder_csrbank12_ev_enable0_r - attribute \src "ls180.v:2653.6-2653.37" + attribute \src "ls180.v:2564.6-2564.37" wire \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:2656.6-2656.36" + attribute \src "ls180.v:2567.6-2567.36" wire \builder_csrbank12_ev_enable0_w - attribute \src "ls180.v:2655.6-2655.37" + attribute \src "ls180.v:2566.6-2566.37" wire \builder_csrbank12_ev_enable0_we - attribute \src "ls180.v:2610.12-2610.37" + attribute \src "ls180.v:2521.12-2521.37" wire width 8 \builder_csrbank12_load0_r - attribute \src "ls180.v:2609.6-2609.32" + attribute \src "ls180.v:2520.6-2520.32" wire \builder_csrbank12_load0_re - attribute \src "ls180.v:2612.12-2612.37" + attribute \src "ls180.v:2523.12-2523.37" wire width 8 \builder_csrbank12_load0_w - attribute \src "ls180.v:2611.6-2611.32" + attribute \src "ls180.v:2522.6-2522.32" wire \builder_csrbank12_load0_we - attribute \src "ls180.v:2606.12-2606.37" + attribute \src "ls180.v:2517.12-2517.37" wire width 8 \builder_csrbank12_load1_r - attribute \src "ls180.v:2605.6-2605.32" + attribute \src "ls180.v:2516.6-2516.32" wire \builder_csrbank12_load1_re - attribute \src "ls180.v:2608.12-2608.37" + attribute \src "ls180.v:2519.12-2519.37" wire width 8 \builder_csrbank12_load1_w - attribute \src "ls180.v:2607.6-2607.32" + attribute \src "ls180.v:2518.6-2518.32" wire \builder_csrbank12_load1_we - attribute \src "ls180.v:2602.12-2602.37" + attribute \src "ls180.v:2513.12-2513.37" wire width 8 \builder_csrbank12_load2_r - attribute \src "ls180.v:2601.6-2601.32" + attribute \src "ls180.v:2512.6-2512.32" wire \builder_csrbank12_load2_re - attribute \src "ls180.v:2604.12-2604.37" + attribute \src "ls180.v:2515.12-2515.37" wire width 8 \builder_csrbank12_load2_w - attribute \src "ls180.v:2603.6-2603.32" + attribute \src "ls180.v:2514.6-2514.32" wire \builder_csrbank12_load2_we - attribute \src "ls180.v:2598.12-2598.37" + attribute \src "ls180.v:2509.12-2509.37" wire width 8 \builder_csrbank12_load3_r - attribute \src "ls180.v:2597.6-2597.32" + attribute \src "ls180.v:2508.6-2508.32" wire \builder_csrbank12_load3_re - attribute \src "ls180.v:2600.12-2600.37" + attribute \src "ls180.v:2511.12-2511.37" wire width 8 \builder_csrbank12_load3_w - attribute \src "ls180.v:2599.6-2599.32" + attribute \src "ls180.v:2510.6-2510.32" wire \builder_csrbank12_load3_we - attribute \src "ls180.v:2626.12-2626.39" + attribute \src "ls180.v:2537.12-2537.39" wire width 8 \builder_csrbank12_reload0_r - attribute \src "ls180.v:2625.6-2625.34" + attribute \src "ls180.v:2536.6-2536.34" wire \builder_csrbank12_reload0_re - attribute \src "ls180.v:2628.12-2628.39" + attribute \src "ls180.v:2539.12-2539.39" wire width 8 \builder_csrbank12_reload0_w - attribute \src "ls180.v:2627.6-2627.34" + attribute \src "ls180.v:2538.6-2538.34" wire \builder_csrbank12_reload0_we - attribute \src "ls180.v:2622.12-2622.39" + attribute \src "ls180.v:2533.12-2533.39" wire width 8 \builder_csrbank12_reload1_r - attribute \src "ls180.v:2621.6-2621.34" + attribute \src "ls180.v:2532.6-2532.34" wire \builder_csrbank12_reload1_re - attribute \src "ls180.v:2624.12-2624.39" + attribute \src "ls180.v:2535.12-2535.39" wire width 8 \builder_csrbank12_reload1_w - attribute \src "ls180.v:2623.6-2623.34" + attribute \src "ls180.v:2534.6-2534.34" wire \builder_csrbank12_reload1_we - attribute \src "ls180.v:2618.12-2618.39" + attribute \src "ls180.v:2529.12-2529.39" wire width 8 \builder_csrbank12_reload2_r - attribute \src "ls180.v:2617.6-2617.34" + attribute \src "ls180.v:2528.6-2528.34" wire \builder_csrbank12_reload2_re - attribute \src "ls180.v:2620.12-2620.39" + attribute \src "ls180.v:2531.12-2531.39" wire width 8 \builder_csrbank12_reload2_w - attribute \src "ls180.v:2619.6-2619.34" + attribute \src "ls180.v:2530.6-2530.34" wire \builder_csrbank12_reload2_we - attribute \src "ls180.v:2614.12-2614.39" + attribute \src "ls180.v:2525.12-2525.39" wire width 8 \builder_csrbank12_reload3_r - attribute \src "ls180.v:2613.6-2613.34" + attribute \src "ls180.v:2524.6-2524.34" wire \builder_csrbank12_reload3_re - attribute \src "ls180.v:2616.12-2616.39" + attribute \src "ls180.v:2527.12-2527.39" wire width 8 \builder_csrbank12_reload3_w - attribute \src "ls180.v:2615.6-2615.34" + attribute \src "ls180.v:2526.6-2526.34" wire \builder_csrbank12_reload3_we - attribute \src "ls180.v:2657.6-2657.27" + attribute \src "ls180.v:2568.6-2568.27" wire \builder_csrbank12_sel - attribute \src "ls180.v:2634.6-2634.39" + attribute \src "ls180.v:2545.6-2545.39" wire \builder_csrbank12_update_value0_r - attribute \src "ls180.v:2633.6-2633.40" + attribute \src "ls180.v:2544.6-2544.40" wire \builder_csrbank12_update_value0_re - attribute \src "ls180.v:2636.6-2636.39" + attribute \src "ls180.v:2547.6-2547.39" wire \builder_csrbank12_update_value0_w - attribute \src "ls180.v:2635.6-2635.40" + attribute \src "ls180.v:2546.6-2546.40" wire \builder_csrbank12_update_value0_we - attribute \src "ls180.v:2650.12-2650.38" + attribute \src "ls180.v:2561.12-2561.38" wire width 8 \builder_csrbank12_value0_r - attribute \src "ls180.v:2649.6-2649.33" + attribute \src "ls180.v:2560.6-2560.33" wire \builder_csrbank12_value0_re - attribute \src "ls180.v:2652.12-2652.38" + attribute \src "ls180.v:2563.12-2563.38" wire width 8 \builder_csrbank12_value0_w - attribute \src "ls180.v:2651.6-2651.33" + attribute \src "ls180.v:2562.6-2562.33" wire \builder_csrbank12_value0_we - attribute \src "ls180.v:2646.12-2646.38" + attribute \src "ls180.v:2557.12-2557.38" wire width 8 \builder_csrbank12_value1_r - attribute \src "ls180.v:2645.6-2645.33" + attribute \src "ls180.v:2556.6-2556.33" wire \builder_csrbank12_value1_re - attribute \src "ls180.v:2648.12-2648.38" + attribute \src "ls180.v:2559.12-2559.38" wire width 8 \builder_csrbank12_value1_w - attribute \src "ls180.v:2647.6-2647.33" + attribute \src "ls180.v:2558.6-2558.33" wire \builder_csrbank12_value1_we - attribute \src "ls180.v:2642.12-2642.38" + attribute \src "ls180.v:2553.12-2553.38" wire width 8 \builder_csrbank12_value2_r - attribute \src "ls180.v:2641.6-2641.33" + attribute \src "ls180.v:2552.6-2552.33" wire \builder_csrbank12_value2_re - attribute \src "ls180.v:2644.12-2644.38" + attribute \src "ls180.v:2555.12-2555.38" wire width 8 \builder_csrbank12_value2_w - attribute \src "ls180.v:2643.6-2643.33" + attribute \src "ls180.v:2554.6-2554.33" wire \builder_csrbank12_value2_we - attribute \src "ls180.v:2638.12-2638.38" + attribute \src "ls180.v:2549.12-2549.38" wire width 8 \builder_csrbank12_value3_r - attribute \src "ls180.v:2637.6-2637.33" + attribute \src "ls180.v:2548.6-2548.33" wire \builder_csrbank12_value3_re - attribute \src "ls180.v:2640.12-2640.38" + attribute \src "ls180.v:2551.12-2551.38" wire width 8 \builder_csrbank12_value3_w - attribute \src "ls180.v:2639.6-2639.33" + attribute \src "ls180.v:2550.6-2550.33" wire \builder_csrbank12_value3_we - attribute \src "ls180.v:2671.12-2671.42" + attribute \src "ls180.v:2582.12-2582.42" wire width 2 \builder_csrbank13_ev_enable0_r - attribute \src "ls180.v:2670.6-2670.37" + attribute \src "ls180.v:2581.6-2581.37" wire \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:2673.12-2673.42" + attribute \src "ls180.v:2584.12-2584.42" wire width 2 \builder_csrbank13_ev_enable0_w - attribute \src "ls180.v:2672.6-2672.37" + attribute \src "ls180.v:2583.6-2583.37" wire \builder_csrbank13_ev_enable0_we - attribute \src "ls180.v:2667.6-2667.33" + attribute \src "ls180.v:2578.6-2578.33" wire \builder_csrbank13_rxempty_r - attribute \src "ls180.v:2666.6-2666.34" + attribute \src "ls180.v:2577.6-2577.34" wire \builder_csrbank13_rxempty_re - attribute \src "ls180.v:2669.6-2669.33" + attribute \src "ls180.v:2580.6-2580.33" wire \builder_csrbank13_rxempty_w - attribute \src "ls180.v:2668.6-2668.34" + attribute \src "ls180.v:2579.6-2579.34" wire \builder_csrbank13_rxempty_we - attribute \src "ls180.v:2679.6-2679.32" + attribute \src "ls180.v:2590.6-2590.32" wire \builder_csrbank13_rxfull_r - attribute \src "ls180.v:2678.6-2678.33" + attribute \src "ls180.v:2589.6-2589.33" wire \builder_csrbank13_rxfull_re - attribute \src "ls180.v:2681.6-2681.32" + attribute \src "ls180.v:2592.6-2592.32" wire \builder_csrbank13_rxfull_w - attribute \src "ls180.v:2680.6-2680.33" + attribute \src "ls180.v:2591.6-2591.33" wire \builder_csrbank13_rxfull_we - attribute \src "ls180.v:2682.6-2682.27" + attribute \src "ls180.v:2593.6-2593.27" wire \builder_csrbank13_sel - attribute \src "ls180.v:2675.6-2675.33" + attribute \src "ls180.v:2586.6-2586.33" wire \builder_csrbank13_txempty_r - attribute \src "ls180.v:2674.6-2674.34" + attribute \src "ls180.v:2585.6-2585.34" wire \builder_csrbank13_txempty_re - attribute \src "ls180.v:2677.6-2677.33" + attribute \src "ls180.v:2588.6-2588.33" wire \builder_csrbank13_txempty_w - attribute \src "ls180.v:2676.6-2676.34" + attribute \src "ls180.v:2587.6-2587.34" wire \builder_csrbank13_txempty_we - attribute \src "ls180.v:2663.6-2663.32" + attribute \src "ls180.v:2574.6-2574.32" wire \builder_csrbank13_txfull_r - attribute \src "ls180.v:2662.6-2662.33" + attribute \src "ls180.v:2573.6-2573.33" wire \builder_csrbank13_txfull_re - attribute \src "ls180.v:2665.6-2665.32" + attribute \src "ls180.v:2576.6-2576.32" wire \builder_csrbank13_txfull_w - attribute \src "ls180.v:2664.6-2664.33" + attribute \src "ls180.v:2575.6-2575.33" wire \builder_csrbank13_txfull_we - attribute \src "ls180.v:2703.6-2703.27" + attribute \src "ls180.v:2614.6-2614.27" wire \builder_csrbank14_sel - attribute \src "ls180.v:2700.12-2700.44" + attribute \src "ls180.v:2611.12-2611.44" wire width 8 \builder_csrbank14_tuning_word0_r - attribute \src "ls180.v:2699.6-2699.39" + attribute \src "ls180.v:2610.6-2610.39" wire \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:2702.12-2702.44" + attribute \src "ls180.v:2613.12-2613.44" wire width 8 \builder_csrbank14_tuning_word0_w - attribute \src "ls180.v:2701.6-2701.39" + attribute \src "ls180.v:2612.6-2612.39" wire \builder_csrbank14_tuning_word0_we - attribute \src "ls180.v:2696.12-2696.44" + attribute \src "ls180.v:2607.12-2607.44" wire width 8 \builder_csrbank14_tuning_word1_r - attribute \src "ls180.v:2695.6-2695.39" + attribute \src "ls180.v:2606.6-2606.39" wire \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:2698.12-2698.44" + attribute \src "ls180.v:2609.12-2609.44" wire width 8 \builder_csrbank14_tuning_word1_w - attribute \src "ls180.v:2697.6-2697.39" + attribute \src "ls180.v:2608.6-2608.39" wire \builder_csrbank14_tuning_word1_we - attribute \src "ls180.v:2692.12-2692.44" + attribute \src "ls180.v:2603.12-2603.44" wire width 8 \builder_csrbank14_tuning_word2_r - attribute \src "ls180.v:2691.6-2691.39" + attribute \src "ls180.v:2602.6-2602.39" wire \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:2694.12-2694.44" + attribute \src "ls180.v:2605.12-2605.44" wire width 8 \builder_csrbank14_tuning_word2_w - attribute \src "ls180.v:2693.6-2693.39" + attribute \src "ls180.v:2604.6-2604.39" wire \builder_csrbank14_tuning_word2_we - attribute \src "ls180.v:2688.12-2688.44" + attribute \src "ls180.v:2599.12-2599.44" wire width 8 \builder_csrbank14_tuning_word3_r - attribute \src "ls180.v:2687.6-2687.39" + attribute \src "ls180.v:2598.6-2598.39" wire \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:2690.12-2690.44" + attribute \src "ls180.v:2601.12-2601.44" wire width 8 \builder_csrbank14_tuning_word3_w - attribute \src "ls180.v:2689.6-2689.39" + attribute \src "ls180.v:2600.6-2600.39" wire \builder_csrbank14_tuning_word3_we - attribute \src "ls180.v:2075.12-2075.34" + attribute \src "ls180.v:1986.12-1986.34" wire width 8 \builder_csrbank1_in0_r - attribute \src "ls180.v:2074.6-2074.29" + attribute \src "ls180.v:1985.6-1985.29" wire \builder_csrbank1_in0_re - attribute \src "ls180.v:2077.12-2077.34" + attribute \src "ls180.v:1988.12-1988.34" wire width 8 \builder_csrbank1_in0_w - attribute \src "ls180.v:2076.6-2076.29" + attribute \src "ls180.v:1987.6-1987.29" wire \builder_csrbank1_in0_we - attribute \src "ls180.v:2071.12-2071.34" + attribute \src "ls180.v:1982.12-1982.34" wire width 8 \builder_csrbank1_in1_r - attribute \src "ls180.v:2070.6-2070.29" + attribute \src "ls180.v:1981.6-1981.29" wire \builder_csrbank1_in1_re - attribute \src "ls180.v:2073.12-2073.34" + attribute \src "ls180.v:1984.12-1984.34" wire width 8 \builder_csrbank1_in1_w - attribute \src "ls180.v:2072.6-2072.29" + attribute \src "ls180.v:1983.6-1983.29" wire \builder_csrbank1_in1_we - attribute \src "ls180.v:2067.12-2067.34" + attribute \src "ls180.v:1978.12-1978.34" wire width 8 \builder_csrbank1_oe0_r - attribute \src "ls180.v:2066.6-2066.29" + attribute \src "ls180.v:1977.6-1977.29" wire \builder_csrbank1_oe0_re - attribute \src "ls180.v:2069.12-2069.34" + attribute \src "ls180.v:1980.12-1980.34" wire width 8 \builder_csrbank1_oe0_w - attribute \src "ls180.v:2068.6-2068.29" + attribute \src "ls180.v:1979.6-1979.29" wire \builder_csrbank1_oe0_we - attribute \src "ls180.v:2063.12-2063.34" + attribute \src "ls180.v:1974.12-1974.34" wire width 8 \builder_csrbank1_oe1_r - attribute \src "ls180.v:2062.6-2062.29" + attribute \src "ls180.v:1973.6-1973.29" wire \builder_csrbank1_oe1_re - attribute \src "ls180.v:2065.12-2065.34" + attribute \src "ls180.v:1976.12-1976.34" wire width 8 \builder_csrbank1_oe1_w - attribute \src "ls180.v:2064.6-2064.29" + attribute \src "ls180.v:1975.6-1975.29" wire \builder_csrbank1_oe1_we - attribute \src "ls180.v:2083.12-2083.35" + attribute \src "ls180.v:1994.12-1994.35" wire width 8 \builder_csrbank1_out0_r - attribute \src "ls180.v:2082.6-2082.30" + attribute \src "ls180.v:1993.6-1993.30" wire \builder_csrbank1_out0_re - attribute \src "ls180.v:2085.12-2085.35" + attribute \src "ls180.v:1996.12-1996.35" wire width 8 \builder_csrbank1_out0_w - attribute \src "ls180.v:2084.6-2084.30" + attribute \src "ls180.v:1995.6-1995.30" wire \builder_csrbank1_out0_we - attribute \src "ls180.v:2079.12-2079.35" + attribute \src "ls180.v:1990.12-1990.35" wire width 8 \builder_csrbank1_out1_r - attribute \src "ls180.v:2078.6-2078.30" + attribute \src "ls180.v:1989.6-1989.30" wire \builder_csrbank1_out1_re - attribute \src "ls180.v:2081.12-2081.35" + attribute \src "ls180.v:1992.12-1992.35" wire width 8 \builder_csrbank1_out1_w - attribute \src "ls180.v:2080.6-2080.30" + attribute \src "ls180.v:1991.6-1991.30" wire \builder_csrbank1_out1_we - attribute \src "ls180.v:2086.6-2086.26" + attribute \src "ls180.v:1997.6-1997.26" wire \builder_csrbank1_sel - attribute \src "ls180.v:2096.6-2096.26" + attribute \src "ls180.v:2007.6-2007.26" wire \builder_csrbank2_r_r - attribute \src "ls180.v:2095.6-2095.27" + attribute \src "ls180.v:2006.6-2006.27" wire \builder_csrbank2_r_re - attribute \src "ls180.v:2098.6-2098.26" + attribute \src "ls180.v:2009.6-2009.26" wire \builder_csrbank2_r_w - attribute \src "ls180.v:2097.6-2097.27" + attribute \src "ls180.v:2008.6-2008.27" wire \builder_csrbank2_r_we - attribute \src "ls180.v:2099.6-2099.26" + attribute \src "ls180.v:2010.6-2010.26" wire \builder_csrbank2_sel - attribute \src "ls180.v:2092.12-2092.33" + attribute \src "ls180.v:2003.12-2003.33" wire width 3 \builder_csrbank2_w0_r - attribute \src "ls180.v:2091.6-2091.28" + attribute \src "ls180.v:2002.6-2002.28" wire \builder_csrbank2_w0_re - attribute \src "ls180.v:2094.12-2094.33" + attribute \src "ls180.v:2005.12-2005.33" wire width 3 \builder_csrbank2_w0_w - attribute \src "ls180.v:2093.6-2093.28" + attribute \src "ls180.v:2004.6-2004.28" wire \builder_csrbank2_w0_we - attribute \src "ls180.v:2105.6-2105.32" + attribute \src "ls180.v:2016.6-2016.32" wire \builder_csrbank3_enable0_r - attribute \src "ls180.v:2104.6-2104.33" + attribute \src "ls180.v:2015.6-2015.33" wire \builder_csrbank3_enable0_re - attribute \src "ls180.v:2107.6-2107.32" + attribute \src "ls180.v:2018.6-2018.32" wire \builder_csrbank3_enable0_w - attribute \src "ls180.v:2106.6-2106.33" + attribute \src "ls180.v:2017.6-2017.33" wire \builder_csrbank3_enable0_we - attribute \src "ls180.v:2137.12-2137.38" + attribute \src "ls180.v:2048.12-2048.38" wire width 8 \builder_csrbank3_period0_r - attribute \src "ls180.v:2136.6-2136.33" + attribute \src "ls180.v:2047.6-2047.33" wire \builder_csrbank3_period0_re - attribute \src "ls180.v:2139.12-2139.38" + attribute \src "ls180.v:2050.12-2050.38" wire width 8 \builder_csrbank3_period0_w - attribute \src "ls180.v:2138.6-2138.33" + attribute \src "ls180.v:2049.6-2049.33" wire \builder_csrbank3_period0_we - attribute \src "ls180.v:2133.12-2133.38" + attribute \src "ls180.v:2044.12-2044.38" wire width 8 \builder_csrbank3_period1_r - attribute \src "ls180.v:2132.6-2132.33" + attribute \src "ls180.v:2043.6-2043.33" wire \builder_csrbank3_period1_re - attribute \src "ls180.v:2135.12-2135.38" + attribute \src "ls180.v:2046.12-2046.38" wire width 8 \builder_csrbank3_period1_w - attribute \src "ls180.v:2134.6-2134.33" + attribute \src "ls180.v:2045.6-2045.33" wire \builder_csrbank3_period1_we - attribute \src "ls180.v:2129.12-2129.38" + attribute \src "ls180.v:2040.12-2040.38" wire width 8 \builder_csrbank3_period2_r - attribute \src "ls180.v:2128.6-2128.33" + attribute \src "ls180.v:2039.6-2039.33" wire \builder_csrbank3_period2_re - attribute \src "ls180.v:2131.12-2131.38" + attribute \src "ls180.v:2042.12-2042.38" wire width 8 \builder_csrbank3_period2_w - attribute \src "ls180.v:2130.6-2130.33" + attribute \src "ls180.v:2041.6-2041.33" wire \builder_csrbank3_period2_we - attribute \src "ls180.v:2125.12-2125.38" + attribute \src "ls180.v:2036.12-2036.38" wire width 8 \builder_csrbank3_period3_r - attribute \src "ls180.v:2124.6-2124.33" + attribute \src "ls180.v:2035.6-2035.33" wire \builder_csrbank3_period3_re - attribute \src "ls180.v:2127.12-2127.38" + attribute \src "ls180.v:2038.12-2038.38" wire width 8 \builder_csrbank3_period3_w - attribute \src "ls180.v:2126.6-2126.33" + attribute \src "ls180.v:2037.6-2037.33" wire \builder_csrbank3_period3_we - attribute \src "ls180.v:2140.6-2140.26" + attribute \src "ls180.v:2051.6-2051.26" wire \builder_csrbank3_sel - attribute \src "ls180.v:2121.12-2121.37" + attribute \src "ls180.v:2032.12-2032.37" wire width 8 \builder_csrbank3_width0_r - attribute \src "ls180.v:2120.6-2120.32" + attribute \src "ls180.v:2031.6-2031.32" wire \builder_csrbank3_width0_re - attribute \src "ls180.v:2123.12-2123.37" + attribute \src "ls180.v:2034.12-2034.37" wire width 8 \builder_csrbank3_width0_w - attribute \src "ls180.v:2122.6-2122.32" + attribute \src "ls180.v:2033.6-2033.32" wire \builder_csrbank3_width0_we - attribute \src "ls180.v:2117.12-2117.37" + attribute \src "ls180.v:2028.12-2028.37" wire width 8 \builder_csrbank3_width1_r - attribute \src "ls180.v:2116.6-2116.32" + attribute \src "ls180.v:2027.6-2027.32" wire \builder_csrbank3_width1_re - attribute \src "ls180.v:2119.12-2119.37" + attribute \src "ls180.v:2030.12-2030.37" wire width 8 \builder_csrbank3_width1_w - attribute \src "ls180.v:2118.6-2118.32" + attribute \src "ls180.v:2029.6-2029.32" wire \builder_csrbank3_width1_we - attribute \src "ls180.v:2113.12-2113.37" + attribute \src "ls180.v:2024.12-2024.37" wire width 8 \builder_csrbank3_width2_r - attribute \src "ls180.v:2112.6-2112.32" + attribute \src "ls180.v:2023.6-2023.32" wire \builder_csrbank3_width2_re - attribute \src "ls180.v:2115.12-2115.37" + attribute \src "ls180.v:2026.12-2026.37" wire width 8 \builder_csrbank3_width2_w - attribute \src "ls180.v:2114.6-2114.32" + attribute \src "ls180.v:2025.6-2025.32" wire \builder_csrbank3_width2_we - attribute \src "ls180.v:2109.12-2109.37" + attribute \src "ls180.v:2020.12-2020.37" wire width 8 \builder_csrbank3_width3_r - attribute \src "ls180.v:2108.6-2108.32" + attribute \src "ls180.v:2019.6-2019.32" wire \builder_csrbank3_width3_re - attribute \src "ls180.v:2111.12-2111.37" + attribute \src "ls180.v:2022.12-2022.37" wire width 8 \builder_csrbank3_width3_w - attribute \src "ls180.v:2110.6-2110.32" + attribute \src "ls180.v:2021.6-2021.32" wire \builder_csrbank3_width3_we - attribute \src "ls180.v:2146.6-2146.32" + attribute \src "ls180.v:2057.6-2057.32" wire \builder_csrbank4_enable0_r - attribute \src "ls180.v:2145.6-2145.33" + attribute \src "ls180.v:2056.6-2056.33" wire \builder_csrbank4_enable0_re - attribute \src "ls180.v:2148.6-2148.32" + attribute \src "ls180.v:2059.6-2059.32" wire \builder_csrbank4_enable0_w - attribute \src "ls180.v:2147.6-2147.33" + attribute \src "ls180.v:2058.6-2058.33" wire \builder_csrbank4_enable0_we - attribute \src "ls180.v:2178.12-2178.38" + attribute \src "ls180.v:2089.12-2089.38" wire width 8 \builder_csrbank4_period0_r - attribute \src "ls180.v:2177.6-2177.33" + attribute \src "ls180.v:2088.6-2088.33" wire \builder_csrbank4_period0_re - attribute \src "ls180.v:2180.12-2180.38" + attribute \src "ls180.v:2091.12-2091.38" wire width 8 \builder_csrbank4_period0_w - attribute \src "ls180.v:2179.6-2179.33" + attribute \src "ls180.v:2090.6-2090.33" wire \builder_csrbank4_period0_we - attribute \src "ls180.v:2174.12-2174.38" + attribute \src "ls180.v:2085.12-2085.38" wire width 8 \builder_csrbank4_period1_r - attribute \src "ls180.v:2173.6-2173.33" + attribute \src "ls180.v:2084.6-2084.33" wire \builder_csrbank4_period1_re - attribute \src "ls180.v:2176.12-2176.38" + attribute \src "ls180.v:2087.12-2087.38" wire width 8 \builder_csrbank4_period1_w - attribute \src "ls180.v:2175.6-2175.33" + attribute \src "ls180.v:2086.6-2086.33" wire \builder_csrbank4_period1_we - attribute \src "ls180.v:2170.12-2170.38" + attribute \src "ls180.v:2081.12-2081.38" wire width 8 \builder_csrbank4_period2_r - attribute \src "ls180.v:2169.6-2169.33" + attribute \src "ls180.v:2080.6-2080.33" wire \builder_csrbank4_period2_re - attribute \src "ls180.v:2172.12-2172.38" + attribute \src "ls180.v:2083.12-2083.38" wire width 8 \builder_csrbank4_period2_w - attribute \src "ls180.v:2171.6-2171.33" + attribute \src "ls180.v:2082.6-2082.33" wire \builder_csrbank4_period2_we - attribute \src "ls180.v:2166.12-2166.38" + attribute \src "ls180.v:2077.12-2077.38" wire width 8 \builder_csrbank4_period3_r - attribute \src "ls180.v:2165.6-2165.33" + attribute \src "ls180.v:2076.6-2076.33" wire \builder_csrbank4_period3_re - attribute \src "ls180.v:2168.12-2168.38" + attribute \src "ls180.v:2079.12-2079.38" wire width 8 \builder_csrbank4_period3_w - attribute \src "ls180.v:2167.6-2167.33" + attribute \src "ls180.v:2078.6-2078.33" wire \builder_csrbank4_period3_we - attribute \src "ls180.v:2181.6-2181.26" + attribute \src "ls180.v:2092.6-2092.26" wire \builder_csrbank4_sel - attribute \src "ls180.v:2162.12-2162.37" + attribute \src "ls180.v:2073.12-2073.37" wire width 8 \builder_csrbank4_width0_r - attribute \src "ls180.v:2161.6-2161.32" + attribute \src "ls180.v:2072.6-2072.32" wire \builder_csrbank4_width0_re - attribute \src "ls180.v:2164.12-2164.37" + attribute \src "ls180.v:2075.12-2075.37" wire width 8 \builder_csrbank4_width0_w - attribute \src "ls180.v:2163.6-2163.32" + attribute \src "ls180.v:2074.6-2074.32" wire \builder_csrbank4_width0_we - attribute \src "ls180.v:2158.12-2158.37" + attribute \src "ls180.v:2069.12-2069.37" wire width 8 \builder_csrbank4_width1_r - attribute \src "ls180.v:2157.6-2157.32" + attribute \src "ls180.v:2068.6-2068.32" wire \builder_csrbank4_width1_re - attribute \src "ls180.v:2160.12-2160.37" + attribute \src "ls180.v:2071.12-2071.37" wire width 8 \builder_csrbank4_width1_w - attribute \src "ls180.v:2159.6-2159.32" + attribute \src "ls180.v:2070.6-2070.32" wire \builder_csrbank4_width1_we - attribute \src "ls180.v:2154.12-2154.37" + attribute \src "ls180.v:2065.12-2065.37" wire width 8 \builder_csrbank4_width2_r - attribute \src "ls180.v:2153.6-2153.32" + attribute \src "ls180.v:2064.6-2064.32" wire \builder_csrbank4_width2_re - attribute \src "ls180.v:2156.12-2156.37" + attribute \src "ls180.v:2067.12-2067.37" wire width 8 \builder_csrbank4_width2_w - attribute \src "ls180.v:2155.6-2155.32" + attribute \src "ls180.v:2066.6-2066.32" wire \builder_csrbank4_width2_we - attribute \src "ls180.v:2150.12-2150.37" + attribute \src "ls180.v:2061.12-2061.37" wire width 8 \builder_csrbank4_width3_r - attribute \src "ls180.v:2149.6-2149.32" + attribute \src "ls180.v:2060.6-2060.32" wire \builder_csrbank4_width3_re - attribute \src "ls180.v:2152.12-2152.37" + attribute \src "ls180.v:2063.12-2063.37" wire width 8 \builder_csrbank4_width3_w - attribute \src "ls180.v:2151.6-2151.32" + attribute \src "ls180.v:2062.6-2062.32" wire \builder_csrbank4_width3_we - attribute \src "ls180.v:2215.12-2215.40" + attribute \src "ls180.v:2126.12-2126.40" wire width 8 \builder_csrbank5_dma_base0_r - attribute \src "ls180.v:2214.6-2214.35" + attribute \src "ls180.v:2125.6-2125.35" wire \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:2217.12-2217.40" + attribute \src "ls180.v:2128.12-2128.40" wire width 8 \builder_csrbank5_dma_base0_w - attribute \src "ls180.v:2216.6-2216.35" + attribute \src "ls180.v:2127.6-2127.35" wire \builder_csrbank5_dma_base0_we - attribute \src "ls180.v:2211.12-2211.40" + attribute \src "ls180.v:2122.12-2122.40" wire width 8 \builder_csrbank5_dma_base1_r - attribute \src "ls180.v:2210.6-2210.35" + attribute \src "ls180.v:2121.6-2121.35" wire \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:2213.12-2213.40" + attribute \src "ls180.v:2124.12-2124.40" wire width 8 \builder_csrbank5_dma_base1_w - attribute \src "ls180.v:2212.6-2212.35" + attribute \src "ls180.v:2123.6-2123.35" wire \builder_csrbank5_dma_base1_we - attribute \src "ls180.v:2207.12-2207.40" + attribute \src "ls180.v:2118.12-2118.40" wire width 8 \builder_csrbank5_dma_base2_r - attribute \src "ls180.v:2206.6-2206.35" + attribute \src "ls180.v:2117.6-2117.35" wire \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:2209.12-2209.40" + attribute \src "ls180.v:2120.12-2120.40" wire width 8 \builder_csrbank5_dma_base2_w - attribute \src "ls180.v:2208.6-2208.35" + attribute \src "ls180.v:2119.6-2119.35" wire \builder_csrbank5_dma_base2_we - attribute \src "ls180.v:2203.12-2203.40" + attribute \src "ls180.v:2114.12-2114.40" wire width 8 \builder_csrbank5_dma_base3_r - attribute \src "ls180.v:2202.6-2202.35" + attribute \src "ls180.v:2113.6-2113.35" wire \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:2205.12-2205.40" + attribute \src "ls180.v:2116.12-2116.40" wire width 8 \builder_csrbank5_dma_base3_w - attribute \src "ls180.v:2204.6-2204.35" + attribute \src "ls180.v:2115.6-2115.35" wire \builder_csrbank5_dma_base3_we - attribute \src "ls180.v:2199.12-2199.40" + attribute \src "ls180.v:2110.12-2110.40" wire width 8 \builder_csrbank5_dma_base4_r - attribute \src "ls180.v:2198.6-2198.35" + attribute \src "ls180.v:2109.6-2109.35" wire \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:2201.12-2201.40" + attribute \src "ls180.v:2112.12-2112.40" wire width 8 \builder_csrbank5_dma_base4_w - attribute \src "ls180.v:2200.6-2200.35" + attribute \src "ls180.v:2111.6-2111.35" wire \builder_csrbank5_dma_base4_we - attribute \src "ls180.v:2195.12-2195.40" + attribute \src "ls180.v:2106.12-2106.40" wire width 8 \builder_csrbank5_dma_base5_r - attribute \src "ls180.v:2194.6-2194.35" + attribute \src "ls180.v:2105.6-2105.35" wire \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:2197.12-2197.40" + attribute \src "ls180.v:2108.12-2108.40" wire width 8 \builder_csrbank5_dma_base5_w - attribute \src "ls180.v:2196.6-2196.35" + attribute \src "ls180.v:2107.6-2107.35" wire \builder_csrbank5_dma_base5_we - attribute \src "ls180.v:2191.12-2191.40" + attribute \src "ls180.v:2102.12-2102.40" wire width 8 \builder_csrbank5_dma_base6_r - attribute \src "ls180.v:2190.6-2190.35" + attribute \src "ls180.v:2101.6-2101.35" wire \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:2193.12-2193.40" + attribute \src "ls180.v:2104.12-2104.40" wire width 8 \builder_csrbank5_dma_base6_w - attribute \src "ls180.v:2192.6-2192.35" + attribute \src "ls180.v:2103.6-2103.35" wire \builder_csrbank5_dma_base6_we - attribute \src "ls180.v:2187.12-2187.40" + attribute \src "ls180.v:2098.12-2098.40" wire width 8 \builder_csrbank5_dma_base7_r - attribute \src "ls180.v:2186.6-2186.35" + attribute \src "ls180.v:2097.6-2097.35" wire \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:2189.12-2189.40" + attribute \src "ls180.v:2100.12-2100.40" wire width 8 \builder_csrbank5_dma_base7_w - attribute \src "ls180.v:2188.6-2188.35" + attribute \src "ls180.v:2099.6-2099.35" wire \builder_csrbank5_dma_base7_we - attribute \src "ls180.v:2239.6-2239.33" + attribute \src "ls180.v:2150.6-2150.33" wire \builder_csrbank5_dma_done_r - attribute \src "ls180.v:2238.6-2238.34" + attribute \src "ls180.v:2149.6-2149.34" wire \builder_csrbank5_dma_done_re - attribute \src "ls180.v:2241.6-2241.33" + attribute \src "ls180.v:2152.6-2152.33" wire \builder_csrbank5_dma_done_w - attribute \src "ls180.v:2240.6-2240.34" + attribute \src "ls180.v:2151.6-2151.34" wire \builder_csrbank5_dma_done_we - attribute \src "ls180.v:2235.6-2235.36" + attribute \src "ls180.v:2146.6-2146.36" wire \builder_csrbank5_dma_enable0_r - attribute \src "ls180.v:2234.6-2234.37" + attribute \src "ls180.v:2145.6-2145.37" wire \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:2237.6-2237.36" + attribute \src "ls180.v:2148.6-2148.36" wire \builder_csrbank5_dma_enable0_w - attribute \src "ls180.v:2236.6-2236.37" + attribute \src "ls180.v:2147.6-2147.37" wire \builder_csrbank5_dma_enable0_we - attribute \src "ls180.v:2231.12-2231.42" + attribute \src "ls180.v:2142.12-2142.42" wire width 8 \builder_csrbank5_dma_length0_r - attribute \src "ls180.v:2230.6-2230.37" + attribute \src "ls180.v:2141.6-2141.37" wire \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:2233.12-2233.42" + attribute \src "ls180.v:2144.12-2144.42" wire width 8 \builder_csrbank5_dma_length0_w - attribute \src "ls180.v:2232.6-2232.37" + attribute \src "ls180.v:2143.6-2143.37" wire \builder_csrbank5_dma_length0_we - attribute \src "ls180.v:2227.12-2227.42" + attribute \src "ls180.v:2138.12-2138.42" wire width 8 \builder_csrbank5_dma_length1_r - attribute \src "ls180.v:2226.6-2226.37" + attribute \src "ls180.v:2137.6-2137.37" wire \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:2229.12-2229.42" + attribute \src "ls180.v:2140.12-2140.42" wire width 8 \builder_csrbank5_dma_length1_w - attribute \src "ls180.v:2228.6-2228.37" + attribute \src "ls180.v:2139.6-2139.37" wire \builder_csrbank5_dma_length1_we - attribute \src "ls180.v:2223.12-2223.42" + attribute \src "ls180.v:2134.12-2134.42" wire width 8 \builder_csrbank5_dma_length2_r - attribute \src "ls180.v:2222.6-2222.37" + attribute \src "ls180.v:2133.6-2133.37" wire \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:2225.12-2225.42" + attribute \src "ls180.v:2136.12-2136.42" wire width 8 \builder_csrbank5_dma_length2_w - attribute \src "ls180.v:2224.6-2224.37" + attribute \src "ls180.v:2135.6-2135.37" wire \builder_csrbank5_dma_length2_we - attribute \src "ls180.v:2219.12-2219.42" + attribute \src "ls180.v:2130.12-2130.42" wire width 8 \builder_csrbank5_dma_length3_r - attribute \src "ls180.v:2218.6-2218.37" + attribute \src "ls180.v:2129.6-2129.37" wire \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:2221.12-2221.42" + attribute \src "ls180.v:2132.12-2132.42" wire width 8 \builder_csrbank5_dma_length3_w - attribute \src "ls180.v:2220.6-2220.37" + attribute \src "ls180.v:2131.6-2131.37" wire \builder_csrbank5_dma_length3_we - attribute \src "ls180.v:2243.6-2243.34" + attribute \src "ls180.v:2154.6-2154.34" wire \builder_csrbank5_dma_loop0_r - attribute \src "ls180.v:2242.6-2242.35" + attribute \src "ls180.v:2153.6-2153.35" wire \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:2245.6-2245.34" + attribute \src "ls180.v:2156.6-2156.34" wire \builder_csrbank5_dma_loop0_w - attribute \src "ls180.v:2244.6-2244.35" + attribute \src "ls180.v:2155.6-2155.35" wire \builder_csrbank5_dma_loop0_we - attribute \src "ls180.v:2246.6-2246.26" + attribute \src "ls180.v:2157.6-2157.26" wire \builder_csrbank5_sel - attribute \src "ls180.v:2376.12-2376.43" + attribute \src "ls180.v:2287.12-2287.43" wire width 8 \builder_csrbank6_block_count0_r - attribute \src "ls180.v:2375.6-2375.38" + attribute \src "ls180.v:2286.6-2286.38" wire \builder_csrbank6_block_count0_re - attribute \src "ls180.v:2378.12-2378.43" + attribute \src "ls180.v:2289.12-2289.43" wire width 8 \builder_csrbank6_block_count0_w - attribute \src "ls180.v:2377.6-2377.38" + attribute \src "ls180.v:2288.6-2288.38" wire \builder_csrbank6_block_count0_we - attribute \src "ls180.v:2372.12-2372.43" + attribute \src "ls180.v:2283.12-2283.43" wire width 8 \builder_csrbank6_block_count1_r - attribute \src "ls180.v:2371.6-2371.38" + attribute \src "ls180.v:2282.6-2282.38" wire \builder_csrbank6_block_count1_re - attribute \src "ls180.v:2374.12-2374.43" + attribute \src "ls180.v:2285.12-2285.43" wire width 8 \builder_csrbank6_block_count1_w - attribute \src "ls180.v:2373.6-2373.38" + attribute \src "ls180.v:2284.6-2284.38" wire \builder_csrbank6_block_count1_we - attribute \src "ls180.v:2368.12-2368.43" + attribute \src "ls180.v:2279.12-2279.43" wire width 8 \builder_csrbank6_block_count2_r - attribute \src "ls180.v:2367.6-2367.38" + attribute \src "ls180.v:2278.6-2278.38" wire \builder_csrbank6_block_count2_re - attribute \src "ls180.v:2370.12-2370.43" + attribute \src "ls180.v:2281.12-2281.43" wire width 8 \builder_csrbank6_block_count2_w - attribute \src "ls180.v:2369.6-2369.38" + attribute \src "ls180.v:2280.6-2280.38" wire \builder_csrbank6_block_count2_we - attribute \src "ls180.v:2364.12-2364.43" + attribute \src "ls180.v:2275.12-2275.43" wire width 8 \builder_csrbank6_block_count3_r - attribute \src "ls180.v:2363.6-2363.38" + attribute \src "ls180.v:2274.6-2274.38" wire \builder_csrbank6_block_count3_re - attribute \src "ls180.v:2366.12-2366.43" + attribute \src "ls180.v:2277.12-2277.43" wire width 8 \builder_csrbank6_block_count3_w - attribute \src "ls180.v:2365.6-2365.38" + attribute \src "ls180.v:2276.6-2276.38" wire \builder_csrbank6_block_count3_we - attribute \src "ls180.v:2360.12-2360.44" + attribute \src "ls180.v:2271.12-2271.44" wire width 8 \builder_csrbank6_block_length0_r - attribute \src "ls180.v:2359.6-2359.39" + attribute \src "ls180.v:2270.6-2270.39" wire \builder_csrbank6_block_length0_re - attribute \src "ls180.v:2362.12-2362.44" + attribute \src "ls180.v:2273.12-2273.44" wire width 8 \builder_csrbank6_block_length0_w - attribute \src "ls180.v:2361.6-2361.39" + attribute \src "ls180.v:2272.6-2272.39" wire \builder_csrbank6_block_length0_we - attribute \src "ls180.v:2356.12-2356.44" + attribute \src "ls180.v:2267.12-2267.44" wire width 2 \builder_csrbank6_block_length1_r - attribute \src "ls180.v:2355.6-2355.39" + attribute \src "ls180.v:2266.6-2266.39" wire \builder_csrbank6_block_length1_re - attribute \src "ls180.v:2358.12-2358.44" + attribute \src "ls180.v:2269.12-2269.44" wire width 2 \builder_csrbank6_block_length1_w - attribute \src "ls180.v:2357.6-2357.39" + attribute \src "ls180.v:2268.6-2268.39" wire \builder_csrbank6_block_length1_we - attribute \src "ls180.v:2264.12-2264.44" + attribute \src "ls180.v:2175.12-2175.44" wire width 8 \builder_csrbank6_cmd_argument0_r - attribute \src "ls180.v:2263.6-2263.39" + attribute \src "ls180.v:2174.6-2174.39" wire \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:2266.12-2266.44" + attribute \src "ls180.v:2177.12-2177.44" wire width 8 \builder_csrbank6_cmd_argument0_w - attribute \src "ls180.v:2265.6-2265.39" + attribute \src "ls180.v:2176.6-2176.39" wire \builder_csrbank6_cmd_argument0_we - attribute \src "ls180.v:2260.12-2260.44" + attribute \src "ls180.v:2171.12-2171.44" wire width 8 \builder_csrbank6_cmd_argument1_r - attribute \src "ls180.v:2259.6-2259.39" + attribute \src "ls180.v:2170.6-2170.39" wire \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:2262.12-2262.44" + attribute \src "ls180.v:2173.12-2173.44" wire width 8 \builder_csrbank6_cmd_argument1_w - attribute \src "ls180.v:2261.6-2261.39" + attribute \src "ls180.v:2172.6-2172.39" wire \builder_csrbank6_cmd_argument1_we - attribute \src "ls180.v:2256.12-2256.44" + attribute \src "ls180.v:2167.12-2167.44" wire width 8 \builder_csrbank6_cmd_argument2_r - attribute \src "ls180.v:2255.6-2255.39" + attribute \src "ls180.v:2166.6-2166.39" wire \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:2258.12-2258.44" + attribute \src "ls180.v:2169.12-2169.44" wire width 8 \builder_csrbank6_cmd_argument2_w - attribute \src "ls180.v:2257.6-2257.39" + attribute \src "ls180.v:2168.6-2168.39" wire \builder_csrbank6_cmd_argument2_we - attribute \src "ls180.v:2252.12-2252.44" + attribute \src "ls180.v:2163.12-2163.44" wire width 8 \builder_csrbank6_cmd_argument3_r - attribute \src "ls180.v:2251.6-2251.39" + attribute \src "ls180.v:2162.6-2162.39" wire \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:2254.12-2254.44" + attribute \src "ls180.v:2165.12-2165.44" wire width 8 \builder_csrbank6_cmd_argument3_w - attribute \src "ls180.v:2253.6-2253.39" + attribute \src "ls180.v:2164.6-2164.39" wire \builder_csrbank6_cmd_argument3_we - attribute \src "ls180.v:2280.12-2280.43" + attribute \src "ls180.v:2191.12-2191.43" wire width 8 \builder_csrbank6_cmd_command0_r - attribute \src "ls180.v:2279.6-2279.38" + attribute \src "ls180.v:2190.6-2190.38" wire \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:2282.12-2282.43" + attribute \src "ls180.v:2193.12-2193.43" wire width 8 \builder_csrbank6_cmd_command0_w - attribute \src "ls180.v:2281.6-2281.38" + attribute \src "ls180.v:2192.6-2192.38" wire \builder_csrbank6_cmd_command0_we - attribute \src "ls180.v:2276.12-2276.43" + attribute \src "ls180.v:2187.12-2187.43" wire width 8 \builder_csrbank6_cmd_command1_r - attribute \src "ls180.v:2275.6-2275.38" + attribute \src "ls180.v:2186.6-2186.38" wire \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:2278.12-2278.43" + attribute \src "ls180.v:2189.12-2189.43" wire width 8 \builder_csrbank6_cmd_command1_w - attribute \src "ls180.v:2277.6-2277.38" + attribute \src "ls180.v:2188.6-2188.38" wire \builder_csrbank6_cmd_command1_we - attribute \src "ls180.v:2272.12-2272.43" + attribute \src "ls180.v:2183.12-2183.43" wire width 8 \builder_csrbank6_cmd_command2_r - attribute \src "ls180.v:2271.6-2271.38" + attribute \src "ls180.v:2182.6-2182.38" wire \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:2274.12-2274.43" + attribute \src "ls180.v:2185.12-2185.43" wire width 8 \builder_csrbank6_cmd_command2_w - attribute \src "ls180.v:2273.6-2273.38" + attribute \src "ls180.v:2184.6-2184.38" wire \builder_csrbank6_cmd_command2_we - attribute \src "ls180.v:2268.12-2268.43" + attribute \src "ls180.v:2179.12-2179.43" wire width 8 \builder_csrbank6_cmd_command3_r - attribute \src "ls180.v:2267.6-2267.38" + attribute \src "ls180.v:2178.6-2178.38" wire \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:2270.12-2270.43" + attribute \src "ls180.v:2181.12-2181.43" wire width 8 \builder_csrbank6_cmd_command3_w - attribute \src "ls180.v:2269.6-2269.38" + attribute \src "ls180.v:2180.6-2180.38" wire \builder_csrbank6_cmd_command3_we - attribute \src "ls180.v:2348.12-2348.40" + attribute \src "ls180.v:2259.12-2259.40" wire width 4 \builder_csrbank6_cmd_event_r - attribute \src "ls180.v:2347.6-2347.35" + attribute \src "ls180.v:2258.6-2258.35" wire \builder_csrbank6_cmd_event_re - attribute \src "ls180.v:2350.12-2350.40" + attribute \src "ls180.v:2261.12-2261.40" wire width 4 \builder_csrbank6_cmd_event_w - attribute \src "ls180.v:2349.6-2349.35" + attribute \src "ls180.v:2260.6-2260.35" wire \builder_csrbank6_cmd_event_we - attribute \src "ls180.v:2344.12-2344.44" + attribute \src "ls180.v:2255.12-2255.44" wire width 8 \builder_csrbank6_cmd_response0_r - attribute \src "ls180.v:2343.6-2343.39" + attribute \src "ls180.v:2254.6-2254.39" wire \builder_csrbank6_cmd_response0_re - attribute \src "ls180.v:2346.12-2346.44" + attribute \src "ls180.v:2257.12-2257.44" wire width 8 \builder_csrbank6_cmd_response0_w - attribute \src "ls180.v:2345.6-2345.39" + attribute \src "ls180.v:2256.6-2256.39" wire \builder_csrbank6_cmd_response0_we - attribute \src "ls180.v:2304.12-2304.45" + attribute \src "ls180.v:2215.12-2215.45" wire width 8 \builder_csrbank6_cmd_response10_r - attribute \src "ls180.v:2303.6-2303.40" + attribute \src "ls180.v:2214.6-2214.40" wire \builder_csrbank6_cmd_response10_re - attribute \src "ls180.v:2306.12-2306.45" + attribute \src "ls180.v:2217.12-2217.45" wire width 8 \builder_csrbank6_cmd_response10_w - attribute \src "ls180.v:2305.6-2305.40" + attribute \src "ls180.v:2216.6-2216.40" wire \builder_csrbank6_cmd_response10_we - attribute \src "ls180.v:2300.12-2300.45" + attribute \src "ls180.v:2211.12-2211.45" wire width 8 \builder_csrbank6_cmd_response11_r - attribute \src "ls180.v:2299.6-2299.40" + attribute \src "ls180.v:2210.6-2210.40" wire \builder_csrbank6_cmd_response11_re - attribute \src "ls180.v:2302.12-2302.45" + attribute \src "ls180.v:2213.12-2213.45" wire width 8 \builder_csrbank6_cmd_response11_w - attribute \src "ls180.v:2301.6-2301.40" + attribute \src "ls180.v:2212.6-2212.40" wire \builder_csrbank6_cmd_response11_we - attribute \src "ls180.v:2296.12-2296.45" + attribute \src "ls180.v:2207.12-2207.45" wire width 8 \builder_csrbank6_cmd_response12_r - attribute \src "ls180.v:2295.6-2295.40" + attribute \src "ls180.v:2206.6-2206.40" wire \builder_csrbank6_cmd_response12_re - attribute \src "ls180.v:2298.12-2298.45" + attribute \src "ls180.v:2209.12-2209.45" wire width 8 \builder_csrbank6_cmd_response12_w - attribute \src "ls180.v:2297.6-2297.40" + attribute \src "ls180.v:2208.6-2208.40" wire \builder_csrbank6_cmd_response12_we - attribute \src "ls180.v:2292.12-2292.45" + attribute \src "ls180.v:2203.12-2203.45" wire width 8 \builder_csrbank6_cmd_response13_r - attribute \src "ls180.v:2291.6-2291.40" + attribute \src "ls180.v:2202.6-2202.40" wire \builder_csrbank6_cmd_response13_re - attribute \src "ls180.v:2294.12-2294.45" + attribute \src "ls180.v:2205.12-2205.45" wire width 8 \builder_csrbank6_cmd_response13_w - attribute \src "ls180.v:2293.6-2293.40" + attribute \src "ls180.v:2204.6-2204.40" wire \builder_csrbank6_cmd_response13_we - attribute \src "ls180.v:2288.12-2288.45" + attribute \src "ls180.v:2199.12-2199.45" wire width 8 \builder_csrbank6_cmd_response14_r - attribute \src "ls180.v:2287.6-2287.40" + attribute \src "ls180.v:2198.6-2198.40" wire \builder_csrbank6_cmd_response14_re - attribute \src "ls180.v:2290.12-2290.45" + attribute \src "ls180.v:2201.12-2201.45" wire width 8 \builder_csrbank6_cmd_response14_w - attribute \src "ls180.v:2289.6-2289.40" + attribute \src "ls180.v:2200.6-2200.40" wire \builder_csrbank6_cmd_response14_we - attribute \src "ls180.v:2284.12-2284.45" + attribute \src "ls180.v:2195.12-2195.45" wire width 8 \builder_csrbank6_cmd_response15_r - attribute \src "ls180.v:2283.6-2283.40" + attribute \src "ls180.v:2194.6-2194.40" wire \builder_csrbank6_cmd_response15_re - attribute \src "ls180.v:2286.12-2286.45" + attribute \src "ls180.v:2197.12-2197.45" wire width 8 \builder_csrbank6_cmd_response15_w - attribute \src "ls180.v:2285.6-2285.40" + attribute \src "ls180.v:2196.6-2196.40" wire \builder_csrbank6_cmd_response15_we - attribute \src "ls180.v:2340.12-2340.44" + attribute \src "ls180.v:2251.12-2251.44" wire width 8 \builder_csrbank6_cmd_response1_r - attribute \src "ls180.v:2339.6-2339.39" + attribute \src "ls180.v:2250.6-2250.39" wire \builder_csrbank6_cmd_response1_re - attribute \src "ls180.v:2342.12-2342.44" + attribute \src "ls180.v:2253.12-2253.44" wire width 8 \builder_csrbank6_cmd_response1_w - attribute \src "ls180.v:2341.6-2341.39" + attribute \src "ls180.v:2252.6-2252.39" wire \builder_csrbank6_cmd_response1_we - attribute \src "ls180.v:2336.12-2336.44" + attribute \src "ls180.v:2247.12-2247.44" wire width 8 \builder_csrbank6_cmd_response2_r - attribute \src "ls180.v:2335.6-2335.39" + attribute \src "ls180.v:2246.6-2246.39" wire \builder_csrbank6_cmd_response2_re - attribute \src "ls180.v:2338.12-2338.44" + attribute \src "ls180.v:2249.12-2249.44" wire width 8 \builder_csrbank6_cmd_response2_w - attribute \src "ls180.v:2337.6-2337.39" + attribute \src "ls180.v:2248.6-2248.39" wire \builder_csrbank6_cmd_response2_we - attribute \src "ls180.v:2332.12-2332.44" + attribute \src "ls180.v:2243.12-2243.44" wire width 8 \builder_csrbank6_cmd_response3_r - attribute \src "ls180.v:2331.6-2331.39" + attribute \src "ls180.v:2242.6-2242.39" wire \builder_csrbank6_cmd_response3_re - attribute \src "ls180.v:2334.12-2334.44" + attribute \src "ls180.v:2245.12-2245.44" wire width 8 \builder_csrbank6_cmd_response3_w - attribute \src "ls180.v:2333.6-2333.39" + attribute \src "ls180.v:2244.6-2244.39" wire \builder_csrbank6_cmd_response3_we - attribute \src "ls180.v:2328.12-2328.44" + attribute \src "ls180.v:2239.12-2239.44" wire width 8 \builder_csrbank6_cmd_response4_r - attribute \src "ls180.v:2327.6-2327.39" + attribute \src "ls180.v:2238.6-2238.39" wire \builder_csrbank6_cmd_response4_re - attribute \src "ls180.v:2330.12-2330.44" + attribute \src "ls180.v:2241.12-2241.44" wire width 8 \builder_csrbank6_cmd_response4_w - attribute \src "ls180.v:2329.6-2329.39" + attribute \src "ls180.v:2240.6-2240.39" wire \builder_csrbank6_cmd_response4_we - attribute \src "ls180.v:2324.12-2324.44" + attribute \src "ls180.v:2235.12-2235.44" wire width 8 \builder_csrbank6_cmd_response5_r - attribute \src "ls180.v:2323.6-2323.39" + attribute \src "ls180.v:2234.6-2234.39" wire \builder_csrbank6_cmd_response5_re - attribute \src "ls180.v:2326.12-2326.44" + attribute \src "ls180.v:2237.12-2237.44" wire width 8 \builder_csrbank6_cmd_response5_w - attribute \src "ls180.v:2325.6-2325.39" + attribute \src "ls180.v:2236.6-2236.39" wire \builder_csrbank6_cmd_response5_we - attribute \src "ls180.v:2320.12-2320.44" + attribute \src "ls180.v:2231.12-2231.44" wire width 8 \builder_csrbank6_cmd_response6_r - attribute \src "ls180.v:2319.6-2319.39" + attribute \src "ls180.v:2230.6-2230.39" wire \builder_csrbank6_cmd_response6_re - attribute \src "ls180.v:2322.12-2322.44" + attribute \src "ls180.v:2233.12-2233.44" wire width 8 \builder_csrbank6_cmd_response6_w - attribute \src "ls180.v:2321.6-2321.39" + attribute \src "ls180.v:2232.6-2232.39" wire \builder_csrbank6_cmd_response6_we - attribute \src "ls180.v:2316.12-2316.44" + attribute \src "ls180.v:2227.12-2227.44" wire width 8 \builder_csrbank6_cmd_response7_r - attribute \src "ls180.v:2315.6-2315.39" + attribute \src "ls180.v:2226.6-2226.39" wire \builder_csrbank6_cmd_response7_re - attribute \src "ls180.v:2318.12-2318.44" + attribute \src "ls180.v:2229.12-2229.44" wire width 8 \builder_csrbank6_cmd_response7_w - attribute \src "ls180.v:2317.6-2317.39" + attribute \src "ls180.v:2228.6-2228.39" wire \builder_csrbank6_cmd_response7_we - attribute \src "ls180.v:2312.12-2312.44" + attribute \src "ls180.v:2223.12-2223.44" wire width 8 \builder_csrbank6_cmd_response8_r - attribute \src "ls180.v:2311.6-2311.39" + attribute \src "ls180.v:2222.6-2222.39" wire \builder_csrbank6_cmd_response8_re - attribute \src "ls180.v:2314.12-2314.44" + attribute \src "ls180.v:2225.12-2225.44" wire width 8 \builder_csrbank6_cmd_response8_w - attribute \src "ls180.v:2313.6-2313.39" + attribute \src "ls180.v:2224.6-2224.39" wire \builder_csrbank6_cmd_response8_we - attribute \src "ls180.v:2308.12-2308.44" + attribute \src "ls180.v:2219.12-2219.44" wire width 8 \builder_csrbank6_cmd_response9_r - attribute \src "ls180.v:2307.6-2307.39" + attribute \src "ls180.v:2218.6-2218.39" wire \builder_csrbank6_cmd_response9_re - attribute \src "ls180.v:2310.12-2310.44" + attribute \src "ls180.v:2221.12-2221.44" wire width 8 \builder_csrbank6_cmd_response9_w - attribute \src "ls180.v:2309.6-2309.39" + attribute \src "ls180.v:2220.6-2220.39" wire \builder_csrbank6_cmd_response9_we - attribute \src "ls180.v:2352.12-2352.41" + attribute \src "ls180.v:2263.12-2263.41" wire width 4 \builder_csrbank6_data_event_r - attribute \src "ls180.v:2351.6-2351.36" + attribute \src "ls180.v:2262.6-2262.36" wire \builder_csrbank6_data_event_re - attribute \src "ls180.v:2354.12-2354.41" + attribute \src "ls180.v:2265.12-2265.41" wire width 4 \builder_csrbank6_data_event_w - attribute \src "ls180.v:2353.6-2353.36" + attribute \src "ls180.v:2264.6-2264.36" wire \builder_csrbank6_data_event_we - attribute \src "ls180.v:2379.6-2379.26" + attribute \src "ls180.v:2290.6-2290.26" wire \builder_csrbank6_sel - attribute \src "ls180.v:2413.12-2413.40" + attribute \src "ls180.v:2324.12-2324.40" wire width 8 \builder_csrbank7_dma_base0_r - attribute \src "ls180.v:2412.6-2412.35" + attribute \src "ls180.v:2323.6-2323.35" wire \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:2415.12-2415.40" + attribute \src "ls180.v:2326.12-2326.40" wire width 8 \builder_csrbank7_dma_base0_w - attribute \src "ls180.v:2414.6-2414.35" + attribute \src "ls180.v:2325.6-2325.35" wire \builder_csrbank7_dma_base0_we - attribute \src "ls180.v:2409.12-2409.40" + attribute \src "ls180.v:2320.12-2320.40" wire width 8 \builder_csrbank7_dma_base1_r - attribute \src "ls180.v:2408.6-2408.35" + attribute \src "ls180.v:2319.6-2319.35" wire \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:2411.12-2411.40" + attribute \src "ls180.v:2322.12-2322.40" wire width 8 \builder_csrbank7_dma_base1_w - attribute \src "ls180.v:2410.6-2410.35" + attribute \src "ls180.v:2321.6-2321.35" wire \builder_csrbank7_dma_base1_we - attribute \src "ls180.v:2405.12-2405.40" + attribute \src "ls180.v:2316.12-2316.40" wire width 8 \builder_csrbank7_dma_base2_r - attribute \src "ls180.v:2404.6-2404.35" + attribute \src "ls180.v:2315.6-2315.35" wire \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:2407.12-2407.40" + attribute \src "ls180.v:2318.12-2318.40" wire width 8 \builder_csrbank7_dma_base2_w - attribute \src "ls180.v:2406.6-2406.35" + attribute \src "ls180.v:2317.6-2317.35" wire \builder_csrbank7_dma_base2_we - attribute \src "ls180.v:2401.12-2401.40" + attribute \src "ls180.v:2312.12-2312.40" wire width 8 \builder_csrbank7_dma_base3_r - attribute \src "ls180.v:2400.6-2400.35" + attribute \src "ls180.v:2311.6-2311.35" wire \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:2403.12-2403.40" + attribute \src "ls180.v:2314.12-2314.40" wire width 8 \builder_csrbank7_dma_base3_w - attribute \src "ls180.v:2402.6-2402.35" + attribute \src "ls180.v:2313.6-2313.35" wire \builder_csrbank7_dma_base3_we - attribute \src "ls180.v:2397.12-2397.40" + attribute \src "ls180.v:2308.12-2308.40" wire width 8 \builder_csrbank7_dma_base4_r - attribute \src "ls180.v:2396.6-2396.35" + attribute \src "ls180.v:2307.6-2307.35" wire \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:2399.12-2399.40" + attribute \src "ls180.v:2310.12-2310.40" wire width 8 \builder_csrbank7_dma_base4_w - attribute \src "ls180.v:2398.6-2398.35" + attribute \src "ls180.v:2309.6-2309.35" wire \builder_csrbank7_dma_base4_we - attribute \src "ls180.v:2393.12-2393.40" + attribute \src "ls180.v:2304.12-2304.40" wire width 8 \builder_csrbank7_dma_base5_r - attribute \src "ls180.v:2392.6-2392.35" + attribute \src "ls180.v:2303.6-2303.35" wire \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:2395.12-2395.40" + attribute \src "ls180.v:2306.12-2306.40" wire width 8 \builder_csrbank7_dma_base5_w - attribute \src "ls180.v:2394.6-2394.35" + attribute \src "ls180.v:2305.6-2305.35" wire \builder_csrbank7_dma_base5_we - attribute \src "ls180.v:2389.12-2389.40" + attribute \src "ls180.v:2300.12-2300.40" wire width 8 \builder_csrbank7_dma_base6_r - attribute \src "ls180.v:2388.6-2388.35" + attribute \src "ls180.v:2299.6-2299.35" wire \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:2391.12-2391.40" + attribute \src "ls180.v:2302.12-2302.40" wire width 8 \builder_csrbank7_dma_base6_w - attribute \src "ls180.v:2390.6-2390.35" + attribute \src "ls180.v:2301.6-2301.35" wire \builder_csrbank7_dma_base6_we - attribute \src "ls180.v:2385.12-2385.40" + attribute \src "ls180.v:2296.12-2296.40" wire width 8 \builder_csrbank7_dma_base7_r - attribute \src "ls180.v:2384.6-2384.35" + attribute \src "ls180.v:2295.6-2295.35" wire \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:2387.12-2387.40" + attribute \src "ls180.v:2298.12-2298.40" wire width 8 \builder_csrbank7_dma_base7_w - attribute \src "ls180.v:2386.6-2386.35" + attribute \src "ls180.v:2297.6-2297.35" wire \builder_csrbank7_dma_base7_we - attribute \src "ls180.v:2437.6-2437.33" + attribute \src "ls180.v:2348.6-2348.33" wire \builder_csrbank7_dma_done_r - attribute \src "ls180.v:2436.6-2436.34" + attribute \src "ls180.v:2347.6-2347.34" wire \builder_csrbank7_dma_done_re - attribute \src "ls180.v:2439.6-2439.33" + attribute \src "ls180.v:2350.6-2350.33" wire \builder_csrbank7_dma_done_w - attribute \src "ls180.v:2438.6-2438.34" + attribute \src "ls180.v:2349.6-2349.34" wire \builder_csrbank7_dma_done_we - attribute \src "ls180.v:2433.6-2433.36" + attribute \src "ls180.v:2344.6-2344.36" wire \builder_csrbank7_dma_enable0_r - attribute \src "ls180.v:2432.6-2432.37" + attribute \src "ls180.v:2343.6-2343.37" wire \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:2435.6-2435.36" + attribute \src "ls180.v:2346.6-2346.36" wire \builder_csrbank7_dma_enable0_w - attribute \src "ls180.v:2434.6-2434.37" + attribute \src "ls180.v:2345.6-2345.37" wire \builder_csrbank7_dma_enable0_we - attribute \src "ls180.v:2429.12-2429.42" + attribute \src "ls180.v:2340.12-2340.42" wire width 8 \builder_csrbank7_dma_length0_r - attribute \src "ls180.v:2428.6-2428.37" + attribute \src "ls180.v:2339.6-2339.37" wire \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:2431.12-2431.42" + attribute \src "ls180.v:2342.12-2342.42" wire width 8 \builder_csrbank7_dma_length0_w - attribute \src "ls180.v:2430.6-2430.37" + attribute \src "ls180.v:2341.6-2341.37" wire \builder_csrbank7_dma_length0_we - attribute \src "ls180.v:2425.12-2425.42" + attribute \src "ls180.v:2336.12-2336.42" wire width 8 \builder_csrbank7_dma_length1_r - attribute \src "ls180.v:2424.6-2424.37" + attribute \src "ls180.v:2335.6-2335.37" wire \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:2427.12-2427.42" + attribute \src "ls180.v:2338.12-2338.42" wire width 8 \builder_csrbank7_dma_length1_w - attribute \src "ls180.v:2426.6-2426.37" + attribute \src "ls180.v:2337.6-2337.37" wire \builder_csrbank7_dma_length1_we - attribute \src "ls180.v:2421.12-2421.42" + attribute \src "ls180.v:2332.12-2332.42" wire width 8 \builder_csrbank7_dma_length2_r - attribute \src "ls180.v:2420.6-2420.37" + attribute \src "ls180.v:2331.6-2331.37" wire \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:2423.12-2423.42" + attribute \src "ls180.v:2334.12-2334.42" wire width 8 \builder_csrbank7_dma_length2_w - attribute \src "ls180.v:2422.6-2422.37" + attribute \src "ls180.v:2333.6-2333.37" wire \builder_csrbank7_dma_length2_we - attribute \src "ls180.v:2417.12-2417.42" + attribute \src "ls180.v:2328.12-2328.42" wire width 8 \builder_csrbank7_dma_length3_r - attribute \src "ls180.v:2416.6-2416.37" + attribute \src "ls180.v:2327.6-2327.37" wire \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:2419.12-2419.42" + attribute \src "ls180.v:2330.12-2330.42" wire width 8 \builder_csrbank7_dma_length3_w - attribute \src "ls180.v:2418.6-2418.37" + attribute \src "ls180.v:2329.6-2329.37" wire \builder_csrbank7_dma_length3_we - attribute \src "ls180.v:2441.6-2441.34" + attribute \src "ls180.v:2352.6-2352.34" wire \builder_csrbank7_dma_loop0_r - attribute \src "ls180.v:2440.6-2440.35" + attribute \src "ls180.v:2351.6-2351.35" wire \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:2443.6-2443.34" + attribute \src "ls180.v:2354.6-2354.34" wire \builder_csrbank7_dma_loop0_w - attribute \src "ls180.v:2442.6-2442.35" + attribute \src "ls180.v:2353.6-2353.35" wire \builder_csrbank7_dma_loop0_we - attribute \src "ls180.v:2457.12-2457.42" + attribute \src "ls180.v:2368.12-2368.42" wire width 8 \builder_csrbank7_dma_offset0_r - attribute \src "ls180.v:2456.6-2456.37" + attribute \src "ls180.v:2367.6-2367.37" wire \builder_csrbank7_dma_offset0_re - attribute \src "ls180.v:2459.12-2459.42" + attribute \src "ls180.v:2370.12-2370.42" wire width 8 \builder_csrbank7_dma_offset0_w - attribute \src "ls180.v:2458.6-2458.37" + attribute \src "ls180.v:2369.6-2369.37" wire \builder_csrbank7_dma_offset0_we - attribute \src "ls180.v:2453.12-2453.42" + attribute \src "ls180.v:2364.12-2364.42" wire width 8 \builder_csrbank7_dma_offset1_r - attribute \src "ls180.v:2452.6-2452.37" + attribute \src "ls180.v:2363.6-2363.37" wire \builder_csrbank7_dma_offset1_re - attribute \src "ls180.v:2455.12-2455.42" + attribute \src "ls180.v:2366.12-2366.42" wire width 8 \builder_csrbank7_dma_offset1_w - attribute \src "ls180.v:2454.6-2454.37" + attribute \src "ls180.v:2365.6-2365.37" wire \builder_csrbank7_dma_offset1_we - attribute \src "ls180.v:2449.12-2449.42" + attribute \src "ls180.v:2360.12-2360.42" wire width 8 \builder_csrbank7_dma_offset2_r - attribute \src "ls180.v:2448.6-2448.37" + attribute \src "ls180.v:2359.6-2359.37" wire \builder_csrbank7_dma_offset2_re - attribute \src "ls180.v:2451.12-2451.42" + attribute \src "ls180.v:2362.12-2362.42" wire width 8 \builder_csrbank7_dma_offset2_w - attribute \src "ls180.v:2450.6-2450.37" + attribute \src "ls180.v:2361.6-2361.37" wire \builder_csrbank7_dma_offset2_we - attribute \src "ls180.v:2445.12-2445.42" + attribute \src "ls180.v:2356.12-2356.42" wire width 8 \builder_csrbank7_dma_offset3_r - attribute \src "ls180.v:2444.6-2444.37" + attribute \src "ls180.v:2355.6-2355.37" wire \builder_csrbank7_dma_offset3_re - attribute \src "ls180.v:2447.12-2447.42" + attribute \src "ls180.v:2358.12-2358.42" wire width 8 \builder_csrbank7_dma_offset3_w - attribute \src "ls180.v:2446.6-2446.37" + attribute \src "ls180.v:2357.6-2357.37" wire \builder_csrbank7_dma_offset3_we - attribute \src "ls180.v:2460.6-2460.26" + attribute \src "ls180.v:2371.6-2371.26" wire \builder_csrbank7_sel - attribute \src "ls180.v:2466.6-2466.36" + attribute \src "ls180.v:2377.6-2377.36" wire \builder_csrbank8_card_detect_r - attribute \src "ls180.v:2465.6-2465.37" + attribute \src "ls180.v:2376.6-2376.37" wire \builder_csrbank8_card_detect_re - attribute \src "ls180.v:2468.6-2468.36" + attribute \src "ls180.v:2379.6-2379.36" wire \builder_csrbank8_card_detect_w - attribute \src "ls180.v:2467.6-2467.37" + attribute \src "ls180.v:2378.6-2378.37" wire \builder_csrbank8_card_detect_we - attribute \src "ls180.v:2474.12-2474.47" + attribute \src "ls180.v:2385.12-2385.47" wire width 8 \builder_csrbank8_clocker_divider0_r - attribute \src "ls180.v:2473.6-2473.42" + attribute \src "ls180.v:2384.6-2384.42" wire \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:2476.12-2476.47" + attribute \src "ls180.v:2387.12-2387.47" wire width 8 \builder_csrbank8_clocker_divider0_w - attribute \src "ls180.v:2475.6-2475.42" + attribute \src "ls180.v:2386.6-2386.42" wire \builder_csrbank8_clocker_divider0_we - attribute \src "ls180.v:2470.6-2470.41" + attribute \src "ls180.v:2381.6-2381.41" wire \builder_csrbank8_clocker_divider1_r - attribute \src "ls180.v:2469.6-2469.42" + attribute \src "ls180.v:2380.6-2380.42" wire \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:2472.6-2472.41" + attribute \src "ls180.v:2383.6-2383.41" wire \builder_csrbank8_clocker_divider1_w - attribute \src "ls180.v:2471.6-2471.42" + attribute \src "ls180.v:2382.6-2382.42" wire \builder_csrbank8_clocker_divider1_we - attribute \src "ls180.v:2477.6-2477.26" + attribute \src "ls180.v:2388.6-2388.26" wire \builder_csrbank8_sel - attribute \src "ls180.v:2483.12-2483.44" + attribute \src "ls180.v:2394.12-2394.44" wire width 4 \builder_csrbank9_dfii_control0_r - attribute \src "ls180.v:2482.6-2482.39" + attribute \src "ls180.v:2393.6-2393.39" wire \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:2485.12-2485.44" + attribute \src "ls180.v:2396.12-2396.44" wire width 4 \builder_csrbank9_dfii_control0_w - attribute \src "ls180.v:2484.6-2484.39" + attribute \src "ls180.v:2395.6-2395.39" wire \builder_csrbank9_dfii_control0_we - attribute \src "ls180.v:2495.12-2495.48" + attribute \src "ls180.v:2406.12-2406.48" wire width 8 \builder_csrbank9_dfii_pi0_address0_r - attribute \src "ls180.v:2494.6-2494.43" + attribute \src "ls180.v:2405.6-2405.43" wire \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:2497.12-2497.48" + attribute \src "ls180.v:2408.12-2408.48" wire width 8 \builder_csrbank9_dfii_pi0_address0_w - attribute \src "ls180.v:2496.6-2496.43" + attribute \src "ls180.v:2407.6-2407.43" wire \builder_csrbank9_dfii_pi0_address0_we - attribute \src "ls180.v:2491.12-2491.48" + attribute \src "ls180.v:2402.12-2402.48" wire width 5 \builder_csrbank9_dfii_pi0_address1_r - attribute \src "ls180.v:2490.6-2490.43" + attribute \src "ls180.v:2401.6-2401.43" wire \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:2493.12-2493.48" + attribute \src "ls180.v:2404.12-2404.48" wire width 5 \builder_csrbank9_dfii_pi0_address1_w - attribute \src "ls180.v:2492.6-2492.43" + attribute \src "ls180.v:2403.6-2403.43" wire \builder_csrbank9_dfii_pi0_address1_we - attribute \src "ls180.v:2499.12-2499.49" + attribute \src "ls180.v:2410.12-2410.49" wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r - attribute \src "ls180.v:2498.6-2498.44" + attribute \src "ls180.v:2409.6-2409.44" wire \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:2501.12-2501.49" + attribute \src "ls180.v:2412.12-2412.49" wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w - attribute \src "ls180.v:2500.6-2500.44" + attribute \src "ls180.v:2411.6-2411.44" wire \builder_csrbank9_dfii_pi0_baddress0_we - attribute \src "ls180.v:2487.12-2487.48" + attribute \src "ls180.v:2398.12-2398.48" wire width 6 \builder_csrbank9_dfii_pi0_command0_r - attribute \src "ls180.v:2486.6-2486.43" + attribute \src "ls180.v:2397.6-2397.43" wire \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:2489.12-2489.48" + attribute \src "ls180.v:2400.12-2400.48" wire width 6 \builder_csrbank9_dfii_pi0_command0_w - attribute \src "ls180.v:2488.6-2488.43" + attribute \src "ls180.v:2399.6-2399.43" wire \builder_csrbank9_dfii_pi0_command0_we - attribute \src "ls180.v:2515.12-2515.47" + attribute \src "ls180.v:2426.12-2426.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r - attribute \src "ls180.v:2514.6-2514.42" + attribute \src "ls180.v:2425.6-2425.42" wire \builder_csrbank9_dfii_pi0_rddata0_re - attribute \src "ls180.v:2517.12-2517.47" + attribute \src "ls180.v:2428.12-2428.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w - attribute \src "ls180.v:2516.6-2516.42" + attribute \src "ls180.v:2427.6-2427.42" wire \builder_csrbank9_dfii_pi0_rddata0_we - attribute \src "ls180.v:2511.12-2511.47" + attribute \src "ls180.v:2422.12-2422.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r - attribute \src "ls180.v:2510.6-2510.42" + attribute \src "ls180.v:2421.6-2421.42" wire \builder_csrbank9_dfii_pi0_rddata1_re - attribute \src "ls180.v:2513.12-2513.47" + attribute \src "ls180.v:2424.12-2424.47" wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w - attribute \src "ls180.v:2512.6-2512.42" + attribute \src "ls180.v:2423.6-2423.42" wire \builder_csrbank9_dfii_pi0_rddata1_we - attribute \src "ls180.v:2507.12-2507.47" + attribute \src "ls180.v:2418.12-2418.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r - attribute \src "ls180.v:2506.6-2506.42" + attribute \src "ls180.v:2417.6-2417.42" wire \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:2509.12-2509.47" + attribute \src "ls180.v:2420.12-2420.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w - attribute \src "ls180.v:2508.6-2508.42" + attribute \src "ls180.v:2419.6-2419.42" wire \builder_csrbank9_dfii_pi0_wrdata0_we - attribute \src "ls180.v:2503.12-2503.47" + attribute \src "ls180.v:2414.12-2414.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r - attribute \src "ls180.v:2502.6-2502.42" + attribute \src "ls180.v:2413.6-2413.42" wire \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:2505.12-2505.47" + attribute \src "ls180.v:2416.12-2416.47" wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w - attribute \src "ls180.v:2504.6-2504.42" + attribute \src "ls180.v:2415.6-2415.42" wire \builder_csrbank9_dfii_pi0_wrdata1_we - attribute \src "ls180.v:2518.6-2518.26" + attribute \src "ls180.v:2429.6-2429.26" wire \builder_csrbank9_sel - attribute \src "ls180.v:2015.6-2015.18" + attribute \src "ls180.v:1926.6-1926.18" wire \builder_done - attribute \src "ls180.v:2013.5-2013.18" + attribute \src "ls180.v:1924.5-1924.18" wire \builder_error - attribute \src "ls180.v:2010.11-2010.24" + attribute \src "ls180.v:1921.11-1921.24" wire width 3 \builder_grant - attribute \src "ls180.v:2017.13-2017.44" + attribute \src "ls180.v:1928.13-1928.44" wire width 14 \builder_interface0_bank_bus_adr - attribute \src "ls180.v:2020.11-2020.44" + attribute \src "ls180.v:1931.11-1931.44" wire width 8 \builder_interface0_bank_bus_dat_r - attribute \src "ls180.v:2019.12-2019.45" + attribute \src "ls180.v:1930.12-1930.45" wire width 8 \builder_interface0_bank_bus_dat_w - attribute \src "ls180.v:2018.6-2018.36" + attribute \src "ls180.v:1929.6-1929.36" wire \builder_interface0_bank_bus_we - attribute \src "ls180.v:2519.13-2519.45" + attribute \src "ls180.v:2430.13-2430.45" wire width 14 \builder_interface10_bank_bus_adr - attribute \src "ls180.v:2522.11-2522.45" + attribute \src "ls180.v:2433.11-2433.45" wire width 8 \builder_interface10_bank_bus_dat_r - attribute \src "ls180.v:2521.12-2521.46" + attribute \src "ls180.v:2432.12-2432.46" wire width 8 \builder_interface10_bank_bus_dat_w - attribute \src "ls180.v:2520.6-2520.37" + attribute \src "ls180.v:2431.6-2431.37" wire \builder_interface10_bank_bus_we - attribute \src "ls180.v:2552.13-2552.45" + attribute \src "ls180.v:2463.13-2463.45" wire width 14 \builder_interface11_bank_bus_adr - attribute \src "ls180.v:2555.11-2555.45" + attribute \src "ls180.v:2466.11-2466.45" wire width 8 \builder_interface11_bank_bus_dat_r - attribute \src "ls180.v:2554.12-2554.46" + attribute \src "ls180.v:2465.12-2465.46" wire width 8 \builder_interface11_bank_bus_dat_w - attribute \src "ls180.v:2553.6-2553.37" + attribute \src "ls180.v:2464.6-2464.37" wire \builder_interface11_bank_bus_we - attribute \src "ls180.v:2593.13-2593.45" + attribute \src "ls180.v:2504.13-2504.45" wire width 14 \builder_interface12_bank_bus_adr - attribute \src "ls180.v:2596.11-2596.45" + attribute \src "ls180.v:2507.11-2507.45" wire width 8 \builder_interface12_bank_bus_dat_r - attribute \src "ls180.v:2595.12-2595.46" + attribute \src "ls180.v:2506.12-2506.46" wire width 8 \builder_interface12_bank_bus_dat_w - attribute \src "ls180.v:2594.6-2594.37" + attribute \src "ls180.v:2505.6-2505.37" wire \builder_interface12_bank_bus_we - attribute \src "ls180.v:2658.13-2658.45" + attribute \src "ls180.v:2569.13-2569.45" wire width 14 \builder_interface13_bank_bus_adr - attribute \src "ls180.v:2661.11-2661.45" + attribute \src "ls180.v:2572.11-2572.45" wire width 8 \builder_interface13_bank_bus_dat_r - attribute \src "ls180.v:2660.12-2660.46" + attribute \src "ls180.v:2571.12-2571.46" wire width 8 \builder_interface13_bank_bus_dat_w - attribute \src "ls180.v:2659.6-2659.37" + attribute \src "ls180.v:2570.6-2570.37" wire \builder_interface13_bank_bus_we - attribute \src "ls180.v:2683.13-2683.45" + attribute \src "ls180.v:2594.13-2594.45" wire width 14 \builder_interface14_bank_bus_adr - attribute \src "ls180.v:2686.11-2686.45" + attribute \src "ls180.v:2597.11-2597.45" wire width 8 \builder_interface14_bank_bus_dat_r - attribute \src "ls180.v:2685.12-2685.46" + attribute \src "ls180.v:2596.12-2596.46" wire width 8 \builder_interface14_bank_bus_dat_w - attribute \src "ls180.v:2684.6-2684.37" + attribute \src "ls180.v:2595.6-2595.37" wire \builder_interface14_bank_bus_we - attribute \src "ls180.v:2058.13-2058.44" + attribute \src "ls180.v:1969.13-1969.44" wire width 14 \builder_interface1_bank_bus_adr - attribute \src "ls180.v:2061.11-2061.44" + attribute \src "ls180.v:1972.11-1972.44" wire width 8 \builder_interface1_bank_bus_dat_r - attribute \src "ls180.v:2060.12-2060.45" + attribute \src "ls180.v:1971.12-1971.45" wire width 8 \builder_interface1_bank_bus_dat_w - attribute \src "ls180.v:2059.6-2059.36" + attribute \src "ls180.v:1970.6-1970.36" wire \builder_interface1_bank_bus_we - attribute \src "ls180.v:2087.13-2087.44" + attribute \src "ls180.v:1998.13-1998.44" wire width 14 \builder_interface2_bank_bus_adr - attribute \src "ls180.v:2090.11-2090.44" + attribute \src "ls180.v:2001.11-2001.44" wire width 8 \builder_interface2_bank_bus_dat_r - attribute \src "ls180.v:2089.12-2089.45" + attribute \src "ls180.v:2000.12-2000.45" wire width 8 \builder_interface2_bank_bus_dat_w - attribute \src "ls180.v:2088.6-2088.36" + attribute \src "ls180.v:1999.6-1999.36" wire \builder_interface2_bank_bus_we - attribute \src "ls180.v:2100.13-2100.44" + attribute \src "ls180.v:2011.13-2011.44" wire width 14 \builder_interface3_bank_bus_adr - attribute \src "ls180.v:2103.11-2103.44" + attribute \src "ls180.v:2014.11-2014.44" wire width 8 \builder_interface3_bank_bus_dat_r - attribute \src "ls180.v:2102.12-2102.45" + attribute \src "ls180.v:2013.12-2013.45" wire width 8 \builder_interface3_bank_bus_dat_w - attribute \src "ls180.v:2101.6-2101.36" + attribute \src "ls180.v:2012.6-2012.36" wire \builder_interface3_bank_bus_we - attribute \src "ls180.v:2141.13-2141.44" + attribute \src "ls180.v:2052.13-2052.44" wire width 14 \builder_interface4_bank_bus_adr - attribute \src "ls180.v:2144.11-2144.44" + attribute \src "ls180.v:2055.11-2055.44" wire width 8 \builder_interface4_bank_bus_dat_r - attribute \src "ls180.v:2143.12-2143.45" + attribute \src "ls180.v:2054.12-2054.45" wire width 8 \builder_interface4_bank_bus_dat_w - attribute \src "ls180.v:2142.6-2142.36" + attribute \src "ls180.v:2053.6-2053.36" wire \builder_interface4_bank_bus_we - attribute \src "ls180.v:2182.13-2182.44" + attribute \src "ls180.v:2093.13-2093.44" wire width 14 \builder_interface5_bank_bus_adr - attribute \src "ls180.v:2185.11-2185.44" + attribute \src "ls180.v:2096.11-2096.44" wire width 8 \builder_interface5_bank_bus_dat_r - attribute \src "ls180.v:2184.12-2184.45" + attribute \src "ls180.v:2095.12-2095.45" wire width 8 \builder_interface5_bank_bus_dat_w - attribute \src "ls180.v:2183.6-2183.36" + attribute \src "ls180.v:2094.6-2094.36" wire \builder_interface5_bank_bus_we - attribute \src "ls180.v:2247.13-2247.44" + attribute \src "ls180.v:2158.13-2158.44" wire width 14 \builder_interface6_bank_bus_adr - attribute \src "ls180.v:2250.11-2250.44" + attribute \src "ls180.v:2161.11-2161.44" wire width 8 \builder_interface6_bank_bus_dat_r - attribute \src "ls180.v:2249.12-2249.45" + attribute \src "ls180.v:2160.12-2160.45" wire width 8 \builder_interface6_bank_bus_dat_w - attribute \src "ls180.v:2248.6-2248.36" + attribute \src "ls180.v:2159.6-2159.36" wire \builder_interface6_bank_bus_we - attribute \src "ls180.v:2380.13-2380.44" + attribute \src "ls180.v:2291.13-2291.44" wire width 14 \builder_interface7_bank_bus_adr - attribute \src "ls180.v:2383.11-2383.44" + attribute \src "ls180.v:2294.11-2294.44" wire width 8 \builder_interface7_bank_bus_dat_r - attribute \src "ls180.v:2382.12-2382.45" + attribute \src "ls180.v:2293.12-2293.45" wire width 8 \builder_interface7_bank_bus_dat_w - attribute \src "ls180.v:2381.6-2381.36" + attribute \src "ls180.v:2292.6-2292.36" wire \builder_interface7_bank_bus_we - attribute \src "ls180.v:2461.13-2461.44" + attribute \src "ls180.v:2372.13-2372.44" wire width 14 \builder_interface8_bank_bus_adr - attribute \src "ls180.v:2464.11-2464.44" + attribute \src "ls180.v:2375.11-2375.44" wire width 8 \builder_interface8_bank_bus_dat_r - attribute \src "ls180.v:2463.12-2463.45" + attribute \src "ls180.v:2374.12-2374.45" wire width 8 \builder_interface8_bank_bus_dat_w - attribute \src "ls180.v:2462.6-2462.36" + attribute \src "ls180.v:2373.6-2373.36" wire \builder_interface8_bank_bus_we - attribute \src "ls180.v:2478.13-2478.44" + attribute \src "ls180.v:2389.13-2389.44" wire width 14 \builder_interface9_bank_bus_adr - attribute \src "ls180.v:2481.11-2481.44" + attribute \src "ls180.v:2392.11-2392.44" wire width 8 \builder_interface9_bank_bus_dat_r - attribute \src "ls180.v:2480.12-2480.45" + attribute \src "ls180.v:2391.12-2391.45" wire width 8 \builder_interface9_bank_bus_dat_w - attribute \src "ls180.v:2479.6-2479.36" + attribute \src "ls180.v:2390.6-2390.36" wire \builder_interface9_bank_bus_we - attribute \src "ls180.v:1975.12-1975.35" + attribute \src "ls180.v:1886.12-1886.35" wire width 14 \builder_libresocsim_adr - attribute \src "ls180.v:2712.12-2712.47" + attribute \src "ls180.v:2623.12-2623.47" wire width 14 \builder_libresocsim_adr_next_value1 - attribute \src "ls180.v:2713.5-2713.43" + attribute \src "ls180.v:2624.5-2624.43" wire \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:1993.5-1993.48" + attribute \src "ls180.v:1904.5-1904.48" wire \builder_libresocsim_converted_interface_ack - attribute \src "ls180.v:1987.13-1987.56" + attribute \src "ls180.v:1898.13-1898.56" wire width 30 \builder_libresocsim_converted_interface_adr - attribute \src "ls180.v:1996.12-1996.55" + attribute \src "ls180.v:1907.12-1907.55" wire width 2 \builder_libresocsim_converted_interface_bte - attribute \src "ls180.v:1995.12-1995.55" + attribute \src "ls180.v:1906.12-1906.55" wire width 3 \builder_libresocsim_converted_interface_cti - attribute \src "ls180.v:1991.6-1991.49" + attribute \src "ls180.v:1902.6-1902.49" wire \builder_libresocsim_converted_interface_cyc - attribute \src "ls180.v:1989.12-1989.57" + attribute \src "ls180.v:1900.12-1900.57" wire width 64 \builder_libresocsim_converted_interface_dat_r - attribute \src "ls180.v:1988.13-1988.58" + attribute \src "ls180.v:1899.13-1899.58" wire width 64 \builder_libresocsim_converted_interface_dat_w - attribute \src "ls180.v:1997.5-1997.48" + attribute \src "ls180.v:1908.5-1908.48" wire \builder_libresocsim_converted_interface_err - attribute \src "ls180.v:1990.12-1990.55" + attribute \src "ls180.v:1901.12-1901.55" wire width 8 \builder_libresocsim_converted_interface_sel - attribute \src "ls180.v:1992.6-1992.49" + attribute \src "ls180.v:1903.6-1903.49" wire \builder_libresocsim_converted_interface_stb - attribute \src "ls180.v:1994.6-1994.48" + attribute \src "ls180.v:1905.6-1905.48" wire \builder_libresocsim_converted_interface_we - attribute \src "ls180.v:1978.12-1978.37" + attribute \src "ls180.v:1889.12-1889.37" wire width 8 \builder_libresocsim_dat_r - attribute \src "ls180.v:1977.11-1977.36" + attribute \src "ls180.v:1888.11-1888.36" wire width 8 \builder_libresocsim_dat_w - attribute \src "ls180.v:2710.11-2710.48" + attribute \src "ls180.v:2621.11-2621.48" wire width 8 \builder_libresocsim_dat_w_next_value0 - attribute \src "ls180.v:2711.5-2711.45" + attribute \src "ls180.v:2622.5-2622.45" wire \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:1976.5-1976.27" + attribute \src "ls180.v:1887.5-1887.27" wire \builder_libresocsim_we - attribute \src "ls180.v:2714.5-2714.39" + attribute \src "ls180.v:2625.5-2625.39" wire \builder_libresocsim_we_next_value2 - attribute \src "ls180.v:2715.5-2715.42" + attribute \src "ls180.v:2626.5-2626.42" wire \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:1985.5-1985.37" + attribute \src "ls180.v:1896.5-1896.37" wire \builder_libresocsim_wishbone_ack - attribute \src "ls180.v:1979.12-1979.44" + attribute \src "ls180.v:1890.12-1890.44" wire width 30 \builder_libresocsim_wishbone_adr - attribute \src "ls180.v:1983.5-1983.37" + attribute \src "ls180.v:1894.5-1894.37" wire \builder_libresocsim_wishbone_cyc - attribute \src "ls180.v:1981.12-1981.46" + attribute \src "ls180.v:1892.12-1892.46" wire width 32 \builder_libresocsim_wishbone_dat_r - attribute \src "ls180.v:1980.12-1980.46" + attribute \src "ls180.v:1891.12-1891.46" wire width 32 \builder_libresocsim_wishbone_dat_w - attribute \src "ls180.v:1982.11-1982.43" + attribute \src "ls180.v:1893.11-1893.43" wire width 4 \builder_libresocsim_wishbone_sel - attribute \src "ls180.v:1984.5-1984.37" + attribute \src "ls180.v:1895.5-1895.37" wire \builder_libresocsim_wishbone_stb - attribute \src "ls180.v:1986.5-1986.36" + attribute \src "ls180.v:1897.5-1897.36" wire \builder_libresocsim_wishbone_we - attribute \src "ls180.v:1878.5-1878.20" + attribute \src "ls180.v:1789.5-1789.20" wire \builder_locked0 - attribute \src "ls180.v:1879.5-1879.20" + attribute \src "ls180.v:1790.5-1790.20" wire \builder_locked1 - attribute \src "ls180.v:1880.5-1880.20" + attribute \src "ls180.v:1791.5-1791.20" wire \builder_locked2 - attribute \src "ls180.v:1881.5-1881.20" + attribute \src "ls180.v:1792.5-1792.20" wire \builder_locked3 - attribute \src "ls180.v:1865.11-1865.41" + attribute \src "ls180.v:1776.11-1776.41" wire width 3 \builder_multiplexer_next_state - attribute \src "ls180.v:1864.11-1864.36" + attribute \src "ls180.v:1775.11-1775.36" wire width 3 \builder_multiplexer_state attribute \no_retiming "true" - attribute \src "ls180.v:2819.32-2819.59" + attribute \src "ls180.v:2730.32-2730.59" wire \builder_multiregimpl0_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2820.32-2820.59" + attribute \src "ls180.v:2731.32-2731.59" wire \builder_multiregimpl0_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2839.32-2839.60" + attribute \src "ls180.v:2750.32-2750.60" wire \builder_multiregimpl10_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2840.32-2840.60" + attribute \src "ls180.v:2751.32-2751.60" wire \builder_multiregimpl10_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2841.32-2841.60" + attribute \src "ls180.v:2752.32-2752.60" wire \builder_multiregimpl11_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2842.32-2842.60" + attribute \src "ls180.v:2753.32-2753.60" wire \builder_multiregimpl11_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2843.32-2843.60" + attribute \src "ls180.v:2754.32-2754.60" wire \builder_multiregimpl12_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2844.32-2844.60" + attribute \src "ls180.v:2755.32-2755.60" wire \builder_multiregimpl12_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2845.32-2845.60" + attribute \src "ls180.v:2756.32-2756.60" wire \builder_multiregimpl13_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2846.32-2846.60" + attribute \src "ls180.v:2757.32-2757.60" wire \builder_multiregimpl13_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2847.32-2847.60" + attribute \src "ls180.v:2758.32-2758.60" wire \builder_multiregimpl14_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2848.32-2848.60" + attribute \src "ls180.v:2759.32-2759.60" wire \builder_multiregimpl14_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2849.32-2849.60" + attribute \src "ls180.v:2760.32-2760.60" wire \builder_multiregimpl15_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2850.32-2850.60" + attribute \src "ls180.v:2761.32-2761.60" wire \builder_multiregimpl15_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2851.32-2851.60" + attribute \src "ls180.v:2762.32-2762.60" wire \builder_multiregimpl16_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2852.32-2852.60" + attribute \src "ls180.v:2763.32-2763.60" wire \builder_multiregimpl16_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2821.32-2821.59" + attribute \src "ls180.v:2732.32-2732.59" wire \builder_multiregimpl1_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2822.32-2822.59" + attribute \src "ls180.v:2733.32-2733.59" wire \builder_multiregimpl1_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2823.32-2823.59" + attribute \src "ls180.v:2734.32-2734.59" wire \builder_multiregimpl2_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2824.32-2824.59" + attribute \src "ls180.v:2735.32-2735.59" wire \builder_multiregimpl2_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2825.32-2825.59" + attribute \src "ls180.v:2736.32-2736.59" wire \builder_multiregimpl3_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2826.32-2826.59" + attribute \src "ls180.v:2737.32-2737.59" wire \builder_multiregimpl3_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2827.32-2827.59" + attribute \src "ls180.v:2738.32-2738.59" wire \builder_multiregimpl4_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2828.32-2828.59" + attribute \src "ls180.v:2739.32-2739.59" wire \builder_multiregimpl4_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2829.32-2829.59" + attribute \src "ls180.v:2740.32-2740.59" wire \builder_multiregimpl5_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2830.32-2830.59" + attribute \src "ls180.v:2741.32-2741.59" wire \builder_multiregimpl5_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2831.32-2831.59" + attribute \src "ls180.v:2742.32-2742.59" wire \builder_multiregimpl6_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2832.32-2832.59" + attribute \src "ls180.v:2743.32-2743.59" wire \builder_multiregimpl6_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2833.32-2833.59" + attribute \src "ls180.v:2744.32-2744.59" wire \builder_multiregimpl7_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2834.32-2834.59" + attribute \src "ls180.v:2745.32-2745.59" wire \builder_multiregimpl7_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2835.32-2835.59" + attribute \src "ls180.v:2746.32-2746.59" wire \builder_multiregimpl8_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2836.32-2836.59" + attribute \src "ls180.v:2747.32-2747.59" wire \builder_multiregimpl8_regs1 attribute \no_retiming "true" - attribute \src "ls180.v:2837.32-2837.59" + attribute \src "ls180.v:2748.32-2748.59" wire \builder_multiregimpl9_regs0 attribute \no_retiming "true" - attribute \src "ls180.v:2838.32-2838.59" + attribute \src "ls180.v:2749.32-2749.59" wire \builder_multiregimpl9_regs1 - attribute \src "ls180.v:1883.5-1883.36" + attribute \src "ls180.v:1794.5-1794.36" wire \builder_new_master_rdata_valid0 - attribute \src "ls180.v:1884.5-1884.36" + attribute \src "ls180.v:1795.5-1795.36" wire \builder_new_master_rdata_valid1 - attribute \src "ls180.v:1885.5-1885.36" + attribute \src "ls180.v:1796.5-1796.36" wire \builder_new_master_rdata_valid2 - attribute \src "ls180.v:1886.5-1886.36" + attribute \src "ls180.v:1797.5-1797.36" wire \builder_new_master_rdata_valid3 - attribute \src "ls180.v:1882.5-1882.35" + attribute \src "ls180.v:1793.5-1793.35" wire \builder_new_master_wdata_ready - attribute \src "ls180.v:2709.11-2709.29" + attribute \src "ls180.v:2620.11-2620.29" wire width 2 \builder_next_state - attribute \src "ls180.v:1855.11-1855.39" + attribute \src "ls180.v:1766.11-1766.39" wire width 2 \builder_refresher_next_state - attribute \src "ls180.v:1854.11-1854.34" + attribute \src "ls180.v:1765.11-1765.34" wire width 2 \builder_refresher_state - attribute \src "ls180.v:2009.12-2009.27" + attribute \src "ls180.v:1920.12-1920.27" wire width 5 \builder_request - attribute \src "ls180.v:1868.6-1868.28" + attribute \src "ls180.v:1779.6-1779.28" wire \builder_roundrobin0_ce - attribute \src "ls180.v:1867.6-1867.31" + attribute \src "ls180.v:1778.6-1778.31" wire \builder_roundrobin0_grant - attribute \src "ls180.v:1866.6-1866.33" + attribute \src "ls180.v:1777.6-1777.33" wire \builder_roundrobin0_request - attribute \src "ls180.v:1871.6-1871.28" + attribute \src "ls180.v:1782.6-1782.28" wire \builder_roundrobin1_ce - attribute \src "ls180.v:1870.6-1870.31" + attribute \src "ls180.v:1781.6-1781.31" wire \builder_roundrobin1_grant - attribute \src "ls180.v:1869.6-1869.33" + attribute \src "ls180.v:1780.6-1780.33" wire \builder_roundrobin1_request - attribute \src "ls180.v:1874.6-1874.28" + attribute \src "ls180.v:1785.6-1785.28" wire \builder_roundrobin2_ce - attribute \src "ls180.v:1873.6-1873.31" + attribute \src "ls180.v:1784.6-1784.31" wire \builder_roundrobin2_grant - attribute \src "ls180.v:1872.6-1872.33" + attribute \src "ls180.v:1783.6-1783.33" wire \builder_roundrobin2_request - attribute \src "ls180.v:1877.6-1877.28" + attribute \src "ls180.v:1788.6-1788.28" wire \builder_roundrobin3_ce - attribute \src "ls180.v:1876.6-1876.31" + attribute \src "ls180.v:1787.6-1787.31" wire \builder_roundrobin3_grant - attribute \src "ls180.v:1875.6-1875.33" + attribute \src "ls180.v:1786.6-1786.33" wire \builder_roundrobin3_request - attribute \src "ls180.v:1964.11-1964.44" + attribute \src "ls180.v:1875.11-1875.44" wire width 2 \builder_sdblock2memdma_next_state - attribute \src "ls180.v:1963.11-1963.39" + attribute \src "ls180.v:1874.11-1874.39" wire width 2 \builder_sdblock2memdma_state - attribute \src "ls180.v:1932.5-1932.50" + attribute \src "ls180.v:1843.5-1843.50" wire \builder_sdcore_crcupstreaminserter_next_state - attribute \src "ls180.v:1931.5-1931.45" + attribute \src "ls180.v:1842.5-1842.45" wire \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:1944.11-1944.40" + attribute \src "ls180.v:1855.11-1855.40" wire width 3 \builder_sdcore_fsm_next_state - attribute \src "ls180.v:1943.11-1943.35" + attribute \src "ls180.v:1854.11-1854.35" wire width 3 \builder_sdcore_fsm_state - attribute \src "ls180.v:1968.5-1968.42" + attribute \src "ls180.v:1879.5-1879.42" wire \builder_sdmem2blockdma_fsm_next_state - attribute \src "ls180.v:1967.5-1967.37" + attribute \src "ls180.v:1878.5-1878.37" wire \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:1972.11-1972.58" + attribute \src "ls180.v:1883.11-1883.58" wire width 2 \builder_sdmem2blockdma_resetinserter_next_state - attribute \src "ls180.v:1971.11-1971.53" + attribute \src "ls180.v:1882.11-1882.53" wire width 2 \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:1920.11-1920.39" + attribute \src "ls180.v:1831.11-1831.39" wire width 3 \builder_sdphy_fsm_next_state - attribute \src "ls180.v:1919.11-1919.34" + attribute \src "ls180.v:1830.11-1830.34" wire width 3 \builder_sdphy_fsm_state - attribute \src "ls180.v:1908.11-1908.45" + attribute \src "ls180.v:1819.11-1819.45" wire width 3 \builder_sdphy_sdphycmdr_next_state - attribute \src "ls180.v:1907.11-1907.40" + attribute \src "ls180.v:1818.11-1818.40" wire width 3 \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:1904.11-1904.45" + attribute \src "ls180.v:1815.11-1815.45" wire width 2 \builder_sdphy_sdphycmdw_next_state - attribute \src "ls180.v:1903.11-1903.40" + attribute \src "ls180.v:1814.11-1814.40" wire width 2 \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:1916.5-1916.39" + attribute \src "ls180.v:1827.5-1827.39" wire \builder_sdphy_sdphycrcr_next_state - attribute \src "ls180.v:1915.5-1915.34" + attribute \src "ls180.v:1826.5-1826.34" wire \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:1924.11-1924.46" + attribute \src "ls180.v:1835.11-1835.46" wire width 3 \builder_sdphy_sdphydatar_next_state - attribute \src "ls180.v:1923.11-1923.41" + attribute \src "ls180.v:1834.11-1834.41" wire width 3 \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:1900.5-1900.39" + attribute \src "ls180.v:1811.5-1811.39" wire \builder_sdphy_sdphyinit_next_state - attribute \src "ls180.v:1899.5-1899.34" + attribute \src "ls180.v:1810.5-1810.34" wire \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:2004.5-2004.23" + attribute \src "ls180.v:1915.5-1915.23" wire \builder_shared_ack - attribute \src "ls180.v:1998.13-1998.31" + attribute \src "ls180.v:1909.13-1909.31" wire width 30 \builder_shared_adr - attribute \src "ls180.v:2007.12-2007.30" + attribute \src "ls180.v:1918.12-1918.30" wire width 2 \builder_shared_bte - attribute \src "ls180.v:2006.12-2006.30" + attribute \src "ls180.v:1917.12-1917.30" wire width 3 \builder_shared_cti - attribute \src "ls180.v:2002.6-2002.24" + attribute \src "ls180.v:1913.6-1913.24" wire \builder_shared_cyc - attribute \src "ls180.v:2000.12-2000.32" + attribute \src "ls180.v:1911.12-1911.32" wire width 32 \builder_shared_dat_r - attribute \src "ls180.v:1999.13-1999.33" + attribute \src "ls180.v:1910.13-1910.33" wire width 32 \builder_shared_dat_w - attribute \src "ls180.v:2008.6-2008.24" + attribute \src "ls180.v:1919.6-1919.24" wire \builder_shared_err - attribute \src "ls180.v:2001.12-2001.30" + attribute \src "ls180.v:1912.12-1912.30" wire width 4 \builder_shared_sel - attribute \src "ls180.v:2003.6-2003.24" + attribute \src "ls180.v:1914.6-1914.24" wire \builder_shared_stb - attribute \src "ls180.v:2005.6-2005.23" + attribute \src "ls180.v:1916.6-1916.23" wire \builder_shared_we - attribute \src "ls180.v:2011.12-2011.29" - wire width 13 \builder_slave_sel - attribute \src "ls180.v:2012.12-2012.31" - wire width 13 \builder_slave_sel_r - attribute \src "ls180.v:1892.11-1892.40" + attribute \src "ls180.v:1922.11-1922.28" + wire width 6 \builder_slave_sel + attribute \src "ls180.v:1923.11-1923.30" + wire width 6 \builder_slave_sel_r + attribute \src "ls180.v:1803.11-1803.40" wire width 2 \builder_spimaster0_next_state - attribute \src "ls180.v:1891.11-1891.35" + attribute \src "ls180.v:1802.11-1802.35" wire width 2 \builder_spimaster0_state - attribute \src "ls180.v:1896.11-1896.40" + attribute \src "ls180.v:1807.11-1807.40" wire width 2 \builder_spimaster1_next_state - attribute \src "ls180.v:1895.11-1895.35" + attribute \src "ls180.v:1806.11-1806.35" wire width 2 \builder_spimaster1_state - attribute \src "ls180.v:2708.11-2708.24" + attribute \src "ls180.v:2619.11-2619.24" wire width 2 \builder_state - attribute \src "ls180.v:2761.5-2761.32" + attribute \src "ls180.v:2672.5-2672.32" wire \builder_sync_f_array_muxed0 - attribute \src "ls180.v:2762.5-2762.32" + attribute \src "ls180.v:2673.5-2673.32" wire \builder_sync_f_array_muxed1 - attribute \src "ls180.v:2754.11-2754.40" + attribute \src "ls180.v:2665.11-2665.40" wire width 2 \builder_sync_rhs_array_muxed0 - attribute \src "ls180.v:2755.12-2755.41" + attribute \src "ls180.v:2666.12-2666.41" wire width 13 \builder_sync_rhs_array_muxed1 - attribute \src "ls180.v:2756.5-2756.34" + attribute \src "ls180.v:2667.5-2667.34" wire \builder_sync_rhs_array_muxed2 - attribute \src "ls180.v:2757.5-2757.34" + attribute \src "ls180.v:2668.5-2668.34" wire \builder_sync_rhs_array_muxed3 - attribute \src "ls180.v:2758.5-2758.34" + attribute \src "ls180.v:2669.5-2669.34" wire \builder_sync_rhs_array_muxed4 - attribute \src "ls180.v:2759.5-2759.34" + attribute \src "ls180.v:2670.5-2670.34" wire \builder_sync_rhs_array_muxed5 - attribute \src "ls180.v:2760.5-2760.34" + attribute \src "ls180.v:2671.5-2671.34" wire \builder_sync_rhs_array_muxed6 - attribute \src "ls180.v:2014.6-2014.18" + attribute \src "ls180.v:1925.6-1925.18" wire \builder_wait - attribute \src "ls180.v:16.19-16.23" - wire width 3 input 12 \eint - attribute \src "ls180.v:182.12-182.18" + attribute \src "ls180.v:37.19-37.23" + wire width 3 input 33 \eint + attribute \src "ls180.v:157.12-157.18" wire width 3 \eint_1 - attribute \src "ls180.v:5.21-5.27" - wire width 16 output 1 \gpio_i - attribute \src "ls180.v:6.20-6.26" - wire width 16 output 2 \gpio_o - attribute \src "ls180.v:7.20-7.27" - wire width 16 output 3 \gpio_oe - attribute \src "ls180.v:8.14-8.21" - wire output 4 \i2c_scl + attribute \src "ls180.v:34.21-34.27" + wire width 16 output 30 \gpio_i + attribute \src "ls180.v:35.20-35.26" + wire width 16 output 31 \gpio_o + attribute \src "ls180.v:36.20-36.27" + wire width 16 output 32 \gpio_oe + attribute \src "ls180.v:7.14-7.21" + wire output 3 \i2c_scl + attribute \src "ls180.v:8.14-8.23" + wire output 4 \i2c_sda_i attribute \src "ls180.v:9.14-9.23" - wire output 5 \i2c_sda_i - attribute \src "ls180.v:10.14-10.23" - wire output 6 \i2c_sda_o - attribute \src "ls180.v:11.14-11.24" - wire output 7 \i2c_sda_oe + wire output 5 \i2c_sda_o + attribute \src "ls180.v:10.14-10.24" + wire output 6 \i2c_sda_oe attribute \src "ls180.v:49.13-49.21" wire input 45 \jtag_tck attribute \src "ls180.v:50.13-50.21" @@ -250593,310 +250017,222 @@ module \ls180 wire output 47 \jtag_tdo attribute \src "ls180.v:48.13-48.21" wire input 44 \jtag_tms - attribute \src "ls180.v:940.6-940.18" + attribute \src "ls180.v:851.6-851.18" wire \main_ack_cmd - attribute \src "ls180.v:942.6-942.20" + attribute \src "ls180.v:853.6-853.20" wire \main_ack_rdata - attribute \src "ls180.v:941.6-941.20" + attribute \src "ls180.v:852.6-852.20" wire \main_ack_wdata - attribute \src "ls180.v:938.5-938.22" + attribute \src "ls180.v:849.5-849.22" wire \main_cmd_consumed - attribute \src "ls180.v:321.5-321.28" + attribute \src "ls180.v:232.5-232.28" wire \main_converter0_counter - attribute \src "ls180.v:1844.5-1844.50" + attribute \src "ls180.v:1755.5-1755.50" wire \main_converter0_counter_converter0_next_value - attribute \src "ls180.v:1845.5-1845.53" + attribute \src "ls180.v:1756.5-1756.53" wire \main_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:323.12-323.33" + attribute \src "ls180.v:234.12-234.33" wire width 64 \main_converter0_dat_r - attribute \src "ls180.v:322.6-322.27" + attribute \src "ls180.v:233.6-233.27" wire \main_converter0_reset - attribute \src "ls180.v:320.5-320.25" + attribute \src "ls180.v:231.5-231.25" wire \main_converter0_skip - attribute \src "ls180.v:336.5-336.28" + attribute \src "ls180.v:247.5-247.28" wire \main_converter1_counter - attribute \src "ls180.v:1848.5-1848.50" + attribute \src "ls180.v:1759.5-1759.50" wire \main_converter1_counter_converter1_next_value - attribute \src "ls180.v:1849.5-1849.53" + attribute \src "ls180.v:1760.5-1760.53" wire \main_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:338.12-338.33" + attribute \src "ls180.v:249.12-249.33" wire width 64 \main_converter1_dat_r - attribute \src "ls180.v:337.6-337.27" + attribute \src "ls180.v:248.6-248.27" wire \main_converter1_reset - attribute \src "ls180.v:335.5-335.25" + attribute \src "ls180.v:246.5-246.25" wire \main_converter1_skip - attribute \src "ls180.v:935.5-935.27" + attribute \src "ls180.v:846.5-846.27" wire \main_converter_counter - attribute \src "ls180.v:1889.5-1889.48" + attribute \src "ls180.v:1800.5-1800.48" wire \main_converter_counter_converter_next_value - attribute \src "ls180.v:1890.5-1890.51" + attribute \src "ls180.v:1801.5-1801.51" wire \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:937.12-937.32" + attribute \src "ls180.v:848.12-848.32" wire width 32 \main_converter_dat_r - attribute \src "ls180.v:936.6-936.26" + attribute \src "ls180.v:847.6-847.26" wire \main_converter_reset - attribute \src "ls180.v:934.5-934.24" + attribute \src "ls180.v:845.5-845.24" wire \main_converter_skip - attribute \src "ls180.v:352.6-352.23" + attribute \src "ls180.v:263.6-263.23" wire \main_dfi_p0_act_n - attribute \src "ls180.v:343.13-343.32" + attribute \src "ls180.v:254.13-254.32" wire width 13 \main_dfi_p0_address - attribute \src "ls180.v:344.12-344.28" + attribute \src "ls180.v:255.12-255.28" wire width 2 \main_dfi_p0_bank - attribute \src "ls180.v:345.6-345.23" + attribute \src "ls180.v:256.6-256.23" wire \main_dfi_p0_cas_n - attribute \src "ls180.v:349.6-349.21" + attribute \src "ls180.v:260.6-260.21" wire \main_dfi_p0_cke - attribute \src "ls180.v:346.6-346.22" + attribute \src "ls180.v:257.6-257.22" wire \main_dfi_p0_cs_n - attribute \src "ls180.v:350.6-350.21" + attribute \src "ls180.v:261.6-261.21" wire \main_dfi_p0_odt - attribute \src "ls180.v:347.6-347.23" + attribute \src "ls180.v:258.6-258.23" wire \main_dfi_p0_ras_n - attribute \src "ls180.v:357.12-357.30" + attribute \src "ls180.v:268.12-268.30" wire width 16 \main_dfi_p0_rddata - attribute \src "ls180.v:356.6-356.27" + attribute \src "ls180.v:267.6-267.27" wire \main_dfi_p0_rddata_en - attribute \src "ls180.v:358.5-358.29" + attribute \src "ls180.v:269.5-269.29" wire \main_dfi_p0_rddata_valid - attribute \src "ls180.v:351.6-351.25" + attribute \src "ls180.v:262.6-262.25" wire \main_dfi_p0_reset_n - attribute \src "ls180.v:348.6-348.22" + attribute \src "ls180.v:259.6-259.22" wire \main_dfi_p0_we_n - attribute \src "ls180.v:353.13-353.31" + attribute \src "ls180.v:264.13-264.31" wire width 16 \main_dfi_p0_wrdata - attribute \src "ls180.v:354.6-354.27" + attribute \src "ls180.v:265.6-265.27" wire \main_dfi_p0_wrdata_en - attribute \src "ls180.v:355.12-355.35" + attribute \src "ls180.v:266.12-266.35" wire width 2 \main_dfi_p0_wrdata_mask - attribute \src "ls180.v:1175.12-1175.22" + attribute \src "ls180.v:1086.12-1086.22" wire width 24 \main_dummy - attribute \src "ls180.v:1085.12-1085.45" + attribute \src "ls180.v:996.12-996.45" wire width 16 \main_gpiotristateasic0_oe_storage - attribute \src "ls180.v:1087.12-1087.46" + attribute \src "ls180.v:998.12-998.46" wire width 16 \main_gpiotristateasic0_out_storage - attribute \src "ls180.v:1088.13-1088.42" + attribute \src "ls180.v:999.13-999.42" wire width 16 \main_gpiotristateasic0_pads_i - attribute \src "ls180.v:1089.13-1089.42" + attribute \src "ls180.v:1000.13-1000.42" wire width 16 \main_gpiotristateasic0_pads_o - attribute \src "ls180.v:1090.13-1090.43" + attribute \src "ls180.v:1001.13-1001.43" wire width 16 \main_gpiotristateasic0_pads_oe - attribute \src "ls180.v:1086.12-1086.41" + attribute \src "ls180.v:997.12-997.41" wire width 16 \main_gpiotristateasic0_status - attribute \src "ls180.v:1092.5-1092.33" + attribute \src "ls180.v:1003.5-1003.33" wire \main_gpiotristateasic1_oe_re - attribute \src "ls180.v:1091.12-1091.45" + attribute \src "ls180.v:1002.12-1002.45" wire width 16 \main_gpiotristateasic1_oe_storage - attribute \src "ls180.v:1096.5-1096.34" + attribute \src "ls180.v:1007.5-1007.34" wire \main_gpiotristateasic1_out_re - attribute \src "ls180.v:1095.12-1095.46" + attribute \src "ls180.v:1006.12-1006.46" wire width 16 \main_gpiotristateasic1_out_storage - attribute \src "ls180.v:1097.13-1097.42" + attribute \src "ls180.v:1008.13-1008.42" wire width 16 \main_gpiotristateasic1_pads_i - attribute \src "ls180.v:1098.13-1098.42" + attribute \src "ls180.v:1009.13-1009.42" wire width 16 \main_gpiotristateasic1_pads_o - attribute \src "ls180.v:1099.13-1099.43" + attribute \src "ls180.v:1010.13-1010.43" wire width 16 \main_gpiotristateasic1_pads_oe - attribute \src "ls180.v:1093.12-1093.41" + attribute \src "ls180.v:1004.12-1004.41" wire width 16 \main_gpiotristateasic1_status - attribute \src "ls180.v:1094.6-1094.31" + attribute \src "ls180.v:1005.6-1005.31" wire \main_gpiotristateasic1_we - attribute \src "ls180.v:1197.6-1197.17" + attribute \src "ls180.v:1108.6-1108.17" wire \main_i2c_oe - attribute \src "ls180.v:1200.5-1200.16" + attribute \src "ls180.v:1111.5-1111.16" wire \main_i2c_re - attribute \src "ls180.v:1196.6-1196.18" + attribute \src "ls180.v:1107.6-1107.18" wire \main_i2c_scl - attribute \src "ls180.v:1198.6-1198.19" + attribute \src "ls180.v:1109.6-1109.19" wire \main_i2c_sda0 - attribute \src "ls180.v:1201.6-1201.19" + attribute \src "ls180.v:1112.6-1112.19" wire \main_i2c_sda1 - attribute \src "ls180.v:1202.6-1202.21" + attribute \src "ls180.v:1113.6-1113.21" wire \main_i2c_status - attribute \src "ls180.v:1199.11-1199.27" + attribute \src "ls180.v:1110.11-1110.27" wire width 3 \main_i2c_storage - attribute \src "ls180.v:1203.6-1203.17" + attribute \src "ls180.v:1114.6-1114.17" wire \main_i2c_we - attribute \src "ls180.v:342.5-342.17" + attribute \src "ls180.v:253.5-253.17" wire \main_int_rst - attribute \src "ls180.v:1663.6-1663.29" + attribute \src "ls180.v:1574.6-1574.29" wire \main_interface0_bus_ack - attribute \src "ls180.v:1657.13-1657.36" + attribute \src "ls180.v:1568.13-1568.36" wire width 32 \main_interface0_bus_adr - attribute \src "ls180.v:1666.11-1666.34" + attribute \src "ls180.v:1577.11-1577.34" wire width 2 \main_interface0_bus_bte - attribute \src "ls180.v:1665.11-1665.34" + attribute \src "ls180.v:1576.11-1576.34" wire width 3 \main_interface0_bus_cti - attribute \src "ls180.v:1661.6-1661.29" + attribute \src "ls180.v:1572.6-1572.29" wire \main_interface0_bus_cyc - attribute \src "ls180.v:1659.13-1659.38" + attribute \src "ls180.v:1570.13-1570.38" wire width 64 \main_interface0_bus_dat_r - attribute \src "ls180.v:1658.13-1658.38" + attribute \src "ls180.v:1569.13-1569.38" wire width 64 \main_interface0_bus_dat_w - attribute \src "ls180.v:1667.6-1667.29" + attribute \src "ls180.v:1578.6-1578.29" wire \main_interface0_bus_err - attribute \src "ls180.v:1660.12-1660.35" + attribute \src "ls180.v:1571.12-1571.35" wire width 8 \main_interface0_bus_sel - attribute \src "ls180.v:1662.6-1662.29" + attribute \src "ls180.v:1573.6-1573.29" wire \main_interface0_bus_stb - attribute \src "ls180.v:1664.6-1664.28" + attribute \src "ls180.v:1575.6-1575.28" wire \main_interface0_bus_we - attribute \src "ls180.v:315.5-315.44" + attribute \src "ls180.v:226.5-226.44" wire \main_interface0_converted_interface_ack - attribute \src "ls180.v:309.13-309.52" + attribute \src "ls180.v:220.13-220.52" wire width 30 \main_interface0_converted_interface_adr - attribute \src "ls180.v:318.12-318.51" + attribute \src "ls180.v:229.12-229.51" wire width 2 \main_interface0_converted_interface_bte - attribute \src "ls180.v:317.12-317.51" + attribute \src "ls180.v:228.12-228.51" wire width 3 \main_interface0_converted_interface_cti - attribute \src "ls180.v:313.6-313.45" + attribute \src "ls180.v:224.6-224.45" wire \main_interface0_converted_interface_cyc - attribute \src "ls180.v:311.13-311.54" + attribute \src "ls180.v:222.13-222.54" wire width 64 \main_interface0_converted_interface_dat_r - attribute \src "ls180.v:310.13-310.54" + attribute \src "ls180.v:221.13-221.54" wire width 64 \main_interface0_converted_interface_dat_w - attribute \src "ls180.v:319.5-319.44" + attribute \src "ls180.v:230.5-230.44" wire \main_interface0_converted_interface_err - attribute \src "ls180.v:312.12-312.51" + attribute \src "ls180.v:223.12-223.51" wire width 8 \main_interface0_converted_interface_sel - attribute \src "ls180.v:314.6-314.45" + attribute \src "ls180.v:225.6-225.45" wire \main_interface0_converted_interface_stb - attribute \src "ls180.v:316.6-316.44" + attribute \src "ls180.v:227.6-227.44" wire \main_interface0_converted_interface_we - attribute \src "ls180.v:255.5-255.32" - wire \main_interface0_ram_bus_ack - attribute \src "ls180.v:249.13-249.40" - wire width 30 \main_interface0_ram_bus_adr - attribute \src "ls180.v:258.12-258.39" - wire width 2 \main_interface0_ram_bus_bte - attribute \src "ls180.v:257.12-257.39" - wire width 3 \main_interface0_ram_bus_cti - attribute \src "ls180.v:253.6-253.33" - wire \main_interface0_ram_bus_cyc - attribute \src "ls180.v:251.13-251.42" - wire width 64 \main_interface0_ram_bus_dat_r - attribute \src "ls180.v:250.13-250.42" - wire width 64 \main_interface0_ram_bus_dat_w - attribute \src "ls180.v:259.5-259.32" - wire \main_interface0_ram_bus_err - attribute \src "ls180.v:252.12-252.39" - wire width 8 \main_interface0_ram_bus_sel - attribute \src "ls180.v:254.6-254.33" - wire \main_interface0_ram_bus_stb - attribute \src "ls180.v:256.6-256.32" - wire \main_interface0_ram_bus_we - attribute \src "ls180.v:1754.6-1754.29" + attribute \src "ls180.v:1665.6-1665.29" wire \main_interface1_bus_ack - attribute \src "ls180.v:1748.12-1748.35" + attribute \src "ls180.v:1659.12-1659.35" wire width 32 \main_interface1_bus_adr - attribute \src "ls180.v:1757.11-1757.34" + attribute \src "ls180.v:1668.11-1668.34" wire width 2 \main_interface1_bus_bte - attribute \src "ls180.v:1756.11-1756.34" + attribute \src "ls180.v:1667.11-1667.34" wire width 3 \main_interface1_bus_cti - attribute \src "ls180.v:1752.5-1752.28" + attribute \src "ls180.v:1663.5-1663.28" wire \main_interface1_bus_cyc - attribute \src "ls180.v:1750.13-1750.38" + attribute \src "ls180.v:1661.13-1661.38" wire width 64 \main_interface1_bus_dat_r - attribute \src "ls180.v:1749.12-1749.37" + attribute \src "ls180.v:1660.12-1660.37" wire width 64 \main_interface1_bus_dat_w - attribute \src "ls180.v:1758.6-1758.29" + attribute \src "ls180.v:1669.6-1669.29" wire \main_interface1_bus_err - attribute \src "ls180.v:1751.11-1751.34" + attribute \src "ls180.v:1662.11-1662.34" wire width 8 \main_interface1_bus_sel - attribute \src "ls180.v:1753.5-1753.28" + attribute \src "ls180.v:1664.5-1664.28" wire \main_interface1_bus_stb - attribute \src "ls180.v:1755.5-1755.27" + attribute \src "ls180.v:1666.5-1666.27" wire \main_interface1_bus_we - attribute \src "ls180.v:330.5-330.44" + attribute \src "ls180.v:241.5-241.44" wire \main_interface1_converted_interface_ack - attribute \src "ls180.v:324.13-324.52" + attribute \src "ls180.v:235.13-235.52" wire width 30 \main_interface1_converted_interface_adr - attribute \src "ls180.v:333.12-333.51" + attribute \src "ls180.v:244.12-244.51" wire width 2 \main_interface1_converted_interface_bte - attribute \src "ls180.v:332.12-332.51" + attribute \src "ls180.v:243.12-243.51" wire width 3 \main_interface1_converted_interface_cti - attribute \src "ls180.v:328.6-328.45" + attribute \src "ls180.v:239.6-239.45" wire \main_interface1_converted_interface_cyc - attribute \src "ls180.v:326.13-326.54" + attribute \src "ls180.v:237.13-237.54" wire width 64 \main_interface1_converted_interface_dat_r - attribute \src "ls180.v:325.13-325.54" + attribute \src "ls180.v:236.13-236.54" wire width 64 \main_interface1_converted_interface_dat_w - attribute \src "ls180.v:334.5-334.44" + attribute \src "ls180.v:245.5-245.44" wire \main_interface1_converted_interface_err - attribute \src "ls180.v:327.12-327.51" + attribute \src "ls180.v:238.12-238.51" wire width 8 \main_interface1_converted_interface_sel - attribute \src "ls180.v:329.6-329.45" + attribute \src "ls180.v:240.6-240.45" wire \main_interface1_converted_interface_stb - attribute \src "ls180.v:331.6-331.44" + attribute \src "ls180.v:242.6-242.44" wire \main_interface1_converted_interface_we - attribute \src "ls180.v:270.5-270.32" - wire \main_interface1_ram_bus_ack - attribute \src "ls180.v:264.13-264.40" - wire width 30 \main_interface1_ram_bus_adr - attribute \src "ls180.v:273.12-273.39" - wire width 2 \main_interface1_ram_bus_bte - attribute \src "ls180.v:272.12-272.39" - wire width 3 \main_interface1_ram_bus_cti - attribute \src "ls180.v:268.6-268.33" - wire \main_interface1_ram_bus_cyc - attribute \src "ls180.v:266.13-266.42" - wire width 64 \main_interface1_ram_bus_dat_r - attribute \src "ls180.v:265.13-265.42" - wire width 64 \main_interface1_ram_bus_dat_w - attribute \src "ls180.v:274.5-274.32" - wire \main_interface1_ram_bus_err - attribute \src "ls180.v:267.12-267.39" - wire width 8 \main_interface1_ram_bus_sel - attribute \src "ls180.v:269.6-269.33" - wire \main_interface1_ram_bus_stb - attribute \src "ls180.v:271.6-271.32" - wire \main_interface1_ram_bus_we - attribute \src "ls180.v:285.5-285.32" - wire \main_interface2_ram_bus_ack - attribute \src "ls180.v:279.13-279.40" - wire width 30 \main_interface2_ram_bus_adr - attribute \src "ls180.v:288.12-288.39" - wire width 2 \main_interface2_ram_bus_bte - attribute \src "ls180.v:287.12-287.39" - wire width 3 \main_interface2_ram_bus_cti - attribute \src "ls180.v:283.6-283.33" - wire \main_interface2_ram_bus_cyc - attribute \src "ls180.v:281.13-281.42" - wire width 64 \main_interface2_ram_bus_dat_r - attribute \src "ls180.v:280.13-280.42" - wire width 64 \main_interface2_ram_bus_dat_w - attribute \src "ls180.v:289.5-289.32" - wire \main_interface2_ram_bus_err - attribute \src "ls180.v:282.12-282.39" - wire width 8 \main_interface2_ram_bus_sel - attribute \src "ls180.v:284.6-284.33" - wire \main_interface2_ram_bus_stb - attribute \src "ls180.v:286.6-286.32" - wire \main_interface2_ram_bus_we - attribute \src "ls180.v:300.5-300.32" - wire \main_interface3_ram_bus_ack - attribute \src "ls180.v:294.13-294.40" - wire width 30 \main_interface3_ram_bus_adr - attribute \src "ls180.v:303.12-303.39" - wire width 2 \main_interface3_ram_bus_bte - attribute \src "ls180.v:302.12-302.39" - wire width 3 \main_interface3_ram_bus_cti - attribute \src "ls180.v:298.6-298.33" - wire \main_interface3_ram_bus_cyc - attribute \src "ls180.v:296.13-296.42" - wire width 64 \main_interface3_ram_bus_dat_r - attribute \src "ls180.v:295.13-295.42" - wire width 64 \main_interface3_ram_bus_dat_w - attribute \src "ls180.v:304.5-304.32" - wire \main_interface3_ram_bus_err - attribute \src "ls180.v:297.12-297.39" - wire width 8 \main_interface3_ram_bus_sel - attribute \src "ls180.v:299.6-299.33" - wire \main_interface3_ram_bus_stb - attribute \src "ls180.v:301.6-301.32" - wire \main_interface3_ram_bus_we - attribute \src "ls180.v:218.12-218.32" - wire width 6 \main_libresocsim_adr + attribute \src "ls180.v:174.12-174.32" + wire width 4 \main_libresocsim_adr attribute \src "ls180.v:62.6-62.32" wire \main_libresocsim_bus_error attribute \src "ls180.v:63.12-63.39" @@ -250905,109 +250241,109 @@ module \ls180 wire width 32 \main_libresocsim_bus_errors_status attribute \src "ls180.v:60.6-60.36" wire \main_libresocsim_bus_errors_we - attribute \src "ls180.v:219.13-219.35" + attribute \src "ls180.v:175.13-175.35" wire width 64 \main_libresocsim_dat_r - attribute \src "ls180.v:221.13-221.35" + attribute \src "ls180.v:177.13-177.35" wire width 64 \main_libresocsim_dat_w - attribute \src "ls180.v:227.5-227.27" + attribute \src "ls180.v:183.5-183.27" wire \main_libresocsim_en_re - attribute \src "ls180.v:226.5-226.32" + attribute \src "ls180.v:182.5-182.32" wire \main_libresocsim_en_storage - attribute \src "ls180.v:243.6-243.45" + attribute \src "ls180.v:199.6-199.45" wire \main_libresocsim_eventmanager_pending_r - attribute \src "ls180.v:242.6-242.46" + attribute \src "ls180.v:198.6-198.46" wire \main_libresocsim_eventmanager_pending_re - attribute \src "ls180.v:245.6-245.45" + attribute \src "ls180.v:201.6-201.45" wire \main_libresocsim_eventmanager_pending_w - attribute \src "ls180.v:244.6-244.46" + attribute \src "ls180.v:200.6-200.46" wire \main_libresocsim_eventmanager_pending_we - attribute \src "ls180.v:247.5-247.37" + attribute \src "ls180.v:203.5-203.37" wire \main_libresocsim_eventmanager_re - attribute \src "ls180.v:239.6-239.44" + attribute \src "ls180.v:195.6-195.44" wire \main_libresocsim_eventmanager_status_r - attribute \src "ls180.v:238.6-238.45" + attribute \src "ls180.v:194.6-194.45" wire \main_libresocsim_eventmanager_status_re - attribute \src "ls180.v:241.6-241.44" + attribute \src "ls180.v:197.6-197.44" wire \main_libresocsim_eventmanager_status_w - attribute \src "ls180.v:240.6-240.45" + attribute \src "ls180.v:196.6-196.45" wire \main_libresocsim_eventmanager_status_we - attribute \src "ls180.v:246.5-246.42" + attribute \src "ls180.v:202.5-202.42" wire \main_libresocsim_eventmanager_storage - attribute \src "ls180.v:232.6-232.26" + attribute \src "ls180.v:188.6-188.26" wire \main_libresocsim_irq - attribute \src "ls180.v:165.6-165.32" + attribute \src "ls180.v:121.6-121.32" wire \main_libresocsim_libresoc0 - attribute \src "ls180.v:166.6-166.32" + attribute \src "ls180.v:122.6-122.32" wire \main_libresocsim_libresoc1 - attribute \src "ls180.v:167.13-167.39" + attribute \src "ls180.v:123.13-123.39" wire width 64 \main_libresocsim_libresoc2 - attribute \src "ls180.v:169.12-169.45" + attribute \src "ls180.v:125.12-125.45" wire width 2 \main_libresocsim_libresoc_clk_sel - attribute \src "ls180.v:171.12-171.66" + attribute \src "ls180.v:154.12-154.66" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i - attribute \src "ls180.v:172.13-172.67" + attribute \src "ls180.v:155.13-155.67" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o - attribute \src "ls180.v:173.13-173.68" + attribute \src "ls180.v:156.13-156.68" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe - attribute \src "ls180.v:174.6-174.61" + attribute \src "ls180.v:127.6-127.61" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - attribute \src "ls180.v:175.5-175.62" + attribute \src "ls180.v:128.5-128.62" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - attribute \src "ls180.v:176.6-176.63" + attribute \src "ls180.v:129.6-129.63" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - attribute \src "ls180.v:177.6-177.64" + attribute \src "ls180.v:130.6-130.64" wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - attribute \src "ls180.v:200.6-200.64" + attribute \src "ls180.v:131.6-131.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - attribute \src "ls180.v:201.5-201.65" + attribute \src "ls180.v:132.5-132.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - attribute \src "ls180.v:202.6-202.66" + attribute \src "ls180.v:133.6-133.66" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - attribute \src "ls180.v:203.6-203.67" + attribute \src "ls180.v:134.6-134.67" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - attribute \src "ls180.v:204.11-204.72" + attribute \src "ls180.v:135.11-135.72" wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i - attribute \src "ls180.v:205.12-205.73" + attribute \src "ls180.v:136.12-136.73" wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o - attribute \src "ls180.v:206.6-206.68" + attribute \src "ls180.v:137.6-137.68" wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe - attribute \src "ls180.v:188.13-188.68" + attribute \src "ls180.v:142.13-142.68" wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a - attribute \src "ls180.v:197.12-197.68" + attribute \src "ls180.v:151.12-151.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba - attribute \src "ls180.v:194.6-194.65" + attribute \src "ls180.v:148.6-148.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - attribute \src "ls180.v:196.6-196.63" + attribute \src "ls180.v:150.6-150.63" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - attribute \src "ls180.v:195.6-195.64" + attribute \src "ls180.v:149.6-149.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - attribute \src "ls180.v:198.12-198.68" + attribute \src "ls180.v:152.12-152.68" wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm - attribute \src "ls180.v:189.12-189.70" + attribute \src "ls180.v:143.12-143.70" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i - attribute \src "ls180.v:190.13-190.71" + attribute \src "ls180.v:144.13-144.71" wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o - attribute \src "ls180.v:191.6-191.65" + attribute \src "ls180.v:145.6-145.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - attribute \src "ls180.v:193.6-193.65" + attribute \src "ls180.v:147.6-147.65" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - attribute \src "ls180.v:192.6-192.64" + attribute \src "ls180.v:146.6-146.64" wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - attribute \src "ls180.v:184.6-184.67" + attribute \src "ls180.v:158.6-158.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - attribute \src "ls180.v:186.6-186.68" + attribute \src "ls180.v:160.6-160.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - attribute \src "ls180.v:187.6-187.68" + attribute \src "ls180.v:161.6-161.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - attribute \src "ls180.v:185.6-185.68" + attribute \src "ls180.v:159.6-159.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - attribute \src "ls180.v:178.6-178.67" + attribute \src "ls180.v:138.6-138.67" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - attribute \src "ls180.v:180.6-180.68" + attribute \src "ls180.v:140.6-140.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - attribute \src "ls180.v:181.6-181.68" + attribute \src "ls180.v:141.6-141.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - attribute \src "ls180.v:179.6-179.68" + attribute \src "ls180.v:139.6-139.68" wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi attribute \src "ls180.v:72.6-72.40" wire \main_libresocsim_libresoc_dbus_ack @@ -251053,103 +250389,15 @@ module \ls180 wire \main_libresocsim_libresoc_ibus_stb attribute \src "ls180.v:84.6-84.39" wire \main_libresocsim_libresoc_ibus_we - attribute \src "ls180.v:123.6-123.46" - wire \main_libresocsim_libresoc_interface0_ack - attribute \src "ls180.v:117.13-117.53" - wire width 29 \main_libresocsim_libresoc_interface0_adr - attribute \src "ls180.v:126.12-126.52" - wire width 2 \main_libresocsim_libresoc_interface0_bte - attribute \src "ls180.v:125.12-125.52" - wire width 3 \main_libresocsim_libresoc_interface0_cti - attribute \src "ls180.v:121.6-121.46" - wire \main_libresocsim_libresoc_interface0_cyc - attribute \src "ls180.v:119.13-119.55" - wire width 64 \main_libresocsim_libresoc_interface0_dat_r - attribute \src "ls180.v:118.13-118.55" - wire width 64 \main_libresocsim_libresoc_interface0_dat_w - attribute \src "ls180.v:127.6-127.46" - wire \main_libresocsim_libresoc_interface0_err - attribute \src "ls180.v:120.12-120.52" - wire width 8 \main_libresocsim_libresoc_interface0_sel - attribute \src "ls180.v:122.6-122.46" - wire \main_libresocsim_libresoc_interface0_stb - attribute \src "ls180.v:124.6-124.45" - wire \main_libresocsim_libresoc_interface0_we - attribute \src "ls180.v:134.6-134.46" - wire \main_libresocsim_libresoc_interface1_ack - attribute \src "ls180.v:128.13-128.53" - wire width 29 \main_libresocsim_libresoc_interface1_adr - attribute \src "ls180.v:137.12-137.52" - wire width 2 \main_libresocsim_libresoc_interface1_bte - attribute \src "ls180.v:136.12-136.52" - wire width 3 \main_libresocsim_libresoc_interface1_cti - attribute \src "ls180.v:132.6-132.46" - wire \main_libresocsim_libresoc_interface1_cyc - attribute \src "ls180.v:130.13-130.55" - wire width 64 \main_libresocsim_libresoc_interface1_dat_r - attribute \src "ls180.v:129.13-129.55" - wire width 64 \main_libresocsim_libresoc_interface1_dat_w - attribute \src "ls180.v:138.6-138.46" - wire \main_libresocsim_libresoc_interface1_err - attribute \src "ls180.v:131.12-131.52" - wire width 8 \main_libresocsim_libresoc_interface1_sel - attribute \src "ls180.v:133.6-133.46" - wire \main_libresocsim_libresoc_interface1_stb - attribute \src "ls180.v:135.6-135.45" - wire \main_libresocsim_libresoc_interface1_we - attribute \src "ls180.v:145.6-145.46" - wire \main_libresocsim_libresoc_interface2_ack - attribute \src "ls180.v:139.13-139.53" - wire width 29 \main_libresocsim_libresoc_interface2_adr - attribute \src "ls180.v:148.12-148.52" - wire width 2 \main_libresocsim_libresoc_interface2_bte - attribute \src "ls180.v:147.12-147.52" - wire width 3 \main_libresocsim_libresoc_interface2_cti - attribute \src "ls180.v:143.6-143.46" - wire \main_libresocsim_libresoc_interface2_cyc - attribute \src "ls180.v:141.13-141.55" - wire width 64 \main_libresocsim_libresoc_interface2_dat_r - attribute \src "ls180.v:140.13-140.55" - wire width 64 \main_libresocsim_libresoc_interface2_dat_w - attribute \src "ls180.v:149.6-149.46" - wire \main_libresocsim_libresoc_interface2_err - attribute \src "ls180.v:142.12-142.52" - wire width 8 \main_libresocsim_libresoc_interface2_sel - attribute \src "ls180.v:144.6-144.46" - wire \main_libresocsim_libresoc_interface2_stb - attribute \src "ls180.v:146.6-146.45" - wire \main_libresocsim_libresoc_interface2_we - attribute \src "ls180.v:156.6-156.46" - wire \main_libresocsim_libresoc_interface3_ack - attribute \src "ls180.v:150.13-150.53" - wire width 29 \main_libresocsim_libresoc_interface3_adr - attribute \src "ls180.v:159.12-159.52" - wire width 2 \main_libresocsim_libresoc_interface3_bte - attribute \src "ls180.v:158.12-158.52" - wire width 3 \main_libresocsim_libresoc_interface3_cti - attribute \src "ls180.v:154.6-154.46" - wire \main_libresocsim_libresoc_interface3_cyc - attribute \src "ls180.v:152.13-152.55" - wire width 64 \main_libresocsim_libresoc_interface3_dat_r - attribute \src "ls180.v:151.13-151.55" - wire width 64 \main_libresocsim_libresoc_interface3_dat_w - attribute \src "ls180.v:160.6-160.46" - wire \main_libresocsim_libresoc_interface3_err - attribute \src "ls180.v:153.12-153.52" - wire width 8 \main_libresocsim_libresoc_interface3_sel - attribute \src "ls180.v:155.6-155.46" - wire \main_libresocsim_libresoc_interface3_stb - attribute \src "ls180.v:157.6-157.45" - wire \main_libresocsim_libresoc_interface3_we attribute \src "ls180.v:65.12-65.47" wire width 16 \main_libresocsim_libresoc_interrupt - attribute \src "ls180.v:161.6-161.40" + attribute \src "ls180.v:117.6-117.40" wire \main_libresocsim_libresoc_jtag_tck - attribute \src "ls180.v:163.6-163.40" + attribute \src "ls180.v:119.6-119.40" wire \main_libresocsim_libresoc_jtag_tdi - attribute \src "ls180.v:164.6-164.40" + attribute \src "ls180.v:120.6-120.40" wire \main_libresocsim_libresoc_jtag_tdo - attribute \src "ls180.v:162.6-162.40" + attribute \src "ls180.v:118.6-118.40" wire \main_libresocsim_libresoc_jtag_tms attribute \src "ls180.v:112.6-112.43" wire \main_libresocsim_libresoc_jtag_wb_ack @@ -251173,9 +250421,9 @@ module \ls180 wire \main_libresocsim_libresoc_jtag_wb_stb attribute \src "ls180.v:113.6-113.42" wire \main_libresocsim_libresoc_jtag_wb_we - attribute \src "ls180.v:168.6-168.40" + attribute \src "ls180.v:124.6-124.40" wire \main_libresocsim_libresoc_pll_18_o - attribute \src "ls180.v:170.6-170.41" + attribute \src "ls180.v:126.6-126.41" wire \main_libresocsim_libresoc_pll_lck_o attribute \src "ls180.v:64.6-64.37" wire \main_libresocsim_libresoc_reset @@ -251215,35 +250463,35 @@ module \ls180 wire \main_libresocsim_libresoc_xics_ics_stb attribute \src "ls180.v:104.5-104.42" wire \main_libresocsim_libresoc_xics_ics_we - attribute \src "ls180.v:223.5-223.29" + attribute \src "ls180.v:179.5-179.29" wire \main_libresocsim_load_re - attribute \src "ls180.v:222.12-222.41" + attribute \src "ls180.v:178.12-178.41" wire width 32 \main_libresocsim_load_storage - attribute \src "ls180.v:213.5-213.33" + attribute \src "ls180.v:169.5-169.33" wire \main_libresocsim_ram_bus_ack - attribute \src "ls180.v:207.13-207.41" + attribute \src "ls180.v:163.13-163.41" wire width 30 \main_libresocsim_ram_bus_adr - attribute \src "ls180.v:216.12-216.40" + attribute \src "ls180.v:172.12-172.40" wire width 2 \main_libresocsim_ram_bus_bte - attribute \src "ls180.v:215.12-215.40" + attribute \src "ls180.v:171.12-171.40" wire width 3 \main_libresocsim_ram_bus_cti - attribute \src "ls180.v:211.6-211.34" + attribute \src "ls180.v:167.6-167.34" wire \main_libresocsim_ram_bus_cyc - attribute \src "ls180.v:209.13-209.43" + attribute \src "ls180.v:165.13-165.43" wire width 64 \main_libresocsim_ram_bus_dat_r - attribute \src "ls180.v:208.13-208.43" + attribute \src "ls180.v:164.13-164.43" wire width 64 \main_libresocsim_ram_bus_dat_w - attribute \src "ls180.v:217.5-217.33" + attribute \src "ls180.v:173.5-173.33" wire \main_libresocsim_ram_bus_err - attribute \src "ls180.v:210.12-210.40" + attribute \src "ls180.v:166.12-166.40" wire width 8 \main_libresocsim_ram_bus_sel - attribute \src "ls180.v:212.6-212.34" + attribute \src "ls180.v:168.6-168.34" wire \main_libresocsim_ram_bus_stb - attribute \src "ls180.v:214.6-214.33" + attribute \src "ls180.v:170.6-170.33" wire \main_libresocsim_ram_bus_we - attribute \src "ls180.v:225.5-225.31" + attribute \src "ls180.v:181.5-181.31" wire \main_libresocsim_reload_re - attribute \src "ls180.v:224.12-224.43" + attribute \src "ls180.v:180.12-180.43" wire width 32 \main_libresocsim_reload_storage attribute \src "ls180.v:61.6-61.28" wire \main_libresocsim_reset @@ -251255,3106 +250503,3098 @@ module \ls180 wire \main_libresocsim_scratch_re attribute \src "ls180.v:57.12-57.44" wire width 32 \main_libresocsim_scratch_storage - attribute \src "ls180.v:229.5-229.37" + attribute \src "ls180.v:185.5-185.37" wire \main_libresocsim_update_value_re - attribute \src "ls180.v:228.5-228.42" + attribute \src "ls180.v:184.5-184.42" wire \main_libresocsim_update_value_storage - attribute \src "ls180.v:248.12-248.34" + attribute \src "ls180.v:204.12-204.34" wire width 32 \main_libresocsim_value - attribute \src "ls180.v:230.12-230.41" + attribute \src "ls180.v:186.12-186.41" wire width 32 \main_libresocsim_value_status - attribute \src "ls180.v:231.6-231.31" + attribute \src "ls180.v:187.6-187.31" wire \main_libresocsim_value_we - attribute \src "ls180.v:220.11-220.30" + attribute \src "ls180.v:176.11-176.30" wire width 8 \main_libresocsim_we - attribute \src "ls180.v:236.5-236.32" + attribute \src "ls180.v:192.5-192.32" wire \main_libresocsim_zero_clear - attribute \src "ls180.v:237.5-237.38" + attribute \src "ls180.v:193.5-193.38" wire \main_libresocsim_zero_old_trigger - attribute \src "ls180.v:234.5-234.34" + attribute \src "ls180.v:190.5-190.34" wire \main_libresocsim_zero_pending - attribute \src "ls180.v:233.6-233.34" + attribute \src "ls180.v:189.6-189.34" wire \main_libresocsim_zero_status - attribute \src "ls180.v:235.6-235.35" + attribute \src "ls180.v:191.6-191.35" wire \main_libresocsim_zero_trigger - attribute \src "ls180.v:932.6-932.26" + attribute \src "ls180.v:843.6-843.26" wire \main_litedram_wb_ack - attribute \src "ls180.v:926.12-926.32" + attribute \src "ls180.v:837.12-837.32" wire width 30 \main_litedram_wb_adr - attribute \src "ls180.v:930.5-930.25" + attribute \src "ls180.v:841.5-841.25" wire \main_litedram_wb_cyc - attribute \src "ls180.v:928.13-928.35" + attribute \src "ls180.v:839.13-839.35" wire width 16 \main_litedram_wb_dat_r - attribute \src "ls180.v:927.12-927.34" + attribute \src "ls180.v:838.12-838.34" wire width 16 \main_litedram_wb_dat_w - attribute \src "ls180.v:929.11-929.31" + attribute \src "ls180.v:840.11-840.31" wire width 2 \main_litedram_wb_sel - attribute \src "ls180.v:931.5-931.25" + attribute \src "ls180.v:842.5-842.25" wire \main_litedram_wb_stb - attribute \src "ls180.v:933.5-933.24" + attribute \src "ls180.v:844.5-844.24" wire \main_litedram_wb_we - attribute \src "ls180.v:1174.13-1174.20" + attribute \src "ls180.v:1085.13-1085.20" wire width 24 \main_nc - attribute \src "ls180.v:893.6-893.24" + attribute \src "ls180.v:804.6-804.24" wire \main_port_cmd_last - attribute \src "ls180.v:895.13-895.39" + attribute \src "ls180.v:806.13-806.39" wire width 24 \main_port_cmd_payload_addr - attribute \src "ls180.v:894.6-894.30" + attribute \src "ls180.v:805.6-805.30" wire \main_port_cmd_payload_we - attribute \src "ls180.v:892.6-892.25" + attribute \src "ls180.v:803.6-803.25" wire \main_port_cmd_ready - attribute \src "ls180.v:891.6-891.25" + attribute \src "ls180.v:802.6-802.25" wire \main_port_cmd_valid - attribute \src "ls180.v:890.6-890.21" + attribute \src "ls180.v:801.6-801.21" wire \main_port_flush - attribute \src "ls180.v:902.13-902.41" + attribute \src "ls180.v:813.13-813.41" wire width 16 \main_port_rdata_payload_data - attribute \src "ls180.v:901.6-901.27" + attribute \src "ls180.v:812.6-812.27" wire \main_port_rdata_ready - attribute \src "ls180.v:900.6-900.27" + attribute \src "ls180.v:811.6-811.27" wire \main_port_rdata_valid - attribute \src "ls180.v:898.13-898.41" + attribute \src "ls180.v:809.13-809.41" wire width 16 \main_port_wdata_payload_data - attribute \src "ls180.v:899.12-899.38" + attribute \src "ls180.v:810.12-810.38" wire width 2 \main_port_wdata_payload_we - attribute \src "ls180.v:897.6-897.27" + attribute \src "ls180.v:808.6-808.27" wire \main_port_wdata_ready - attribute \src "ls180.v:896.6-896.27" + attribute \src "ls180.v:807.6-807.27" wire \main_port_wdata_valid - attribute \src "ls180.v:1179.12-1179.29" + attribute \src "ls180.v:1090.12-1090.29" wire width 32 \main_pwm0_counter - attribute \src "ls180.v:1176.6-1176.22" + attribute \src "ls180.v:1087.6-1087.22" wire \main_pwm0_enable - attribute \src "ls180.v:1181.5-1181.24" + attribute \src "ls180.v:1092.5-1092.24" wire \main_pwm0_enable_re - attribute \src "ls180.v:1180.5-1180.29" + attribute \src "ls180.v:1091.5-1091.29" wire \main_pwm0_enable_storage - attribute \src "ls180.v:1178.13-1178.29" + attribute \src "ls180.v:1089.13-1089.29" wire width 32 \main_pwm0_period - attribute \src "ls180.v:1185.5-1185.24" + attribute \src "ls180.v:1096.5-1096.24" wire \main_pwm0_period_re - attribute \src "ls180.v:1184.12-1184.36" + attribute \src "ls180.v:1095.12-1095.36" wire width 32 \main_pwm0_period_storage - attribute \src "ls180.v:1177.13-1177.28" + attribute \src "ls180.v:1088.13-1088.28" wire width 32 \main_pwm0_width - attribute \src "ls180.v:1183.5-1183.23" + attribute \src "ls180.v:1094.5-1094.23" wire \main_pwm0_width_re - attribute \src "ls180.v:1182.12-1182.35" + attribute \src "ls180.v:1093.12-1093.35" wire width 32 \main_pwm0_width_storage - attribute \src "ls180.v:1189.12-1189.29" + attribute \src "ls180.v:1100.12-1100.29" wire width 32 \main_pwm1_counter - attribute \src "ls180.v:1186.6-1186.22" + attribute \src "ls180.v:1097.6-1097.22" wire \main_pwm1_enable - attribute \src "ls180.v:1191.5-1191.24" + attribute \src "ls180.v:1102.5-1102.24" wire \main_pwm1_enable_re - attribute \src "ls180.v:1190.5-1190.29" + attribute \src "ls180.v:1101.5-1101.29" wire \main_pwm1_enable_storage - attribute \src "ls180.v:1188.13-1188.29" + attribute \src "ls180.v:1099.13-1099.29" wire width 32 \main_pwm1_period - attribute \src "ls180.v:1195.5-1195.24" + attribute \src "ls180.v:1106.5-1106.24" wire \main_pwm1_period_re - attribute \src "ls180.v:1194.12-1194.36" + attribute \src "ls180.v:1105.12-1105.36" wire width 32 \main_pwm1_period_storage - attribute \src "ls180.v:1187.13-1187.28" + attribute \src "ls180.v:1098.13-1098.28" wire width 32 \main_pwm1_width - attribute \src "ls180.v:1193.5-1193.23" + attribute \src "ls180.v:1104.5-1104.23" wire \main_pwm1_width_re - attribute \src "ls180.v:1192.12-1192.35" + attribute \src "ls180.v:1103.12-1103.35" wire width 32 \main_pwm1_width_storage - attribute \src "ls180.v:359.11-359.25" + attribute \src "ls180.v:216.12-216.24" + wire width 4 \main_ram_adr + attribute \src "ls180.v:211.5-211.29" + wire \main_ram_bus_ram_bus_ack + attribute \src "ls180.v:205.13-205.37" + wire width 30 \main_ram_bus_ram_bus_adr + attribute \src "ls180.v:214.12-214.36" + wire width 2 \main_ram_bus_ram_bus_bte + attribute \src "ls180.v:213.12-213.36" + wire width 3 \main_ram_bus_ram_bus_cti + attribute \src "ls180.v:209.6-209.30" + wire \main_ram_bus_ram_bus_cyc + attribute \src "ls180.v:207.13-207.39" + wire width 64 \main_ram_bus_ram_bus_dat_r + attribute \src "ls180.v:206.13-206.39" + wire width 64 \main_ram_bus_ram_bus_dat_w + attribute \src "ls180.v:215.5-215.29" + wire \main_ram_bus_ram_bus_err + attribute \src "ls180.v:208.12-208.36" + wire width 8 \main_ram_bus_ram_bus_sel + attribute \src "ls180.v:210.6-210.30" + wire \main_ram_bus_ram_bus_stb + attribute \src "ls180.v:212.6-212.29" + wire \main_ram_bus_ram_bus_we + attribute \src "ls180.v:217.13-217.27" + wire width 64 \main_ram_dat_r + attribute \src "ls180.v:219.13-219.27" + wire width 64 \main_ram_dat_w + attribute \src "ls180.v:218.11-218.22" + wire width 8 \main_ram_we + attribute \src "ls180.v:270.11-270.25" wire width 3 \main_rddata_en - attribute \src "ls180.v:1717.11-1717.43" + attribute \src "ls180.v:1628.11-1628.43" wire width 3 \main_sdblock2mem_converter_demux - attribute \src "ls180.v:1718.6-1718.42" + attribute \src "ls180.v:1629.6-1629.42" wire \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:1708.6-1708.43" + attribute \src "ls180.v:1619.6-1619.43" wire \main_sdblock2mem_converter_sink_first - attribute \src "ls180.v:1709.6-1709.42" + attribute \src "ls180.v:1620.6-1620.42" wire \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:1710.12-1710.56" + attribute \src "ls180.v:1621.12-1621.56" wire width 8 \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:1707.6-1707.43" + attribute \src "ls180.v:1618.6-1618.43" wire \main_sdblock2mem_converter_sink_ready - attribute \src "ls180.v:1706.6-1706.43" + attribute \src "ls180.v:1617.6-1617.43" wire \main_sdblock2mem_converter_sink_valid - attribute \src "ls180.v:1713.5-1713.44" + attribute \src "ls180.v:1624.5-1624.44" wire \main_sdblock2mem_converter_source_first - attribute \src "ls180.v:1714.5-1714.43" + attribute \src "ls180.v:1625.5-1625.43" wire \main_sdblock2mem_converter_source_last - attribute \src "ls180.v:1715.12-1715.58" + attribute \src "ls180.v:1626.12-1626.58" wire width 64 \main_sdblock2mem_converter_source_payload_data - attribute \src "ls180.v:1716.11-1716.70" + attribute \src "ls180.v:1627.11-1627.70" wire width 4 \main_sdblock2mem_converter_source_payload_valid_token_count - attribute \src "ls180.v:1712.6-1712.45" + attribute \src "ls180.v:1623.6-1623.45" wire \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:1711.6-1711.45" + attribute \src "ls180.v:1622.6-1622.45" wire \main_sdblock2mem_converter_source_valid - attribute \src "ls180.v:1719.5-1719.42" + attribute \src "ls180.v:1630.5-1630.42" wire \main_sdblock2mem_converter_strobe_all - attribute \src "ls180.v:1692.11-1692.40" + attribute \src "ls180.v:1603.11-1603.40" wire width 5 \main_sdblock2mem_fifo_consume - attribute \src "ls180.v:1697.6-1697.35" + attribute \src "ls180.v:1608.6-1608.35" wire \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:1701.6-1701.41" + attribute \src "ls180.v:1612.6-1612.41" wire \main_sdblock2mem_fifo_fifo_in_first - attribute \src "ls180.v:1702.6-1702.40" + attribute \src "ls180.v:1613.6-1613.40" wire \main_sdblock2mem_fifo_fifo_in_last - attribute \src "ls180.v:1700.12-1700.54" + attribute \src "ls180.v:1611.12-1611.54" wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data - attribute \src "ls180.v:1704.6-1704.42" + attribute \src "ls180.v:1615.6-1615.42" wire \main_sdblock2mem_fifo_fifo_out_first - attribute \src "ls180.v:1705.6-1705.41" + attribute \src "ls180.v:1616.6-1616.41" wire \main_sdblock2mem_fifo_fifo_out_last - attribute \src "ls180.v:1703.12-1703.55" + attribute \src "ls180.v:1614.12-1614.55" wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data - attribute \src "ls180.v:1689.11-1689.38" + attribute \src "ls180.v:1600.11-1600.38" wire width 6 \main_sdblock2mem_fifo_level - attribute \src "ls180.v:1691.11-1691.40" + attribute \src "ls180.v:1602.11-1602.40" wire width 5 \main_sdblock2mem_fifo_produce - attribute \src "ls180.v:1698.12-1698.44" + attribute \src "ls180.v:1609.12-1609.44" wire width 5 \main_sdblock2mem_fifo_rdport_adr - attribute \src "ls180.v:1699.12-1699.46" + attribute \src "ls180.v:1610.12-1610.46" wire width 10 \main_sdblock2mem_fifo_rdport_dat_r - attribute \src "ls180.v:1690.5-1690.34" + attribute \src "ls180.v:1601.5-1601.34" wire \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:1675.6-1675.38" + attribute \src "ls180.v:1586.6-1586.38" wire \main_sdblock2mem_fifo_sink_first - attribute \src "ls180.v:1676.6-1676.37" + attribute \src "ls180.v:1587.6-1587.37" wire \main_sdblock2mem_fifo_sink_last - attribute \src "ls180.v:1677.12-1677.51" + attribute \src "ls180.v:1588.12-1588.51" wire width 8 \main_sdblock2mem_fifo_sink_payload_data - attribute \src "ls180.v:1674.6-1674.38" + attribute \src "ls180.v:1585.6-1585.38" wire \main_sdblock2mem_fifo_sink_ready - attribute \src "ls180.v:1673.6-1673.38" + attribute \src "ls180.v:1584.6-1584.38" wire \main_sdblock2mem_fifo_sink_valid - attribute \src "ls180.v:1680.6-1680.40" + attribute \src "ls180.v:1591.6-1591.40" wire \main_sdblock2mem_fifo_source_first - attribute \src "ls180.v:1681.6-1681.39" + attribute \src "ls180.v:1592.6-1592.39" wire \main_sdblock2mem_fifo_source_last - attribute \src "ls180.v:1682.12-1682.53" + attribute \src "ls180.v:1593.12-1593.53" wire width 8 \main_sdblock2mem_fifo_source_payload_data - attribute \src "ls180.v:1679.6-1679.40" + attribute \src "ls180.v:1590.6-1590.40" wire \main_sdblock2mem_fifo_source_ready - attribute \src "ls180.v:1678.6-1678.40" + attribute \src "ls180.v:1589.6-1589.40" wire \main_sdblock2mem_fifo_source_valid - attribute \src "ls180.v:1687.12-1687.46" + attribute \src "ls180.v:1598.12-1598.46" wire width 10 \main_sdblock2mem_fifo_syncfifo_din - attribute \src "ls180.v:1688.12-1688.47" + attribute \src "ls180.v:1599.12-1599.47" wire width 10 \main_sdblock2mem_fifo_syncfifo_dout - attribute \src "ls180.v:1685.6-1685.39" + attribute \src "ls180.v:1596.6-1596.39" wire \main_sdblock2mem_fifo_syncfifo_re - attribute \src "ls180.v:1686.6-1686.45" + attribute \src "ls180.v:1597.6-1597.45" wire \main_sdblock2mem_fifo_syncfifo_readable - attribute \src "ls180.v:1683.6-1683.39" + attribute \src "ls180.v:1594.6-1594.39" wire \main_sdblock2mem_fifo_syncfifo_we - attribute \src "ls180.v:1684.6-1684.45" + attribute \src "ls180.v:1595.6-1595.45" wire \main_sdblock2mem_fifo_syncfifo_writable - attribute \src "ls180.v:1693.11-1693.43" + attribute \src "ls180.v:1604.11-1604.43" wire width 5 \main_sdblock2mem_fifo_wrport_adr - attribute \src "ls180.v:1694.12-1694.46" + attribute \src "ls180.v:1605.12-1605.46" wire width 10 \main_sdblock2mem_fifo_wrport_dat_r - attribute \src "ls180.v:1696.12-1696.46" + attribute \src "ls180.v:1607.12-1607.46" wire width 10 \main_sdblock2mem_fifo_wrport_dat_w - attribute \src "ls180.v:1695.6-1695.37" + attribute \src "ls180.v:1606.6-1606.37" wire \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:1670.6-1670.38" + attribute \src "ls180.v:1581.6-1581.38" wire \main_sdblock2mem_sink_sink_first - attribute \src "ls180.v:1671.6-1671.37" + attribute \src "ls180.v:1582.6-1582.37" wire \main_sdblock2mem_sink_sink_last - attribute \src "ls180.v:1727.12-1727.54" + attribute \src "ls180.v:1638.12-1638.54" wire width 32 \main_sdblock2mem_sink_sink_payload_address - attribute \src "ls180.v:1672.12-1672.52" + attribute \src "ls180.v:1583.12-1583.52" wire width 8 \main_sdblock2mem_sink_sink_payload_data0 - attribute \src "ls180.v:1728.12-1728.52" + attribute \src "ls180.v:1639.12-1639.52" wire width 64 \main_sdblock2mem_sink_sink_payload_data1 - attribute \src "ls180.v:1669.6-1669.39" + attribute \src "ls180.v:1580.6-1580.39" wire \main_sdblock2mem_sink_sink_ready0 - attribute \src "ls180.v:1726.6-1726.39" + attribute \src "ls180.v:1637.6-1637.39" wire \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:1668.6-1668.39" + attribute \src "ls180.v:1579.6-1579.39" wire \main_sdblock2mem_sink_sink_valid0 - attribute \src "ls180.v:1725.5-1725.38" + attribute \src "ls180.v:1636.5-1636.38" wire \main_sdblock2mem_sink_sink_valid1 - attribute \src "ls180.v:1722.6-1722.42" + attribute \src "ls180.v:1633.6-1633.42" wire \main_sdblock2mem_source_source_first - attribute \src "ls180.v:1723.6-1723.41" + attribute \src "ls180.v:1634.6-1634.41" wire \main_sdblock2mem_source_source_last - attribute \src "ls180.v:1724.13-1724.56" + attribute \src "ls180.v:1635.13-1635.56" wire width 64 \main_sdblock2mem_source_source_payload_data - attribute \src "ls180.v:1721.6-1721.42" + attribute \src "ls180.v:1632.6-1632.42" wire \main_sdblock2mem_source_source_ready - attribute \src "ls180.v:1720.6-1720.42" + attribute \src "ls180.v:1631.6-1631.42" wire \main_sdblock2mem_source_source_valid - attribute \src "ls180.v:1744.13-1744.52" + attribute \src "ls180.v:1655.13-1655.52" wire width 32 \main_sdblock2mem_wishbonedmawriter_base - attribute \src "ls180.v:1735.5-1735.47" + attribute \src "ls180.v:1646.5-1646.47" wire \main_sdblock2mem_wishbonedmawriter_base_re - attribute \src "ls180.v:1734.12-1734.59" + attribute \src "ls180.v:1645.12-1645.59" wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage - attribute \src "ls180.v:1739.5-1739.49" + attribute \src "ls180.v:1650.5-1650.49" wire \main_sdblock2mem_wishbonedmawriter_enable_re - attribute \src "ls180.v:1738.5-1738.54" + attribute \src "ls180.v:1649.5-1649.54" wire \main_sdblock2mem_wishbonedmawriter_enable_storage - attribute \src "ls180.v:1746.13-1746.54" + attribute \src "ls180.v:1657.13-1657.54" wire width 32 \main_sdblock2mem_wishbonedmawriter_length - attribute \src "ls180.v:1737.5-1737.49" + attribute \src "ls180.v:1648.5-1648.49" wire \main_sdblock2mem_wishbonedmawriter_length_re - attribute \src "ls180.v:1736.12-1736.61" + attribute \src "ls180.v:1647.12-1647.61" wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage - attribute \src "ls180.v:1743.5-1743.47" + attribute \src "ls180.v:1654.5-1654.47" wire \main_sdblock2mem_wishbonedmawriter_loop_re - attribute \src "ls180.v:1742.5-1742.52" + attribute \src "ls180.v:1653.5-1653.52" wire \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:1745.12-1745.53" + attribute \src "ls180.v:1656.12-1656.53" wire width 32 \main_sdblock2mem_wishbonedmawriter_offset - attribute \src "ls180.v:1965.12-1965.79" + attribute \src "ls180.v:1876.12-1876.79" wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - attribute \src "ls180.v:1966.5-1966.75" + attribute \src "ls180.v:1877.5-1877.75" wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:1747.6-1747.46" + attribute \src "ls180.v:1658.6-1658.46" wire \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:1731.6-1731.51" + attribute \src "ls180.v:1642.6-1642.51" wire \main_sdblock2mem_wishbonedmawriter_sink_first - attribute \src "ls180.v:1732.6-1732.50" + attribute \src "ls180.v:1643.6-1643.50" wire \main_sdblock2mem_wishbonedmawriter_sink_last - attribute \src "ls180.v:1733.13-1733.65" + attribute \src "ls180.v:1644.13-1644.65" wire width 64 \main_sdblock2mem_wishbonedmawriter_sink_payload_data - attribute \src "ls180.v:1730.5-1730.50" + attribute \src "ls180.v:1641.5-1641.50" wire \main_sdblock2mem_wishbonedmawriter_sink_ready - attribute \src "ls180.v:1729.6-1729.51" + attribute \src "ls180.v:1640.6-1640.51" wire \main_sdblock2mem_wishbonedmawriter_sink_valid - attribute \src "ls180.v:1740.5-1740.46" + attribute \src "ls180.v:1651.5-1651.46" wire \main_sdblock2mem_wishbonedmawriter_status - attribute \src "ls180.v:1741.6-1741.43" + attribute \src "ls180.v:1652.6-1652.43" wire \main_sdblock2mem_wishbonedmawriter_we - attribute \src "ls180.v:1509.5-1509.31" + attribute \src "ls180.v:1420.5-1420.31" wire \main_sdcore_block_count_re - attribute \src "ls180.v:1508.12-1508.43" + attribute \src "ls180.v:1419.12-1419.43" wire width 32 \main_sdcore_block_count_storage - attribute \src "ls180.v:1507.5-1507.32" + attribute \src "ls180.v:1418.5-1418.32" wire \main_sdcore_block_length_re - attribute \src "ls180.v:1506.11-1506.43" + attribute \src "ls180.v:1417.11-1417.43" wire width 10 \main_sdcore_block_length_storage - attribute \src "ls180.v:1493.5-1493.32" + attribute \src "ls180.v:1404.5-1404.32" wire \main_sdcore_cmd_argument_re - attribute \src "ls180.v:1492.12-1492.44" + attribute \src "ls180.v:1403.12-1403.44" wire width 32 \main_sdcore_cmd_argument_storage - attribute \src "ls180.v:1495.5-1495.31" + attribute \src "ls180.v:1406.5-1406.31" wire \main_sdcore_cmd_command_re - attribute \src "ls180.v:1494.12-1494.43" + attribute \src "ls180.v:1405.12-1405.43" wire width 32 \main_sdcore_cmd_command_storage - attribute \src "ls180.v:1648.11-1648.32" + attribute \src "ls180.v:1559.11-1559.32" wire width 3 \main_sdcore_cmd_count - attribute \src "ls180.v:1949.11-1949.55" + attribute \src "ls180.v:1860.11-1860.55" wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 - attribute \src "ls180.v:1950.5-1950.52" + attribute \src "ls180.v:1861.5-1861.52" wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:1649.5-1649.25" + attribute \src "ls180.v:1560.5-1560.25" wire \main_sdcore_cmd_done - attribute \src "ls180.v:1945.5-1945.48" + attribute \src "ls180.v:1856.5-1856.48" wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 - attribute \src "ls180.v:1946.5-1946.51" + attribute \src "ls180.v:1857.5-1857.51" wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:1650.5-1650.26" + attribute \src "ls180.v:1561.5-1561.26" wire \main_sdcore_cmd_error - attribute \src "ls180.v:1953.5-1953.49" + attribute \src "ls180.v:1864.5-1864.49" wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 - attribute \src "ls180.v:1954.5-1954.52" + attribute \src "ls180.v:1865.5-1865.52" wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:1502.12-1502.40" + attribute \src "ls180.v:1413.12-1413.40" wire width 4 \main_sdcore_cmd_event_status - attribute \src "ls180.v:1503.6-1503.30" + attribute \src "ls180.v:1414.6-1414.30" wire \main_sdcore_cmd_event_we - attribute \src "ls180.v:1500.13-1500.44" + attribute \src "ls180.v:1411.13-1411.44" wire width 128 \main_sdcore_cmd_response_status - attribute \src "ls180.v:1961.13-1961.67" + attribute \src "ls180.v:1872.13-1872.67" wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 - attribute \src "ls180.v:1962.5-1962.62" + attribute \src "ls180.v:1873.5-1873.62" wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:1501.6-1501.33" + attribute \src "ls180.v:1412.6-1412.33" wire \main_sdcore_cmd_response_we - attribute \src "ls180.v:1497.6-1497.28" + attribute \src "ls180.v:1408.6-1408.28" wire \main_sdcore_cmd_send_r - attribute \src "ls180.v:1496.6-1496.29" + attribute \src "ls180.v:1407.6-1407.29" wire \main_sdcore_cmd_send_re - attribute \src "ls180.v:1499.5-1499.27" + attribute \src "ls180.v:1410.5-1410.27" wire \main_sdcore_cmd_send_w - attribute \src "ls180.v:1498.6-1498.29" + attribute \src "ls180.v:1409.6-1409.29" wire \main_sdcore_cmd_send_we - attribute \src "ls180.v:1651.5-1651.28" + attribute \src "ls180.v:1562.5-1562.28" wire \main_sdcore_cmd_timeout - attribute \src "ls180.v:1955.5-1955.51" + attribute \src "ls180.v:1866.5-1866.51" wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 - attribute \src "ls180.v:1956.5-1956.54" + attribute \src "ls180.v:1867.5-1867.54" wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:1647.12-1647.32" + attribute \src "ls180.v:1558.12-1558.32" wire width 2 \main_sdcore_cmd_type - attribute \src "ls180.v:1609.11-1609.40" + attribute \src "ls180.v:1520.11-1520.40" wire width 4 \main_sdcore_crc16_checker_cnt - attribute \src "ls180.v:1615.5-1615.39" + attribute \src "ls180.v:1526.5-1526.39" wire \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:1614.12-1614.46" + attribute \src "ls180.v:1525.12-1525.46" wire width 16 \main_sdcore_crc16_checker_crc0_crc - attribute \src "ls180.v:1610.12-1610.50" + attribute \src "ls180.v:1521.12-1521.50" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 - attribute \src "ls180.v:1611.13-1611.51" + attribute \src "ls180.v:1522.13-1522.51" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 - attribute \src "ls180.v:1612.13-1612.51" + attribute \src "ls180.v:1523.13-1523.51" wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:1616.6-1616.43" + attribute \src "ls180.v:1527.6-1527.43" wire \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:1613.12-1613.46" + attribute \src "ls180.v:1524.12-1524.46" wire width 2 \main_sdcore_crc16_checker_crc0_val - attribute \src "ls180.v:1622.5-1622.39" + attribute \src "ls180.v:1533.5-1533.39" wire \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:1621.12-1621.46" + attribute \src "ls180.v:1532.12-1532.46" wire width 16 \main_sdcore_crc16_checker_crc1_crc - attribute \src "ls180.v:1617.12-1617.50" + attribute \src "ls180.v:1528.12-1528.50" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 - attribute \src "ls180.v:1618.13-1618.51" + attribute \src "ls180.v:1529.13-1529.51" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 - attribute \src "ls180.v:1619.13-1619.51" + attribute \src "ls180.v:1530.13-1530.51" wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:1623.6-1623.43" + attribute \src "ls180.v:1534.6-1534.43" wire \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:1620.12-1620.46" + attribute \src "ls180.v:1531.12-1531.46" wire width 2 \main_sdcore_crc16_checker_crc1_val - attribute \src "ls180.v:1629.5-1629.39" + attribute \src "ls180.v:1540.5-1540.39" wire \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:1628.12-1628.46" + attribute \src "ls180.v:1539.12-1539.46" wire width 16 \main_sdcore_crc16_checker_crc2_crc - attribute \src "ls180.v:1624.12-1624.50" + attribute \src "ls180.v:1535.12-1535.50" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 - attribute \src "ls180.v:1625.13-1625.51" + attribute \src "ls180.v:1536.13-1536.51" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 - attribute \src "ls180.v:1626.13-1626.51" + attribute \src "ls180.v:1537.13-1537.51" wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:1630.6-1630.43" + attribute \src "ls180.v:1541.6-1541.43" wire \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:1627.12-1627.46" + attribute \src "ls180.v:1538.12-1538.46" wire width 2 \main_sdcore_crc16_checker_crc2_val - attribute \src "ls180.v:1636.5-1636.39" + attribute \src "ls180.v:1547.5-1547.39" wire \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:1635.12-1635.46" + attribute \src "ls180.v:1546.12-1546.46" wire width 16 \main_sdcore_crc16_checker_crc3_crc - attribute \src "ls180.v:1631.12-1631.50" + attribute \src "ls180.v:1542.12-1542.50" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 - attribute \src "ls180.v:1632.13-1632.51" + attribute \src "ls180.v:1543.13-1543.51" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 - attribute \src "ls180.v:1633.13-1633.51" + attribute \src "ls180.v:1544.13-1544.51" wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:1637.6-1637.43" + attribute \src "ls180.v:1548.6-1548.43" wire \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:1634.12-1634.46" + attribute \src "ls180.v:1545.12-1545.46" wire width 2 \main_sdcore_crc16_checker_crc3_val - attribute \src "ls180.v:1638.12-1638.45" + attribute \src "ls180.v:1549.12-1549.45" wire width 16 \main_sdcore_crc16_checker_crctmp0 - attribute \src "ls180.v:1639.12-1639.45" + attribute \src "ls180.v:1550.12-1550.45" wire width 16 \main_sdcore_crc16_checker_crctmp1 - attribute \src "ls180.v:1640.12-1640.45" + attribute \src "ls180.v:1551.12-1551.45" wire width 16 \main_sdcore_crc16_checker_crctmp2 - attribute \src "ls180.v:1641.12-1641.45" + attribute \src "ls180.v:1552.12-1552.45" wire width 16 \main_sdcore_crc16_checker_crctmp3 - attribute \src "ls180.v:1643.12-1643.43" + attribute \src "ls180.v:1554.12-1554.43" wire width 16 \main_sdcore_crc16_checker_fifo0 - attribute \src "ls180.v:1644.12-1644.43" + attribute \src "ls180.v:1555.12-1555.43" wire width 16 \main_sdcore_crc16_checker_fifo1 - attribute \src "ls180.v:1645.12-1645.43" + attribute \src "ls180.v:1556.12-1556.43" wire width 16 \main_sdcore_crc16_checker_fifo2 - attribute \src "ls180.v:1646.12-1646.43" + attribute \src "ls180.v:1557.12-1557.43" wire width 16 \main_sdcore_crc16_checker_fifo3 - attribute \src "ls180.v:1600.5-1600.41" + attribute \src "ls180.v:1511.5-1511.41" wire \main_sdcore_crc16_checker_sink_first - attribute \src "ls180.v:1601.5-1601.40" + attribute \src "ls180.v:1512.5-1512.40" wire \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:1602.11-1602.54" + attribute \src "ls180.v:1513.11-1513.54" wire width 8 \main_sdcore_crc16_checker_sink_payload_data - attribute \src "ls180.v:1599.5-1599.41" + attribute \src "ls180.v:1510.5-1510.41" wire \main_sdcore_crc16_checker_sink_ready - attribute \src "ls180.v:1598.5-1598.41" + attribute \src "ls180.v:1509.5-1509.41" wire \main_sdcore_crc16_checker_sink_valid - attribute \src "ls180.v:1605.5-1605.43" + attribute \src "ls180.v:1516.5-1516.43" wire \main_sdcore_crc16_checker_source_first - attribute \src "ls180.v:1606.6-1606.43" + attribute \src "ls180.v:1517.6-1517.43" wire \main_sdcore_crc16_checker_source_last - attribute \src "ls180.v:1607.12-1607.57" + attribute \src "ls180.v:1518.12-1518.57" wire width 8 \main_sdcore_crc16_checker_source_payload_data - attribute \src "ls180.v:1604.6-1604.44" + attribute \src "ls180.v:1515.6-1515.44" wire \main_sdcore_crc16_checker_source_ready - attribute \src "ls180.v:1603.5-1603.43" + attribute \src "ls180.v:1514.5-1514.43" wire \main_sdcore_crc16_checker_source_valid - attribute \src "ls180.v:1608.11-1608.40" + attribute \src "ls180.v:1519.11-1519.40" wire width 8 \main_sdcore_crc16_checker_val - attribute \src "ls180.v:1642.5-1642.36" + attribute \src "ls180.v:1553.5-1553.36" wire \main_sdcore_crc16_checker_valid - attribute \src "ls180.v:1565.11-1565.41" + attribute \src "ls180.v:1476.11-1476.41" wire width 3 \main_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:1941.11-1941.80" + attribute \src "ls180.v:1852.11-1852.80" wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - attribute \src "ls180.v:1942.5-1942.77" + attribute \src "ls180.v:1853.5-1853.77" wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:1571.6-1571.41" + attribute \src "ls180.v:1482.6-1482.41" wire \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:1570.12-1570.47" + attribute \src "ls180.v:1481.12-1481.47" wire width 16 \main_sdcore_crc16_inserter_crc0_crc - attribute \src "ls180.v:1566.12-1566.51" + attribute \src "ls180.v:1477.12-1477.51" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 - attribute \src "ls180.v:1567.13-1567.52" + attribute \src "ls180.v:1478.13-1478.52" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 - attribute \src "ls180.v:1568.13-1568.52" + attribute \src "ls180.v:1479.13-1479.52" wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:1572.6-1572.44" + attribute \src "ls180.v:1483.6-1483.44" wire \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:1569.12-1569.47" + attribute \src "ls180.v:1480.12-1480.47" wire width 2 \main_sdcore_crc16_inserter_crc0_val - attribute \src "ls180.v:1578.6-1578.41" + attribute \src "ls180.v:1489.6-1489.41" wire \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:1577.12-1577.47" + attribute \src "ls180.v:1488.12-1488.47" wire width 16 \main_sdcore_crc16_inserter_crc1_crc - attribute \src "ls180.v:1573.12-1573.51" + attribute \src "ls180.v:1484.12-1484.51" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 - attribute \src "ls180.v:1574.13-1574.52" + attribute \src "ls180.v:1485.13-1485.52" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 - attribute \src "ls180.v:1575.13-1575.52" + attribute \src "ls180.v:1486.13-1486.52" wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:1579.6-1579.44" + attribute \src "ls180.v:1490.6-1490.44" wire \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:1576.12-1576.47" + attribute \src "ls180.v:1487.12-1487.47" wire width 2 \main_sdcore_crc16_inserter_crc1_val - attribute \src "ls180.v:1585.6-1585.41" + attribute \src "ls180.v:1496.6-1496.41" wire \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:1584.12-1584.47" + attribute \src "ls180.v:1495.12-1495.47" wire width 16 \main_sdcore_crc16_inserter_crc2_crc - attribute \src "ls180.v:1580.12-1580.51" + attribute \src "ls180.v:1491.12-1491.51" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 - attribute \src "ls180.v:1581.13-1581.52" + attribute \src "ls180.v:1492.13-1492.52" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 - attribute \src "ls180.v:1582.13-1582.52" + attribute \src "ls180.v:1493.13-1493.52" wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:1586.6-1586.44" + attribute \src "ls180.v:1497.6-1497.44" wire \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:1583.12-1583.47" + attribute \src "ls180.v:1494.12-1494.47" wire width 2 \main_sdcore_crc16_inserter_crc2_val - attribute \src "ls180.v:1592.6-1592.41" + attribute \src "ls180.v:1503.6-1503.41" wire \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:1591.12-1591.47" + attribute \src "ls180.v:1502.12-1502.47" wire width 16 \main_sdcore_crc16_inserter_crc3_crc - attribute \src "ls180.v:1587.12-1587.51" + attribute \src "ls180.v:1498.12-1498.51" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 - attribute \src "ls180.v:1588.13-1588.52" + attribute \src "ls180.v:1499.13-1499.52" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 - attribute \src "ls180.v:1589.13-1589.52" + attribute \src "ls180.v:1500.13-1500.52" wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:1593.6-1593.44" + attribute \src "ls180.v:1504.6-1504.44" wire \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:1590.12-1590.47" + attribute \src "ls180.v:1501.12-1501.47" wire width 2 \main_sdcore_crc16_inserter_crc3_val - attribute \src "ls180.v:1594.12-1594.46" + attribute \src "ls180.v:1505.12-1505.46" wire width 16 \main_sdcore_crc16_inserter_crctmp0 - attribute \src "ls180.v:1933.12-1933.85" + attribute \src "ls180.v:1844.12-1844.85" wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - attribute \src "ls180.v:1934.5-1934.81" + attribute \src "ls180.v:1845.5-1845.81" wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:1595.12-1595.46" + attribute \src "ls180.v:1506.12-1506.46" wire width 16 \main_sdcore_crc16_inserter_crctmp1 - attribute \src "ls180.v:1935.12-1935.85" + attribute \src "ls180.v:1846.12-1846.85" wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - attribute \src "ls180.v:1936.5-1936.81" + attribute \src "ls180.v:1847.5-1847.81" wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:1596.12-1596.46" + attribute \src "ls180.v:1507.12-1507.46" wire width 16 \main_sdcore_crc16_inserter_crctmp2 - attribute \src "ls180.v:1937.12-1937.85" + attribute \src "ls180.v:1848.12-1848.85" wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - attribute \src "ls180.v:1938.5-1938.81" + attribute \src "ls180.v:1849.5-1849.81" wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:1597.12-1597.46" + attribute \src "ls180.v:1508.12-1508.46" wire width 16 \main_sdcore_crc16_inserter_crctmp3 - attribute \src "ls180.v:1939.12-1939.85" + attribute \src "ls180.v:1850.12-1850.85" wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - attribute \src "ls180.v:1940.5-1940.81" + attribute \src "ls180.v:1851.5-1851.81" wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:1557.6-1557.43" + attribute \src "ls180.v:1468.6-1468.43" wire \main_sdcore_crc16_inserter_sink_first - attribute \src "ls180.v:1558.6-1558.42" + attribute \src "ls180.v:1469.6-1469.42" wire \main_sdcore_crc16_inserter_sink_last - attribute \src "ls180.v:1559.12-1559.56" + attribute \src "ls180.v:1470.12-1470.56" wire width 8 \main_sdcore_crc16_inserter_sink_payload_data - attribute \src "ls180.v:1556.5-1556.42" + attribute \src "ls180.v:1467.5-1467.42" wire \main_sdcore_crc16_inserter_sink_ready - attribute \src "ls180.v:1555.6-1555.43" + attribute \src "ls180.v:1466.6-1466.43" wire \main_sdcore_crc16_inserter_sink_valid - attribute \src "ls180.v:1562.5-1562.44" + attribute \src "ls180.v:1473.5-1473.44" wire \main_sdcore_crc16_inserter_source_first - attribute \src "ls180.v:1563.5-1563.43" + attribute \src "ls180.v:1474.5-1474.43" wire \main_sdcore_crc16_inserter_source_last - attribute \src "ls180.v:1564.11-1564.57" + attribute \src "ls180.v:1475.11-1475.57" wire width 8 \main_sdcore_crc16_inserter_source_payload_data - attribute \src "ls180.v:1561.5-1561.44" + attribute \src "ls180.v:1472.5-1472.44" wire \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:1560.5-1560.44" + attribute \src "ls180.v:1471.5-1471.44" wire \main_sdcore_crc16_inserter_source_valid - attribute \src "ls180.v:1553.6-1553.35" + attribute \src "ls180.v:1464.6-1464.35" wire \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:1552.11-1552.40" + attribute \src "ls180.v:1463.11-1463.40" wire width 7 \main_sdcore_crc7_inserter_crc - attribute \src "ls180.v:1510.11-1510.44" + attribute \src "ls180.v:1421.11-1421.44" wire width 7 \main_sdcore_crc7_inserter_crcreg0 - attribute \src "ls180.v:1511.12-1511.45" + attribute \src "ls180.v:1422.12-1422.45" wire width 7 \main_sdcore_crc7_inserter_crcreg1 - attribute \src "ls180.v:1520.12-1520.46" + attribute \src "ls180.v:1431.12-1431.46" wire width 7 \main_sdcore_crc7_inserter_crcreg10 - attribute \src "ls180.v:1521.12-1521.46" + attribute \src "ls180.v:1432.12-1432.46" wire width 7 \main_sdcore_crc7_inserter_crcreg11 - attribute \src "ls180.v:1522.12-1522.46" + attribute \src "ls180.v:1433.12-1433.46" wire width 7 \main_sdcore_crc7_inserter_crcreg12 - attribute \src "ls180.v:1523.12-1523.46" + attribute \src "ls180.v:1434.12-1434.46" wire width 7 \main_sdcore_crc7_inserter_crcreg13 - attribute \src "ls180.v:1524.12-1524.46" + attribute \src "ls180.v:1435.12-1435.46" wire width 7 \main_sdcore_crc7_inserter_crcreg14 - attribute \src "ls180.v:1525.12-1525.46" + attribute \src "ls180.v:1436.12-1436.46" wire width 7 \main_sdcore_crc7_inserter_crcreg15 - attribute \src "ls180.v:1526.12-1526.46" + attribute \src "ls180.v:1437.12-1437.46" wire width 7 \main_sdcore_crc7_inserter_crcreg16 - attribute \src "ls180.v:1527.12-1527.46" + attribute \src "ls180.v:1438.12-1438.46" wire width 7 \main_sdcore_crc7_inserter_crcreg17 - attribute \src "ls180.v:1528.12-1528.46" + attribute \src "ls180.v:1439.12-1439.46" wire width 7 \main_sdcore_crc7_inserter_crcreg18 - attribute \src "ls180.v:1529.12-1529.46" + attribute \src "ls180.v:1440.12-1440.46" wire width 7 \main_sdcore_crc7_inserter_crcreg19 - attribute \src "ls180.v:1512.12-1512.45" + attribute \src "ls180.v:1423.12-1423.45" wire width 7 \main_sdcore_crc7_inserter_crcreg2 - attribute \src "ls180.v:1530.12-1530.46" + attribute \src "ls180.v:1441.12-1441.46" wire width 7 \main_sdcore_crc7_inserter_crcreg20 - attribute \src "ls180.v:1531.12-1531.46" + attribute \src "ls180.v:1442.12-1442.46" wire width 7 \main_sdcore_crc7_inserter_crcreg21 - attribute \src "ls180.v:1532.12-1532.46" + attribute \src "ls180.v:1443.12-1443.46" wire width 7 \main_sdcore_crc7_inserter_crcreg22 - attribute \src "ls180.v:1533.12-1533.46" + attribute \src "ls180.v:1444.12-1444.46" wire width 7 \main_sdcore_crc7_inserter_crcreg23 - attribute \src "ls180.v:1534.12-1534.46" + attribute \src "ls180.v:1445.12-1445.46" wire width 7 \main_sdcore_crc7_inserter_crcreg24 - attribute \src "ls180.v:1535.12-1535.46" + attribute \src "ls180.v:1446.12-1446.46" wire width 7 \main_sdcore_crc7_inserter_crcreg25 - attribute \src "ls180.v:1536.12-1536.46" + attribute \src "ls180.v:1447.12-1447.46" wire width 7 \main_sdcore_crc7_inserter_crcreg26 - attribute \src "ls180.v:1537.12-1537.46" + attribute \src "ls180.v:1448.12-1448.46" wire width 7 \main_sdcore_crc7_inserter_crcreg27 - attribute \src "ls180.v:1538.12-1538.46" + attribute \src "ls180.v:1449.12-1449.46" wire width 7 \main_sdcore_crc7_inserter_crcreg28 - attribute \src "ls180.v:1539.12-1539.46" + attribute \src "ls180.v:1450.12-1450.46" wire width 7 \main_sdcore_crc7_inserter_crcreg29 - attribute \src "ls180.v:1513.12-1513.45" + attribute \src "ls180.v:1424.12-1424.45" wire width 7 \main_sdcore_crc7_inserter_crcreg3 - attribute \src "ls180.v:1540.12-1540.46" + attribute \src "ls180.v:1451.12-1451.46" wire width 7 \main_sdcore_crc7_inserter_crcreg30 - attribute \src "ls180.v:1541.12-1541.46" + attribute \src "ls180.v:1452.12-1452.46" wire width 7 \main_sdcore_crc7_inserter_crcreg31 - attribute \src "ls180.v:1542.12-1542.46" + attribute \src "ls180.v:1453.12-1453.46" wire width 7 \main_sdcore_crc7_inserter_crcreg32 - attribute \src "ls180.v:1543.12-1543.46" + attribute \src "ls180.v:1454.12-1454.46" wire width 7 \main_sdcore_crc7_inserter_crcreg33 - attribute \src "ls180.v:1544.12-1544.46" + attribute \src "ls180.v:1455.12-1455.46" wire width 7 \main_sdcore_crc7_inserter_crcreg34 - attribute \src "ls180.v:1545.12-1545.46" + attribute \src "ls180.v:1456.12-1456.46" wire width 7 \main_sdcore_crc7_inserter_crcreg35 - attribute \src "ls180.v:1546.12-1546.46" + attribute \src "ls180.v:1457.12-1457.46" wire width 7 \main_sdcore_crc7_inserter_crcreg36 - attribute \src "ls180.v:1547.12-1547.46" + attribute \src "ls180.v:1458.12-1458.46" wire width 7 \main_sdcore_crc7_inserter_crcreg37 - attribute \src "ls180.v:1548.12-1548.46" + attribute \src "ls180.v:1459.12-1459.46" wire width 7 \main_sdcore_crc7_inserter_crcreg38 - attribute \src "ls180.v:1549.12-1549.46" + attribute \src "ls180.v:1460.12-1460.46" wire width 7 \main_sdcore_crc7_inserter_crcreg39 - attribute \src "ls180.v:1514.12-1514.45" + attribute \src "ls180.v:1425.12-1425.45" wire width 7 \main_sdcore_crc7_inserter_crcreg4 - attribute \src "ls180.v:1550.12-1550.46" + attribute \src "ls180.v:1461.12-1461.46" wire width 7 \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:1515.12-1515.45" + attribute \src "ls180.v:1426.12-1426.45" wire width 7 \main_sdcore_crc7_inserter_crcreg5 - attribute \src "ls180.v:1516.12-1516.45" + attribute \src "ls180.v:1427.12-1427.45" wire width 7 \main_sdcore_crc7_inserter_crcreg6 - attribute \src "ls180.v:1517.12-1517.45" + attribute \src "ls180.v:1428.12-1428.45" wire width 7 \main_sdcore_crc7_inserter_crcreg7 - attribute \src "ls180.v:1518.12-1518.45" + attribute \src "ls180.v:1429.12-1429.45" wire width 7 \main_sdcore_crc7_inserter_crcreg8 - attribute \src "ls180.v:1519.12-1519.45" + attribute \src "ls180.v:1430.12-1430.45" wire width 7 \main_sdcore_crc7_inserter_crcreg9 - attribute \src "ls180.v:1554.6-1554.38" + attribute \src "ls180.v:1465.6-1465.38" wire \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:1551.13-1551.42" + attribute \src "ls180.v:1462.13-1462.42" wire width 40 \main_sdcore_crc7_inserter_val - attribute \src "ls180.v:1653.12-1653.34" + attribute \src "ls180.v:1564.12-1564.34" wire width 32 \main_sdcore_data_count - attribute \src "ls180.v:1951.12-1951.57" + attribute \src "ls180.v:1862.12-1862.57" wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 - attribute \src "ls180.v:1952.5-1952.53" + attribute \src "ls180.v:1863.5-1863.53" wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:1654.5-1654.26" + attribute \src "ls180.v:1565.5-1565.26" wire \main_sdcore_data_done - attribute \src "ls180.v:1947.5-1947.49" + attribute \src "ls180.v:1858.5-1858.49" wire \main_sdcore_data_done_sdcore_fsm_next_value1 - attribute \src "ls180.v:1948.5-1948.52" + attribute \src "ls180.v:1859.5-1859.52" wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:1655.5-1655.27" + attribute \src "ls180.v:1566.5-1566.27" wire \main_sdcore_data_error - attribute \src "ls180.v:1957.5-1957.50" + attribute \src "ls180.v:1868.5-1868.50" wire \main_sdcore_data_error_sdcore_fsm_next_value6 - attribute \src "ls180.v:1958.5-1958.53" + attribute \src "ls180.v:1869.5-1869.53" wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:1504.12-1504.41" + attribute \src "ls180.v:1415.12-1415.41" wire width 4 \main_sdcore_data_event_status - attribute \src "ls180.v:1505.6-1505.31" + attribute \src "ls180.v:1416.6-1416.31" wire \main_sdcore_data_event_we - attribute \src "ls180.v:1656.5-1656.29" + attribute \src "ls180.v:1567.5-1567.29" wire \main_sdcore_data_timeout - attribute \src "ls180.v:1959.5-1959.52" + attribute \src "ls180.v:1870.5-1870.52" wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 - attribute \src "ls180.v:1960.5-1960.55" + attribute \src "ls180.v:1871.5-1871.55" wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:1652.12-1652.33" + attribute \src "ls180.v:1563.12-1563.33" wire width 2 \main_sdcore_data_type - attribute \src "ls180.v:1484.6-1484.33" + attribute \src "ls180.v:1395.6-1395.33" wire \main_sdcore_sink_sink_first - attribute \src "ls180.v:1485.6-1485.32" + attribute \src "ls180.v:1396.6-1396.32" wire \main_sdcore_sink_sink_last - attribute \src "ls180.v:1486.12-1486.46" + attribute \src "ls180.v:1397.12-1397.46" wire width 8 \main_sdcore_sink_sink_payload_data - attribute \src "ls180.v:1483.6-1483.33" + attribute \src "ls180.v:1394.6-1394.33" wire \main_sdcore_sink_sink_ready - attribute \src "ls180.v:1482.6-1482.33" + attribute \src "ls180.v:1393.6-1393.33" wire \main_sdcore_sink_sink_valid - attribute \src "ls180.v:1489.6-1489.37" + attribute \src "ls180.v:1400.6-1400.37" wire \main_sdcore_source_source_first - attribute \src "ls180.v:1490.6-1490.36" + attribute \src "ls180.v:1401.6-1401.36" wire \main_sdcore_source_source_last - attribute \src "ls180.v:1491.12-1491.50" + attribute \src "ls180.v:1402.12-1402.50" wire width 8 \main_sdcore_source_source_payload_data - attribute \src "ls180.v:1488.6-1488.37" + attribute \src "ls180.v:1399.6-1399.37" wire \main_sdcore_source_source_ready - attribute \src "ls180.v:1487.6-1487.37" + attribute \src "ls180.v:1398.6-1398.37" wire \main_sdcore_source_source_valid - attribute \src "ls180.v:1802.6-1802.38" + attribute \src "ls180.v:1713.6-1713.38" wire \main_sdmem2block_converter_first - attribute \src "ls180.v:1803.6-1803.37" + attribute \src "ls180.v:1714.6-1714.37" wire \main_sdmem2block_converter_last - attribute \src "ls180.v:1801.11-1801.41" + attribute \src "ls180.v:1712.11-1712.41" wire width 3 \main_sdmem2block_converter_mux - attribute \src "ls180.v:1792.6-1792.43" + attribute \src "ls180.v:1703.6-1703.43" wire \main_sdmem2block_converter_sink_first - attribute \src "ls180.v:1793.6-1793.42" + attribute \src "ls180.v:1704.6-1704.42" wire \main_sdmem2block_converter_sink_last - attribute \src "ls180.v:1794.13-1794.57" + attribute \src "ls180.v:1705.13-1705.57" wire width 64 \main_sdmem2block_converter_sink_payload_data - attribute \src "ls180.v:1791.6-1791.43" + attribute \src "ls180.v:1702.6-1702.43" wire \main_sdmem2block_converter_sink_ready - attribute \src "ls180.v:1790.6-1790.43" + attribute \src "ls180.v:1701.6-1701.43" wire \main_sdmem2block_converter_sink_valid - attribute \src "ls180.v:1797.6-1797.45" + attribute \src "ls180.v:1708.6-1708.45" wire \main_sdmem2block_converter_source_first - attribute \src "ls180.v:1798.6-1798.44" + attribute \src "ls180.v:1709.6-1709.44" wire \main_sdmem2block_converter_source_last - attribute \src "ls180.v:1799.11-1799.57" + attribute \src "ls180.v:1710.11-1710.57" wire width 8 \main_sdmem2block_converter_source_payload_data - attribute \src "ls180.v:1800.6-1800.65" + attribute \src "ls180.v:1711.6-1711.65" wire \main_sdmem2block_converter_source_payload_valid_token_count - attribute \src "ls180.v:1796.6-1796.45" + attribute \src "ls180.v:1707.6-1707.45" wire \main_sdmem2block_converter_source_ready - attribute \src "ls180.v:1795.6-1795.45" + attribute \src "ls180.v:1706.6-1706.45" wire \main_sdmem2block_converter_source_valid - attribute \src "ls180.v:1786.13-1786.38" + attribute \src "ls180.v:1697.13-1697.38" wire width 32 \main_sdmem2block_dma_base - attribute \src "ls180.v:1775.5-1775.33" + attribute \src "ls180.v:1686.5-1686.33" wire \main_sdmem2block_dma_base_re - attribute \src "ls180.v:1774.12-1774.45" + attribute \src "ls180.v:1685.12-1685.45" wire width 64 \main_sdmem2block_dma_base_storage - attribute \src "ls180.v:1773.12-1773.37" + attribute \src "ls180.v:1684.12-1684.37" wire width 64 \main_sdmem2block_dma_data - attribute \src "ls180.v:1969.12-1969.67" + attribute \src "ls180.v:1880.12-1880.67" wire width 64 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - attribute \src "ls180.v:1970.5-1970.63" + attribute \src "ls180.v:1881.5-1881.63" wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:1780.5-1780.37" + attribute \src "ls180.v:1691.5-1691.37" wire \main_sdmem2block_dma_done_status - attribute \src "ls180.v:1781.6-1781.34" + attribute \src "ls180.v:1692.6-1692.34" wire \main_sdmem2block_dma_done_we - attribute \src "ls180.v:1779.5-1779.35" + attribute \src "ls180.v:1690.5-1690.35" wire \main_sdmem2block_dma_enable_re - attribute \src "ls180.v:1778.5-1778.40" + attribute \src "ls180.v:1689.5-1689.40" wire \main_sdmem2block_dma_enable_storage - attribute \src "ls180.v:1788.13-1788.40" + attribute \src "ls180.v:1699.13-1699.40" wire width 32 \main_sdmem2block_dma_length - attribute \src "ls180.v:1777.5-1777.35" + attribute \src "ls180.v:1688.5-1688.35" wire \main_sdmem2block_dma_length_re - attribute \src "ls180.v:1776.12-1776.47" + attribute \src "ls180.v:1687.12-1687.47" wire width 32 \main_sdmem2block_dma_length_storage - attribute \src "ls180.v:1783.5-1783.33" + attribute \src "ls180.v:1694.5-1694.33" wire \main_sdmem2block_dma_loop_re - attribute \src "ls180.v:1782.5-1782.38" + attribute \src "ls180.v:1693.5-1693.38" wire \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:1787.12-1787.39" + attribute \src "ls180.v:1698.12-1698.39" wire width 32 \main_sdmem2block_dma_offset - attribute \src "ls180.v:1973.12-1973.79" + attribute \src "ls180.v:1884.12-1884.79" wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - attribute \src "ls180.v:1974.5-1974.75" + attribute \src "ls180.v:1885.5-1885.75" wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:1784.13-1784.47" + attribute \src "ls180.v:1695.13-1695.47" wire width 32 \main_sdmem2block_dma_offset_status - attribute \src "ls180.v:1785.6-1785.36" + attribute \src "ls180.v:1696.6-1696.36" wire \main_sdmem2block_dma_offset_we - attribute \src "ls180.v:1789.6-1789.32" + attribute \src "ls180.v:1700.6-1700.32" wire \main_sdmem2block_dma_reset - attribute \src "ls180.v:1766.5-1766.35" + attribute \src "ls180.v:1677.5-1677.35" wire \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:1767.12-1767.53" + attribute \src "ls180.v:1678.12-1678.53" wire width 32 \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:1765.5-1765.36" + attribute \src "ls180.v:1676.5-1676.36" wire \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:1764.5-1764.36" + attribute \src "ls180.v:1675.5-1675.36" wire \main_sdmem2block_dma_sink_valid - attribute \src "ls180.v:1770.5-1770.38" + attribute \src "ls180.v:1681.5-1681.38" wire \main_sdmem2block_dma_source_first - attribute \src "ls180.v:1771.5-1771.37" + attribute \src "ls180.v:1682.5-1682.37" wire \main_sdmem2block_dma_source_last - attribute \src "ls180.v:1772.12-1772.52" + attribute \src "ls180.v:1683.12-1683.52" wire width 64 \main_sdmem2block_dma_source_payload_data - attribute \src "ls180.v:1769.6-1769.39" + attribute \src "ls180.v:1680.6-1680.39" wire \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:1768.5-1768.38" + attribute \src "ls180.v:1679.5-1679.38" wire \main_sdmem2block_dma_source_valid - attribute \src "ls180.v:1828.11-1828.40" + attribute \src "ls180.v:1739.11-1739.40" wire width 5 \main_sdmem2block_fifo_consume - attribute \src "ls180.v:1833.6-1833.35" + attribute \src "ls180.v:1744.6-1744.35" wire \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:1837.6-1837.41" + attribute \src "ls180.v:1748.6-1748.41" wire \main_sdmem2block_fifo_fifo_in_first - attribute \src "ls180.v:1838.6-1838.40" + attribute \src "ls180.v:1749.6-1749.40" wire \main_sdmem2block_fifo_fifo_in_last - attribute \src "ls180.v:1836.12-1836.54" + attribute \src "ls180.v:1747.12-1747.54" wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data - attribute \src "ls180.v:1840.6-1840.42" + attribute \src "ls180.v:1751.6-1751.42" wire \main_sdmem2block_fifo_fifo_out_first - attribute \src "ls180.v:1841.6-1841.41" + attribute \src "ls180.v:1752.6-1752.41" wire \main_sdmem2block_fifo_fifo_out_last - attribute \src "ls180.v:1839.12-1839.55" + attribute \src "ls180.v:1750.12-1750.55" wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data - attribute \src "ls180.v:1825.11-1825.38" + attribute \src "ls180.v:1736.11-1736.38" wire width 6 \main_sdmem2block_fifo_level - attribute \src "ls180.v:1827.11-1827.40" + attribute \src "ls180.v:1738.11-1738.40" wire width 5 \main_sdmem2block_fifo_produce - attribute \src "ls180.v:1834.12-1834.44" + attribute \src "ls180.v:1745.12-1745.44" wire width 5 \main_sdmem2block_fifo_rdport_adr - attribute \src "ls180.v:1835.12-1835.46" + attribute \src "ls180.v:1746.12-1746.46" wire width 10 \main_sdmem2block_fifo_rdport_dat_r - attribute \src "ls180.v:1826.5-1826.34" + attribute \src "ls180.v:1737.5-1737.34" wire \main_sdmem2block_fifo_replace - attribute \src "ls180.v:1811.6-1811.38" + attribute \src "ls180.v:1722.6-1722.38" wire \main_sdmem2block_fifo_sink_first - attribute \src "ls180.v:1812.6-1812.37" + attribute \src "ls180.v:1723.6-1723.37" wire \main_sdmem2block_fifo_sink_last - attribute \src "ls180.v:1813.12-1813.51" + attribute \src "ls180.v:1724.12-1724.51" wire width 8 \main_sdmem2block_fifo_sink_payload_data - attribute \src "ls180.v:1810.6-1810.38" + attribute \src "ls180.v:1721.6-1721.38" wire \main_sdmem2block_fifo_sink_ready - attribute \src "ls180.v:1809.6-1809.38" + attribute \src "ls180.v:1720.6-1720.38" wire \main_sdmem2block_fifo_sink_valid - attribute \src "ls180.v:1816.6-1816.40" + attribute \src "ls180.v:1727.6-1727.40" wire \main_sdmem2block_fifo_source_first - attribute \src "ls180.v:1817.6-1817.39" + attribute \src "ls180.v:1728.6-1728.39" wire \main_sdmem2block_fifo_source_last - attribute \src "ls180.v:1818.12-1818.53" + attribute \src "ls180.v:1729.12-1729.53" wire width 8 \main_sdmem2block_fifo_source_payload_data - attribute \src "ls180.v:1815.6-1815.40" + attribute \src "ls180.v:1726.6-1726.40" wire \main_sdmem2block_fifo_source_ready - attribute \src "ls180.v:1814.6-1814.40" + attribute \src "ls180.v:1725.6-1725.40" wire \main_sdmem2block_fifo_source_valid - attribute \src "ls180.v:1823.12-1823.46" + attribute \src "ls180.v:1734.12-1734.46" wire width 10 \main_sdmem2block_fifo_syncfifo_din - attribute \src "ls180.v:1824.12-1824.47" + attribute \src "ls180.v:1735.12-1735.47" wire width 10 \main_sdmem2block_fifo_syncfifo_dout - attribute \src "ls180.v:1821.6-1821.39" + attribute \src "ls180.v:1732.6-1732.39" wire \main_sdmem2block_fifo_syncfifo_re - attribute \src "ls180.v:1822.6-1822.45" + attribute \src "ls180.v:1733.6-1733.45" wire \main_sdmem2block_fifo_syncfifo_readable - attribute \src "ls180.v:1819.6-1819.39" + attribute \src "ls180.v:1730.6-1730.39" wire \main_sdmem2block_fifo_syncfifo_we - attribute \src "ls180.v:1820.6-1820.45" + attribute \src "ls180.v:1731.6-1731.45" wire \main_sdmem2block_fifo_syncfifo_writable - attribute \src "ls180.v:1829.11-1829.43" + attribute \src "ls180.v:1740.11-1740.43" wire width 5 \main_sdmem2block_fifo_wrport_adr - attribute \src "ls180.v:1830.12-1830.46" + attribute \src "ls180.v:1741.12-1741.46" wire width 10 \main_sdmem2block_fifo_wrport_dat_r - attribute \src "ls180.v:1832.12-1832.46" + attribute \src "ls180.v:1743.12-1743.46" wire width 10 \main_sdmem2block_fifo_wrport_dat_w - attribute \src "ls180.v:1831.6-1831.37" + attribute \src "ls180.v:1742.6-1742.37" wire \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:1761.6-1761.43" + attribute \src "ls180.v:1672.6-1672.43" wire \main_sdmem2block_source_source_first0 - attribute \src "ls180.v:1806.6-1806.43" + attribute \src "ls180.v:1717.6-1717.43" wire \main_sdmem2block_source_source_first1 - attribute \src "ls180.v:1762.6-1762.42" + attribute \src "ls180.v:1673.6-1673.42" wire \main_sdmem2block_source_source_last0 - attribute \src "ls180.v:1807.6-1807.42" + attribute \src "ls180.v:1718.6-1718.42" wire \main_sdmem2block_source_source_last1 - attribute \src "ls180.v:1763.12-1763.56" + attribute \src "ls180.v:1674.12-1674.56" wire width 8 \main_sdmem2block_source_source_payload_data0 - attribute \src "ls180.v:1808.12-1808.56" + attribute \src "ls180.v:1719.12-1719.56" wire width 8 \main_sdmem2block_source_source_payload_data1 - attribute \src "ls180.v:1760.6-1760.43" + attribute \src "ls180.v:1671.6-1671.43" wire \main_sdmem2block_source_source_ready0 - attribute \src "ls180.v:1805.6-1805.43" + attribute \src "ls180.v:1716.6-1716.43" wire \main_sdmem2block_source_source_ready1 - attribute \src "ls180.v:1759.6-1759.43" + attribute \src "ls180.v:1670.6-1670.43" wire \main_sdmem2block_source_source_valid0 - attribute \src "ls180.v:1804.6-1804.43" + attribute \src "ls180.v:1715.6-1715.43" wire \main_sdmem2block_source_source_valid1 - attribute \src "ls180.v:1210.6-1210.27" + attribute \src "ls180.v:1121.6-1121.27" wire \main_sdphy_clocker_ce - attribute \src "ls180.v:1209.5-1209.28" + attribute \src "ls180.v:1120.5-1120.28" wire \main_sdphy_clocker_clk0 - attribute \src "ls180.v:1212.5-1212.28" + attribute \src "ls180.v:1123.5-1123.28" wire \main_sdphy_clocker_clk1 - attribute \src "ls180.v:1213.5-1213.29" + attribute \src "ls180.v:1124.5-1124.29" wire \main_sdphy_clocker_clk_d - attribute \src "ls180.v:1211.11-1211.34" + attribute \src "ls180.v:1122.11-1122.34" wire width 9 \main_sdphy_clocker_clks - attribute \src "ls180.v:1207.5-1207.26" + attribute \src "ls180.v:1118.5-1118.26" wire \main_sdphy_clocker_re - attribute \src "ls180.v:1208.6-1208.29" + attribute \src "ls180.v:1119.6-1119.29" wire \main_sdphy_clocker_stop - attribute \src "ls180.v:1206.11-1206.37" + attribute \src "ls180.v:1117.11-1117.37" wire width 9 \main_sdphy_clocker_storage - attribute \src "ls180.v:1310.6-1310.41" + attribute \src "ls180.v:1221.6-1221.41" wire \main_sdphy_cmdr_cmdr_buf_sink_first - attribute \src "ls180.v:1311.6-1311.40" + attribute \src "ls180.v:1222.6-1222.40" wire \main_sdphy_cmdr_cmdr_buf_sink_last - attribute \src "ls180.v:1312.12-1312.54" + attribute \src "ls180.v:1223.12-1223.54" wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data - attribute \src "ls180.v:1309.6-1309.41" + attribute \src "ls180.v:1220.6-1220.41" wire \main_sdphy_cmdr_cmdr_buf_sink_ready - attribute \src "ls180.v:1308.6-1308.41" + attribute \src "ls180.v:1219.6-1219.41" wire \main_sdphy_cmdr_cmdr_buf_sink_valid - attribute \src "ls180.v:1315.5-1315.42" + attribute \src "ls180.v:1226.5-1226.42" wire \main_sdphy_cmdr_cmdr_buf_source_first - attribute \src "ls180.v:1316.5-1316.41" + attribute \src "ls180.v:1227.5-1227.41" wire \main_sdphy_cmdr_cmdr_buf_source_last - attribute \src "ls180.v:1317.11-1317.55" + attribute \src "ls180.v:1228.11-1228.55" wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data - attribute \src "ls180.v:1314.6-1314.43" + attribute \src "ls180.v:1225.6-1225.43" wire \main_sdphy_cmdr_cmdr_buf_source_ready - attribute \src "ls180.v:1313.5-1313.42" + attribute \src "ls180.v:1224.5-1224.42" wire \main_sdphy_cmdr_cmdr_buf_source_valid - attribute \src "ls180.v:1300.11-1300.47" + attribute \src "ls180.v:1211.11-1211.47" wire width 3 \main_sdphy_cmdr_cmdr_converter_demux - attribute \src "ls180.v:1301.6-1301.46" + attribute \src "ls180.v:1212.6-1212.46" wire \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:1291.5-1291.46" + attribute \src "ls180.v:1202.5-1202.46" wire \main_sdphy_cmdr_cmdr_converter_sink_first - attribute \src "ls180.v:1292.5-1292.45" + attribute \src "ls180.v:1203.5-1203.45" wire \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:1293.6-1293.54" + attribute \src "ls180.v:1204.6-1204.54" wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:1290.6-1290.47" + attribute \src "ls180.v:1201.6-1201.47" wire \main_sdphy_cmdr_cmdr_converter_sink_ready - attribute \src "ls180.v:1289.6-1289.47" + attribute \src "ls180.v:1200.6-1200.47" wire \main_sdphy_cmdr_cmdr_converter_sink_valid - attribute \src "ls180.v:1296.5-1296.48" + attribute \src "ls180.v:1207.5-1207.48" wire \main_sdphy_cmdr_cmdr_converter_source_first - attribute \src "ls180.v:1297.5-1297.47" + attribute \src "ls180.v:1208.5-1208.47" wire \main_sdphy_cmdr_cmdr_converter_source_last - attribute \src "ls180.v:1298.11-1298.61" + attribute \src "ls180.v:1209.11-1209.61" wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data - attribute \src "ls180.v:1299.11-1299.74" + attribute \src "ls180.v:1210.11-1210.74" wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1295.6-1295.49" + attribute \src "ls180.v:1206.6-1206.49" wire \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:1294.6-1294.49" + attribute \src "ls180.v:1205.6-1205.49" wire \main_sdphy_cmdr_cmdr_converter_source_valid - attribute \src "ls180.v:1302.5-1302.46" + attribute \src "ls180.v:1213.5-1213.46" wire \main_sdphy_cmdr_cmdr_converter_strobe_all - attribute \src "ls180.v:1273.6-1273.40" + attribute \src "ls180.v:1184.6-1184.40" wire \main_sdphy_cmdr_cmdr_pads_in_first - attribute \src "ls180.v:1274.6-1274.39" + attribute \src "ls180.v:1185.6-1185.39" wire \main_sdphy_cmdr_cmdr_pads_in_last - attribute \src "ls180.v:1275.6-1275.46" + attribute \src "ls180.v:1186.6-1186.46" wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk - attribute \src "ls180.v:1276.6-1276.48" + attribute \src "ls180.v:1187.6-1187.48" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - attribute \src "ls180.v:1277.6-1277.48" + attribute \src "ls180.v:1188.6-1188.48" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o - attribute \src "ls180.v:1278.6-1278.49" + attribute \src "ls180.v:1189.6-1189.49" wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1279.12-1279.55" + attribute \src "ls180.v:1190.12-1190.55" wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i - attribute \src "ls180.v:1280.12-1280.55" + attribute \src "ls180.v:1191.12-1191.55" wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o - attribute \src "ls180.v:1281.6-1281.50" + attribute \src "ls180.v:1192.6-1192.50" wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe - attribute \src "ls180.v:1272.5-1272.39" + attribute \src "ls180.v:1183.5-1183.39" wire \main_sdphy_cmdr_cmdr_pads_in_ready - attribute \src "ls180.v:1271.6-1271.40" + attribute \src "ls180.v:1182.6-1182.40" wire \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:1318.5-1318.31" + attribute \src "ls180.v:1229.5-1229.31" wire \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:1913.5-1913.59" + attribute \src "ls180.v:1824.5-1824.59" wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - attribute \src "ls180.v:1914.5-1914.62" + attribute \src "ls180.v:1825.5-1825.62" wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:1288.5-1288.29" + attribute \src "ls180.v:1199.5-1199.29" wire \main_sdphy_cmdr_cmdr_run - attribute \src "ls180.v:1284.6-1284.47" + attribute \src "ls180.v:1195.6-1195.47" wire \main_sdphy_cmdr_cmdr_source_source_first0 - attribute \src "ls180.v:1305.6-1305.47" + attribute \src "ls180.v:1216.6-1216.47" wire \main_sdphy_cmdr_cmdr_source_source_first1 - attribute \src "ls180.v:1285.6-1285.46" + attribute \src "ls180.v:1196.6-1196.46" wire \main_sdphy_cmdr_cmdr_source_source_last0 - attribute \src "ls180.v:1306.6-1306.46" + attribute \src "ls180.v:1217.6-1217.46" wire \main_sdphy_cmdr_cmdr_source_source_last1 - attribute \src "ls180.v:1286.12-1286.60" + attribute \src "ls180.v:1197.12-1197.60" wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 - attribute \src "ls180.v:1307.12-1307.60" + attribute \src "ls180.v:1218.12-1218.60" wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 - attribute \src "ls180.v:1283.5-1283.46" + attribute \src "ls180.v:1194.5-1194.46" wire \main_sdphy_cmdr_cmdr_source_source_ready0 - attribute \src "ls180.v:1304.6-1304.47" + attribute \src "ls180.v:1215.6-1215.47" wire \main_sdphy_cmdr_cmdr_source_source_ready1 - attribute \src "ls180.v:1282.6-1282.47" + attribute \src "ls180.v:1193.6-1193.47" wire \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:1303.6-1303.47" + attribute \src "ls180.v:1214.6-1214.47" wire \main_sdphy_cmdr_cmdr_source_source_valid1 - attribute \src "ls180.v:1287.6-1287.32" + attribute \src "ls180.v:1198.6-1198.32" wire \main_sdphy_cmdr_cmdr_start - attribute \src "ls180.v:1270.11-1270.32" + attribute \src "ls180.v:1181.11-1181.32" wire width 8 \main_sdphy_cmdr_count - attribute \src "ls180.v:1909.11-1909.60" + attribute \src "ls180.v:1820.11-1820.60" wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 - attribute \src "ls180.v:1910.5-1910.57" + attribute \src "ls180.v:1821.5-1821.57" wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:1245.5-1245.42" + attribute \src "ls180.v:1156.5-1156.42" wire \main_sdphy_cmdr_pads_in_pads_in_first - attribute \src "ls180.v:1246.5-1246.41" + attribute \src "ls180.v:1157.5-1157.41" wire \main_sdphy_cmdr_pads_in_pads_in_last - attribute \src "ls180.v:1247.5-1247.48" + attribute \src "ls180.v:1158.5-1158.48" wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1248.6-1248.51" + attribute \src "ls180.v:1159.6-1159.51" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1249.5-1249.50" + attribute \src "ls180.v:1160.5-1160.50" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1250.5-1250.51" + attribute \src "ls180.v:1161.5-1161.51" wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1251.12-1251.58" + attribute \src "ls180.v:1162.12-1162.58" wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1252.11-1252.57" + attribute \src "ls180.v:1163.11-1163.57" wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1253.5-1253.52" + attribute \src "ls180.v:1164.5-1164.52" wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1244.6-1244.43" + attribute \src "ls180.v:1155.6-1155.43" wire \main_sdphy_cmdr_pads_in_pads_in_ready - attribute \src "ls180.v:1243.6-1243.43" + attribute \src "ls180.v:1154.6-1154.43" wire \main_sdphy_cmdr_pads_in_pads_in_valid - attribute \src "ls180.v:1255.5-1255.41" + attribute \src "ls180.v:1166.5-1166.41" wire \main_sdphy_cmdr_pads_out_payload_clk - attribute \src "ls180.v:1256.5-1256.43" + attribute \src "ls180.v:1167.5-1167.43" wire \main_sdphy_cmdr_pads_out_payload_cmd_o - attribute \src "ls180.v:1257.5-1257.44" + attribute \src "ls180.v:1168.5-1168.44" wire \main_sdphy_cmdr_pads_out_payload_cmd_oe - attribute \src "ls180.v:1258.11-1258.50" + attribute \src "ls180.v:1169.11-1169.50" wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o - attribute \src "ls180.v:1259.5-1259.45" + attribute \src "ls180.v:1170.5-1170.45" wire \main_sdphy_cmdr_pads_out_payload_data_oe - attribute \src "ls180.v:1254.6-1254.36" + attribute \src "ls180.v:1165.6-1165.36" wire \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:1262.5-1262.30" + attribute \src "ls180.v:1173.5-1173.30" wire \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:1263.11-1263.46" + attribute \src "ls180.v:1174.11-1174.46" wire width 8 \main_sdphy_cmdr_sink_payload_length - attribute \src "ls180.v:1261.5-1261.31" + attribute \src "ls180.v:1172.5-1172.31" wire \main_sdphy_cmdr_sink_ready - attribute \src "ls180.v:1260.5-1260.31" + attribute \src "ls180.v:1171.5-1171.31" wire \main_sdphy_cmdr_sink_valid - attribute \src "ls180.v:1266.5-1266.32" + attribute \src "ls180.v:1177.5-1177.32" wire \main_sdphy_cmdr_source_last - attribute \src "ls180.v:1267.11-1267.46" + attribute \src "ls180.v:1178.11-1178.46" wire width 8 \main_sdphy_cmdr_source_payload_data - attribute \src "ls180.v:1268.11-1268.48" + attribute \src "ls180.v:1179.11-1179.48" wire width 3 \main_sdphy_cmdr_source_payload_status - attribute \src "ls180.v:1265.5-1265.33" + attribute \src "ls180.v:1176.5-1176.33" wire \main_sdphy_cmdr_source_ready - attribute \src "ls180.v:1264.5-1264.33" + attribute \src "ls180.v:1175.5-1175.33" wire \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:1269.12-1269.35" + attribute \src "ls180.v:1180.12-1180.35" wire width 32 \main_sdphy_cmdr_timeout - attribute \src "ls180.v:1911.12-1911.63" + attribute \src "ls180.v:1822.12-1822.63" wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 - attribute \src "ls180.v:1912.5-1912.59" + attribute \src "ls180.v:1823.5-1823.59" wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:1242.11-1242.32" + attribute \src "ls180.v:1153.11-1153.32" wire width 8 \main_sdphy_cmdw_count - attribute \src "ls180.v:1905.11-1905.59" + attribute \src "ls180.v:1816.11-1816.59" wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value - attribute \src "ls180.v:1906.5-1906.56" + attribute \src "ls180.v:1817.5-1817.56" wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:1241.5-1241.25" + attribute \src "ls180.v:1152.5-1152.25" wire \main_sdphy_cmdw_done - attribute \src "ls180.v:1229.6-1229.43" + attribute \src "ls180.v:1140.6-1140.43" wire \main_sdphy_cmdw_pads_in_payload_cmd_i - attribute \src "ls180.v:1230.12-1230.50" + attribute \src "ls180.v:1141.12-1141.50" wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i - attribute \src "ls180.v:1228.6-1228.35" + attribute \src "ls180.v:1139.6-1139.35" wire \main_sdphy_cmdw_pads_in_valid - attribute \src "ls180.v:1232.5-1232.41" + attribute \src "ls180.v:1143.5-1143.41" wire \main_sdphy_cmdw_pads_out_payload_clk - attribute \src "ls180.v:1233.5-1233.43" + attribute \src "ls180.v:1144.5-1144.43" wire \main_sdphy_cmdw_pads_out_payload_cmd_o - attribute \src "ls180.v:1234.5-1234.44" + attribute \src "ls180.v:1145.5-1145.44" wire \main_sdphy_cmdw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1235.11-1235.50" + attribute \src "ls180.v:1146.11-1146.50" wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o - attribute \src "ls180.v:1236.5-1236.45" + attribute \src "ls180.v:1147.5-1147.45" wire \main_sdphy_cmdw_pads_out_payload_data_oe - attribute \src "ls180.v:1231.6-1231.36" + attribute \src "ls180.v:1142.6-1142.36" wire \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:1239.5-1239.30" + attribute \src "ls180.v:1150.5-1150.30" wire \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:1240.11-1240.44" + attribute \src "ls180.v:1151.11-1151.44" wire width 8 \main_sdphy_cmdw_sink_payload_data - attribute \src "ls180.v:1238.5-1238.31" + attribute \src "ls180.v:1149.5-1149.31" wire \main_sdphy_cmdw_sink_ready - attribute \src "ls180.v:1237.5-1237.31" + attribute \src "ls180.v:1148.5-1148.31" wire \main_sdphy_cmdw_sink_valid - attribute \src "ls180.v:1426.11-1426.33" + attribute \src "ls180.v:1337.11-1337.33" wire width 10 \main_sdphy_datar_count - attribute \src "ls180.v:1925.11-1925.62" + attribute \src "ls180.v:1836.11-1836.62" wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 - attribute \src "ls180.v:1926.5-1926.59" + attribute \src "ls180.v:1837.5-1837.59" wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:1466.6-1466.43" + attribute \src "ls180.v:1377.6-1377.43" wire \main_sdphy_datar_datar_buf_sink_first - attribute \src "ls180.v:1467.6-1467.42" + attribute \src "ls180.v:1378.6-1378.42" wire \main_sdphy_datar_datar_buf_sink_last - attribute \src "ls180.v:1468.12-1468.56" + attribute \src "ls180.v:1379.12-1379.56" wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data - attribute \src "ls180.v:1465.6-1465.43" + attribute \src "ls180.v:1376.6-1376.43" wire \main_sdphy_datar_datar_buf_sink_ready - attribute \src "ls180.v:1464.6-1464.43" + attribute \src "ls180.v:1375.6-1375.43" wire \main_sdphy_datar_datar_buf_sink_valid - attribute \src "ls180.v:1471.5-1471.44" + attribute \src "ls180.v:1382.5-1382.44" wire \main_sdphy_datar_datar_buf_source_first - attribute \src "ls180.v:1472.5-1472.43" + attribute \src "ls180.v:1383.5-1383.43" wire \main_sdphy_datar_datar_buf_source_last - attribute \src "ls180.v:1473.11-1473.57" + attribute \src "ls180.v:1384.11-1384.57" wire width 8 \main_sdphy_datar_datar_buf_source_payload_data - attribute \src "ls180.v:1470.6-1470.45" + attribute \src "ls180.v:1381.6-1381.45" wire \main_sdphy_datar_datar_buf_source_ready - attribute \src "ls180.v:1469.5-1469.44" + attribute \src "ls180.v:1380.5-1380.44" wire \main_sdphy_datar_datar_buf_source_valid - attribute \src "ls180.v:1456.5-1456.43" + attribute \src "ls180.v:1367.5-1367.43" wire \main_sdphy_datar_datar_converter_demux - attribute \src "ls180.v:1457.6-1457.48" + attribute \src "ls180.v:1368.6-1368.48" wire \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:1447.5-1447.48" + attribute \src "ls180.v:1358.5-1358.48" wire \main_sdphy_datar_datar_converter_sink_first - attribute \src "ls180.v:1448.5-1448.47" + attribute \src "ls180.v:1359.5-1359.47" wire \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:1449.12-1449.62" + attribute \src "ls180.v:1360.12-1360.62" wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:1446.6-1446.49" + attribute \src "ls180.v:1357.6-1357.49" wire \main_sdphy_datar_datar_converter_sink_ready - attribute \src "ls180.v:1445.6-1445.49" + attribute \src "ls180.v:1356.6-1356.49" wire \main_sdphy_datar_datar_converter_sink_valid - attribute \src "ls180.v:1452.5-1452.50" + attribute \src "ls180.v:1363.5-1363.50" wire \main_sdphy_datar_datar_converter_source_first - attribute \src "ls180.v:1453.5-1453.49" + attribute \src "ls180.v:1364.5-1364.49" wire \main_sdphy_datar_datar_converter_source_last - attribute \src "ls180.v:1454.11-1454.63" + attribute \src "ls180.v:1365.11-1365.63" wire width 8 \main_sdphy_datar_datar_converter_source_payload_data - attribute \src "ls180.v:1455.11-1455.76" + attribute \src "ls180.v:1366.11-1366.76" wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count - attribute \src "ls180.v:1451.6-1451.51" + attribute \src "ls180.v:1362.6-1362.51" wire \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:1450.6-1450.51" + attribute \src "ls180.v:1361.6-1361.51" wire \main_sdphy_datar_datar_converter_source_valid - attribute \src "ls180.v:1458.5-1458.48" + attribute \src "ls180.v:1369.5-1369.48" wire \main_sdphy_datar_datar_converter_strobe_all - attribute \src "ls180.v:1429.6-1429.42" + attribute \src "ls180.v:1340.6-1340.42" wire \main_sdphy_datar_datar_pads_in_first - attribute \src "ls180.v:1430.6-1430.41" + attribute \src "ls180.v:1341.6-1341.41" wire \main_sdphy_datar_datar_pads_in_last - attribute \src "ls180.v:1431.6-1431.48" + attribute \src "ls180.v:1342.6-1342.48" wire \main_sdphy_datar_datar_pads_in_payload_clk - attribute \src "ls180.v:1432.6-1432.50" + attribute \src "ls180.v:1343.6-1343.50" wire \main_sdphy_datar_datar_pads_in_payload_cmd_i - attribute \src "ls180.v:1433.6-1433.50" + attribute \src "ls180.v:1344.6-1344.50" wire \main_sdphy_datar_datar_pads_in_payload_cmd_o - attribute \src "ls180.v:1434.6-1434.51" + attribute \src "ls180.v:1345.6-1345.51" wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe - attribute \src "ls180.v:1435.12-1435.57" + attribute \src "ls180.v:1346.12-1346.57" wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i - attribute \src "ls180.v:1436.12-1436.57" + attribute \src "ls180.v:1347.12-1347.57" wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o - attribute \src "ls180.v:1437.6-1437.52" + attribute \src "ls180.v:1348.6-1348.52" wire \main_sdphy_datar_datar_pads_in_payload_data_oe - attribute \src "ls180.v:1428.5-1428.41" + attribute \src "ls180.v:1339.5-1339.41" wire \main_sdphy_datar_datar_pads_in_ready - attribute \src "ls180.v:1427.6-1427.42" + attribute \src "ls180.v:1338.6-1338.42" wire \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:1474.5-1474.33" + attribute \src "ls180.v:1385.5-1385.33" wire \main_sdphy_datar_datar_reset - attribute \src "ls180.v:1929.5-1929.62" + attribute \src "ls180.v:1840.5-1840.62" wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 - attribute \src "ls180.v:1930.5-1930.65" + attribute \src "ls180.v:1841.5-1841.65" wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:1444.5-1444.31" + attribute \src "ls180.v:1355.5-1355.31" wire \main_sdphy_datar_datar_run - attribute \src "ls180.v:1440.6-1440.49" + attribute \src "ls180.v:1351.6-1351.49" wire \main_sdphy_datar_datar_source_source_first0 - attribute \src "ls180.v:1461.6-1461.49" + attribute \src "ls180.v:1372.6-1372.49" wire \main_sdphy_datar_datar_source_source_first1 - attribute \src "ls180.v:1441.6-1441.48" + attribute \src "ls180.v:1352.6-1352.48" wire \main_sdphy_datar_datar_source_source_last0 - attribute \src "ls180.v:1462.6-1462.48" + attribute \src "ls180.v:1373.6-1373.48" wire \main_sdphy_datar_datar_source_source_last1 - attribute \src "ls180.v:1442.12-1442.62" + attribute \src "ls180.v:1353.12-1353.62" wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 - attribute \src "ls180.v:1463.12-1463.62" + attribute \src "ls180.v:1374.12-1374.62" wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 - attribute \src "ls180.v:1439.5-1439.48" + attribute \src "ls180.v:1350.5-1350.48" wire \main_sdphy_datar_datar_source_source_ready0 - attribute \src "ls180.v:1460.6-1460.49" + attribute \src "ls180.v:1371.6-1371.49" wire \main_sdphy_datar_datar_source_source_ready1 - attribute \src "ls180.v:1438.6-1438.49" + attribute \src "ls180.v:1349.6-1349.49" wire \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:1459.6-1459.49" + attribute \src "ls180.v:1370.6-1370.49" wire \main_sdphy_datar_datar_source_source_valid1 - attribute \src "ls180.v:1443.6-1443.34" + attribute \src "ls180.v:1354.6-1354.34" wire \main_sdphy_datar_datar_start - attribute \src "ls180.v:1399.5-1399.43" + attribute \src "ls180.v:1310.5-1310.43" wire \main_sdphy_datar_pads_in_pads_in_first - attribute \src "ls180.v:1400.5-1400.42" + attribute \src "ls180.v:1311.5-1311.42" wire \main_sdphy_datar_pads_in_pads_in_last - attribute \src "ls180.v:1401.5-1401.49" + attribute \src "ls180.v:1312.5-1312.49" wire \main_sdphy_datar_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1402.6-1402.52" + attribute \src "ls180.v:1313.6-1313.52" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1403.5-1403.51" + attribute \src "ls180.v:1314.5-1314.51" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1404.5-1404.52" + attribute \src "ls180.v:1315.5-1315.52" wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1405.12-1405.59" + attribute \src "ls180.v:1316.12-1316.59" wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1406.11-1406.58" + attribute \src "ls180.v:1317.11-1317.58" wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1407.5-1407.53" + attribute \src "ls180.v:1318.5-1318.53" wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1398.6-1398.44" + attribute \src "ls180.v:1309.6-1309.44" wire \main_sdphy_datar_pads_in_pads_in_ready - attribute \src "ls180.v:1397.6-1397.44" + attribute \src "ls180.v:1308.6-1308.44" wire \main_sdphy_datar_pads_in_pads_in_valid - attribute \src "ls180.v:1409.5-1409.42" + attribute \src "ls180.v:1320.5-1320.42" wire \main_sdphy_datar_pads_out_payload_clk - attribute \src "ls180.v:1410.5-1410.44" + attribute \src "ls180.v:1321.5-1321.44" wire \main_sdphy_datar_pads_out_payload_cmd_o - attribute \src "ls180.v:1411.5-1411.45" + attribute \src "ls180.v:1322.5-1322.45" wire \main_sdphy_datar_pads_out_payload_cmd_oe - attribute \src "ls180.v:1412.11-1412.51" + attribute \src "ls180.v:1323.11-1323.51" wire width 4 \main_sdphy_datar_pads_out_payload_data_o - attribute \src "ls180.v:1413.5-1413.46" + attribute \src "ls180.v:1324.5-1324.46" wire \main_sdphy_datar_pads_out_payload_data_oe - attribute \src "ls180.v:1408.6-1408.37" + attribute \src "ls180.v:1319.6-1319.37" wire \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:1416.5-1416.31" + attribute \src "ls180.v:1327.5-1327.31" wire \main_sdphy_datar_sink_last - attribute \src "ls180.v:1417.11-1417.53" + attribute \src "ls180.v:1328.11-1328.53" wire width 10 \main_sdphy_datar_sink_payload_block_length - attribute \src "ls180.v:1415.5-1415.32" + attribute \src "ls180.v:1326.5-1326.32" wire \main_sdphy_datar_sink_ready - attribute \src "ls180.v:1414.5-1414.32" + attribute \src "ls180.v:1325.5-1325.32" wire \main_sdphy_datar_sink_valid - attribute \src "ls180.v:1420.5-1420.34" + attribute \src "ls180.v:1331.5-1331.34" wire \main_sdphy_datar_source_first - attribute \src "ls180.v:1421.5-1421.33" + attribute \src "ls180.v:1332.5-1332.33" wire \main_sdphy_datar_source_last - attribute \src "ls180.v:1422.11-1422.47" + attribute \src "ls180.v:1333.11-1333.47" wire width 8 \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:1423.11-1423.49" + attribute \src "ls180.v:1334.11-1334.49" wire width 3 \main_sdphy_datar_source_payload_status - attribute \src "ls180.v:1419.5-1419.34" + attribute \src "ls180.v:1330.5-1330.34" wire \main_sdphy_datar_source_ready - attribute \src "ls180.v:1418.5-1418.34" + attribute \src "ls180.v:1329.5-1329.34" wire \main_sdphy_datar_source_valid - attribute \src "ls180.v:1424.5-1424.26" + attribute \src "ls180.v:1335.5-1335.26" wire \main_sdphy_datar_stop - attribute \src "ls180.v:1425.12-1425.36" + attribute \src "ls180.v:1336.12-1336.36" wire width 32 \main_sdphy_datar_timeout - attribute \src "ls180.v:1927.12-1927.65" + attribute \src "ls180.v:1838.12-1838.65" wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 - attribute \src "ls180.v:1928.5-1928.61" + attribute \src "ls180.v:1839.5-1839.61" wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:1334.11-1334.33" + attribute \src "ls180.v:1245.11-1245.33" wire width 8 \main_sdphy_dataw_count - attribute \src "ls180.v:1921.11-1921.54" + attribute \src "ls180.v:1832.11-1832.54" wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value - attribute \src "ls180.v:1922.5-1922.51" + attribute \src "ls180.v:1833.5-1833.51" wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:1388.6-1388.42" + attribute \src "ls180.v:1299.6-1299.42" wire \main_sdphy_dataw_crcr_buf_sink_first - attribute \src "ls180.v:1389.6-1389.41" + attribute \src "ls180.v:1300.6-1300.41" wire \main_sdphy_dataw_crcr_buf_sink_last - attribute \src "ls180.v:1390.12-1390.55" + attribute \src "ls180.v:1301.12-1301.55" wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data - attribute \src "ls180.v:1387.6-1387.42" + attribute \src "ls180.v:1298.6-1298.42" wire \main_sdphy_dataw_crcr_buf_sink_ready - attribute \src "ls180.v:1386.6-1386.42" + attribute \src "ls180.v:1297.6-1297.42" wire \main_sdphy_dataw_crcr_buf_sink_valid - attribute \src "ls180.v:1393.5-1393.43" + attribute \src "ls180.v:1304.5-1304.43" wire \main_sdphy_dataw_crcr_buf_source_first - attribute \src "ls180.v:1394.5-1394.42" + attribute \src "ls180.v:1305.5-1305.42" wire \main_sdphy_dataw_crcr_buf_source_last - attribute \src "ls180.v:1395.11-1395.56" + attribute \src "ls180.v:1306.11-1306.56" wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data - attribute \src "ls180.v:1392.6-1392.44" + attribute \src "ls180.v:1303.6-1303.44" wire \main_sdphy_dataw_crcr_buf_source_ready - attribute \src "ls180.v:1391.5-1391.43" + attribute \src "ls180.v:1302.5-1302.43" wire \main_sdphy_dataw_crcr_buf_source_valid - attribute \src "ls180.v:1378.11-1378.48" + attribute \src "ls180.v:1289.11-1289.48" wire width 3 \main_sdphy_dataw_crcr_converter_demux - attribute \src "ls180.v:1379.6-1379.47" + attribute \src "ls180.v:1290.6-1290.47" wire \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:1369.5-1369.47" + attribute \src "ls180.v:1280.5-1280.47" wire \main_sdphy_dataw_crcr_converter_sink_first - attribute \src "ls180.v:1370.5-1370.46" + attribute \src "ls180.v:1281.5-1281.46" wire \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:1371.6-1371.55" + attribute \src "ls180.v:1282.6-1282.55" wire \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:1368.6-1368.48" + attribute \src "ls180.v:1279.6-1279.48" wire \main_sdphy_dataw_crcr_converter_sink_ready - attribute \src "ls180.v:1367.6-1367.48" + attribute \src "ls180.v:1278.6-1278.48" wire \main_sdphy_dataw_crcr_converter_sink_valid - attribute \src "ls180.v:1374.5-1374.49" + attribute \src "ls180.v:1285.5-1285.49" wire \main_sdphy_dataw_crcr_converter_source_first - attribute \src "ls180.v:1375.5-1375.48" + attribute \src "ls180.v:1286.5-1286.48" wire \main_sdphy_dataw_crcr_converter_source_last - attribute \src "ls180.v:1376.11-1376.62" + attribute \src "ls180.v:1287.11-1287.62" wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data - attribute \src "ls180.v:1377.11-1377.75" + attribute \src "ls180.v:1288.11-1288.75" wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1373.6-1373.50" + attribute \src "ls180.v:1284.6-1284.50" wire \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:1372.6-1372.50" + attribute \src "ls180.v:1283.6-1283.50" wire \main_sdphy_dataw_crcr_converter_source_valid - attribute \src "ls180.v:1380.5-1380.47" + attribute \src "ls180.v:1291.5-1291.47" wire \main_sdphy_dataw_crcr_converter_strobe_all - attribute \src "ls180.v:1351.6-1351.41" + attribute \src "ls180.v:1262.6-1262.41" wire \main_sdphy_dataw_crcr_pads_in_first - attribute \src "ls180.v:1352.6-1352.40" + attribute \src "ls180.v:1263.6-1263.40" wire \main_sdphy_dataw_crcr_pads_in_last - attribute \src "ls180.v:1353.6-1353.47" + attribute \src "ls180.v:1264.6-1264.47" wire \main_sdphy_dataw_crcr_pads_in_payload_clk - attribute \src "ls180.v:1354.6-1354.49" + attribute \src "ls180.v:1265.6-1265.49" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i - attribute \src "ls180.v:1355.6-1355.49" + attribute \src "ls180.v:1266.6-1266.49" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o - attribute \src "ls180.v:1356.6-1356.50" + attribute \src "ls180.v:1267.6-1267.50" wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1357.12-1357.56" + attribute \src "ls180.v:1268.12-1268.56" wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i - attribute \src "ls180.v:1358.12-1358.56" + attribute \src "ls180.v:1269.12-1269.56" wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o - attribute \src "ls180.v:1359.6-1359.51" + attribute \src "ls180.v:1270.6-1270.51" wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe - attribute \src "ls180.v:1350.5-1350.40" + attribute \src "ls180.v:1261.5-1261.40" wire \main_sdphy_dataw_crcr_pads_in_ready - attribute \src "ls180.v:1349.6-1349.41" + attribute \src "ls180.v:1260.6-1260.41" wire \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:1396.5-1396.32" + attribute \src "ls180.v:1307.5-1307.32" wire \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:1917.5-1917.59" + attribute \src "ls180.v:1828.5-1828.59" wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value - attribute \src "ls180.v:1918.5-1918.62" + attribute \src "ls180.v:1829.5-1829.62" wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:1366.5-1366.30" + attribute \src "ls180.v:1277.5-1277.30" wire \main_sdphy_dataw_crcr_run - attribute \src "ls180.v:1362.6-1362.48" + attribute \src "ls180.v:1273.6-1273.48" wire \main_sdphy_dataw_crcr_source_source_first0 - attribute \src "ls180.v:1383.6-1383.48" + attribute \src "ls180.v:1294.6-1294.48" wire \main_sdphy_dataw_crcr_source_source_first1 - attribute \src "ls180.v:1363.6-1363.47" + attribute \src "ls180.v:1274.6-1274.47" wire \main_sdphy_dataw_crcr_source_source_last0 - attribute \src "ls180.v:1384.6-1384.47" + attribute \src "ls180.v:1295.6-1295.47" wire \main_sdphy_dataw_crcr_source_source_last1 - attribute \src "ls180.v:1364.12-1364.61" + attribute \src "ls180.v:1275.12-1275.61" wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 - attribute \src "ls180.v:1385.12-1385.61" + attribute \src "ls180.v:1296.12-1296.61" wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 - attribute \src "ls180.v:1361.5-1361.47" + attribute \src "ls180.v:1272.5-1272.47" wire \main_sdphy_dataw_crcr_source_source_ready0 - attribute \src "ls180.v:1382.6-1382.48" + attribute \src "ls180.v:1293.6-1293.48" wire \main_sdphy_dataw_crcr_source_source_ready1 - attribute \src "ls180.v:1360.6-1360.48" + attribute \src "ls180.v:1271.6-1271.48" wire \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:1381.6-1381.48" + attribute \src "ls180.v:1292.6-1292.48" wire \main_sdphy_dataw_crcr_source_source_valid1 - attribute \src "ls180.v:1365.6-1365.33" + attribute \src "ls180.v:1276.6-1276.33" wire \main_sdphy_dataw_crcr_start - attribute \src "ls180.v:1348.5-1348.27" + attribute \src "ls180.v:1259.5-1259.27" wire \main_sdphy_dataw_error - attribute \src "ls180.v:1337.5-1337.43" + attribute \src "ls180.v:1248.5-1248.43" wire \main_sdphy_dataw_pads_in_pads_in_first - attribute \src "ls180.v:1338.5-1338.42" + attribute \src "ls180.v:1249.5-1249.42" wire \main_sdphy_dataw_pads_in_pads_in_last - attribute \src "ls180.v:1339.5-1339.49" + attribute \src "ls180.v:1250.5-1250.49" wire \main_sdphy_dataw_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1340.5-1340.51" + attribute \src "ls180.v:1251.5-1251.51" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1341.5-1341.51" + attribute \src "ls180.v:1252.5-1252.51" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1342.5-1342.52" + attribute \src "ls180.v:1253.5-1253.52" wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1343.11-1343.58" + attribute \src "ls180.v:1254.11-1254.58" wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1344.11-1344.58" + attribute \src "ls180.v:1255.11-1255.58" wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1345.5-1345.53" + attribute \src "ls180.v:1256.5-1256.53" wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1336.6-1336.44" + attribute \src "ls180.v:1247.6-1247.44" wire \main_sdphy_dataw_pads_in_pads_in_ready - attribute \src "ls180.v:1335.5-1335.43" + attribute \src "ls180.v:1246.5-1246.43" wire \main_sdphy_dataw_pads_in_pads_in_valid - attribute \src "ls180.v:1320.6-1320.44" + attribute \src "ls180.v:1231.6-1231.44" wire \main_sdphy_dataw_pads_in_payload_cmd_i - attribute \src "ls180.v:1321.12-1321.51" + attribute \src "ls180.v:1232.12-1232.51" wire width 4 \main_sdphy_dataw_pads_in_payload_data_i - attribute \src "ls180.v:1319.6-1319.36" + attribute \src "ls180.v:1230.6-1230.36" wire \main_sdphy_dataw_pads_in_valid - attribute \src "ls180.v:1323.5-1323.42" + attribute \src "ls180.v:1234.5-1234.42" wire \main_sdphy_dataw_pads_out_payload_clk - attribute \src "ls180.v:1324.5-1324.44" + attribute \src "ls180.v:1235.5-1235.44" wire \main_sdphy_dataw_pads_out_payload_cmd_o - attribute \src "ls180.v:1325.5-1325.45" + attribute \src "ls180.v:1236.5-1236.45" wire \main_sdphy_dataw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1326.11-1326.51" + attribute \src "ls180.v:1237.11-1237.51" wire width 4 \main_sdphy_dataw_pads_out_payload_data_o - attribute \src "ls180.v:1327.5-1327.46" + attribute \src "ls180.v:1238.5-1238.46" wire \main_sdphy_dataw_pads_out_payload_data_oe - attribute \src "ls180.v:1322.6-1322.37" + attribute \src "ls180.v:1233.6-1233.37" wire \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:1330.5-1330.32" + attribute \src "ls180.v:1241.5-1241.32" wire \main_sdphy_dataw_sink_first - attribute \src "ls180.v:1331.5-1331.31" + attribute \src "ls180.v:1242.5-1242.31" wire \main_sdphy_dataw_sink_last - attribute \src "ls180.v:1332.11-1332.45" + attribute \src "ls180.v:1243.11-1243.45" wire width 8 \main_sdphy_dataw_sink_payload_data - attribute \src "ls180.v:1329.5-1329.32" + attribute \src "ls180.v:1240.5-1240.32" wire \main_sdphy_dataw_sink_ready - attribute \src "ls180.v:1328.5-1328.32" + attribute \src "ls180.v:1239.5-1239.32" wire \main_sdphy_dataw_sink_valid - attribute \src "ls180.v:1346.5-1346.27" + attribute \src "ls180.v:1257.5-1257.27" wire \main_sdphy_dataw_start - attribute \src "ls180.v:1333.5-1333.26" + attribute \src "ls180.v:1244.5-1244.26" wire \main_sdphy_dataw_stop - attribute \src "ls180.v:1347.5-1347.27" + attribute \src "ls180.v:1258.5-1258.27" wire \main_sdphy_dataw_valid - attribute \src "ls180.v:1227.11-1227.32" + attribute \src "ls180.v:1138.11-1138.32" wire width 8 \main_sdphy_init_count - attribute \src "ls180.v:1901.11-1901.59" + attribute \src "ls180.v:1812.11-1812.59" wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value - attribute \src "ls180.v:1902.5-1902.56" + attribute \src "ls180.v:1813.5-1813.56" wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:1215.6-1215.34" + attribute \src "ls180.v:1126.6-1126.34" wire \main_sdphy_init_initialize_r - attribute \src "ls180.v:1214.6-1214.35" + attribute \src "ls180.v:1125.6-1125.35" wire \main_sdphy_init_initialize_re - attribute \src "ls180.v:1217.5-1217.33" + attribute \src "ls180.v:1128.5-1128.33" wire \main_sdphy_init_initialize_w - attribute \src "ls180.v:1216.6-1216.35" + attribute \src "ls180.v:1127.6-1127.35" wire \main_sdphy_init_initialize_we - attribute \src "ls180.v:1219.6-1219.43" + attribute \src "ls180.v:1130.6-1130.43" wire \main_sdphy_init_pads_in_payload_cmd_i - attribute \src "ls180.v:1220.12-1220.50" + attribute \src "ls180.v:1131.12-1131.50" wire width 4 \main_sdphy_init_pads_in_payload_data_i - attribute \src "ls180.v:1218.6-1218.35" + attribute \src "ls180.v:1129.6-1129.35" wire \main_sdphy_init_pads_in_valid - attribute \src "ls180.v:1222.5-1222.41" + attribute \src "ls180.v:1133.5-1133.41" wire \main_sdphy_init_pads_out_payload_clk - attribute \src "ls180.v:1223.5-1223.43" + attribute \src "ls180.v:1134.5-1134.43" wire \main_sdphy_init_pads_out_payload_cmd_o - attribute \src "ls180.v:1224.5-1224.44" + attribute \src "ls180.v:1135.5-1135.44" wire \main_sdphy_init_pads_out_payload_cmd_oe - attribute \src "ls180.v:1225.11-1225.50" + attribute \src "ls180.v:1136.11-1136.50" wire width 4 \main_sdphy_init_pads_out_payload_data_o - attribute \src "ls180.v:1226.5-1226.45" + attribute \src "ls180.v:1137.5-1137.45" wire \main_sdphy_init_pads_out_payload_data_oe - attribute \src "ls180.v:1221.6-1221.36" + attribute \src "ls180.v:1132.6-1132.36" wire \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:1475.6-1475.27" + attribute \src "ls180.v:1386.6-1386.27" wire \main_sdphy_sdpads_clk - attribute \src "ls180.v:1476.5-1476.28" + attribute \src "ls180.v:1387.5-1387.28" wire \main_sdphy_sdpads_cmd_i - attribute \src "ls180.v:1477.6-1477.29" + attribute \src "ls180.v:1388.6-1388.29" wire \main_sdphy_sdpads_cmd_o - attribute \src "ls180.v:1478.6-1478.30" + attribute \src "ls180.v:1389.6-1389.30" wire \main_sdphy_sdpads_cmd_oe - attribute \src "ls180.v:1479.11-1479.35" + attribute \src "ls180.v:1390.11-1390.35" wire width 4 \main_sdphy_sdpads_data_i - attribute \src "ls180.v:1480.12-1480.36" + attribute \src "ls180.v:1391.12-1391.36" wire width 4 \main_sdphy_sdpads_data_o - attribute \src "ls180.v:1481.6-1481.31" + attribute \src "ls180.v:1392.6-1392.31" wire \main_sdphy_sdpads_data_oe - attribute \src "ls180.v:1204.6-1204.23" + attribute \src "ls180.v:1115.6-1115.23" wire \main_sdphy_status - attribute \src "ls180.v:1205.6-1205.19" + attribute \src "ls180.v:1116.6-1116.19" wire \main_sdphy_we - attribute \src "ls180.v:421.5-421.26" + attribute \src "ls180.v:332.5-332.26" wire \main_sdram_address_re - attribute \src "ls180.v:420.12-420.38" + attribute \src "ls180.v:331.12-331.38" wire width 13 \main_sdram_address_storage - attribute \src "ls180.v:423.5-423.27" + attribute \src "ls180.v:334.5-334.27" wire \main_sdram_baddress_re - attribute \src "ls180.v:422.11-422.38" + attribute \src "ls180.v:333.11-333.38" wire width 2 \main_sdram_baddress_storage - attribute \src "ls180.v:519.5-519.43" + attribute \src "ls180.v:430.5-430.43" wire \main_sdram_bankmachine0_auto_precharge - attribute \src "ls180.v:541.11-541.63" + attribute \src "ls180.v:452.11-452.63" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - attribute \src "ls180.v:546.6-546.58" + attribute \src "ls180.v:457.6-457.58" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:551.6-551.64" + attribute \src "ls180.v:462.6-462.64" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:552.6-552.63" + attribute \src "ls180.v:463.6-463.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:550.13-550.78" + attribute \src "ls180.v:461.13-461.78" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:549.6-549.69" + attribute \src "ls180.v:460.6-460.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:555.6-555.65" + attribute \src "ls180.v:466.6-466.65" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:556.6-556.64" + attribute \src "ls180.v:467.6-467.64" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:554.13-554.79" + attribute \src "ls180.v:465.13-465.79" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:553.6-553.70" + attribute \src "ls180.v:464.6-464.70" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:538.11-538.61" + attribute \src "ls180.v:449.11-449.61" wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level - attribute \src "ls180.v:540.11-540.63" + attribute \src "ls180.v:451.11-451.63" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - attribute \src "ls180.v:547.12-547.67" + attribute \src "ls180.v:458.12-458.67" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:548.13-548.70" + attribute \src "ls180.v:459.13-459.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:539.5-539.57" + attribute \src "ls180.v:450.5-450.57" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:522.5-522.60" + attribute \src "ls180.v:433.5-433.60" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:523.5-523.59" + attribute \src "ls180.v:434.5-434.59" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:525.13-525.75" + attribute \src "ls180.v:436.13-436.75" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:524.6-524.66" + attribute \src "ls180.v:435.6-435.66" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:521.6-521.61" + attribute \src "ls180.v:432.6-432.61" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:520.6-520.61" + attribute \src "ls180.v:431.6-431.61" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:528.6-528.63" + attribute \src "ls180.v:439.6-439.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:529.6-529.62" + attribute \src "ls180.v:440.6-440.62" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:531.13-531.77" + attribute \src "ls180.v:442.13-442.77" wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:530.6-530.68" + attribute \src "ls180.v:441.6-441.68" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:527.6-527.63" + attribute \src "ls180.v:438.6-438.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:526.6-526.63" + attribute \src "ls180.v:437.6-437.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:536.13-536.71" + attribute \src "ls180.v:447.13-447.71" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - attribute \src "ls180.v:537.13-537.72" + attribute \src "ls180.v:448.13-448.72" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - attribute \src "ls180.v:534.6-534.63" + attribute \src "ls180.v:445.6-445.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - attribute \src "ls180.v:535.6-535.69" + attribute \src "ls180.v:446.6-446.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - attribute \src "ls180.v:532.6-532.63" + attribute \src "ls180.v:443.6-443.63" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - attribute \src "ls180.v:533.6-533.69" + attribute \src "ls180.v:444.6-444.69" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - attribute \src "ls180.v:542.11-542.66" + attribute \src "ls180.v:453.11-453.66" wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:543.13-543.70" + attribute \src "ls180.v:454.13-454.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:545.13-545.70" + attribute \src "ls180.v:456.13-456.70" wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:544.6-544.60" + attribute \src "ls180.v:455.6-455.60" wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:559.6-559.51" + attribute \src "ls180.v:470.6-470.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_first - attribute \src "ls180.v:560.6-560.50" + attribute \src "ls180.v:471.6-471.50" wire \main_sdram_bankmachine0_cmd_buffer_sink_last - attribute \src "ls180.v:562.13-562.65" + attribute \src "ls180.v:473.13-473.65" wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:561.6-561.56" + attribute \src "ls180.v:472.6-472.56" wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - attribute \src "ls180.v:558.6-558.51" + attribute \src "ls180.v:469.6-469.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_ready - attribute \src "ls180.v:557.6-557.51" + attribute \src "ls180.v:468.6-468.51" wire \main_sdram_bankmachine0_cmd_buffer_sink_valid - attribute \src "ls180.v:565.5-565.52" + attribute \src "ls180.v:476.5-476.52" wire \main_sdram_bankmachine0_cmd_buffer_source_first - attribute \src "ls180.v:566.5-566.51" + attribute \src "ls180.v:477.5-477.51" wire \main_sdram_bankmachine0_cmd_buffer_source_last - attribute \src "ls180.v:568.12-568.66" + attribute \src "ls180.v:479.12-479.66" wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - attribute \src "ls180.v:567.5-567.57" + attribute \src "ls180.v:478.5-478.57" wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:564.6-564.53" + attribute \src "ls180.v:475.6-475.53" wire \main_sdram_bankmachine0_cmd_buffer_source_ready - attribute \src "ls180.v:563.5-563.52" + attribute \src "ls180.v:474.5-474.52" wire \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:511.12-511.49" + attribute \src "ls180.v:422.12-422.49" wire width 13 \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:512.12-512.50" + attribute \src "ls180.v:423.12-423.50" wire width 2 \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:513.5-513.44" + attribute \src "ls180.v:424.5-424.44" wire \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:516.5-516.47" + attribute \src "ls180.v:427.5-427.47" wire \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:517.5-517.48" + attribute \src "ls180.v:428.5-428.48" wire \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:518.5-518.49" + attribute \src "ls180.v:429.5-429.49" wire \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:514.5-514.44" + attribute \src "ls180.v:425.5-425.44" wire \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:515.5-515.43" + attribute \src "ls180.v:426.5-426.43" wire \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:510.5-510.38" + attribute \src "ls180.v:421.5-421.38" wire \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:509.5-509.38" + attribute \src "ls180.v:420.5-420.38" wire \main_sdram_bankmachine0_cmd_valid - attribute \src "ls180.v:508.5-508.40" + attribute \src "ls180.v:419.5-419.40" wire \main_sdram_bankmachine0_refresh_gnt - attribute \src "ls180.v:507.6-507.41" + attribute \src "ls180.v:418.6-418.41" wire \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:503.13-503.45" + attribute \src "ls180.v:414.13-414.45" wire width 22 \main_sdram_bankmachine0_req_addr - attribute \src "ls180.v:504.6-504.38" + attribute \src "ls180.v:415.6-415.38" wire \main_sdram_bankmachine0_req_lock - attribute \src "ls180.v:506.5-506.44" + attribute \src "ls180.v:417.5-417.44" wire \main_sdram_bankmachine0_req_rdata_valid - attribute \src "ls180.v:501.6-501.39" + attribute \src "ls180.v:412.6-412.39" wire \main_sdram_bankmachine0_req_ready - attribute \src "ls180.v:500.6-500.39" + attribute \src "ls180.v:411.6-411.39" wire \main_sdram_bankmachine0_req_valid - attribute \src "ls180.v:505.5-505.44" + attribute \src "ls180.v:416.5-416.44" wire \main_sdram_bankmachine0_req_wdata_ready - attribute \src "ls180.v:502.6-502.36" + attribute \src "ls180.v:413.6-413.36" wire \main_sdram_bankmachine0_req_we - attribute \src "ls180.v:569.12-569.39" + attribute \src "ls180.v:480.12-480.39" wire width 13 \main_sdram_bankmachine0_row - attribute \src "ls180.v:573.5-573.38" + attribute \src "ls180.v:484.5-484.38" wire \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:574.5-574.47" + attribute \src "ls180.v:485.5-485.47" wire \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:571.6-571.37" + attribute \src "ls180.v:482.6-482.37" wire \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:572.5-572.37" + attribute \src "ls180.v:483.5-483.37" wire \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:570.5-570.39" + attribute \src "ls180.v:481.5-481.39" wire \main_sdram_bankmachine0_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:581.32-581.69" + attribute \src "ls180.v:492.32-492.69" wire \main_sdram_bankmachine0_trascon_ready - attribute \src "ls180.v:580.6-580.43" + attribute \src "ls180.v:491.6-491.43" wire \main_sdram_bankmachine0_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:579.32-579.68" + attribute \src "ls180.v:490.32-490.68" wire \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:578.6-578.42" + attribute \src "ls180.v:489.6-489.42" wire \main_sdram_bankmachine0_trccon_valid - attribute \src "ls180.v:577.11-577.48" + attribute \src "ls180.v:488.11-488.48" wire width 3 \main_sdram_bankmachine0_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:576.32-576.69" + attribute \src "ls180.v:487.32-487.69" wire \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:575.6-575.43" + attribute \src "ls180.v:486.6-486.43" wire \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:601.5-601.43" + attribute \src "ls180.v:512.5-512.43" wire \main_sdram_bankmachine1_auto_precharge - attribute \src "ls180.v:623.11-623.63" + attribute \src "ls180.v:534.11-534.63" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - attribute \src "ls180.v:628.6-628.58" + attribute \src "ls180.v:539.6-539.58" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:633.6-633.64" + attribute \src "ls180.v:544.6-544.64" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:634.6-634.63" + attribute \src "ls180.v:545.6-545.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:632.13-632.78" + attribute \src "ls180.v:543.13-543.78" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:631.6-631.69" + attribute \src "ls180.v:542.6-542.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:637.6-637.65" + attribute \src "ls180.v:548.6-548.65" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:638.6-638.64" + attribute \src "ls180.v:549.6-549.64" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:636.13-636.79" + attribute \src "ls180.v:547.13-547.79" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:635.6-635.70" + attribute \src "ls180.v:546.6-546.70" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:620.11-620.61" + attribute \src "ls180.v:531.11-531.61" wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level - attribute \src "ls180.v:622.11-622.63" + attribute \src "ls180.v:533.11-533.63" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - attribute \src "ls180.v:629.12-629.67" + attribute \src "ls180.v:540.12-540.67" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:630.13-630.70" + attribute \src "ls180.v:541.13-541.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:621.5-621.57" + attribute \src "ls180.v:532.5-532.57" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:604.5-604.60" + attribute \src "ls180.v:515.5-515.60" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:605.5-605.59" + attribute \src "ls180.v:516.5-516.59" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:607.13-607.75" + attribute \src "ls180.v:518.13-518.75" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:606.6-606.66" + attribute \src "ls180.v:517.6-517.66" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:603.6-603.61" + attribute \src "ls180.v:514.6-514.61" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:602.6-602.61" + attribute \src "ls180.v:513.6-513.61" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:610.6-610.63" + attribute \src "ls180.v:521.6-521.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:611.6-611.62" + attribute \src "ls180.v:522.6-522.62" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:613.13-613.77" + attribute \src "ls180.v:524.13-524.77" wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:612.6-612.68" + attribute \src "ls180.v:523.6-523.68" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:609.6-609.63" + attribute \src "ls180.v:520.6-520.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:608.6-608.63" + attribute \src "ls180.v:519.6-519.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:618.13-618.71" + attribute \src "ls180.v:529.13-529.71" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - attribute \src "ls180.v:619.13-619.72" + attribute \src "ls180.v:530.13-530.72" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - attribute \src "ls180.v:616.6-616.63" + attribute \src "ls180.v:527.6-527.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - attribute \src "ls180.v:617.6-617.69" + attribute \src "ls180.v:528.6-528.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - attribute \src "ls180.v:614.6-614.63" + attribute \src "ls180.v:525.6-525.63" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - attribute \src "ls180.v:615.6-615.69" + attribute \src "ls180.v:526.6-526.69" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - attribute \src "ls180.v:624.11-624.66" + attribute \src "ls180.v:535.11-535.66" wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:625.13-625.70" + attribute \src "ls180.v:536.13-536.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:627.13-627.70" + attribute \src "ls180.v:538.13-538.70" wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:626.6-626.60" + attribute \src "ls180.v:537.6-537.60" wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:641.6-641.51" + attribute \src "ls180.v:552.6-552.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_first - attribute \src "ls180.v:642.6-642.50" + attribute \src "ls180.v:553.6-553.50" wire \main_sdram_bankmachine1_cmd_buffer_sink_last - attribute \src "ls180.v:644.13-644.65" + attribute \src "ls180.v:555.13-555.65" wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:643.6-643.56" + attribute \src "ls180.v:554.6-554.56" wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - attribute \src "ls180.v:640.6-640.51" + attribute \src "ls180.v:551.6-551.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_ready - attribute \src "ls180.v:639.6-639.51" + attribute \src "ls180.v:550.6-550.51" wire \main_sdram_bankmachine1_cmd_buffer_sink_valid - attribute \src "ls180.v:647.5-647.52" + attribute \src "ls180.v:558.5-558.52" wire \main_sdram_bankmachine1_cmd_buffer_source_first - attribute \src "ls180.v:648.5-648.51" + attribute \src "ls180.v:559.5-559.51" wire \main_sdram_bankmachine1_cmd_buffer_source_last - attribute \src "ls180.v:650.12-650.66" + attribute \src "ls180.v:561.12-561.66" wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - attribute \src "ls180.v:649.5-649.57" + attribute \src "ls180.v:560.5-560.57" wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:646.6-646.53" + attribute \src "ls180.v:557.6-557.53" wire \main_sdram_bankmachine1_cmd_buffer_source_ready - attribute \src "ls180.v:645.5-645.52" + attribute \src "ls180.v:556.5-556.52" wire \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:593.12-593.49" + attribute \src "ls180.v:504.12-504.49" wire width 13 \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:594.12-594.50" + attribute \src "ls180.v:505.12-505.50" wire width 2 \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:595.5-595.44" + attribute \src "ls180.v:506.5-506.44" wire \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:598.5-598.47" + attribute \src "ls180.v:509.5-509.47" wire \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:599.5-599.48" + attribute \src "ls180.v:510.5-510.48" wire \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:600.5-600.49" + attribute \src "ls180.v:511.5-511.49" wire \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:596.5-596.44" + attribute \src "ls180.v:507.5-507.44" wire \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:597.5-597.43" + attribute \src "ls180.v:508.5-508.43" wire \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:592.5-592.38" + attribute \src "ls180.v:503.5-503.38" wire \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:591.5-591.38" + attribute \src "ls180.v:502.5-502.38" wire \main_sdram_bankmachine1_cmd_valid - attribute \src "ls180.v:590.5-590.40" + attribute \src "ls180.v:501.5-501.40" wire \main_sdram_bankmachine1_refresh_gnt - attribute \src "ls180.v:589.6-589.41" + attribute \src "ls180.v:500.6-500.41" wire \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:585.13-585.45" + attribute \src "ls180.v:496.13-496.45" wire width 22 \main_sdram_bankmachine1_req_addr - attribute \src "ls180.v:586.6-586.38" + attribute \src "ls180.v:497.6-497.38" wire \main_sdram_bankmachine1_req_lock - attribute \src "ls180.v:588.5-588.44" + attribute \src "ls180.v:499.5-499.44" wire \main_sdram_bankmachine1_req_rdata_valid - attribute \src "ls180.v:583.6-583.39" + attribute \src "ls180.v:494.6-494.39" wire \main_sdram_bankmachine1_req_ready - attribute \src "ls180.v:582.6-582.39" + attribute \src "ls180.v:493.6-493.39" wire \main_sdram_bankmachine1_req_valid - attribute \src "ls180.v:587.5-587.44" + attribute \src "ls180.v:498.5-498.44" wire \main_sdram_bankmachine1_req_wdata_ready - attribute \src "ls180.v:584.6-584.36" + attribute \src "ls180.v:495.6-495.36" wire \main_sdram_bankmachine1_req_we - attribute \src "ls180.v:651.12-651.39" + attribute \src "ls180.v:562.12-562.39" wire width 13 \main_sdram_bankmachine1_row - attribute \src "ls180.v:655.5-655.38" + attribute \src "ls180.v:566.5-566.38" wire \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:656.5-656.47" + attribute \src "ls180.v:567.5-567.47" wire \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:653.6-653.37" + attribute \src "ls180.v:564.6-564.37" wire \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:654.5-654.37" + attribute \src "ls180.v:565.5-565.37" wire \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:652.5-652.39" + attribute \src "ls180.v:563.5-563.39" wire \main_sdram_bankmachine1_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:663.32-663.69" + attribute \src "ls180.v:574.32-574.69" wire \main_sdram_bankmachine1_trascon_ready - attribute \src "ls180.v:662.6-662.43" + attribute \src "ls180.v:573.6-573.43" wire \main_sdram_bankmachine1_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:661.32-661.68" + attribute \src "ls180.v:572.32-572.68" wire \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:660.6-660.42" + attribute \src "ls180.v:571.6-571.42" wire \main_sdram_bankmachine1_trccon_valid - attribute \src "ls180.v:659.11-659.48" + attribute \src "ls180.v:570.11-570.48" wire width 3 \main_sdram_bankmachine1_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:658.32-658.69" + attribute \src "ls180.v:569.32-569.69" wire \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:657.6-657.43" + attribute \src "ls180.v:568.6-568.43" wire \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:683.5-683.43" + attribute \src "ls180.v:594.5-594.43" wire \main_sdram_bankmachine2_auto_precharge - attribute \src "ls180.v:705.11-705.63" + attribute \src "ls180.v:616.11-616.63" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - attribute \src "ls180.v:710.6-710.58" + attribute \src "ls180.v:621.6-621.58" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:715.6-715.64" + attribute \src "ls180.v:626.6-626.64" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:716.6-716.63" + attribute \src "ls180.v:627.6-627.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:714.13-714.78" + attribute \src "ls180.v:625.13-625.78" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:713.6-713.69" + attribute \src "ls180.v:624.6-624.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:719.6-719.65" + attribute \src "ls180.v:630.6-630.65" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:720.6-720.64" + attribute \src "ls180.v:631.6-631.64" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:718.13-718.79" + attribute \src "ls180.v:629.13-629.79" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:717.6-717.70" + attribute \src "ls180.v:628.6-628.70" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:702.11-702.61" + attribute \src "ls180.v:613.11-613.61" wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level - attribute \src "ls180.v:704.11-704.63" + attribute \src "ls180.v:615.11-615.63" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - attribute \src "ls180.v:711.12-711.67" + attribute \src "ls180.v:622.12-622.67" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:712.13-712.70" + attribute \src "ls180.v:623.13-623.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:703.5-703.57" + attribute \src "ls180.v:614.5-614.57" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:686.5-686.60" + attribute \src "ls180.v:597.5-597.60" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:687.5-687.59" + attribute \src "ls180.v:598.5-598.59" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:689.13-689.75" + attribute \src "ls180.v:600.13-600.75" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:688.6-688.66" + attribute \src "ls180.v:599.6-599.66" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:685.6-685.61" + attribute \src "ls180.v:596.6-596.61" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:684.6-684.61" + attribute \src "ls180.v:595.6-595.61" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:692.6-692.63" + attribute \src "ls180.v:603.6-603.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:693.6-693.62" + attribute \src "ls180.v:604.6-604.62" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:695.13-695.77" + attribute \src "ls180.v:606.13-606.77" wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:694.6-694.68" + attribute \src "ls180.v:605.6-605.68" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:691.6-691.63" + attribute \src "ls180.v:602.6-602.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:690.6-690.63" + attribute \src "ls180.v:601.6-601.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:700.13-700.71" + attribute \src "ls180.v:611.13-611.71" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - attribute \src "ls180.v:701.13-701.72" + attribute \src "ls180.v:612.13-612.72" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - attribute \src "ls180.v:698.6-698.63" + attribute \src "ls180.v:609.6-609.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - attribute \src "ls180.v:699.6-699.69" + attribute \src "ls180.v:610.6-610.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - attribute \src "ls180.v:696.6-696.63" + attribute \src "ls180.v:607.6-607.63" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - attribute \src "ls180.v:697.6-697.69" + attribute \src "ls180.v:608.6-608.69" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - attribute \src "ls180.v:706.11-706.66" + attribute \src "ls180.v:617.11-617.66" wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:707.13-707.70" + attribute \src "ls180.v:618.13-618.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:709.13-709.70" + attribute \src "ls180.v:620.13-620.70" wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:708.6-708.60" + attribute \src "ls180.v:619.6-619.60" wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:723.6-723.51" + attribute \src "ls180.v:634.6-634.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_first - attribute \src "ls180.v:724.6-724.50" + attribute \src "ls180.v:635.6-635.50" wire \main_sdram_bankmachine2_cmd_buffer_sink_last - attribute \src "ls180.v:726.13-726.65" + attribute \src "ls180.v:637.13-637.65" wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:725.6-725.56" + attribute \src "ls180.v:636.6-636.56" wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - attribute \src "ls180.v:722.6-722.51" + attribute \src "ls180.v:633.6-633.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_ready - attribute \src "ls180.v:721.6-721.51" + attribute \src "ls180.v:632.6-632.51" wire \main_sdram_bankmachine2_cmd_buffer_sink_valid - attribute \src "ls180.v:729.5-729.52" + attribute \src "ls180.v:640.5-640.52" wire \main_sdram_bankmachine2_cmd_buffer_source_first - attribute \src "ls180.v:730.5-730.51" + attribute \src "ls180.v:641.5-641.51" wire \main_sdram_bankmachine2_cmd_buffer_source_last - attribute \src "ls180.v:732.12-732.66" + attribute \src "ls180.v:643.12-643.66" wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - attribute \src "ls180.v:731.5-731.57" + attribute \src "ls180.v:642.5-642.57" wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:728.6-728.53" + attribute \src "ls180.v:639.6-639.53" wire \main_sdram_bankmachine2_cmd_buffer_source_ready - attribute \src "ls180.v:727.5-727.52" + attribute \src "ls180.v:638.5-638.52" wire \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:675.12-675.49" + attribute \src "ls180.v:586.12-586.49" wire width 13 \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:676.12-676.50" + attribute \src "ls180.v:587.12-587.50" wire width 2 \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:677.5-677.44" + attribute \src "ls180.v:588.5-588.44" wire \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:680.5-680.47" + attribute \src "ls180.v:591.5-591.47" wire \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:681.5-681.48" + attribute \src "ls180.v:592.5-592.48" wire \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:682.5-682.49" + attribute \src "ls180.v:593.5-593.49" wire \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:678.5-678.44" + attribute \src "ls180.v:589.5-589.44" wire \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:679.5-679.43" + attribute \src "ls180.v:590.5-590.43" wire \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:674.5-674.38" + attribute \src "ls180.v:585.5-585.38" wire \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:673.5-673.38" + attribute \src "ls180.v:584.5-584.38" wire \main_sdram_bankmachine2_cmd_valid - attribute \src "ls180.v:672.5-672.40" + attribute \src "ls180.v:583.5-583.40" wire \main_sdram_bankmachine2_refresh_gnt - attribute \src "ls180.v:671.6-671.41" + attribute \src "ls180.v:582.6-582.41" wire \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:667.13-667.45" + attribute \src "ls180.v:578.13-578.45" wire width 22 \main_sdram_bankmachine2_req_addr - attribute \src "ls180.v:668.6-668.38" + attribute \src "ls180.v:579.6-579.38" wire \main_sdram_bankmachine2_req_lock - attribute \src "ls180.v:670.5-670.44" + attribute \src "ls180.v:581.5-581.44" wire \main_sdram_bankmachine2_req_rdata_valid - attribute \src "ls180.v:665.6-665.39" + attribute \src "ls180.v:576.6-576.39" wire \main_sdram_bankmachine2_req_ready - attribute \src "ls180.v:664.6-664.39" + attribute \src "ls180.v:575.6-575.39" wire \main_sdram_bankmachine2_req_valid - attribute \src "ls180.v:669.5-669.44" + attribute \src "ls180.v:580.5-580.44" wire \main_sdram_bankmachine2_req_wdata_ready - attribute \src "ls180.v:666.6-666.36" + attribute \src "ls180.v:577.6-577.36" wire \main_sdram_bankmachine2_req_we - attribute \src "ls180.v:733.12-733.39" + attribute \src "ls180.v:644.12-644.39" wire width 13 \main_sdram_bankmachine2_row - attribute \src "ls180.v:737.5-737.38" + attribute \src "ls180.v:648.5-648.38" wire \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:738.5-738.47" + attribute \src "ls180.v:649.5-649.47" wire \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:735.6-735.37" + attribute \src "ls180.v:646.6-646.37" wire \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:736.5-736.37" + attribute \src "ls180.v:647.5-647.37" wire \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:734.5-734.39" + attribute \src "ls180.v:645.5-645.39" wire \main_sdram_bankmachine2_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:745.32-745.69" + attribute \src "ls180.v:656.32-656.69" wire \main_sdram_bankmachine2_trascon_ready - attribute \src "ls180.v:744.6-744.43" + attribute \src "ls180.v:655.6-655.43" wire \main_sdram_bankmachine2_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:743.32-743.68" + attribute \src "ls180.v:654.32-654.68" wire \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:742.6-742.42" + attribute \src "ls180.v:653.6-653.42" wire \main_sdram_bankmachine2_trccon_valid - attribute \src "ls180.v:741.11-741.48" + attribute \src "ls180.v:652.11-652.48" wire width 3 \main_sdram_bankmachine2_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:740.32-740.69" + attribute \src "ls180.v:651.32-651.69" wire \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:739.6-739.43" + attribute \src "ls180.v:650.6-650.43" wire \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:765.5-765.43" + attribute \src "ls180.v:676.5-676.43" wire \main_sdram_bankmachine3_auto_precharge - attribute \src "ls180.v:787.11-787.63" + attribute \src "ls180.v:698.11-698.63" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - attribute \src "ls180.v:792.6-792.58" + attribute \src "ls180.v:703.6-703.58" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:797.6-797.64" + attribute \src "ls180.v:708.6-708.64" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:798.6-798.63" + attribute \src "ls180.v:709.6-709.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:796.13-796.78" + attribute \src "ls180.v:707.13-707.78" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:795.6-795.69" + attribute \src "ls180.v:706.6-706.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:801.6-801.65" + attribute \src "ls180.v:712.6-712.65" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:802.6-802.64" + attribute \src "ls180.v:713.6-713.64" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:800.13-800.79" + attribute \src "ls180.v:711.13-711.79" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:799.6-799.70" + attribute \src "ls180.v:710.6-710.70" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:784.11-784.61" + attribute \src "ls180.v:695.11-695.61" wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level - attribute \src "ls180.v:786.11-786.63" + attribute \src "ls180.v:697.11-697.63" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - attribute \src "ls180.v:793.12-793.67" + attribute \src "ls180.v:704.12-704.67" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:794.13-794.70" + attribute \src "ls180.v:705.13-705.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:785.5-785.57" + attribute \src "ls180.v:696.5-696.57" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:768.5-768.60" + attribute \src "ls180.v:679.5-679.60" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:769.5-769.59" + attribute \src "ls180.v:680.5-680.59" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:771.13-771.75" + attribute \src "ls180.v:682.13-682.75" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:770.6-770.66" + attribute \src "ls180.v:681.6-681.66" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:767.6-767.61" + attribute \src "ls180.v:678.6-678.61" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:766.6-766.61" + attribute \src "ls180.v:677.6-677.61" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:774.6-774.63" + attribute \src "ls180.v:685.6-685.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:775.6-775.62" + attribute \src "ls180.v:686.6-686.62" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:777.13-777.77" + attribute \src "ls180.v:688.13-688.77" wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:776.6-776.68" + attribute \src "ls180.v:687.6-687.68" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:773.6-773.63" + attribute \src "ls180.v:684.6-684.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:772.6-772.63" + attribute \src "ls180.v:683.6-683.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:782.13-782.71" + attribute \src "ls180.v:693.13-693.71" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - attribute \src "ls180.v:783.13-783.72" + attribute \src "ls180.v:694.13-694.72" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - attribute \src "ls180.v:780.6-780.63" + attribute \src "ls180.v:691.6-691.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - attribute \src "ls180.v:781.6-781.69" + attribute \src "ls180.v:692.6-692.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - attribute \src "ls180.v:778.6-778.63" + attribute \src "ls180.v:689.6-689.63" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - attribute \src "ls180.v:779.6-779.69" + attribute \src "ls180.v:690.6-690.69" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - attribute \src "ls180.v:788.11-788.66" + attribute \src "ls180.v:699.11-699.66" wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:789.13-789.70" + attribute \src "ls180.v:700.13-700.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:791.13-791.70" + attribute \src "ls180.v:702.13-702.70" wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:790.6-790.60" + attribute \src "ls180.v:701.6-701.60" wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:805.6-805.51" + attribute \src "ls180.v:716.6-716.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_first - attribute \src "ls180.v:806.6-806.50" + attribute \src "ls180.v:717.6-717.50" wire \main_sdram_bankmachine3_cmd_buffer_sink_last - attribute \src "ls180.v:808.13-808.65" + attribute \src "ls180.v:719.13-719.65" wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:807.6-807.56" + attribute \src "ls180.v:718.6-718.56" wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - attribute \src "ls180.v:804.6-804.51" + attribute \src "ls180.v:715.6-715.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_ready - attribute \src "ls180.v:803.6-803.51" + attribute \src "ls180.v:714.6-714.51" wire \main_sdram_bankmachine3_cmd_buffer_sink_valid - attribute \src "ls180.v:811.5-811.52" + attribute \src "ls180.v:722.5-722.52" wire \main_sdram_bankmachine3_cmd_buffer_source_first - attribute \src "ls180.v:812.5-812.51" + attribute \src "ls180.v:723.5-723.51" wire \main_sdram_bankmachine3_cmd_buffer_source_last - attribute \src "ls180.v:814.12-814.66" + attribute \src "ls180.v:725.12-725.66" wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - attribute \src "ls180.v:813.5-813.57" + attribute \src "ls180.v:724.5-724.57" wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:810.6-810.53" + attribute \src "ls180.v:721.6-721.53" wire \main_sdram_bankmachine3_cmd_buffer_source_ready - attribute \src "ls180.v:809.5-809.52" + attribute \src "ls180.v:720.5-720.52" wire \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:757.12-757.49" + attribute \src "ls180.v:668.12-668.49" wire width 13 \main_sdram_bankmachine3_cmd_payload_a - attribute \src "ls180.v:758.12-758.50" + attribute \src "ls180.v:669.12-669.50" wire width 2 \main_sdram_bankmachine3_cmd_payload_ba - attribute \src "ls180.v:759.5-759.44" + attribute \src "ls180.v:670.5-670.44" wire \main_sdram_bankmachine3_cmd_payload_cas - attribute \src "ls180.v:762.5-762.47" + attribute \src "ls180.v:673.5-673.47" wire \main_sdram_bankmachine3_cmd_payload_is_cmd - attribute \src "ls180.v:763.5-763.48" + attribute \src "ls180.v:674.5-674.48" wire \main_sdram_bankmachine3_cmd_payload_is_read - attribute \src "ls180.v:764.5-764.49" + attribute \src "ls180.v:675.5-675.49" wire \main_sdram_bankmachine3_cmd_payload_is_write - attribute \src "ls180.v:760.5-760.44" + attribute \src "ls180.v:671.5-671.44" wire \main_sdram_bankmachine3_cmd_payload_ras - attribute \src "ls180.v:761.5-761.43" + attribute \src "ls180.v:672.5-672.43" wire \main_sdram_bankmachine3_cmd_payload_we - attribute \src "ls180.v:756.5-756.38" + attribute \src "ls180.v:667.5-667.38" wire \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:755.5-755.38" + attribute \src "ls180.v:666.5-666.38" wire \main_sdram_bankmachine3_cmd_valid - attribute \src "ls180.v:754.5-754.40" + attribute \src "ls180.v:665.5-665.40" wire \main_sdram_bankmachine3_refresh_gnt - attribute \src "ls180.v:753.6-753.41" + attribute \src "ls180.v:664.6-664.41" wire \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:749.13-749.45" + attribute \src "ls180.v:660.13-660.45" wire width 22 \main_sdram_bankmachine3_req_addr - attribute \src "ls180.v:750.6-750.38" + attribute \src "ls180.v:661.6-661.38" wire \main_sdram_bankmachine3_req_lock - attribute \src "ls180.v:752.5-752.44" + attribute \src "ls180.v:663.5-663.44" wire \main_sdram_bankmachine3_req_rdata_valid - attribute \src "ls180.v:747.6-747.39" + attribute \src "ls180.v:658.6-658.39" wire \main_sdram_bankmachine3_req_ready - attribute \src "ls180.v:746.6-746.39" + attribute \src "ls180.v:657.6-657.39" wire \main_sdram_bankmachine3_req_valid - attribute \src "ls180.v:751.5-751.44" + attribute \src "ls180.v:662.5-662.44" wire \main_sdram_bankmachine3_req_wdata_ready - attribute \src "ls180.v:748.6-748.36" + attribute \src "ls180.v:659.6-659.36" wire \main_sdram_bankmachine3_req_we - attribute \src "ls180.v:815.12-815.39" + attribute \src "ls180.v:726.12-726.39" wire width 13 \main_sdram_bankmachine3_row - attribute \src "ls180.v:819.5-819.38" + attribute \src "ls180.v:730.5-730.38" wire \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:820.5-820.47" + attribute \src "ls180.v:731.5-731.47" wire \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:817.6-817.37" + attribute \src "ls180.v:728.6-728.37" wire \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:818.5-818.37" + attribute \src "ls180.v:729.5-729.37" wire \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:816.5-816.39" + attribute \src "ls180.v:727.5-727.39" wire \main_sdram_bankmachine3_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:827.32-827.69" + attribute \src "ls180.v:738.32-738.69" wire \main_sdram_bankmachine3_trascon_ready - attribute \src "ls180.v:826.6-826.43" + attribute \src "ls180.v:737.6-737.43" wire \main_sdram_bankmachine3_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:825.32-825.68" + attribute \src "ls180.v:736.32-736.68" wire \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:824.6-824.42" + attribute \src "ls180.v:735.6-735.42" wire \main_sdram_bankmachine3_trccon_valid - attribute \src "ls180.v:823.11-823.48" + attribute \src "ls180.v:734.11-734.48" wire width 3 \main_sdram_bankmachine3_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:822.32-822.69" + attribute \src "ls180.v:733.32-733.69" wire \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:821.6-821.43" + attribute \src "ls180.v:732.6-732.43" wire \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:829.6-829.28" + attribute \src "ls180.v:740.6-740.28" wire \main_sdram_cas_allowed - attribute \src "ls180.v:847.6-847.30" + attribute \src "ls180.v:758.6-758.30" wire \main_sdram_choose_cmd_ce - attribute \src "ls180.v:836.13-836.48" + attribute \src "ls180.v:747.13-747.48" wire width 13 \main_sdram_choose_cmd_cmd_payload_a - attribute \src "ls180.v:837.12-837.48" + attribute \src "ls180.v:748.12-748.48" wire width 2 \main_sdram_choose_cmd_cmd_payload_ba - attribute \src "ls180.v:838.5-838.42" + attribute \src "ls180.v:749.5-749.42" wire \main_sdram_choose_cmd_cmd_payload_cas - attribute \src "ls180.v:841.6-841.46" + attribute \src "ls180.v:752.6-752.46" wire \main_sdram_choose_cmd_cmd_payload_is_cmd - attribute \src "ls180.v:842.6-842.47" + attribute \src "ls180.v:753.6-753.47" wire \main_sdram_choose_cmd_cmd_payload_is_read - attribute \src "ls180.v:843.6-843.48" + attribute \src "ls180.v:754.6-754.48" wire \main_sdram_choose_cmd_cmd_payload_is_write - attribute \src "ls180.v:839.5-839.42" + attribute \src "ls180.v:750.5-750.42" wire \main_sdram_choose_cmd_cmd_payload_ras - attribute \src "ls180.v:840.5-840.41" + attribute \src "ls180.v:751.5-751.41" wire \main_sdram_choose_cmd_cmd_payload_we - attribute \src "ls180.v:835.5-835.36" + attribute \src "ls180.v:746.5-746.36" wire \main_sdram_choose_cmd_cmd_ready - attribute \src "ls180.v:834.6-834.37" + attribute \src "ls180.v:745.6-745.37" wire \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:846.11-846.38" + attribute \src "ls180.v:757.11-757.38" wire width 2 \main_sdram_choose_cmd_grant - attribute \src "ls180.v:845.12-845.41" + attribute \src "ls180.v:756.12-756.41" wire width 4 \main_sdram_choose_cmd_request - attribute \src "ls180.v:844.11-844.39" + attribute \src "ls180.v:755.11-755.39" wire width 4 \main_sdram_choose_cmd_valids - attribute \src "ls180.v:833.5-833.41" + attribute \src "ls180.v:744.5-744.41" wire \main_sdram_choose_cmd_want_activates - attribute \src "ls180.v:832.5-832.36" + attribute \src "ls180.v:743.5-743.36" wire \main_sdram_choose_cmd_want_cmds - attribute \src "ls180.v:830.5-830.37" + attribute \src "ls180.v:741.5-741.37" wire \main_sdram_choose_cmd_want_reads - attribute \src "ls180.v:831.5-831.38" + attribute \src "ls180.v:742.5-742.38" wire \main_sdram_choose_cmd_want_writes - attribute \src "ls180.v:865.6-865.30" + attribute \src "ls180.v:776.6-776.30" wire \main_sdram_choose_req_ce - attribute \src "ls180.v:854.13-854.48" + attribute \src "ls180.v:765.13-765.48" wire width 13 \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:855.12-855.48" + attribute \src "ls180.v:766.12-766.48" wire width 2 \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:856.5-856.42" + attribute \src "ls180.v:767.5-767.42" wire \main_sdram_choose_req_cmd_payload_cas - attribute \src "ls180.v:859.6-859.46" + attribute \src "ls180.v:770.6-770.46" wire \main_sdram_choose_req_cmd_payload_is_cmd - attribute \src "ls180.v:860.6-860.47" + attribute \src "ls180.v:771.6-771.47" wire \main_sdram_choose_req_cmd_payload_is_read - attribute \src "ls180.v:861.6-861.48" + attribute \src "ls180.v:772.6-772.48" wire \main_sdram_choose_req_cmd_payload_is_write - attribute \src "ls180.v:857.5-857.42" + attribute \src "ls180.v:768.5-768.42" wire \main_sdram_choose_req_cmd_payload_ras - attribute \src "ls180.v:858.5-858.41" + attribute \src "ls180.v:769.5-769.41" wire \main_sdram_choose_req_cmd_payload_we - attribute \src "ls180.v:853.5-853.36" + attribute \src "ls180.v:764.5-764.36" wire \main_sdram_choose_req_cmd_ready - attribute \src "ls180.v:852.6-852.37" + attribute \src "ls180.v:763.6-763.37" wire \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:864.11-864.38" + attribute \src "ls180.v:775.11-775.38" wire width 2 \main_sdram_choose_req_grant - attribute \src "ls180.v:863.12-863.41" + attribute \src "ls180.v:774.12-774.41" wire width 4 \main_sdram_choose_req_request - attribute \src "ls180.v:862.11-862.39" + attribute \src "ls180.v:773.11-773.39" wire width 4 \main_sdram_choose_req_valids - attribute \src "ls180.v:851.5-851.41" + attribute \src "ls180.v:762.5-762.41" wire \main_sdram_choose_req_want_activates - attribute \src "ls180.v:850.6-850.37" + attribute \src "ls180.v:761.6-761.37" wire \main_sdram_choose_req_want_cmds - attribute \src "ls180.v:848.5-848.37" + attribute \src "ls180.v:759.5-759.37" wire \main_sdram_choose_req_want_reads - attribute \src "ls180.v:849.5-849.38" + attribute \src "ls180.v:760.5-760.38" wire \main_sdram_choose_req_want_writes - attribute \src "ls180.v:409.6-409.20" + attribute \src "ls180.v:320.6-320.20" wire \main_sdram_cke - attribute \src "ls180.v:477.5-477.24" + attribute \src "ls180.v:388.5-388.24" wire \main_sdram_cmd_last - attribute \src "ls180.v:478.12-478.36" + attribute \src "ls180.v:389.12-389.36" wire width 13 \main_sdram_cmd_payload_a - attribute \src "ls180.v:479.11-479.36" + attribute \src "ls180.v:390.11-390.36" wire width 2 \main_sdram_cmd_payload_ba - attribute \src "ls180.v:480.5-480.31" + attribute \src "ls180.v:391.5-391.31" wire \main_sdram_cmd_payload_cas - attribute \src "ls180.v:483.5-483.35" + attribute \src "ls180.v:394.5-394.35" wire \main_sdram_cmd_payload_is_read - attribute \src "ls180.v:484.5-484.36" + attribute \src "ls180.v:395.5-395.36" wire \main_sdram_cmd_payload_is_write - attribute \src "ls180.v:481.5-481.31" + attribute \src "ls180.v:392.5-392.31" wire \main_sdram_cmd_payload_ras - attribute \src "ls180.v:482.5-482.30" + attribute \src "ls180.v:393.5-393.30" wire \main_sdram_cmd_payload_we - attribute \src "ls180.v:476.5-476.25" + attribute \src "ls180.v:387.5-387.25" wire \main_sdram_cmd_ready - attribute \src "ls180.v:475.5-475.25" + attribute \src "ls180.v:386.5-386.25" wire \main_sdram_cmd_valid - attribute \src "ls180.v:417.6-417.32" + attribute \src "ls180.v:328.6-328.32" wire \main_sdram_command_issue_r - attribute \src "ls180.v:416.6-416.33" + attribute \src "ls180.v:327.6-327.33" wire \main_sdram_command_issue_re - attribute \src "ls180.v:419.5-419.31" + attribute \src "ls180.v:330.5-330.31" wire \main_sdram_command_issue_w - attribute \src "ls180.v:418.6-418.33" + attribute \src "ls180.v:329.6-329.33" wire \main_sdram_command_issue_we - attribute \src "ls180.v:415.5-415.26" + attribute \src "ls180.v:326.5-326.26" wire \main_sdram_command_re - attribute \src "ls180.v:414.11-414.37" + attribute \src "ls180.v:325.11-325.37" wire width 6 \main_sdram_command_storage - attribute \src "ls180.v:468.5-468.28" + attribute \src "ls180.v:379.5-379.28" wire \main_sdram_dfi_p0_act_n - attribute \src "ls180.v:459.12-459.37" + attribute \src "ls180.v:370.12-370.37" wire width 13 \main_sdram_dfi_p0_address - attribute \src "ls180.v:460.11-460.33" + attribute \src "ls180.v:371.11-371.33" wire width 2 \main_sdram_dfi_p0_bank - attribute \src "ls180.v:461.5-461.28" + attribute \src "ls180.v:372.5-372.28" wire \main_sdram_dfi_p0_cas_n - attribute \src "ls180.v:465.6-465.27" + attribute \src "ls180.v:376.6-376.27" wire \main_sdram_dfi_p0_cke - attribute \src "ls180.v:462.5-462.27" + attribute \src "ls180.v:373.5-373.27" wire \main_sdram_dfi_p0_cs_n - attribute \src "ls180.v:466.6-466.27" + attribute \src "ls180.v:377.6-377.27" wire \main_sdram_dfi_p0_odt - attribute \src "ls180.v:463.5-463.28" + attribute \src "ls180.v:374.5-374.28" wire \main_sdram_dfi_p0_ras_n - attribute \src "ls180.v:473.13-473.37" + attribute \src "ls180.v:384.13-384.37" wire width 16 \main_sdram_dfi_p0_rddata - attribute \src "ls180.v:472.5-472.32" + attribute \src "ls180.v:383.5-383.32" wire \main_sdram_dfi_p0_rddata_en - attribute \src "ls180.v:474.6-474.36" + attribute \src "ls180.v:385.6-385.36" wire \main_sdram_dfi_p0_rddata_valid - attribute \src "ls180.v:467.6-467.31" + attribute \src "ls180.v:378.6-378.31" wire \main_sdram_dfi_p0_reset_n - attribute \src "ls180.v:464.5-464.27" + attribute \src "ls180.v:375.5-375.27" wire \main_sdram_dfi_p0_we_n - attribute \src "ls180.v:469.13-469.37" + attribute \src "ls180.v:380.13-380.37" wire width 16 \main_sdram_dfi_p0_wrdata - attribute \src "ls180.v:470.5-470.32" + attribute \src "ls180.v:381.5-381.32" wire \main_sdram_dfi_p0_wrdata_en - attribute \src "ls180.v:471.12-471.41" + attribute \src "ls180.v:382.12-382.41" wire width 2 \main_sdram_dfi_p0_wrdata_mask - attribute \src "ls180.v:883.5-883.19" + attribute \src "ls180.v:794.5-794.19" wire \main_sdram_en0 - attribute \src "ls180.v:886.5-886.19" + attribute \src "ls180.v:797.5-797.19" wire \main_sdram_en1 - attribute \src "ls180.v:889.6-889.30" + attribute \src "ls180.v:800.6-800.30" wire \main_sdram_go_to_refresh - attribute \src "ls180.v:431.13-431.44" + attribute \src "ls180.v:342.13-342.44" wire width 22 \main_sdram_interface_bank0_addr - attribute \src "ls180.v:432.6-432.37" + attribute \src "ls180.v:343.6-343.37" wire \main_sdram_interface_bank0_lock - attribute \src "ls180.v:434.6-434.44" + attribute \src "ls180.v:345.6-345.44" wire \main_sdram_interface_bank0_rdata_valid - attribute \src "ls180.v:429.6-429.38" + attribute \src "ls180.v:340.6-340.38" wire \main_sdram_interface_bank0_ready - attribute \src "ls180.v:428.6-428.38" + attribute \src "ls180.v:339.6-339.38" wire \main_sdram_interface_bank0_valid - attribute \src "ls180.v:433.6-433.44" + attribute \src "ls180.v:344.6-344.44" wire \main_sdram_interface_bank0_wdata_ready - attribute \src "ls180.v:430.6-430.35" + attribute \src "ls180.v:341.6-341.35" wire \main_sdram_interface_bank0_we - attribute \src "ls180.v:438.13-438.44" + attribute \src "ls180.v:349.13-349.44" wire width 22 \main_sdram_interface_bank1_addr - attribute \src "ls180.v:439.6-439.37" + attribute \src "ls180.v:350.6-350.37" wire \main_sdram_interface_bank1_lock - attribute \src "ls180.v:441.6-441.44" + attribute \src "ls180.v:352.6-352.44" wire \main_sdram_interface_bank1_rdata_valid - attribute \src "ls180.v:436.6-436.38" + attribute \src "ls180.v:347.6-347.38" wire \main_sdram_interface_bank1_ready - attribute \src "ls180.v:435.6-435.38" + attribute \src "ls180.v:346.6-346.38" wire \main_sdram_interface_bank1_valid - attribute \src "ls180.v:440.6-440.44" + attribute \src "ls180.v:351.6-351.44" wire \main_sdram_interface_bank1_wdata_ready - attribute \src "ls180.v:437.6-437.35" + attribute \src "ls180.v:348.6-348.35" wire \main_sdram_interface_bank1_we - attribute \src "ls180.v:445.13-445.44" + attribute \src "ls180.v:356.13-356.44" wire width 22 \main_sdram_interface_bank2_addr - attribute \src "ls180.v:446.6-446.37" + attribute \src "ls180.v:357.6-357.37" wire \main_sdram_interface_bank2_lock - attribute \src "ls180.v:448.6-448.44" + attribute \src "ls180.v:359.6-359.44" wire \main_sdram_interface_bank2_rdata_valid - attribute \src "ls180.v:443.6-443.38" + attribute \src "ls180.v:354.6-354.38" wire \main_sdram_interface_bank2_ready - attribute \src "ls180.v:442.6-442.38" + attribute \src "ls180.v:353.6-353.38" wire \main_sdram_interface_bank2_valid - attribute \src "ls180.v:447.6-447.44" + attribute \src "ls180.v:358.6-358.44" wire \main_sdram_interface_bank2_wdata_ready - attribute \src "ls180.v:444.6-444.35" + attribute \src "ls180.v:355.6-355.35" wire \main_sdram_interface_bank2_we - attribute \src "ls180.v:452.13-452.44" + attribute \src "ls180.v:363.13-363.44" wire width 22 \main_sdram_interface_bank3_addr - attribute \src "ls180.v:453.6-453.37" + attribute \src "ls180.v:364.6-364.37" wire \main_sdram_interface_bank3_lock - attribute \src "ls180.v:455.6-455.44" + attribute \src "ls180.v:366.6-366.44" wire \main_sdram_interface_bank3_rdata_valid - attribute \src "ls180.v:450.6-450.38" + attribute \src "ls180.v:361.6-361.38" wire \main_sdram_interface_bank3_ready - attribute \src "ls180.v:449.6-449.38" + attribute \src "ls180.v:360.6-360.38" wire \main_sdram_interface_bank3_valid - attribute \src "ls180.v:454.6-454.44" + attribute \src "ls180.v:365.6-365.44" wire \main_sdram_interface_bank3_wdata_ready - attribute \src "ls180.v:451.6-451.35" + attribute \src "ls180.v:362.6-362.35" wire \main_sdram_interface_bank3_we - attribute \src "ls180.v:458.13-458.39" + attribute \src "ls180.v:369.13-369.39" wire width 16 \main_sdram_interface_rdata - attribute \src "ls180.v:456.12-456.38" + attribute \src "ls180.v:367.12-367.38" wire width 16 \main_sdram_interface_wdata - attribute \src "ls180.v:457.11-457.40" + attribute \src "ls180.v:368.11-368.40" wire width 2 \main_sdram_interface_wdata_we - attribute \src "ls180.v:369.5-369.29" + attribute \src "ls180.v:280.5-280.29" wire \main_sdram_inti_p0_act_n - attribute \src "ls180.v:360.13-360.39" + attribute \src "ls180.v:271.13-271.39" wire width 13 \main_sdram_inti_p0_address - attribute \src "ls180.v:361.12-361.35" + attribute \src "ls180.v:272.12-272.35" wire width 2 \main_sdram_inti_p0_bank - attribute \src "ls180.v:362.5-362.29" + attribute \src "ls180.v:273.5-273.29" wire \main_sdram_inti_p0_cas_n - attribute \src "ls180.v:366.6-366.28" + attribute \src "ls180.v:277.6-277.28" wire \main_sdram_inti_p0_cke - attribute \src "ls180.v:363.5-363.28" + attribute \src "ls180.v:274.5-274.28" wire \main_sdram_inti_p0_cs_n - attribute \src "ls180.v:367.6-367.28" + attribute \src "ls180.v:278.6-278.28" wire \main_sdram_inti_p0_odt - attribute \src "ls180.v:364.5-364.29" + attribute \src "ls180.v:275.5-275.29" wire \main_sdram_inti_p0_ras_n - attribute \src "ls180.v:374.12-374.37" + attribute \src "ls180.v:285.12-285.37" wire width 16 \main_sdram_inti_p0_rddata - attribute \src "ls180.v:373.6-373.34" + attribute \src "ls180.v:284.6-284.34" wire \main_sdram_inti_p0_rddata_en - attribute \src "ls180.v:375.5-375.36" + attribute \src "ls180.v:286.5-286.36" wire \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:368.6-368.32" + attribute \src "ls180.v:279.6-279.32" wire \main_sdram_inti_p0_reset_n - attribute \src "ls180.v:365.5-365.28" + attribute \src "ls180.v:276.5-276.28" wire \main_sdram_inti_p0_we_n - attribute \src "ls180.v:370.13-370.38" + attribute \src "ls180.v:281.13-281.38" wire width 16 \main_sdram_inti_p0_wrdata - attribute \src "ls180.v:371.6-371.34" + attribute \src "ls180.v:282.6-282.34" wire \main_sdram_inti_p0_wrdata_en - attribute \src "ls180.v:372.12-372.42" + attribute \src "ls180.v:283.12-283.42" wire width 2 \main_sdram_inti_p0_wrdata_mask - attribute \src "ls180.v:401.5-401.31" + attribute \src "ls180.v:312.5-312.31" wire \main_sdram_master_p0_act_n - attribute \src "ls180.v:392.12-392.40" + attribute \src "ls180.v:303.12-303.40" wire width 13 \main_sdram_master_p0_address - attribute \src "ls180.v:393.11-393.36" + attribute \src "ls180.v:304.11-304.36" wire width 2 \main_sdram_master_p0_bank - attribute \src "ls180.v:394.5-394.31" + attribute \src "ls180.v:305.5-305.31" wire \main_sdram_master_p0_cas_n - attribute \src "ls180.v:398.5-398.29" + attribute \src "ls180.v:309.5-309.29" wire \main_sdram_master_p0_cke - attribute \src "ls180.v:395.5-395.30" + attribute \src "ls180.v:306.5-306.30" wire \main_sdram_master_p0_cs_n - attribute \src "ls180.v:399.5-399.29" + attribute \src "ls180.v:310.5-310.29" wire \main_sdram_master_p0_odt - attribute \src "ls180.v:396.5-396.31" + attribute \src "ls180.v:307.5-307.31" wire \main_sdram_master_p0_ras_n - attribute \src "ls180.v:406.13-406.40" + attribute \src "ls180.v:317.13-317.40" wire width 16 \main_sdram_master_p0_rddata - attribute \src "ls180.v:405.5-405.35" + attribute \src "ls180.v:316.5-316.35" wire \main_sdram_master_p0_rddata_en - attribute \src "ls180.v:407.6-407.39" + attribute \src "ls180.v:318.6-318.39" wire \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:400.5-400.33" + attribute \src "ls180.v:311.5-311.33" wire \main_sdram_master_p0_reset_n - attribute \src "ls180.v:397.5-397.30" + attribute \src "ls180.v:308.5-308.30" wire \main_sdram_master_p0_we_n - attribute \src "ls180.v:402.12-402.39" + attribute \src "ls180.v:313.12-313.39" wire width 16 \main_sdram_master_p0_wrdata - attribute \src "ls180.v:403.5-403.35" + attribute \src "ls180.v:314.5-314.35" wire \main_sdram_master_p0_wrdata_en - attribute \src "ls180.v:404.11-404.43" + attribute \src "ls180.v:315.11-315.43" wire width 2 \main_sdram_master_p0_wrdata_mask - attribute \src "ls180.v:884.6-884.26" + attribute \src "ls180.v:795.6-795.26" wire \main_sdram_max_time0 - attribute \src "ls180.v:887.6-887.26" + attribute \src "ls180.v:798.6-798.26" wire \main_sdram_max_time1 - attribute \src "ls180.v:866.12-866.28" + attribute \src "ls180.v:777.12-777.28" wire width 13 \main_sdram_nop_a - attribute \src "ls180.v:867.11-867.28" + attribute \src "ls180.v:778.11-778.28" wire width 2 \main_sdram_nop_ba - attribute \src "ls180.v:410.6-410.20" + attribute \src "ls180.v:321.6-321.20" wire \main_sdram_odt - attribute \src "ls180.v:493.5-493.31" + attribute \src "ls180.v:404.5-404.31" wire \main_sdram_postponer_count - attribute \src "ls180.v:491.6-491.32" + attribute \src "ls180.v:402.6-402.32" wire \main_sdram_postponer_req_i - attribute \src "ls180.v:492.5-492.31" + attribute \src "ls180.v:403.5-403.31" wire \main_sdram_postponer_req_o - attribute \src "ls180.v:828.6-828.28" + attribute \src "ls180.v:739.6-739.28" wire \main_sdram_ras_allowed - attribute \src "ls180.v:413.5-413.18" + attribute \src "ls180.v:324.5-324.18" wire \main_sdram_re - attribute \src "ls180.v:881.6-881.31" + attribute \src "ls180.v:792.6-792.31" wire \main_sdram_read_available - attribute \src "ls180.v:411.6-411.24" + attribute \src "ls180.v:322.6-322.24" wire \main_sdram_reset_n - attribute \src "ls180.v:408.6-408.20" + attribute \src "ls180.v:319.6-319.20" wire \main_sdram_sel - attribute \src "ls180.v:499.5-499.31" + attribute \src "ls180.v:410.5-410.31" wire \main_sdram_sequencer_count - attribute \src "ls180.v:498.11-498.39" + attribute \src "ls180.v:409.11-409.39" wire width 4 \main_sdram_sequencer_counter - attribute \src "ls180.v:495.6-495.32" + attribute \src "ls180.v:406.6-406.32" wire \main_sdram_sequencer_done0 - attribute \src "ls180.v:497.5-497.31" + attribute \src "ls180.v:408.5-408.31" wire \main_sdram_sequencer_done1 - attribute \src "ls180.v:494.5-494.32" + attribute \src "ls180.v:405.5-405.32" wire \main_sdram_sequencer_start0 - attribute \src "ls180.v:496.6-496.33" + attribute \src "ls180.v:407.6-407.33" wire \main_sdram_sequencer_start1 - attribute \src "ls180.v:385.6-385.31" + attribute \src "ls180.v:296.6-296.31" wire \main_sdram_slave_p0_act_n - attribute \src "ls180.v:376.13-376.40" + attribute \src "ls180.v:287.13-287.40" wire width 13 \main_sdram_slave_p0_address - attribute \src "ls180.v:377.12-377.36" + attribute \src "ls180.v:288.12-288.36" wire width 2 \main_sdram_slave_p0_bank - attribute \src "ls180.v:378.6-378.31" + attribute \src "ls180.v:289.6-289.31" wire \main_sdram_slave_p0_cas_n - attribute \src "ls180.v:382.6-382.29" + attribute \src "ls180.v:293.6-293.29" wire \main_sdram_slave_p0_cke - attribute \src "ls180.v:379.6-379.30" + attribute \src "ls180.v:290.6-290.30" wire \main_sdram_slave_p0_cs_n - attribute \src "ls180.v:383.6-383.29" + attribute \src "ls180.v:294.6-294.29" wire \main_sdram_slave_p0_odt - attribute \src "ls180.v:380.6-380.31" + attribute \src "ls180.v:291.6-291.31" wire \main_sdram_slave_p0_ras_n - attribute \src "ls180.v:390.12-390.38" + attribute \src "ls180.v:301.12-301.38" wire width 16 \main_sdram_slave_p0_rddata - attribute \src "ls180.v:389.6-389.35" + attribute \src "ls180.v:300.6-300.35" wire \main_sdram_slave_p0_rddata_en - attribute \src "ls180.v:391.5-391.37" + attribute \src "ls180.v:302.5-302.37" wire \main_sdram_slave_p0_rddata_valid - attribute \src "ls180.v:384.6-384.33" + attribute \src "ls180.v:295.6-295.33" wire \main_sdram_slave_p0_reset_n - attribute \src "ls180.v:381.6-381.30" + attribute \src "ls180.v:292.6-292.30" wire \main_sdram_slave_p0_we_n - attribute \src "ls180.v:386.13-386.39" + attribute \src "ls180.v:297.13-297.39" wire width 16 \main_sdram_slave_p0_wrdata - attribute \src "ls180.v:387.6-387.35" + attribute \src "ls180.v:298.6-298.35" wire \main_sdram_slave_p0_wrdata_en - attribute \src "ls180.v:388.12-388.43" + attribute \src "ls180.v:299.12-299.43" wire width 2 \main_sdram_slave_p0_wrdata_mask - attribute \src "ls180.v:426.12-426.29" + attribute \src "ls180.v:337.12-337.29" wire width 16 \main_sdram_status - attribute \src "ls180.v:869.5-869.24" + attribute \src "ls180.v:780.5-780.24" wire \main_sdram_steerer0 - attribute \src "ls180.v:870.5-870.24" + attribute \src "ls180.v:781.5-781.24" wire \main_sdram_steerer1 - attribute \src "ls180.v:868.11-868.33" + attribute \src "ls180.v:779.11-779.33" wire width 2 \main_sdram_steerer_sel - attribute \src "ls180.v:412.11-412.29" + attribute \src "ls180.v:323.11-323.29" wire width 4 \main_sdram_storage - attribute \src "ls180.v:877.5-877.29" + attribute \src "ls180.v:788.5-788.29" wire \main_sdram_tccdcon_count attribute \no_retiming "true" - attribute \src "ls180.v:876.32-876.56" + attribute \src "ls180.v:787.32-787.56" wire \main_sdram_tccdcon_ready - attribute \src "ls180.v:875.6-875.30" + attribute \src "ls180.v:786.6-786.30" wire \main_sdram_tccdcon_valid attribute \no_retiming "true" - attribute \src "ls180.v:874.32-874.56" + attribute \src "ls180.v:785.32-785.56" wire \main_sdram_tfawcon_ready - attribute \src "ls180.v:873.6-873.30" + attribute \src "ls180.v:784.6-784.30" wire \main_sdram_tfawcon_valid - attribute \src "ls180.v:885.11-885.27" + attribute \src "ls180.v:796.11-796.27" wire width 5 \main_sdram_time0 - attribute \src "ls180.v:888.11-888.27" + attribute \src "ls180.v:799.11-799.27" wire width 4 \main_sdram_time1 - attribute \src "ls180.v:488.12-488.35" + attribute \src "ls180.v:399.12-399.35" wire width 10 \main_sdram_timer_count0 - attribute \src "ls180.v:490.11-490.34" + attribute \src "ls180.v:401.11-401.34" wire width 10 \main_sdram_timer_count1 - attribute \src "ls180.v:487.6-487.28" + attribute \src "ls180.v:398.6-398.28" wire \main_sdram_timer_done0 - attribute \src "ls180.v:489.6-489.28" + attribute \src "ls180.v:400.6-400.28" wire \main_sdram_timer_done1 - attribute \src "ls180.v:486.6-486.27" + attribute \src "ls180.v:397.6-397.27" wire \main_sdram_timer_wait attribute \no_retiming "true" - attribute \src "ls180.v:872.32-872.56" + attribute \src "ls180.v:783.32-783.56" wire \main_sdram_trrdcon_ready - attribute \src "ls180.v:871.6-871.30" + attribute \src "ls180.v:782.6-782.30" wire \main_sdram_trrdcon_valid - attribute \src "ls180.v:880.11-880.35" + attribute \src "ls180.v:791.11-791.35" wire width 3 \main_sdram_twtrcon_count attribute \no_retiming "true" - attribute \src "ls180.v:879.32-879.56" + attribute \src "ls180.v:790.32-790.56" wire \main_sdram_twtrcon_ready - attribute \src "ls180.v:878.6-878.30" + attribute \src "ls180.v:789.6-789.30" wire \main_sdram_twtrcon_valid - attribute \src "ls180.v:485.6-485.30" + attribute \src "ls180.v:396.6-396.30" wire \main_sdram_wants_refresh - attribute \src "ls180.v:427.6-427.19" + attribute \src "ls180.v:338.6-338.19" wire \main_sdram_we - attribute \src "ls180.v:425.5-425.25" + attribute \src "ls180.v:336.5-336.25" wire \main_sdram_wrdata_re - attribute \src "ls180.v:424.12-424.37" + attribute \src "ls180.v:335.12-335.37" wire width 16 \main_sdram_wrdata_storage - attribute \src "ls180.v:882.6-882.32" + attribute \src "ls180.v:793.6-793.32" wire \main_sdram_write_available - attribute \src "ls180.v:917.5-917.47" + attribute \src "ls180.v:828.5-828.47" wire \main_socbushandler_converted_interface_ack - attribute \src "ls180.v:911.13-911.55" + attribute \src "ls180.v:822.13-822.55" wire width 30 \main_socbushandler_converted_interface_adr - attribute \src "ls180.v:920.12-920.54" + attribute \src "ls180.v:831.12-831.54" wire width 2 \main_socbushandler_converted_interface_bte - attribute \src "ls180.v:919.12-919.54" + attribute \src "ls180.v:830.12-830.54" wire width 3 \main_socbushandler_converted_interface_cti - attribute \src "ls180.v:915.6-915.48" + attribute \src "ls180.v:826.6-826.48" wire \main_socbushandler_converted_interface_cyc - attribute \src "ls180.v:913.13-913.57" + attribute \src "ls180.v:824.13-824.57" wire width 64 \main_socbushandler_converted_interface_dat_r - attribute \src "ls180.v:912.13-912.57" + attribute \src "ls180.v:823.13-823.57" wire width 64 \main_socbushandler_converted_interface_dat_w - attribute \src "ls180.v:921.5-921.47" + attribute \src "ls180.v:832.5-832.47" wire \main_socbushandler_converted_interface_err - attribute \src "ls180.v:914.12-914.54" + attribute \src "ls180.v:825.12-825.54" wire width 8 \main_socbushandler_converted_interface_sel - attribute \src "ls180.v:916.6-916.48" + attribute \src "ls180.v:827.6-827.48" wire \main_socbushandler_converted_interface_stb - attribute \src "ls180.v:918.6-918.47" + attribute \src "ls180.v:829.6-829.47" wire \main_socbushandler_converted_interface_we - attribute \src "ls180.v:923.5-923.31" + attribute \src "ls180.v:834.5-834.31" wire \main_socbushandler_counter - attribute \src "ls180.v:1852.5-1852.53" + attribute \src "ls180.v:1763.5-1763.53" wire \main_socbushandler_counter_converter2_next_value - attribute \src "ls180.v:1853.5-1853.56" + attribute \src "ls180.v:1764.5-1764.56" wire \main_socbushandler_counter_converter2_next_value_ce - attribute \src "ls180.v:925.12-925.36" + attribute \src "ls180.v:836.12-836.36" wire width 64 \main_socbushandler_dat_r - attribute \src "ls180.v:924.6-924.30" + attribute \src "ls180.v:835.6-835.30" wire \main_socbushandler_reset - attribute \src "ls180.v:922.5-922.28" + attribute \src "ls180.v:833.5-833.28" wire \main_socbushandler_skip - attribute \src "ls180.v:1100.6-1100.27" + attribute \src "ls180.v:1011.6-1011.27" wire \main_spimaster0_start - attribute \src "ls180.v:1110.12-1110.35" + attribute \src "ls180.v:1021.12-1021.35" wire width 8 \main_spimaster10_length - attribute \src "ls180.v:1111.12-1111.36" + attribute \src "ls180.v:1022.12-1022.36" wire width 16 \main_spimaster11_storage - attribute \src "ls180.v:1112.5-1112.24" + attribute \src "ls180.v:1023.5-1023.24" wire \main_spimaster12_re - attribute \src "ls180.v:1113.6-1113.27" + attribute \src "ls180.v:1024.6-1024.27" wire \main_spimaster13_done - attribute \src "ls180.v:1114.6-1114.29" + attribute \src "ls180.v:1025.6-1025.29" wire \main_spimaster14_status - attribute \src "ls180.v:1115.6-1115.25" + attribute \src "ls180.v:1026.6-1026.25" wire \main_spimaster15_we - attribute \src "ls180.v:1116.11-1116.35" + attribute \src "ls180.v:1027.11-1027.35" wire width 8 \main_spimaster16_storage - attribute \src "ls180.v:1117.5-1117.24" + attribute \src "ls180.v:1028.5-1028.24" wire \main_spimaster17_re - attribute \src "ls180.v:1118.12-1118.35" + attribute \src "ls180.v:1029.12-1029.35" wire width 8 \main_spimaster18_status - attribute \src "ls180.v:1119.6-1119.25" + attribute \src "ls180.v:1030.6-1030.25" wire \main_spimaster19_we - attribute \src "ls180.v:1101.12-1101.34" + attribute \src "ls180.v:1012.12-1012.34" wire width 8 \main_spimaster1_length - attribute \src "ls180.v:1173.5-1173.23" + attribute \src "ls180.v:1084.5-1084.23" wire \main_spimaster1_re - attribute \src "ls180.v:1172.12-1172.35" + attribute \src "ls180.v:1083.12-1083.35" wire width 16 \main_spimaster1_storage - attribute \src "ls180.v:1120.6-1120.26" + attribute \src "ls180.v:1031.6-1031.26" wire \main_spimaster20_sel - attribute \src "ls180.v:1121.5-1121.29" + attribute \src "ls180.v:1032.5-1032.29" wire \main_spimaster21_storage - attribute \src "ls180.v:1122.5-1122.24" + attribute \src "ls180.v:1033.5-1033.24" wire \main_spimaster22_re - attribute \src "ls180.v:1123.5-1123.29" + attribute \src "ls180.v:1034.5-1034.29" wire \main_spimaster23_storage - attribute \src "ls180.v:1124.5-1124.24" + attribute \src "ls180.v:1035.5-1035.24" wire \main_spimaster24_re - attribute \src "ls180.v:1125.5-1125.32" + attribute \src "ls180.v:1036.5-1036.32" wire \main_spimaster25_clk_enable - attribute \src "ls180.v:1126.5-1126.31" + attribute \src "ls180.v:1037.5-1037.31" wire \main_spimaster26_cs_enable - attribute \src "ls180.v:1127.11-1127.33" + attribute \src "ls180.v:1038.11-1038.33" wire width 3 \main_spimaster27_count - attribute \src "ls180.v:1893.11-1893.55" + attribute \src "ls180.v:1804.11-1804.55" wire width 3 \main_spimaster27_count_spimaster0_next_value - attribute \src "ls180.v:1894.5-1894.52" + attribute \src "ls180.v:1805.5-1805.52" wire \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:1128.5-1128.32" + attribute \src "ls180.v:1039.5-1039.32" wire \main_spimaster28_mosi_latch - attribute \src "ls180.v:1129.5-1129.32" + attribute \src "ls180.v:1040.5-1040.32" wire \main_spimaster29_miso_latch - attribute \src "ls180.v:1102.5-1102.25" + attribute \src "ls180.v:1013.5-1013.25" wire \main_spimaster2_done - attribute \src "ls180.v:1130.12-1130.40" + attribute \src "ls180.v:1041.12-1041.40" wire width 16 \main_spimaster30_clk_divider - attribute \src "ls180.v:1131.6-1131.31" + attribute \src "ls180.v:1042.6-1042.31" wire \main_spimaster31_clk_rise - attribute \src "ls180.v:1132.6-1132.31" + attribute \src "ls180.v:1043.6-1043.31" wire \main_spimaster32_clk_fall - attribute \src "ls180.v:1133.11-1133.37" + attribute \src "ls180.v:1044.11-1044.37" wire width 8 \main_spimaster33_mosi_data - attribute \src "ls180.v:1134.11-1134.36" + attribute \src "ls180.v:1045.11-1045.36" wire width 3 \main_spimaster34_mosi_sel - attribute \src "ls180.v:1135.11-1135.37" + attribute \src "ls180.v:1046.11-1046.37" wire width 8 \main_spimaster35_miso_data - attribute \src "ls180.v:1103.5-1103.24" + attribute \src "ls180.v:1014.5-1014.24" wire \main_spimaster3_irq - attribute \src "ls180.v:1104.12-1104.32" + attribute \src "ls180.v:1015.12-1015.32" wire width 8 \main_spimaster4_mosi - attribute \src "ls180.v:1105.11-1105.31" + attribute \src "ls180.v:1016.11-1016.31" wire width 8 \main_spimaster5_miso - attribute \src "ls180.v:1106.6-1106.24" + attribute \src "ls180.v:1017.6-1017.24" wire \main_spimaster6_cs - attribute \src "ls180.v:1107.6-1107.30" + attribute \src "ls180.v:1018.6-1018.30" wire \main_spimaster7_loopback - attribute \src "ls180.v:1108.12-1108.39" + attribute \src "ls180.v:1019.12-1019.39" wire width 16 \main_spimaster8_clk_divider - attribute \src "ls180.v:1109.5-1109.26" + attribute \src "ls180.v:1020.5-1020.26" wire \main_spimaster9_start - attribute \src "ls180.v:1144.13-1144.40" + attribute \src "ls180.v:1055.13-1055.40" wire width 16 \main_spisdcard_clk_divider0 - attribute \src "ls180.v:1166.12-1166.39" + attribute \src "ls180.v:1077.12-1077.39" wire width 16 \main_spisdcard_clk_divider1 - attribute \src "ls180.v:1161.5-1161.30" + attribute \src "ls180.v:1072.5-1072.30" wire \main_spisdcard_clk_enable - attribute \src "ls180.v:1168.6-1168.29" + attribute \src "ls180.v:1079.6-1079.29" wire \main_spisdcard_clk_fall - attribute \src "ls180.v:1167.6-1167.29" + attribute \src "ls180.v:1078.6-1078.29" wire \main_spisdcard_clk_rise - attribute \src "ls180.v:1148.5-1148.30" + attribute \src "ls180.v:1059.5-1059.30" wire \main_spisdcard_control_re - attribute \src "ls180.v:1147.12-1147.42" + attribute \src "ls180.v:1058.12-1058.42" wire width 16 \main_spisdcard_control_storage - attribute \src "ls180.v:1163.11-1163.31" + attribute \src "ls180.v:1074.11-1074.31" wire width 3 \main_spisdcard_count - attribute \src "ls180.v:1897.11-1897.53" + attribute \src "ls180.v:1808.11-1808.53" wire width 3 \main_spisdcard_count_spimaster1_next_value - attribute \src "ls180.v:1898.5-1898.50" + attribute \src "ls180.v:1809.5-1809.50" wire \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:1142.6-1142.23" + attribute \src "ls180.v:1053.6-1053.23" wire \main_spisdcard_cs - attribute \src "ls180.v:1162.5-1162.29" + attribute \src "ls180.v:1073.5-1073.29" wire \main_spisdcard_cs_enable - attribute \src "ls180.v:1158.5-1158.25" + attribute \src "ls180.v:1069.5-1069.25" wire \main_spisdcard_cs_re - attribute \src "ls180.v:1157.5-1157.30" + attribute \src "ls180.v:1068.5-1068.30" wire \main_spisdcard_cs_storage - attribute \src "ls180.v:1138.5-1138.25" + attribute \src "ls180.v:1049.5-1049.25" wire \main_spisdcard_done0 - attribute \src "ls180.v:1149.6-1149.26" + attribute \src "ls180.v:1060.6-1060.26" wire \main_spisdcard_done1 - attribute \src "ls180.v:1139.5-1139.23" + attribute \src "ls180.v:1050.5-1050.23" wire \main_spisdcard_irq - attribute \src "ls180.v:1137.12-1137.34" + attribute \src "ls180.v:1048.12-1048.34" wire width 8 \main_spisdcard_length0 - attribute \src "ls180.v:1146.12-1146.34" + attribute \src "ls180.v:1057.12-1057.34" wire width 8 \main_spisdcard_length1 - attribute \src "ls180.v:1143.6-1143.29" + attribute \src "ls180.v:1054.6-1054.29" wire \main_spisdcard_loopback - attribute \src "ls180.v:1160.5-1160.31" + attribute \src "ls180.v:1071.5-1071.31" wire \main_spisdcard_loopback_re - attribute \src "ls180.v:1159.5-1159.36" + attribute \src "ls180.v:1070.5-1070.36" wire \main_spisdcard_loopback_storage - attribute \src "ls180.v:1141.11-1141.30" + attribute \src "ls180.v:1052.11-1052.30" wire width 8 \main_spisdcard_miso - attribute \src "ls180.v:1171.11-1171.35" + attribute \src "ls180.v:1082.11-1082.35" wire width 8 \main_spisdcard_miso_data - attribute \src "ls180.v:1165.5-1165.30" + attribute \src "ls180.v:1076.5-1076.30" wire \main_spisdcard_miso_latch - attribute \src "ls180.v:1154.12-1154.38" + attribute \src "ls180.v:1065.12-1065.38" wire width 8 \main_spisdcard_miso_status - attribute \src "ls180.v:1155.6-1155.28" + attribute \src "ls180.v:1066.6-1066.28" wire \main_spisdcard_miso_we - attribute \src "ls180.v:1140.12-1140.31" + attribute \src "ls180.v:1051.12-1051.31" wire width 8 \main_spisdcard_mosi - attribute \src "ls180.v:1169.11-1169.35" + attribute \src "ls180.v:1080.11-1080.35" wire width 8 \main_spisdcard_mosi_data - attribute \src "ls180.v:1164.5-1164.30" + attribute \src "ls180.v:1075.5-1075.30" wire \main_spisdcard_mosi_latch - attribute \src "ls180.v:1153.5-1153.27" + attribute \src "ls180.v:1064.5-1064.27" wire \main_spisdcard_mosi_re - attribute \src "ls180.v:1170.11-1170.34" + attribute \src "ls180.v:1081.11-1081.34" wire width 3 \main_spisdcard_mosi_sel - attribute \src "ls180.v:1152.11-1152.38" + attribute \src "ls180.v:1063.11-1063.38" wire width 8 \main_spisdcard_mosi_storage - attribute \src "ls180.v:1156.6-1156.24" + attribute \src "ls180.v:1067.6-1067.24" wire \main_spisdcard_sel - attribute \src "ls180.v:1136.6-1136.27" + attribute \src "ls180.v:1047.6-1047.27" wire \main_spisdcard_start0 - attribute \src "ls180.v:1145.5-1145.26" + attribute \src "ls180.v:1056.5-1056.26" wire \main_spisdcard_start1 - attribute \src "ls180.v:1150.6-1150.34" + attribute \src "ls180.v:1061.6-1061.34" wire \main_spisdcard_status_status - attribute \src "ls180.v:1151.6-1151.30" + attribute \src "ls180.v:1062.6-1062.30" wire \main_spisdcard_status_we - attribute \src "ls180.v:260.12-260.26" - wire width 6 \main_sram0_adr - attribute \src "ls180.v:261.13-261.29" - wire width 64 \main_sram0_dat_r - attribute \src "ls180.v:263.13-263.29" - wire width 64 \main_sram0_dat_w - attribute \src "ls180.v:262.11-262.24" - wire width 8 \main_sram0_we - attribute \src "ls180.v:275.12-275.26" - wire width 6 \main_sram1_adr - attribute \src "ls180.v:276.13-276.29" - wire width 64 \main_sram1_dat_r - attribute \src "ls180.v:278.13-278.29" - wire width 64 \main_sram1_dat_w - attribute \src "ls180.v:277.11-277.24" - wire width 8 \main_sram1_we - attribute \src "ls180.v:290.12-290.26" - wire width 6 \main_sram2_adr - attribute \src "ls180.v:291.13-291.29" - wire width 64 \main_sram2_dat_r - attribute \src "ls180.v:293.13-293.29" - wire width 64 \main_sram2_dat_w - attribute \src "ls180.v:292.11-292.24" - wire width 8 \main_sram2_we - attribute \src "ls180.v:305.12-305.26" - wire width 6 \main_sram3_adr - attribute \src "ls180.v:306.13-306.29" - wire width 64 \main_sram3_dat_r - attribute \src "ls180.v:308.13-308.29" - wire width 64 \main_sram3_dat_w - attribute \src "ls180.v:307.11-307.24" - wire width 8 \main_sram3_we - attribute \src "ls180.v:991.12-991.44" + attribute \src "ls180.v:902.12-902.44" wire width 2 \main_uart_eventmanager_pending_r - attribute \src "ls180.v:990.6-990.39" + attribute \src "ls180.v:901.6-901.39" wire \main_uart_eventmanager_pending_re - attribute \src "ls180.v:993.11-993.43" + attribute \src "ls180.v:904.11-904.43" wire width 2 \main_uart_eventmanager_pending_w - attribute \src "ls180.v:992.6-992.39" + attribute \src "ls180.v:903.6-903.39" wire \main_uart_eventmanager_pending_we - attribute \src "ls180.v:995.5-995.30" + attribute \src "ls180.v:906.5-906.30" wire \main_uart_eventmanager_re - attribute \src "ls180.v:987.12-987.43" + attribute \src "ls180.v:898.12-898.43" wire width 2 \main_uart_eventmanager_status_r - attribute \src "ls180.v:986.6-986.38" + attribute \src "ls180.v:897.6-897.38" wire \main_uart_eventmanager_status_re - attribute \src "ls180.v:989.11-989.42" + attribute \src "ls180.v:900.11-900.42" wire width 2 \main_uart_eventmanager_status_w - attribute \src "ls180.v:988.6-988.38" + attribute \src "ls180.v:899.6-899.38" wire \main_uart_eventmanager_status_we - attribute \src "ls180.v:994.11-994.41" + attribute \src "ls180.v:905.11-905.41" wire width 2 \main_uart_eventmanager_storage - attribute \src "ls180.v:975.6-975.19" + attribute \src "ls180.v:886.6-886.19" wire \main_uart_irq - attribute \src "ls180.v:961.12-961.46" + attribute \src "ls180.v:872.12-872.46" wire width 32 \main_uart_phy_phase_accumulator_rx - attribute \src "ls180.v:951.12-951.46" + attribute \src "ls180.v:862.12-862.46" wire width 32 \main_uart_phy_phase_accumulator_tx - attribute \src "ls180.v:944.5-944.21" + attribute \src "ls180.v:855.5-855.21" wire \main_uart_phy_re - attribute \src "ls180.v:962.6-962.22" + attribute \src "ls180.v:873.6-873.22" wire \main_uart_phy_rx - attribute \src "ls180.v:965.11-965.36" + attribute \src "ls180.v:876.11-876.36" wire width 4 \main_uart_phy_rx_bitcount - attribute \src "ls180.v:966.5-966.26" + attribute \src "ls180.v:877.5-877.26" wire \main_uart_phy_rx_busy - attribute \src "ls180.v:963.5-963.23" + attribute \src "ls180.v:874.5-874.23" wire \main_uart_phy_rx_r - attribute \src "ls180.v:964.11-964.31" + attribute \src "ls180.v:875.11-875.31" wire width 8 \main_uart_phy_rx_reg - attribute \src "ls180.v:947.6-947.30" + attribute \src "ls180.v:858.6-858.30" wire \main_uart_phy_sink_first - attribute \src "ls180.v:948.6-948.29" + attribute \src "ls180.v:859.6-859.29" wire \main_uart_phy_sink_last - attribute \src "ls180.v:949.12-949.43" + attribute \src "ls180.v:860.12-860.43" wire width 8 \main_uart_phy_sink_payload_data - attribute \src "ls180.v:946.5-946.29" + attribute \src "ls180.v:857.5-857.29" wire \main_uart_phy_sink_ready - attribute \src "ls180.v:945.6-945.30" + attribute \src "ls180.v:856.6-856.30" wire \main_uart_phy_sink_valid - attribute \src "ls180.v:957.5-957.31" + attribute \src "ls180.v:868.5-868.31" wire \main_uart_phy_source_first - attribute \src "ls180.v:958.5-958.30" + attribute \src "ls180.v:869.5-869.30" wire \main_uart_phy_source_last - attribute \src "ls180.v:959.11-959.44" + attribute \src "ls180.v:870.11-870.44" wire width 8 \main_uart_phy_source_payload_data - attribute \src "ls180.v:956.6-956.32" + attribute \src "ls180.v:867.6-867.32" wire \main_uart_phy_source_ready - attribute \src "ls180.v:955.5-955.31" + attribute \src "ls180.v:866.5-866.31" wire \main_uart_phy_source_valid - attribute \src "ls180.v:943.12-943.33" + attribute \src "ls180.v:854.12-854.33" wire width 32 \main_uart_phy_storage - attribute \src "ls180.v:953.11-953.36" + attribute \src "ls180.v:864.11-864.36" wire width 4 \main_uart_phy_tx_bitcount - attribute \src "ls180.v:954.5-954.26" + attribute \src "ls180.v:865.5-865.26" wire \main_uart_phy_tx_busy - attribute \src "ls180.v:952.11-952.31" + attribute \src "ls180.v:863.11-863.31" wire width 8 \main_uart_phy_tx_reg - attribute \src "ls180.v:960.5-960.32" + attribute \src "ls180.v:871.5-871.32" wire \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:950.5-950.32" + attribute \src "ls180.v:861.5-861.32" wire \main_uart_phy_uart_clk_txen - attribute \src "ls180.v:1084.5-1084.20" + attribute \src "ls180.v:995.5-995.20" wire \main_uart_reset - attribute \src "ls180.v:984.5-984.23" + attribute \src "ls180.v:895.5-895.23" wire \main_uart_rx_clear - attribute \src "ls180.v:1068.11-1068.36" + attribute \src "ls180.v:979.11-979.36" wire width 4 \main_uart_rx_fifo_consume - attribute \src "ls180.v:1073.6-1073.31" + attribute \src "ls180.v:984.6-984.31" wire \main_uart_rx_fifo_do_read - attribute \src "ls180.v:1079.6-1079.37" + attribute \src "ls180.v:990.6-990.37" wire \main_uart_rx_fifo_fifo_in_first - attribute \src "ls180.v:1080.6-1080.36" + attribute \src "ls180.v:991.6-991.36" wire \main_uart_rx_fifo_fifo_in_last - attribute \src "ls180.v:1078.12-1078.50" + attribute \src "ls180.v:989.12-989.50" wire width 8 \main_uart_rx_fifo_fifo_in_payload_data - attribute \src "ls180.v:1082.6-1082.38" + attribute \src "ls180.v:993.6-993.38" wire \main_uart_rx_fifo_fifo_out_first - attribute \src "ls180.v:1083.6-1083.37" + attribute \src "ls180.v:994.6-994.37" wire \main_uart_rx_fifo_fifo_out_last - attribute \src "ls180.v:1081.12-1081.51" + attribute \src "ls180.v:992.12-992.51" wire width 8 \main_uart_rx_fifo_fifo_out_payload_data - attribute \src "ls180.v:1065.11-1065.35" + attribute \src "ls180.v:976.11-976.35" wire width 5 \main_uart_rx_fifo_level0 - attribute \src "ls180.v:1077.12-1077.36" + attribute \src "ls180.v:988.12-988.36" wire width 5 \main_uart_rx_fifo_level1 - attribute \src "ls180.v:1067.11-1067.36" + attribute \src "ls180.v:978.11-978.36" wire width 4 \main_uart_rx_fifo_produce - attribute \src "ls180.v:1074.12-1074.40" + attribute \src "ls180.v:985.12-985.40" wire width 4 \main_uart_rx_fifo_rdport_adr - attribute \src "ls180.v:1075.12-1075.42" + attribute \src "ls180.v:986.12-986.42" wire width 10 \main_uart_rx_fifo_rdport_dat_r - attribute \src "ls180.v:1076.6-1076.33" + attribute \src "ls180.v:987.6-987.33" wire \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:1057.6-1057.26" + attribute \src "ls180.v:968.6-968.26" wire \main_uart_rx_fifo_re - attribute \src "ls180.v:1058.5-1058.31" + attribute \src "ls180.v:969.5-969.31" wire \main_uart_rx_fifo_readable - attribute \src "ls180.v:1066.5-1066.30" + attribute \src "ls180.v:977.5-977.30" wire \main_uart_rx_fifo_replace - attribute \src "ls180.v:1049.6-1049.34" + attribute \src "ls180.v:960.6-960.34" wire \main_uart_rx_fifo_sink_first - attribute \src "ls180.v:1050.6-1050.33" + attribute \src "ls180.v:961.6-961.33" wire \main_uart_rx_fifo_sink_last - attribute \src "ls180.v:1051.12-1051.47" + attribute \src "ls180.v:962.12-962.47" wire width 8 \main_uart_rx_fifo_sink_payload_data - attribute \src "ls180.v:1048.6-1048.34" + attribute \src "ls180.v:959.6-959.34" wire \main_uart_rx_fifo_sink_ready - attribute \src "ls180.v:1047.6-1047.34" + attribute \src "ls180.v:958.6-958.34" wire \main_uart_rx_fifo_sink_valid - attribute \src "ls180.v:1054.6-1054.36" + attribute \src "ls180.v:965.6-965.36" wire \main_uart_rx_fifo_source_first - attribute \src "ls180.v:1055.6-1055.35" + attribute \src "ls180.v:966.6-966.35" wire \main_uart_rx_fifo_source_last - attribute \src "ls180.v:1056.12-1056.49" + attribute \src "ls180.v:967.12-967.49" wire width 8 \main_uart_rx_fifo_source_payload_data - attribute \src "ls180.v:1053.6-1053.36" + attribute \src "ls180.v:964.6-964.36" wire \main_uart_rx_fifo_source_ready - attribute \src "ls180.v:1052.6-1052.36" + attribute \src "ls180.v:963.6-963.36" wire \main_uart_rx_fifo_source_valid - attribute \src "ls180.v:1063.12-1063.42" + attribute \src "ls180.v:974.12-974.42" wire width 10 \main_uart_rx_fifo_syncfifo_din - attribute \src "ls180.v:1064.12-1064.43" + attribute \src "ls180.v:975.12-975.43" wire width 10 \main_uart_rx_fifo_syncfifo_dout - attribute \src "ls180.v:1061.6-1061.35" + attribute \src "ls180.v:972.6-972.35" wire \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:1062.6-1062.41" + attribute \src "ls180.v:973.6-973.41" wire \main_uart_rx_fifo_syncfifo_readable - attribute \src "ls180.v:1059.6-1059.35" + attribute \src "ls180.v:970.6-970.35" wire \main_uart_rx_fifo_syncfifo_we - attribute \src "ls180.v:1060.6-1060.41" + attribute \src "ls180.v:971.6-971.41" wire \main_uart_rx_fifo_syncfifo_writable - attribute \src "ls180.v:1069.11-1069.39" + attribute \src "ls180.v:980.11-980.39" wire width 4 \main_uart_rx_fifo_wrport_adr - attribute \src "ls180.v:1070.12-1070.42" + attribute \src "ls180.v:981.12-981.42" wire width 10 \main_uart_rx_fifo_wrport_dat_r - attribute \src "ls180.v:1072.12-1072.42" + attribute \src "ls180.v:983.12-983.42" wire width 10 \main_uart_rx_fifo_wrport_dat_w - attribute \src "ls180.v:1071.6-1071.33" + attribute \src "ls180.v:982.6-982.33" wire \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:985.5-985.29" + attribute \src "ls180.v:896.5-896.29" wire \main_uart_rx_old_trigger - attribute \src "ls180.v:982.5-982.25" + attribute \src "ls180.v:893.5-893.25" wire \main_uart_rx_pending - attribute \src "ls180.v:981.6-981.25" + attribute \src "ls180.v:892.6-892.25" wire \main_uart_rx_status - attribute \src "ls180.v:983.6-983.26" + attribute \src "ls180.v:894.6-894.26" wire \main_uart_rx_trigger - attribute \src "ls180.v:973.6-973.30" + attribute \src "ls180.v:884.6-884.30" wire \main_uart_rxempty_status - attribute \src "ls180.v:974.6-974.26" + attribute \src "ls180.v:885.6-885.26" wire \main_uart_rxempty_we - attribute \src "ls180.v:998.6-998.29" + attribute \src "ls180.v:909.6-909.29" wire \main_uart_rxfull_status - attribute \src "ls180.v:999.6-999.25" + attribute \src "ls180.v:910.6-910.25" wire \main_uart_rxfull_we - attribute \src "ls180.v:968.12-968.28" + attribute \src "ls180.v:879.12-879.28" wire width 8 \main_uart_rxtx_r - attribute \src "ls180.v:967.6-967.23" + attribute \src "ls180.v:878.6-878.23" wire \main_uart_rxtx_re - attribute \src "ls180.v:970.12-970.28" + attribute \src "ls180.v:881.12-881.28" wire width 8 \main_uart_rxtx_w - attribute \src "ls180.v:969.6-969.23" + attribute \src "ls180.v:880.6-880.23" wire \main_uart_rxtx_we - attribute \src "ls180.v:979.5-979.23" + attribute \src "ls180.v:890.5-890.23" wire \main_uart_tx_clear - attribute \src "ls180.v:1031.11-1031.36" + attribute \src "ls180.v:942.11-942.36" wire width 4 \main_uart_tx_fifo_consume - attribute \src "ls180.v:1036.6-1036.31" + attribute \src "ls180.v:947.6-947.31" wire \main_uart_tx_fifo_do_read - attribute \src "ls180.v:1042.6-1042.37" + attribute \src "ls180.v:953.6-953.37" wire \main_uart_tx_fifo_fifo_in_first - attribute \src "ls180.v:1043.6-1043.36" + attribute \src "ls180.v:954.6-954.36" wire \main_uart_tx_fifo_fifo_in_last - attribute \src "ls180.v:1041.12-1041.50" + attribute \src "ls180.v:952.12-952.50" wire width 8 \main_uart_tx_fifo_fifo_in_payload_data - attribute \src "ls180.v:1045.6-1045.38" + attribute \src "ls180.v:956.6-956.38" wire \main_uart_tx_fifo_fifo_out_first - attribute \src "ls180.v:1046.6-1046.37" + attribute \src "ls180.v:957.6-957.37" wire \main_uart_tx_fifo_fifo_out_last - attribute \src "ls180.v:1044.12-1044.51" + attribute \src "ls180.v:955.12-955.51" wire width 8 \main_uart_tx_fifo_fifo_out_payload_data - attribute \src "ls180.v:1028.11-1028.35" + attribute \src "ls180.v:939.11-939.35" wire width 5 \main_uart_tx_fifo_level0 - attribute \src "ls180.v:1040.12-1040.36" + attribute \src "ls180.v:951.12-951.36" wire width 5 \main_uart_tx_fifo_level1 - attribute \src "ls180.v:1030.11-1030.36" + attribute \src "ls180.v:941.11-941.36" wire width 4 \main_uart_tx_fifo_produce - attribute \src "ls180.v:1037.12-1037.40" + attribute \src "ls180.v:948.12-948.40" wire width 4 \main_uart_tx_fifo_rdport_adr - attribute \src "ls180.v:1038.12-1038.42" + attribute \src "ls180.v:949.12-949.42" wire width 10 \main_uart_tx_fifo_rdport_dat_r - attribute \src "ls180.v:1039.6-1039.33" + attribute \src "ls180.v:950.6-950.33" wire \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:1020.6-1020.26" + attribute \src "ls180.v:931.6-931.26" wire \main_uart_tx_fifo_re - attribute \src "ls180.v:1021.5-1021.31" + attribute \src "ls180.v:932.5-932.31" wire \main_uart_tx_fifo_readable - attribute \src "ls180.v:1029.5-1029.30" + attribute \src "ls180.v:940.5-940.30" wire \main_uart_tx_fifo_replace - attribute \src "ls180.v:1012.5-1012.33" + attribute \src "ls180.v:923.5-923.33" wire \main_uart_tx_fifo_sink_first - attribute \src "ls180.v:1013.5-1013.32" + attribute \src "ls180.v:924.5-924.32" wire \main_uart_tx_fifo_sink_last - attribute \src "ls180.v:1014.12-1014.47" + attribute \src "ls180.v:925.12-925.47" wire width 8 \main_uart_tx_fifo_sink_payload_data - attribute \src "ls180.v:1011.6-1011.34" + attribute \src "ls180.v:922.6-922.34" wire \main_uart_tx_fifo_sink_ready - attribute \src "ls180.v:1010.6-1010.34" + attribute \src "ls180.v:921.6-921.34" wire \main_uart_tx_fifo_sink_valid - attribute \src "ls180.v:1017.6-1017.36" + attribute \src "ls180.v:928.6-928.36" wire \main_uart_tx_fifo_source_first - attribute \src "ls180.v:1018.6-1018.35" + attribute \src "ls180.v:929.6-929.35" wire \main_uart_tx_fifo_source_last - attribute \src "ls180.v:1019.12-1019.49" + attribute \src "ls180.v:930.12-930.49" wire width 8 \main_uart_tx_fifo_source_payload_data - attribute \src "ls180.v:1016.6-1016.36" + attribute \src "ls180.v:927.6-927.36" wire \main_uart_tx_fifo_source_ready - attribute \src "ls180.v:1015.6-1015.36" + attribute \src "ls180.v:926.6-926.36" wire \main_uart_tx_fifo_source_valid - attribute \src "ls180.v:1026.12-1026.42" + attribute \src "ls180.v:937.12-937.42" wire width 10 \main_uart_tx_fifo_syncfifo_din - attribute \src "ls180.v:1027.12-1027.43" + attribute \src "ls180.v:938.12-938.43" wire width 10 \main_uart_tx_fifo_syncfifo_dout - attribute \src "ls180.v:1024.6-1024.35" + attribute \src "ls180.v:935.6-935.35" wire \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:1025.6-1025.41" + attribute \src "ls180.v:936.6-936.41" wire \main_uart_tx_fifo_syncfifo_readable - attribute \src "ls180.v:1022.6-1022.35" + attribute \src "ls180.v:933.6-933.35" wire \main_uart_tx_fifo_syncfifo_we - attribute \src "ls180.v:1023.6-1023.41" + attribute \src "ls180.v:934.6-934.41" wire \main_uart_tx_fifo_syncfifo_writable - attribute \src "ls180.v:1032.11-1032.39" + attribute \src "ls180.v:943.11-943.39" wire width 4 \main_uart_tx_fifo_wrport_adr - attribute \src "ls180.v:1033.12-1033.42" + attribute \src "ls180.v:944.12-944.42" wire width 10 \main_uart_tx_fifo_wrport_dat_r - attribute \src "ls180.v:1035.12-1035.42" + attribute \src "ls180.v:946.12-946.42" wire width 10 \main_uart_tx_fifo_wrport_dat_w - attribute \src "ls180.v:1034.6-1034.33" + attribute \src "ls180.v:945.6-945.33" wire \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:980.5-980.29" + attribute \src "ls180.v:891.5-891.29" wire \main_uart_tx_old_trigger - attribute \src "ls180.v:977.5-977.25" + attribute \src "ls180.v:888.5-888.25" wire \main_uart_tx_pending - attribute \src "ls180.v:976.6-976.25" + attribute \src "ls180.v:887.6-887.25" wire \main_uart_tx_status - attribute \src "ls180.v:978.6-978.26" + attribute \src "ls180.v:889.6-889.26" wire \main_uart_tx_trigger - attribute \src "ls180.v:996.6-996.30" + attribute \src "ls180.v:907.6-907.30" wire \main_uart_txempty_status - attribute \src "ls180.v:997.6-997.26" + attribute \src "ls180.v:908.6-908.26" wire \main_uart_txempty_we - attribute \src "ls180.v:971.6-971.29" + attribute \src "ls180.v:882.6-882.29" wire \main_uart_txfull_status - attribute \src "ls180.v:972.6-972.25" + attribute \src "ls180.v:883.6-883.25" wire \main_uart_txfull_we - attribute \src "ls180.v:1002.6-1002.31" + attribute \src "ls180.v:913.6-913.31" wire \main_uart_uart_sink_first - attribute \src "ls180.v:1003.6-1003.30" + attribute \src "ls180.v:914.6-914.30" wire \main_uart_uart_sink_last - attribute \src "ls180.v:1004.12-1004.44" + attribute \src "ls180.v:915.12-915.44" wire width 8 \main_uart_uart_sink_payload_data - attribute \src "ls180.v:1001.6-1001.31" + attribute \src "ls180.v:912.6-912.31" wire \main_uart_uart_sink_ready - attribute \src "ls180.v:1000.6-1000.31" + attribute \src "ls180.v:911.6-911.31" wire \main_uart_uart_sink_valid - attribute \src "ls180.v:1007.6-1007.33" + attribute \src "ls180.v:918.6-918.33" wire \main_uart_uart_source_first - attribute \src "ls180.v:1008.6-1008.32" + attribute \src "ls180.v:919.6-919.32" wire \main_uart_uart_source_last - attribute \src "ls180.v:1009.12-1009.46" + attribute \src "ls180.v:920.12-920.46" wire width 8 \main_uart_uart_source_payload_data - attribute \src "ls180.v:1006.6-1006.33" + attribute \src "ls180.v:917.6-917.33" wire \main_uart_uart_source_ready - attribute \src "ls180.v:1005.6-1005.33" + attribute \src "ls180.v:916.6-916.33" wire \main_uart_uart_source_valid - attribute \src "ls180.v:909.5-909.22" + attribute \src "ls180.v:820.5-820.22" wire \main_wb_sdram_ack - attribute \src "ls180.v:903.12-903.29" + attribute \src "ls180.v:814.12-814.29" wire width 30 \main_wb_sdram_adr - attribute \src "ls180.v:907.5-907.22" + attribute \src "ls180.v:818.5-818.22" wire \main_wb_sdram_cyc - attribute \src "ls180.v:905.13-905.32" + attribute \src "ls180.v:816.13-816.32" wire width 32 \main_wb_sdram_dat_r - attribute \src "ls180.v:904.12-904.31" + attribute \src "ls180.v:815.12-815.31" wire width 32 \main_wb_sdram_dat_w - attribute \src "ls180.v:906.11-906.28" + attribute \src "ls180.v:817.11-817.28" wire width 4 \main_wb_sdram_sel - attribute \src "ls180.v:908.5-908.22" + attribute \src "ls180.v:819.5-819.22" wire \main_wb_sdram_stb - attribute \src "ls180.v:910.5-910.21" + attribute \src "ls180.v:821.5-821.21" wire \main_wb_sdram_we - attribute \src "ls180.v:939.5-939.24" + attribute \src "ls180.v:850.5-850.24" wire \main_wdata_consumed - attribute \src "ls180.v:10352.11-10352.17" - wire width 6 \memadr - attribute \src "ls180.v:10380.11-10380.19" - wire width 6 \memadr_1 - attribute \src "ls180.v:10408.11-10408.19" - wire width 6 \memadr_2 - attribute \src "ls180.v:10436.11-10436.19" - wire width 6 \memadr_3 - attribute \src "ls180.v:10464.11-10464.19" - wire width 6 \memadr_4 - attribute \src "ls180.v:10492.12-10492.18" + attribute \src "ls180.v:10143.11-10143.17" + wire width 4 \memadr + attribute \src "ls180.v:10171.11-10171.19" + wire width 4 \memadr_1 + attribute \src "ls180.v:10199.12-10199.18" wire width 25 \memdat - attribute \src "ls180.v:10506.12-10506.20" + attribute \src "ls180.v:10213.12-10213.20" wire width 25 \memdat_1 - attribute \src "ls180.v:10520.12-10520.20" + attribute \src "ls180.v:10227.12-10227.20" wire width 25 \memdat_2 - attribute \src "ls180.v:10534.12-10534.20" + attribute \src "ls180.v:10241.12-10241.20" wire width 25 \memdat_3 - attribute \src "ls180.v:10548.11-10548.19" + attribute \src "ls180.v:10255.11-10255.19" wire width 10 \memdat_4 - attribute \src "ls180.v:10549.11-10549.19" + attribute \src "ls180.v:10256.11-10256.19" wire width 10 \memdat_5 - attribute \src "ls180.v:10565.11-10565.19" + attribute \src "ls180.v:10272.11-10272.19" wire width 10 \memdat_6 - attribute \src "ls180.v:10566.11-10566.19" + attribute \src "ls180.v:10273.11-10273.19" wire width 10 \memdat_7 - attribute \src "ls180.v:10582.11-10582.19" + attribute \src "ls180.v:10289.11-10289.19" wire width 10 \memdat_8 - attribute \src "ls180.v:10596.11-10596.19" + attribute \src "ls180.v:10303.11-10303.19" wire width 10 \memdat_9 attribute \src "ls180.v:52.20-52.22" wire width 24 input 48 \nc - attribute \src "ls180.v:341.6-341.13" + attribute \src "ls180.v:252.6-252.13" wire \por_clk - attribute \src "ls180.v:17.19-17.22" - wire width 2 output 13 \pwm - attribute \src "ls180.v:183.12-183.17" + attribute \src "ls180.v:42.19-42.22" + wire width 2 output 38 \pwm + attribute \src "ls180.v:162.12-162.17" wire width 2 \pwm_1 - attribute \src "ls180.v:36.13-36.23" - wire output 32 \sdcard_clk - attribute \src "ls180.v:37.14-37.26" - wire output 33 \sdcard_cmd_i - attribute \src "ls180.v:38.13-38.25" - wire output 34 \sdcard_cmd_o - attribute \src "ls180.v:39.13-39.26" - wire output 35 \sdcard_cmd_oe - attribute \src "ls180.v:40.20-40.33" - wire width 4 output 36 \sdcard_data_i - attribute \src "ls180.v:41.19-41.32" - wire width 4 output 37 \sdcard_data_o - attribute \src "ls180.v:42.13-42.27" - wire output 38 \sdcard_data_oe + attribute \src "ls180.v:11.13-11.23" + wire output 7 \sdcard_clk + attribute \src "ls180.v:12.14-12.26" + wire output 8 \sdcard_cmd_i + attribute \src "ls180.v:13.13-13.25" + wire output 9 \sdcard_cmd_o + attribute \src "ls180.v:14.13-14.26" + wire output 10 \sdcard_cmd_oe + attribute \src "ls180.v:15.20-15.33" + wire width 4 output 11 \sdcard_data_i + attribute \src "ls180.v:16.19-16.32" + wire width 4 output 12 \sdcard_data_o + attribute \src "ls180.v:17.13-17.27" + wire output 13 \sdcard_data_oe attribute \src "ls180.v:22.20-22.27" wire width 13 output 18 \sdram_a attribute \src "ls180.v:31.19-31.27" @@ -254365,7 +253605,7 @@ module \ls180 wire output 26 \sdram_cke attribute \src "ls180.v:33.13-33.24" wire output 29 \sdram_clock - attribute \src "ls180.v:199.6-199.19" + attribute \src "ls180.v:153.6-153.19" wire \sdram_clock_1 attribute \src "ls180.v:29.13-29.23" wire output 25 \sdram_cs_n @@ -254381,163 +253621,163 @@ module \ls180 wire output 23 \sdram_ras_n attribute \src "ls180.v:26.13-26.23" wire output 22 \sdram_we_n - attribute \src "ls180.v:2763.6-2763.15" + attribute \src "ls180.v:2674.6-2674.15" wire \sdrio_clk - attribute \src "ls180.v:2764.6-2764.17" + attribute \src "ls180.v:2675.6-2675.17" wire \sdrio_clk_1 - attribute \src "ls180.v:2773.6-2773.18" + attribute \src "ls180.v:2684.6-2684.18" wire \sdrio_clk_10 - attribute \src "ls180.v:2774.6-2774.18" + attribute \src "ls180.v:2685.6-2685.18" wire \sdrio_clk_11 - attribute \src "ls180.v:2775.6-2775.18" + attribute \src "ls180.v:2686.6-2686.18" wire \sdrio_clk_12 - attribute \src "ls180.v:2776.6-2776.18" + attribute \src "ls180.v:2687.6-2687.18" wire \sdrio_clk_13 - attribute \src "ls180.v:2777.6-2777.18" + attribute \src "ls180.v:2688.6-2688.18" wire \sdrio_clk_14 - attribute \src "ls180.v:2778.6-2778.18" + attribute \src "ls180.v:2689.6-2689.18" wire \sdrio_clk_15 - attribute \src "ls180.v:2779.6-2779.18" + attribute \src "ls180.v:2690.6-2690.18" wire \sdrio_clk_16 - attribute \src "ls180.v:2780.6-2780.18" + attribute \src "ls180.v:2691.6-2691.18" wire \sdrio_clk_17 - attribute \src "ls180.v:2781.6-2781.18" + attribute \src "ls180.v:2692.6-2692.18" wire \sdrio_clk_18 - attribute \src "ls180.v:2782.6-2782.18" + attribute \src "ls180.v:2693.6-2693.18" wire \sdrio_clk_19 - attribute \src "ls180.v:2765.6-2765.17" + attribute \src "ls180.v:2676.6-2676.17" wire \sdrio_clk_2 - attribute \src "ls180.v:2783.6-2783.18" + attribute \src "ls180.v:2694.6-2694.18" wire \sdrio_clk_20 - attribute \src "ls180.v:2784.6-2784.18" + attribute \src "ls180.v:2695.6-2695.18" wire \sdrio_clk_21 - attribute \src "ls180.v:2785.6-2785.18" + attribute \src "ls180.v:2696.6-2696.18" wire \sdrio_clk_22 - attribute \src "ls180.v:2786.6-2786.18" + attribute \src "ls180.v:2697.6-2697.18" wire \sdrio_clk_23 - attribute \src "ls180.v:2787.6-2787.18" + attribute \src "ls180.v:2698.6-2698.18" wire \sdrio_clk_24 - attribute \src "ls180.v:2788.6-2788.18" + attribute \src "ls180.v:2699.6-2699.18" wire \sdrio_clk_25 - attribute \src "ls180.v:2789.6-2789.18" + attribute \src "ls180.v:2700.6-2700.18" wire \sdrio_clk_26 - attribute \src "ls180.v:2790.6-2790.18" + attribute \src "ls180.v:2701.6-2701.18" wire \sdrio_clk_27 - attribute \src "ls180.v:2791.6-2791.18" + attribute \src "ls180.v:2702.6-2702.18" wire \sdrio_clk_28 - attribute \src "ls180.v:2792.6-2792.18" + attribute \src "ls180.v:2703.6-2703.18" wire \sdrio_clk_29 - attribute \src "ls180.v:2766.6-2766.17" + attribute \src "ls180.v:2677.6-2677.17" wire \sdrio_clk_3 - attribute \src "ls180.v:2793.6-2793.18" + attribute \src "ls180.v:2704.6-2704.18" wire \sdrio_clk_30 - attribute \src "ls180.v:2794.6-2794.18" + attribute \src "ls180.v:2705.6-2705.18" wire \sdrio_clk_31 - attribute \src "ls180.v:2795.6-2795.18" + attribute \src "ls180.v:2706.6-2706.18" wire \sdrio_clk_32 - attribute \src "ls180.v:2796.6-2796.18" + attribute \src "ls180.v:2707.6-2707.18" wire \sdrio_clk_33 - attribute \src "ls180.v:2797.6-2797.18" + attribute \src "ls180.v:2708.6-2708.18" wire \sdrio_clk_34 - attribute \src "ls180.v:2798.6-2798.18" + attribute \src "ls180.v:2709.6-2709.18" wire \sdrio_clk_35 - attribute \src "ls180.v:2799.6-2799.18" + attribute \src "ls180.v:2710.6-2710.18" wire \sdrio_clk_36 - attribute \src "ls180.v:2800.6-2800.18" + attribute \src "ls180.v:2711.6-2711.18" wire \sdrio_clk_37 - attribute \src "ls180.v:2801.6-2801.18" + attribute \src "ls180.v:2712.6-2712.18" wire \sdrio_clk_38 - attribute \src "ls180.v:2802.6-2802.18" + attribute \src "ls180.v:2713.6-2713.18" wire \sdrio_clk_39 - attribute \src "ls180.v:2767.6-2767.17" + attribute \src "ls180.v:2678.6-2678.17" wire \sdrio_clk_4 - attribute \src "ls180.v:2803.6-2803.18" + attribute \src "ls180.v:2714.6-2714.18" wire \sdrio_clk_40 - attribute \src "ls180.v:2804.6-2804.18" + attribute \src "ls180.v:2715.6-2715.18" wire \sdrio_clk_41 - attribute \src "ls180.v:2805.6-2805.18" + attribute \src "ls180.v:2716.6-2716.18" wire \sdrio_clk_42 - attribute \src "ls180.v:2806.6-2806.18" + attribute \src "ls180.v:2717.6-2717.18" wire \sdrio_clk_43 - attribute \src "ls180.v:2807.6-2807.18" + attribute \src "ls180.v:2718.6-2718.18" wire \sdrio_clk_44 - attribute \src "ls180.v:2808.6-2808.18" + attribute \src "ls180.v:2719.6-2719.18" wire \sdrio_clk_45 - attribute \src "ls180.v:2809.6-2809.18" + attribute \src "ls180.v:2720.6-2720.18" wire \sdrio_clk_46 - attribute \src "ls180.v:2810.6-2810.18" + attribute \src "ls180.v:2721.6-2721.18" wire \sdrio_clk_47 - attribute \src "ls180.v:2811.6-2811.18" + attribute \src "ls180.v:2722.6-2722.18" wire \sdrio_clk_48 - attribute \src "ls180.v:2812.6-2812.18" + attribute \src "ls180.v:2723.6-2723.18" wire \sdrio_clk_49 - attribute \src "ls180.v:2768.6-2768.17" + attribute \src "ls180.v:2679.6-2679.17" wire \sdrio_clk_5 - attribute \src "ls180.v:2813.6-2813.18" + attribute \src "ls180.v:2724.6-2724.18" wire \sdrio_clk_50 - attribute \src "ls180.v:2814.6-2814.18" + attribute \src "ls180.v:2725.6-2725.18" wire \sdrio_clk_51 - attribute \src "ls180.v:2815.6-2815.18" + attribute \src "ls180.v:2726.6-2726.18" wire \sdrio_clk_52 - attribute \src "ls180.v:2816.6-2816.18" + attribute \src "ls180.v:2727.6-2727.18" wire \sdrio_clk_53 - attribute \src "ls180.v:2817.6-2817.18" + attribute \src "ls180.v:2728.6-2728.18" wire \sdrio_clk_54 - attribute \src "ls180.v:2818.6-2818.18" + attribute \src "ls180.v:2729.6-2729.18" wire \sdrio_clk_55 - attribute \src "ls180.v:2853.6-2853.18" + attribute \src "ls180.v:2764.6-2764.18" wire \sdrio_clk_56 - attribute \src "ls180.v:2854.6-2854.18" + attribute \src "ls180.v:2765.6-2765.18" wire \sdrio_clk_57 - attribute \src "ls180.v:2855.6-2855.18" + attribute \src "ls180.v:2766.6-2766.18" wire \sdrio_clk_58 - attribute \src "ls180.v:2856.6-2856.18" + attribute \src "ls180.v:2767.6-2767.18" wire \sdrio_clk_59 - attribute \src "ls180.v:2769.6-2769.17" + attribute \src "ls180.v:2680.6-2680.17" wire \sdrio_clk_6 - attribute \src "ls180.v:2857.6-2857.18" + attribute \src "ls180.v:2768.6-2768.18" wire \sdrio_clk_60 - attribute \src "ls180.v:2858.6-2858.18" + attribute \src "ls180.v:2769.6-2769.18" wire \sdrio_clk_61 - attribute \src "ls180.v:2859.6-2859.18" + attribute \src "ls180.v:2770.6-2770.18" wire \sdrio_clk_62 - attribute \src "ls180.v:2860.6-2860.18" + attribute \src "ls180.v:2771.6-2771.18" wire \sdrio_clk_63 - attribute \src "ls180.v:2861.6-2861.18" + attribute \src "ls180.v:2772.6-2772.18" wire \sdrio_clk_64 - attribute \src "ls180.v:2862.6-2862.18" + attribute \src "ls180.v:2773.6-2773.18" wire \sdrio_clk_65 - attribute \src "ls180.v:2863.6-2863.18" + attribute \src "ls180.v:2774.6-2774.18" wire \sdrio_clk_66 - attribute \src "ls180.v:2864.6-2864.18" + attribute \src "ls180.v:2775.6-2775.18" wire \sdrio_clk_67 - attribute \src "ls180.v:2865.6-2865.18" + attribute \src "ls180.v:2776.6-2776.18" wire \sdrio_clk_68 - attribute \src "ls180.v:2770.6-2770.17" + attribute \src "ls180.v:2681.6-2681.17" wire \sdrio_clk_7 - attribute \src "ls180.v:2771.6-2771.17" + attribute \src "ls180.v:2682.6-2682.17" wire \sdrio_clk_8 - attribute \src "ls180.v:2772.6-2772.17" + attribute \src "ls180.v:2683.6-2683.17" wire \sdrio_clk_9 + attribute \src "ls180.v:38.13-38.26" + wire output 34 \spimaster_clk + attribute \src "ls180.v:40.13-40.27" + wire output 36 \spimaster_cs_n + attribute \src "ls180.v:41.13-41.27" + wire input 37 \spimaster_miso + attribute \src "ls180.v:39.13-39.27" + wire output 35 \spimaster_mosi attribute \src "ls180.v:18.13-18.26" - wire output 14 \spimaster_clk + wire output 14 \spisdcard_clk attribute \src "ls180.v:20.13-20.27" - wire output 16 \spimaster_cs_n + wire output 16 \spisdcard_cs_n attribute \src "ls180.v:21.13-21.27" - wire input 17 \spimaster_miso + wire input 17 \spisdcard_miso attribute \src "ls180.v:19.13-19.27" - wire output 15 \spimaster_mosi - attribute \src "ls180.v:12.13-12.26" - wire output 8 \spisdcard_clk - attribute \src "ls180.v:14.13-14.27" - wire output 10 \spisdcard_cs_n - attribute \src "ls180.v:15.13-15.27" - wire input 11 \spisdcard_miso - attribute \src "ls180.v:13.13-13.27" - wire output 9 \spisdcard_mosi + wire output 15 \spisdcard_mosi attribute \src "ls180.v:43.13-43.20" wire input 39 \sys_clk - attribute \src "ls180.v:339.6-339.15" + attribute \src "ls180.v:250.6-250.15" wire \sys_clk_1 attribute \src "ls180.v:45.19-45.31" wire width 2 input 41 \sys_clksel_i @@ -254547,40 +253787,34 @@ module \ls180 wire output 43 \sys_pll_lck_o attribute \src "ls180.v:44.13-44.20" wire input 40 \sys_rst - attribute \src "ls180.v:340.6-340.15" + attribute \src "ls180.v:251.6-251.15" wire \sys_rst_1 - attribute \src "ls180.v:35.13-35.20" - wire input 31 \uart_rx - attribute \src "ls180.v:34.13-34.20" - wire output 30 \uart_tx - attribute \src "ls180.v:10351.12-10351.15" - memory width 64 size 64 \mem - attribute \src "ls180.v:10379.12-10379.17" - memory width 64 size 64 \mem_1 - attribute \src "ls180.v:10407.12-10407.17" - memory width 64 size 64 \mem_2 - attribute \src "ls180.v:10435.12-10435.17" - memory width 64 size 64 \mem_3 - attribute \src "ls180.v:10463.12-10463.17" - memory width 64 size 64 \mem_4 - attribute \src "ls180.v:10491.12-10491.19" + attribute \src "ls180.v:6.13-6.20" + wire input 2 \uart_rx + attribute \src "ls180.v:5.13-5.20" + wire output 1 \uart_tx + attribute \src "ls180.v:10142.12-10142.15" + memory width 64 size 16 \mem + attribute \src "ls180.v:10170.12-10170.17" + memory width 64 size 16 \mem_1 + attribute \src "ls180.v:10198.12-10198.19" memory width 25 size 8 \storage - attribute \src "ls180.v:10505.12-10505.21" + attribute \src "ls180.v:10212.12-10212.21" memory width 25 size 8 \storage_1 - attribute \src "ls180.v:10519.12-10519.21" + attribute \src "ls180.v:10226.12-10226.21" memory width 25 size 8 \storage_2 - attribute \src "ls180.v:10533.12-10533.21" + attribute \src "ls180.v:10240.12-10240.21" memory width 25 size 8 \storage_3 - attribute \src "ls180.v:10547.11-10547.20" + attribute \src "ls180.v:10254.11-10254.20" memory width 10 size 16 \storage_4 - attribute \src "ls180.v:10564.11-10564.20" + attribute \src "ls180.v:10271.11-10271.20" memory width 10 size 16 \storage_5 - attribute \src "ls180.v:10581.11-10581.20" + attribute \src "ls180.v:10288.11-10288.20" memory width 10 size 32 \storage_6 - attribute \src "ls180.v:10595.11-10595.20" + attribute \src "ls180.v:10302.11-10302.20" memory width 10 size 32 \storage_7 - attribute \src "ls180.v:2935.56-2935.86" - cell $add $add$ls180.v:2935$58 + attribute \src "ls180.v:2846.56-2846.86" + cell $add $add$ls180.v:2846$34 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254588,10 +253822,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter0_counter connect \B 1'1 - connect \Y $add$ls180.v:2935$58_Y + connect \Y $add$ls180.v:2846$34_Y end - attribute \src "ls180.v:2995.56-2995.86" - cell $add $add$ls180.v:2995$69 + attribute \src "ls180.v:2906.56-2906.86" + cell $add $add$ls180.v:2906$45 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254599,10 +253833,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter1_counter connect \B 1'1 - connect \Y $add$ls180.v:2995$69_Y + connect \Y $add$ls180.v:2906$45_Y end - attribute \src "ls180.v:3055.59-3055.92" - cell $add $add$ls180.v:3055$80 + attribute \src "ls180.v:2966.59-2966.92" + cell $add $add$ls180.v:2966$56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254610,10 +253844,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_socbushandler_counter connect \B 1'1 - connect \Y $add$ls180.v:3055$80_Y + connect \Y $add$ls180.v:2966$56_Y end - attribute \src "ls180.v:4248.54-4248.83" - cell $add $add$ls180.v:4248$685 + attribute \src "ls180.v:4117.54-4117.83" + cell $add $add$ls180.v:4117$586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -254621,10 +253855,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter_counter connect \B 1'1 - connect \Y $add$ls180.v:4248$685_Y + connect \Y $add$ls180.v:4117$586_Y end - attribute \src "ls180.v:4348.36-4348.89" - cell $add $add$ls180.v:4348$731 + attribute \src "ls180.v:4217.36-4217.89" + cell $add $add$ls180.v:4217$632 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -254632,10 +253866,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B \main_uart_tx_fifo_readable - connect \Y $add$ls180.v:4348$731_Y + connect \Y $add$ls180.v:4217$632_Y end - attribute \src "ls180.v:4378.36-4378.89" - cell $add $add$ls180.v:4378$742 + attribute \src "ls180.v:4247.36-4247.89" + cell $add $add$ls180.v:4247$643 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -254643,10 +253877,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B \main_uart_rx_fifo_readable - connect \Y $add$ls180.v:4378$742_Y + connect \Y $add$ls180.v:4247$643_Y end - attribute \src "ls180.v:4444.54-4444.83" - cell $add $add$ls180.v:4444$757 + attribute \src "ls180.v:4313.54-4313.83" + cell $add $add$ls180.v:4313$658 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254654,10 +253888,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spimaster27_count connect \B 1'1 - connect \Y $add$ls180.v:4444$757_Y + connect \Y $add$ls180.v:4313$658_Y end - attribute \src "ls180.v:4503.52-4503.79" - cell $add $add$ls180.v:4503$765 + attribute \src "ls180.v:4372.52-4372.79" + cell $add $add$ls180.v:4372$666 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254665,10 +253899,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spisdcard_count connect \B 1'1 - connect \Y $add$ls180.v:4503$765_Y + connect \Y $add$ls180.v:4372$666_Y end - attribute \src "ls180.v:4607.58-4607.86" - cell $add $add$ls180.v:4607$793 + attribute \src "ls180.v:4476.58-4476.86" + cell $add $add$ls180.v:4476$694 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -254676,10 +253910,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_init_count connect \B 1'1 - connect \Y $add$ls180.v:4607$793_Y + connect \Y $add$ls180.v:4476$694_Y end - attribute \src "ls180.v:4664.58-4664.86" - cell $add $add$ls180.v:4664$796 + attribute \src "ls180.v:4533.58-4533.86" + cell $add $add$ls180.v:4533$697 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -254687,10 +253921,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdw_count connect \B 1'1 - connect \Y $add$ls180.v:4664$796_Y + connect \Y $add$ls180.v:4533$697_Y end - attribute \src "ls180.v:4681.58-4681.86" - cell $add $add$ls180.v:4681$798 + attribute \src "ls180.v:4550.58-4550.86" + cell $add $add$ls180.v:4550$699 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -254698,10 +253932,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdw_count connect \B 1'1 - connect \Y $add$ls180.v:4681$798_Y + connect \Y $add$ls180.v:4550$699_Y end - attribute \src "ls180.v:4774.59-4774.87" - cell $add $add$ls180.v:4774$815 + attribute \src "ls180.v:4643.59-4643.87" + cell $add $add$ls180.v:4643$716 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -254709,10 +253943,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_count connect \B 1'1 - connect \Y $add$ls180.v:4774$815_Y + connect \Y $add$ls180.v:4643$716_Y end - attribute \src "ls180.v:4799.59-4799.87" - cell $add $add$ls180.v:4799$818 + attribute \src "ls180.v:4668.59-4668.87" + cell $add $add$ls180.v:4668$719 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -254720,10 +253954,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_count connect \B 1'1 - connect \Y $add$ls180.v:4799$818_Y + connect \Y $add$ls180.v:4668$719_Y end - attribute \src "ls180.v:4921.53-4921.82" - cell $add $add$ls180.v:4921$835 + attribute \src "ls180.v:4790.53-4790.82" + cell $add $add$ls180.v:4790$736 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -254731,10 +253965,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_dataw_count connect \B 1'1 - connect \Y $add$ls180.v:4921$835_Y + connect \Y $add$ls180.v:4790$736_Y end - attribute \src "ls180.v:5032.65-5032.114" - cell $add $add$ls180.v:5032$849 + attribute \src "ls180.v:4901.65-4901.114" + cell $add $add$ls180.v:4901$750 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -254742,10 +253976,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_sink_payload_block_length connect \B 4'1000 - connect \Y $add$ls180.v:5032$849_Y + connect \Y $add$ls180.v:4901$750_Y end - attribute \src "ls180.v:5037.62-5037.91" - cell $add $add$ls180.v:5037$852 + attribute \src "ls180.v:4906.62-4906.91" + cell $add $add$ls180.v:4906$753 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -254753,10 +253987,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_count connect \B 1'1 - connect \Y $add$ls180.v:5037$852_Y + connect \Y $add$ls180.v:4906$753_Y end - attribute \src "ls180.v:5063.61-5063.90" - cell $add $add$ls180.v:5063$855 + attribute \src "ls180.v:4932.61-4932.90" + cell $add $add$ls180.v:4932$756 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -254764,10 +253998,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdphy_datar_count connect \B 1'1 - connect \Y $add$ls180.v:5063$855_Y + connect \Y $add$ls180.v:4932$756_Y end - attribute \src "ls180.v:5267.80-5267.117" - cell $add $add$ls180.v:5267$1040 + attribute \src "ls180.v:5136.80-5136.117" + cell $add $add$ls180.v:5136$941 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254775,10 +254009,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdcore_crc16_inserter_cnt connect \B 1'1 - connect \Y $add$ls180.v:5267$1040_Y + connect \Y $add$ls180.v:5136$941_Y end - attribute \src "ls180.v:5461.54-5461.82" - cell $add $add$ls180.v:5461$1115 + attribute \src "ls180.v:5330.54-5330.82" + cell $add $add$ls180.v:5330$1016 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254786,10 +254020,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdcore_cmd_count connect \B 1'1 - connect \Y $add$ls180.v:5461$1115_Y + connect \Y $add$ls180.v:5330$1016_Y end - attribute \src "ls180.v:5513.55-5513.84" - cell $add $add$ls180.v:5513$1125 + attribute \src "ls180.v:5382.55-5382.84" + cell $add $add$ls180.v:5382$1026 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254797,10 +254031,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_data_count connect \B 1'1 - connect \Y $add$ls180.v:5513$1125_Y + connect \Y $add$ls180.v:5382$1026_Y end - attribute \src "ls180.v:5539.57-5539.86" - cell $add $add$ls180.v:5539$1133 + attribute \src "ls180.v:5408.57-5408.86" + cell $add $add$ls180.v:5408$1034 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254808,10 +254042,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_data_count connect \B 1'1 - connect \Y $add$ls180.v:5539$1133_Y + connect \Y $add$ls180.v:5408$1034_Y end - attribute \src "ls180.v:5660.51-5660.134" - cell $add $add$ls180.v:5660$1149 + attribute \src "ls180.v:5529.51-5529.134" + cell $add $add$ls180.v:5529$1050 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254819,10 +254053,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_base connect \B \main_sdblock2mem_wishbonedmawriter_offset - connect \Y $add$ls180.v:5660$1149_Y + connect \Y $add$ls180.v:5529$1050_Y end - attribute \src "ls180.v:5663.77-5663.125" - cell $add $add$ls180.v:5663$1151 + attribute \src "ls180.v:5532.77-5532.125" + cell $add $add$ls180.v:5532$1052 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254830,10 +254064,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_offset connect \B 1'1 - connect \Y $add$ls180.v:5663$1151_Y + connect \Y $add$ls180.v:5532$1052_Y end - attribute \src "ls180.v:5756.50-5756.105" - cell $add $add$ls180.v:5756$1160 + attribute \src "ls180.v:5625.50-5625.105" + cell $add $add$ls180.v:5625$1061 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254841,10 +254075,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_base connect \B \main_sdmem2block_dma_offset - connect \Y $add$ls180.v:5756$1160_Y + connect \Y $add$ls180.v:5625$1061_Y end - attribute \src "ls180.v:5758.77-5758.111" - cell $add $add$ls180.v:5758$1161 + attribute \src "ls180.v:5627.77-5627.111" + cell $add $add$ls180.v:5627$1062 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254852,10 +254086,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_offset connect \B 1'1 - connect \Y $add$ls180.v:5758$1161_Y + connect \Y $add$ls180.v:5627$1062_Y end - attribute \src "ls180.v:7765.36-7765.70" - cell $add $add$ls180.v:7765$2604 + attribute \src "ls180.v:7571.36-7571.70" + cell $add $add$ls180.v:7571$2463 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -254863,10 +254097,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_bus_errors connect \B 1'1 - connect \Y $add$ls180.v:7765$2604_Y + connect \Y $add$ls180.v:7571$2463_Y end - attribute \src "ls180.v:7866.37-7866.72" - cell $add $add$ls180.v:7866$2637 + attribute \src "ls180.v:7660.37-7660.72" + cell $add $add$ls180.v:7660$2487 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254874,10 +254108,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_sequencer_counter connect \B 1'1 - connect \Y $add$ls180.v:7866$2637_Y + connect \Y $add$ls180.v:7660$2487_Y end - attribute \src "ls180.v:7883.60-7883.119" - cell $add $add$ls180.v:7883$2641 + attribute \src "ls180.v:7677.60-7677.119" + cell $add $add$ls180.v:7677$2491 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254885,10 +254119,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7883$2641_Y + connect \Y $add$ls180.v:7677$2491_Y end - attribute \src "ls180.v:7886.60-7886.119" - cell $add $add$ls180.v:7886$2642 + attribute \src "ls180.v:7680.60-7680.119" + cell $add $add$ls180.v:7680$2492 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254896,10 +254130,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7886$2642_Y + connect \Y $add$ls180.v:7680$2492_Y end - attribute \src "ls180.v:7890.59-7890.116" - cell $add $add$ls180.v:7890$2647 + attribute \src "ls180.v:7684.59-7684.116" + cell $add $add$ls180.v:7684$2497 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254907,10 +254141,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7890$2647_Y + connect \Y $add$ls180.v:7684$2497_Y end - attribute \src "ls180.v:7929.60-7929.119" - cell $add $add$ls180.v:7929$2657 + attribute \src "ls180.v:7723.60-7723.119" + cell $add $add$ls180.v:7723$2507 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254918,10 +254152,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7929$2657_Y + connect \Y $add$ls180.v:7723$2507_Y end - attribute \src "ls180.v:7932.60-7932.119" - cell $add $add$ls180.v:7932$2658 + attribute \src "ls180.v:7726.60-7726.119" + cell $add $add$ls180.v:7726$2508 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254929,10 +254163,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7932$2658_Y + connect \Y $add$ls180.v:7726$2508_Y end - attribute \src "ls180.v:7936.59-7936.116" - cell $add $add$ls180.v:7936$2663 + attribute \src "ls180.v:7730.59-7730.116" + cell $add $add$ls180.v:7730$2513 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254940,10 +254174,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7936$2663_Y + connect \Y $add$ls180.v:7730$2513_Y end - attribute \src "ls180.v:7975.60-7975.119" - cell $add $add$ls180.v:7975$2673 + attribute \src "ls180.v:7769.60-7769.119" + cell $add $add$ls180.v:7769$2523 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254951,10 +254185,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7975$2673_Y + connect \Y $add$ls180.v:7769$2523_Y end - attribute \src "ls180.v:7978.60-7978.119" - cell $add $add$ls180.v:7978$2674 + attribute \src "ls180.v:7772.60-7772.119" + cell $add $add$ls180.v:7772$2524 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254962,10 +254196,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7978$2674_Y + connect \Y $add$ls180.v:7772$2524_Y end - attribute \src "ls180.v:7982.59-7982.116" - cell $add $add$ls180.v:7982$2679 + attribute \src "ls180.v:7776.59-7776.116" + cell $add $add$ls180.v:7776$2529 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -254973,10 +254207,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7982$2679_Y + connect \Y $add$ls180.v:7776$2529_Y end - attribute \src "ls180.v:8021.60-8021.119" - cell $add $add$ls180.v:8021$2689 + attribute \src "ls180.v:7815.60-7815.119" + cell $add $add$ls180.v:7815$2539 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254984,10 +254218,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:8021$2689_Y + connect \Y $add$ls180.v:7815$2539_Y end - attribute \src "ls180.v:8024.60-8024.119" - cell $add $add$ls180.v:8024$2690 + attribute \src "ls180.v:7818.60-7818.119" + cell $add $add$ls180.v:7818$2540 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -254995,10 +254229,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:8024$2690_Y + connect \Y $add$ls180.v:7818$2540_Y end - attribute \src "ls180.v:8028.59-8028.116" - cell $add $add$ls180.v:8028$2695 + attribute \src "ls180.v:7822.59-7822.116" + cell $add $add$ls180.v:7822$2545 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255006,10 +254240,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:8028$2695_Y + connect \Y $add$ls180.v:7822$2545_Y end - attribute \src "ls180.v:8258.34-8258.66" - cell $add $add$ls180.v:8258$2749 + attribute \src "ls180.v:8052.34-8052.66" + cell $add $add$ls180.v:8052$2599 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255017,10 +254251,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_phy_tx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:8258$2749_Y + connect \Y $add$ls180.v:8052$2599_Y end - attribute \src "ls180.v:8274.73-8274.131" - cell $add $add$ls180.v:8274$2752 + attribute \src "ls180.v:8068.73-8068.131" + cell $add $add$ls180.v:8068$2602 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255028,10 +254262,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \main_uart_phy_phase_accumulator_tx connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8274$2752_Y + connect \Y $add$ls180.v:8068$2602_Y end - attribute \src "ls180.v:8287.34-8287.66" - cell $add $add$ls180.v:8287$2756 + attribute \src "ls180.v:8081.34-8081.66" + cell $add $add$ls180.v:8081$2606 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255039,10 +254273,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_phy_rx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:8287$2756_Y + connect \Y $add$ls180.v:8081$2606_Y end - attribute \src "ls180.v:8306.73-8306.131" - cell $add $add$ls180.v:8306$2759 + attribute \src "ls180.v:8100.73-8100.131" + cell $add $add$ls180.v:8100$2609 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255050,10 +254284,10 @@ module \ls180 parameter \Y_WIDTH 33 connect \A \main_uart_phy_phase_accumulator_rx connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8306$2759_Y + connect \Y $add$ls180.v:8100$2609_Y end - attribute \src "ls180.v:8332.33-8332.65" - cell $add $add$ls180.v:8332$2767 + attribute \src "ls180.v:8126.33-8126.65" + cell $add $add$ls180.v:8126$2617 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255061,10 +254295,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8332$2767_Y + connect \Y $add$ls180.v:8126$2617_Y end - attribute \src "ls180.v:8335.33-8335.65" - cell $add $add$ls180.v:8335$2768 + attribute \src "ls180.v:8129.33-8129.65" + cell $add $add$ls180.v:8129$2618 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255072,10 +254306,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8335$2768_Y + connect \Y $add$ls180.v:8129$2618_Y end - attribute \src "ls180.v:8339.33-8339.64" - cell $add $add$ls180.v:8339$2773 + attribute \src "ls180.v:8133.33-8133.64" + cell $add $add$ls180.v:8133$2623 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255083,10 +254317,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8339$2773_Y + connect \Y $add$ls180.v:8133$2623_Y end - attribute \src "ls180.v:8354.33-8354.65" - cell $add $add$ls180.v:8354$2778 + attribute \src "ls180.v:8148.33-8148.65" + cell $add $add$ls180.v:8148$2628 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255094,10 +254328,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8354$2778_Y + connect \Y $add$ls180.v:8148$2628_Y end - attribute \src "ls180.v:8357.33-8357.65" - cell $add $add$ls180.v:8357$2779 + attribute \src "ls180.v:8151.33-8151.65" + cell $add $add$ls180.v:8151$2629 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255105,10 +254339,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8357$2779_Y + connect \Y $add$ls180.v:8151$2629_Y end - attribute \src "ls180.v:8361.33-8361.64" - cell $add $add$ls180.v:8361$2784 + attribute \src "ls180.v:8155.33-8155.64" + cell $add $add$ls180.v:8155$2634 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255116,10 +254350,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8361$2784_Y + connect \Y $add$ls180.v:8155$2634_Y end - attribute \src "ls180.v:8382.35-8382.70" - cell $add $add$ls180.v:8382$2786 + attribute \src "ls180.v:8176.35-8176.70" + cell $add $add$ls180.v:8176$2636 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -255127,10 +254361,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spimaster30_clk_divider connect \B 1'1 - connect \Y $add$ls180.v:8382$2786_Y + connect \Y $add$ls180.v:8176$2636_Y end - attribute \src "ls180.v:8417.34-8417.68" - cell $add $add$ls180.v:8417$2791 + attribute \src "ls180.v:8211.34-8211.68" + cell $add $add$ls180.v:8211$2641 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -255138,10 +254372,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spisdcard_clk_divider1 connect \B 1'1 - connect \Y $add$ls180.v:8417$2791_Y + connect \Y $add$ls180.v:8211$2641_Y end - attribute \src "ls180.v:8453.25-8453.49" - cell $add $add$ls180.v:8453$2796 + attribute \src "ls180.v:8247.25-8247.49" + cell $add $add$ls180.v:8247$2646 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255149,10 +254383,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_counter connect \B 1'1 - connect \Y $add$ls180.v:8453$2796_Y + connect \Y $add$ls180.v:8247$2646_Y end - attribute \src "ls180.v:8467.25-8467.49" - cell $add $add$ls180.v:8467$2800 + attribute \src "ls180.v:8261.25-8261.49" + cell $add $add$ls180.v:8261$2650 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -255160,10 +254394,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_counter connect \B 1'1 - connect \Y $add$ls180.v:8467$2800_Y + connect \Y $add$ls180.v:8261$2650_Y end - attribute \src "ls180.v:8481.31-8481.61" - cell $add $add$ls180.v:8481$2805 + attribute \src "ls180.v:8275.31-8275.61" + cell $add $add$ls180.v:8275$2655 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \B_SIGNED 0 @@ -255171,10 +254405,10 @@ module \ls180 parameter \Y_WIDTH 9 connect \A \main_sdphy_clocker_clks connect \B 1'1 - connect \Y $add$ls180.v:8481$2805_Y + connect \Y $add$ls180.v:8275$2655_Y end - attribute \src "ls180.v:8504.45-8504.88" - cell $add $add$ls180.v:8504$2809 + attribute \src "ls180.v:8298.45-8298.88" + cell $add $add$ls180.v:8298$2659 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255182,10 +254416,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8504$2809_Y + connect \Y $add$ls180.v:8298$2659_Y end - attribute \src "ls180.v:8550.71-8550.114" - cell $add $add$ls180.v:8550$2815 + attribute \src "ls180.v:8344.71-8344.114" + cell $add $add$ls180.v:8344$2665 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255193,10 +254427,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8550$2815_Y + connect \Y $add$ls180.v:8344$2665_Y end - attribute \src "ls180.v:8585.46-8585.90" - cell $add $add$ls180.v:8585$2821 + attribute \src "ls180.v:8379.46-8379.90" + cell $add $add$ls180.v:8379$2671 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255204,10 +254438,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8585$2821_Y + connect \Y $add$ls180.v:8379$2671_Y end - attribute \src "ls180.v:8631.72-8631.116" - cell $add $add$ls180.v:8631$2827 + attribute \src "ls180.v:8425.72-8425.116" + cell $add $add$ls180.v:8425$2677 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255215,10 +254449,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8631$2827_Y + connect \Y $add$ls180.v:8425$2677_Y end - attribute \src "ls180.v:8664.47-8664.92" - cell $add $add$ls180.v:8664$2833 + attribute \src "ls180.v:8458.47-8458.92" + cell $add $add$ls180.v:8458$2683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255226,10 +254460,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8664$2833_Y + connect \Y $add$ls180.v:8458$2683_Y end - attribute \src "ls180.v:8692.73-8692.118" - cell $add $add$ls180.v:8692$2839 + attribute \src "ls180.v:8486.73-8486.118" + cell $add $add$ls180.v:8486$2689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255237,10 +254471,10 @@ module \ls180 parameter \Y_WIDTH 2 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8692$2839_Y + connect \Y $add$ls180.v:8486$2689_Y end - attribute \src "ls180.v:8804.39-8804.75" - cell $add $add$ls180.v:8804$2852 + attribute \src "ls180.v:8598.39-8598.75" + cell $add $add$ls180.v:8598$2702 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -255248,10 +254482,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdcore_crc16_checker_cnt connect \B 1'1 - connect \Y $add$ls180.v:8804$2852_Y + connect \Y $add$ls180.v:8598$2702_Y end - attribute \src "ls180.v:8865.37-8865.73" - cell $add $add$ls180.v:8865$2856 + attribute \src "ls180.v:8659.37-8659.73" + cell $add $add$ls180.v:8659$2706 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255259,10 +254493,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8865$2856_Y + connect \Y $add$ls180.v:8659$2706_Y end - attribute \src "ls180.v:8868.37-8868.73" - cell $add $add$ls180.v:8868$2857 + attribute \src "ls180.v:8662.37-8662.73" + cell $add $add$ls180.v:8662$2707 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255270,10 +254504,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8868$2857_Y + connect \Y $add$ls180.v:8662$2707_Y end - attribute \src "ls180.v:8872.36-8872.70" - cell $add $add$ls180.v:8872$2862 + attribute \src "ls180.v:8666.36-8666.70" + cell $add $add$ls180.v:8666$2712 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -255281,10 +254515,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8872$2862_Y + connect \Y $add$ls180.v:8666$2712_Y end - attribute \src "ls180.v:8887.41-8887.80" - cell $add $add$ls180.v:8887$2866 + attribute \src "ls180.v:8681.41-8681.80" + cell $add $add$ls180.v:8681$2716 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255292,10 +254526,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8887$2866_Y + connect \Y $add$ls180.v:8681$2716_Y end - attribute \src "ls180.v:8933.67-8933.106" - cell $add $add$ls180.v:8933$2872 + attribute \src "ls180.v:8727.67-8727.106" + cell $add $add$ls180.v:8727$2722 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255303,10 +254537,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdblock2mem_converter_demux connect \B 1'1 - connect \Y $add$ls180.v:8933$2872_Y + connect \Y $add$ls180.v:8727$2722_Y end - attribute \src "ls180.v:8959.39-8959.76" - cell $add $add$ls180.v:8959$2874 + attribute \src "ls180.v:8753.39-8753.76" + cell $add $add$ls180.v:8753$2724 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -255314,10 +254548,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdmem2block_converter_mux connect \B 1'1 - connect \Y $add$ls180.v:8959$2874_Y + connect \Y $add$ls180.v:8753$2724_Y end - attribute \src "ls180.v:8963.37-8963.73" - cell $add $add$ls180.v:8963$2878 + attribute \src "ls180.v:8757.37-8757.73" + cell $add $add$ls180.v:8757$2728 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255325,10 +254559,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8963$2878_Y + connect \Y $add$ls180.v:8757$2728_Y end - attribute \src "ls180.v:8966.37-8966.73" - cell $add $add$ls180.v:8966$2879 + attribute \src "ls180.v:8760.37-8760.73" + cell $add $add$ls180.v:8760$2729 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -255336,10 +254570,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8966$2879_Y + connect \Y $add$ls180.v:8760$2729_Y end - attribute \src "ls180.v:8970.36-8970.70" - cell $add $add$ls180.v:8970$2884 + attribute \src "ls180.v:8764.36-8764.70" + cell $add $add$ls180.v:8764$2734 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -255347,10 +254581,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $add$ls180.v:8970$2884_Y + connect \Y $add$ls180.v:8764$2734_Y end - attribute \src "ls180.v:2929.9-2929.90" - cell $and $and$ls180.v:2929$53 + attribute \src "ls180.v:2840.9-2840.90" + cell $and $and$ls180.v:2840$29 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255358,10 +254592,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_converted_interface_stb connect \B \main_interface0_converted_interface_cyc - connect \Y $and$ls180.v:2929$53_Y + connect \Y $and$ls180.v:2840$29_Y end - attribute \src "ls180.v:2947.9-2947.90" - cell $and $and$ls180.v:2947$60 + attribute \src "ls180.v:2858.9-2858.90" + cell $and $and$ls180.v:2858$36 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255369,10 +254603,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface0_converted_interface_stb connect \B \main_interface0_converted_interface_cyc - connect \Y $and$ls180.v:2947$60_Y + connect \Y $and$ls180.v:2858$36_Y end - attribute \src "ls180.v:2989.9-2989.90" - cell $and $and$ls180.v:2989$64 + attribute \src "ls180.v:2900.9-2900.90" + cell $and $and$ls180.v:2900$40 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255380,10 +254614,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_converted_interface_stb connect \B \main_interface1_converted_interface_cyc - connect \Y $and$ls180.v:2989$64_Y + connect \Y $and$ls180.v:2900$40_Y end - attribute \src "ls180.v:3007.9-3007.90" - cell $and $and$ls180.v:3007$71 + attribute \src "ls180.v:2918.9-2918.90" + cell $and $and$ls180.v:2918$47 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255391,10 +254625,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_converted_interface_stb connect \B \main_interface1_converted_interface_cyc - connect \Y $and$ls180.v:3007$71_Y + connect \Y $and$ls180.v:2918$47_Y end - attribute \src "ls180.v:3049.9-3049.96" - cell $and $and$ls180.v:3049$75 + attribute \src "ls180.v:2960.9-2960.96" + cell $and $and$ls180.v:2960$51 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255402,10 +254636,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_socbushandler_converted_interface_stb connect \B \main_socbushandler_converted_interface_cyc - connect \Y $and$ls180.v:3049$75_Y + connect \Y $and$ls180.v:2960$51_Y end - attribute \src "ls180.v:3067.9-3067.96" - cell $and $and$ls180.v:3067$82 + attribute \src "ls180.v:2978.9-2978.96" + cell $and $and$ls180.v:2978$58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255413,10 +254647,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_socbushandler_converted_interface_stb connect \B \main_socbushandler_converted_interface_cyc - connect \Y $and$ls180.v:3067$82_Y + connect \Y $and$ls180.v:2978$58_Y end - attribute \src "ls180.v:3077.31-3077.90" - cell $and $and$ls180.v:3077$84 + attribute \src "ls180.v:2988.31-2988.90" + cell $and $and$ls180.v:2988$60 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255424,32 +254658,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3077$84_Y + connect \Y $and$ls180.v:2988$60_Y end - attribute \src "ls180.v:3077.30-3077.121" - cell $and $and$ls180.v:3077$85 + attribute \src "ls180.v:2988.30-2988.121" + cell $and $and$ls180.v:2988$61 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3077$84_Y + connect \A $and$ls180.v:2988$60_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3077$85_Y + connect \Y $and$ls180.v:2988$61_Y end - attribute \src "ls180.v:3077.29-3077.156" - cell $and $and$ls180.v:3077$86 + attribute \src "ls180.v:2988.29-2988.156" + cell $and $and$ls180.v:2988$62 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3077$85_Y + connect \A $and$ls180.v:2988$61_Y connect \B \main_libresocsim_ram_bus_sel [0] - connect \Y $and$ls180.v:3077$86_Y + connect \Y $and$ls180.v:2988$62_Y end - attribute \src "ls180.v:3078.31-3078.90" - cell $and $and$ls180.v:3078$87 + attribute \src "ls180.v:2989.31-2989.90" + cell $and $and$ls180.v:2989$63 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255457,32 +254691,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3078$87_Y + connect \Y $and$ls180.v:2989$63_Y end - attribute \src "ls180.v:3078.30-3078.121" - cell $and $and$ls180.v:3078$88 + attribute \src "ls180.v:2989.30-2989.121" + cell $and $and$ls180.v:2989$64 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3078$87_Y + connect \A $and$ls180.v:2989$63_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3078$88_Y + connect \Y $and$ls180.v:2989$64_Y end - attribute \src "ls180.v:3078.29-3078.156" - cell $and $and$ls180.v:3078$89 + attribute \src "ls180.v:2989.29-2989.156" + cell $and $and$ls180.v:2989$65 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3078$88_Y + connect \A $and$ls180.v:2989$64_Y connect \B \main_libresocsim_ram_bus_sel [1] - connect \Y $and$ls180.v:3078$89_Y + connect \Y $and$ls180.v:2989$65_Y end - attribute \src "ls180.v:3079.31-3079.90" - cell $and $and$ls180.v:3079$90 + attribute \src "ls180.v:2990.31-2990.90" + cell $and $and$ls180.v:2990$66 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255490,32 +254724,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3079$90_Y + connect \Y $and$ls180.v:2990$66_Y end - attribute \src "ls180.v:3079.30-3079.121" - cell $and $and$ls180.v:3079$91 + attribute \src "ls180.v:2990.30-2990.121" + cell $and $and$ls180.v:2990$67 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3079$90_Y + connect \A $and$ls180.v:2990$66_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3079$91_Y + connect \Y $and$ls180.v:2990$67_Y end - attribute \src "ls180.v:3079.29-3079.156" - cell $and $and$ls180.v:3079$92 + attribute \src "ls180.v:2990.29-2990.156" + cell $and $and$ls180.v:2990$68 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3079$91_Y + connect \A $and$ls180.v:2990$67_Y connect \B \main_libresocsim_ram_bus_sel [2] - connect \Y $and$ls180.v:3079$92_Y + connect \Y $and$ls180.v:2990$68_Y end - attribute \src "ls180.v:3080.31-3080.90" - cell $and $and$ls180.v:3080$93 + attribute \src "ls180.v:2991.31-2991.90" + cell $and $and$ls180.v:2991$69 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255523,32 +254757,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3080$93_Y + connect \Y $and$ls180.v:2991$69_Y end - attribute \src "ls180.v:3080.30-3080.121" - cell $and $and$ls180.v:3080$94 + attribute \src "ls180.v:2991.30-2991.121" + cell $and $and$ls180.v:2991$70 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3080$93_Y + connect \A $and$ls180.v:2991$69_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3080$94_Y + connect \Y $and$ls180.v:2991$70_Y end - attribute \src "ls180.v:3080.29-3080.156" - cell $and $and$ls180.v:3080$95 + attribute \src "ls180.v:2991.29-2991.156" + cell $and $and$ls180.v:2991$71 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3080$94_Y + connect \A $and$ls180.v:2991$70_Y connect \B \main_libresocsim_ram_bus_sel [3] - connect \Y $and$ls180.v:3080$95_Y + connect \Y $and$ls180.v:2991$71_Y end - attribute \src "ls180.v:3081.31-3081.90" - cell $and $and$ls180.v:3081$96 + attribute \src "ls180.v:2992.31-2992.90" + cell $and $and$ls180.v:2992$72 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255556,65 +254790,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3081$96_Y + connect \Y $and$ls180.v:2992$72_Y end - attribute \src "ls180.v:3081.30-3081.121" - cell $and $and$ls180.v:3081$97 + attribute \src "ls180.v:2992.30-2992.121" + cell $and $and$ls180.v:2992$73 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3081$96_Y + connect \A $and$ls180.v:2992$72_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3081$97_Y + connect \Y $and$ls180.v:2992$73_Y end - attribute \src "ls180.v:3081.29-3081.156" - cell $and $and$ls180.v:3081$98 + attribute \src "ls180.v:2992.29-2992.156" + cell $and $and$ls180.v:2992$74 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3081$97_Y + connect \A $and$ls180.v:2992$73_Y connect \B \main_libresocsim_ram_bus_sel [4] - connect \Y $and$ls180.v:3081$98_Y + connect \Y $and$ls180.v:2992$74_Y end - attribute \src "ls180.v:3082.30-3082.121" - cell $and $and$ls180.v:3082$100 + attribute \src "ls180.v:2993.31-2993.90" + cell $and $and$ls180.v:2993$75 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3082$99_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3082$100_Y + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2993$75_Y end - attribute \src "ls180.v:3082.29-3082.156" - cell $and $and$ls180.v:3082$101 + attribute \src "ls180.v:2993.30-2993.121" + cell $and $and$ls180.v:2993$76 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3082$100_Y - connect \B \main_libresocsim_ram_bus_sel [5] - connect \Y $and$ls180.v:3082$101_Y + connect \A $and$ls180.v:2993$75_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2993$76_Y end - attribute \src "ls180.v:3082.31-3082.90" - cell $and $and$ls180.v:3082$99 + attribute \src "ls180.v:2993.29-2993.156" + cell $and $and$ls180.v:2993$77 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3082$99_Y + connect \A $and$ls180.v:2993$76_Y + connect \B \main_libresocsim_ram_bus_sel [5] + connect \Y $and$ls180.v:2993$77_Y end - attribute \src "ls180.v:3083.31-3083.90" - cell $and $and$ls180.v:3083$102 + attribute \src "ls180.v:2994.31-2994.90" + cell $and $and$ls180.v:2994$78 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255622,32 +254856,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3083$102_Y + connect \Y $and$ls180.v:2994$78_Y end - attribute \src "ls180.v:3083.30-3083.121" - cell $and $and$ls180.v:3083$103 + attribute \src "ls180.v:2994.30-2994.121" + cell $and $and$ls180.v:2994$79 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3083$102_Y + connect \A $and$ls180.v:2994$78_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3083$103_Y + connect \Y $and$ls180.v:2994$79_Y end - attribute \src "ls180.v:3083.29-3083.156" - cell $and $and$ls180.v:3083$104 + attribute \src "ls180.v:2994.29-2994.156" + cell $and $and$ls180.v:2994$80 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3083$103_Y + connect \A $and$ls180.v:2994$79_Y connect \B \main_libresocsim_ram_bus_sel [6] - connect \Y $and$ls180.v:3083$104_Y + connect \Y $and$ls180.v:2994$80_Y end - attribute \src "ls180.v:3084.31-3084.90" - cell $and $and$ls180.v:3084$105 + attribute \src "ls180.v:2995.31-2995.90" + cell $and $and$ls180.v:2995$81 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255655,32 +254889,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:3084$105_Y + connect \Y $and$ls180.v:2995$81_Y end - attribute \src "ls180.v:3084.30-3084.121" - cell $and $and$ls180.v:3084$106 + attribute \src "ls180.v:2995.30-2995.121" + cell $and $and$ls180.v:2995$82 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3084$105_Y + connect \A $and$ls180.v:2995$81_Y connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:3084$106_Y + connect \Y $and$ls180.v:2995$82_Y end - attribute \src "ls180.v:3084.29-3084.156" - cell $and $and$ls180.v:3084$107 + attribute \src "ls180.v:2995.29-2995.156" + cell $and $and$ls180.v:2995$83 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3084$106_Y + connect \A $and$ls180.v:2995$82_Y connect \B \main_libresocsim_ram_bus_sel [7] - connect \Y $and$ls180.v:3084$107_Y + connect \Y $and$ls180.v:2995$83_Y end - attribute \src "ls180.v:3093.7-3093.89" - cell $and $and$ls180.v:3093$110 + attribute \src "ls180.v:3004.7-3004.89" + cell $and $and$ls180.v:3004$86 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255688,10 +254922,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_eventmanager_pending_re connect \B \main_libresocsim_eventmanager_pending_r - connect \Y $and$ls180.v:3093$110_Y + connect \Y $and$ls180.v:3004$86_Y end - attribute \src "ls180.v:3098.32-3098.111" - cell $and $and$ls180.v:3098$111 + attribute \src "ls180.v:3009.32-3009.111" + cell $and $and$ls180.v:3009$87 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -255699,1066 +254933,274 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_eventmanager_pending_w connect \B \main_libresocsim_eventmanager_storage - connect \Y $and$ls180.v:3098$111_Y - end - attribute \src "ls180.v:3102.25-3102.82" - cell $and $and$ls180.v:3102$113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3102$113_Y - end - attribute \src "ls180.v:3102.24-3102.112" - cell $and $and$ls180.v:3102$114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3102$113_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3102$114_Y - end - attribute \src "ls180.v:3102.23-3102.146" - cell $and $and$ls180.v:3102$115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3102$114_Y - connect \B \main_interface0_ram_bus_sel [0] - connect \Y $and$ls180.v:3102$115_Y - end - attribute \src "ls180.v:3103.25-3103.82" - cell $and $and$ls180.v:3103$116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3103$116_Y - end - attribute \src "ls180.v:3103.24-3103.112" - cell $and $and$ls180.v:3103$117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3103$116_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3103$117_Y - end - attribute \src "ls180.v:3103.23-3103.146" - cell $and $and$ls180.v:3103$118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3103$117_Y - connect \B \main_interface0_ram_bus_sel [1] - connect \Y $and$ls180.v:3103$118_Y - end - attribute \src "ls180.v:3104.25-3104.82" - cell $and $and$ls180.v:3104$119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3104$119_Y - end - attribute \src "ls180.v:3104.24-3104.112" - cell $and $and$ls180.v:3104$120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3104$119_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3104$120_Y - end - attribute \src "ls180.v:3104.23-3104.146" - cell $and $and$ls180.v:3104$121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3104$120_Y - connect \B \main_interface0_ram_bus_sel [2] - connect \Y $and$ls180.v:3104$121_Y - end - attribute \src "ls180.v:3105.25-3105.82" - cell $and $and$ls180.v:3105$122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3105$122_Y - end - attribute \src "ls180.v:3105.24-3105.112" - cell $and $and$ls180.v:3105$123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3105$122_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3105$123_Y - end - attribute \src "ls180.v:3105.23-3105.146" - cell $and $and$ls180.v:3105$124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3105$123_Y - connect \B \main_interface0_ram_bus_sel [3] - connect \Y $and$ls180.v:3105$124_Y - end - attribute \src "ls180.v:3106.25-3106.82" - cell $and $and$ls180.v:3106$125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3106$125_Y - end - attribute \src "ls180.v:3106.24-3106.112" - cell $and $and$ls180.v:3106$126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3106$125_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3106$126_Y - end - attribute \src "ls180.v:3106.23-3106.146" - cell $and $and$ls180.v:3106$127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3106$126_Y - connect \B \main_interface0_ram_bus_sel [4] - connect \Y $and$ls180.v:3106$127_Y - end - attribute \src "ls180.v:3107.25-3107.82" - cell $and $and$ls180.v:3107$128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3107$128_Y - end - attribute \src "ls180.v:3107.24-3107.112" - cell $and $and$ls180.v:3107$129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3107$128_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3107$129_Y - end - attribute \src "ls180.v:3107.23-3107.146" - cell $and $and$ls180.v:3107$130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3107$129_Y - connect \B \main_interface0_ram_bus_sel [5] - connect \Y $and$ls180.v:3107$130_Y - end - attribute \src "ls180.v:3108.25-3108.82" - cell $and $and$ls180.v:3108$131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3108$131_Y - end - attribute \src "ls180.v:3108.24-3108.112" - cell $and $and$ls180.v:3108$132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3108$131_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3108$132_Y - end - attribute \src "ls180.v:3108.23-3108.146" - cell $and $and$ls180.v:3108$133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3108$132_Y - connect \B \main_interface0_ram_bus_sel [6] - connect \Y $and$ls180.v:3108$133_Y - end - attribute \src "ls180.v:3109.25-3109.82" - cell $and $and$ls180.v:3109$134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:3109$134_Y - end - attribute \src "ls180.v:3109.24-3109.112" - cell $and $and$ls180.v:3109$135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3109$134_Y - connect \B \main_interface0_ram_bus_we - connect \Y $and$ls180.v:3109$135_Y - end - attribute \src "ls180.v:3109.23-3109.146" - cell $and $and$ls180.v:3109$136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3109$135_Y - connect \B \main_interface0_ram_bus_sel [7] - connect \Y $and$ls180.v:3109$136_Y - end - attribute \src "ls180.v:3116.25-3116.82" - cell $and $and$ls180.v:3116$138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3116$138_Y - end - attribute \src "ls180.v:3116.24-3116.112" - cell $and $and$ls180.v:3116$139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3116$138_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3116$139_Y - end - attribute \src "ls180.v:3116.23-3116.146" - cell $and $and$ls180.v:3116$140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3116$139_Y - connect \B \main_interface1_ram_bus_sel [0] - connect \Y $and$ls180.v:3116$140_Y - end - attribute \src "ls180.v:3117.25-3117.82" - cell $and $and$ls180.v:3117$141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3117$141_Y - end - attribute \src "ls180.v:3117.24-3117.112" - cell $and $and$ls180.v:3117$142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3117$141_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3117$142_Y - end - attribute \src "ls180.v:3117.23-3117.146" - cell $and $and$ls180.v:3117$143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3117$142_Y - connect \B \main_interface1_ram_bus_sel [1] - connect \Y $and$ls180.v:3117$143_Y - end - attribute \src "ls180.v:3118.25-3118.82" - cell $and $and$ls180.v:3118$144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3118$144_Y - end - attribute \src "ls180.v:3118.24-3118.112" - cell $and $and$ls180.v:3118$145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3118$144_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3118$145_Y - end - attribute \src "ls180.v:3118.23-3118.146" - cell $and $and$ls180.v:3118$146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3118$145_Y - connect \B \main_interface1_ram_bus_sel [2] - connect \Y $and$ls180.v:3118$146_Y - end - attribute \src "ls180.v:3119.25-3119.82" - cell $and $and$ls180.v:3119$147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3119$147_Y - end - attribute \src "ls180.v:3119.24-3119.112" - cell $and $and$ls180.v:3119$148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3119$147_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3119$148_Y - end - attribute \src "ls180.v:3119.23-3119.146" - cell $and $and$ls180.v:3119$149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3119$148_Y - connect \B \main_interface1_ram_bus_sel [3] - connect \Y $and$ls180.v:3119$149_Y - end - attribute \src "ls180.v:3120.25-3120.82" - cell $and $and$ls180.v:3120$150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3120$150_Y - end - attribute \src "ls180.v:3120.24-3120.112" - cell $and $and$ls180.v:3120$151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3120$150_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3120$151_Y - end - attribute \src "ls180.v:3120.23-3120.146" - cell $and $and$ls180.v:3120$152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3120$151_Y - connect \B \main_interface1_ram_bus_sel [4] - connect \Y $and$ls180.v:3120$152_Y - end - attribute \src "ls180.v:3121.25-3121.82" - cell $and $and$ls180.v:3121$153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3121$153_Y - end - attribute \src "ls180.v:3121.24-3121.112" - cell $and $and$ls180.v:3121$154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3121$153_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3121$154_Y - end - attribute \src "ls180.v:3121.23-3121.146" - cell $and $and$ls180.v:3121$155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3121$154_Y - connect \B \main_interface1_ram_bus_sel [5] - connect \Y $and$ls180.v:3121$155_Y - end - attribute \src "ls180.v:3122.25-3122.82" - cell $and $and$ls180.v:3122$156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3122$156_Y - end - attribute \src "ls180.v:3122.24-3122.112" - cell $and $and$ls180.v:3122$157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3122$156_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3122$157_Y - end - attribute \src "ls180.v:3122.23-3122.146" - cell $and $and$ls180.v:3122$158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3122$157_Y - connect \B \main_interface1_ram_bus_sel [6] - connect \Y $and$ls180.v:3122$158_Y - end - attribute \src "ls180.v:3123.25-3123.82" - cell $and $and$ls180.v:3123$159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:3123$159_Y - end - attribute \src "ls180.v:3123.24-3123.112" - cell $and $and$ls180.v:3123$160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3123$159_Y - connect \B \main_interface1_ram_bus_we - connect \Y $and$ls180.v:3123$160_Y - end - attribute \src "ls180.v:3123.23-3123.146" - cell $and $and$ls180.v:3123$161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3123$160_Y - connect \B \main_interface1_ram_bus_sel [7] - connect \Y $and$ls180.v:3123$161_Y - end - attribute \src "ls180.v:3130.25-3130.82" - cell $and $and$ls180.v:3130$163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3130$163_Y - end - attribute \src "ls180.v:3130.24-3130.112" - cell $and $and$ls180.v:3130$164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3130$163_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3130$164_Y - end - attribute \src "ls180.v:3130.23-3130.146" - cell $and $and$ls180.v:3130$165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3130$164_Y - connect \B \main_interface2_ram_bus_sel [0] - connect \Y $and$ls180.v:3130$165_Y - end - attribute \src "ls180.v:3131.25-3131.82" - cell $and $and$ls180.v:3131$166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3131$166_Y - end - attribute \src "ls180.v:3131.24-3131.112" - cell $and $and$ls180.v:3131$167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3131$166_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3131$167_Y - end - attribute \src "ls180.v:3131.23-3131.146" - cell $and $and$ls180.v:3131$168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3131$167_Y - connect \B \main_interface2_ram_bus_sel [1] - connect \Y $and$ls180.v:3131$168_Y - end - attribute \src "ls180.v:3132.25-3132.82" - cell $and $and$ls180.v:3132$169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3132$169_Y - end - attribute \src "ls180.v:3132.24-3132.112" - cell $and $and$ls180.v:3132$170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3132$169_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3132$170_Y - end - attribute \src "ls180.v:3132.23-3132.146" - cell $and $and$ls180.v:3132$171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3132$170_Y - connect \B \main_interface2_ram_bus_sel [2] - connect \Y $and$ls180.v:3132$171_Y - end - attribute \src "ls180.v:3133.25-3133.82" - cell $and $and$ls180.v:3133$172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3133$172_Y - end - attribute \src "ls180.v:3133.24-3133.112" - cell $and $and$ls180.v:3133$173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3133$172_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3133$173_Y - end - attribute \src "ls180.v:3133.23-3133.146" - cell $and $and$ls180.v:3133$174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3133$173_Y - connect \B \main_interface2_ram_bus_sel [3] - connect \Y $and$ls180.v:3133$174_Y - end - attribute \src "ls180.v:3134.25-3134.82" - cell $and $and$ls180.v:3134$175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3134$175_Y - end - attribute \src "ls180.v:3134.24-3134.112" - cell $and $and$ls180.v:3134$176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3134$175_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3134$176_Y - end - attribute \src "ls180.v:3134.23-3134.146" - cell $and $and$ls180.v:3134$177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3134$176_Y - connect \B \main_interface2_ram_bus_sel [4] - connect \Y $and$ls180.v:3134$177_Y - end - attribute \src "ls180.v:3135.25-3135.82" - cell $and $and$ls180.v:3135$178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3135$178_Y - end - attribute \src "ls180.v:3135.24-3135.112" - cell $and $and$ls180.v:3135$179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3135$178_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3135$179_Y - end - attribute \src "ls180.v:3135.23-3135.146" - cell $and $and$ls180.v:3135$180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3135$179_Y - connect \B \main_interface2_ram_bus_sel [5] - connect \Y $and$ls180.v:3135$180_Y - end - attribute \src "ls180.v:3136.25-3136.82" - cell $and $and$ls180.v:3136$181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3136$181_Y - end - attribute \src "ls180.v:3136.24-3136.112" - cell $and $and$ls180.v:3136$182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3136$181_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3136$182_Y - end - attribute \src "ls180.v:3136.23-3136.146" - cell $and $and$ls180.v:3136$183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3136$182_Y - connect \B \main_interface2_ram_bus_sel [6] - connect \Y $and$ls180.v:3136$183_Y - end - attribute \src "ls180.v:3137.25-3137.82" - cell $and $and$ls180.v:3137$184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:3137$184_Y - end - attribute \src "ls180.v:3137.24-3137.112" - cell $and $and$ls180.v:3137$185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3137$184_Y - connect \B \main_interface2_ram_bus_we - connect \Y $and$ls180.v:3137$185_Y - end - attribute \src "ls180.v:3137.23-3137.146" - cell $and $and$ls180.v:3137$186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3137$185_Y - connect \B \main_interface2_ram_bus_sel [7] - connect \Y $and$ls180.v:3137$186_Y + connect \Y $and$ls180.v:3009$87_Y end - attribute \src "ls180.v:3144.25-3144.82" - cell $and $and$ls180.v:3144$188 + attribute \src "ls180.v:3013.23-3013.74" + cell $and $and$ls180.v:3013$89 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3144$188_Y + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:3013$89_Y end - attribute \src "ls180.v:3144.24-3144.112" - cell $and $and$ls180.v:3144$189 + attribute \src "ls180.v:3013.22-3013.101" + cell $and $and$ls180.v:3013$90 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3144$188_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3144$189_Y + connect \A $and$ls180.v:3013$89_Y + connect \B \main_ram_bus_ram_bus_we + connect \Y $and$ls180.v:3013$90_Y end - attribute \src "ls180.v:3144.23-3144.146" - cell $and $and$ls180.v:3144$190 + attribute \src "ls180.v:3013.21-3013.132" + cell $and $and$ls180.v:3013$91 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3144$189_Y - connect \B \main_interface3_ram_bus_sel [0] - connect \Y $and$ls180.v:3144$190_Y + connect \A $and$ls180.v:3013$90_Y + connect \B \main_ram_bus_ram_bus_sel [0] + connect \Y $and$ls180.v:3013$91_Y end - attribute \src "ls180.v:3145.25-3145.82" - cell $and $and$ls180.v:3145$191 + attribute \src "ls180.v:3014.23-3014.74" + cell $and $and$ls180.v:3014$92 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3145$191_Y + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:3014$92_Y end - attribute \src "ls180.v:3145.24-3145.112" - cell $and $and$ls180.v:3145$192 + attribute \src "ls180.v:3014.22-3014.101" + cell $and $and$ls180.v:3014$93 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3145$191_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3145$192_Y + connect \A $and$ls180.v:3014$92_Y + connect \B \main_ram_bus_ram_bus_we + connect \Y $and$ls180.v:3014$93_Y end - attribute \src "ls180.v:3145.23-3145.146" - cell $and $and$ls180.v:3145$193 + attribute \src "ls180.v:3014.21-3014.132" + cell $and $and$ls180.v:3014$94 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3145$192_Y - connect \B \main_interface3_ram_bus_sel [1] - connect \Y $and$ls180.v:3145$193_Y + connect \A $and$ls180.v:3014$93_Y + connect \B \main_ram_bus_ram_bus_sel [1] + connect \Y $and$ls180.v:3014$94_Y end - attribute \src "ls180.v:3146.25-3146.82" - cell $and $and$ls180.v:3146$194 + attribute \src "ls180.v:3015.23-3015.74" + cell $and $and$ls180.v:3015$95 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3146$194_Y + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:3015$95_Y end - attribute \src "ls180.v:3146.24-3146.112" - cell $and $and$ls180.v:3146$195 + attribute \src "ls180.v:3015.22-3015.101" + cell $and $and$ls180.v:3015$96 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3146$194_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3146$195_Y + connect \A $and$ls180.v:3015$95_Y + connect \B \main_ram_bus_ram_bus_we + connect \Y $and$ls180.v:3015$96_Y end - attribute \src "ls180.v:3146.23-3146.146" - cell $and $and$ls180.v:3146$196 + attribute \src "ls180.v:3015.21-3015.132" + cell $and $and$ls180.v:3015$97 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3146$195_Y - connect \B \main_interface3_ram_bus_sel [2] - connect \Y $and$ls180.v:3146$196_Y + connect \A $and$ls180.v:3015$96_Y + connect \B \main_ram_bus_ram_bus_sel [2] + connect \Y $and$ls180.v:3015$97_Y end - attribute \src "ls180.v:3147.25-3147.82" - cell $and $and$ls180.v:3147$197 + attribute \src "ls180.v:3016.21-3016.132" + cell $and $and$ls180.v:3016$100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3147$197_Y + connect \A $and$ls180.v:3016$99_Y + connect \B \main_ram_bus_ram_bus_sel [3] + connect \Y $and$ls180.v:3016$100_Y end - attribute \src "ls180.v:3147.24-3147.112" - cell $and $and$ls180.v:3147$198 + attribute \src "ls180.v:3016.23-3016.74" + cell $and $and$ls180.v:3016$98 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3147$197_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3147$198_Y + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:3016$98_Y end - attribute \src "ls180.v:3147.23-3147.146" - cell $and $and$ls180.v:3147$199 + attribute \src "ls180.v:3016.22-3016.101" + cell $and $and$ls180.v:3016$99 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3147$198_Y - connect \B \main_interface3_ram_bus_sel [3] - connect \Y $and$ls180.v:3147$199_Y + connect \A $and$ls180.v:3016$98_Y + connect \B \main_ram_bus_ram_bus_we + connect \Y $and$ls180.v:3016$99_Y end - attribute \src "ls180.v:3148.25-3148.82" - cell $and $and$ls180.v:3148$200 + attribute \src "ls180.v:3017.23-3017.74" + cell $and $and$ls180.v:3017$101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3148$200_Y + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:3017$101_Y end - attribute \src "ls180.v:3148.24-3148.112" - cell $and $and$ls180.v:3148$201 + attribute \src "ls180.v:3017.22-3017.101" + cell $and $and$ls180.v:3017$102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3148$200_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3148$201_Y + connect \A $and$ls180.v:3017$101_Y + connect \B \main_ram_bus_ram_bus_we + connect \Y $and$ls180.v:3017$102_Y end - attribute \src "ls180.v:3148.23-3148.146" - cell $and $and$ls180.v:3148$202 + attribute \src "ls180.v:3017.21-3017.132" + cell $and $and$ls180.v:3017$103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3148$201_Y - connect \B \main_interface3_ram_bus_sel [4] - connect \Y $and$ls180.v:3148$202_Y + connect \A $and$ls180.v:3017$102_Y + connect \B \main_ram_bus_ram_bus_sel [4] + connect \Y $and$ls180.v:3017$103_Y end - attribute \src "ls180.v:3149.25-3149.82" - cell $and $and$ls180.v:3149$203 + attribute \src "ls180.v:3018.23-3018.74" + cell $and $and$ls180.v:3018$104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3149$203_Y + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:3018$104_Y end - attribute \src "ls180.v:3149.24-3149.112" - cell $and $and$ls180.v:3149$204 + attribute \src "ls180.v:3018.22-3018.101" + cell $and $and$ls180.v:3018$105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3149$203_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3149$204_Y + connect \A $and$ls180.v:3018$104_Y + connect \B \main_ram_bus_ram_bus_we + connect \Y $and$ls180.v:3018$105_Y end - attribute \src "ls180.v:3149.23-3149.146" - cell $and $and$ls180.v:3149$205 + attribute \src "ls180.v:3018.21-3018.132" + cell $and $and$ls180.v:3018$106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3149$204_Y - connect \B \main_interface3_ram_bus_sel [5] - connect \Y $and$ls180.v:3149$205_Y + connect \A $and$ls180.v:3018$105_Y + connect \B \main_ram_bus_ram_bus_sel [5] + connect \Y $and$ls180.v:3018$106_Y end - attribute \src "ls180.v:3150.25-3150.82" - cell $and $and$ls180.v:3150$206 + attribute \src "ls180.v:3019.23-3019.74" + cell $and $and$ls180.v:3019$107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3150$206_Y + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:3019$107_Y end - attribute \src "ls180.v:3150.24-3150.112" - cell $and $and$ls180.v:3150$207 + attribute \src "ls180.v:3019.22-3019.101" + cell $and $and$ls180.v:3019$108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3150$206_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3150$207_Y + connect \A $and$ls180.v:3019$107_Y + connect \B \main_ram_bus_ram_bus_we + connect \Y $and$ls180.v:3019$108_Y end - attribute \src "ls180.v:3150.23-3150.146" - cell $and $and$ls180.v:3150$208 + attribute \src "ls180.v:3019.21-3019.132" + cell $and $and$ls180.v:3019$109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3150$207_Y - connect \B \main_interface3_ram_bus_sel [6] - connect \Y $and$ls180.v:3150$208_Y + connect \A $and$ls180.v:3019$108_Y + connect \B \main_ram_bus_ram_bus_sel [6] + connect \Y $and$ls180.v:3019$109_Y end - attribute \src "ls180.v:3151.25-3151.82" - cell $and $and$ls180.v:3151$209 + attribute \src "ls180.v:3020.23-3020.74" + cell $and $and$ls180.v:3020$110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:3151$209_Y + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:3020$110_Y end - attribute \src "ls180.v:3151.24-3151.112" - cell $and $and$ls180.v:3151$210 + attribute \src "ls180.v:3020.22-3020.101" + cell $and $and$ls180.v:3020$111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3151$209_Y - connect \B \main_interface3_ram_bus_we - connect \Y $and$ls180.v:3151$210_Y + connect \A $and$ls180.v:3020$110_Y + connect \B \main_ram_bus_ram_bus_we + connect \Y $and$ls180.v:3020$111_Y end - attribute \src "ls180.v:3151.23-3151.146" - cell $and $and$ls180.v:3151$211 + attribute \src "ls180.v:3020.21-3020.132" + cell $and $and$ls180.v:3020$112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3151$210_Y - connect \B \main_interface3_ram_bus_sel [7] - connect \Y $and$ls180.v:3151$211_Y + connect \A $and$ls180.v:3020$111_Y + connect \B \main_ram_bus_ram_bus_sel [7] + connect \Y $and$ls180.v:3020$112_Y end - attribute \src "ls180.v:3268.40-3268.99" - cell $and $and$ls180.v:3268$218 + attribute \src "ls180.v:3137.40-3137.99" + cell $and $and$ls180.v:3137$119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256766,10 +255208,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_command_issue_re connect \B \main_sdram_command_storage [4] - connect \Y $and$ls180.v:3268$218_Y + connect \Y $and$ls180.v:3137$119_Y end - attribute \src "ls180.v:3269.40-3269.99" - cell $and $and$ls180.v:3269$219 + attribute \src "ls180.v:3138.40-3138.99" + cell $and $and$ls180.v:3138$120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256777,21 +255219,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_command_issue_re connect \B \main_sdram_command_storage [5] - connect \Y $and$ls180.v:3269$219_Y + connect \Y $and$ls180.v:3138$120_Y end - attribute \src "ls180.v:3307.38-3307.103" - cell $and $and$ls180.v:3307$225 + attribute \src "ls180.v:3176.38-3176.103" + cell $and $and$ls180.v:3176$126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_done1 - connect \B $eq$ls180.v:3307$224_Y - connect \Y $and$ls180.v:3307$225_Y + connect \B $eq$ls180.v:3176$125_Y + connect \Y $and$ls180.v:3176$126_Y end - attribute \src "ls180.v:3361.50-3361.119" - cell $and $and$ls180.v:3361$233 + attribute \src "ls180.v:3230.50-3230.119" + cell $and $and$ls180.v:3230$134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256799,21 +255241,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3361$233_Y + connect \Y $and$ls180.v:3230$134_Y end - attribute \src "ls180.v:3361.49-3361.167" - cell $and $and$ls180.v:3361$234 + attribute \src "ls180.v:3230.49-3230.167" + cell $and $and$ls180.v:3230$135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3361$233_Y + connect \A $and$ls180.v:3230$134_Y connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3361$234_Y + connect \Y $and$ls180.v:3230$135_Y end - attribute \src "ls180.v:3362.49-3362.118" - cell $and $and$ls180.v:3362$235 + attribute \src "ls180.v:3231.49-3231.118" + cell $and $and$ls180.v:3231$136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256821,21 +255263,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3362$235_Y + connect \Y $and$ls180.v:3231$136_Y end - attribute \src "ls180.v:3362.48-3362.154" - cell $and $and$ls180.v:3362$236 + attribute \src "ls180.v:3231.48-3231.154" + cell $and $and$ls180.v:3231$137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3362$235_Y + connect \A $and$ls180.v:3231$136_Y connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3362$236_Y + connect \Y $and$ls180.v:3231$137_Y end - attribute \src "ls180.v:3363.50-3363.119" - cell $and $and$ls180.v:3363$237 + attribute \src "ls180.v:3232.50-3232.119" + cell $and $and$ls180.v:3232$138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256843,21 +255285,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3363$237_Y + connect \Y $and$ls180.v:3232$138_Y end - attribute \src "ls180.v:3363.49-3363.155" - cell $and $and$ls180.v:3363$238 + attribute \src "ls180.v:3232.49-3232.155" + cell $and $and$ls180.v:3232$139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3363$237_Y + connect \A $and$ls180.v:3232$138_Y connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3363$238_Y + connect \Y $and$ls180.v:3232$139_Y end - attribute \src "ls180.v:3366.7-3366.114" - cell $and $and$ls180.v:3366$240 + attribute \src "ls180.v:3235.7-3235.114" + cell $and $and$ls180.v:3235$141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256865,21 +255307,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $and$ls180.v:3366$240_Y + connect \Y $and$ls180.v:3235$141_Y end - attribute \src "ls180.v:3395.66-3395.246" - cell $and $and$ls180.v:3395$246 + attribute \src "ls180.v:3264.66-3264.246" + cell $and $and$ls180.v:3264$147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B $or$ls180.v:3395$245_Y - connect \Y $and$ls180.v:3395$246_Y + connect \B $or$ls180.v:3264$146_Y + connect \Y $and$ls180.v:3264$147_Y end - attribute \src "ls180.v:3396.64-3396.187" - cell $and $and$ls180.v:3396$247 + attribute \src "ls180.v:3265.64-3265.187" + cell $and $and$ls180.v:3265$148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256887,10 +255329,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - connect \Y $and$ls180.v:3396$247_Y + connect \Y $and$ls180.v:3265$148_Y end - attribute \src "ls180.v:3420.9-3420.86" - cell $and $and$ls180.v:3420$253 + attribute \src "ls180.v:3289.9-3289.86" + cell $and $and$ls180.v:3289$154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256898,10 +255340,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3420$253_Y + connect \Y $and$ls180.v:3289$154_Y end - attribute \src "ls180.v:3432.9-3432.86" - cell $and $and$ls180.v:3432$254 + attribute \src "ls180.v:3301.9-3301.86" + cell $and $and$ls180.v:3301$155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256909,10 +255351,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3432$254_Y + connect \Y $and$ls180.v:3301$155_Y end - attribute \src "ls180.v:3482.13-3482.87" - cell $and $and$ls180.v:3482$256 + attribute \src "ls180.v:3351.13-3351.87" + cell $and $and$ls180.v:3351$157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256920,10 +255362,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_ready connect \B \main_sdram_bankmachine0_auto_precharge - connect \Y $and$ls180.v:3482$256_Y + connect \Y $and$ls180.v:3351$157_Y end - attribute \src "ls180.v:3518.50-3518.119" - cell $and $and$ls180.v:3518$263 + attribute \src "ls180.v:3387.50-3387.119" + cell $and $and$ls180.v:3387$164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256931,21 +255373,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3518$263_Y + connect \Y $and$ls180.v:3387$164_Y end - attribute \src "ls180.v:3518.49-3518.167" - cell $and $and$ls180.v:3518$264 + attribute \src "ls180.v:3387.49-3387.167" + cell $and $and$ls180.v:3387$165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3518$263_Y + connect \A $and$ls180.v:3387$164_Y connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3518$264_Y + connect \Y $and$ls180.v:3387$165_Y end - attribute \src "ls180.v:3519.49-3519.118" - cell $and $and$ls180.v:3519$265 + attribute \src "ls180.v:3388.49-3388.118" + cell $and $and$ls180.v:3388$166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256953,21 +255395,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3519$265_Y + connect \Y $and$ls180.v:3388$166_Y end - attribute \src "ls180.v:3519.48-3519.154" - cell $and $and$ls180.v:3519$266 + attribute \src "ls180.v:3388.48-3388.154" + cell $and $and$ls180.v:3388$167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3519$265_Y + connect \A $and$ls180.v:3388$166_Y connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3519$266_Y + connect \Y $and$ls180.v:3388$167_Y end - attribute \src "ls180.v:3520.50-3520.119" - cell $and $and$ls180.v:3520$267 + attribute \src "ls180.v:3389.50-3389.119" + cell $and $and$ls180.v:3389$168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256975,21 +255417,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3520$267_Y + connect \Y $and$ls180.v:3389$168_Y end - attribute \src "ls180.v:3520.49-3520.155" - cell $and $and$ls180.v:3520$268 + attribute \src "ls180.v:3389.49-3389.155" + cell $and $and$ls180.v:3389$169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3520$267_Y + connect \A $and$ls180.v:3389$168_Y connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3520$268_Y + connect \Y $and$ls180.v:3389$169_Y end - attribute \src "ls180.v:3523.7-3523.114" - cell $and $and$ls180.v:3523$270 + attribute \src "ls180.v:3392.7-3392.114" + cell $and $and$ls180.v:3392$171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -256997,21 +255439,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $and$ls180.v:3523$270_Y + connect \Y $and$ls180.v:3392$171_Y end - attribute \src "ls180.v:3552.66-3552.246" - cell $and $and$ls180.v:3552$276 + attribute \src "ls180.v:3421.66-3421.246" + cell $and $and$ls180.v:3421$177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B $or$ls180.v:3552$275_Y - connect \Y $and$ls180.v:3552$276_Y + connect \B $or$ls180.v:3421$176_Y + connect \Y $and$ls180.v:3421$177_Y end - attribute \src "ls180.v:3553.64-3553.187" - cell $and $and$ls180.v:3553$277 + attribute \src "ls180.v:3422.64-3422.187" + cell $and $and$ls180.v:3422$178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257019,10 +255461,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - connect \Y $and$ls180.v:3553$277_Y + connect \Y $and$ls180.v:3422$178_Y end - attribute \src "ls180.v:3577.9-3577.86" - cell $and $and$ls180.v:3577$283 + attribute \src "ls180.v:3446.9-3446.86" + cell $and $and$ls180.v:3446$184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257030,10 +255472,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3577$283_Y + connect \Y $and$ls180.v:3446$184_Y end - attribute \src "ls180.v:3589.9-3589.86" - cell $and $and$ls180.v:3589$284 + attribute \src "ls180.v:3458.9-3458.86" + cell $and $and$ls180.v:3458$185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257041,10 +255483,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3589$284_Y + connect \Y $and$ls180.v:3458$185_Y end - attribute \src "ls180.v:3639.13-3639.87" - cell $and $and$ls180.v:3639$286 + attribute \src "ls180.v:3508.13-3508.87" + cell $and $and$ls180.v:3508$187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257052,10 +255494,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_ready connect \B \main_sdram_bankmachine1_auto_precharge - connect \Y $and$ls180.v:3639$286_Y + connect \Y $and$ls180.v:3508$187_Y end - attribute \src "ls180.v:3675.50-3675.119" - cell $and $and$ls180.v:3675$293 + attribute \src "ls180.v:3544.50-3544.119" + cell $and $and$ls180.v:3544$194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257063,21 +255505,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3675$293_Y + connect \Y $and$ls180.v:3544$194_Y end - attribute \src "ls180.v:3675.49-3675.167" - cell $and $and$ls180.v:3675$294 + attribute \src "ls180.v:3544.49-3544.167" + cell $and $and$ls180.v:3544$195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3675$293_Y + connect \A $and$ls180.v:3544$194_Y connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3675$294_Y + connect \Y $and$ls180.v:3544$195_Y end - attribute \src "ls180.v:3676.49-3676.118" - cell $and $and$ls180.v:3676$295 + attribute \src "ls180.v:3545.49-3545.118" + cell $and $and$ls180.v:3545$196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257085,21 +255527,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3676$295_Y + connect \Y $and$ls180.v:3545$196_Y end - attribute \src "ls180.v:3676.48-3676.154" - cell $and $and$ls180.v:3676$296 + attribute \src "ls180.v:3545.48-3545.154" + cell $and $and$ls180.v:3545$197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3676$295_Y + connect \A $and$ls180.v:3545$196_Y connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3676$296_Y + connect \Y $and$ls180.v:3545$197_Y end - attribute \src "ls180.v:3677.50-3677.119" - cell $and $and$ls180.v:3677$297 + attribute \src "ls180.v:3546.50-3546.119" + cell $and $and$ls180.v:3546$198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257107,21 +255549,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3677$297_Y + connect \Y $and$ls180.v:3546$198_Y end - attribute \src "ls180.v:3677.49-3677.155" - cell $and $and$ls180.v:3677$298 + attribute \src "ls180.v:3546.49-3546.155" + cell $and $and$ls180.v:3546$199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3677$297_Y + connect \A $and$ls180.v:3546$198_Y connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3677$298_Y + connect \Y $and$ls180.v:3546$199_Y end - attribute \src "ls180.v:3680.7-3680.114" - cell $and $and$ls180.v:3680$300 + attribute \src "ls180.v:3549.7-3549.114" + cell $and $and$ls180.v:3549$201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257129,21 +255571,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $and$ls180.v:3680$300_Y + connect \Y $and$ls180.v:3549$201_Y end - attribute \src "ls180.v:3709.66-3709.246" - cell $and $and$ls180.v:3709$306 + attribute \src "ls180.v:3578.66-3578.246" + cell $and $and$ls180.v:3578$207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B $or$ls180.v:3709$305_Y - connect \Y $and$ls180.v:3709$306_Y + connect \B $or$ls180.v:3578$206_Y + connect \Y $and$ls180.v:3578$207_Y end - attribute \src "ls180.v:3710.64-3710.187" - cell $and $and$ls180.v:3710$307 + attribute \src "ls180.v:3579.64-3579.187" + cell $and $and$ls180.v:3579$208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257151,10 +255593,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - connect \Y $and$ls180.v:3710$307_Y + connect \Y $and$ls180.v:3579$208_Y end - attribute \src "ls180.v:3734.9-3734.86" - cell $and $and$ls180.v:3734$313 + attribute \src "ls180.v:3603.9-3603.86" + cell $and $and$ls180.v:3603$214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257162,10 +255604,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3734$313_Y + connect \Y $and$ls180.v:3603$214_Y end - attribute \src "ls180.v:3746.9-3746.86" - cell $and $and$ls180.v:3746$314 + attribute \src "ls180.v:3615.9-3615.86" + cell $and $and$ls180.v:3615$215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257173,10 +255615,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3746$314_Y + connect \Y $and$ls180.v:3615$215_Y end - attribute \src "ls180.v:3796.13-3796.87" - cell $and $and$ls180.v:3796$316 + attribute \src "ls180.v:3665.13-3665.87" + cell $and $and$ls180.v:3665$217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257184,10 +255626,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_ready connect \B \main_sdram_bankmachine2_auto_precharge - connect \Y $and$ls180.v:3796$316_Y + connect \Y $and$ls180.v:3665$217_Y end - attribute \src "ls180.v:3832.50-3832.119" - cell $and $and$ls180.v:3832$323 + attribute \src "ls180.v:3701.50-3701.119" + cell $and $and$ls180.v:3701$224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257195,21 +255637,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3832$323_Y + connect \Y $and$ls180.v:3701$224_Y end - attribute \src "ls180.v:3832.49-3832.167" - cell $and $and$ls180.v:3832$324 + attribute \src "ls180.v:3701.49-3701.167" + cell $and $and$ls180.v:3701$225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3832$323_Y + connect \A $and$ls180.v:3701$224_Y connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3832$324_Y + connect \Y $and$ls180.v:3701$225_Y end - attribute \src "ls180.v:3833.49-3833.118" - cell $and $and$ls180.v:3833$325 + attribute \src "ls180.v:3702.49-3702.118" + cell $and $and$ls180.v:3702$226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257217,21 +255659,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3833$325_Y + connect \Y $and$ls180.v:3702$226_Y end - attribute \src "ls180.v:3833.48-3833.154" - cell $and $and$ls180.v:3833$326 + attribute \src "ls180.v:3702.48-3702.154" + cell $and $and$ls180.v:3702$227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3833$325_Y + connect \A $and$ls180.v:3702$226_Y connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3833$326_Y + connect \Y $and$ls180.v:3702$227_Y end - attribute \src "ls180.v:3834.50-3834.119" - cell $and $and$ls180.v:3834$327 + attribute \src "ls180.v:3703.50-3703.119" + cell $and $and$ls180.v:3703$228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257239,21 +255681,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3834$327_Y + connect \Y $and$ls180.v:3703$228_Y end - attribute \src "ls180.v:3834.49-3834.155" - cell $and $and$ls180.v:3834$328 + attribute \src "ls180.v:3703.49-3703.155" + cell $and $and$ls180.v:3703$229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3834$327_Y + connect \A $and$ls180.v:3703$228_Y connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3834$328_Y + connect \Y $and$ls180.v:3703$229_Y end - attribute \src "ls180.v:3837.7-3837.114" - cell $and $and$ls180.v:3837$330 + attribute \src "ls180.v:3706.7-3706.114" + cell $and $and$ls180.v:3706$231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257261,21 +255703,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $and$ls180.v:3837$330_Y + connect \Y $and$ls180.v:3706$231_Y end - attribute \src "ls180.v:3866.66-3866.246" - cell $and $and$ls180.v:3866$336 + attribute \src "ls180.v:3735.66-3735.246" + cell $and $and$ls180.v:3735$237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B $or$ls180.v:3866$335_Y - connect \Y $and$ls180.v:3866$336_Y + connect \B $or$ls180.v:3735$236_Y + connect \Y $and$ls180.v:3735$237_Y end - attribute \src "ls180.v:3867.64-3867.187" - cell $and $and$ls180.v:3867$337 + attribute \src "ls180.v:3736.64-3736.187" + cell $and $and$ls180.v:3736$238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257283,10 +255725,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - connect \Y $and$ls180.v:3867$337_Y + connect \Y $and$ls180.v:3736$238_Y end - attribute \src "ls180.v:3891.9-3891.86" - cell $and $and$ls180.v:3891$343 + attribute \src "ls180.v:3760.9-3760.86" + cell $and $and$ls180.v:3760$244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257294,10 +255736,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3891$343_Y + connect \Y $and$ls180.v:3760$244_Y end - attribute \src "ls180.v:3903.9-3903.86" - cell $and $and$ls180.v:3903$344 + attribute \src "ls180.v:3772.9-3772.86" + cell $and $and$ls180.v:3772$245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257305,10 +255747,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3903$344_Y + connect \Y $and$ls180.v:3772$245_Y end - attribute \src "ls180.v:3953.13-3953.87" - cell $and $and$ls180.v:3953$346 + attribute \src "ls180.v:3822.13-3822.87" + cell $and $and$ls180.v:3822$247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257316,10 +255758,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_ready connect \B \main_sdram_bankmachine3_auto_precharge - connect \Y $and$ls180.v:3953$346_Y + connect \Y $and$ls180.v:3822$247_Y end - attribute \src "ls180.v:3968.37-3968.102" - cell $and $and$ls180.v:3968$347 + attribute \src "ls180.v:3837.37-3837.102" + cell $and $and$ls180.v:3837$248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257327,43 +255769,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3968$347_Y + connect \Y $and$ls180.v:3837$248_Y end - attribute \src "ls180.v:3968.108-3968.188" - cell $and $and$ls180.v:3968$349 + attribute \src "ls180.v:3837.108-3837.188" + cell $and $and$ls180.v:3837$250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3968$348_Y - connect \Y $and$ls180.v:3968$349_Y + connect \B $not$ls180.v:3837$249_Y + connect \Y $and$ls180.v:3837$250_Y end - attribute \src "ls180.v:3968.107-3968.231" - cell $and $and$ls180.v:3968$351 + attribute \src "ls180.v:3837.107-3837.231" + cell $and $and$ls180.v:3837$252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3968$349_Y - connect \B $not$ls180.v:3968$350_Y - connect \Y $and$ls180.v:3968$351_Y + connect \A $and$ls180.v:3837$250_Y + connect \B $not$ls180.v:3837$251_Y + connect \Y $and$ls180.v:3837$252_Y end - attribute \src "ls180.v:3968.36-3968.232" - cell $and $and$ls180.v:3968$352 + attribute \src "ls180.v:3837.36-3837.232" + cell $and $and$ls180.v:3837$253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3968$347_Y - connect \B $and$ls180.v:3968$351_Y - connect \Y $and$ls180.v:3968$352_Y + connect \A $and$ls180.v:3837$248_Y + connect \B $and$ls180.v:3837$252_Y + connect \Y $and$ls180.v:3837$253_Y end - attribute \src "ls180.v:3969.37-3969.102" - cell $and $and$ls180.v:3969$353 + attribute \src "ls180.v:3838.37-3838.102" + cell $and $and$ls180.v:3838$254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257371,43 +255813,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3969$353_Y + connect \Y $and$ls180.v:3838$254_Y end - attribute \src "ls180.v:3969.108-3969.188" - cell $and $and$ls180.v:3969$355 + attribute \src "ls180.v:3838.108-3838.188" + cell $and $and$ls180.v:3838$256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3969$354_Y - connect \Y $and$ls180.v:3969$355_Y + connect \B $not$ls180.v:3838$255_Y + connect \Y $and$ls180.v:3838$256_Y end - attribute \src "ls180.v:3969.107-3969.231" - cell $and $and$ls180.v:3969$357 + attribute \src "ls180.v:3838.107-3838.231" + cell $and $and$ls180.v:3838$258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3969$355_Y - connect \B $not$ls180.v:3969$356_Y - connect \Y $and$ls180.v:3969$357_Y + connect \A $and$ls180.v:3838$256_Y + connect \B $not$ls180.v:3838$257_Y + connect \Y $and$ls180.v:3838$258_Y end - attribute \src "ls180.v:3969.36-3969.232" - cell $and $and$ls180.v:3969$358 + attribute \src "ls180.v:3838.36-3838.232" + cell $and $and$ls180.v:3838$259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3969$353_Y - connect \B $and$ls180.v:3969$357_Y - connect \Y $and$ls180.v:3969$358_Y + connect \A $and$ls180.v:3838$254_Y + connect \B $and$ls180.v:3838$258_Y + connect \Y $and$ls180.v:3838$259_Y end - attribute \src "ls180.v:3970.34-3970.85" - cell $and $and$ls180.v:3970$359 + attribute \src "ls180.v:3839.34-3839.85" + cell $and $and$ls180.v:3839$260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257415,10 +255857,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_trrdcon_ready connect \B \main_sdram_tfawcon_ready - connect \Y $and$ls180.v:3970$359_Y + connect \Y $and$ls180.v:3839$260_Y end - attribute \src "ls180.v:3971.37-3971.102" - cell $and $and$ls180.v:3971$360 + attribute \src "ls180.v:3840.37-3840.102" + cell $and $and$ls180.v:3840$261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257426,21 +255868,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3971$360_Y + connect \Y $and$ls180.v:3840$261_Y end - attribute \src "ls180.v:3971.36-3971.194" - cell $and $and$ls180.v:3971$362 + attribute \src "ls180.v:3840.36-3840.194" + cell $and $and$ls180.v:3840$263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3971$360_Y - connect \B $or$ls180.v:3971$361_Y - connect \Y $and$ls180.v:3971$362_Y + connect \A $and$ls180.v:3840$261_Y + connect \B $or$ls180.v:3840$262_Y + connect \Y $and$ls180.v:3840$263_Y end - attribute \src "ls180.v:3973.37-3973.102" - cell $and $and$ls180.v:3973$363 + attribute \src "ls180.v:3842.37-3842.102" + cell $and $and$ls180.v:3842$264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257448,21 +255890,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3973$363_Y + connect \Y $and$ls180.v:3842$264_Y end - attribute \src "ls180.v:3973.36-3973.148" - cell $and $and$ls180.v:3973$364 + attribute \src "ls180.v:3842.36-3842.148" + cell $and $and$ls180.v:3842$265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3973$363_Y + connect \A $and$ls180.v:3842$264_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:3973$364_Y + connect \Y $and$ls180.v:3842$265_Y end - attribute \src "ls180.v:3974.40-3974.119" - cell $and $and$ls180.v:3974$365 + attribute \src "ls180.v:3843.40-3843.119" + cell $and $and$ls180.v:3843$266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257470,10 +255912,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_payload_is_read - connect \Y $and$ls180.v:3974$365_Y + connect \Y $and$ls180.v:3843$266_Y end - attribute \src "ls180.v:3974.124-3974.203" - cell $and $and$ls180.v:3974$366 + attribute \src "ls180.v:3843.124-3843.203" + cell $and $and$ls180.v:3843$267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257481,10 +255923,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_payload_is_read - connect \Y $and$ls180.v:3974$366_Y + connect \Y $and$ls180.v:3843$267_Y end - attribute \src "ls180.v:3974.209-3974.288" - cell $and $and$ls180.v:3974$368 + attribute \src "ls180.v:3843.209-3843.288" + cell $and $and$ls180.v:3843$269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257492,10 +255934,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_payload_is_read - connect \Y $and$ls180.v:3974$368_Y + connect \Y $and$ls180.v:3843$269_Y end - attribute \src "ls180.v:3974.294-3974.373" - cell $and $and$ls180.v:3974$370 + attribute \src "ls180.v:3843.294-3843.373" + cell $and $and$ls180.v:3843$271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257503,10 +255945,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_payload_is_read - connect \Y $and$ls180.v:3974$370_Y + connect \Y $and$ls180.v:3843$271_Y end - attribute \src "ls180.v:3975.41-3975.121" - cell $and $and$ls180.v:3975$372 + attribute \src "ls180.v:3844.41-3844.121" + cell $and $and$ls180.v:3844$273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257514,10 +255956,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3975$372_Y + connect \Y $and$ls180.v:3844$273_Y end - attribute \src "ls180.v:3975.126-3975.206" - cell $and $and$ls180.v:3975$373 + attribute \src "ls180.v:3844.126-3844.206" + cell $and $and$ls180.v:3844$274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257525,10 +255967,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3975$373_Y + connect \Y $and$ls180.v:3844$274_Y end - attribute \src "ls180.v:3975.212-3975.292" - cell $and $and$ls180.v:3975$375 + attribute \src "ls180.v:3844.212-3844.292" + cell $and $and$ls180.v:3844$276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257536,10 +255978,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3975$375_Y + connect \Y $and$ls180.v:3844$276_Y end - attribute \src "ls180.v:3975.298-3975.378" - cell $and $and$ls180.v:3975$377 + attribute \src "ls180.v:3844.298-3844.378" + cell $and $and$ls180.v:3844$278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257547,10 +255989,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3975$377_Y + connect \Y $and$ls180.v:3844$278_Y end - attribute \src "ls180.v:3982.38-3982.111" - cell $and $and$ls180.v:3982$381 + attribute \src "ls180.v:3851.38-3851.111" + cell $and $and$ls180.v:3851$282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257558,32 +256000,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_refresh_gnt connect \B \main_sdram_bankmachine1_refresh_gnt - connect \Y $and$ls180.v:3982$381_Y + connect \Y $and$ls180.v:3851$282_Y end - attribute \src "ls180.v:3982.37-3982.150" - cell $and $and$ls180.v:3982$382 + attribute \src "ls180.v:3851.37-3851.150" + cell $and $and$ls180.v:3851$283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3982$381_Y + connect \A $and$ls180.v:3851$282_Y connect \B \main_sdram_bankmachine2_refresh_gnt - connect \Y $and$ls180.v:3982$382_Y + connect \Y $and$ls180.v:3851$283_Y end - attribute \src "ls180.v:3982.36-3982.189" - cell $and $and$ls180.v:3982$383 + attribute \src "ls180.v:3851.36-3851.189" + cell $and $and$ls180.v:3851$284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3982$382_Y + connect \A $and$ls180.v:3851$283_Y connect \B \main_sdram_bankmachine3_refresh_gnt - connect \Y $and$ls180.v:3982$383_Y + connect \Y $and$ls180.v:3851$284_Y end - attribute \src "ls180.v:3988.77-3988.153" - cell $and $and$ls180.v:3988$386 + attribute \src "ls180.v:3857.77-3857.153" + cell $and $and$ls180.v:3857$287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257591,65 +256033,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3988$386_Y + connect \Y $and$ls180.v:3857$287_Y end - attribute \src "ls180.v:3988.162-3988.246" - cell $and $and$ls180.v:3988$388 + attribute \src "ls180.v:3857.162-3857.246" + cell $and $and$ls180.v:3857$289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3988$387_Y - connect \Y $and$ls180.v:3988$388_Y + connect \B $not$ls180.v:3857$288_Y + connect \Y $and$ls180.v:3857$289_Y end - attribute \src "ls180.v:3988.161-3988.291" - cell $and $and$ls180.v:3988$390 + attribute \src "ls180.v:3857.161-3857.291" + cell $and $and$ls180.v:3857$291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$388_Y - connect \B $not$ls180.v:3988$389_Y - connect \Y $and$ls180.v:3988$390_Y + connect \A $and$ls180.v:3857$289_Y + connect \B $not$ls180.v:3857$290_Y + connect \Y $and$ls180.v:3857$291_Y end - attribute \src "ls180.v:3988.76-3988.333" - cell $and $and$ls180.v:3988$393 + attribute \src "ls180.v:3857.76-3857.333" + cell $and $and$ls180.v:3857$294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$386_Y - connect \B $or$ls180.v:3988$392_Y - connect \Y $and$ls180.v:3988$393_Y + connect \A $and$ls180.v:3857$287_Y + connect \B $or$ls180.v:3857$293_Y + connect \Y $and$ls180.v:3857$294_Y end - attribute \src "ls180.v:3988.338-3988.505" - cell $and $and$ls180.v:3988$396 + attribute \src "ls180.v:3857.338-3857.505" + cell $and $and$ls180.v:3857$297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3988$394_Y - connect \B $eq$ls180.v:3988$395_Y - connect \Y $and$ls180.v:3988$396_Y + connect \A $eq$ls180.v:3857$295_Y + connect \B $eq$ls180.v:3857$296_Y + connect \Y $and$ls180.v:3857$297_Y end - attribute \src "ls180.v:3988.38-3988.507" - cell $and $and$ls180.v:3988$398 + attribute \src "ls180.v:3857.38-3857.507" + cell $and $and$ls180.v:3857$299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3988$397_Y - connect \Y $and$ls180.v:3988$398_Y + connect \B $or$ls180.v:3857$298_Y + connect \Y $and$ls180.v:3857$299_Y end - attribute \src "ls180.v:3989.77-3989.153" - cell $and $and$ls180.v:3989$399 + attribute \src "ls180.v:3858.77-3858.153" + cell $and $and$ls180.v:3858$300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257657,65 +256099,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3989$399_Y + connect \Y $and$ls180.v:3858$300_Y end - attribute \src "ls180.v:3989.162-3989.246" - cell $and $and$ls180.v:3989$401 + attribute \src "ls180.v:3858.162-3858.246" + cell $and $and$ls180.v:3858$302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3989$400_Y - connect \Y $and$ls180.v:3989$401_Y + connect \B $not$ls180.v:3858$301_Y + connect \Y $and$ls180.v:3858$302_Y end - attribute \src "ls180.v:3989.161-3989.291" - cell $and $and$ls180.v:3989$403 + attribute \src "ls180.v:3858.161-3858.291" + cell $and $and$ls180.v:3858$304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3989$401_Y - connect \B $not$ls180.v:3989$402_Y - connect \Y $and$ls180.v:3989$403_Y + connect \A $and$ls180.v:3858$302_Y + connect \B $not$ls180.v:3858$303_Y + connect \Y $and$ls180.v:3858$304_Y end - attribute \src "ls180.v:3989.76-3989.333" - cell $and $and$ls180.v:3989$406 + attribute \src "ls180.v:3858.76-3858.333" + cell $and $and$ls180.v:3858$307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3989$399_Y - connect \B $or$ls180.v:3989$405_Y - connect \Y $and$ls180.v:3989$406_Y + connect \A $and$ls180.v:3858$300_Y + connect \B $or$ls180.v:3858$306_Y + connect \Y $and$ls180.v:3858$307_Y end - attribute \src "ls180.v:3989.338-3989.505" - cell $and $and$ls180.v:3989$409 + attribute \src "ls180.v:3858.338-3858.505" + cell $and $and$ls180.v:3858$310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3989$407_Y - connect \B $eq$ls180.v:3989$408_Y - connect \Y $and$ls180.v:3989$409_Y + connect \A $eq$ls180.v:3858$308_Y + connect \B $eq$ls180.v:3858$309_Y + connect \Y $and$ls180.v:3858$310_Y end - attribute \src "ls180.v:3989.38-3989.507" - cell $and $and$ls180.v:3989$411 + attribute \src "ls180.v:3858.38-3858.507" + cell $and $and$ls180.v:3858$312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3989$410_Y - connect \Y $and$ls180.v:3989$411_Y + connect \B $or$ls180.v:3858$311_Y + connect \Y $and$ls180.v:3858$312_Y end - attribute \src "ls180.v:3990.77-3990.153" - cell $and $and$ls180.v:3990$412 + attribute \src "ls180.v:3859.77-3859.153" + cell $and $and$ls180.v:3859$313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257723,65 +256165,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3990$412_Y + connect \Y $and$ls180.v:3859$313_Y end - attribute \src "ls180.v:3990.162-3990.246" - cell $and $and$ls180.v:3990$414 + attribute \src "ls180.v:3859.162-3859.246" + cell $and $and$ls180.v:3859$315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3990$413_Y - connect \Y $and$ls180.v:3990$414_Y + connect \B $not$ls180.v:3859$314_Y + connect \Y $and$ls180.v:3859$315_Y end - attribute \src "ls180.v:3990.161-3990.291" - cell $and $and$ls180.v:3990$416 + attribute \src "ls180.v:3859.161-3859.291" + cell $and $and$ls180.v:3859$317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3990$414_Y - connect \B $not$ls180.v:3990$415_Y - connect \Y $and$ls180.v:3990$416_Y + connect \A $and$ls180.v:3859$315_Y + connect \B $not$ls180.v:3859$316_Y + connect \Y $and$ls180.v:3859$317_Y end - attribute \src "ls180.v:3990.76-3990.333" - cell $and $and$ls180.v:3990$419 + attribute \src "ls180.v:3859.76-3859.333" + cell $and $and$ls180.v:3859$320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3990$412_Y - connect \B $or$ls180.v:3990$418_Y - connect \Y $and$ls180.v:3990$419_Y + connect \A $and$ls180.v:3859$313_Y + connect \B $or$ls180.v:3859$319_Y + connect \Y $and$ls180.v:3859$320_Y end - attribute \src "ls180.v:3990.338-3990.505" - cell $and $and$ls180.v:3990$422 + attribute \src "ls180.v:3859.338-3859.505" + cell $and $and$ls180.v:3859$323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3990$420_Y - connect \B $eq$ls180.v:3990$421_Y - connect \Y $and$ls180.v:3990$422_Y + connect \A $eq$ls180.v:3859$321_Y + connect \B $eq$ls180.v:3859$322_Y + connect \Y $and$ls180.v:3859$323_Y end - attribute \src "ls180.v:3990.38-3990.507" - cell $and $and$ls180.v:3990$424 + attribute \src "ls180.v:3859.38-3859.507" + cell $and $and$ls180.v:3859$325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3990$423_Y - connect \Y $and$ls180.v:3990$424_Y + connect \B $or$ls180.v:3859$324_Y + connect \Y $and$ls180.v:3859$325_Y end - attribute \src "ls180.v:3991.77-3991.153" - cell $and $and$ls180.v:3991$425 + attribute \src "ls180.v:3860.77-3860.153" + cell $and $and$ls180.v:3860$326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257789,65 +256231,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3991$425_Y + connect \Y $and$ls180.v:3860$326_Y end - attribute \src "ls180.v:3991.162-3991.246" - cell $and $and$ls180.v:3991$427 + attribute \src "ls180.v:3860.162-3860.246" + cell $and $and$ls180.v:3860$328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3991$426_Y - connect \Y $and$ls180.v:3991$427_Y + connect \B $not$ls180.v:3860$327_Y + connect \Y $and$ls180.v:3860$328_Y end - attribute \src "ls180.v:3991.161-3991.291" - cell $and $and$ls180.v:3991$429 + attribute \src "ls180.v:3860.161-3860.291" + cell $and $and$ls180.v:3860$330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3991$427_Y - connect \B $not$ls180.v:3991$428_Y - connect \Y $and$ls180.v:3991$429_Y + connect \A $and$ls180.v:3860$328_Y + connect \B $not$ls180.v:3860$329_Y + connect \Y $and$ls180.v:3860$330_Y end - attribute \src "ls180.v:3991.76-3991.333" - cell $and $and$ls180.v:3991$432 + attribute \src "ls180.v:3860.76-3860.333" + cell $and $and$ls180.v:3860$333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3991$425_Y - connect \B $or$ls180.v:3991$431_Y - connect \Y $and$ls180.v:3991$432_Y + connect \A $and$ls180.v:3860$326_Y + connect \B $or$ls180.v:3860$332_Y + connect \Y $and$ls180.v:3860$333_Y end - attribute \src "ls180.v:3991.338-3991.505" - cell $and $and$ls180.v:3991$435 + attribute \src "ls180.v:3860.338-3860.505" + cell $and $and$ls180.v:3860$336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3991$433_Y - connect \B $eq$ls180.v:3991$434_Y - connect \Y $and$ls180.v:3991$435_Y + connect \A $eq$ls180.v:3860$334_Y + connect \B $eq$ls180.v:3860$335_Y + connect \Y $and$ls180.v:3860$336_Y end - attribute \src "ls180.v:3991.38-3991.507" - cell $and $and$ls180.v:3991$437 + attribute \src "ls180.v:3860.38-3860.507" + cell $and $and$ls180.v:3860$338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3991$436_Y - connect \Y $and$ls180.v:3991$437_Y + connect \B $or$ls180.v:3860$337_Y + connect \Y $and$ls180.v:3860$338_Y end - attribute \src "ls180.v:4021.77-4021.153" - cell $and $and$ls180.v:4021$444 + attribute \src "ls180.v:3890.77-3890.153" + cell $and $and$ls180.v:3890$345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257855,65 +256297,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:4021$444_Y + connect \Y $and$ls180.v:3890$345_Y end - attribute \src "ls180.v:4021.162-4021.246" - cell $and $and$ls180.v:4021$446 + attribute \src "ls180.v:3890.162-3890.246" + cell $and $and$ls180.v:3890$347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:4021$445_Y - connect \Y $and$ls180.v:4021$446_Y + connect \B $not$ls180.v:3890$346_Y + connect \Y $and$ls180.v:3890$347_Y end - attribute \src "ls180.v:4021.161-4021.291" - cell $and $and$ls180.v:4021$448 + attribute \src "ls180.v:3890.161-3890.291" + cell $and $and$ls180.v:3890$349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4021$446_Y - connect \B $not$ls180.v:4021$447_Y - connect \Y $and$ls180.v:4021$448_Y + connect \A $and$ls180.v:3890$347_Y + connect \B $not$ls180.v:3890$348_Y + connect \Y $and$ls180.v:3890$349_Y end - attribute \src "ls180.v:4021.76-4021.333" - cell $and $and$ls180.v:4021$451 + attribute \src "ls180.v:3890.76-3890.333" + cell $and $and$ls180.v:3890$352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4021$444_Y - connect \B $or$ls180.v:4021$450_Y - connect \Y $and$ls180.v:4021$451_Y + connect \A $and$ls180.v:3890$345_Y + connect \B $or$ls180.v:3890$351_Y + connect \Y $and$ls180.v:3890$352_Y end - attribute \src "ls180.v:4021.338-4021.505" - cell $and $and$ls180.v:4021$454 + attribute \src "ls180.v:3890.338-3890.505" + cell $and $and$ls180.v:3890$355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4021$452_Y - connect \B $eq$ls180.v:4021$453_Y - connect \Y $and$ls180.v:4021$454_Y + connect \A $eq$ls180.v:3890$353_Y + connect \B $eq$ls180.v:3890$354_Y + connect \Y $and$ls180.v:3890$355_Y end - attribute \src "ls180.v:4021.38-4021.507" - cell $and $and$ls180.v:4021$456 + attribute \src "ls180.v:3890.38-3890.507" + cell $and $and$ls180.v:3890$357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:4021$455_Y - connect \Y $and$ls180.v:4021$456_Y + connect \B $or$ls180.v:3890$356_Y + connect \Y $and$ls180.v:3890$357_Y end - attribute \src "ls180.v:4022.77-4022.153" - cell $and $and$ls180.v:4022$457 + attribute \src "ls180.v:3891.77-3891.153" + cell $and $and$ls180.v:3891$358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257921,65 +256363,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:4022$457_Y + connect \Y $and$ls180.v:3891$358_Y end - attribute \src "ls180.v:4022.162-4022.246" - cell $and $and$ls180.v:4022$459 + attribute \src "ls180.v:3891.162-3891.246" + cell $and $and$ls180.v:3891$360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:4022$458_Y - connect \Y $and$ls180.v:4022$459_Y + connect \B $not$ls180.v:3891$359_Y + connect \Y $and$ls180.v:3891$360_Y end - attribute \src "ls180.v:4022.161-4022.291" - cell $and $and$ls180.v:4022$461 + attribute \src "ls180.v:3891.161-3891.291" + cell $and $and$ls180.v:3891$362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4022$459_Y - connect \B $not$ls180.v:4022$460_Y - connect \Y $and$ls180.v:4022$461_Y + connect \A $and$ls180.v:3891$360_Y + connect \B $not$ls180.v:3891$361_Y + connect \Y $and$ls180.v:3891$362_Y end - attribute \src "ls180.v:4022.76-4022.333" - cell $and $and$ls180.v:4022$464 + attribute \src "ls180.v:3891.76-3891.333" + cell $and $and$ls180.v:3891$365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4022$457_Y - connect \B $or$ls180.v:4022$463_Y - connect \Y $and$ls180.v:4022$464_Y + connect \A $and$ls180.v:3891$358_Y + connect \B $or$ls180.v:3891$364_Y + connect \Y $and$ls180.v:3891$365_Y end - attribute \src "ls180.v:4022.338-4022.505" - cell $and $and$ls180.v:4022$467 + attribute \src "ls180.v:3891.338-3891.505" + cell $and $and$ls180.v:3891$368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4022$465_Y - connect \B $eq$ls180.v:4022$466_Y - connect \Y $and$ls180.v:4022$467_Y + connect \A $eq$ls180.v:3891$366_Y + connect \B $eq$ls180.v:3891$367_Y + connect \Y $and$ls180.v:3891$368_Y end - attribute \src "ls180.v:4022.38-4022.507" - cell $and $and$ls180.v:4022$469 + attribute \src "ls180.v:3891.38-3891.507" + cell $and $and$ls180.v:3891$370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:4022$468_Y - connect \Y $and$ls180.v:4022$469_Y + connect \B $or$ls180.v:3891$369_Y + connect \Y $and$ls180.v:3891$370_Y end - attribute \src "ls180.v:4023.77-4023.153" - cell $and $and$ls180.v:4023$470 + attribute \src "ls180.v:3892.77-3892.153" + cell $and $and$ls180.v:3892$371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -257987,65 +256429,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:4023$470_Y + connect \Y $and$ls180.v:3892$371_Y end - attribute \src "ls180.v:4023.162-4023.246" - cell $and $and$ls180.v:4023$472 + attribute \src "ls180.v:3892.162-3892.246" + cell $and $and$ls180.v:3892$373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:4023$471_Y - connect \Y $and$ls180.v:4023$472_Y + connect \B $not$ls180.v:3892$372_Y + connect \Y $and$ls180.v:3892$373_Y end - attribute \src "ls180.v:4023.161-4023.291" - cell $and $and$ls180.v:4023$474 + attribute \src "ls180.v:3892.161-3892.291" + cell $and $and$ls180.v:3892$375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4023$472_Y - connect \B $not$ls180.v:4023$473_Y - connect \Y $and$ls180.v:4023$474_Y + connect \A $and$ls180.v:3892$373_Y + connect \B $not$ls180.v:3892$374_Y + connect \Y $and$ls180.v:3892$375_Y end - attribute \src "ls180.v:4023.76-4023.333" - cell $and $and$ls180.v:4023$477 + attribute \src "ls180.v:3892.76-3892.333" + cell $and $and$ls180.v:3892$378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4023$470_Y - connect \B $or$ls180.v:4023$476_Y - connect \Y $and$ls180.v:4023$477_Y + connect \A $and$ls180.v:3892$371_Y + connect \B $or$ls180.v:3892$377_Y + connect \Y $and$ls180.v:3892$378_Y end - attribute \src "ls180.v:4023.338-4023.505" - cell $and $and$ls180.v:4023$480 + attribute \src "ls180.v:3892.338-3892.505" + cell $and $and$ls180.v:3892$381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4023$478_Y - connect \B $eq$ls180.v:4023$479_Y - connect \Y $and$ls180.v:4023$480_Y + connect \A $eq$ls180.v:3892$379_Y + connect \B $eq$ls180.v:3892$380_Y + connect \Y $and$ls180.v:3892$381_Y end - attribute \src "ls180.v:4023.38-4023.507" - cell $and $and$ls180.v:4023$482 + attribute \src "ls180.v:3892.38-3892.507" + cell $and $and$ls180.v:3892$383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:4023$481_Y - connect \Y $and$ls180.v:4023$482_Y + connect \B $or$ls180.v:3892$382_Y + connect \Y $and$ls180.v:3892$383_Y end - attribute \src "ls180.v:4024.77-4024.153" - cell $and $and$ls180.v:4024$483 + attribute \src "ls180.v:3893.77-3893.153" + cell $and $and$ls180.v:3893$384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258053,65 +256495,65 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:4024$483_Y + connect \Y $and$ls180.v:3893$384_Y end - attribute \src "ls180.v:4024.162-4024.246" - cell $and $and$ls180.v:4024$485 + attribute \src "ls180.v:3893.162-3893.246" + cell $and $and$ls180.v:3893$386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:4024$484_Y - connect \Y $and$ls180.v:4024$485_Y + connect \B $not$ls180.v:3893$385_Y + connect \Y $and$ls180.v:3893$386_Y end - attribute \src "ls180.v:4024.161-4024.291" - cell $and $and$ls180.v:4024$487 + attribute \src "ls180.v:3893.161-3893.291" + cell $and $and$ls180.v:3893$388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4024$485_Y - connect \B $not$ls180.v:4024$486_Y - connect \Y $and$ls180.v:4024$487_Y + connect \A $and$ls180.v:3893$386_Y + connect \B $not$ls180.v:3893$387_Y + connect \Y $and$ls180.v:3893$388_Y end - attribute \src "ls180.v:4024.76-4024.333" - cell $and $and$ls180.v:4024$490 + attribute \src "ls180.v:3893.76-3893.333" + cell $and $and$ls180.v:3893$391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4024$483_Y - connect \B $or$ls180.v:4024$489_Y - connect \Y $and$ls180.v:4024$490_Y + connect \A $and$ls180.v:3893$384_Y + connect \B $or$ls180.v:3893$390_Y + connect \Y $and$ls180.v:3893$391_Y end - attribute \src "ls180.v:4024.338-4024.505" - cell $and $and$ls180.v:4024$493 + attribute \src "ls180.v:3893.338-3893.505" + cell $and $and$ls180.v:3893$394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4024$491_Y - connect \B $eq$ls180.v:4024$492_Y - connect \Y $and$ls180.v:4024$493_Y + connect \A $eq$ls180.v:3893$392_Y + connect \B $eq$ls180.v:3893$393_Y + connect \Y $and$ls180.v:3893$394_Y end - attribute \src "ls180.v:4024.38-4024.507" - cell $and $and$ls180.v:4024$495 + attribute \src "ls180.v:3893.38-3893.507" + cell $and $and$ls180.v:3893$396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:4024$494_Y - connect \Y $and$ls180.v:4024$495_Y + connect \B $or$ls180.v:3893$395_Y + connect \Y $and$ls180.v:3893$396_Y end - attribute \src "ls180.v:4053.8-4053.73" - cell $and $and$ls180.v:4053$500 + attribute \src "ls180.v:3922.8-3922.73" + cell $and $and$ls180.v:3922$401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258119,21 +256561,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:4053$500_Y + connect \Y $and$ls180.v:3922$401_Y end - attribute \src "ls180.v:4053.7-4053.114" - cell $and $and$ls180.v:4053$502 + attribute \src "ls180.v:3922.7-3922.114" + cell $and $and$ls180.v:3922$403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4053$500_Y - connect \B $eq$ls180.v:4053$501_Y - connect \Y $and$ls180.v:4053$502_Y + connect \A $and$ls180.v:3922$401_Y + connect \B $eq$ls180.v:3922$402_Y + connect \Y $and$ls180.v:3922$403_Y end - attribute \src "ls180.v:4056.8-4056.73" - cell $and $and$ls180.v:4056$503 + attribute \src "ls180.v:3925.8-3925.73" + cell $and $and$ls180.v:3925$404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258141,21 +256583,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4056$503_Y + connect \Y $and$ls180.v:3925$404_Y end - attribute \src "ls180.v:4056.7-4056.114" - cell $and $and$ls180.v:4056$505 + attribute \src "ls180.v:3925.7-3925.114" + cell $and $and$ls180.v:3925$406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4056$503_Y - connect \B $eq$ls180.v:4056$504_Y - connect \Y $and$ls180.v:4056$505_Y + connect \A $and$ls180.v:3925$404_Y + connect \B $eq$ls180.v:3925$405_Y + connect \Y $and$ls180.v:3925$406_Y end - attribute \src "ls180.v:4062.8-4062.73" - cell $and $and$ls180.v:4062$507 + attribute \src "ls180.v:3931.8-3931.73" + cell $and $and$ls180.v:3931$408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258163,21 +256605,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:4062$507_Y + connect \Y $and$ls180.v:3931$408_Y end - attribute \src "ls180.v:4062.7-4062.114" - cell $and $and$ls180.v:4062$509 + attribute \src "ls180.v:3931.7-3931.114" + cell $and $and$ls180.v:3931$410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4062$507_Y - connect \B $eq$ls180.v:4062$508_Y - connect \Y $and$ls180.v:4062$509_Y + connect \A $and$ls180.v:3931$408_Y + connect \B $eq$ls180.v:3931$409_Y + connect \Y $and$ls180.v:3931$410_Y end - attribute \src "ls180.v:4065.8-4065.73" - cell $and $and$ls180.v:4065$510 + attribute \src "ls180.v:3934.8-3934.73" + cell $and $and$ls180.v:3934$411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258185,21 +256627,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4065$510_Y + connect \Y $and$ls180.v:3934$411_Y end - attribute \src "ls180.v:4065.7-4065.114" - cell $and $and$ls180.v:4065$512 + attribute \src "ls180.v:3934.7-3934.114" + cell $and $and$ls180.v:3934$413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4065$510_Y - connect \B $eq$ls180.v:4065$511_Y - connect \Y $and$ls180.v:4065$512_Y + connect \A $and$ls180.v:3934$411_Y + connect \B $eq$ls180.v:3934$412_Y + connect \Y $and$ls180.v:3934$413_Y end - attribute \src "ls180.v:4071.8-4071.73" - cell $and $and$ls180.v:4071$514 + attribute \src "ls180.v:3940.8-3940.73" + cell $and $and$ls180.v:3940$415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258207,21 +256649,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:4071$514_Y + connect \Y $and$ls180.v:3940$415_Y end - attribute \src "ls180.v:4071.7-4071.114" - cell $and $and$ls180.v:4071$516 + attribute \src "ls180.v:3940.7-3940.114" + cell $and $and$ls180.v:3940$417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4071$514_Y - connect \B $eq$ls180.v:4071$515_Y - connect \Y $and$ls180.v:4071$516_Y + connect \A $and$ls180.v:3940$415_Y + connect \B $eq$ls180.v:3940$416_Y + connect \Y $and$ls180.v:3940$417_Y end - attribute \src "ls180.v:4074.8-4074.73" - cell $and $and$ls180.v:4074$517 + attribute \src "ls180.v:3943.8-3943.73" + cell $and $and$ls180.v:3943$418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258229,21 +256671,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4074$517_Y + connect \Y $and$ls180.v:3943$418_Y end - attribute \src "ls180.v:4074.7-4074.114" - cell $and $and$ls180.v:4074$519 + attribute \src "ls180.v:3943.7-3943.114" + cell $and $and$ls180.v:3943$420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4074$517_Y - connect \B $eq$ls180.v:4074$518_Y - connect \Y $and$ls180.v:4074$519_Y + connect \A $and$ls180.v:3943$418_Y + connect \B $eq$ls180.v:3943$419_Y + connect \Y $and$ls180.v:3943$420_Y end - attribute \src "ls180.v:4080.8-4080.73" - cell $and $and$ls180.v:4080$521 + attribute \src "ls180.v:3949.8-3949.73" + cell $and $and$ls180.v:3949$422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258251,21 +256693,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:4080$521_Y + connect \Y $and$ls180.v:3949$422_Y end - attribute \src "ls180.v:4080.7-4080.114" - cell $and $and$ls180.v:4080$523 + attribute \src "ls180.v:3949.7-3949.114" + cell $and $and$ls180.v:3949$424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4080$521_Y - connect \B $eq$ls180.v:4080$522_Y - connect \Y $and$ls180.v:4080$523_Y + connect \A $and$ls180.v:3949$422_Y + connect \B $eq$ls180.v:3949$423_Y + connect \Y $and$ls180.v:3949$424_Y end - attribute \src "ls180.v:4083.8-4083.73" - cell $and $and$ls180.v:4083$524 + attribute \src "ls180.v:3952.8-3952.73" + cell $and $and$ls180.v:3952$425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258273,615 +256715,615 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:4083$524_Y + connect \Y $and$ls180.v:3952$425_Y end - attribute \src "ls180.v:4083.7-4083.114" - cell $and $and$ls180.v:4083$526 + attribute \src "ls180.v:3952.7-3952.114" + cell $and $and$ls180.v:3952$427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4083$524_Y - connect \B $eq$ls180.v:4083$525_Y - connect \Y $and$ls180.v:4083$526_Y + connect \A $and$ls180.v:3952$425_Y + connect \B $eq$ls180.v:3952$426_Y + connect \Y $and$ls180.v:3952$427_Y end - attribute \src "ls180.v:4108.71-4108.151" - cell $and $and$ls180.v:4108$531 + attribute \src "ls180.v:3977.71-3977.151" + cell $and $and$ls180.v:3977$432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:4108$530_Y - connect \Y $and$ls180.v:4108$531_Y + connect \B $not$ls180.v:3977$431_Y + connect \Y $and$ls180.v:3977$432_Y end - attribute \src "ls180.v:4108.70-4108.194" - cell $and $and$ls180.v:4108$533 + attribute \src "ls180.v:3977.70-3977.194" + cell $and $and$ls180.v:3977$434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4108$531_Y - connect \B $not$ls180.v:4108$532_Y - connect \Y $and$ls180.v:4108$533_Y + connect \A $and$ls180.v:3977$432_Y + connect \B $not$ls180.v:3977$433_Y + connect \Y $and$ls180.v:3977$434_Y end - attribute \src "ls180.v:4108.41-4108.222" - cell $and $and$ls180.v:4108$536 + attribute \src "ls180.v:3977.41-3977.222" + cell $and $and$ls180.v:3977$437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:4108$535_Y - connect \Y $and$ls180.v:4108$536_Y + connect \B $or$ls180.v:3977$436_Y + connect \Y $and$ls180.v:3977$437_Y end - attribute \src "ls180.v:4146.71-4146.151" - cell $and $and$ls180.v:4146$540 + attribute \src "ls180.v:4015.71-4015.151" + cell $and $and$ls180.v:4015$441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:4146$539_Y - connect \Y $and$ls180.v:4146$540_Y + connect \B $not$ls180.v:4015$440_Y + connect \Y $and$ls180.v:4015$441_Y end - attribute \src "ls180.v:4146.70-4146.194" - cell $and $and$ls180.v:4146$542 + attribute \src "ls180.v:4015.70-4015.194" + cell $and $and$ls180.v:4015$443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4146$540_Y - connect \B $not$ls180.v:4146$541_Y - connect \Y $and$ls180.v:4146$542_Y + connect \A $and$ls180.v:4015$441_Y + connect \B $not$ls180.v:4015$442_Y + connect \Y $and$ls180.v:4015$443_Y end - attribute \src "ls180.v:4146.41-4146.222" - cell $and $and$ls180.v:4146$545 + attribute \src "ls180.v:4015.41-4015.222" + cell $and $and$ls180.v:4015$446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:4146$544_Y - connect \Y $and$ls180.v:4146$545_Y + connect \B $or$ls180.v:4015$445_Y + connect \Y $and$ls180.v:4015$446_Y end - attribute \src "ls180.v:4164.110-4164.179" - cell $and $and$ls180.v:4164$550 + attribute \src "ls180.v:4033.110-4033.179" + cell $and $and$ls180.v:4033$451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4164$549_Y - connect \Y $and$ls180.v:4164$550_Y + connect \B $eq$ls180.v:4033$450_Y + connect \Y $and$ls180.v:4033$451_Y end - attribute \src "ls180.v:4164.185-4164.254" - cell $and $and$ls180.v:4164$553 + attribute \src "ls180.v:4033.185-4033.254" + cell $and $and$ls180.v:4033$454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4164$552_Y - connect \Y $and$ls180.v:4164$553_Y + connect \B $eq$ls180.v:4033$453_Y + connect \Y $and$ls180.v:4033$454_Y end - attribute \src "ls180.v:4164.260-4164.329" - cell $and $and$ls180.v:4164$556 + attribute \src "ls180.v:4033.260-4033.329" + cell $and $and$ls180.v:4033$457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4164$555_Y - connect \Y $and$ls180.v:4164$556_Y + connect \B $eq$ls180.v:4033$456_Y + connect \Y $and$ls180.v:4033$457_Y end - attribute \src "ls180.v:4164.41-4164.332" - cell $and $and$ls180.v:4164$559 + attribute \src "ls180.v:4033.41-4033.332" + cell $and $and$ls180.v:4033$460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4164$548_Y - connect \B $not$ls180.v:4164$558_Y - connect \Y $and$ls180.v:4164$559_Y + connect \A $eq$ls180.v:4033$449_Y + connect \B $not$ls180.v:4033$459_Y + connect \Y $and$ls180.v:4033$460_Y end - attribute \src "ls180.v:4164.40-4164.355" - cell $and $and$ls180.v:4164$560 + attribute \src "ls180.v:4033.40-4033.355" + cell $and $and$ls180.v:4033$461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4164$559_Y + connect \A $and$ls180.v:4033$460_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4164$560_Y + connect \Y $and$ls180.v:4033$461_Y end - attribute \src "ls180.v:4165.34-4165.106" - cell $and $and$ls180.v:4165$563 + attribute \src "ls180.v:4034.34-4034.106" + cell $and $and$ls180.v:4034$464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4165$561_Y - connect \B $not$ls180.v:4165$562_Y - connect \Y $and$ls180.v:4165$563_Y + connect \A $not$ls180.v:4034$462_Y + connect \B $not$ls180.v:4034$463_Y + connect \Y $and$ls180.v:4034$464_Y end - attribute \src "ls180.v:4169.110-4169.179" - cell $and $and$ls180.v:4169$566 + attribute \src "ls180.v:4038.110-4038.179" + cell $and $and$ls180.v:4038$467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4169$565_Y - connect \Y $and$ls180.v:4169$566_Y + connect \B $eq$ls180.v:4038$466_Y + connect \Y $and$ls180.v:4038$467_Y end - attribute \src "ls180.v:4169.185-4169.254" - cell $and $and$ls180.v:4169$569 + attribute \src "ls180.v:4038.185-4038.254" + cell $and $and$ls180.v:4038$470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4169$568_Y - connect \Y $and$ls180.v:4169$569_Y + connect \B $eq$ls180.v:4038$469_Y + connect \Y $and$ls180.v:4038$470_Y end - attribute \src "ls180.v:4169.260-4169.329" - cell $and $and$ls180.v:4169$572 + attribute \src "ls180.v:4038.260-4038.329" + cell $and $and$ls180.v:4038$473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4169$571_Y - connect \Y $and$ls180.v:4169$572_Y + connect \B $eq$ls180.v:4038$472_Y + connect \Y $and$ls180.v:4038$473_Y end - attribute \src "ls180.v:4169.41-4169.332" - cell $and $and$ls180.v:4169$575 + attribute \src "ls180.v:4038.41-4038.332" + cell $and $and$ls180.v:4038$476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4169$564_Y - connect \B $not$ls180.v:4169$574_Y - connect \Y $and$ls180.v:4169$575_Y + connect \A $eq$ls180.v:4038$465_Y + connect \B $not$ls180.v:4038$475_Y + connect \Y $and$ls180.v:4038$476_Y end - attribute \src "ls180.v:4169.40-4169.355" - cell $and $and$ls180.v:4169$576 + attribute \src "ls180.v:4038.40-4038.355" + cell $and $and$ls180.v:4038$477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4169$575_Y + connect \A $and$ls180.v:4038$476_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4169$576_Y + connect \Y $and$ls180.v:4038$477_Y end - attribute \src "ls180.v:4170.34-4170.106" - cell $and $and$ls180.v:4170$579 + attribute \src "ls180.v:4039.34-4039.106" + cell $and $and$ls180.v:4039$480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4170$577_Y - connect \B $not$ls180.v:4170$578_Y - connect \Y $and$ls180.v:4170$579_Y + connect \A $not$ls180.v:4039$478_Y + connect \B $not$ls180.v:4039$479_Y + connect \Y $and$ls180.v:4039$480_Y end - attribute \src "ls180.v:4174.110-4174.179" - cell $and $and$ls180.v:4174$582 + attribute \src "ls180.v:4043.110-4043.179" + cell $and $and$ls180.v:4043$483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4174$581_Y - connect \Y $and$ls180.v:4174$582_Y + connect \B $eq$ls180.v:4043$482_Y + connect \Y $and$ls180.v:4043$483_Y end - attribute \src "ls180.v:4174.185-4174.254" - cell $and $and$ls180.v:4174$585 + attribute \src "ls180.v:4043.185-4043.254" + cell $and $and$ls180.v:4043$486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4174$584_Y - connect \Y $and$ls180.v:4174$585_Y + connect \B $eq$ls180.v:4043$485_Y + connect \Y $and$ls180.v:4043$486_Y end - attribute \src "ls180.v:4174.260-4174.329" - cell $and $and$ls180.v:4174$588 + attribute \src "ls180.v:4043.260-4043.329" + cell $and $and$ls180.v:4043$489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4174$587_Y - connect \Y $and$ls180.v:4174$588_Y + connect \B $eq$ls180.v:4043$488_Y + connect \Y $and$ls180.v:4043$489_Y end - attribute \src "ls180.v:4174.41-4174.332" - cell $and $and$ls180.v:4174$591 + attribute \src "ls180.v:4043.41-4043.332" + cell $and $and$ls180.v:4043$492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4174$580_Y - connect \B $not$ls180.v:4174$590_Y - connect \Y $and$ls180.v:4174$591_Y + connect \A $eq$ls180.v:4043$481_Y + connect \B $not$ls180.v:4043$491_Y + connect \Y $and$ls180.v:4043$492_Y end - attribute \src "ls180.v:4174.40-4174.355" - cell $and $and$ls180.v:4174$592 + attribute \src "ls180.v:4043.40-4043.355" + cell $and $and$ls180.v:4043$493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4174$591_Y + connect \A $and$ls180.v:4043$492_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4174$592_Y + connect \Y $and$ls180.v:4043$493_Y end - attribute \src "ls180.v:4175.34-4175.106" - cell $and $and$ls180.v:4175$595 + attribute \src "ls180.v:4044.34-4044.106" + cell $and $and$ls180.v:4044$496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4175$593_Y - connect \B $not$ls180.v:4175$594_Y - connect \Y $and$ls180.v:4175$595_Y + connect \A $not$ls180.v:4044$494_Y + connect \B $not$ls180.v:4044$495_Y + connect \Y $and$ls180.v:4044$496_Y end - attribute \src "ls180.v:4179.110-4179.179" - cell $and $and$ls180.v:4179$598 + attribute \src "ls180.v:4048.110-4048.179" + cell $and $and$ls180.v:4048$499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4179$597_Y - connect \Y $and$ls180.v:4179$598_Y + connect \B $eq$ls180.v:4048$498_Y + connect \Y $and$ls180.v:4048$499_Y end - attribute \src "ls180.v:4179.185-4179.254" - cell $and $and$ls180.v:4179$601 + attribute \src "ls180.v:4048.185-4048.254" + cell $and $and$ls180.v:4048$502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4179$600_Y - connect \Y $and$ls180.v:4179$601_Y + connect \B $eq$ls180.v:4048$501_Y + connect \Y $and$ls180.v:4048$502_Y end - attribute \src "ls180.v:4179.260-4179.329" - cell $and $and$ls180.v:4179$604 + attribute \src "ls180.v:4048.260-4048.329" + cell $and $and$ls180.v:4048$505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4179$603_Y - connect \Y $and$ls180.v:4179$604_Y + connect \B $eq$ls180.v:4048$504_Y + connect \Y $and$ls180.v:4048$505_Y end - attribute \src "ls180.v:4179.41-4179.332" - cell $and $and$ls180.v:4179$607 + attribute \src "ls180.v:4048.41-4048.332" + cell $and $and$ls180.v:4048$508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4179$596_Y - connect \B $not$ls180.v:4179$606_Y - connect \Y $and$ls180.v:4179$607_Y + connect \A $eq$ls180.v:4048$497_Y + connect \B $not$ls180.v:4048$507_Y + connect \Y $and$ls180.v:4048$508_Y end - attribute \src "ls180.v:4179.40-4179.355" - cell $and $and$ls180.v:4179$608 + attribute \src "ls180.v:4048.40-4048.355" + cell $and $and$ls180.v:4048$509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4179$607_Y + connect \A $and$ls180.v:4048$508_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4179$608_Y + connect \Y $and$ls180.v:4048$509_Y end - attribute \src "ls180.v:4180.34-4180.106" - cell $and $and$ls180.v:4180$611 + attribute \src "ls180.v:4049.34-4049.106" + cell $and $and$ls180.v:4049$512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4180$609_Y - connect \B $not$ls180.v:4180$610_Y - connect \Y $and$ls180.v:4180$611_Y + connect \A $not$ls180.v:4049$510_Y + connect \B $not$ls180.v:4049$511_Y + connect \Y $and$ls180.v:4049$512_Y end - attribute \src "ls180.v:4184.151-4184.220" - cell $and $and$ls180.v:4184$615 + attribute \src "ls180.v:4053.151-4053.220" + cell $and $and$ls180.v:4053$516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4184$614_Y - connect \Y $and$ls180.v:4184$615_Y + connect \B $eq$ls180.v:4053$515_Y + connect \Y $and$ls180.v:4053$516_Y end - attribute \src "ls180.v:4184.226-4184.295" - cell $and $and$ls180.v:4184$618 + attribute \src "ls180.v:4053.226-4053.295" + cell $and $and$ls180.v:4053$519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4184$617_Y - connect \Y $and$ls180.v:4184$618_Y + connect \B $eq$ls180.v:4053$518_Y + connect \Y $and$ls180.v:4053$519_Y end - attribute \src "ls180.v:4184.301-4184.370" - cell $and $and$ls180.v:4184$621 + attribute \src "ls180.v:4053.301-4053.370" + cell $and $and$ls180.v:4053$522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4184$620_Y - connect \Y $and$ls180.v:4184$621_Y + connect \B $eq$ls180.v:4053$521_Y + connect \Y $and$ls180.v:4053$522_Y end - attribute \src "ls180.v:4184.82-4184.373" - cell $and $and$ls180.v:4184$624 + attribute \src "ls180.v:4053.82-4053.373" + cell $and $and$ls180.v:4053$525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4184$613_Y - connect \B $not$ls180.v:4184$623_Y - connect \Y $and$ls180.v:4184$624_Y + connect \A $eq$ls180.v:4053$514_Y + connect \B $not$ls180.v:4053$524_Y + connect \Y $and$ls180.v:4053$525_Y end - attribute \src "ls180.v:4184.43-4184.374" - cell $and $and$ls180.v:4184$625 + attribute \src "ls180.v:4053.43-4053.374" + cell $and $and$ls180.v:4053$526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4184$612_Y - connect \B $and$ls180.v:4184$624_Y - connect \Y $and$ls180.v:4184$625_Y + connect \A $eq$ls180.v:4053$513_Y + connect \B $and$ls180.v:4053$525_Y + connect \Y $and$ls180.v:4053$526_Y end - attribute \src "ls180.v:4184.42-4184.410" - cell $and $and$ls180.v:4184$626 + attribute \src "ls180.v:4053.42-4053.410" + cell $and $and$ls180.v:4053$527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4184$625_Y + connect \A $and$ls180.v:4053$526_Y connect \B \main_sdram_interface_bank0_ready - connect \Y $and$ls180.v:4184$626_Y + connect \Y $and$ls180.v:4053$527_Y end - attribute \src "ls180.v:4184.525-4184.594" - cell $and $and$ls180.v:4184$631 + attribute \src "ls180.v:4053.525-4053.594" + cell $and $and$ls180.v:4053$532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4184$630_Y - connect \Y $and$ls180.v:4184$631_Y + connect \B $eq$ls180.v:4053$531_Y + connect \Y $and$ls180.v:4053$532_Y end - attribute \src "ls180.v:4184.600-4184.669" - cell $and $and$ls180.v:4184$634 + attribute \src "ls180.v:4053.600-4053.669" + cell $and $and$ls180.v:4053$535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4184$633_Y - connect \Y $and$ls180.v:4184$634_Y + connect \B $eq$ls180.v:4053$534_Y + connect \Y $and$ls180.v:4053$535_Y end - attribute \src "ls180.v:4184.675-4184.744" - cell $and $and$ls180.v:4184$637 + attribute \src "ls180.v:4053.675-4053.744" + cell $and $and$ls180.v:4053$538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4184$636_Y - connect \Y $and$ls180.v:4184$637_Y + connect \B $eq$ls180.v:4053$537_Y + connect \Y $and$ls180.v:4053$538_Y end - attribute \src "ls180.v:4184.456-4184.747" - cell $and $and$ls180.v:4184$640 + attribute \src "ls180.v:4053.456-4053.747" + cell $and $and$ls180.v:4053$541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4184$629_Y - connect \B $not$ls180.v:4184$639_Y - connect \Y $and$ls180.v:4184$640_Y + connect \A $eq$ls180.v:4053$530_Y + connect \B $not$ls180.v:4053$540_Y + connect \Y $and$ls180.v:4053$541_Y end - attribute \src "ls180.v:4184.417-4184.748" - cell $and $and$ls180.v:4184$641 + attribute \src "ls180.v:4053.417-4053.748" + cell $and $and$ls180.v:4053$542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4184$628_Y - connect \B $and$ls180.v:4184$640_Y - connect \Y $and$ls180.v:4184$641_Y + connect \A $eq$ls180.v:4053$529_Y + connect \B $and$ls180.v:4053$541_Y + connect \Y $and$ls180.v:4053$542_Y end - attribute \src "ls180.v:4184.416-4184.784" - cell $and $and$ls180.v:4184$642 + attribute \src "ls180.v:4053.416-4053.784" + cell $and $and$ls180.v:4053$543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4184$641_Y + connect \A $and$ls180.v:4053$542_Y connect \B \main_sdram_interface_bank1_ready - connect \Y $and$ls180.v:4184$642_Y + connect \Y $and$ls180.v:4053$543_Y end - attribute \src "ls180.v:4184.899-4184.968" - cell $and $and$ls180.v:4184$647 + attribute \src "ls180.v:4053.899-4053.968" + cell $and $and$ls180.v:4053$548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4184$646_Y - connect \Y $and$ls180.v:4184$647_Y + connect \B $eq$ls180.v:4053$547_Y + connect \Y $and$ls180.v:4053$548_Y end - attribute \src "ls180.v:4184.974-4184.1043" - cell $and $and$ls180.v:4184$650 + attribute \src "ls180.v:4053.974-4053.1043" + cell $and $and$ls180.v:4053$551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4184$649_Y - connect \Y $and$ls180.v:4184$650_Y + connect \B $eq$ls180.v:4053$550_Y + connect \Y $and$ls180.v:4053$551_Y end - attribute \src "ls180.v:4184.1049-4184.1118" - cell $and $and$ls180.v:4184$653 + attribute \src "ls180.v:4053.1049-4053.1118" + cell $and $and$ls180.v:4053$554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4184$652_Y - connect \Y $and$ls180.v:4184$653_Y + connect \B $eq$ls180.v:4053$553_Y + connect \Y $and$ls180.v:4053$554_Y end - attribute \src "ls180.v:4184.830-4184.1121" - cell $and $and$ls180.v:4184$656 + attribute \src "ls180.v:4053.830-4053.1121" + cell $and $and$ls180.v:4053$557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4184$645_Y - connect \B $not$ls180.v:4184$655_Y - connect \Y $and$ls180.v:4184$656_Y + connect \A $eq$ls180.v:4053$546_Y + connect \B $not$ls180.v:4053$556_Y + connect \Y $and$ls180.v:4053$557_Y end - attribute \src "ls180.v:4184.791-4184.1122" - cell $and $and$ls180.v:4184$657 + attribute \src "ls180.v:4053.791-4053.1122" + cell $and $and$ls180.v:4053$558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4184$644_Y - connect \B $and$ls180.v:4184$656_Y - connect \Y $and$ls180.v:4184$657_Y + connect \A $eq$ls180.v:4053$545_Y + connect \B $and$ls180.v:4053$557_Y + connect \Y $and$ls180.v:4053$558_Y end - attribute \src "ls180.v:4184.790-4184.1158" - cell $and $and$ls180.v:4184$658 + attribute \src "ls180.v:4053.790-4053.1158" + cell $and $and$ls180.v:4053$559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4184$657_Y + connect \A $and$ls180.v:4053$558_Y connect \B \main_sdram_interface_bank2_ready - connect \Y $and$ls180.v:4184$658_Y + connect \Y $and$ls180.v:4053$559_Y end - attribute \src "ls180.v:4184.1273-4184.1342" - cell $and $and$ls180.v:4184$663 + attribute \src "ls180.v:4053.1273-4053.1342" + cell $and $and$ls180.v:4053$564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4184$662_Y - connect \Y $and$ls180.v:4184$663_Y + connect \B $eq$ls180.v:4053$563_Y + connect \Y $and$ls180.v:4053$564_Y end - attribute \src "ls180.v:4184.1348-4184.1417" - cell $and $and$ls180.v:4184$666 + attribute \src "ls180.v:4053.1348-4053.1417" + cell $and $and$ls180.v:4053$567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4184$665_Y - connect \Y $and$ls180.v:4184$666_Y + connect \B $eq$ls180.v:4053$566_Y + connect \Y $and$ls180.v:4053$567_Y end - attribute \src "ls180.v:4184.1423-4184.1492" - cell $and $and$ls180.v:4184$669 + attribute \src "ls180.v:4053.1423-4053.1492" + cell $and $and$ls180.v:4053$570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4184$668_Y - connect \Y $and$ls180.v:4184$669_Y + connect \B $eq$ls180.v:4053$569_Y + connect \Y $and$ls180.v:4053$570_Y end - attribute \src "ls180.v:4184.1204-4184.1495" - cell $and $and$ls180.v:4184$672 + attribute \src "ls180.v:4053.1204-4053.1495" + cell $and $and$ls180.v:4053$573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4184$661_Y - connect \B $not$ls180.v:4184$671_Y - connect \Y $and$ls180.v:4184$672_Y + connect \A $eq$ls180.v:4053$562_Y + connect \B $not$ls180.v:4053$572_Y + connect \Y $and$ls180.v:4053$573_Y end - attribute \src "ls180.v:4184.1165-4184.1496" - cell $and $and$ls180.v:4184$673 + attribute \src "ls180.v:4053.1165-4053.1496" + cell $and $and$ls180.v:4053$574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4184$660_Y - connect \B $and$ls180.v:4184$672_Y - connect \Y $and$ls180.v:4184$673_Y + connect \A $eq$ls180.v:4053$561_Y + connect \B $and$ls180.v:4053$573_Y + connect \Y $and$ls180.v:4053$574_Y end - attribute \src "ls180.v:4184.1164-4184.1532" - cell $and $and$ls180.v:4184$674 + attribute \src "ls180.v:4053.1164-4053.1532" + cell $and $and$ls180.v:4053$575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4184$673_Y + connect \A $and$ls180.v:4053$574_Y connect \B \main_sdram_interface_bank3_ready - connect \Y $and$ls180.v:4184$674_Y + connect \Y $and$ls180.v:4053$575_Y end - attribute \src "ls180.v:4242.9-4242.46" - cell $and $and$ls180.v:4242$680 + attribute \src "ls180.v:4111.9-4111.46" + cell $and $and$ls180.v:4111$581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258889,10 +257331,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_stb connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4242$680_Y + connect \Y $and$ls180.v:4111$581_Y end - attribute \src "ls180.v:4260.9-4260.46" - cell $and $and$ls180.v:4260$687 + attribute \src "ls180.v:4129.9-4129.46" + cell $and $and$ls180.v:4129$588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258900,10 +257342,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_stb connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4260$687_Y + connect \Y $and$ls180.v:4129$588_Y end - attribute \src "ls180.v:4273.32-4273.75" - cell $and $and$ls180.v:4273$691 + attribute \src "ls180.v:4142.32-4142.75" + cell $and $and$ls180.v:4142$592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258911,54 +257353,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_cyc connect \B \main_litedram_wb_stb - connect \Y $and$ls180.v:4273$691_Y + connect \Y $and$ls180.v:4142$592_Y end - attribute \src "ls180.v:4273.31-4273.99" - cell $and $and$ls180.v:4273$693 + attribute \src "ls180.v:4142.31-4142.99" + cell $and $and$ls180.v:4142$594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4273$691_Y - connect \B $not$ls180.v:4273$692_Y - connect \Y $and$ls180.v:4273$693_Y + connect \A $and$ls180.v:4142$592_Y + connect \B $not$ls180.v:4142$593_Y + connect \Y $and$ls180.v:4142$594_Y end - attribute \src "ls180.v:4274.34-4274.102" - cell $and $and$ls180.v:4274$695 + attribute \src "ls180.v:4143.34-4143.102" + cell $and $and$ls180.v:4143$596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4274$694_Y + connect \A $or$ls180.v:4143$595_Y connect \B \main_port_cmd_payload_we - connect \Y $and$ls180.v:4274$695_Y + connect \Y $and$ls180.v:4143$596_Y end - attribute \src "ls180.v:4274.33-4274.128" - cell $and $and$ls180.v:4274$697 + attribute \src "ls180.v:4143.33-4143.128" + cell $and $and$ls180.v:4143$598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4274$695_Y - connect \B $not$ls180.v:4274$696_Y - connect \Y $and$ls180.v:4274$697_Y + connect \A $and$ls180.v:4143$596_Y + connect \B $not$ls180.v:4143$597_Y + connect \Y $and$ls180.v:4143$598_Y end - attribute \src "ls180.v:4275.33-4275.104" - cell $and $and$ls180.v:4275$700 + attribute \src "ls180.v:4144.33-4144.104" + cell $and $and$ls180.v:4144$601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4275$698_Y - connect \B $not$ls180.v:4275$699_Y - connect \Y $and$ls180.v:4275$700_Y + connect \A $or$ls180.v:4144$599_Y + connect \B $not$ls180.v:4144$600_Y + connect \Y $and$ls180.v:4144$601_Y end - attribute \src "ls180.v:4276.49-4276.85" - cell $and $and$ls180.v:4276$701 + attribute \src "ls180.v:4145.49-4145.85" + cell $and $and$ls180.v:4145$602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258966,32 +257408,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we connect \B \main_ack_wdata - connect \Y $and$ls180.v:4276$701_Y + connect \Y $and$ls180.v:4145$602_Y end - attribute \src "ls180.v:4276.90-4276.129" - cell $and $and$ls180.v:4276$703 + attribute \src "ls180.v:4145.90-4145.129" + cell $and $and$ls180.v:4145$604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4276$702_Y + connect \A $not$ls180.v:4145$603_Y connect \B \main_ack_rdata - connect \Y $and$ls180.v:4276$703_Y + connect \Y $and$ls180.v:4145$604_Y end - attribute \src "ls180.v:4276.32-4276.131" - cell $and $and$ls180.v:4276$705 + attribute \src "ls180.v:4145.32-4145.131" + cell $and $and$ls180.v:4145$606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_ack_cmd - connect \B $or$ls180.v:4276$704_Y - connect \Y $and$ls180.v:4276$705_Y + connect \B $or$ls180.v:4145$605_Y + connect \Y $and$ls180.v:4145$606_Y end - attribute \src "ls180.v:4277.25-4277.66" - cell $and $and$ls180.v:4277$706 + attribute \src "ls180.v:4146.25-4146.66" + cell $and $and$ls180.v:4146$607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -258999,10 +257441,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:4277$706_Y + connect \Y $and$ls180.v:4146$607_Y end - attribute \src "ls180.v:4278.27-4278.72" - cell $and $and$ls180.v:4278$708 + attribute \src "ls180.v:4147.27-4147.72" + cell $and $and$ls180.v:4147$609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259010,10 +257452,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_wdata_valid connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:4278$708_Y + connect \Y $and$ls180.v:4147$609_Y end - attribute \src "ls180.v:4279.26-4279.71" - cell $and $and$ls180.v:4279$710 + attribute \src "ls180.v:4148.26-4148.71" + cell $and $and$ls180.v:4148$611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259021,10 +257463,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_rdata_valid connect \B \main_port_rdata_ready - connect \Y $and$ls180.v:4279$710_Y + connect \Y $and$ls180.v:4148$611_Y end - attribute \src "ls180.v:4308.64-4308.88" - cell $and $and$ls180.v:4308$716 + attribute \src "ls180.v:4177.64-4177.88" + cell $and $and$ls180.v:4177$617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259032,10 +257474,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A 1'0 connect \B \main_uart_rxtx_we - connect \Y $and$ls180.v:4308$716_Y + connect \Y $and$ls180.v:4177$617_Y end - attribute \src "ls180.v:4312.7-4312.78" - cell $and $and$ls180.v:4312$720 + attribute \src "ls180.v:4181.7-4181.78" + cell $and $and$ls180.v:4181$621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259043,10 +257485,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_re connect \B \main_uart_eventmanager_pending_r [0] - connect \Y $and$ls180.v:4312$720_Y + connect \Y $and$ls180.v:4181$621_Y end - attribute \src "ls180.v:4323.7-4323.78" - cell $and $and$ls180.v:4323$723 + attribute \src "ls180.v:4192.7-4192.78" + cell $and $and$ls180.v:4192$624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259054,10 +257496,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_re connect \B \main_uart_eventmanager_pending_r [1] - connect \Y $and$ls180.v:4323$723_Y + connect \Y $and$ls180.v:4192$624_Y end - attribute \src "ls180.v:4332.26-4332.97" - cell $and $and$ls180.v:4332$725 + attribute \src "ls180.v:4201.26-4201.97" + cell $and $and$ls180.v:4201$626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259065,10 +257507,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_w [0] connect \B \main_uart_eventmanager_storage [0] - connect \Y $and$ls180.v:4332$725_Y + connect \Y $and$ls180.v:4201$626_Y end - attribute \src "ls180.v:4332.102-4332.173" - cell $and $and$ls180.v:4332$726 + attribute \src "ls180.v:4201.102-4201.173" + cell $and $and$ls180.v:4201$627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259076,32 +257518,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_eventmanager_pending_w [1] connect \B \main_uart_eventmanager_storage [1] - connect \Y $and$ls180.v:4332$726_Y + connect \Y $and$ls180.v:4201$627_Y end - attribute \src "ls180.v:4347.41-4347.133" - cell $and $and$ls180.v:4347$730 + attribute \src "ls180.v:4216.41-4216.133" + cell $and $and$ls180.v:4216$631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_readable - connect \B $or$ls180.v:4347$729_Y - connect \Y $and$ls180.v:4347$730_Y + connect \B $or$ls180.v:4216$630_Y + connect \Y $and$ls180.v:4216$631_Y end - attribute \src "ls180.v:4358.39-4358.136" - cell $and $and$ls180.v:4358$735 + attribute \src "ls180.v:4227.39-4227.136" + cell $and $and$ls180.v:4227$636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we - connect \B $or$ls180.v:4358$734_Y - connect \Y $and$ls180.v:4358$735_Y + connect \B $or$ls180.v:4227$635_Y + connect \Y $and$ls180.v:4227$636_Y end - attribute \src "ls180.v:4359.37-4359.104" - cell $and $and$ls180.v:4359$736 + attribute \src "ls180.v:4228.37-4228.104" + cell $and $and$ls180.v:4228$637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259109,32 +257551,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_readable connect \B \main_uart_tx_fifo_syncfifo_re - connect \Y $and$ls180.v:4359$736_Y + connect \Y $and$ls180.v:4228$637_Y end - attribute \src "ls180.v:4377.41-4377.133" - cell $and $and$ls180.v:4377$741 + attribute \src "ls180.v:4246.41-4246.133" + cell $and $and$ls180.v:4246$642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_readable - connect \B $or$ls180.v:4377$740_Y - connect \Y $and$ls180.v:4377$741_Y + connect \B $or$ls180.v:4246$641_Y + connect \Y $and$ls180.v:4246$642_Y end - attribute \src "ls180.v:4388.39-4388.136" - cell $and $and$ls180.v:4388$746 + attribute \src "ls180.v:4257.39-4257.136" + cell $and $and$ls180.v:4257$647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we - connect \B $or$ls180.v:4388$745_Y - connect \Y $and$ls180.v:4388$746_Y + connect \B $or$ls180.v:4257$646_Y + connect \Y $and$ls180.v:4257$647_Y end - attribute \src "ls180.v:4389.37-4389.104" - cell $and $and$ls180.v:4389$747 + attribute \src "ls180.v:4258.37-4258.104" + cell $and $and$ls180.v:4258$648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259142,21 +257584,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_readable connect \B \main_uart_rx_fifo_syncfifo_re - connect \Y $and$ls180.v:4389$747_Y + connect \Y $and$ls180.v:4258$648_Y end - attribute \src "ls180.v:4588.33-4588.86" - cell $and $and$ls180.v:4588$791 + attribute \src "ls180.v:4457.33-4457.86" + cell $and $and$ls180.v:4457$692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk1 - connect \B $not$ls180.v:4588$790_Y - connect \Y $and$ls180.v:4588$791_Y + connect \B $not$ls180.v:4457$691_Y + connect \Y $and$ls180.v:4457$692_Y end - attribute \src "ls180.v:4692.9-4692.68" - cell $and $and$ls180.v:4692$800 + attribute \src "ls180.v:4561.9-4561.68" + cell $and $and$ls180.v:4561$701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259164,21 +257606,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_sink_valid connect \B \main_sdphy_cmdw_pads_out_ready - connect \Y $and$ls180.v:4692$800_Y + connect \Y $and$ls180.v:4561$701_Y end - attribute \src "ls180.v:4712.53-4712.145" - cell $and $and$ls180.v:4712$803 + attribute \src "ls180.v:4581.53-4581.145" + cell $and $and$ls180.v:4581$704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_pads_in_valid - connect \B $or$ls180.v:4712$802_Y - connect \Y $and$ls180.v:4712$803_Y + connect \B $or$ls180.v:4581$703_Y + connect \Y $and$ls180.v:4581$704_Y end - attribute \src "ls180.v:4731.52-4731.137" - cell $and $and$ls180.v:4731$806 + attribute \src "ls180.v:4600.52-4600.137" + cell $and $and$ls180.v:4600$707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259186,10 +257628,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:4731$806_Y + connect \Y $and$ls180.v:4600$707_Y end - attribute \src "ls180.v:4772.9-4772.68" - cell $and $and$ls180.v:4772$814 + attribute \src "ls180.v:4641.9-4641.68" + cell $and $and$ls180.v:4641$715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259197,10 +257639,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_valid connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4772$814_Y + connect \Y $and$ls180.v:4641$715_Y end - attribute \src "ls180.v:4810.9-4810.68" - cell $and $and$ls180.v:4810$820 + attribute \src "ls180.v:4679.9-4679.68" + cell $and $and$ls180.v:4679$721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259208,10 +257650,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_valid connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4810$820_Y + connect \Y $and$ls180.v:4679$721_Y end - attribute \src "ls180.v:4819.10-4819.69" - cell $and $and$ls180.v:4819$821 + attribute \src "ls180.v:4688.10-4688.69" + cell $and $and$ls180.v:4688$722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259219,21 +257661,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_sink_valid connect \B \main_sdphy_cmdr_pads_out_ready - connect \Y $and$ls180.v:4819$821_Y + connect \Y $and$ls180.v:4688$722_Y end - attribute \src "ls180.v:4819.9-4819.93" - cell $and $and$ls180.v:4819$822 + attribute \src "ls180.v:4688.9-4688.93" + cell $and $and$ls180.v:4688$723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4819$821_Y + connect \A $and$ls180.v:4688$722_Y connect \B \main_sdphy_cmdw_done - connect \Y $and$ls180.v:4819$822_Y + connect \Y $and$ls180.v:4688$723_Y end - attribute \src "ls180.v:4839.54-4839.117" - cell $and $and$ls180.v:4839$824 + attribute \src "ls180.v:4708.54-4708.117" + cell $and $and$ls180.v:4708$725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259241,10 +257683,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_pads_in_valid connect \B \main_sdphy_dataw_crcr_run - connect \Y $and$ls180.v:4839$824_Y + connect \Y $and$ls180.v:4708$725_Y end - attribute \src "ls180.v:4858.53-4858.140" - cell $and $and$ls180.v:4858$827 + attribute \src "ls180.v:4727.53-4727.140" + cell $and $and$ls180.v:4727$728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259252,10 +257694,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:4858$827_Y + connect \Y $and$ls180.v:4727$728_Y end - attribute \src "ls180.v:4955.9-4955.70" - cell $and $and$ls180.v:4955$837 + attribute \src "ls180.v:4824.9-4824.70" + cell $and $and$ls180.v:4824$738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259263,10 +257705,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid connect \B \main_sdphy_dataw_pads_out_ready - connect \Y $and$ls180.v:4955$837_Y + connect \Y $and$ls180.v:4824$738_Y end - attribute \src "ls180.v:4973.55-4973.120" - cell $and $and$ls180.v:4973$839 + attribute \src "ls180.v:4842.55-4842.120" + cell $and $and$ls180.v:4842$740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259274,10 +257716,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_pads_in_valid connect \B \main_sdphy_datar_datar_run - connect \Y $and$ls180.v:4973$839_Y + connect \Y $and$ls180.v:4842$740_Y end - attribute \src "ls180.v:4992.54-4992.143" - cell $and $and$ls180.v:4992$842 + attribute \src "ls180.v:4861.54-4861.143" + cell $and $and$ls180.v:4861$743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259285,10 +257727,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:4992$842_Y + connect \Y $and$ls180.v:4861$743_Y end - attribute \src "ls180.v:5074.9-5074.70" - cell $and $and$ls180.v:5074$857 + attribute \src "ls180.v:4943.9-4943.70" + cell $and $and$ls180.v:4943$758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259296,10 +257738,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_valid connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:5074$857_Y + connect \Y $and$ls180.v:4943$758_Y end - attribute \src "ls180.v:5081.9-5081.70" - cell $and $and$ls180.v:5081$858 + attribute \src "ls180.v:4950.9-4950.70" + cell $and $and$ls180.v:4950$759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259307,10 +257749,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_sink_valid connect \B \main_sdphy_datar_pads_out_ready - connect \Y $and$ls180.v:5081$858_Y + connect \Y $and$ls180.v:4950$759_Y end - attribute \src "ls180.v:5162.48-5162.124" - cell $and $and$ls180.v:5162$981 + attribute \src "ls180.v:5031.48-5031.124" + cell $and $and$ls180.v:5031$882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259318,21 +257760,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5162$981_Y + connect \Y $and$ls180.v:5031$882_Y end - attribute \src "ls180.v:5162.47-5162.165" - cell $and $and$ls180.v:5162$982 + attribute \src "ls180.v:5031.47-5031.165" + cell $and $and$ls180.v:5031$883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5162$981_Y + connect \A $and$ls180.v:5031$882_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5162$982_Y + connect \Y $and$ls180.v:5031$883_Y end - attribute \src "ls180.v:5163.50-5163.127" - cell $and $and$ls180.v:5163$983 + attribute \src "ls180.v:5032.50-5032.127" + cell $and $and$ls180.v:5032$884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259340,10 +257782,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5163$983_Y + connect \Y $and$ls180.v:5032$884_Y end - attribute \src "ls180.v:5165.48-5165.124" - cell $and $and$ls180.v:5165$984 + attribute \src "ls180.v:5034.48-5034.124" + cell $and $and$ls180.v:5034$885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259351,21 +257793,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5165$984_Y + connect \Y $and$ls180.v:5034$885_Y end - attribute \src "ls180.v:5165.47-5165.165" - cell $and $and$ls180.v:5165$985 + attribute \src "ls180.v:5034.47-5034.165" + cell $and $and$ls180.v:5034$886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5165$984_Y + connect \A $and$ls180.v:5034$885_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5165$985_Y + connect \Y $and$ls180.v:5034$886_Y end - attribute \src "ls180.v:5166.50-5166.127" - cell $and $and$ls180.v:5166$986 + attribute \src "ls180.v:5035.50-5035.127" + cell $and $and$ls180.v:5035$887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259373,10 +257815,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5166$986_Y + connect \Y $and$ls180.v:5035$887_Y end - attribute \src "ls180.v:5168.48-5168.124" - cell $and $and$ls180.v:5168$987 + attribute \src "ls180.v:5037.48-5037.124" + cell $and $and$ls180.v:5037$888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259384,21 +257826,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5168$987_Y + connect \Y $and$ls180.v:5037$888_Y end - attribute \src "ls180.v:5168.47-5168.165" - cell $and $and$ls180.v:5168$988 + attribute \src "ls180.v:5037.47-5037.165" + cell $and $and$ls180.v:5037$889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5168$987_Y + connect \A $and$ls180.v:5037$888_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5168$988_Y + connect \Y $and$ls180.v:5037$889_Y end - attribute \src "ls180.v:5169.50-5169.127" - cell $and $and$ls180.v:5169$989 + attribute \src "ls180.v:5038.50-5038.127" + cell $and $and$ls180.v:5038$890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259406,10 +257848,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5169$989_Y + connect \Y $and$ls180.v:5038$890_Y end - attribute \src "ls180.v:5171.48-5171.124" - cell $and $and$ls180.v:5171$990 + attribute \src "ls180.v:5040.48-5040.124" + cell $and $and$ls180.v:5040$891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259417,21 +257859,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_last connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5171$990_Y + connect \Y $and$ls180.v:5040$891_Y end - attribute \src "ls180.v:5171.47-5171.165" - cell $and $and$ls180.v:5171$991 + attribute \src "ls180.v:5040.47-5040.165" + cell $and $and$ls180.v:5040$892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5171$990_Y + connect \A $and$ls180.v:5040$891_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5171$991_Y + connect \Y $and$ls180.v:5040$892_Y end - attribute \src "ls180.v:5172.50-5172.127" - cell $and $and$ls180.v:5172$992 + attribute \src "ls180.v:5041.50-5041.127" + cell $and $and$ls180.v:5041$893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259439,10 +257881,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5172$992_Y + connect \Y $and$ls180.v:5041$893_Y end - attribute \src "ls180.v:5285.10-5285.86" - cell $and $and$ls180.v:5285$1041 + attribute \src "ls180.v:5154.10-5154.86" + cell $and $and$ls180.v:5154$942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259450,54 +257892,54 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_sink_valid connect \B \main_sdcore_crc16_inserter_sink_last - connect \Y $and$ls180.v:5285$1041_Y + connect \Y $and$ls180.v:5154$942_Y end - attribute \src "ls180.v:5285.9-5285.127" - cell $and $and$ls180.v:5285$1042 + attribute \src "ls180.v:5154.9-5154.127" + cell $and $and$ls180.v:5154$943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5285$1041_Y + connect \A $and$ls180.v:5154$942_Y connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5285$1042_Y + connect \Y $and$ls180.v:5154$943_Y end - attribute \src "ls180.v:5295.9-5295.152" - cell $and $and$ls180.v:5295$1046 + attribute \src "ls180.v:5164.9-5164.152" + cell $and $and$ls180.v:5164$947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:5295$1044_Y - connect \B $eq$ls180.v:5295$1045_Y - connect \Y $and$ls180.v:5295$1046_Y + connect \A $eq$ls180.v:5164$945_Y + connect \B $eq$ls180.v:5164$946_Y + connect \Y $and$ls180.v:5164$947_Y end - attribute \src "ls180.v:5295.8-5295.226" - cell $and $and$ls180.v:5295$1048 + attribute \src "ls180.v:5164.8-5164.226" + cell $and $and$ls180.v:5164$949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5295$1046_Y - connect \B $eq$ls180.v:5295$1047_Y - connect \Y $and$ls180.v:5295$1048_Y + connect \A $and$ls180.v:5164$947_Y + connect \B $eq$ls180.v:5164$948_Y + connect \Y $and$ls180.v:5164$949_Y end - attribute \src "ls180.v:5295.7-5295.300" - cell $and $and$ls180.v:5295$1050 + attribute \src "ls180.v:5164.7-5164.300" + cell $and $and$ls180.v:5164$951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5295$1048_Y - connect \B $eq$ls180.v:5295$1049_Y - connect \Y $and$ls180.v:5295$1050_Y + connect \A $and$ls180.v:5164$949_Y + connect \B $eq$ls180.v:5164$950_Y + connect \Y $and$ls180.v:5164$951_Y end - attribute \src "ls180.v:5300.49-5300.124" - cell $and $and$ls180.v:5300$1051 + attribute \src "ls180.v:5169.49-5169.124" + cell $and $and$ls180.v:5169$952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259505,10 +257947,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5300$1051_Y + connect \Y $and$ls180.v:5169$952_Y end - attribute \src "ls180.v:5310.49-5310.124" - cell $and $and$ls180.v:5310$1054 + attribute \src "ls180.v:5179.49-5179.124" + cell $and $and$ls180.v:5179$955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259516,10 +257958,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5310$1054_Y + connect \Y $and$ls180.v:5179$955_Y end - attribute \src "ls180.v:5320.49-5320.124" - cell $and $and$ls180.v:5320$1057 + attribute \src "ls180.v:5189.49-5189.124" + cell $and $and$ls180.v:5189$958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259527,10 +257969,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5320$1057_Y + connect \Y $and$ls180.v:5189$958_Y end - attribute \src "ls180.v:5330.49-5330.124" - cell $and $and$ls180.v:5330$1060 + attribute \src "ls180.v:5199.49-5199.124" + cell $and $and$ls180.v:5199$961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259538,21 +257980,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5330$1060_Y + connect \Y $and$ls180.v:5199$961_Y end - attribute \src "ls180.v:5342.7-5342.84" - cell $and $and$ls180.v:5342$1065 + attribute \src "ls180.v:5211.7-5211.84" + cell $and $and$ls180.v:5211$966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid - connect \B $gt$ls180.v:5342$1064_Y - connect \Y $and$ls180.v:5342$1065_Y + connect \B $gt$ls180.v:5211$965_Y + connect \Y $and$ls180.v:5211$966_Y end - attribute \src "ls180.v:5460.9-5460.64" - cell $and $and$ls180.v:5460$1114 + attribute \src "ls180.v:5329.9-5329.64" + cell $and $and$ls180.v:5329$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259560,10 +258002,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_sink_valid connect \B \main_sdphy_cmdw_sink_ready - connect \Y $and$ls180.v:5460$1114_Y + connect \Y $and$ls180.v:5329$1015_Y end - attribute \src "ls180.v:5512.10-5512.66" - cell $and $and$ls180.v:5512$1123 + attribute \src "ls180.v:5381.10-5381.66" + cell $and $and$ls180.v:5381$1024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259571,21 +258013,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid connect \B \main_sdphy_dataw_sink_last - connect \Y $and$ls180.v:5512$1123_Y + connect \Y $and$ls180.v:5381$1024_Y end - attribute \src "ls180.v:5512.9-5512.97" - cell $and $and$ls180.v:5512$1124 + attribute \src "ls180.v:5381.9-5381.97" + cell $and $and$ls180.v:5381$1025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5512$1123_Y + connect \A $and$ls180.v:5381$1024_Y connect \B \main_sdphy_dataw_sink_ready - connect \Y $and$ls180.v:5512$1124_Y + connect \Y $and$ls180.v:5381$1025_Y end - attribute \src "ls180.v:5538.11-5538.71" - cell $and $and$ls180.v:5538$1132 + attribute \src "ls180.v:5407.11-5407.71" + cell $and $and$ls180.v:5407$1033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259593,21 +258035,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_last connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:5538$1132_Y + connect \Y $and$ls180.v:5407$1033_Y end - attribute \src "ls180.v:5622.43-5622.152" - cell $and $and$ls180.v:5622$1140 + attribute \src "ls180.v:5491.43-5491.152" + cell $and $and$ls180.v:5491$1041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B $or$ls180.v:5622$1139_Y - connect \Y $and$ls180.v:5622$1140_Y + connect \B $or$ls180.v:5491$1040_Y + connect \Y $and$ls180.v:5491$1041_Y end - attribute \src "ls180.v:5623.41-5623.116" - cell $and $and$ls180.v:5623$1141 + attribute \src "ls180.v:5492.41-5492.116" + cell $and $and$ls180.v:5492$1042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259615,10 +258057,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_readable connect \B \main_sdblock2mem_fifo_syncfifo_re - connect \Y $and$ls180.v:5623$1141_Y + connect \Y $and$ls180.v:5492$1042_Y end - attribute \src "ls180.v:5635.48-5635.125" - cell $and $and$ls180.v:5635$1146 + attribute \src "ls180.v:5504.48-5504.125" + cell $and $and$ls180.v:5504$1047 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259626,10 +258068,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:5635$1146_Y + connect \Y $and$ls180.v:5504$1047_Y end - attribute \src "ls180.v:5662.9-5662.102" - cell $and $and$ls180.v:5662$1150 + attribute \src "ls180.v:5531.9-5531.102" + cell $and $and$ls180.v:5531$1051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259637,10 +258079,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready - connect \Y $and$ls180.v:5662$1150_Y + connect \Y $and$ls180.v:5531$1051_Y end - attribute \src "ls180.v:5735.9-5735.58" - cell $and $and$ls180.v:5735$1156 + attribute \src "ls180.v:5604.9-5604.58" + cell $and $and$ls180.v:5604$1057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259648,10 +258090,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_interface1_bus_stb connect \B \main_interface1_bus_ack - connect \Y $and$ls180.v:5735$1156_Y + connect \Y $and$ls180.v:5604$1057_Y end - attribute \src "ls180.v:5788.51-5788.123" - cell $and $and$ls180.v:5788$1164 + attribute \src "ls180.v:5657.51-5657.123" + cell $and $and$ls180.v:5657$1065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259659,10 +258101,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_sink_first connect \B \main_sdmem2block_converter_first - connect \Y $and$ls180.v:5788$1164_Y + connect \Y $and$ls180.v:5657$1065_Y end - attribute \src "ls180.v:5789.50-5789.120" - cell $and $and$ls180.v:5789$1165 + attribute \src "ls180.v:5658.50-5658.120" + cell $and $and$ls180.v:5658$1066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259670,10 +258112,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_sink_last connect \B \main_sdmem2block_converter_last - connect \Y $and$ls180.v:5789$1165_Y + connect \Y $and$ls180.v:5658$1066_Y end - attribute \src "ls180.v:5790.49-5790.122" - cell $and $and$ls180.v:5790$1166 + attribute \src "ls180.v:5659.49-5659.122" + cell $and $and$ls180.v:5659$1067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259681,21 +258123,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_last connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:5790$1166_Y + connect \Y $and$ls180.v:5659$1067_Y end - attribute \src "ls180.v:5842.43-5842.152" - cell $and $and$ls180.v:5842$1171 + attribute \src "ls180.v:5711.43-5711.152" + cell $and $and$ls180.v:5711$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B $or$ls180.v:5842$1170_Y - connect \Y $and$ls180.v:5842$1171_Y + connect \B $or$ls180.v:5711$1071_Y + connect \Y $and$ls180.v:5711$1072_Y end - attribute \src "ls180.v:5843.41-5843.116" - cell $and $and$ls180.v:5843$1172 + attribute \src "ls180.v:5712.41-5712.116" + cell $and $and$ls180.v:5712$1073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259703,10 +258145,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_readable connect \B \main_sdmem2block_fifo_syncfifo_re - connect \Y $and$ls180.v:5843$1172_Y + connect \Y $and$ls180.v:5712$1073_Y end - attribute \src "ls180.v:5875.9-5875.76" - cell $and $and$ls180.v:5875$1176 + attribute \src "ls180.v:5744.9-5744.76" + cell $and $and$ls180.v:5744$1077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259714,131 +258156,131 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_cyc connect \B \builder_libresocsim_wishbone_stb - connect \Y $and$ls180.v:5875$1176_Y + connect \Y $and$ls180.v:5744$1077_Y end - attribute \src "ls180.v:5878.44-5878.120" - cell $and $and$ls180.v:5878$1178 + attribute \src "ls180.v:5747.44-5747.120" + cell $and $and$ls180.v:5747$1079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_we - connect \B $ne$ls180.v:5878$1177_Y - connect \Y $and$ls180.v:5878$1178_Y + connect \B $ne$ls180.v:5747$1078_Y + connect \Y $and$ls180.v:5747$1079_Y end - attribute \src "ls180.v:5898.46-5898.90" - cell $and $and$ls180.v:5898$1180 + attribute \src "ls180.v:5767.46-5767.90" + cell $and $and$ls180.v:5767$1081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5898$1179_Y - connect \Y $and$ls180.v:5898$1180_Y + connect \B $eq$ls180.v:5767$1080_Y + connect \Y $and$ls180.v:5767$1081_Y end - attribute \src "ls180.v:5899.46-5899.90" - cell $and $and$ls180.v:5899$1182 + attribute \src "ls180.v:5768.46-5768.90" + cell $and $and$ls180.v:5768$1083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5899$1181_Y - connect \Y $and$ls180.v:5899$1182_Y + connect \B $eq$ls180.v:5768$1082_Y + connect \Y $and$ls180.v:5768$1083_Y end - attribute \src "ls180.v:5900.49-5900.93" - cell $and $and$ls180.v:5900$1184 + attribute \src "ls180.v:5769.49-5769.93" + cell $and $and$ls180.v:5769$1085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5900$1183_Y - connect \Y $and$ls180.v:5900$1184_Y + connect \B $eq$ls180.v:5769$1084_Y + connect \Y $and$ls180.v:5769$1085_Y end - attribute \src "ls180.v:5901.35-5901.79" - cell $and $and$ls180.v:5901$1186 + attribute \src "ls180.v:5770.35-5770.79" + cell $and $and$ls180.v:5770$1087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5901$1185_Y - connect \Y $and$ls180.v:5901$1186_Y + connect \B $eq$ls180.v:5770$1086_Y + connect \Y $and$ls180.v:5770$1087_Y end - attribute \src "ls180.v:5902.35-5902.79" - cell $and $and$ls180.v:5902$1188 + attribute \src "ls180.v:5771.35-5771.79" + cell $and $and$ls180.v:5771$1089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \B $eq$ls180.v:5902$1187_Y - connect \Y $and$ls180.v:5902$1188_Y + connect \B $eq$ls180.v:5771$1088_Y + connect \Y $and$ls180.v:5771$1089_Y end - attribute \src "ls180.v:5903.46-5903.90" - cell $and $and$ls180.v:5903$1190 + attribute \src "ls180.v:5772.46-5772.90" + cell $and $and$ls180.v:5772$1091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5903$1189_Y - connect \Y $and$ls180.v:5903$1190_Y + connect \B $eq$ls180.v:5772$1090_Y + connect \Y $and$ls180.v:5772$1091_Y end - attribute \src "ls180.v:5904.46-5904.90" - cell $and $and$ls180.v:5904$1192 + attribute \src "ls180.v:5773.46-5773.90" + cell $and $and$ls180.v:5773$1093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5904$1191_Y - connect \Y $and$ls180.v:5904$1192_Y + connect \B $eq$ls180.v:5773$1092_Y + connect \Y $and$ls180.v:5773$1093_Y end - attribute \src "ls180.v:5905.49-5905.93" - cell $and $and$ls180.v:5905$1194 + attribute \src "ls180.v:5774.49-5774.93" + cell $and $and$ls180.v:5774$1095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5905$1193_Y - connect \Y $and$ls180.v:5905$1194_Y + connect \B $eq$ls180.v:5774$1094_Y + connect \Y $and$ls180.v:5774$1095_Y end - attribute \src "ls180.v:5906.35-5906.79" - cell $and $and$ls180.v:5906$1196 + attribute \src "ls180.v:5775.35-5775.79" + cell $and $and$ls180.v:5775$1097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5906$1195_Y - connect \Y $and$ls180.v:5906$1196_Y + connect \B $eq$ls180.v:5775$1096_Y + connect \Y $and$ls180.v:5775$1097_Y end - attribute \src "ls180.v:5907.35-5907.79" - cell $and $and$ls180.v:5907$1198 + attribute \src "ls180.v:5776.35-5776.79" + cell $and $and$ls180.v:5776$1099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_err - connect \B $eq$ls180.v:5907$1197_Y - connect \Y $and$ls180.v:5907$1198_Y + connect \B $eq$ls180.v:5776$1098_Y + connect \Y $and$ls180.v:5776$1099_Y end - attribute \src "ls180.v:6016.40-6016.81" - cell $and $and$ls180.v:6016$1213 + attribute \src "ls180.v:5829.40-5829.81" + cell $and $and$ls180.v:5829$1107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259846,10 +258288,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [0] - connect \Y $and$ls180.v:6016$1213_Y + connect \Y $and$ls180.v:5829$1107_Y end - attribute \src "ls180.v:6017.39-6017.80" - cell $and $and$ls180.v:6017$1214 + attribute \src "ls180.v:5830.36-5830.77" + cell $and $and$ls180.v:5830$1108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259857,10 +258299,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [1] - connect \Y $and$ls180.v:6017$1214_Y + connect \Y $and$ls180.v:5830$1108_Y end - attribute \src "ls180.v:6018.39-6018.80" - cell $and $and$ls180.v:6018$1215 + attribute \src "ls180.v:5831.51-5831.92" + cell $and $and$ls180.v:5831$1109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259868,10 +258310,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [2] - connect \Y $and$ls180.v:6018$1215_Y + connect \Y $and$ls180.v:5831$1109_Y end - attribute \src "ls180.v:6019.39-6019.80" - cell $and $and$ls180.v:6019$1216 + attribute \src "ls180.v:5832.51-5832.92" + cell $and $and$ls180.v:5832$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259879,10 +258321,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [3] - connect \Y $and$ls180.v:6019$1216_Y + connect \Y $and$ls180.v:5832$1110_Y end - attribute \src "ls180.v:6020.39-6020.80" - cell $and $and$ls180.v:6020$1217 + attribute \src "ls180.v:5833.54-5833.95" + cell $and $and$ls180.v:5833$1111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259890,10 +258332,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [4] - connect \Y $and$ls180.v:6020$1217_Y + connect \Y $and$ls180.v:5833$1111_Y end - attribute \src "ls180.v:6021.51-6021.92" - cell $and $and$ls180.v:6021$1218 + attribute \src "ls180.v:5834.55-5834.96" + cell $and $and$ls180.v:5834$1112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259901,87 +258343,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_cyc connect \B \builder_slave_sel [5] - connect \Y $and$ls180.v:6021$1218_Y + connect \Y $and$ls180.v:5834$1112_Y end - attribute \src "ls180.v:6022.51-6022.92" - cell $and $and$ls180.v:6022$1219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [6] - connect \Y $and$ls180.v:6022$1219_Y - end - attribute \src "ls180.v:6023.52-6023.93" - cell $and $and$ls180.v:6023$1220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [7] - connect \Y $and$ls180.v:6023$1220_Y - end - attribute \src "ls180.v:6024.52-6024.93" - cell $and $and$ls180.v:6024$1221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [8] - connect \Y $and$ls180.v:6024$1221_Y - end - attribute \src "ls180.v:6025.52-6025.93" - cell $and $and$ls180.v:6025$1222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [9] - connect \Y $and$ls180.v:6025$1222_Y - end - attribute \src "ls180.v:6026.52-6026.94" - cell $and $and$ls180.v:6026$1223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [10] - connect \Y $and$ls180.v:6026$1223_Y - end - attribute \src "ls180.v:6027.54-6027.96" - cell $and $and$ls180.v:6027$1224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [11] - connect \Y $and$ls180.v:6027$1224_Y - end - attribute \src "ls180.v:6028.55-6028.97" - cell $and $and$ls180.v:6028$1225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [12] - connect \Y $and$ls180.v:6028$1225_Y - end - attribute \src "ls180.v:6030.25-6030.64" - cell $and $and$ls180.v:6030$1238 + attribute \src "ls180.v:5836.25-5836.64" + cell $and $and$ls180.v:5836$1118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -259989,21 +258354,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_stb connect \B \builder_shared_cyc - connect \Y $and$ls180.v:6030$1238_Y + connect \Y $and$ls180.v:5836$1118_Y end - attribute \src "ls180.v:6030.24-6030.89" - cell $and $and$ls180.v:6030$1240 + attribute \src "ls180.v:5836.24-5836.89" + cell $and $and$ls180.v:5836$1120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6030$1238_Y - connect \B $not$ls180.v:6030$1239_Y - connect \Y $and$ls180.v:6030$1240_Y + connect \A $and$ls180.v:5836$1118_Y + connect \B $not$ls180.v:5836$1119_Y + connect \Y $and$ls180.v:5836$1120_Y end - attribute \src "ls180.v:6036.39-6036.100" - cell $and $and$ls180.v:6036$1254 + attribute \src "ls180.v:5842.32-5842.93" + cell $and $and$ls180.v:5842$1127 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -260011,142 +258376,65 @@ module \ls180 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } connect \B \main_libresocsim_ram_bus_dat_r - connect \Y $and$ls180.v:6036$1254_Y + connect \Y $and$ls180.v:5842$1127_Y end - attribute \src "ls180.v:6036.105-6036.165" - cell $and $and$ls180.v:6036$1255 + attribute \src "ls180.v:5842.98-5842.155" + cell $and $and$ls180.v:5842$1128 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } - connect \B \main_interface0_ram_bus_dat_r - connect \Y $and$ls180.v:6036$1255_Y + connect \B \main_ram_bus_ram_bus_dat_r + connect \Y $and$ls180.v:5842$1128_Y end - attribute \src "ls180.v:6036.171-6036.231" - cell $and $and$ls180.v:6036$1257 + attribute \src "ls180.v:5842.161-5842.233" + cell $and $and$ls180.v:5842$1130 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } - connect \B \main_interface1_ram_bus_dat_r - connect \Y $and$ls180.v:6036$1257_Y - end - attribute \src "ls180.v:6036.237-6036.297" - cell $and $and$ls180.v:6036$1259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } - connect \B \main_interface2_ram_bus_dat_r - connect \Y $and$ls180.v:6036$1259_Y - end - attribute \src "ls180.v:6036.303-6036.363" - cell $and $and$ls180.v:6036$1261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } - connect \B \main_interface3_ram_bus_dat_r - connect \Y $and$ls180.v:6036$1261_Y - end - attribute \src "ls180.v:6036.369-6036.441" - cell $and $and$ls180.v:6036$1263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] } connect \B \main_interface0_converted_interface_dat_r - connect \Y $and$ls180.v:6036$1263_Y + connect \Y $and$ls180.v:5842$1130_Y end - attribute \src "ls180.v:6036.447-6036.519" - cell $and $and$ls180.v:6036$1265 + attribute \src "ls180.v:5842.239-5842.311" + cell $and $and$ls180.v:5842$1132 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] } + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } connect \B \main_interface1_converted_interface_dat_r - connect \Y $and$ls180.v:6036$1265_Y + connect \Y $and$ls180.v:5842$1132_Y end - attribute \src "ls180.v:6036.525-6036.598" - cell $and $and$ls180.v:6036$1267 + attribute \src "ls180.v:5842.317-5842.392" + cell $and $and$ls180.v:5842$1134 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] } - connect \B \main_libresocsim_libresoc_interface0_dat_r - connect \Y $and$ls180.v:6036$1267_Y - end - attribute \src "ls180.v:6036.604-6036.677" - cell $and $and$ls180.v:6036$1269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] } - connect \B \main_libresocsim_libresoc_interface1_dat_r - connect \Y $and$ls180.v:6036$1269_Y - end - attribute \src "ls180.v:6036.683-6036.756" - cell $and $and$ls180.v:6036$1271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] } - connect \B \main_libresocsim_libresoc_interface2_dat_r - connect \Y $and$ls180.v:6036$1271_Y - end - attribute \src "ls180.v:6036.762-6036.836" - cell $and $and$ls180.v:6036$1273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] } - connect \B \main_libresocsim_libresoc_interface3_dat_r - connect \Y $and$ls180.v:6036$1273_Y - end - attribute \src "ls180.v:6036.842-6036.918" - cell $and $and$ls180.v:6036$1275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] } + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } connect \B \main_socbushandler_converted_interface_dat_r - connect \Y $and$ls180.v:6036$1275_Y + connect \Y $and$ls180.v:5842$1134_Y end - attribute \src "ls180.v:6036.924-6036.1001" - cell $and $and$ls180.v:6036$1277 + attribute \src "ls180.v:5842.398-5842.474" + cell $and $and$ls180.v:5842$1136 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] } + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] } connect \B \builder_libresocsim_converted_interface_dat_r - connect \Y $and$ls180.v:6036$1277_Y + connect \Y $and$ls180.v:5842$1136_Y end - attribute \src "ls180.v:6046.39-6046.92" - cell $and $and$ls180.v:6046$1281 + attribute \src "ls180.v:5852.39-5852.92" + cell $and $and$ls180.v:5852$1140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260154,43 +258442,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6046$1281_Y + connect \Y $and$ls180.v:5852$1140_Y end - attribute \src "ls180.v:6046.38-6046.142" - cell $and $and$ls180.v:6046$1283 + attribute \src "ls180.v:5852.38-5852.142" + cell $and $and$ls180.v:5852$1142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6046$1281_Y - connect \B $eq$ls180.v:6046$1282_Y - connect \Y $and$ls180.v:6046$1283_Y + connect \A $and$ls180.v:5852$1140_Y + connect \B $eq$ls180.v:5852$1141_Y + connect \Y $and$ls180.v:5852$1142_Y end - attribute \src "ls180.v:6047.39-6047.95" - cell $and $and$ls180.v:6047$1285 + attribute \src "ls180.v:5853.39-5853.95" + cell $and $and$ls180.v:5853$1144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6047$1284_Y - connect \Y $and$ls180.v:6047$1285_Y + connect \B $not$ls180.v:5853$1143_Y + connect \Y $and$ls180.v:5853$1144_Y end - attribute \src "ls180.v:6047.38-6047.145" - cell $and $and$ls180.v:6047$1287 + attribute \src "ls180.v:5853.38-5853.145" + cell $and $and$ls180.v:5853$1146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6047$1285_Y - connect \B $eq$ls180.v:6047$1286_Y - connect \Y $and$ls180.v:6047$1287_Y + connect \A $and$ls180.v:5853$1144_Y + connect \B $eq$ls180.v:5853$1145_Y + connect \Y $and$ls180.v:5853$1146_Y end - attribute \src "ls180.v:6049.41-6049.94" - cell $and $and$ls180.v:6049$1288 + attribute \src "ls180.v:5855.41-5855.94" + cell $and $and$ls180.v:5855$1147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260198,43 +258486,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6049$1288_Y + connect \Y $and$ls180.v:5855$1147_Y end - attribute \src "ls180.v:6049.40-6049.144" - cell $and $and$ls180.v:6049$1290 + attribute \src "ls180.v:5855.40-5855.144" + cell $and $and$ls180.v:5855$1149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6049$1288_Y - connect \B $eq$ls180.v:6049$1289_Y - connect \Y $and$ls180.v:6049$1290_Y + connect \A $and$ls180.v:5855$1147_Y + connect \B $eq$ls180.v:5855$1148_Y + connect \Y $and$ls180.v:5855$1149_Y end - attribute \src "ls180.v:6050.41-6050.97" - cell $and $and$ls180.v:6050$1292 + attribute \src "ls180.v:5856.41-5856.97" + cell $and $and$ls180.v:5856$1151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6050$1291_Y - connect \Y $and$ls180.v:6050$1292_Y + connect \B $not$ls180.v:5856$1150_Y + connect \Y $and$ls180.v:5856$1151_Y end - attribute \src "ls180.v:6050.40-6050.147" - cell $and $and$ls180.v:6050$1294 + attribute \src "ls180.v:5856.40-5856.147" + cell $and $and$ls180.v:5856$1153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6050$1292_Y - connect \B $eq$ls180.v:6050$1293_Y - connect \Y $and$ls180.v:6050$1294_Y + connect \A $and$ls180.v:5856$1151_Y + connect \B $eq$ls180.v:5856$1152_Y + connect \Y $and$ls180.v:5856$1153_Y end - attribute \src "ls180.v:6052.41-6052.94" - cell $and $and$ls180.v:6052$1295 + attribute \src "ls180.v:5858.41-5858.94" + cell $and $and$ls180.v:5858$1154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260242,43 +258530,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6052$1295_Y + connect \Y $and$ls180.v:5858$1154_Y end - attribute \src "ls180.v:6052.40-6052.144" - cell $and $and$ls180.v:6052$1297 + attribute \src "ls180.v:5858.40-5858.144" + cell $and $and$ls180.v:5858$1156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6052$1295_Y - connect \B $eq$ls180.v:6052$1296_Y - connect \Y $and$ls180.v:6052$1297_Y + connect \A $and$ls180.v:5858$1154_Y + connect \B $eq$ls180.v:5858$1155_Y + connect \Y $and$ls180.v:5858$1156_Y end - attribute \src "ls180.v:6053.41-6053.97" - cell $and $and$ls180.v:6053$1299 + attribute \src "ls180.v:5859.41-5859.97" + cell $and $and$ls180.v:5859$1158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6053$1298_Y - connect \Y $and$ls180.v:6053$1299_Y + connect \B $not$ls180.v:5859$1157_Y + connect \Y $and$ls180.v:5859$1158_Y end - attribute \src "ls180.v:6053.40-6053.147" - cell $and $and$ls180.v:6053$1301 + attribute \src "ls180.v:5859.40-5859.147" + cell $and $and$ls180.v:5859$1160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6053$1299_Y - connect \B $eq$ls180.v:6053$1300_Y - connect \Y $and$ls180.v:6053$1301_Y + connect \A $and$ls180.v:5859$1158_Y + connect \B $eq$ls180.v:5859$1159_Y + connect \Y $and$ls180.v:5859$1160_Y end - attribute \src "ls180.v:6055.41-6055.94" - cell $and $and$ls180.v:6055$1302 + attribute \src "ls180.v:5861.41-5861.94" + cell $and $and$ls180.v:5861$1161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260286,43 +258574,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6055$1302_Y + connect \Y $and$ls180.v:5861$1161_Y end - attribute \src "ls180.v:6055.40-6055.144" - cell $and $and$ls180.v:6055$1304 + attribute \src "ls180.v:5861.40-5861.144" + cell $and $and$ls180.v:5861$1163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6055$1302_Y - connect \B $eq$ls180.v:6055$1303_Y - connect \Y $and$ls180.v:6055$1304_Y + connect \A $and$ls180.v:5861$1161_Y + connect \B $eq$ls180.v:5861$1162_Y + connect \Y $and$ls180.v:5861$1163_Y end - attribute \src "ls180.v:6056.41-6056.97" - cell $and $and$ls180.v:6056$1306 + attribute \src "ls180.v:5862.41-5862.97" + cell $and $and$ls180.v:5862$1165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6056$1305_Y - connect \Y $and$ls180.v:6056$1306_Y + connect \B $not$ls180.v:5862$1164_Y + connect \Y $and$ls180.v:5862$1165_Y end - attribute \src "ls180.v:6056.40-6056.147" - cell $and $and$ls180.v:6056$1308 + attribute \src "ls180.v:5862.40-5862.147" + cell $and $and$ls180.v:5862$1167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6056$1306_Y - connect \B $eq$ls180.v:6056$1307_Y - connect \Y $and$ls180.v:6056$1308_Y + connect \A $and$ls180.v:5862$1165_Y + connect \B $eq$ls180.v:5862$1166_Y + connect \Y $and$ls180.v:5862$1167_Y end - attribute \src "ls180.v:6058.41-6058.94" - cell $and $and$ls180.v:6058$1309 + attribute \src "ls180.v:5864.41-5864.94" + cell $and $and$ls180.v:5864$1168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260330,43 +258618,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6058$1309_Y + connect \Y $and$ls180.v:5864$1168_Y end - attribute \src "ls180.v:6058.40-6058.144" - cell $and $and$ls180.v:6058$1311 + attribute \src "ls180.v:5864.40-5864.144" + cell $and $and$ls180.v:5864$1170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6058$1309_Y - connect \B $eq$ls180.v:6058$1310_Y - connect \Y $and$ls180.v:6058$1311_Y + connect \A $and$ls180.v:5864$1168_Y + connect \B $eq$ls180.v:5864$1169_Y + connect \Y $and$ls180.v:5864$1170_Y end - attribute \src "ls180.v:6059.41-6059.97" - cell $and $and$ls180.v:6059$1313 + attribute \src "ls180.v:5865.41-5865.97" + cell $and $and$ls180.v:5865$1172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6059$1312_Y - connect \Y $and$ls180.v:6059$1313_Y + connect \B $not$ls180.v:5865$1171_Y + connect \Y $and$ls180.v:5865$1172_Y end - attribute \src "ls180.v:6059.40-6059.147" - cell $and $and$ls180.v:6059$1315 + attribute \src "ls180.v:5865.40-5865.147" + cell $and $and$ls180.v:5865$1174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6059$1313_Y - connect \B $eq$ls180.v:6059$1314_Y - connect \Y $and$ls180.v:6059$1315_Y + connect \A $and$ls180.v:5865$1172_Y + connect \B $eq$ls180.v:5865$1173_Y + connect \Y $and$ls180.v:5865$1174_Y end - attribute \src "ls180.v:6061.44-6061.97" - cell $and $and$ls180.v:6061$1316 + attribute \src "ls180.v:5867.44-5867.97" + cell $and $and$ls180.v:5867$1175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260374,43 +258662,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6061$1316_Y + connect \Y $and$ls180.v:5867$1175_Y end - attribute \src "ls180.v:6061.43-6061.147" - cell $and $and$ls180.v:6061$1318 + attribute \src "ls180.v:5867.43-5867.147" + cell $and $and$ls180.v:5867$1177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6061$1316_Y - connect \B $eq$ls180.v:6061$1317_Y - connect \Y $and$ls180.v:6061$1318_Y + connect \A $and$ls180.v:5867$1175_Y + connect \B $eq$ls180.v:5867$1176_Y + connect \Y $and$ls180.v:5867$1177_Y end - attribute \src "ls180.v:6062.44-6062.100" - cell $and $and$ls180.v:6062$1320 + attribute \src "ls180.v:5868.44-5868.100" + cell $and $and$ls180.v:5868$1179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6062$1319_Y - connect \Y $and$ls180.v:6062$1320_Y + connect \B $not$ls180.v:5868$1178_Y + connect \Y $and$ls180.v:5868$1179_Y end - attribute \src "ls180.v:6062.43-6062.150" - cell $and $and$ls180.v:6062$1322 + attribute \src "ls180.v:5868.43-5868.150" + cell $and $and$ls180.v:5868$1181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6062$1320_Y - connect \B $eq$ls180.v:6062$1321_Y - connect \Y $and$ls180.v:6062$1322_Y + connect \A $and$ls180.v:5868$1179_Y + connect \B $eq$ls180.v:5868$1180_Y + connect \Y $and$ls180.v:5868$1181_Y end - attribute \src "ls180.v:6064.44-6064.97" - cell $and $and$ls180.v:6064$1323 + attribute \src "ls180.v:5870.44-5870.97" + cell $and $and$ls180.v:5870$1182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260418,43 +258706,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6064$1323_Y + connect \Y $and$ls180.v:5870$1182_Y end - attribute \src "ls180.v:6064.43-6064.147" - cell $and $and$ls180.v:6064$1325 + attribute \src "ls180.v:5870.43-5870.147" + cell $and $and$ls180.v:5870$1184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6064$1323_Y - connect \B $eq$ls180.v:6064$1324_Y - connect \Y $and$ls180.v:6064$1325_Y + connect \A $and$ls180.v:5870$1182_Y + connect \B $eq$ls180.v:5870$1183_Y + connect \Y $and$ls180.v:5870$1184_Y end - attribute \src "ls180.v:6065.44-6065.100" - cell $and $and$ls180.v:6065$1327 + attribute \src "ls180.v:5871.44-5871.100" + cell $and $and$ls180.v:5871$1186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6065$1326_Y - connect \Y $and$ls180.v:6065$1327_Y + connect \B $not$ls180.v:5871$1185_Y + connect \Y $and$ls180.v:5871$1186_Y end - attribute \src "ls180.v:6065.43-6065.150" - cell $and $and$ls180.v:6065$1329 + attribute \src "ls180.v:5871.43-5871.150" + cell $and $and$ls180.v:5871$1188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6065$1327_Y - connect \B $eq$ls180.v:6065$1328_Y - connect \Y $and$ls180.v:6065$1329_Y + connect \A $and$ls180.v:5871$1186_Y + connect \B $eq$ls180.v:5871$1187_Y + connect \Y $and$ls180.v:5871$1188_Y end - attribute \src "ls180.v:6067.44-6067.97" - cell $and $and$ls180.v:6067$1330 + attribute \src "ls180.v:5873.44-5873.97" + cell $and $and$ls180.v:5873$1189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260462,43 +258750,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6067$1330_Y + connect \Y $and$ls180.v:5873$1189_Y end - attribute \src "ls180.v:6067.43-6067.147" - cell $and $and$ls180.v:6067$1332 + attribute \src "ls180.v:5873.43-5873.147" + cell $and $and$ls180.v:5873$1191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6067$1330_Y - connect \B $eq$ls180.v:6067$1331_Y - connect \Y $and$ls180.v:6067$1332_Y + connect \A $and$ls180.v:5873$1189_Y + connect \B $eq$ls180.v:5873$1190_Y + connect \Y $and$ls180.v:5873$1191_Y end - attribute \src "ls180.v:6068.44-6068.100" - cell $and $and$ls180.v:6068$1334 + attribute \src "ls180.v:5874.44-5874.100" + cell $and $and$ls180.v:5874$1193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6068$1333_Y - connect \Y $and$ls180.v:6068$1334_Y + connect \B $not$ls180.v:5874$1192_Y + connect \Y $and$ls180.v:5874$1193_Y end - attribute \src "ls180.v:6068.43-6068.150" - cell $and $and$ls180.v:6068$1336 + attribute \src "ls180.v:5874.43-5874.150" + cell $and $and$ls180.v:5874$1195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6068$1334_Y - connect \B $eq$ls180.v:6068$1335_Y - connect \Y $and$ls180.v:6068$1336_Y + connect \A $and$ls180.v:5874$1193_Y + connect \B $eq$ls180.v:5874$1194_Y + connect \Y $and$ls180.v:5874$1195_Y end - attribute \src "ls180.v:6070.44-6070.97" - cell $and $and$ls180.v:6070$1337 + attribute \src "ls180.v:5876.44-5876.97" + cell $and $and$ls180.v:5876$1196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260506,43 +258794,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:6070$1337_Y + connect \Y $and$ls180.v:5876$1196_Y end - attribute \src "ls180.v:6070.43-6070.147" - cell $and $and$ls180.v:6070$1339 + attribute \src "ls180.v:5876.43-5876.147" + cell $and $and$ls180.v:5876$1198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6070$1337_Y - connect \B $eq$ls180.v:6070$1338_Y - connect \Y $and$ls180.v:6070$1339_Y + connect \A $and$ls180.v:5876$1196_Y + connect \B $eq$ls180.v:5876$1197_Y + connect \Y $and$ls180.v:5876$1198_Y end - attribute \src "ls180.v:6071.44-6071.100" - cell $and $and$ls180.v:6071$1341 + attribute \src "ls180.v:5877.44-5877.100" + cell $and $and$ls180.v:5877$1200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:6071$1340_Y - connect \Y $and$ls180.v:6071$1341_Y + connect \B $not$ls180.v:5877$1199_Y + connect \Y $and$ls180.v:5877$1200_Y end - attribute \src "ls180.v:6071.43-6071.150" - cell $and $and$ls180.v:6071$1343 + attribute \src "ls180.v:5877.43-5877.150" + cell $and $and$ls180.v:5877$1202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6071$1341_Y - connect \B $eq$ls180.v:6071$1342_Y - connect \Y $and$ls180.v:6071$1343_Y + connect \A $and$ls180.v:5877$1200_Y + connect \B $eq$ls180.v:5877$1201_Y + connect \Y $and$ls180.v:5877$1202_Y end - attribute \src "ls180.v:6084.36-6084.89" - cell $and $and$ls180.v:6084$1345 + attribute \src "ls180.v:5890.36-5890.89" + cell $and $and$ls180.v:5890$1204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260550,43 +258838,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6084$1345_Y + connect \Y $and$ls180.v:5890$1204_Y end - attribute \src "ls180.v:6084.35-6084.139" - cell $and $and$ls180.v:6084$1347 + attribute \src "ls180.v:5890.35-5890.139" + cell $and $and$ls180.v:5890$1206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6084$1345_Y - connect \B $eq$ls180.v:6084$1346_Y - connect \Y $and$ls180.v:6084$1347_Y + connect \A $and$ls180.v:5890$1204_Y + connect \B $eq$ls180.v:5890$1205_Y + connect \Y $and$ls180.v:5890$1206_Y end - attribute \src "ls180.v:6085.36-6085.92" - cell $and $and$ls180.v:6085$1349 + attribute \src "ls180.v:5891.36-5891.92" + cell $and $and$ls180.v:5891$1208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6085$1348_Y - connect \Y $and$ls180.v:6085$1349_Y + connect \B $not$ls180.v:5891$1207_Y + connect \Y $and$ls180.v:5891$1208_Y end - attribute \src "ls180.v:6085.35-6085.142" - cell $and $and$ls180.v:6085$1351 + attribute \src "ls180.v:5891.35-5891.142" + cell $and $and$ls180.v:5891$1210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6085$1349_Y - connect \B $eq$ls180.v:6085$1350_Y - connect \Y $and$ls180.v:6085$1351_Y + connect \A $and$ls180.v:5891$1208_Y + connect \B $eq$ls180.v:5891$1209_Y + connect \Y $and$ls180.v:5891$1210_Y end - attribute \src "ls180.v:6087.36-6087.89" - cell $and $and$ls180.v:6087$1352 + attribute \src "ls180.v:5893.36-5893.89" + cell $and $and$ls180.v:5893$1211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260594,43 +258882,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6087$1352_Y + connect \Y $and$ls180.v:5893$1211_Y end - attribute \src "ls180.v:6087.35-6087.139" - cell $and $and$ls180.v:6087$1354 + attribute \src "ls180.v:5893.35-5893.139" + cell $and $and$ls180.v:5893$1213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6087$1352_Y - connect \B $eq$ls180.v:6087$1353_Y - connect \Y $and$ls180.v:6087$1354_Y + connect \A $and$ls180.v:5893$1211_Y + connect \B $eq$ls180.v:5893$1212_Y + connect \Y $and$ls180.v:5893$1213_Y end - attribute \src "ls180.v:6088.36-6088.92" - cell $and $and$ls180.v:6088$1356 + attribute \src "ls180.v:5894.36-5894.92" + cell $and $and$ls180.v:5894$1215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6088$1355_Y - connect \Y $and$ls180.v:6088$1356_Y + connect \B $not$ls180.v:5894$1214_Y + connect \Y $and$ls180.v:5894$1215_Y end - attribute \src "ls180.v:6088.35-6088.142" - cell $and $and$ls180.v:6088$1358 + attribute \src "ls180.v:5894.35-5894.142" + cell $and $and$ls180.v:5894$1217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6088$1356_Y - connect \B $eq$ls180.v:6088$1357_Y - connect \Y $and$ls180.v:6088$1358_Y + connect \A $and$ls180.v:5894$1215_Y + connect \B $eq$ls180.v:5894$1216_Y + connect \Y $and$ls180.v:5894$1217_Y end - attribute \src "ls180.v:6090.36-6090.89" - cell $and $and$ls180.v:6090$1359 + attribute \src "ls180.v:5896.36-5896.89" + cell $and $and$ls180.v:5896$1218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260638,43 +258926,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6090$1359_Y + connect \Y $and$ls180.v:5896$1218_Y end - attribute \src "ls180.v:6090.35-6090.139" - cell $and $and$ls180.v:6090$1361 + attribute \src "ls180.v:5896.35-5896.139" + cell $and $and$ls180.v:5896$1220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6090$1359_Y - connect \B $eq$ls180.v:6090$1360_Y - connect \Y $and$ls180.v:6090$1361_Y + connect \A $and$ls180.v:5896$1218_Y + connect \B $eq$ls180.v:5896$1219_Y + connect \Y $and$ls180.v:5896$1220_Y end - attribute \src "ls180.v:6091.36-6091.92" - cell $and $and$ls180.v:6091$1363 + attribute \src "ls180.v:5897.36-5897.92" + cell $and $and$ls180.v:5897$1222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6091$1362_Y - connect \Y $and$ls180.v:6091$1363_Y + connect \B $not$ls180.v:5897$1221_Y + connect \Y $and$ls180.v:5897$1222_Y end - attribute \src "ls180.v:6091.35-6091.142" - cell $and $and$ls180.v:6091$1365 + attribute \src "ls180.v:5897.35-5897.142" + cell $and $and$ls180.v:5897$1224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6091$1363_Y - connect \B $eq$ls180.v:6091$1364_Y - connect \Y $and$ls180.v:6091$1365_Y + connect \A $and$ls180.v:5897$1222_Y + connect \B $eq$ls180.v:5897$1223_Y + connect \Y $and$ls180.v:5897$1224_Y end - attribute \src "ls180.v:6093.36-6093.89" - cell $and $and$ls180.v:6093$1366 + attribute \src "ls180.v:5899.36-5899.89" + cell $and $and$ls180.v:5899$1225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260682,43 +258970,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6093$1366_Y + connect \Y $and$ls180.v:5899$1225_Y end - attribute \src "ls180.v:6093.35-6093.139" - cell $and $and$ls180.v:6093$1368 + attribute \src "ls180.v:5899.35-5899.139" + cell $and $and$ls180.v:5899$1227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6093$1366_Y - connect \B $eq$ls180.v:6093$1367_Y - connect \Y $and$ls180.v:6093$1368_Y + connect \A $and$ls180.v:5899$1225_Y + connect \B $eq$ls180.v:5899$1226_Y + connect \Y $and$ls180.v:5899$1227_Y end - attribute \src "ls180.v:6094.36-6094.92" - cell $and $and$ls180.v:6094$1370 + attribute \src "ls180.v:5900.36-5900.92" + cell $and $and$ls180.v:5900$1229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6094$1369_Y - connect \Y $and$ls180.v:6094$1370_Y + connect \B $not$ls180.v:5900$1228_Y + connect \Y $and$ls180.v:5900$1229_Y end - attribute \src "ls180.v:6094.35-6094.142" - cell $and $and$ls180.v:6094$1372 + attribute \src "ls180.v:5900.35-5900.142" + cell $and $and$ls180.v:5900$1231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6094$1370_Y - connect \B $eq$ls180.v:6094$1371_Y - connect \Y $and$ls180.v:6094$1372_Y + connect \A $and$ls180.v:5900$1229_Y + connect \B $eq$ls180.v:5900$1230_Y + connect \Y $and$ls180.v:5900$1231_Y end - attribute \src "ls180.v:6096.37-6096.90" - cell $and $and$ls180.v:6096$1373 + attribute \src "ls180.v:5902.37-5902.90" + cell $and $and$ls180.v:5902$1232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260726,43 +259014,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6096$1373_Y + connect \Y $and$ls180.v:5902$1232_Y end - attribute \src "ls180.v:6096.36-6096.140" - cell $and $and$ls180.v:6096$1375 + attribute \src "ls180.v:5902.36-5902.140" + cell $and $and$ls180.v:5902$1234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6096$1373_Y - connect \B $eq$ls180.v:6096$1374_Y - connect \Y $and$ls180.v:6096$1375_Y + connect \A $and$ls180.v:5902$1232_Y + connect \B $eq$ls180.v:5902$1233_Y + connect \Y $and$ls180.v:5902$1234_Y end - attribute \src "ls180.v:6097.37-6097.93" - cell $and $and$ls180.v:6097$1377 + attribute \src "ls180.v:5903.37-5903.93" + cell $and $and$ls180.v:5903$1236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6097$1376_Y - connect \Y $and$ls180.v:6097$1377_Y + connect \B $not$ls180.v:5903$1235_Y + connect \Y $and$ls180.v:5903$1236_Y end - attribute \src "ls180.v:6097.36-6097.143" - cell $and $and$ls180.v:6097$1379 + attribute \src "ls180.v:5903.36-5903.143" + cell $and $and$ls180.v:5903$1238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6097$1377_Y - connect \B $eq$ls180.v:6097$1378_Y - connect \Y $and$ls180.v:6097$1379_Y + connect \A $and$ls180.v:5903$1236_Y + connect \B $eq$ls180.v:5903$1237_Y + connect \Y $and$ls180.v:5903$1238_Y end - attribute \src "ls180.v:6099.37-6099.90" - cell $and $and$ls180.v:6099$1380 + attribute \src "ls180.v:5905.37-5905.90" + cell $and $and$ls180.v:5905$1239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260770,43 +259058,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:6099$1380_Y + connect \Y $and$ls180.v:5905$1239_Y end - attribute \src "ls180.v:6099.36-6099.140" - cell $and $and$ls180.v:6099$1382 + attribute \src "ls180.v:5905.36-5905.140" + cell $and $and$ls180.v:5905$1241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6099$1380_Y - connect \B $eq$ls180.v:6099$1381_Y - connect \Y $and$ls180.v:6099$1382_Y + connect \A $and$ls180.v:5905$1239_Y + connect \B $eq$ls180.v:5905$1240_Y + connect \Y $and$ls180.v:5905$1241_Y end - attribute \src "ls180.v:6100.37-6100.93" - cell $and $and$ls180.v:6100$1384 + attribute \src "ls180.v:5906.37-5906.93" + cell $and $and$ls180.v:5906$1243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:6100$1383_Y - connect \Y $and$ls180.v:6100$1384_Y + connect \B $not$ls180.v:5906$1242_Y + connect \Y $and$ls180.v:5906$1243_Y end - attribute \src "ls180.v:6100.36-6100.143" - cell $and $and$ls180.v:6100$1386 + attribute \src "ls180.v:5906.36-5906.143" + cell $and $and$ls180.v:5906$1245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6100$1384_Y - connect \B $eq$ls180.v:6100$1385_Y - connect \Y $and$ls180.v:6100$1386_Y + connect \A $and$ls180.v:5906$1243_Y + connect \B $eq$ls180.v:5906$1244_Y + connect \Y $and$ls180.v:5906$1245_Y end - attribute \src "ls180.v:6110.35-6110.88" - cell $and $and$ls180.v:6110$1388 + attribute \src "ls180.v:5916.35-5916.88" + cell $and $and$ls180.v:5916$1247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260814,43 +259102,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:6110$1388_Y + connect \Y $and$ls180.v:5916$1247_Y end - attribute \src "ls180.v:6110.34-6110.136" - cell $and $and$ls180.v:6110$1390 + attribute \src "ls180.v:5916.34-5916.136" + cell $and $and$ls180.v:5916$1249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6110$1388_Y - connect \B $eq$ls180.v:6110$1389_Y - connect \Y $and$ls180.v:6110$1390_Y + connect \A $and$ls180.v:5916$1247_Y + connect \B $eq$ls180.v:5916$1248_Y + connect \Y $and$ls180.v:5916$1249_Y end - attribute \src "ls180.v:6111.35-6111.91" - cell $and $and$ls180.v:6111$1392 + attribute \src "ls180.v:5917.35-5917.91" + cell $and $and$ls180.v:5917$1251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:6111$1391_Y - connect \Y $and$ls180.v:6111$1392_Y + connect \B $not$ls180.v:5917$1250_Y + connect \Y $and$ls180.v:5917$1251_Y end - attribute \src "ls180.v:6111.34-6111.139" - cell $and $and$ls180.v:6111$1394 + attribute \src "ls180.v:5917.34-5917.139" + cell $and $and$ls180.v:5917$1253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6111$1392_Y - connect \B $eq$ls180.v:6111$1393_Y - connect \Y $and$ls180.v:6111$1394_Y + connect \A $and$ls180.v:5917$1251_Y + connect \B $eq$ls180.v:5917$1252_Y + connect \Y $and$ls180.v:5917$1253_Y end - attribute \src "ls180.v:6113.34-6113.87" - cell $and $and$ls180.v:6113$1395 + attribute \src "ls180.v:5919.34-5919.87" + cell $and $and$ls180.v:5919$1254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260858,43 +259146,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:6113$1395_Y + connect \Y $and$ls180.v:5919$1254_Y end - attribute \src "ls180.v:6113.33-6113.135" - cell $and $and$ls180.v:6113$1397 + attribute \src "ls180.v:5919.33-5919.135" + cell $and $and$ls180.v:5919$1256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6113$1395_Y - connect \B $eq$ls180.v:6113$1396_Y - connect \Y $and$ls180.v:6113$1397_Y + connect \A $and$ls180.v:5919$1254_Y + connect \B $eq$ls180.v:5919$1255_Y + connect \Y $and$ls180.v:5919$1256_Y end - attribute \src "ls180.v:6114.34-6114.90" - cell $and $and$ls180.v:6114$1399 + attribute \src "ls180.v:5920.34-5920.90" + cell $and $and$ls180.v:5920$1258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:6114$1398_Y - connect \Y $and$ls180.v:6114$1399_Y + connect \B $not$ls180.v:5920$1257_Y + connect \Y $and$ls180.v:5920$1258_Y end - attribute \src "ls180.v:6114.33-6114.138" - cell $and $and$ls180.v:6114$1401 + attribute \src "ls180.v:5920.33-5920.138" + cell $and $and$ls180.v:5920$1260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6114$1399_Y - connect \B $eq$ls180.v:6114$1400_Y - connect \Y $and$ls180.v:6114$1401_Y + connect \A $and$ls180.v:5920$1258_Y + connect \B $eq$ls180.v:5920$1259_Y + connect \Y $and$ls180.v:5920$1260_Y end - attribute \src "ls180.v:6124.40-6124.93" - cell $and $and$ls180.v:6124$1403 + attribute \src "ls180.v:5930.40-5930.93" + cell $and $and$ls180.v:5930$1262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260902,43 +259190,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6124$1403_Y + connect \Y $and$ls180.v:5930$1262_Y end - attribute \src "ls180.v:6124.39-6124.143" - cell $and $and$ls180.v:6124$1405 + attribute \src "ls180.v:5930.39-5930.143" + cell $and $and$ls180.v:5930$1264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6124$1403_Y - connect \B $eq$ls180.v:6124$1404_Y - connect \Y $and$ls180.v:6124$1405_Y + connect \A $and$ls180.v:5930$1262_Y + connect \B $eq$ls180.v:5930$1263_Y + connect \Y $and$ls180.v:5930$1264_Y end - attribute \src "ls180.v:6125.40-6125.96" - cell $and $and$ls180.v:6125$1407 + attribute \src "ls180.v:5931.40-5931.96" + cell $and $and$ls180.v:5931$1266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6125$1406_Y - connect \Y $and$ls180.v:6125$1407_Y + connect \B $not$ls180.v:5931$1265_Y + connect \Y $and$ls180.v:5931$1266_Y end - attribute \src "ls180.v:6125.39-6125.146" - cell $and $and$ls180.v:6125$1409 + attribute \src "ls180.v:5931.39-5931.146" + cell $and $and$ls180.v:5931$1268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6125$1407_Y - connect \B $eq$ls180.v:6125$1408_Y - connect \Y $and$ls180.v:6125$1409_Y + connect \A $and$ls180.v:5931$1266_Y + connect \B $eq$ls180.v:5931$1267_Y + connect \Y $and$ls180.v:5931$1268_Y end - attribute \src "ls180.v:6127.39-6127.92" - cell $and $and$ls180.v:6127$1410 + attribute \src "ls180.v:5933.39-5933.92" + cell $and $and$ls180.v:5933$1269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260946,43 +259234,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6127$1410_Y + connect \Y $and$ls180.v:5933$1269_Y end - attribute \src "ls180.v:6127.38-6127.142" - cell $and $and$ls180.v:6127$1412 + attribute \src "ls180.v:5933.38-5933.142" + cell $and $and$ls180.v:5933$1271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6127$1410_Y - connect \B $eq$ls180.v:6127$1411_Y - connect \Y $and$ls180.v:6127$1412_Y + connect \A $and$ls180.v:5933$1269_Y + connect \B $eq$ls180.v:5933$1270_Y + connect \Y $and$ls180.v:5933$1271_Y end - attribute \src "ls180.v:6128.39-6128.95" - cell $and $and$ls180.v:6128$1414 + attribute \src "ls180.v:5934.39-5934.95" + cell $and $and$ls180.v:5934$1273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6128$1413_Y - connect \Y $and$ls180.v:6128$1414_Y + connect \B $not$ls180.v:5934$1272_Y + connect \Y $and$ls180.v:5934$1273_Y end - attribute \src "ls180.v:6128.38-6128.145" - cell $and $and$ls180.v:6128$1416 + attribute \src "ls180.v:5934.38-5934.145" + cell $and $and$ls180.v:5934$1275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6128$1414_Y - connect \B $eq$ls180.v:6128$1415_Y - connect \Y $and$ls180.v:6128$1416_Y + connect \A $and$ls180.v:5934$1273_Y + connect \B $eq$ls180.v:5934$1274_Y + connect \Y $and$ls180.v:5934$1275_Y end - attribute \src "ls180.v:6130.39-6130.92" - cell $and $and$ls180.v:6130$1417 + attribute \src "ls180.v:5936.39-5936.92" + cell $and $and$ls180.v:5936$1276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -260990,43 +259278,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6130$1417_Y + connect \Y $and$ls180.v:5936$1276_Y end - attribute \src "ls180.v:6130.38-6130.142" - cell $and $and$ls180.v:6130$1419 + attribute \src "ls180.v:5936.38-5936.142" + cell $and $and$ls180.v:5936$1278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6130$1417_Y - connect \B $eq$ls180.v:6130$1418_Y - connect \Y $and$ls180.v:6130$1419_Y + connect \A $and$ls180.v:5936$1276_Y + connect \B $eq$ls180.v:5936$1277_Y + connect \Y $and$ls180.v:5936$1278_Y end - attribute \src "ls180.v:6131.39-6131.95" - cell $and $and$ls180.v:6131$1421 + attribute \src "ls180.v:5937.39-5937.95" + cell $and $and$ls180.v:5937$1280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6131$1420_Y - connect \Y $and$ls180.v:6131$1421_Y + connect \B $not$ls180.v:5937$1279_Y + connect \Y $and$ls180.v:5937$1280_Y end - attribute \src "ls180.v:6131.38-6131.145" - cell $and $and$ls180.v:6131$1423 + attribute \src "ls180.v:5937.38-5937.145" + cell $and $and$ls180.v:5937$1282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6131$1421_Y - connect \B $eq$ls180.v:6131$1422_Y - connect \Y $and$ls180.v:6131$1423_Y + connect \A $and$ls180.v:5937$1280_Y + connect \B $eq$ls180.v:5937$1281_Y + connect \Y $and$ls180.v:5937$1282_Y end - attribute \src "ls180.v:6133.39-6133.92" - cell $and $and$ls180.v:6133$1424 + attribute \src "ls180.v:5939.39-5939.92" + cell $and $and$ls180.v:5939$1283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261034,43 +259322,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6133$1424_Y + connect \Y $and$ls180.v:5939$1283_Y end - attribute \src "ls180.v:6133.38-6133.142" - cell $and $and$ls180.v:6133$1426 + attribute \src "ls180.v:5939.38-5939.142" + cell $and $and$ls180.v:5939$1285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6133$1424_Y - connect \B $eq$ls180.v:6133$1425_Y - connect \Y $and$ls180.v:6133$1426_Y + connect \A $and$ls180.v:5939$1283_Y + connect \B $eq$ls180.v:5939$1284_Y + connect \Y $and$ls180.v:5939$1285_Y end - attribute \src "ls180.v:6134.39-6134.95" - cell $and $and$ls180.v:6134$1428 + attribute \src "ls180.v:5940.39-5940.95" + cell $and $and$ls180.v:5940$1287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6134$1427_Y - connect \Y $and$ls180.v:6134$1428_Y + connect \B $not$ls180.v:5940$1286_Y + connect \Y $and$ls180.v:5940$1287_Y end - attribute \src "ls180.v:6134.38-6134.145" - cell $and $and$ls180.v:6134$1430 + attribute \src "ls180.v:5940.38-5940.145" + cell $and $and$ls180.v:5940$1289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6134$1428_Y - connect \B $eq$ls180.v:6134$1429_Y - connect \Y $and$ls180.v:6134$1430_Y + connect \A $and$ls180.v:5940$1287_Y + connect \B $eq$ls180.v:5940$1288_Y + connect \Y $and$ls180.v:5940$1289_Y end - attribute \src "ls180.v:6136.39-6136.92" - cell $and $and$ls180.v:6136$1431 + attribute \src "ls180.v:5942.39-5942.92" + cell $and $and$ls180.v:5942$1290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261078,43 +259366,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6136$1431_Y + connect \Y $and$ls180.v:5942$1290_Y end - attribute \src "ls180.v:6136.38-6136.142" - cell $and $and$ls180.v:6136$1433 + attribute \src "ls180.v:5942.38-5942.142" + cell $and $and$ls180.v:5942$1292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6136$1431_Y - connect \B $eq$ls180.v:6136$1432_Y - connect \Y $and$ls180.v:6136$1433_Y + connect \A $and$ls180.v:5942$1290_Y + connect \B $eq$ls180.v:5942$1291_Y + connect \Y $and$ls180.v:5942$1292_Y end - attribute \src "ls180.v:6137.39-6137.95" - cell $and $and$ls180.v:6137$1435 + attribute \src "ls180.v:5943.39-5943.95" + cell $and $and$ls180.v:5943$1294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6137$1434_Y - connect \Y $and$ls180.v:6137$1435_Y + connect \B $not$ls180.v:5943$1293_Y + connect \Y $and$ls180.v:5943$1294_Y end - attribute \src "ls180.v:6137.38-6137.145" - cell $and $and$ls180.v:6137$1437 + attribute \src "ls180.v:5943.38-5943.145" + cell $and $and$ls180.v:5943$1296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6137$1435_Y - connect \B $eq$ls180.v:6137$1436_Y - connect \Y $and$ls180.v:6137$1437_Y + connect \A $and$ls180.v:5943$1294_Y + connect \B $eq$ls180.v:5943$1295_Y + connect \Y $and$ls180.v:5943$1296_Y end - attribute \src "ls180.v:6139.40-6139.93" - cell $and $and$ls180.v:6139$1438 + attribute \src "ls180.v:5945.40-5945.93" + cell $and $and$ls180.v:5945$1297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261122,43 +259410,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6139$1438_Y + connect \Y $and$ls180.v:5945$1297_Y end - attribute \src "ls180.v:6139.39-6139.143" - cell $and $and$ls180.v:6139$1440 + attribute \src "ls180.v:5945.39-5945.143" + cell $and $and$ls180.v:5945$1299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6139$1438_Y - connect \B $eq$ls180.v:6139$1439_Y - connect \Y $and$ls180.v:6139$1440_Y + connect \A $and$ls180.v:5945$1297_Y + connect \B $eq$ls180.v:5945$1298_Y + connect \Y $and$ls180.v:5945$1299_Y end - attribute \src "ls180.v:6140.40-6140.96" - cell $and $and$ls180.v:6140$1442 + attribute \src "ls180.v:5946.40-5946.96" + cell $and $and$ls180.v:5946$1301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6140$1441_Y - connect \Y $and$ls180.v:6140$1442_Y + connect \B $not$ls180.v:5946$1300_Y + connect \Y $and$ls180.v:5946$1301_Y end - attribute \src "ls180.v:6140.39-6140.146" - cell $and $and$ls180.v:6140$1444 + attribute \src "ls180.v:5946.39-5946.146" + cell $and $and$ls180.v:5946$1303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6140$1442_Y - connect \B $eq$ls180.v:6140$1443_Y - connect \Y $and$ls180.v:6140$1444_Y + connect \A $and$ls180.v:5946$1301_Y + connect \B $eq$ls180.v:5946$1302_Y + connect \Y $and$ls180.v:5946$1303_Y end - attribute \src "ls180.v:6142.40-6142.93" - cell $and $and$ls180.v:6142$1445 + attribute \src "ls180.v:5948.40-5948.93" + cell $and $and$ls180.v:5948$1304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261166,43 +259454,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6142$1445_Y + connect \Y $and$ls180.v:5948$1304_Y end - attribute \src "ls180.v:6142.39-6142.143" - cell $and $and$ls180.v:6142$1447 + attribute \src "ls180.v:5948.39-5948.143" + cell $and $and$ls180.v:5948$1306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6142$1445_Y - connect \B $eq$ls180.v:6142$1446_Y - connect \Y $and$ls180.v:6142$1447_Y + connect \A $and$ls180.v:5948$1304_Y + connect \B $eq$ls180.v:5948$1305_Y + connect \Y $and$ls180.v:5948$1306_Y end - attribute \src "ls180.v:6143.40-6143.96" - cell $and $and$ls180.v:6143$1449 + attribute \src "ls180.v:5949.40-5949.96" + cell $and $and$ls180.v:5949$1308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6143$1448_Y - connect \Y $and$ls180.v:6143$1449_Y + connect \B $not$ls180.v:5949$1307_Y + connect \Y $and$ls180.v:5949$1308_Y end - attribute \src "ls180.v:6143.39-6143.146" - cell $and $and$ls180.v:6143$1451 + attribute \src "ls180.v:5949.39-5949.146" + cell $and $and$ls180.v:5949$1310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6143$1449_Y - connect \B $eq$ls180.v:6143$1450_Y - connect \Y $and$ls180.v:6143$1451_Y + connect \A $and$ls180.v:5949$1308_Y + connect \B $eq$ls180.v:5949$1309_Y + connect \Y $and$ls180.v:5949$1310_Y end - attribute \src "ls180.v:6145.40-6145.93" - cell $and $and$ls180.v:6145$1452 + attribute \src "ls180.v:5951.40-5951.93" + cell $and $and$ls180.v:5951$1311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261210,43 +259498,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6145$1452_Y + connect \Y $and$ls180.v:5951$1311_Y end - attribute \src "ls180.v:6145.39-6145.143" - cell $and $and$ls180.v:6145$1454 + attribute \src "ls180.v:5951.39-5951.143" + cell $and $and$ls180.v:5951$1313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6145$1452_Y - connect \B $eq$ls180.v:6145$1453_Y - connect \Y $and$ls180.v:6145$1454_Y + connect \A $and$ls180.v:5951$1311_Y + connect \B $eq$ls180.v:5951$1312_Y + connect \Y $and$ls180.v:5951$1313_Y end - attribute \src "ls180.v:6146.40-6146.96" - cell $and $and$ls180.v:6146$1456 + attribute \src "ls180.v:5952.40-5952.96" + cell $and $and$ls180.v:5952$1315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6146$1455_Y - connect \Y $and$ls180.v:6146$1456_Y + connect \B $not$ls180.v:5952$1314_Y + connect \Y $and$ls180.v:5952$1315_Y end - attribute \src "ls180.v:6146.39-6146.146" - cell $and $and$ls180.v:6146$1458 + attribute \src "ls180.v:5952.39-5952.146" + cell $and $and$ls180.v:5952$1317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6146$1456_Y - connect \B $eq$ls180.v:6146$1457_Y - connect \Y $and$ls180.v:6146$1458_Y + connect \A $and$ls180.v:5952$1315_Y + connect \B $eq$ls180.v:5952$1316_Y + connect \Y $and$ls180.v:5952$1317_Y end - attribute \src "ls180.v:6148.40-6148.93" - cell $and $and$ls180.v:6148$1459 + attribute \src "ls180.v:5954.40-5954.93" + cell $and $and$ls180.v:5954$1318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261254,43 +259542,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:6148$1459_Y + connect \Y $and$ls180.v:5954$1318_Y end - attribute \src "ls180.v:6148.39-6148.143" - cell $and $and$ls180.v:6148$1461 + attribute \src "ls180.v:5954.39-5954.143" + cell $and $and$ls180.v:5954$1320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6148$1459_Y - connect \B $eq$ls180.v:6148$1460_Y - connect \Y $and$ls180.v:6148$1461_Y + connect \A $and$ls180.v:5954$1318_Y + connect \B $eq$ls180.v:5954$1319_Y + connect \Y $and$ls180.v:5954$1320_Y end - attribute \src "ls180.v:6149.40-6149.96" - cell $and $and$ls180.v:6149$1463 + attribute \src "ls180.v:5955.40-5955.96" + cell $and $and$ls180.v:5955$1322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:6149$1462_Y - connect \Y $and$ls180.v:6149$1463_Y + connect \B $not$ls180.v:5955$1321_Y + connect \Y $and$ls180.v:5955$1322_Y end - attribute \src "ls180.v:6149.39-6149.146" - cell $and $and$ls180.v:6149$1465 + attribute \src "ls180.v:5955.39-5955.146" + cell $and $and$ls180.v:5955$1324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6149$1463_Y - connect \B $eq$ls180.v:6149$1464_Y - connect \Y $and$ls180.v:6149$1465_Y + connect \A $and$ls180.v:5955$1322_Y + connect \B $eq$ls180.v:5955$1323_Y + connect \Y $and$ls180.v:5955$1324_Y end - attribute \src "ls180.v:6161.40-6161.93" - cell $and $and$ls180.v:6161$1467 + attribute \src "ls180.v:5967.40-5967.93" + cell $and $and$ls180.v:5967$1326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261298,43 +259586,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6161$1467_Y + connect \Y $and$ls180.v:5967$1326_Y end - attribute \src "ls180.v:6161.39-6161.143" - cell $and $and$ls180.v:6161$1469 + attribute \src "ls180.v:5967.39-5967.143" + cell $and $and$ls180.v:5967$1328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6161$1467_Y - connect \B $eq$ls180.v:6161$1468_Y - connect \Y $and$ls180.v:6161$1469_Y + connect \A $and$ls180.v:5967$1326_Y + connect \B $eq$ls180.v:5967$1327_Y + connect \Y $and$ls180.v:5967$1328_Y end - attribute \src "ls180.v:6162.40-6162.96" - cell $and $and$ls180.v:6162$1471 + attribute \src "ls180.v:5968.40-5968.96" + cell $and $and$ls180.v:5968$1330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6162$1470_Y - connect \Y $and$ls180.v:6162$1471_Y + connect \B $not$ls180.v:5968$1329_Y + connect \Y $and$ls180.v:5968$1330_Y end - attribute \src "ls180.v:6162.39-6162.146" - cell $and $and$ls180.v:6162$1473 + attribute \src "ls180.v:5968.39-5968.146" + cell $and $and$ls180.v:5968$1332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6162$1471_Y - connect \B $eq$ls180.v:6162$1472_Y - connect \Y $and$ls180.v:6162$1473_Y + connect \A $and$ls180.v:5968$1330_Y + connect \B $eq$ls180.v:5968$1331_Y + connect \Y $and$ls180.v:5968$1332_Y end - attribute \src "ls180.v:6164.39-6164.92" - cell $and $and$ls180.v:6164$1474 + attribute \src "ls180.v:5970.39-5970.92" + cell $and $and$ls180.v:5970$1333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261342,43 +259630,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6164$1474_Y + connect \Y $and$ls180.v:5970$1333_Y end - attribute \src "ls180.v:6164.38-6164.142" - cell $and $and$ls180.v:6164$1476 + attribute \src "ls180.v:5970.38-5970.142" + cell $and $and$ls180.v:5970$1335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6164$1474_Y - connect \B $eq$ls180.v:6164$1475_Y - connect \Y $and$ls180.v:6164$1476_Y + connect \A $and$ls180.v:5970$1333_Y + connect \B $eq$ls180.v:5970$1334_Y + connect \Y $and$ls180.v:5970$1335_Y end - attribute \src "ls180.v:6165.39-6165.95" - cell $and $and$ls180.v:6165$1478 + attribute \src "ls180.v:5971.39-5971.95" + cell $and $and$ls180.v:5971$1337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6165$1477_Y - connect \Y $and$ls180.v:6165$1478_Y + connect \B $not$ls180.v:5971$1336_Y + connect \Y $and$ls180.v:5971$1337_Y end - attribute \src "ls180.v:6165.38-6165.145" - cell $and $and$ls180.v:6165$1480 + attribute \src "ls180.v:5971.38-5971.145" + cell $and $and$ls180.v:5971$1339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6165$1478_Y - connect \B $eq$ls180.v:6165$1479_Y - connect \Y $and$ls180.v:6165$1480_Y + connect \A $and$ls180.v:5971$1337_Y + connect \B $eq$ls180.v:5971$1338_Y + connect \Y $and$ls180.v:5971$1339_Y end - attribute \src "ls180.v:6167.39-6167.92" - cell $and $and$ls180.v:6167$1481 + attribute \src "ls180.v:5973.39-5973.92" + cell $and $and$ls180.v:5973$1340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261386,43 +259674,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6167$1481_Y + connect \Y $and$ls180.v:5973$1340_Y end - attribute \src "ls180.v:6167.38-6167.142" - cell $and $and$ls180.v:6167$1483 + attribute \src "ls180.v:5973.38-5973.142" + cell $and $and$ls180.v:5973$1342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6167$1481_Y - connect \B $eq$ls180.v:6167$1482_Y - connect \Y $and$ls180.v:6167$1483_Y + connect \A $and$ls180.v:5973$1340_Y + connect \B $eq$ls180.v:5973$1341_Y + connect \Y $and$ls180.v:5973$1342_Y end - attribute \src "ls180.v:6168.39-6168.95" - cell $and $and$ls180.v:6168$1485 + attribute \src "ls180.v:5974.39-5974.95" + cell $and $and$ls180.v:5974$1344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6168$1484_Y - connect \Y $and$ls180.v:6168$1485_Y + connect \B $not$ls180.v:5974$1343_Y + connect \Y $and$ls180.v:5974$1344_Y end - attribute \src "ls180.v:6168.38-6168.145" - cell $and $and$ls180.v:6168$1487 + attribute \src "ls180.v:5974.38-5974.145" + cell $and $and$ls180.v:5974$1346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6168$1485_Y - connect \B $eq$ls180.v:6168$1486_Y - connect \Y $and$ls180.v:6168$1487_Y + connect \A $and$ls180.v:5974$1344_Y + connect \B $eq$ls180.v:5974$1345_Y + connect \Y $and$ls180.v:5974$1346_Y end - attribute \src "ls180.v:6170.39-6170.92" - cell $and $and$ls180.v:6170$1488 + attribute \src "ls180.v:5976.39-5976.92" + cell $and $and$ls180.v:5976$1347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261430,43 +259718,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6170$1488_Y + connect \Y $and$ls180.v:5976$1347_Y end - attribute \src "ls180.v:6170.38-6170.142" - cell $and $and$ls180.v:6170$1490 + attribute \src "ls180.v:5976.38-5976.142" + cell $and $and$ls180.v:5976$1349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6170$1488_Y - connect \B $eq$ls180.v:6170$1489_Y - connect \Y $and$ls180.v:6170$1490_Y + connect \A $and$ls180.v:5976$1347_Y + connect \B $eq$ls180.v:5976$1348_Y + connect \Y $and$ls180.v:5976$1349_Y end - attribute \src "ls180.v:6171.39-6171.95" - cell $and $and$ls180.v:6171$1492 + attribute \src "ls180.v:5977.39-5977.95" + cell $and $and$ls180.v:5977$1351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6171$1491_Y - connect \Y $and$ls180.v:6171$1492_Y + connect \B $not$ls180.v:5977$1350_Y + connect \Y $and$ls180.v:5977$1351_Y end - attribute \src "ls180.v:6171.38-6171.145" - cell $and $and$ls180.v:6171$1494 + attribute \src "ls180.v:5977.38-5977.145" + cell $and $and$ls180.v:5977$1353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6171$1492_Y - connect \B $eq$ls180.v:6171$1493_Y - connect \Y $and$ls180.v:6171$1494_Y + connect \A $and$ls180.v:5977$1351_Y + connect \B $eq$ls180.v:5977$1352_Y + connect \Y $and$ls180.v:5977$1353_Y end - attribute \src "ls180.v:6173.39-6173.92" - cell $and $and$ls180.v:6173$1495 + attribute \src "ls180.v:5979.39-5979.92" + cell $and $and$ls180.v:5979$1354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261474,43 +259762,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6173$1495_Y + connect \Y $and$ls180.v:5979$1354_Y end - attribute \src "ls180.v:6173.38-6173.142" - cell $and $and$ls180.v:6173$1497 + attribute \src "ls180.v:5979.38-5979.142" + cell $and $and$ls180.v:5979$1356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6173$1495_Y - connect \B $eq$ls180.v:6173$1496_Y - connect \Y $and$ls180.v:6173$1497_Y + connect \A $and$ls180.v:5979$1354_Y + connect \B $eq$ls180.v:5979$1355_Y + connect \Y $and$ls180.v:5979$1356_Y end - attribute \src "ls180.v:6174.39-6174.95" - cell $and $and$ls180.v:6174$1499 + attribute \src "ls180.v:5980.39-5980.95" + cell $and $and$ls180.v:5980$1358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6174$1498_Y - connect \Y $and$ls180.v:6174$1499_Y + connect \B $not$ls180.v:5980$1357_Y + connect \Y $and$ls180.v:5980$1358_Y end - attribute \src "ls180.v:6174.38-6174.145" - cell $and $and$ls180.v:6174$1501 + attribute \src "ls180.v:5980.38-5980.145" + cell $and $and$ls180.v:5980$1360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6174$1499_Y - connect \B $eq$ls180.v:6174$1500_Y - connect \Y $and$ls180.v:6174$1501_Y + connect \A $and$ls180.v:5980$1358_Y + connect \B $eq$ls180.v:5980$1359_Y + connect \Y $and$ls180.v:5980$1360_Y end - attribute \src "ls180.v:6176.40-6176.93" - cell $and $and$ls180.v:6176$1502 + attribute \src "ls180.v:5982.40-5982.93" + cell $and $and$ls180.v:5982$1361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261518,43 +259806,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6176$1502_Y + connect \Y $and$ls180.v:5982$1361_Y end - attribute \src "ls180.v:6176.39-6176.143" - cell $and $and$ls180.v:6176$1504 + attribute \src "ls180.v:5982.39-5982.143" + cell $and $and$ls180.v:5982$1363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6176$1502_Y - connect \B $eq$ls180.v:6176$1503_Y - connect \Y $and$ls180.v:6176$1504_Y + connect \A $and$ls180.v:5982$1361_Y + connect \B $eq$ls180.v:5982$1362_Y + connect \Y $and$ls180.v:5982$1363_Y end - attribute \src "ls180.v:6177.40-6177.96" - cell $and $and$ls180.v:6177$1506 + attribute \src "ls180.v:5983.40-5983.96" + cell $and $and$ls180.v:5983$1365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6177$1505_Y - connect \Y $and$ls180.v:6177$1506_Y + connect \B $not$ls180.v:5983$1364_Y + connect \Y $and$ls180.v:5983$1365_Y end - attribute \src "ls180.v:6177.39-6177.146" - cell $and $and$ls180.v:6177$1508 + attribute \src "ls180.v:5983.39-5983.146" + cell $and $and$ls180.v:5983$1367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6177$1506_Y - connect \B $eq$ls180.v:6177$1507_Y - connect \Y $and$ls180.v:6177$1508_Y + connect \A $and$ls180.v:5983$1365_Y + connect \B $eq$ls180.v:5983$1366_Y + connect \Y $and$ls180.v:5983$1367_Y end - attribute \src "ls180.v:6179.40-6179.93" - cell $and $and$ls180.v:6179$1509 + attribute \src "ls180.v:5985.40-5985.93" + cell $and $and$ls180.v:5985$1368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261562,43 +259850,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6179$1509_Y + connect \Y $and$ls180.v:5985$1368_Y end - attribute \src "ls180.v:6179.39-6179.143" - cell $and $and$ls180.v:6179$1511 + attribute \src "ls180.v:5985.39-5985.143" + cell $and $and$ls180.v:5985$1370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6179$1509_Y - connect \B $eq$ls180.v:6179$1510_Y - connect \Y $and$ls180.v:6179$1511_Y + connect \A $and$ls180.v:5985$1368_Y + connect \B $eq$ls180.v:5985$1369_Y + connect \Y $and$ls180.v:5985$1370_Y end - attribute \src "ls180.v:6180.40-6180.96" - cell $and $and$ls180.v:6180$1513 + attribute \src "ls180.v:5986.40-5986.96" + cell $and $and$ls180.v:5986$1372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6180$1512_Y - connect \Y $and$ls180.v:6180$1513_Y + connect \B $not$ls180.v:5986$1371_Y + connect \Y $and$ls180.v:5986$1372_Y end - attribute \src "ls180.v:6180.39-6180.146" - cell $and $and$ls180.v:6180$1515 + attribute \src "ls180.v:5986.39-5986.146" + cell $and $and$ls180.v:5986$1374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6180$1513_Y - connect \B $eq$ls180.v:6180$1514_Y - connect \Y $and$ls180.v:6180$1515_Y + connect \A $and$ls180.v:5986$1372_Y + connect \B $eq$ls180.v:5986$1373_Y + connect \Y $and$ls180.v:5986$1374_Y end - attribute \src "ls180.v:6182.40-6182.93" - cell $and $and$ls180.v:6182$1516 + attribute \src "ls180.v:5988.40-5988.93" + cell $and $and$ls180.v:5988$1375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261606,43 +259894,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6182$1516_Y + connect \Y $and$ls180.v:5988$1375_Y end - attribute \src "ls180.v:6182.39-6182.143" - cell $and $and$ls180.v:6182$1518 + attribute \src "ls180.v:5988.39-5988.143" + cell $and $and$ls180.v:5988$1377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6182$1516_Y - connect \B $eq$ls180.v:6182$1517_Y - connect \Y $and$ls180.v:6182$1518_Y + connect \A $and$ls180.v:5988$1375_Y + connect \B $eq$ls180.v:5988$1376_Y + connect \Y $and$ls180.v:5988$1377_Y end - attribute \src "ls180.v:6183.40-6183.96" - cell $and $and$ls180.v:6183$1520 + attribute \src "ls180.v:5989.40-5989.96" + cell $and $and$ls180.v:5989$1379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6183$1519_Y - connect \Y $and$ls180.v:6183$1520_Y + connect \B $not$ls180.v:5989$1378_Y + connect \Y $and$ls180.v:5989$1379_Y end - attribute \src "ls180.v:6183.39-6183.146" - cell $and $and$ls180.v:6183$1522 + attribute \src "ls180.v:5989.39-5989.146" + cell $and $and$ls180.v:5989$1381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6183$1520_Y - connect \B $eq$ls180.v:6183$1521_Y - connect \Y $and$ls180.v:6183$1522_Y + connect \A $and$ls180.v:5989$1379_Y + connect \B $eq$ls180.v:5989$1380_Y + connect \Y $and$ls180.v:5989$1381_Y end - attribute \src "ls180.v:6185.40-6185.93" - cell $and $and$ls180.v:6185$1523 + attribute \src "ls180.v:5991.40-5991.93" + cell $and $and$ls180.v:5991$1382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261650,43 +259938,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:6185$1523_Y + connect \Y $and$ls180.v:5991$1382_Y end - attribute \src "ls180.v:6185.39-6185.143" - cell $and $and$ls180.v:6185$1525 + attribute \src "ls180.v:5991.39-5991.143" + cell $and $and$ls180.v:5991$1384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6185$1523_Y - connect \B $eq$ls180.v:6185$1524_Y - connect \Y $and$ls180.v:6185$1525_Y + connect \A $and$ls180.v:5991$1382_Y + connect \B $eq$ls180.v:5991$1383_Y + connect \Y $and$ls180.v:5991$1384_Y end - attribute \src "ls180.v:6186.40-6186.96" - cell $and $and$ls180.v:6186$1527 + attribute \src "ls180.v:5992.40-5992.96" + cell $and $and$ls180.v:5992$1386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:6186$1526_Y - connect \Y $and$ls180.v:6186$1527_Y + connect \B $not$ls180.v:5992$1385_Y + connect \Y $and$ls180.v:5992$1386_Y end - attribute \src "ls180.v:6186.39-6186.146" - cell $and $and$ls180.v:6186$1529 + attribute \src "ls180.v:5992.39-5992.146" + cell $and $and$ls180.v:5992$1388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6186$1527_Y - connect \B $eq$ls180.v:6186$1528_Y - connect \Y $and$ls180.v:6186$1529_Y + connect \A $and$ls180.v:5992$1386_Y + connect \B $eq$ls180.v:5992$1387_Y + connect \Y $and$ls180.v:5992$1388_Y end - attribute \src "ls180.v:6198.42-6198.95" - cell $and $and$ls180.v:6198$1531 + attribute \src "ls180.v:6004.42-6004.95" + cell $and $and$ls180.v:6004$1390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261694,43 +259982,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6198$1531_Y + connect \Y $and$ls180.v:6004$1390_Y end - attribute \src "ls180.v:6198.41-6198.145" - cell $and $and$ls180.v:6198$1533 + attribute \src "ls180.v:6004.41-6004.145" + cell $and $and$ls180.v:6004$1392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6198$1531_Y - connect \B $eq$ls180.v:6198$1532_Y - connect \Y $and$ls180.v:6198$1533_Y + connect \A $and$ls180.v:6004$1390_Y + connect \B $eq$ls180.v:6004$1391_Y + connect \Y $and$ls180.v:6004$1392_Y end - attribute \src "ls180.v:6199.42-6199.98" - cell $and $and$ls180.v:6199$1535 + attribute \src "ls180.v:6005.42-6005.98" + cell $and $and$ls180.v:6005$1394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6199$1534_Y - connect \Y $and$ls180.v:6199$1535_Y + connect \B $not$ls180.v:6005$1393_Y + connect \Y $and$ls180.v:6005$1394_Y end - attribute \src "ls180.v:6199.41-6199.148" - cell $and $and$ls180.v:6199$1537 + attribute \src "ls180.v:6005.41-6005.148" + cell $and $and$ls180.v:6005$1396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6199$1535_Y - connect \B $eq$ls180.v:6199$1536_Y - connect \Y $and$ls180.v:6199$1537_Y + connect \A $and$ls180.v:6005$1394_Y + connect \B $eq$ls180.v:6005$1395_Y + connect \Y $and$ls180.v:6005$1396_Y end - attribute \src "ls180.v:6201.42-6201.95" - cell $and $and$ls180.v:6201$1538 + attribute \src "ls180.v:6007.42-6007.95" + cell $and $and$ls180.v:6007$1397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261738,43 +260026,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6201$1538_Y + connect \Y $and$ls180.v:6007$1397_Y end - attribute \src "ls180.v:6201.41-6201.145" - cell $and $and$ls180.v:6201$1540 + attribute \src "ls180.v:6007.41-6007.145" + cell $and $and$ls180.v:6007$1399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6201$1538_Y - connect \B $eq$ls180.v:6201$1539_Y - connect \Y $and$ls180.v:6201$1540_Y + connect \A $and$ls180.v:6007$1397_Y + connect \B $eq$ls180.v:6007$1398_Y + connect \Y $and$ls180.v:6007$1399_Y end - attribute \src "ls180.v:6202.42-6202.98" - cell $and $and$ls180.v:6202$1542 + attribute \src "ls180.v:6008.42-6008.98" + cell $and $and$ls180.v:6008$1401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6202$1541_Y - connect \Y $and$ls180.v:6202$1542_Y + connect \B $not$ls180.v:6008$1400_Y + connect \Y $and$ls180.v:6008$1401_Y end - attribute \src "ls180.v:6202.41-6202.148" - cell $and $and$ls180.v:6202$1544 + attribute \src "ls180.v:6008.41-6008.148" + cell $and $and$ls180.v:6008$1403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6202$1542_Y - connect \B $eq$ls180.v:6202$1543_Y - connect \Y $and$ls180.v:6202$1544_Y + connect \A $and$ls180.v:6008$1401_Y + connect \B $eq$ls180.v:6008$1402_Y + connect \Y $and$ls180.v:6008$1403_Y end - attribute \src "ls180.v:6204.42-6204.95" - cell $and $and$ls180.v:6204$1545 + attribute \src "ls180.v:6010.42-6010.95" + cell $and $and$ls180.v:6010$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261782,43 +260070,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6204$1545_Y + connect \Y $and$ls180.v:6010$1404_Y end - attribute \src "ls180.v:6204.41-6204.145" - cell $and $and$ls180.v:6204$1547 + attribute \src "ls180.v:6010.41-6010.145" + cell $and $and$ls180.v:6010$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6204$1545_Y - connect \B $eq$ls180.v:6204$1546_Y - connect \Y $and$ls180.v:6204$1547_Y + connect \A $and$ls180.v:6010$1404_Y + connect \B $eq$ls180.v:6010$1405_Y + connect \Y $and$ls180.v:6010$1406_Y end - attribute \src "ls180.v:6205.42-6205.98" - cell $and $and$ls180.v:6205$1549 + attribute \src "ls180.v:6011.42-6011.98" + cell $and $and$ls180.v:6011$1408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6205$1548_Y - connect \Y $and$ls180.v:6205$1549_Y + connect \B $not$ls180.v:6011$1407_Y + connect \Y $and$ls180.v:6011$1408_Y end - attribute \src "ls180.v:6205.41-6205.148" - cell $and $and$ls180.v:6205$1551 + attribute \src "ls180.v:6011.41-6011.148" + cell $and $and$ls180.v:6011$1410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6205$1549_Y - connect \B $eq$ls180.v:6205$1550_Y - connect \Y $and$ls180.v:6205$1551_Y + connect \A $and$ls180.v:6011$1408_Y + connect \B $eq$ls180.v:6011$1409_Y + connect \Y $and$ls180.v:6011$1410_Y end - attribute \src "ls180.v:6207.42-6207.95" - cell $and $and$ls180.v:6207$1552 + attribute \src "ls180.v:6013.42-6013.95" + cell $and $and$ls180.v:6013$1411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261826,43 +260114,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6207$1552_Y + connect \Y $and$ls180.v:6013$1411_Y end - attribute \src "ls180.v:6207.41-6207.145" - cell $and $and$ls180.v:6207$1554 + attribute \src "ls180.v:6013.41-6013.145" + cell $and $and$ls180.v:6013$1413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6207$1552_Y - connect \B $eq$ls180.v:6207$1553_Y - connect \Y $and$ls180.v:6207$1554_Y + connect \A $and$ls180.v:6013$1411_Y + connect \B $eq$ls180.v:6013$1412_Y + connect \Y $and$ls180.v:6013$1413_Y end - attribute \src "ls180.v:6208.42-6208.98" - cell $and $and$ls180.v:6208$1556 + attribute \src "ls180.v:6014.42-6014.98" + cell $and $and$ls180.v:6014$1415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6208$1555_Y - connect \Y $and$ls180.v:6208$1556_Y + connect \B $not$ls180.v:6014$1414_Y + connect \Y $and$ls180.v:6014$1415_Y end - attribute \src "ls180.v:6208.41-6208.148" - cell $and $and$ls180.v:6208$1558 + attribute \src "ls180.v:6014.41-6014.148" + cell $and $and$ls180.v:6014$1417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6208$1556_Y - connect \B $eq$ls180.v:6208$1557_Y - connect \Y $and$ls180.v:6208$1558_Y + connect \A $and$ls180.v:6014$1415_Y + connect \B $eq$ls180.v:6014$1416_Y + connect \Y $and$ls180.v:6014$1417_Y end - attribute \src "ls180.v:6210.42-6210.95" - cell $and $and$ls180.v:6210$1559 + attribute \src "ls180.v:6016.42-6016.95" + cell $and $and$ls180.v:6016$1418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261870,43 +260158,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6210$1559_Y + connect \Y $and$ls180.v:6016$1418_Y end - attribute \src "ls180.v:6210.41-6210.145" - cell $and $and$ls180.v:6210$1561 + attribute \src "ls180.v:6016.41-6016.145" + cell $and $and$ls180.v:6016$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6210$1559_Y - connect \B $eq$ls180.v:6210$1560_Y - connect \Y $and$ls180.v:6210$1561_Y + connect \A $and$ls180.v:6016$1418_Y + connect \B $eq$ls180.v:6016$1419_Y + connect \Y $and$ls180.v:6016$1420_Y end - attribute \src "ls180.v:6211.42-6211.98" - cell $and $and$ls180.v:6211$1563 + attribute \src "ls180.v:6017.42-6017.98" + cell $and $and$ls180.v:6017$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6211$1562_Y - connect \Y $and$ls180.v:6211$1563_Y + connect \B $not$ls180.v:6017$1421_Y + connect \Y $and$ls180.v:6017$1422_Y end - attribute \src "ls180.v:6211.41-6211.148" - cell $and $and$ls180.v:6211$1565 + attribute \src "ls180.v:6017.41-6017.148" + cell $and $and$ls180.v:6017$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6211$1563_Y - connect \B $eq$ls180.v:6211$1564_Y - connect \Y $and$ls180.v:6211$1565_Y + connect \A $and$ls180.v:6017$1422_Y + connect \B $eq$ls180.v:6017$1423_Y + connect \Y $and$ls180.v:6017$1424_Y end - attribute \src "ls180.v:6213.42-6213.95" - cell $and $and$ls180.v:6213$1566 + attribute \src "ls180.v:6019.42-6019.95" + cell $and $and$ls180.v:6019$1425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261914,43 +260202,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6213$1566_Y + connect \Y $and$ls180.v:6019$1425_Y end - attribute \src "ls180.v:6213.41-6213.145" - cell $and $and$ls180.v:6213$1568 + attribute \src "ls180.v:6019.41-6019.145" + cell $and $and$ls180.v:6019$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6213$1566_Y - connect \B $eq$ls180.v:6213$1567_Y - connect \Y $and$ls180.v:6213$1568_Y + connect \A $and$ls180.v:6019$1425_Y + connect \B $eq$ls180.v:6019$1426_Y + connect \Y $and$ls180.v:6019$1427_Y end - attribute \src "ls180.v:6214.42-6214.98" - cell $and $and$ls180.v:6214$1570 + attribute \src "ls180.v:6020.42-6020.98" + cell $and $and$ls180.v:6020$1429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6214$1569_Y - connect \Y $and$ls180.v:6214$1570_Y + connect \B $not$ls180.v:6020$1428_Y + connect \Y $and$ls180.v:6020$1429_Y end - attribute \src "ls180.v:6214.41-6214.148" - cell $and $and$ls180.v:6214$1572 + attribute \src "ls180.v:6020.41-6020.148" + cell $and $and$ls180.v:6020$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6214$1570_Y - connect \B $eq$ls180.v:6214$1571_Y - connect \Y $and$ls180.v:6214$1572_Y + connect \A $and$ls180.v:6020$1429_Y + connect \B $eq$ls180.v:6020$1430_Y + connect \Y $and$ls180.v:6020$1431_Y end - attribute \src "ls180.v:6216.42-6216.95" - cell $and $and$ls180.v:6216$1573 + attribute \src "ls180.v:6022.42-6022.95" + cell $and $and$ls180.v:6022$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -261958,43 +260246,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6216$1573_Y + connect \Y $and$ls180.v:6022$1432_Y end - attribute \src "ls180.v:6216.41-6216.145" - cell $and $and$ls180.v:6216$1575 + attribute \src "ls180.v:6022.41-6022.145" + cell $and $and$ls180.v:6022$1434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6216$1573_Y - connect \B $eq$ls180.v:6216$1574_Y - connect \Y $and$ls180.v:6216$1575_Y + connect \A $and$ls180.v:6022$1432_Y + connect \B $eq$ls180.v:6022$1433_Y + connect \Y $and$ls180.v:6022$1434_Y end - attribute \src "ls180.v:6217.42-6217.98" - cell $and $and$ls180.v:6217$1577 + attribute \src "ls180.v:6023.42-6023.98" + cell $and $and$ls180.v:6023$1436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6217$1576_Y - connect \Y $and$ls180.v:6217$1577_Y + connect \B $not$ls180.v:6023$1435_Y + connect \Y $and$ls180.v:6023$1436_Y end - attribute \src "ls180.v:6217.41-6217.148" - cell $and $and$ls180.v:6217$1579 + attribute \src "ls180.v:6023.41-6023.148" + cell $and $and$ls180.v:6023$1438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6217$1577_Y - connect \B $eq$ls180.v:6217$1578_Y - connect \Y $and$ls180.v:6217$1579_Y + connect \A $and$ls180.v:6023$1436_Y + connect \B $eq$ls180.v:6023$1437_Y + connect \Y $and$ls180.v:6023$1438_Y end - attribute \src "ls180.v:6219.42-6219.95" - cell $and $and$ls180.v:6219$1580 + attribute \src "ls180.v:6025.42-6025.95" + cell $and $and$ls180.v:6025$1439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262002,43 +260290,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6219$1580_Y + connect \Y $and$ls180.v:6025$1439_Y end - attribute \src "ls180.v:6219.41-6219.145" - cell $and $and$ls180.v:6219$1582 + attribute \src "ls180.v:6025.41-6025.145" + cell $and $and$ls180.v:6025$1441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6219$1580_Y - connect \B $eq$ls180.v:6219$1581_Y - connect \Y $and$ls180.v:6219$1582_Y + connect \A $and$ls180.v:6025$1439_Y + connect \B $eq$ls180.v:6025$1440_Y + connect \Y $and$ls180.v:6025$1441_Y end - attribute \src "ls180.v:6220.42-6220.98" - cell $and $and$ls180.v:6220$1584 + attribute \src "ls180.v:6026.42-6026.98" + cell $and $and$ls180.v:6026$1443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6220$1583_Y - connect \Y $and$ls180.v:6220$1584_Y + connect \B $not$ls180.v:6026$1442_Y + connect \Y $and$ls180.v:6026$1443_Y end - attribute \src "ls180.v:6220.41-6220.148" - cell $and $and$ls180.v:6220$1586 + attribute \src "ls180.v:6026.41-6026.148" + cell $and $and$ls180.v:6026$1445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6220$1584_Y - connect \B $eq$ls180.v:6220$1585_Y - connect \Y $and$ls180.v:6220$1586_Y + connect \A $and$ls180.v:6026$1443_Y + connect \B $eq$ls180.v:6026$1444_Y + connect \Y $and$ls180.v:6026$1445_Y end - attribute \src "ls180.v:6222.44-6222.97" - cell $and $and$ls180.v:6222$1587 + attribute \src "ls180.v:6028.44-6028.97" + cell $and $and$ls180.v:6028$1446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262046,43 +260334,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6222$1587_Y + connect \Y $and$ls180.v:6028$1446_Y end - attribute \src "ls180.v:6222.43-6222.147" - cell $and $and$ls180.v:6222$1589 + attribute \src "ls180.v:6028.43-6028.147" + cell $and $and$ls180.v:6028$1448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6222$1587_Y - connect \B $eq$ls180.v:6222$1588_Y - connect \Y $and$ls180.v:6222$1589_Y + connect \A $and$ls180.v:6028$1446_Y + connect \B $eq$ls180.v:6028$1447_Y + connect \Y $and$ls180.v:6028$1448_Y end - attribute \src "ls180.v:6223.44-6223.100" - cell $and $and$ls180.v:6223$1591 + attribute \src "ls180.v:6029.44-6029.100" + cell $and $and$ls180.v:6029$1450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6223$1590_Y - connect \Y $and$ls180.v:6223$1591_Y + connect \B $not$ls180.v:6029$1449_Y + connect \Y $and$ls180.v:6029$1450_Y end - attribute \src "ls180.v:6223.43-6223.150" - cell $and $and$ls180.v:6223$1593 + attribute \src "ls180.v:6029.43-6029.150" + cell $and $and$ls180.v:6029$1452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6223$1591_Y - connect \B $eq$ls180.v:6223$1592_Y - connect \Y $and$ls180.v:6223$1593_Y + connect \A $and$ls180.v:6029$1450_Y + connect \B $eq$ls180.v:6029$1451_Y + connect \Y $and$ls180.v:6029$1452_Y end - attribute \src "ls180.v:6225.44-6225.97" - cell $and $and$ls180.v:6225$1594 + attribute \src "ls180.v:6031.44-6031.97" + cell $and $and$ls180.v:6031$1453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262090,43 +260378,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6225$1594_Y + connect \Y $and$ls180.v:6031$1453_Y end - attribute \src "ls180.v:6225.43-6225.147" - cell $and $and$ls180.v:6225$1596 + attribute \src "ls180.v:6031.43-6031.147" + cell $and $and$ls180.v:6031$1455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6225$1594_Y - connect \B $eq$ls180.v:6225$1595_Y - connect \Y $and$ls180.v:6225$1596_Y + connect \A $and$ls180.v:6031$1453_Y + connect \B $eq$ls180.v:6031$1454_Y + connect \Y $and$ls180.v:6031$1455_Y end - attribute \src "ls180.v:6226.44-6226.100" - cell $and $and$ls180.v:6226$1598 + attribute \src "ls180.v:6032.44-6032.100" + cell $and $and$ls180.v:6032$1457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6226$1597_Y - connect \Y $and$ls180.v:6226$1598_Y + connect \B $not$ls180.v:6032$1456_Y + connect \Y $and$ls180.v:6032$1457_Y end - attribute \src "ls180.v:6226.43-6226.150" - cell $and $and$ls180.v:6226$1600 + attribute \src "ls180.v:6032.43-6032.150" + cell $and $and$ls180.v:6032$1459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6226$1598_Y - connect \B $eq$ls180.v:6226$1599_Y - connect \Y $and$ls180.v:6226$1600_Y + connect \A $and$ls180.v:6032$1457_Y + connect \B $eq$ls180.v:6032$1458_Y + connect \Y $and$ls180.v:6032$1459_Y end - attribute \src "ls180.v:6228.44-6228.97" - cell $and $and$ls180.v:6228$1601 + attribute \src "ls180.v:6034.44-6034.97" + cell $and $and$ls180.v:6034$1460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262134,43 +260422,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6228$1601_Y + connect \Y $and$ls180.v:6034$1460_Y end - attribute \src "ls180.v:6228.43-6228.148" - cell $and $and$ls180.v:6228$1603 + attribute \src "ls180.v:6034.43-6034.148" + cell $and $and$ls180.v:6034$1462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6228$1601_Y - connect \B $eq$ls180.v:6228$1602_Y - connect \Y $and$ls180.v:6228$1603_Y + connect \A $and$ls180.v:6034$1460_Y + connect \B $eq$ls180.v:6034$1461_Y + connect \Y $and$ls180.v:6034$1462_Y end - attribute \src "ls180.v:6229.44-6229.100" - cell $and $and$ls180.v:6229$1605 + attribute \src "ls180.v:6035.44-6035.100" + cell $and $and$ls180.v:6035$1464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6229$1604_Y - connect \Y $and$ls180.v:6229$1605_Y + connect \B $not$ls180.v:6035$1463_Y + connect \Y $and$ls180.v:6035$1464_Y end - attribute \src "ls180.v:6229.43-6229.151" - cell $and $and$ls180.v:6229$1607 + attribute \src "ls180.v:6035.43-6035.151" + cell $and $and$ls180.v:6035$1466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6229$1605_Y - connect \B $eq$ls180.v:6229$1606_Y - connect \Y $and$ls180.v:6229$1607_Y + connect \A $and$ls180.v:6035$1464_Y + connect \B $eq$ls180.v:6035$1465_Y + connect \Y $and$ls180.v:6035$1466_Y end - attribute \src "ls180.v:6231.44-6231.97" - cell $and $and$ls180.v:6231$1608 + attribute \src "ls180.v:6037.44-6037.97" + cell $and $and$ls180.v:6037$1467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262178,43 +260466,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6231$1608_Y + connect \Y $and$ls180.v:6037$1467_Y end - attribute \src "ls180.v:6231.43-6231.148" - cell $and $and$ls180.v:6231$1610 + attribute \src "ls180.v:6037.43-6037.148" + cell $and $and$ls180.v:6037$1469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6231$1608_Y - connect \B $eq$ls180.v:6231$1609_Y - connect \Y $and$ls180.v:6231$1610_Y + connect \A $and$ls180.v:6037$1467_Y + connect \B $eq$ls180.v:6037$1468_Y + connect \Y $and$ls180.v:6037$1469_Y end - attribute \src "ls180.v:6232.44-6232.100" - cell $and $and$ls180.v:6232$1612 + attribute \src "ls180.v:6038.44-6038.100" + cell $and $and$ls180.v:6038$1471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6232$1611_Y - connect \Y $and$ls180.v:6232$1612_Y + connect \B $not$ls180.v:6038$1470_Y + connect \Y $and$ls180.v:6038$1471_Y end - attribute \src "ls180.v:6232.43-6232.151" - cell $and $and$ls180.v:6232$1614 + attribute \src "ls180.v:6038.43-6038.151" + cell $and $and$ls180.v:6038$1473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6232$1612_Y - connect \B $eq$ls180.v:6232$1613_Y - connect \Y $and$ls180.v:6232$1614_Y + connect \A $and$ls180.v:6038$1471_Y + connect \B $eq$ls180.v:6038$1472_Y + connect \Y $and$ls180.v:6038$1473_Y end - attribute \src "ls180.v:6234.44-6234.97" - cell $and $and$ls180.v:6234$1615 + attribute \src "ls180.v:6040.44-6040.97" + cell $and $and$ls180.v:6040$1474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262222,43 +260510,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6234$1615_Y + connect \Y $and$ls180.v:6040$1474_Y end - attribute \src "ls180.v:6234.43-6234.148" - cell $and $and$ls180.v:6234$1617 + attribute \src "ls180.v:6040.43-6040.148" + cell $and $and$ls180.v:6040$1476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6234$1615_Y - connect \B $eq$ls180.v:6234$1616_Y - connect \Y $and$ls180.v:6234$1617_Y + connect \A $and$ls180.v:6040$1474_Y + connect \B $eq$ls180.v:6040$1475_Y + connect \Y $and$ls180.v:6040$1476_Y end - attribute \src "ls180.v:6235.44-6235.100" - cell $and $and$ls180.v:6235$1619 + attribute \src "ls180.v:6041.44-6041.100" + cell $and $and$ls180.v:6041$1478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6235$1618_Y - connect \Y $and$ls180.v:6235$1619_Y + connect \B $not$ls180.v:6041$1477_Y + connect \Y $and$ls180.v:6041$1478_Y end - attribute \src "ls180.v:6235.43-6235.151" - cell $and $and$ls180.v:6235$1621 + attribute \src "ls180.v:6041.43-6041.151" + cell $and $and$ls180.v:6041$1480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6235$1619_Y - connect \B $eq$ls180.v:6235$1620_Y - connect \Y $and$ls180.v:6235$1621_Y + connect \A $and$ls180.v:6041$1478_Y + connect \B $eq$ls180.v:6041$1479_Y + connect \Y $and$ls180.v:6041$1480_Y end - attribute \src "ls180.v:6237.41-6237.94" - cell $and $and$ls180.v:6237$1622 + attribute \src "ls180.v:6043.41-6043.94" + cell $and $and$ls180.v:6043$1481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262266,43 +260554,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6237$1622_Y + connect \Y $and$ls180.v:6043$1481_Y end - attribute \src "ls180.v:6237.40-6237.145" - cell $and $and$ls180.v:6237$1624 + attribute \src "ls180.v:6043.40-6043.145" + cell $and $and$ls180.v:6043$1483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6237$1622_Y - connect \B $eq$ls180.v:6237$1623_Y - connect \Y $and$ls180.v:6237$1624_Y + connect \A $and$ls180.v:6043$1481_Y + connect \B $eq$ls180.v:6043$1482_Y + connect \Y $and$ls180.v:6043$1483_Y end - attribute \src "ls180.v:6238.41-6238.97" - cell $and $and$ls180.v:6238$1626 + attribute \src "ls180.v:6044.41-6044.97" + cell $and $and$ls180.v:6044$1485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6238$1625_Y - connect \Y $and$ls180.v:6238$1626_Y + connect \B $not$ls180.v:6044$1484_Y + connect \Y $and$ls180.v:6044$1485_Y end - attribute \src "ls180.v:6238.40-6238.148" - cell $and $and$ls180.v:6238$1628 + attribute \src "ls180.v:6044.40-6044.148" + cell $and $and$ls180.v:6044$1487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6238$1626_Y - connect \B $eq$ls180.v:6238$1627_Y - connect \Y $and$ls180.v:6238$1628_Y + connect \A $and$ls180.v:6044$1485_Y + connect \B $eq$ls180.v:6044$1486_Y + connect \Y $and$ls180.v:6044$1487_Y end - attribute \src "ls180.v:6240.42-6240.95" - cell $and $and$ls180.v:6240$1629 + attribute \src "ls180.v:6046.42-6046.95" + cell $and $and$ls180.v:6046$1488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262310,43 +260598,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6240$1629_Y + connect \Y $and$ls180.v:6046$1488_Y end - attribute \src "ls180.v:6240.41-6240.146" - cell $and $and$ls180.v:6240$1631 + attribute \src "ls180.v:6046.41-6046.146" + cell $and $and$ls180.v:6046$1490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6240$1629_Y - connect \B $eq$ls180.v:6240$1630_Y - connect \Y $and$ls180.v:6240$1631_Y + connect \A $and$ls180.v:6046$1488_Y + connect \B $eq$ls180.v:6046$1489_Y + connect \Y $and$ls180.v:6046$1490_Y end - attribute \src "ls180.v:6241.42-6241.98" - cell $and $and$ls180.v:6241$1633 + attribute \src "ls180.v:6047.42-6047.98" + cell $and $and$ls180.v:6047$1492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6241$1632_Y - connect \Y $and$ls180.v:6241$1633_Y + connect \B $not$ls180.v:6047$1491_Y + connect \Y $and$ls180.v:6047$1492_Y end - attribute \src "ls180.v:6241.41-6241.149" - cell $and $and$ls180.v:6241$1635 + attribute \src "ls180.v:6047.41-6047.149" + cell $and $and$ls180.v:6047$1494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6241$1633_Y - connect \B $eq$ls180.v:6241$1634_Y - connect \Y $and$ls180.v:6241$1635_Y + connect \A $and$ls180.v:6047$1492_Y + connect \B $eq$ls180.v:6047$1493_Y + connect \Y $and$ls180.v:6047$1494_Y end - attribute \src "ls180.v:6260.46-6260.99" - cell $and $and$ls180.v:6260$1637 + attribute \src "ls180.v:6066.46-6066.99" + cell $and $and$ls180.v:6066$1496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262354,43 +260642,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6260$1637_Y + connect \Y $and$ls180.v:6066$1496_Y end - attribute \src "ls180.v:6260.45-6260.149" - cell $and $and$ls180.v:6260$1639 + attribute \src "ls180.v:6066.45-6066.149" + cell $and $and$ls180.v:6066$1498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6260$1637_Y - connect \B $eq$ls180.v:6260$1638_Y - connect \Y $and$ls180.v:6260$1639_Y + connect \A $and$ls180.v:6066$1496_Y + connect \B $eq$ls180.v:6066$1497_Y + connect \Y $and$ls180.v:6066$1498_Y end - attribute \src "ls180.v:6261.46-6261.102" - cell $and $and$ls180.v:6261$1641 + attribute \src "ls180.v:6067.46-6067.102" + cell $and $and$ls180.v:6067$1500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6261$1640_Y - connect \Y $and$ls180.v:6261$1641_Y + connect \B $not$ls180.v:6067$1499_Y + connect \Y $and$ls180.v:6067$1500_Y end - attribute \src "ls180.v:6261.45-6261.152" - cell $and $and$ls180.v:6261$1643 + attribute \src "ls180.v:6067.45-6067.152" + cell $and $and$ls180.v:6067$1502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6261$1641_Y - connect \B $eq$ls180.v:6261$1642_Y - connect \Y $and$ls180.v:6261$1643_Y + connect \A $and$ls180.v:6067$1500_Y + connect \B $eq$ls180.v:6067$1501_Y + connect \Y $and$ls180.v:6067$1502_Y end - attribute \src "ls180.v:6263.46-6263.99" - cell $and $and$ls180.v:6263$1644 + attribute \src "ls180.v:6069.46-6069.99" + cell $and $and$ls180.v:6069$1503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262398,43 +260686,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6263$1644_Y + connect \Y $and$ls180.v:6069$1503_Y end - attribute \src "ls180.v:6263.45-6263.149" - cell $and $and$ls180.v:6263$1646 + attribute \src "ls180.v:6069.45-6069.149" + cell $and $and$ls180.v:6069$1505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6263$1644_Y - connect \B $eq$ls180.v:6263$1645_Y - connect \Y $and$ls180.v:6263$1646_Y + connect \A $and$ls180.v:6069$1503_Y + connect \B $eq$ls180.v:6069$1504_Y + connect \Y $and$ls180.v:6069$1505_Y end - attribute \src "ls180.v:6264.46-6264.102" - cell $and $and$ls180.v:6264$1648 + attribute \src "ls180.v:6070.46-6070.102" + cell $and $and$ls180.v:6070$1507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6264$1647_Y - connect \Y $and$ls180.v:6264$1648_Y + connect \B $not$ls180.v:6070$1506_Y + connect \Y $and$ls180.v:6070$1507_Y end - attribute \src "ls180.v:6264.45-6264.152" - cell $and $and$ls180.v:6264$1650 + attribute \src "ls180.v:6070.45-6070.152" + cell $and $and$ls180.v:6070$1509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6264$1648_Y - connect \B $eq$ls180.v:6264$1649_Y - connect \Y $and$ls180.v:6264$1650_Y + connect \A $and$ls180.v:6070$1507_Y + connect \B $eq$ls180.v:6070$1508_Y + connect \Y $and$ls180.v:6070$1509_Y end - attribute \src "ls180.v:6266.46-6266.99" - cell $and $and$ls180.v:6266$1651 + attribute \src "ls180.v:6072.46-6072.99" + cell $and $and$ls180.v:6072$1510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262442,43 +260730,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6266$1651_Y + connect \Y $and$ls180.v:6072$1510_Y end - attribute \src "ls180.v:6266.45-6266.149" - cell $and $and$ls180.v:6266$1653 + attribute \src "ls180.v:6072.45-6072.149" + cell $and $and$ls180.v:6072$1512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6266$1651_Y - connect \B $eq$ls180.v:6266$1652_Y - connect \Y $and$ls180.v:6266$1653_Y + connect \A $and$ls180.v:6072$1510_Y + connect \B $eq$ls180.v:6072$1511_Y + connect \Y $and$ls180.v:6072$1512_Y end - attribute \src "ls180.v:6267.46-6267.102" - cell $and $and$ls180.v:6267$1655 + attribute \src "ls180.v:6073.46-6073.102" + cell $and $and$ls180.v:6073$1514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6267$1654_Y - connect \Y $and$ls180.v:6267$1655_Y + connect \B $not$ls180.v:6073$1513_Y + connect \Y $and$ls180.v:6073$1514_Y end - attribute \src "ls180.v:6267.45-6267.152" - cell $and $and$ls180.v:6267$1657 + attribute \src "ls180.v:6073.45-6073.152" + cell $and $and$ls180.v:6073$1516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6267$1655_Y - connect \B $eq$ls180.v:6267$1656_Y - connect \Y $and$ls180.v:6267$1657_Y + connect \A $and$ls180.v:6073$1514_Y + connect \B $eq$ls180.v:6073$1515_Y + connect \Y $and$ls180.v:6073$1516_Y end - attribute \src "ls180.v:6269.46-6269.99" - cell $and $and$ls180.v:6269$1658 + attribute \src "ls180.v:6075.46-6075.99" + cell $and $and$ls180.v:6075$1517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262486,43 +260774,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6269$1658_Y + connect \Y $and$ls180.v:6075$1517_Y end - attribute \src "ls180.v:6269.45-6269.149" - cell $and $and$ls180.v:6269$1660 + attribute \src "ls180.v:6075.45-6075.149" + cell $and $and$ls180.v:6075$1519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6269$1658_Y - connect \B $eq$ls180.v:6269$1659_Y - connect \Y $and$ls180.v:6269$1660_Y + connect \A $and$ls180.v:6075$1517_Y + connect \B $eq$ls180.v:6075$1518_Y + connect \Y $and$ls180.v:6075$1519_Y end - attribute \src "ls180.v:6270.46-6270.102" - cell $and $and$ls180.v:6270$1662 + attribute \src "ls180.v:6076.46-6076.102" + cell $and $and$ls180.v:6076$1521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6270$1661_Y - connect \Y $and$ls180.v:6270$1662_Y + connect \B $not$ls180.v:6076$1520_Y + connect \Y $and$ls180.v:6076$1521_Y end - attribute \src "ls180.v:6270.45-6270.152" - cell $and $and$ls180.v:6270$1664 + attribute \src "ls180.v:6076.45-6076.152" + cell $and $and$ls180.v:6076$1523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6270$1662_Y - connect \B $eq$ls180.v:6270$1663_Y - connect \Y $and$ls180.v:6270$1664_Y + connect \A $and$ls180.v:6076$1521_Y + connect \B $eq$ls180.v:6076$1522_Y + connect \Y $and$ls180.v:6076$1523_Y end - attribute \src "ls180.v:6272.45-6272.98" - cell $and $and$ls180.v:6272$1665 + attribute \src "ls180.v:6078.45-6078.98" + cell $and $and$ls180.v:6078$1524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262530,43 +260818,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6272$1665_Y + connect \Y $and$ls180.v:6078$1524_Y end - attribute \src "ls180.v:6272.44-6272.148" - cell $and $and$ls180.v:6272$1667 + attribute \src "ls180.v:6078.44-6078.148" + cell $and $and$ls180.v:6078$1526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6272$1665_Y - connect \B $eq$ls180.v:6272$1666_Y - connect \Y $and$ls180.v:6272$1667_Y + connect \A $and$ls180.v:6078$1524_Y + connect \B $eq$ls180.v:6078$1525_Y + connect \Y $and$ls180.v:6078$1526_Y end - attribute \src "ls180.v:6273.45-6273.101" - cell $and $and$ls180.v:6273$1669 + attribute \src "ls180.v:6079.45-6079.101" + cell $and $and$ls180.v:6079$1528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6273$1668_Y - connect \Y $and$ls180.v:6273$1669_Y + connect \B $not$ls180.v:6079$1527_Y + connect \Y $and$ls180.v:6079$1528_Y end - attribute \src "ls180.v:6273.44-6273.151" - cell $and $and$ls180.v:6273$1671 + attribute \src "ls180.v:6079.44-6079.151" + cell $and $and$ls180.v:6079$1530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6273$1669_Y - connect \B $eq$ls180.v:6273$1670_Y - connect \Y $and$ls180.v:6273$1671_Y + connect \A $and$ls180.v:6079$1528_Y + connect \B $eq$ls180.v:6079$1529_Y + connect \Y $and$ls180.v:6079$1530_Y end - attribute \src "ls180.v:6275.45-6275.98" - cell $and $and$ls180.v:6275$1672 + attribute \src "ls180.v:6081.45-6081.98" + cell $and $and$ls180.v:6081$1531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262574,43 +260862,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6275$1672_Y + connect \Y $and$ls180.v:6081$1531_Y end - attribute \src "ls180.v:6275.44-6275.148" - cell $and $and$ls180.v:6275$1674 + attribute \src "ls180.v:6081.44-6081.148" + cell $and $and$ls180.v:6081$1533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6275$1672_Y - connect \B $eq$ls180.v:6275$1673_Y - connect \Y $and$ls180.v:6275$1674_Y + connect \A $and$ls180.v:6081$1531_Y + connect \B $eq$ls180.v:6081$1532_Y + connect \Y $and$ls180.v:6081$1533_Y end - attribute \src "ls180.v:6276.45-6276.101" - cell $and $and$ls180.v:6276$1676 + attribute \src "ls180.v:6082.45-6082.101" + cell $and $and$ls180.v:6082$1535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6276$1675_Y - connect \Y $and$ls180.v:6276$1676_Y + connect \B $not$ls180.v:6082$1534_Y + connect \Y $and$ls180.v:6082$1535_Y end - attribute \src "ls180.v:6276.44-6276.151" - cell $and $and$ls180.v:6276$1678 + attribute \src "ls180.v:6082.44-6082.151" + cell $and $and$ls180.v:6082$1537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6276$1676_Y - connect \B $eq$ls180.v:6276$1677_Y - connect \Y $and$ls180.v:6276$1678_Y + connect \A $and$ls180.v:6082$1535_Y + connect \B $eq$ls180.v:6082$1536_Y + connect \Y $and$ls180.v:6082$1537_Y end - attribute \src "ls180.v:6278.45-6278.98" - cell $and $and$ls180.v:6278$1679 + attribute \src "ls180.v:6084.45-6084.98" + cell $and $and$ls180.v:6084$1538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262618,43 +260906,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6278$1679_Y + connect \Y $and$ls180.v:6084$1538_Y end - attribute \src "ls180.v:6278.44-6278.148" - cell $and $and$ls180.v:6278$1681 + attribute \src "ls180.v:6084.44-6084.148" + cell $and $and$ls180.v:6084$1540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6278$1679_Y - connect \B $eq$ls180.v:6278$1680_Y - connect \Y $and$ls180.v:6278$1681_Y + connect \A $and$ls180.v:6084$1538_Y + connect \B $eq$ls180.v:6084$1539_Y + connect \Y $and$ls180.v:6084$1540_Y end - attribute \src "ls180.v:6279.45-6279.101" - cell $and $and$ls180.v:6279$1683 + attribute \src "ls180.v:6085.45-6085.101" + cell $and $and$ls180.v:6085$1542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6279$1682_Y - connect \Y $and$ls180.v:6279$1683_Y + connect \B $not$ls180.v:6085$1541_Y + connect \Y $and$ls180.v:6085$1542_Y end - attribute \src "ls180.v:6279.44-6279.151" - cell $and $and$ls180.v:6279$1685 + attribute \src "ls180.v:6085.44-6085.151" + cell $and $and$ls180.v:6085$1544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6279$1683_Y - connect \B $eq$ls180.v:6279$1684_Y - connect \Y $and$ls180.v:6279$1685_Y + connect \A $and$ls180.v:6085$1542_Y + connect \B $eq$ls180.v:6085$1543_Y + connect \Y $and$ls180.v:6085$1544_Y end - attribute \src "ls180.v:6281.45-6281.98" - cell $and $and$ls180.v:6281$1686 + attribute \src "ls180.v:6087.45-6087.98" + cell $and $and$ls180.v:6087$1545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262662,43 +260950,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6281$1686_Y + connect \Y $and$ls180.v:6087$1545_Y end - attribute \src "ls180.v:6281.44-6281.148" - cell $and $and$ls180.v:6281$1688 + attribute \src "ls180.v:6087.44-6087.148" + cell $and $and$ls180.v:6087$1547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6281$1686_Y - connect \B $eq$ls180.v:6281$1687_Y - connect \Y $and$ls180.v:6281$1688_Y + connect \A $and$ls180.v:6087$1545_Y + connect \B $eq$ls180.v:6087$1546_Y + connect \Y $and$ls180.v:6087$1547_Y end - attribute \src "ls180.v:6282.45-6282.101" - cell $and $and$ls180.v:6282$1690 + attribute \src "ls180.v:6088.45-6088.101" + cell $and $and$ls180.v:6088$1549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6282$1689_Y - connect \Y $and$ls180.v:6282$1690_Y + connect \B $not$ls180.v:6088$1548_Y + connect \Y $and$ls180.v:6088$1549_Y end - attribute \src "ls180.v:6282.44-6282.151" - cell $and $and$ls180.v:6282$1692 + attribute \src "ls180.v:6088.44-6088.151" + cell $and $and$ls180.v:6088$1551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6282$1690_Y - connect \B $eq$ls180.v:6282$1691_Y - connect \Y $and$ls180.v:6282$1692_Y + connect \A $and$ls180.v:6088$1549_Y + connect \B $eq$ls180.v:6088$1550_Y + connect \Y $and$ls180.v:6088$1551_Y end - attribute \src "ls180.v:6284.36-6284.89" - cell $and $and$ls180.v:6284$1693 + attribute \src "ls180.v:6090.36-6090.89" + cell $and $and$ls180.v:6090$1552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262706,43 +260994,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6284$1693_Y + connect \Y $and$ls180.v:6090$1552_Y end - attribute \src "ls180.v:6284.35-6284.139" - cell $and $and$ls180.v:6284$1695 + attribute \src "ls180.v:6090.35-6090.139" + cell $and $and$ls180.v:6090$1554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6284$1693_Y - connect \B $eq$ls180.v:6284$1694_Y - connect \Y $and$ls180.v:6284$1695_Y + connect \A $and$ls180.v:6090$1552_Y + connect \B $eq$ls180.v:6090$1553_Y + connect \Y $and$ls180.v:6090$1554_Y end - attribute \src "ls180.v:6285.36-6285.92" - cell $and $and$ls180.v:6285$1697 + attribute \src "ls180.v:6091.36-6091.92" + cell $and $and$ls180.v:6091$1556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6285$1696_Y - connect \Y $and$ls180.v:6285$1697_Y + connect \B $not$ls180.v:6091$1555_Y + connect \Y $and$ls180.v:6091$1556_Y end - attribute \src "ls180.v:6285.35-6285.142" - cell $and $and$ls180.v:6285$1699 + attribute \src "ls180.v:6091.35-6091.142" + cell $and $and$ls180.v:6091$1558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6285$1697_Y - connect \B $eq$ls180.v:6285$1698_Y - connect \Y $and$ls180.v:6285$1699_Y + connect \A $and$ls180.v:6091$1556_Y + connect \B $eq$ls180.v:6091$1557_Y + connect \Y $and$ls180.v:6091$1558_Y end - attribute \src "ls180.v:6287.47-6287.100" - cell $and $and$ls180.v:6287$1700 + attribute \src "ls180.v:6093.47-6093.100" + cell $and $and$ls180.v:6093$1559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262750,43 +261038,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6287$1700_Y + connect \Y $and$ls180.v:6093$1559_Y end - attribute \src "ls180.v:6287.46-6287.150" - cell $and $and$ls180.v:6287$1702 + attribute \src "ls180.v:6093.46-6093.150" + cell $and $and$ls180.v:6093$1561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6287$1700_Y - connect \B $eq$ls180.v:6287$1701_Y - connect \Y $and$ls180.v:6287$1702_Y + connect \A $and$ls180.v:6093$1559_Y + connect \B $eq$ls180.v:6093$1560_Y + connect \Y $and$ls180.v:6093$1561_Y end - attribute \src "ls180.v:6288.47-6288.103" - cell $and $and$ls180.v:6288$1704 + attribute \src "ls180.v:6094.47-6094.103" + cell $and $and$ls180.v:6094$1563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6288$1703_Y - connect \Y $and$ls180.v:6288$1704_Y + connect \B $not$ls180.v:6094$1562_Y + connect \Y $and$ls180.v:6094$1563_Y end - attribute \src "ls180.v:6288.46-6288.153" - cell $and $and$ls180.v:6288$1706 + attribute \src "ls180.v:6094.46-6094.153" + cell $and $and$ls180.v:6094$1565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6288$1704_Y - connect \B $eq$ls180.v:6288$1705_Y - connect \Y $and$ls180.v:6288$1706_Y + connect \A $and$ls180.v:6094$1563_Y + connect \B $eq$ls180.v:6094$1564_Y + connect \Y $and$ls180.v:6094$1565_Y end - attribute \src "ls180.v:6290.47-6290.100" - cell $and $and$ls180.v:6290$1707 + attribute \src "ls180.v:6096.47-6096.100" + cell $and $and$ls180.v:6096$1566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262794,43 +261082,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6290$1707_Y + connect \Y $and$ls180.v:6096$1566_Y end - attribute \src "ls180.v:6290.46-6290.151" - cell $and $and$ls180.v:6290$1709 + attribute \src "ls180.v:6096.46-6096.151" + cell $and $and$ls180.v:6096$1568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6290$1707_Y - connect \B $eq$ls180.v:6290$1708_Y - connect \Y $and$ls180.v:6290$1709_Y + connect \A $and$ls180.v:6096$1566_Y + connect \B $eq$ls180.v:6096$1567_Y + connect \Y $and$ls180.v:6096$1568_Y end - attribute \src "ls180.v:6291.47-6291.103" - cell $and $and$ls180.v:6291$1711 + attribute \src "ls180.v:6097.47-6097.103" + cell $and $and$ls180.v:6097$1570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6291$1710_Y - connect \Y $and$ls180.v:6291$1711_Y + connect \B $not$ls180.v:6097$1569_Y + connect \Y $and$ls180.v:6097$1570_Y end - attribute \src "ls180.v:6291.46-6291.154" - cell $and $and$ls180.v:6291$1713 + attribute \src "ls180.v:6097.46-6097.154" + cell $and $and$ls180.v:6097$1572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6291$1711_Y - connect \B $eq$ls180.v:6291$1712_Y - connect \Y $and$ls180.v:6291$1713_Y + connect \A $and$ls180.v:6097$1570_Y + connect \B $eq$ls180.v:6097$1571_Y + connect \Y $and$ls180.v:6097$1572_Y end - attribute \src "ls180.v:6293.47-6293.100" - cell $and $and$ls180.v:6293$1714 + attribute \src "ls180.v:6099.47-6099.100" + cell $and $and$ls180.v:6099$1573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262838,43 +261126,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6293$1714_Y + connect \Y $and$ls180.v:6099$1573_Y end - attribute \src "ls180.v:6293.46-6293.151" - cell $and $and$ls180.v:6293$1716 + attribute \src "ls180.v:6099.46-6099.151" + cell $and $and$ls180.v:6099$1575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6293$1714_Y - connect \B $eq$ls180.v:6293$1715_Y - connect \Y $and$ls180.v:6293$1716_Y + connect \A $and$ls180.v:6099$1573_Y + connect \B $eq$ls180.v:6099$1574_Y + connect \Y $and$ls180.v:6099$1575_Y end - attribute \src "ls180.v:6294.47-6294.103" - cell $and $and$ls180.v:6294$1718 + attribute \src "ls180.v:6100.47-6100.103" + cell $and $and$ls180.v:6100$1577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6294$1717_Y - connect \Y $and$ls180.v:6294$1718_Y + connect \B $not$ls180.v:6100$1576_Y + connect \Y $and$ls180.v:6100$1577_Y end - attribute \src "ls180.v:6294.46-6294.154" - cell $and $and$ls180.v:6294$1720 + attribute \src "ls180.v:6100.46-6100.154" + cell $and $and$ls180.v:6100$1579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6294$1718_Y - connect \B $eq$ls180.v:6294$1719_Y - connect \Y $and$ls180.v:6294$1720_Y + connect \A $and$ls180.v:6100$1577_Y + connect \B $eq$ls180.v:6100$1578_Y + connect \Y $and$ls180.v:6100$1579_Y end - attribute \src "ls180.v:6296.47-6296.100" - cell $and $and$ls180.v:6296$1721 + attribute \src "ls180.v:6102.47-6102.100" + cell $and $and$ls180.v:6102$1580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262882,43 +261170,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6296$1721_Y + connect \Y $and$ls180.v:6102$1580_Y end - attribute \src "ls180.v:6296.46-6296.151" - cell $and $and$ls180.v:6296$1723 + attribute \src "ls180.v:6102.46-6102.151" + cell $and $and$ls180.v:6102$1582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6296$1721_Y - connect \B $eq$ls180.v:6296$1722_Y - connect \Y $and$ls180.v:6296$1723_Y + connect \A $and$ls180.v:6102$1580_Y + connect \B $eq$ls180.v:6102$1581_Y + connect \Y $and$ls180.v:6102$1582_Y end - attribute \src "ls180.v:6297.47-6297.103" - cell $and $and$ls180.v:6297$1725 + attribute \src "ls180.v:6103.47-6103.103" + cell $and $and$ls180.v:6103$1584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6297$1724_Y - connect \Y $and$ls180.v:6297$1725_Y + connect \B $not$ls180.v:6103$1583_Y + connect \Y $and$ls180.v:6103$1584_Y end - attribute \src "ls180.v:6297.46-6297.154" - cell $and $and$ls180.v:6297$1727 + attribute \src "ls180.v:6103.46-6103.154" + cell $and $and$ls180.v:6103$1586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6297$1725_Y - connect \B $eq$ls180.v:6297$1726_Y - connect \Y $and$ls180.v:6297$1727_Y + connect \A $and$ls180.v:6103$1584_Y + connect \B $eq$ls180.v:6103$1585_Y + connect \Y $and$ls180.v:6103$1586_Y end - attribute \src "ls180.v:6299.47-6299.100" - cell $and $and$ls180.v:6299$1728 + attribute \src "ls180.v:6105.47-6105.100" + cell $and $and$ls180.v:6105$1587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262926,43 +261214,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6299$1728_Y + connect \Y $and$ls180.v:6105$1587_Y end - attribute \src "ls180.v:6299.46-6299.151" - cell $and $and$ls180.v:6299$1730 + attribute \src "ls180.v:6105.46-6105.151" + cell $and $and$ls180.v:6105$1589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6299$1728_Y - connect \B $eq$ls180.v:6299$1729_Y - connect \Y $and$ls180.v:6299$1730_Y + connect \A $and$ls180.v:6105$1587_Y + connect \B $eq$ls180.v:6105$1588_Y + connect \Y $and$ls180.v:6105$1589_Y end - attribute \src "ls180.v:6300.47-6300.103" - cell $and $and$ls180.v:6300$1732 + attribute \src "ls180.v:6106.47-6106.103" + cell $and $and$ls180.v:6106$1591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6300$1731_Y - connect \Y $and$ls180.v:6300$1732_Y + connect \B $not$ls180.v:6106$1590_Y + connect \Y $and$ls180.v:6106$1591_Y end - attribute \src "ls180.v:6300.46-6300.154" - cell $and $and$ls180.v:6300$1734 + attribute \src "ls180.v:6106.46-6106.154" + cell $and $and$ls180.v:6106$1593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6300$1732_Y - connect \B $eq$ls180.v:6300$1733_Y - connect \Y $and$ls180.v:6300$1734_Y + connect \A $and$ls180.v:6106$1591_Y + connect \B $eq$ls180.v:6106$1592_Y + connect \Y $and$ls180.v:6106$1593_Y end - attribute \src "ls180.v:6302.47-6302.100" - cell $and $and$ls180.v:6302$1735 + attribute \src "ls180.v:6108.47-6108.100" + cell $and $and$ls180.v:6108$1594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -262970,43 +261258,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6302$1735_Y + connect \Y $and$ls180.v:6108$1594_Y end - attribute \src "ls180.v:6302.46-6302.151" - cell $and $and$ls180.v:6302$1737 + attribute \src "ls180.v:6108.46-6108.151" + cell $and $and$ls180.v:6108$1596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6302$1735_Y - connect \B $eq$ls180.v:6302$1736_Y - connect \Y $and$ls180.v:6302$1737_Y + connect \A $and$ls180.v:6108$1594_Y + connect \B $eq$ls180.v:6108$1595_Y + connect \Y $and$ls180.v:6108$1596_Y end - attribute \src "ls180.v:6303.47-6303.103" - cell $and $and$ls180.v:6303$1739 + attribute \src "ls180.v:6109.47-6109.103" + cell $and $and$ls180.v:6109$1598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6303$1738_Y - connect \Y $and$ls180.v:6303$1739_Y + connect \B $not$ls180.v:6109$1597_Y + connect \Y $and$ls180.v:6109$1598_Y end - attribute \src "ls180.v:6303.46-6303.154" - cell $and $and$ls180.v:6303$1741 + attribute \src "ls180.v:6109.46-6109.154" + cell $and $and$ls180.v:6109$1600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6303$1739_Y - connect \B $eq$ls180.v:6303$1740_Y - connect \Y $and$ls180.v:6303$1741_Y + connect \A $and$ls180.v:6109$1598_Y + connect \B $eq$ls180.v:6109$1599_Y + connect \Y $and$ls180.v:6109$1600_Y end - attribute \src "ls180.v:6305.46-6305.99" - cell $and $and$ls180.v:6305$1742 + attribute \src "ls180.v:6111.46-6111.99" + cell $and $and$ls180.v:6111$1601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263014,43 +261302,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6305$1742_Y + connect \Y $and$ls180.v:6111$1601_Y end - attribute \src "ls180.v:6305.45-6305.150" - cell $and $and$ls180.v:6305$1744 + attribute \src "ls180.v:6111.45-6111.150" + cell $and $and$ls180.v:6111$1603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6305$1742_Y - connect \B $eq$ls180.v:6305$1743_Y - connect \Y $and$ls180.v:6305$1744_Y + connect \A $and$ls180.v:6111$1601_Y + connect \B $eq$ls180.v:6111$1602_Y + connect \Y $and$ls180.v:6111$1603_Y end - attribute \src "ls180.v:6306.46-6306.102" - cell $and $and$ls180.v:6306$1746 + attribute \src "ls180.v:6112.46-6112.102" + cell $and $and$ls180.v:6112$1605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6306$1745_Y - connect \Y $and$ls180.v:6306$1746_Y + connect \B $not$ls180.v:6112$1604_Y + connect \Y $and$ls180.v:6112$1605_Y end - attribute \src "ls180.v:6306.45-6306.153" - cell $and $and$ls180.v:6306$1748 + attribute \src "ls180.v:6112.45-6112.153" + cell $and $and$ls180.v:6112$1607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6306$1746_Y - connect \B $eq$ls180.v:6306$1747_Y - connect \Y $and$ls180.v:6306$1748_Y + connect \A $and$ls180.v:6112$1605_Y + connect \B $eq$ls180.v:6112$1606_Y + connect \Y $and$ls180.v:6112$1607_Y end - attribute \src "ls180.v:6308.46-6308.99" - cell $and $and$ls180.v:6308$1749 + attribute \src "ls180.v:6114.46-6114.99" + cell $and $and$ls180.v:6114$1608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263058,43 +261346,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6308$1749_Y + connect \Y $and$ls180.v:6114$1608_Y end - attribute \src "ls180.v:6308.45-6308.150" - cell $and $and$ls180.v:6308$1751 + attribute \src "ls180.v:6114.45-6114.150" + cell $and $and$ls180.v:6114$1610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6308$1749_Y - connect \B $eq$ls180.v:6308$1750_Y - connect \Y $and$ls180.v:6308$1751_Y + connect \A $and$ls180.v:6114$1608_Y + connect \B $eq$ls180.v:6114$1609_Y + connect \Y $and$ls180.v:6114$1610_Y end - attribute \src "ls180.v:6309.46-6309.102" - cell $and $and$ls180.v:6309$1753 + attribute \src "ls180.v:6115.46-6115.102" + cell $and $and$ls180.v:6115$1612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6309$1752_Y - connect \Y $and$ls180.v:6309$1753_Y + connect \B $not$ls180.v:6115$1611_Y + connect \Y $and$ls180.v:6115$1612_Y end - attribute \src "ls180.v:6309.45-6309.153" - cell $and $and$ls180.v:6309$1755 + attribute \src "ls180.v:6115.45-6115.153" + cell $and $and$ls180.v:6115$1614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6309$1753_Y - connect \B $eq$ls180.v:6309$1754_Y - connect \Y $and$ls180.v:6309$1755_Y + connect \A $and$ls180.v:6115$1612_Y + connect \B $eq$ls180.v:6115$1613_Y + connect \Y $and$ls180.v:6115$1614_Y end - attribute \src "ls180.v:6311.46-6311.99" - cell $and $and$ls180.v:6311$1756 + attribute \src "ls180.v:6117.46-6117.99" + cell $and $and$ls180.v:6117$1615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263102,43 +261390,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6311$1756_Y + connect \Y $and$ls180.v:6117$1615_Y end - attribute \src "ls180.v:6311.45-6311.150" - cell $and $and$ls180.v:6311$1758 + attribute \src "ls180.v:6117.45-6117.150" + cell $and $and$ls180.v:6117$1617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6311$1756_Y - connect \B $eq$ls180.v:6311$1757_Y - connect \Y $and$ls180.v:6311$1758_Y + connect \A $and$ls180.v:6117$1615_Y + connect \B $eq$ls180.v:6117$1616_Y + connect \Y $and$ls180.v:6117$1617_Y end - attribute \src "ls180.v:6312.46-6312.102" - cell $and $and$ls180.v:6312$1760 + attribute \src "ls180.v:6118.46-6118.102" + cell $and $and$ls180.v:6118$1619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6312$1759_Y - connect \Y $and$ls180.v:6312$1760_Y + connect \B $not$ls180.v:6118$1618_Y + connect \Y $and$ls180.v:6118$1619_Y end - attribute \src "ls180.v:6312.45-6312.153" - cell $and $and$ls180.v:6312$1762 + attribute \src "ls180.v:6118.45-6118.153" + cell $and $and$ls180.v:6118$1621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6312$1760_Y - connect \B $eq$ls180.v:6312$1761_Y - connect \Y $and$ls180.v:6312$1762_Y + connect \A $and$ls180.v:6118$1619_Y + connect \B $eq$ls180.v:6118$1620_Y + connect \Y $and$ls180.v:6118$1621_Y end - attribute \src "ls180.v:6314.46-6314.99" - cell $and $and$ls180.v:6314$1763 + attribute \src "ls180.v:6120.46-6120.99" + cell $and $and$ls180.v:6120$1622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263146,43 +261434,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6314$1763_Y + connect \Y $and$ls180.v:6120$1622_Y end - attribute \src "ls180.v:6314.45-6314.150" - cell $and $and$ls180.v:6314$1765 + attribute \src "ls180.v:6120.45-6120.150" + cell $and $and$ls180.v:6120$1624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6314$1763_Y - connect \B $eq$ls180.v:6314$1764_Y - connect \Y $and$ls180.v:6314$1765_Y + connect \A $and$ls180.v:6120$1622_Y + connect \B $eq$ls180.v:6120$1623_Y + connect \Y $and$ls180.v:6120$1624_Y end - attribute \src "ls180.v:6315.46-6315.102" - cell $and $and$ls180.v:6315$1767 + attribute \src "ls180.v:6121.46-6121.102" + cell $and $and$ls180.v:6121$1626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6315$1766_Y - connect \Y $and$ls180.v:6315$1767_Y + connect \B $not$ls180.v:6121$1625_Y + connect \Y $and$ls180.v:6121$1626_Y end - attribute \src "ls180.v:6315.45-6315.153" - cell $and $and$ls180.v:6315$1769 + attribute \src "ls180.v:6121.45-6121.153" + cell $and $and$ls180.v:6121$1628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6315$1767_Y - connect \B $eq$ls180.v:6315$1768_Y - connect \Y $and$ls180.v:6315$1769_Y + connect \A $and$ls180.v:6121$1626_Y + connect \B $eq$ls180.v:6121$1627_Y + connect \Y $and$ls180.v:6121$1628_Y end - attribute \src "ls180.v:6317.46-6317.99" - cell $and $and$ls180.v:6317$1770 + attribute \src "ls180.v:6123.46-6123.99" + cell $and $and$ls180.v:6123$1629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263190,43 +261478,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6317$1770_Y + connect \Y $and$ls180.v:6123$1629_Y end - attribute \src "ls180.v:6317.45-6317.150" - cell $and $and$ls180.v:6317$1772 + attribute \src "ls180.v:6123.45-6123.150" + cell $and $and$ls180.v:6123$1631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6317$1770_Y - connect \B $eq$ls180.v:6317$1771_Y - connect \Y $and$ls180.v:6317$1772_Y + connect \A $and$ls180.v:6123$1629_Y + connect \B $eq$ls180.v:6123$1630_Y + connect \Y $and$ls180.v:6123$1631_Y end - attribute \src "ls180.v:6318.46-6318.102" - cell $and $and$ls180.v:6318$1774 + attribute \src "ls180.v:6124.46-6124.102" + cell $and $and$ls180.v:6124$1633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6318$1773_Y - connect \Y $and$ls180.v:6318$1774_Y + connect \B $not$ls180.v:6124$1632_Y + connect \Y $and$ls180.v:6124$1633_Y end - attribute \src "ls180.v:6318.45-6318.153" - cell $and $and$ls180.v:6318$1776 + attribute \src "ls180.v:6124.45-6124.153" + cell $and $and$ls180.v:6124$1635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6318$1774_Y - connect \B $eq$ls180.v:6318$1775_Y - connect \Y $and$ls180.v:6318$1776_Y + connect \A $and$ls180.v:6124$1633_Y + connect \B $eq$ls180.v:6124$1634_Y + connect \Y $and$ls180.v:6124$1635_Y end - attribute \src "ls180.v:6320.46-6320.99" - cell $and $and$ls180.v:6320$1777 + attribute \src "ls180.v:6126.46-6126.99" + cell $and $and$ls180.v:6126$1636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263234,43 +261522,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6320$1777_Y + connect \Y $and$ls180.v:6126$1636_Y end - attribute \src "ls180.v:6320.45-6320.150" - cell $and $and$ls180.v:6320$1779 + attribute \src "ls180.v:6126.45-6126.150" + cell $and $and$ls180.v:6126$1638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6320$1777_Y - connect \B $eq$ls180.v:6320$1778_Y - connect \Y $and$ls180.v:6320$1779_Y + connect \A $and$ls180.v:6126$1636_Y + connect \B $eq$ls180.v:6126$1637_Y + connect \Y $and$ls180.v:6126$1638_Y end - attribute \src "ls180.v:6321.46-6321.102" - cell $and $and$ls180.v:6321$1781 + attribute \src "ls180.v:6127.46-6127.102" + cell $and $and$ls180.v:6127$1640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6321$1780_Y - connect \Y $and$ls180.v:6321$1781_Y + connect \B $not$ls180.v:6127$1639_Y + connect \Y $and$ls180.v:6127$1640_Y end - attribute \src "ls180.v:6321.45-6321.153" - cell $and $and$ls180.v:6321$1783 + attribute \src "ls180.v:6127.45-6127.153" + cell $and $and$ls180.v:6127$1642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6321$1781_Y - connect \B $eq$ls180.v:6321$1782_Y - connect \Y $and$ls180.v:6321$1783_Y + connect \A $and$ls180.v:6127$1640_Y + connect \B $eq$ls180.v:6127$1641_Y + connect \Y $and$ls180.v:6127$1642_Y end - attribute \src "ls180.v:6323.46-6323.99" - cell $and $and$ls180.v:6323$1784 + attribute \src "ls180.v:6129.46-6129.99" + cell $and $and$ls180.v:6129$1643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263278,43 +261566,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6323$1784_Y + connect \Y $and$ls180.v:6129$1643_Y end - attribute \src "ls180.v:6323.45-6323.150" - cell $and $and$ls180.v:6323$1786 + attribute \src "ls180.v:6129.45-6129.150" + cell $and $and$ls180.v:6129$1645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6323$1784_Y - connect \B $eq$ls180.v:6323$1785_Y - connect \Y $and$ls180.v:6323$1786_Y + connect \A $and$ls180.v:6129$1643_Y + connect \B $eq$ls180.v:6129$1644_Y + connect \Y $and$ls180.v:6129$1645_Y end - attribute \src "ls180.v:6324.46-6324.102" - cell $and $and$ls180.v:6324$1788 + attribute \src "ls180.v:6130.46-6130.102" + cell $and $and$ls180.v:6130$1647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6324$1787_Y - connect \Y $and$ls180.v:6324$1788_Y + connect \B $not$ls180.v:6130$1646_Y + connect \Y $and$ls180.v:6130$1647_Y end - attribute \src "ls180.v:6324.45-6324.153" - cell $and $and$ls180.v:6324$1790 + attribute \src "ls180.v:6130.45-6130.153" + cell $and $and$ls180.v:6130$1649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6324$1788_Y - connect \B $eq$ls180.v:6324$1789_Y - connect \Y $and$ls180.v:6324$1790_Y + connect \A $and$ls180.v:6130$1647_Y + connect \B $eq$ls180.v:6130$1648_Y + connect \Y $and$ls180.v:6130$1649_Y end - attribute \src "ls180.v:6326.46-6326.99" - cell $and $and$ls180.v:6326$1791 + attribute \src "ls180.v:6132.46-6132.99" + cell $and $and$ls180.v:6132$1650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263322,43 +261610,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6326$1791_Y + connect \Y $and$ls180.v:6132$1650_Y end - attribute \src "ls180.v:6326.45-6326.150" - cell $and $and$ls180.v:6326$1793 + attribute \src "ls180.v:6132.45-6132.150" + cell $and $and$ls180.v:6132$1652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6326$1791_Y - connect \B $eq$ls180.v:6326$1792_Y - connect \Y $and$ls180.v:6326$1793_Y + connect \A $and$ls180.v:6132$1650_Y + connect \B $eq$ls180.v:6132$1651_Y + connect \Y $and$ls180.v:6132$1652_Y end - attribute \src "ls180.v:6327.46-6327.102" - cell $and $and$ls180.v:6327$1795 + attribute \src "ls180.v:6133.46-6133.102" + cell $and $and$ls180.v:6133$1654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6327$1794_Y - connect \Y $and$ls180.v:6327$1795_Y + connect \B $not$ls180.v:6133$1653_Y + connect \Y $and$ls180.v:6133$1654_Y end - attribute \src "ls180.v:6327.45-6327.153" - cell $and $and$ls180.v:6327$1797 + attribute \src "ls180.v:6133.45-6133.153" + cell $and $and$ls180.v:6133$1656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6327$1795_Y - connect \B $eq$ls180.v:6327$1796_Y - connect \Y $and$ls180.v:6327$1797_Y + connect \A $and$ls180.v:6133$1654_Y + connect \B $eq$ls180.v:6133$1655_Y + connect \Y $and$ls180.v:6133$1656_Y end - attribute \src "ls180.v:6329.46-6329.99" - cell $and $and$ls180.v:6329$1798 + attribute \src "ls180.v:6135.46-6135.99" + cell $and $and$ls180.v:6135$1657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263366,43 +261654,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6329$1798_Y + connect \Y $and$ls180.v:6135$1657_Y end - attribute \src "ls180.v:6329.45-6329.150" - cell $and $and$ls180.v:6329$1800 + attribute \src "ls180.v:6135.45-6135.150" + cell $and $and$ls180.v:6135$1659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6329$1798_Y - connect \B $eq$ls180.v:6329$1799_Y - connect \Y $and$ls180.v:6329$1800_Y + connect \A $and$ls180.v:6135$1657_Y + connect \B $eq$ls180.v:6135$1658_Y + connect \Y $and$ls180.v:6135$1659_Y end - attribute \src "ls180.v:6330.46-6330.102" - cell $and $and$ls180.v:6330$1802 + attribute \src "ls180.v:6136.46-6136.102" + cell $and $and$ls180.v:6136$1661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6330$1801_Y - connect \Y $and$ls180.v:6330$1802_Y + connect \B $not$ls180.v:6136$1660_Y + connect \Y $and$ls180.v:6136$1661_Y end - attribute \src "ls180.v:6330.45-6330.153" - cell $and $and$ls180.v:6330$1804 + attribute \src "ls180.v:6136.45-6136.153" + cell $and $and$ls180.v:6136$1663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6330$1802_Y - connect \B $eq$ls180.v:6330$1803_Y - connect \Y $and$ls180.v:6330$1804_Y + connect \A $and$ls180.v:6136$1661_Y + connect \B $eq$ls180.v:6136$1662_Y + connect \Y $and$ls180.v:6136$1663_Y end - attribute \src "ls180.v:6332.46-6332.99" - cell $and $and$ls180.v:6332$1805 + attribute \src "ls180.v:6138.46-6138.99" + cell $and $and$ls180.v:6138$1664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263410,43 +261698,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6332$1805_Y + connect \Y $and$ls180.v:6138$1664_Y end - attribute \src "ls180.v:6332.45-6332.150" - cell $and $and$ls180.v:6332$1807 + attribute \src "ls180.v:6138.45-6138.150" + cell $and $and$ls180.v:6138$1666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6332$1805_Y - connect \B $eq$ls180.v:6332$1806_Y - connect \Y $and$ls180.v:6332$1807_Y + connect \A $and$ls180.v:6138$1664_Y + connect \B $eq$ls180.v:6138$1665_Y + connect \Y $and$ls180.v:6138$1666_Y end - attribute \src "ls180.v:6333.46-6333.102" - cell $and $and$ls180.v:6333$1809 + attribute \src "ls180.v:6139.46-6139.102" + cell $and $and$ls180.v:6139$1668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6333$1808_Y - connect \Y $and$ls180.v:6333$1809_Y + connect \B $not$ls180.v:6139$1667_Y + connect \Y $and$ls180.v:6139$1668_Y end - attribute \src "ls180.v:6333.45-6333.153" - cell $and $and$ls180.v:6333$1811 + attribute \src "ls180.v:6139.45-6139.153" + cell $and $and$ls180.v:6139$1670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6333$1809_Y - connect \B $eq$ls180.v:6333$1810_Y - connect \Y $and$ls180.v:6333$1811_Y + connect \A $and$ls180.v:6139$1668_Y + connect \B $eq$ls180.v:6139$1669_Y + connect \Y $and$ls180.v:6139$1670_Y end - attribute \src "ls180.v:6335.42-6335.95" - cell $and $and$ls180.v:6335$1812 + attribute \src "ls180.v:6141.42-6141.95" + cell $and $and$ls180.v:6141$1671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263454,43 +261742,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6335$1812_Y + connect \Y $and$ls180.v:6141$1671_Y end - attribute \src "ls180.v:6335.41-6335.146" - cell $and $and$ls180.v:6335$1814 + attribute \src "ls180.v:6141.41-6141.146" + cell $and $and$ls180.v:6141$1673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6335$1812_Y - connect \B $eq$ls180.v:6335$1813_Y - connect \Y $and$ls180.v:6335$1814_Y + connect \A $and$ls180.v:6141$1671_Y + connect \B $eq$ls180.v:6141$1672_Y + connect \Y $and$ls180.v:6141$1673_Y end - attribute \src "ls180.v:6336.42-6336.98" - cell $and $and$ls180.v:6336$1816 + attribute \src "ls180.v:6142.42-6142.98" + cell $and $and$ls180.v:6142$1675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6336$1815_Y - connect \Y $and$ls180.v:6336$1816_Y + connect \B $not$ls180.v:6142$1674_Y + connect \Y $and$ls180.v:6142$1675_Y end - attribute \src "ls180.v:6336.41-6336.149" - cell $and $and$ls180.v:6336$1818 + attribute \src "ls180.v:6142.41-6142.149" + cell $and $and$ls180.v:6142$1677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6336$1816_Y - connect \B $eq$ls180.v:6336$1817_Y - connect \Y $and$ls180.v:6336$1818_Y + connect \A $and$ls180.v:6142$1675_Y + connect \B $eq$ls180.v:6142$1676_Y + connect \Y $and$ls180.v:6142$1677_Y end - attribute \src "ls180.v:6338.43-6338.96" - cell $and $and$ls180.v:6338$1819 + attribute \src "ls180.v:6144.43-6144.96" + cell $and $and$ls180.v:6144$1678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263498,43 +261786,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6338$1819_Y + connect \Y $and$ls180.v:6144$1678_Y end - attribute \src "ls180.v:6338.42-6338.147" - cell $and $and$ls180.v:6338$1821 + attribute \src "ls180.v:6144.42-6144.147" + cell $and $and$ls180.v:6144$1680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6338$1819_Y - connect \B $eq$ls180.v:6338$1820_Y - connect \Y $and$ls180.v:6338$1821_Y + connect \A $and$ls180.v:6144$1678_Y + connect \B $eq$ls180.v:6144$1679_Y + connect \Y $and$ls180.v:6144$1680_Y end - attribute \src "ls180.v:6339.43-6339.99" - cell $and $and$ls180.v:6339$1823 + attribute \src "ls180.v:6145.43-6145.99" + cell $and $and$ls180.v:6145$1682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6339$1822_Y - connect \Y $and$ls180.v:6339$1823_Y + connect \B $not$ls180.v:6145$1681_Y + connect \Y $and$ls180.v:6145$1682_Y end - attribute \src "ls180.v:6339.42-6339.150" - cell $and $and$ls180.v:6339$1825 + attribute \src "ls180.v:6145.42-6145.150" + cell $and $and$ls180.v:6145$1684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6339$1823_Y - connect \B $eq$ls180.v:6339$1824_Y - connect \Y $and$ls180.v:6339$1825_Y + connect \A $and$ls180.v:6145$1682_Y + connect \B $eq$ls180.v:6145$1683_Y + connect \Y $and$ls180.v:6145$1684_Y end - attribute \src "ls180.v:6341.46-6341.99" - cell $and $and$ls180.v:6341$1826 + attribute \src "ls180.v:6147.46-6147.99" + cell $and $and$ls180.v:6147$1685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263542,43 +261830,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6341$1826_Y + connect \Y $and$ls180.v:6147$1685_Y end - attribute \src "ls180.v:6341.45-6341.150" - cell $and $and$ls180.v:6341$1828 + attribute \src "ls180.v:6147.45-6147.150" + cell $and $and$ls180.v:6147$1687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6341$1826_Y - connect \B $eq$ls180.v:6341$1827_Y - connect \Y $and$ls180.v:6341$1828_Y + connect \A $and$ls180.v:6147$1685_Y + connect \B $eq$ls180.v:6147$1686_Y + connect \Y $and$ls180.v:6147$1687_Y end - attribute \src "ls180.v:6342.46-6342.102" - cell $and $and$ls180.v:6342$1830 + attribute \src "ls180.v:6148.46-6148.102" + cell $and $and$ls180.v:6148$1689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6342$1829_Y - connect \Y $and$ls180.v:6342$1830_Y + connect \B $not$ls180.v:6148$1688_Y + connect \Y $and$ls180.v:6148$1689_Y end - attribute \src "ls180.v:6342.45-6342.153" - cell $and $and$ls180.v:6342$1832 + attribute \src "ls180.v:6148.45-6148.153" + cell $and $and$ls180.v:6148$1691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6342$1830_Y - connect \B $eq$ls180.v:6342$1831_Y - connect \Y $and$ls180.v:6342$1832_Y + connect \A $and$ls180.v:6148$1689_Y + connect \B $eq$ls180.v:6148$1690_Y + connect \Y $and$ls180.v:6148$1691_Y end - attribute \src "ls180.v:6344.46-6344.99" - cell $and $and$ls180.v:6344$1833 + attribute \src "ls180.v:6150.46-6150.99" + cell $and $and$ls180.v:6150$1692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263586,43 +261874,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6344$1833_Y + connect \Y $and$ls180.v:6150$1692_Y end - attribute \src "ls180.v:6344.45-6344.150" - cell $and $and$ls180.v:6344$1835 + attribute \src "ls180.v:6150.45-6150.150" + cell $and $and$ls180.v:6150$1694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6344$1833_Y - connect \B $eq$ls180.v:6344$1834_Y - connect \Y $and$ls180.v:6344$1835_Y + connect \A $and$ls180.v:6150$1692_Y + connect \B $eq$ls180.v:6150$1693_Y + connect \Y $and$ls180.v:6150$1694_Y end - attribute \src "ls180.v:6345.46-6345.102" - cell $and $and$ls180.v:6345$1837 + attribute \src "ls180.v:6151.46-6151.102" + cell $and $and$ls180.v:6151$1696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6345$1836_Y - connect \Y $and$ls180.v:6345$1837_Y + connect \B $not$ls180.v:6151$1695_Y + connect \Y $and$ls180.v:6151$1696_Y end - attribute \src "ls180.v:6345.45-6345.153" - cell $and $and$ls180.v:6345$1839 + attribute \src "ls180.v:6151.45-6151.153" + cell $and $and$ls180.v:6151$1698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6345$1837_Y - connect \B $eq$ls180.v:6345$1838_Y - connect \Y $and$ls180.v:6345$1839_Y + connect \A $and$ls180.v:6151$1696_Y + connect \B $eq$ls180.v:6151$1697_Y + connect \Y $and$ls180.v:6151$1698_Y end - attribute \src "ls180.v:6347.45-6347.98" - cell $and $and$ls180.v:6347$1840 + attribute \src "ls180.v:6153.45-6153.98" + cell $and $and$ls180.v:6153$1699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263630,43 +261918,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6347$1840_Y + connect \Y $and$ls180.v:6153$1699_Y end - attribute \src "ls180.v:6347.44-6347.149" - cell $and $and$ls180.v:6347$1842 + attribute \src "ls180.v:6153.44-6153.149" + cell $and $and$ls180.v:6153$1701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6347$1840_Y - connect \B $eq$ls180.v:6347$1841_Y - connect \Y $and$ls180.v:6347$1842_Y + connect \A $and$ls180.v:6153$1699_Y + connect \B $eq$ls180.v:6153$1700_Y + connect \Y $and$ls180.v:6153$1701_Y end - attribute \src "ls180.v:6348.45-6348.101" - cell $and $and$ls180.v:6348$1844 + attribute \src "ls180.v:6154.45-6154.101" + cell $and $and$ls180.v:6154$1703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6348$1843_Y - connect \Y $and$ls180.v:6348$1844_Y + connect \B $not$ls180.v:6154$1702_Y + connect \Y $and$ls180.v:6154$1703_Y end - attribute \src "ls180.v:6348.44-6348.152" - cell $and $and$ls180.v:6348$1846 + attribute \src "ls180.v:6154.44-6154.152" + cell $and $and$ls180.v:6154$1705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6348$1844_Y - connect \B $eq$ls180.v:6348$1845_Y - connect \Y $and$ls180.v:6348$1846_Y + connect \A $and$ls180.v:6154$1703_Y + connect \B $eq$ls180.v:6154$1704_Y + connect \Y $and$ls180.v:6154$1705_Y end - attribute \src "ls180.v:6350.45-6350.98" - cell $and $and$ls180.v:6350$1847 + attribute \src "ls180.v:6156.45-6156.98" + cell $and $and$ls180.v:6156$1706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263674,43 +261962,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6350$1847_Y + connect \Y $and$ls180.v:6156$1706_Y end - attribute \src "ls180.v:6350.44-6350.149" - cell $and $and$ls180.v:6350$1849 + attribute \src "ls180.v:6156.44-6156.149" + cell $and $and$ls180.v:6156$1708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6350$1847_Y - connect \B $eq$ls180.v:6350$1848_Y - connect \Y $and$ls180.v:6350$1849_Y + connect \A $and$ls180.v:6156$1706_Y + connect \B $eq$ls180.v:6156$1707_Y + connect \Y $and$ls180.v:6156$1708_Y end - attribute \src "ls180.v:6351.45-6351.101" - cell $and $and$ls180.v:6351$1851 + attribute \src "ls180.v:6157.45-6157.101" + cell $and $and$ls180.v:6157$1710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6351$1850_Y - connect \Y $and$ls180.v:6351$1851_Y + connect \B $not$ls180.v:6157$1709_Y + connect \Y $and$ls180.v:6157$1710_Y end - attribute \src "ls180.v:6351.44-6351.152" - cell $and $and$ls180.v:6351$1853 + attribute \src "ls180.v:6157.44-6157.152" + cell $and $and$ls180.v:6157$1712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6351$1851_Y - connect \B $eq$ls180.v:6351$1852_Y - connect \Y $and$ls180.v:6351$1853_Y + connect \A $and$ls180.v:6157$1710_Y + connect \B $eq$ls180.v:6157$1711_Y + connect \Y $and$ls180.v:6157$1712_Y end - attribute \src "ls180.v:6353.45-6353.98" - cell $and $and$ls180.v:6353$1854 + attribute \src "ls180.v:6159.45-6159.98" + cell $and $and$ls180.v:6159$1713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263718,43 +262006,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6353$1854_Y + connect \Y $and$ls180.v:6159$1713_Y end - attribute \src "ls180.v:6353.44-6353.149" - cell $and $and$ls180.v:6353$1856 + attribute \src "ls180.v:6159.44-6159.149" + cell $and $and$ls180.v:6159$1715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6353$1854_Y - connect \B $eq$ls180.v:6353$1855_Y - connect \Y $and$ls180.v:6353$1856_Y + connect \A $and$ls180.v:6159$1713_Y + connect \B $eq$ls180.v:6159$1714_Y + connect \Y $and$ls180.v:6159$1715_Y end - attribute \src "ls180.v:6354.45-6354.101" - cell $and $and$ls180.v:6354$1858 + attribute \src "ls180.v:6160.45-6160.101" + cell $and $and$ls180.v:6160$1717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6354$1857_Y - connect \Y $and$ls180.v:6354$1858_Y + connect \B $not$ls180.v:6160$1716_Y + connect \Y $and$ls180.v:6160$1717_Y end - attribute \src "ls180.v:6354.44-6354.152" - cell $and $and$ls180.v:6354$1860 + attribute \src "ls180.v:6160.44-6160.152" + cell $and $and$ls180.v:6160$1719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6354$1858_Y - connect \B $eq$ls180.v:6354$1859_Y - connect \Y $and$ls180.v:6354$1860_Y + connect \A $and$ls180.v:6160$1717_Y + connect \B $eq$ls180.v:6160$1718_Y + connect \Y $and$ls180.v:6160$1719_Y end - attribute \src "ls180.v:6356.45-6356.98" - cell $and $and$ls180.v:6356$1861 + attribute \src "ls180.v:6162.45-6162.98" + cell $and $and$ls180.v:6162$1720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263762,43 +262050,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6356$1861_Y + connect \Y $and$ls180.v:6162$1720_Y end - attribute \src "ls180.v:6356.44-6356.149" - cell $and $and$ls180.v:6356$1863 + attribute \src "ls180.v:6162.44-6162.149" + cell $and $and$ls180.v:6162$1722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6356$1861_Y - connect \B $eq$ls180.v:6356$1862_Y - connect \Y $and$ls180.v:6356$1863_Y + connect \A $and$ls180.v:6162$1720_Y + connect \B $eq$ls180.v:6162$1721_Y + connect \Y $and$ls180.v:6162$1722_Y end - attribute \src "ls180.v:6357.45-6357.101" - cell $and $and$ls180.v:6357$1865 + attribute \src "ls180.v:6163.45-6163.101" + cell $and $and$ls180.v:6163$1724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6357$1864_Y - connect \Y $and$ls180.v:6357$1865_Y + connect \B $not$ls180.v:6163$1723_Y + connect \Y $and$ls180.v:6163$1724_Y end - attribute \src "ls180.v:6357.44-6357.152" - cell $and $and$ls180.v:6357$1867 + attribute \src "ls180.v:6163.44-6163.152" + cell $and $and$ls180.v:6163$1726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6357$1865_Y - connect \B $eq$ls180.v:6357$1866_Y - connect \Y $and$ls180.v:6357$1867_Y + connect \A $and$ls180.v:6163$1724_Y + connect \B $eq$ls180.v:6163$1725_Y + connect \Y $and$ls180.v:6163$1726_Y end - attribute \src "ls180.v:6395.42-6395.95" - cell $and $and$ls180.v:6395$1869 + attribute \src "ls180.v:6201.42-6201.95" + cell $and $and$ls180.v:6201$1728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263806,43 +262094,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6395$1869_Y + connect \Y $and$ls180.v:6201$1728_Y end - attribute \src "ls180.v:6395.41-6395.145" - cell $and $and$ls180.v:6395$1871 + attribute \src "ls180.v:6201.41-6201.145" + cell $and $and$ls180.v:6201$1730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6395$1869_Y - connect \B $eq$ls180.v:6395$1870_Y - connect \Y $and$ls180.v:6395$1871_Y + connect \A $and$ls180.v:6201$1728_Y + connect \B $eq$ls180.v:6201$1729_Y + connect \Y $and$ls180.v:6201$1730_Y end - attribute \src "ls180.v:6396.42-6396.98" - cell $and $and$ls180.v:6396$1873 + attribute \src "ls180.v:6202.42-6202.98" + cell $and $and$ls180.v:6202$1732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6396$1872_Y - connect \Y $and$ls180.v:6396$1873_Y + connect \B $not$ls180.v:6202$1731_Y + connect \Y $and$ls180.v:6202$1732_Y end - attribute \src "ls180.v:6396.41-6396.148" - cell $and $and$ls180.v:6396$1875 + attribute \src "ls180.v:6202.41-6202.148" + cell $and $and$ls180.v:6202$1734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6396$1873_Y - connect \B $eq$ls180.v:6396$1874_Y - connect \Y $and$ls180.v:6396$1875_Y + connect \A $and$ls180.v:6202$1732_Y + connect \B $eq$ls180.v:6202$1733_Y + connect \Y $and$ls180.v:6202$1734_Y end - attribute \src "ls180.v:6398.42-6398.95" - cell $and $and$ls180.v:6398$1876 + attribute \src "ls180.v:6204.42-6204.95" + cell $and $and$ls180.v:6204$1735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263850,43 +262138,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6398$1876_Y + connect \Y $and$ls180.v:6204$1735_Y end - attribute \src "ls180.v:6398.41-6398.145" - cell $and $and$ls180.v:6398$1878 + attribute \src "ls180.v:6204.41-6204.145" + cell $and $and$ls180.v:6204$1737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6398$1876_Y - connect \B $eq$ls180.v:6398$1877_Y - connect \Y $and$ls180.v:6398$1878_Y + connect \A $and$ls180.v:6204$1735_Y + connect \B $eq$ls180.v:6204$1736_Y + connect \Y $and$ls180.v:6204$1737_Y end - attribute \src "ls180.v:6399.42-6399.98" - cell $and $and$ls180.v:6399$1880 + attribute \src "ls180.v:6205.42-6205.98" + cell $and $and$ls180.v:6205$1739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6399$1879_Y - connect \Y $and$ls180.v:6399$1880_Y + connect \B $not$ls180.v:6205$1738_Y + connect \Y $and$ls180.v:6205$1739_Y end - attribute \src "ls180.v:6399.41-6399.148" - cell $and $and$ls180.v:6399$1882 + attribute \src "ls180.v:6205.41-6205.148" + cell $and $and$ls180.v:6205$1741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6399$1880_Y - connect \B $eq$ls180.v:6399$1881_Y - connect \Y $and$ls180.v:6399$1882_Y + connect \A $and$ls180.v:6205$1739_Y + connect \B $eq$ls180.v:6205$1740_Y + connect \Y $and$ls180.v:6205$1741_Y end - attribute \src "ls180.v:6401.42-6401.95" - cell $and $and$ls180.v:6401$1883 + attribute \src "ls180.v:6207.42-6207.95" + cell $and $and$ls180.v:6207$1742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263894,43 +262182,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6401$1883_Y + connect \Y $and$ls180.v:6207$1742_Y end - attribute \src "ls180.v:6401.41-6401.145" - cell $and $and$ls180.v:6401$1885 + attribute \src "ls180.v:6207.41-6207.145" + cell $and $and$ls180.v:6207$1744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6401$1883_Y - connect \B $eq$ls180.v:6401$1884_Y - connect \Y $and$ls180.v:6401$1885_Y + connect \A $and$ls180.v:6207$1742_Y + connect \B $eq$ls180.v:6207$1743_Y + connect \Y $and$ls180.v:6207$1744_Y end - attribute \src "ls180.v:6402.42-6402.98" - cell $and $and$ls180.v:6402$1887 + attribute \src "ls180.v:6208.42-6208.98" + cell $and $and$ls180.v:6208$1746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6402$1886_Y - connect \Y $and$ls180.v:6402$1887_Y + connect \B $not$ls180.v:6208$1745_Y + connect \Y $and$ls180.v:6208$1746_Y end - attribute \src "ls180.v:6402.41-6402.148" - cell $and $and$ls180.v:6402$1889 + attribute \src "ls180.v:6208.41-6208.148" + cell $and $and$ls180.v:6208$1748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6402$1887_Y - connect \B $eq$ls180.v:6402$1888_Y - connect \Y $and$ls180.v:6402$1889_Y + connect \A $and$ls180.v:6208$1746_Y + connect \B $eq$ls180.v:6208$1747_Y + connect \Y $and$ls180.v:6208$1748_Y end - attribute \src "ls180.v:6404.42-6404.95" - cell $and $and$ls180.v:6404$1890 + attribute \src "ls180.v:6210.42-6210.95" + cell $and $and$ls180.v:6210$1749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263938,43 +262226,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6404$1890_Y + connect \Y $and$ls180.v:6210$1749_Y end - attribute \src "ls180.v:6404.41-6404.145" - cell $and $and$ls180.v:6404$1892 + attribute \src "ls180.v:6210.41-6210.145" + cell $and $and$ls180.v:6210$1751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6404$1890_Y - connect \B $eq$ls180.v:6404$1891_Y - connect \Y $and$ls180.v:6404$1892_Y + connect \A $and$ls180.v:6210$1749_Y + connect \B $eq$ls180.v:6210$1750_Y + connect \Y $and$ls180.v:6210$1751_Y end - attribute \src "ls180.v:6405.42-6405.98" - cell $and $and$ls180.v:6405$1894 + attribute \src "ls180.v:6211.42-6211.98" + cell $and $and$ls180.v:6211$1753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6405$1893_Y - connect \Y $and$ls180.v:6405$1894_Y + connect \B $not$ls180.v:6211$1752_Y + connect \Y $and$ls180.v:6211$1753_Y end - attribute \src "ls180.v:6405.41-6405.148" - cell $and $and$ls180.v:6405$1896 + attribute \src "ls180.v:6211.41-6211.148" + cell $and $and$ls180.v:6211$1755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6405$1894_Y - connect \B $eq$ls180.v:6405$1895_Y - connect \Y $and$ls180.v:6405$1896_Y + connect \A $and$ls180.v:6211$1753_Y + connect \B $eq$ls180.v:6211$1754_Y + connect \Y $and$ls180.v:6211$1755_Y end - attribute \src "ls180.v:6407.42-6407.95" - cell $and $and$ls180.v:6407$1897 + attribute \src "ls180.v:6213.42-6213.95" + cell $and $and$ls180.v:6213$1756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -263982,43 +262270,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6407$1897_Y + connect \Y $and$ls180.v:6213$1756_Y end - attribute \src "ls180.v:6407.41-6407.145" - cell $and $and$ls180.v:6407$1899 + attribute \src "ls180.v:6213.41-6213.145" + cell $and $and$ls180.v:6213$1758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6407$1897_Y - connect \B $eq$ls180.v:6407$1898_Y - connect \Y $and$ls180.v:6407$1899_Y + connect \A $and$ls180.v:6213$1756_Y + connect \B $eq$ls180.v:6213$1757_Y + connect \Y $and$ls180.v:6213$1758_Y end - attribute \src "ls180.v:6408.42-6408.98" - cell $and $and$ls180.v:6408$1901 + attribute \src "ls180.v:6214.42-6214.98" + cell $and $and$ls180.v:6214$1760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6408$1900_Y - connect \Y $and$ls180.v:6408$1901_Y + connect \B $not$ls180.v:6214$1759_Y + connect \Y $and$ls180.v:6214$1760_Y end - attribute \src "ls180.v:6408.41-6408.148" - cell $and $and$ls180.v:6408$1903 + attribute \src "ls180.v:6214.41-6214.148" + cell $and $and$ls180.v:6214$1762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6408$1901_Y - connect \B $eq$ls180.v:6408$1902_Y - connect \Y $and$ls180.v:6408$1903_Y + connect \A $and$ls180.v:6214$1760_Y + connect \B $eq$ls180.v:6214$1761_Y + connect \Y $and$ls180.v:6214$1762_Y end - attribute \src "ls180.v:6410.42-6410.95" - cell $and $and$ls180.v:6410$1904 + attribute \src "ls180.v:6216.42-6216.95" + cell $and $and$ls180.v:6216$1763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264026,43 +262314,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6410$1904_Y + connect \Y $and$ls180.v:6216$1763_Y end - attribute \src "ls180.v:6410.41-6410.145" - cell $and $and$ls180.v:6410$1906 + attribute \src "ls180.v:6216.41-6216.145" + cell $and $and$ls180.v:6216$1765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6410$1904_Y - connect \B $eq$ls180.v:6410$1905_Y - connect \Y $and$ls180.v:6410$1906_Y + connect \A $and$ls180.v:6216$1763_Y + connect \B $eq$ls180.v:6216$1764_Y + connect \Y $and$ls180.v:6216$1765_Y end - attribute \src "ls180.v:6411.42-6411.98" - cell $and $and$ls180.v:6411$1908 + attribute \src "ls180.v:6217.42-6217.98" + cell $and $and$ls180.v:6217$1767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6411$1907_Y - connect \Y $and$ls180.v:6411$1908_Y + connect \B $not$ls180.v:6217$1766_Y + connect \Y $and$ls180.v:6217$1767_Y end - attribute \src "ls180.v:6411.41-6411.148" - cell $and $and$ls180.v:6411$1910 + attribute \src "ls180.v:6217.41-6217.148" + cell $and $and$ls180.v:6217$1769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6411$1908_Y - connect \B $eq$ls180.v:6411$1909_Y - connect \Y $and$ls180.v:6411$1910_Y + connect \A $and$ls180.v:6217$1767_Y + connect \B $eq$ls180.v:6217$1768_Y + connect \Y $and$ls180.v:6217$1769_Y end - attribute \src "ls180.v:6413.42-6413.95" - cell $and $and$ls180.v:6413$1911 + attribute \src "ls180.v:6219.42-6219.95" + cell $and $and$ls180.v:6219$1770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264070,43 +262358,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6413$1911_Y + connect \Y $and$ls180.v:6219$1770_Y end - attribute \src "ls180.v:6413.41-6413.145" - cell $and $and$ls180.v:6413$1913 + attribute \src "ls180.v:6219.41-6219.145" + cell $and $and$ls180.v:6219$1772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6413$1911_Y - connect \B $eq$ls180.v:6413$1912_Y - connect \Y $and$ls180.v:6413$1913_Y + connect \A $and$ls180.v:6219$1770_Y + connect \B $eq$ls180.v:6219$1771_Y + connect \Y $and$ls180.v:6219$1772_Y end - attribute \src "ls180.v:6414.42-6414.98" - cell $and $and$ls180.v:6414$1915 + attribute \src "ls180.v:6220.42-6220.98" + cell $and $and$ls180.v:6220$1774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6414$1914_Y - connect \Y $and$ls180.v:6414$1915_Y + connect \B $not$ls180.v:6220$1773_Y + connect \Y $and$ls180.v:6220$1774_Y end - attribute \src "ls180.v:6414.41-6414.148" - cell $and $and$ls180.v:6414$1917 + attribute \src "ls180.v:6220.41-6220.148" + cell $and $and$ls180.v:6220$1776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6414$1915_Y - connect \B $eq$ls180.v:6414$1916_Y - connect \Y $and$ls180.v:6414$1917_Y + connect \A $and$ls180.v:6220$1774_Y + connect \B $eq$ls180.v:6220$1775_Y + connect \Y $and$ls180.v:6220$1776_Y end - attribute \src "ls180.v:6416.42-6416.95" - cell $and $and$ls180.v:6416$1918 + attribute \src "ls180.v:6222.42-6222.95" + cell $and $and$ls180.v:6222$1777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264114,43 +262402,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6416$1918_Y + connect \Y $and$ls180.v:6222$1777_Y end - attribute \src "ls180.v:6416.41-6416.145" - cell $and $and$ls180.v:6416$1920 + attribute \src "ls180.v:6222.41-6222.145" + cell $and $and$ls180.v:6222$1779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6416$1918_Y - connect \B $eq$ls180.v:6416$1919_Y - connect \Y $and$ls180.v:6416$1920_Y + connect \A $and$ls180.v:6222$1777_Y + connect \B $eq$ls180.v:6222$1778_Y + connect \Y $and$ls180.v:6222$1779_Y end - attribute \src "ls180.v:6417.42-6417.98" - cell $and $and$ls180.v:6417$1922 + attribute \src "ls180.v:6223.42-6223.98" + cell $and $and$ls180.v:6223$1781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6417$1921_Y - connect \Y $and$ls180.v:6417$1922_Y + connect \B $not$ls180.v:6223$1780_Y + connect \Y $and$ls180.v:6223$1781_Y end - attribute \src "ls180.v:6417.41-6417.148" - cell $and $and$ls180.v:6417$1924 + attribute \src "ls180.v:6223.41-6223.148" + cell $and $and$ls180.v:6223$1783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6417$1922_Y - connect \B $eq$ls180.v:6417$1923_Y - connect \Y $and$ls180.v:6417$1924_Y + connect \A $and$ls180.v:6223$1781_Y + connect \B $eq$ls180.v:6223$1782_Y + connect \Y $and$ls180.v:6223$1783_Y end - attribute \src "ls180.v:6419.44-6419.97" - cell $and $and$ls180.v:6419$1925 + attribute \src "ls180.v:6225.44-6225.97" + cell $and $and$ls180.v:6225$1784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264158,43 +262446,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6419$1925_Y + connect \Y $and$ls180.v:6225$1784_Y end - attribute \src "ls180.v:6419.43-6419.147" - cell $and $and$ls180.v:6419$1927 + attribute \src "ls180.v:6225.43-6225.147" + cell $and $and$ls180.v:6225$1786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6419$1925_Y - connect \B $eq$ls180.v:6419$1926_Y - connect \Y $and$ls180.v:6419$1927_Y + connect \A $and$ls180.v:6225$1784_Y + connect \B $eq$ls180.v:6225$1785_Y + connect \Y $and$ls180.v:6225$1786_Y end - attribute \src "ls180.v:6420.44-6420.100" - cell $and $and$ls180.v:6420$1929 + attribute \src "ls180.v:6226.44-6226.100" + cell $and $and$ls180.v:6226$1788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6420$1928_Y - connect \Y $and$ls180.v:6420$1929_Y + connect \B $not$ls180.v:6226$1787_Y + connect \Y $and$ls180.v:6226$1788_Y end - attribute \src "ls180.v:6420.43-6420.150" - cell $and $and$ls180.v:6420$1931 + attribute \src "ls180.v:6226.43-6226.150" + cell $and $and$ls180.v:6226$1790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6420$1929_Y - connect \B $eq$ls180.v:6420$1930_Y - connect \Y $and$ls180.v:6420$1931_Y + connect \A $and$ls180.v:6226$1788_Y + connect \B $eq$ls180.v:6226$1789_Y + connect \Y $and$ls180.v:6226$1790_Y end - attribute \src "ls180.v:6422.44-6422.97" - cell $and $and$ls180.v:6422$1932 + attribute \src "ls180.v:6228.44-6228.97" + cell $and $and$ls180.v:6228$1791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264202,43 +262490,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6422$1932_Y + connect \Y $and$ls180.v:6228$1791_Y end - attribute \src "ls180.v:6422.43-6422.147" - cell $and $and$ls180.v:6422$1934 + attribute \src "ls180.v:6228.43-6228.147" + cell $and $and$ls180.v:6228$1793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6422$1932_Y - connect \B $eq$ls180.v:6422$1933_Y - connect \Y $and$ls180.v:6422$1934_Y + connect \A $and$ls180.v:6228$1791_Y + connect \B $eq$ls180.v:6228$1792_Y + connect \Y $and$ls180.v:6228$1793_Y end - attribute \src "ls180.v:6423.44-6423.100" - cell $and $and$ls180.v:6423$1936 + attribute \src "ls180.v:6229.44-6229.100" + cell $and $and$ls180.v:6229$1795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6423$1935_Y - connect \Y $and$ls180.v:6423$1936_Y + connect \B $not$ls180.v:6229$1794_Y + connect \Y $and$ls180.v:6229$1795_Y end - attribute \src "ls180.v:6423.43-6423.150" - cell $and $and$ls180.v:6423$1938 + attribute \src "ls180.v:6229.43-6229.150" + cell $and $and$ls180.v:6229$1797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6423$1936_Y - connect \B $eq$ls180.v:6423$1937_Y - connect \Y $and$ls180.v:6423$1938_Y + connect \A $and$ls180.v:6229$1795_Y + connect \B $eq$ls180.v:6229$1796_Y + connect \Y $and$ls180.v:6229$1797_Y end - attribute \src "ls180.v:6425.44-6425.97" - cell $and $and$ls180.v:6425$1939 + attribute \src "ls180.v:6231.44-6231.97" + cell $and $and$ls180.v:6231$1798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264246,43 +262534,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6425$1939_Y + connect \Y $and$ls180.v:6231$1798_Y end - attribute \src "ls180.v:6425.43-6425.148" - cell $and $and$ls180.v:6425$1941 + attribute \src "ls180.v:6231.43-6231.148" + cell $and $and$ls180.v:6231$1800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6425$1939_Y - connect \B $eq$ls180.v:6425$1940_Y - connect \Y $and$ls180.v:6425$1941_Y + connect \A $and$ls180.v:6231$1798_Y + connect \B $eq$ls180.v:6231$1799_Y + connect \Y $and$ls180.v:6231$1800_Y end - attribute \src "ls180.v:6426.44-6426.100" - cell $and $and$ls180.v:6426$1943 + attribute \src "ls180.v:6232.44-6232.100" + cell $and $and$ls180.v:6232$1802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6426$1942_Y - connect \Y $and$ls180.v:6426$1943_Y + connect \B $not$ls180.v:6232$1801_Y + connect \Y $and$ls180.v:6232$1802_Y end - attribute \src "ls180.v:6426.43-6426.151" - cell $and $and$ls180.v:6426$1945 + attribute \src "ls180.v:6232.43-6232.151" + cell $and $and$ls180.v:6232$1804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6426$1943_Y - connect \B $eq$ls180.v:6426$1944_Y - connect \Y $and$ls180.v:6426$1945_Y + connect \A $and$ls180.v:6232$1802_Y + connect \B $eq$ls180.v:6232$1803_Y + connect \Y $and$ls180.v:6232$1804_Y end - attribute \src "ls180.v:6428.44-6428.97" - cell $and $and$ls180.v:6428$1946 + attribute \src "ls180.v:6234.44-6234.97" + cell $and $and$ls180.v:6234$1805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264290,43 +262578,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6428$1946_Y + connect \Y $and$ls180.v:6234$1805_Y end - attribute \src "ls180.v:6428.43-6428.148" - cell $and $and$ls180.v:6428$1948 + attribute \src "ls180.v:6234.43-6234.148" + cell $and $and$ls180.v:6234$1807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6428$1946_Y - connect \B $eq$ls180.v:6428$1947_Y - connect \Y $and$ls180.v:6428$1948_Y + connect \A $and$ls180.v:6234$1805_Y + connect \B $eq$ls180.v:6234$1806_Y + connect \Y $and$ls180.v:6234$1807_Y end - attribute \src "ls180.v:6429.44-6429.100" - cell $and $and$ls180.v:6429$1950 + attribute \src "ls180.v:6235.44-6235.100" + cell $and $and$ls180.v:6235$1809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6429$1949_Y - connect \Y $and$ls180.v:6429$1950_Y + connect \B $not$ls180.v:6235$1808_Y + connect \Y $and$ls180.v:6235$1809_Y end - attribute \src "ls180.v:6429.43-6429.151" - cell $and $and$ls180.v:6429$1952 + attribute \src "ls180.v:6235.43-6235.151" + cell $and $and$ls180.v:6235$1811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6429$1950_Y - connect \B $eq$ls180.v:6429$1951_Y - connect \Y $and$ls180.v:6429$1952_Y + connect \A $and$ls180.v:6235$1809_Y + connect \B $eq$ls180.v:6235$1810_Y + connect \Y $and$ls180.v:6235$1811_Y end - attribute \src "ls180.v:6431.44-6431.97" - cell $and $and$ls180.v:6431$1953 + attribute \src "ls180.v:6237.44-6237.97" + cell $and $and$ls180.v:6237$1812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264334,43 +262622,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6431$1953_Y + connect \Y $and$ls180.v:6237$1812_Y end - attribute \src "ls180.v:6431.43-6431.148" - cell $and $and$ls180.v:6431$1955 + attribute \src "ls180.v:6237.43-6237.148" + cell $and $and$ls180.v:6237$1814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6431$1953_Y - connect \B $eq$ls180.v:6431$1954_Y - connect \Y $and$ls180.v:6431$1955_Y + connect \A $and$ls180.v:6237$1812_Y + connect \B $eq$ls180.v:6237$1813_Y + connect \Y $and$ls180.v:6237$1814_Y end - attribute \src "ls180.v:6432.44-6432.100" - cell $and $and$ls180.v:6432$1957 + attribute \src "ls180.v:6238.44-6238.100" + cell $and $and$ls180.v:6238$1816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6432$1956_Y - connect \Y $and$ls180.v:6432$1957_Y + connect \B $not$ls180.v:6238$1815_Y + connect \Y $and$ls180.v:6238$1816_Y end - attribute \src "ls180.v:6432.43-6432.151" - cell $and $and$ls180.v:6432$1959 + attribute \src "ls180.v:6238.43-6238.151" + cell $and $and$ls180.v:6238$1818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6432$1957_Y - connect \B $eq$ls180.v:6432$1958_Y - connect \Y $and$ls180.v:6432$1959_Y + connect \A $and$ls180.v:6238$1816_Y + connect \B $eq$ls180.v:6238$1817_Y + connect \Y $and$ls180.v:6238$1818_Y end - attribute \src "ls180.v:6434.41-6434.94" - cell $and $and$ls180.v:6434$1960 + attribute \src "ls180.v:6240.41-6240.94" + cell $and $and$ls180.v:6240$1819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264378,43 +262666,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6434$1960_Y + connect \Y $and$ls180.v:6240$1819_Y end - attribute \src "ls180.v:6434.40-6434.145" - cell $and $and$ls180.v:6434$1962 + attribute \src "ls180.v:6240.40-6240.145" + cell $and $and$ls180.v:6240$1821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6434$1960_Y - connect \B $eq$ls180.v:6434$1961_Y - connect \Y $and$ls180.v:6434$1962_Y + connect \A $and$ls180.v:6240$1819_Y + connect \B $eq$ls180.v:6240$1820_Y + connect \Y $and$ls180.v:6240$1821_Y end - attribute \src "ls180.v:6435.41-6435.97" - cell $and $and$ls180.v:6435$1964 + attribute \src "ls180.v:6241.41-6241.97" + cell $and $and$ls180.v:6241$1823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6435$1963_Y - connect \Y $and$ls180.v:6435$1964_Y + connect \B $not$ls180.v:6241$1822_Y + connect \Y $and$ls180.v:6241$1823_Y end - attribute \src "ls180.v:6435.40-6435.148" - cell $and $and$ls180.v:6435$1966 + attribute \src "ls180.v:6241.40-6241.148" + cell $and $and$ls180.v:6241$1825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6435$1964_Y - connect \B $eq$ls180.v:6435$1965_Y - connect \Y $and$ls180.v:6435$1966_Y + connect \A $and$ls180.v:6241$1823_Y + connect \B $eq$ls180.v:6241$1824_Y + connect \Y $and$ls180.v:6241$1825_Y end - attribute \src "ls180.v:6437.42-6437.95" - cell $and $and$ls180.v:6437$1967 + attribute \src "ls180.v:6243.42-6243.95" + cell $and $and$ls180.v:6243$1826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264422,43 +262710,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6437$1967_Y + connect \Y $and$ls180.v:6243$1826_Y end - attribute \src "ls180.v:6437.41-6437.146" - cell $and $and$ls180.v:6437$1969 + attribute \src "ls180.v:6243.41-6243.146" + cell $and $and$ls180.v:6243$1828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6437$1967_Y - connect \B $eq$ls180.v:6437$1968_Y - connect \Y $and$ls180.v:6437$1969_Y + connect \A $and$ls180.v:6243$1826_Y + connect \B $eq$ls180.v:6243$1827_Y + connect \Y $and$ls180.v:6243$1828_Y end - attribute \src "ls180.v:6438.42-6438.98" - cell $and $and$ls180.v:6438$1971 + attribute \src "ls180.v:6244.42-6244.98" + cell $and $and$ls180.v:6244$1830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6438$1970_Y - connect \Y $and$ls180.v:6438$1971_Y + connect \B $not$ls180.v:6244$1829_Y + connect \Y $and$ls180.v:6244$1830_Y end - attribute \src "ls180.v:6438.41-6438.149" - cell $and $and$ls180.v:6438$1973 + attribute \src "ls180.v:6244.41-6244.149" + cell $and $and$ls180.v:6244$1832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6438$1971_Y - connect \B $eq$ls180.v:6438$1972_Y - connect \Y $and$ls180.v:6438$1973_Y + connect \A $and$ls180.v:6244$1830_Y + connect \B $eq$ls180.v:6244$1831_Y + connect \Y $and$ls180.v:6244$1832_Y end - attribute \src "ls180.v:6440.44-6440.97" - cell $and $and$ls180.v:6440$1974 + attribute \src "ls180.v:6246.44-6246.97" + cell $and $and$ls180.v:6246$1833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264466,43 +262754,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6440$1974_Y + connect \Y $and$ls180.v:6246$1833_Y end - attribute \src "ls180.v:6440.43-6440.148" - cell $and $and$ls180.v:6440$1976 + attribute \src "ls180.v:6246.43-6246.148" + cell $and $and$ls180.v:6246$1835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6440$1974_Y - connect \B $eq$ls180.v:6440$1975_Y - connect \Y $and$ls180.v:6440$1976_Y + connect \A $and$ls180.v:6246$1833_Y + connect \B $eq$ls180.v:6246$1834_Y + connect \Y $and$ls180.v:6246$1835_Y end - attribute \src "ls180.v:6441.44-6441.100" - cell $and $and$ls180.v:6441$1978 + attribute \src "ls180.v:6247.44-6247.100" + cell $and $and$ls180.v:6247$1837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6441$1977_Y - connect \Y $and$ls180.v:6441$1978_Y + connect \B $not$ls180.v:6247$1836_Y + connect \Y $and$ls180.v:6247$1837_Y end - attribute \src "ls180.v:6441.43-6441.151" - cell $and $and$ls180.v:6441$1980 + attribute \src "ls180.v:6247.43-6247.151" + cell $and $and$ls180.v:6247$1839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6441$1978_Y - connect \B $eq$ls180.v:6441$1979_Y - connect \Y $and$ls180.v:6441$1980_Y + connect \A $and$ls180.v:6247$1837_Y + connect \B $eq$ls180.v:6247$1838_Y + connect \Y $and$ls180.v:6247$1839_Y end - attribute \src "ls180.v:6443.44-6443.97" - cell $and $and$ls180.v:6443$1981 + attribute \src "ls180.v:6249.44-6249.97" + cell $and $and$ls180.v:6249$1840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264510,43 +262798,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6443$1981_Y + connect \Y $and$ls180.v:6249$1840_Y end - attribute \src "ls180.v:6443.43-6443.148" - cell $and $and$ls180.v:6443$1983 + attribute \src "ls180.v:6249.43-6249.148" + cell $and $and$ls180.v:6249$1842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6443$1981_Y - connect \B $eq$ls180.v:6443$1982_Y - connect \Y $and$ls180.v:6443$1983_Y + connect \A $and$ls180.v:6249$1840_Y + connect \B $eq$ls180.v:6249$1841_Y + connect \Y $and$ls180.v:6249$1842_Y end - attribute \src "ls180.v:6444.44-6444.100" - cell $and $and$ls180.v:6444$1985 + attribute \src "ls180.v:6250.44-6250.100" + cell $and $and$ls180.v:6250$1844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6444$1984_Y - connect \Y $and$ls180.v:6444$1985_Y + connect \B $not$ls180.v:6250$1843_Y + connect \Y $and$ls180.v:6250$1844_Y end - attribute \src "ls180.v:6444.43-6444.151" - cell $and $and$ls180.v:6444$1987 + attribute \src "ls180.v:6250.43-6250.151" + cell $and $and$ls180.v:6250$1846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6444$1985_Y - connect \B $eq$ls180.v:6444$1986_Y - connect \Y $and$ls180.v:6444$1987_Y + connect \A $and$ls180.v:6250$1844_Y + connect \B $eq$ls180.v:6250$1845_Y + connect \Y $and$ls180.v:6250$1846_Y end - attribute \src "ls180.v:6446.44-6446.97" - cell $and $and$ls180.v:6446$1988 + attribute \src "ls180.v:6252.44-6252.97" + cell $and $and$ls180.v:6252$1847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264554,43 +262842,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6446$1988_Y + connect \Y $and$ls180.v:6252$1847_Y end - attribute \src "ls180.v:6446.43-6446.148" - cell $and $and$ls180.v:6446$1990 + attribute \src "ls180.v:6252.43-6252.148" + cell $and $and$ls180.v:6252$1849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6446$1988_Y - connect \B $eq$ls180.v:6446$1989_Y - connect \Y $and$ls180.v:6446$1990_Y + connect \A $and$ls180.v:6252$1847_Y + connect \B $eq$ls180.v:6252$1848_Y + connect \Y $and$ls180.v:6252$1849_Y end - attribute \src "ls180.v:6447.44-6447.100" - cell $and $and$ls180.v:6447$1992 + attribute \src "ls180.v:6253.44-6253.100" + cell $and $and$ls180.v:6253$1851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6447$1991_Y - connect \Y $and$ls180.v:6447$1992_Y + connect \B $not$ls180.v:6253$1850_Y + connect \Y $and$ls180.v:6253$1851_Y end - attribute \src "ls180.v:6447.43-6447.151" - cell $and $and$ls180.v:6447$1994 + attribute \src "ls180.v:6253.43-6253.151" + cell $and $and$ls180.v:6253$1853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6447$1992_Y - connect \B $eq$ls180.v:6447$1993_Y - connect \Y $and$ls180.v:6447$1994_Y + connect \A $and$ls180.v:6253$1851_Y + connect \B $eq$ls180.v:6253$1852_Y + connect \Y $and$ls180.v:6253$1853_Y end - attribute \src "ls180.v:6449.44-6449.97" - cell $and $and$ls180.v:6449$1995 + attribute \src "ls180.v:6255.44-6255.97" + cell $and $and$ls180.v:6255$1854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264598,43 +262886,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6449$1995_Y + connect \Y $and$ls180.v:6255$1854_Y end - attribute \src "ls180.v:6449.43-6449.148" - cell $and $and$ls180.v:6449$1997 + attribute \src "ls180.v:6255.43-6255.148" + cell $and $and$ls180.v:6255$1856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6449$1995_Y - connect \B $eq$ls180.v:6449$1996_Y - connect \Y $and$ls180.v:6449$1997_Y + connect \A $and$ls180.v:6255$1854_Y + connect \B $eq$ls180.v:6255$1855_Y + connect \Y $and$ls180.v:6255$1856_Y end - attribute \src "ls180.v:6450.44-6450.100" - cell $and $and$ls180.v:6450$1999 + attribute \src "ls180.v:6256.44-6256.100" + cell $and $and$ls180.v:6256$1858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6450$1998_Y - connect \Y $and$ls180.v:6450$1999_Y + connect \B $not$ls180.v:6256$1857_Y + connect \Y $and$ls180.v:6256$1858_Y end - attribute \src "ls180.v:6450.43-6450.151" - cell $and $and$ls180.v:6450$2001 + attribute \src "ls180.v:6256.43-6256.151" + cell $and $and$ls180.v:6256$1860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6450$1999_Y - connect \B $eq$ls180.v:6450$2000_Y - connect \Y $and$ls180.v:6450$2001_Y + connect \A $and$ls180.v:6256$1858_Y + connect \B $eq$ls180.v:6256$1859_Y + connect \Y $and$ls180.v:6256$1860_Y end - attribute \src "ls180.v:6474.44-6474.97" - cell $and $and$ls180.v:6474$2003 + attribute \src "ls180.v:6280.44-6280.97" + cell $and $and$ls180.v:6280$1862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264642,43 +262930,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6474$2003_Y + connect \Y $and$ls180.v:6280$1862_Y end - attribute \src "ls180.v:6474.43-6474.147" - cell $and $and$ls180.v:6474$2005 + attribute \src "ls180.v:6280.43-6280.147" + cell $and $and$ls180.v:6280$1864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6474$2003_Y - connect \B $eq$ls180.v:6474$2004_Y - connect \Y $and$ls180.v:6474$2005_Y + connect \A $and$ls180.v:6280$1862_Y + connect \B $eq$ls180.v:6280$1863_Y + connect \Y $and$ls180.v:6280$1864_Y end - attribute \src "ls180.v:6475.44-6475.100" - cell $and $and$ls180.v:6475$2007 + attribute \src "ls180.v:6281.44-6281.100" + cell $and $and$ls180.v:6281$1866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6475$2006_Y - connect \Y $and$ls180.v:6475$2007_Y + connect \B $not$ls180.v:6281$1865_Y + connect \Y $and$ls180.v:6281$1866_Y end - attribute \src "ls180.v:6475.43-6475.150" - cell $and $and$ls180.v:6475$2009 + attribute \src "ls180.v:6281.43-6281.150" + cell $and $and$ls180.v:6281$1868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6475$2007_Y - connect \B $eq$ls180.v:6475$2008_Y - connect \Y $and$ls180.v:6475$2009_Y + connect \A $and$ls180.v:6281$1866_Y + connect \B $eq$ls180.v:6281$1867_Y + connect \Y $and$ls180.v:6281$1868_Y end - attribute \src "ls180.v:6477.49-6477.102" - cell $and $and$ls180.v:6477$2010 + attribute \src "ls180.v:6283.49-6283.102" + cell $and $and$ls180.v:6283$1869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264686,43 +262974,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6477$2010_Y + connect \Y $and$ls180.v:6283$1869_Y end - attribute \src "ls180.v:6477.48-6477.152" - cell $and $and$ls180.v:6477$2012 + attribute \src "ls180.v:6283.48-6283.152" + cell $and $and$ls180.v:6283$1871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6477$2010_Y - connect \B $eq$ls180.v:6477$2011_Y - connect \Y $and$ls180.v:6477$2012_Y + connect \A $and$ls180.v:6283$1869_Y + connect \B $eq$ls180.v:6283$1870_Y + connect \Y $and$ls180.v:6283$1871_Y end - attribute \src "ls180.v:6478.49-6478.105" - cell $and $and$ls180.v:6478$2014 + attribute \src "ls180.v:6284.49-6284.105" + cell $and $and$ls180.v:6284$1873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6478$2013_Y - connect \Y $and$ls180.v:6478$2014_Y + connect \B $not$ls180.v:6284$1872_Y + connect \Y $and$ls180.v:6284$1873_Y end - attribute \src "ls180.v:6478.48-6478.155" - cell $and $and$ls180.v:6478$2016 + attribute \src "ls180.v:6284.48-6284.155" + cell $and $and$ls180.v:6284$1875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6478$2014_Y - connect \B $eq$ls180.v:6478$2015_Y - connect \Y $and$ls180.v:6478$2016_Y + connect \A $and$ls180.v:6284$1873_Y + connect \B $eq$ls180.v:6284$1874_Y + connect \Y $and$ls180.v:6284$1875_Y end - attribute \src "ls180.v:6480.49-6480.102" - cell $and $and$ls180.v:6480$2017 + attribute \src "ls180.v:6286.49-6286.102" + cell $and $and$ls180.v:6286$1876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264730,43 +263018,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6480$2017_Y + connect \Y $and$ls180.v:6286$1876_Y end - attribute \src "ls180.v:6480.48-6480.152" - cell $and $and$ls180.v:6480$2019 + attribute \src "ls180.v:6286.48-6286.152" + cell $and $and$ls180.v:6286$1878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6480$2017_Y - connect \B $eq$ls180.v:6480$2018_Y - connect \Y $and$ls180.v:6480$2019_Y + connect \A $and$ls180.v:6286$1876_Y + connect \B $eq$ls180.v:6286$1877_Y + connect \Y $and$ls180.v:6286$1878_Y end - attribute \src "ls180.v:6481.49-6481.105" - cell $and $and$ls180.v:6481$2021 + attribute \src "ls180.v:6287.49-6287.105" + cell $and $and$ls180.v:6287$1880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6481$2020_Y - connect \Y $and$ls180.v:6481$2021_Y + connect \B $not$ls180.v:6287$1879_Y + connect \Y $and$ls180.v:6287$1880_Y end - attribute \src "ls180.v:6481.48-6481.155" - cell $and $and$ls180.v:6481$2023 + attribute \src "ls180.v:6287.48-6287.155" + cell $and $and$ls180.v:6287$1882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6481$2021_Y - connect \B $eq$ls180.v:6481$2022_Y - connect \Y $and$ls180.v:6481$2023_Y + connect \A $and$ls180.v:6287$1880_Y + connect \B $eq$ls180.v:6287$1881_Y + connect \Y $and$ls180.v:6287$1882_Y end - attribute \src "ls180.v:6483.42-6483.95" - cell $and $and$ls180.v:6483$2024 + attribute \src "ls180.v:6289.42-6289.95" + cell $and $and$ls180.v:6289$1883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264774,43 +263062,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6483$2024_Y + connect \Y $and$ls180.v:6289$1883_Y end - attribute \src "ls180.v:6483.41-6483.145" - cell $and $and$ls180.v:6483$2026 + attribute \src "ls180.v:6289.41-6289.145" + cell $and $and$ls180.v:6289$1885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6483$2024_Y - connect \B $eq$ls180.v:6483$2025_Y - connect \Y $and$ls180.v:6483$2026_Y + connect \A $and$ls180.v:6289$1883_Y + connect \B $eq$ls180.v:6289$1884_Y + connect \Y $and$ls180.v:6289$1885_Y end - attribute \src "ls180.v:6484.42-6484.98" - cell $and $and$ls180.v:6484$2028 + attribute \src "ls180.v:6290.42-6290.98" + cell $and $and$ls180.v:6290$1887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6484$2027_Y - connect \Y $and$ls180.v:6484$2028_Y + connect \B $not$ls180.v:6290$1886_Y + connect \Y $and$ls180.v:6290$1887_Y end - attribute \src "ls180.v:6484.41-6484.148" - cell $and $and$ls180.v:6484$2030 + attribute \src "ls180.v:6290.41-6290.148" + cell $and $and$ls180.v:6290$1889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6484$2028_Y - connect \B $eq$ls180.v:6484$2029_Y - connect \Y $and$ls180.v:6484$2030_Y + connect \A $and$ls180.v:6290$1887_Y + connect \B $eq$ls180.v:6290$1888_Y + connect \Y $and$ls180.v:6290$1889_Y end - attribute \src "ls180.v:6491.46-6491.99" - cell $and $and$ls180.v:6491$2032 + attribute \src "ls180.v:6297.46-6297.99" + cell $and $and$ls180.v:6297$1891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264818,43 +263106,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6491$2032_Y + connect \Y $and$ls180.v:6297$1891_Y end - attribute \src "ls180.v:6491.45-6491.149" - cell $and $and$ls180.v:6491$2034 + attribute \src "ls180.v:6297.45-6297.149" + cell $and $and$ls180.v:6297$1893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6491$2032_Y - connect \B $eq$ls180.v:6491$2033_Y - connect \Y $and$ls180.v:6491$2034_Y + connect \A $and$ls180.v:6297$1891_Y + connect \B $eq$ls180.v:6297$1892_Y + connect \Y $and$ls180.v:6297$1893_Y end - attribute \src "ls180.v:6492.46-6492.102" - cell $and $and$ls180.v:6492$2036 + attribute \src "ls180.v:6298.46-6298.102" + cell $and $and$ls180.v:6298$1895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6492$2035_Y - connect \Y $and$ls180.v:6492$2036_Y + connect \B $not$ls180.v:6298$1894_Y + connect \Y $and$ls180.v:6298$1895_Y end - attribute \src "ls180.v:6492.45-6492.152" - cell $and $and$ls180.v:6492$2038 + attribute \src "ls180.v:6298.45-6298.152" + cell $and $and$ls180.v:6298$1897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6492$2036_Y - connect \B $eq$ls180.v:6492$2037_Y - connect \Y $and$ls180.v:6492$2038_Y + connect \A $and$ls180.v:6298$1895_Y + connect \B $eq$ls180.v:6298$1896_Y + connect \Y $and$ls180.v:6298$1897_Y end - attribute \src "ls180.v:6494.50-6494.103" - cell $and $and$ls180.v:6494$2039 + attribute \src "ls180.v:6300.50-6300.103" + cell $and $and$ls180.v:6300$1898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264862,43 +263150,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6494$2039_Y + connect \Y $and$ls180.v:6300$1898_Y end - attribute \src "ls180.v:6494.49-6494.153" - cell $and $and$ls180.v:6494$2041 + attribute \src "ls180.v:6300.49-6300.153" + cell $and $and$ls180.v:6300$1900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6494$2039_Y - connect \B $eq$ls180.v:6494$2040_Y - connect \Y $and$ls180.v:6494$2041_Y + connect \A $and$ls180.v:6300$1898_Y + connect \B $eq$ls180.v:6300$1899_Y + connect \Y $and$ls180.v:6300$1900_Y end - attribute \src "ls180.v:6495.50-6495.106" - cell $and $and$ls180.v:6495$2043 + attribute \src "ls180.v:6301.50-6301.106" + cell $and $and$ls180.v:6301$1902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6495$2042_Y - connect \Y $and$ls180.v:6495$2043_Y + connect \B $not$ls180.v:6301$1901_Y + connect \Y $and$ls180.v:6301$1902_Y end - attribute \src "ls180.v:6495.49-6495.156" - cell $and $and$ls180.v:6495$2045 + attribute \src "ls180.v:6301.49-6301.156" + cell $and $and$ls180.v:6301$1904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6495$2043_Y - connect \B $eq$ls180.v:6495$2044_Y - connect \Y $and$ls180.v:6495$2045_Y + connect \A $and$ls180.v:6301$1902_Y + connect \B $eq$ls180.v:6301$1903_Y + connect \Y $and$ls180.v:6301$1904_Y end - attribute \src "ls180.v:6497.40-6497.93" - cell $and $and$ls180.v:6497$2046 + attribute \src "ls180.v:6303.40-6303.93" + cell $and $and$ls180.v:6303$1905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264906,43 +263194,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6497$2046_Y + connect \Y $and$ls180.v:6303$1905_Y end - attribute \src "ls180.v:6497.39-6497.143" - cell $and $and$ls180.v:6497$2048 + attribute \src "ls180.v:6303.39-6303.143" + cell $and $and$ls180.v:6303$1907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6497$2046_Y - connect \B $eq$ls180.v:6497$2047_Y - connect \Y $and$ls180.v:6497$2048_Y + connect \A $and$ls180.v:6303$1905_Y + connect \B $eq$ls180.v:6303$1906_Y + connect \Y $and$ls180.v:6303$1907_Y end - attribute \src "ls180.v:6498.40-6498.96" - cell $and $and$ls180.v:6498$2050 + attribute \src "ls180.v:6304.40-6304.96" + cell $and $and$ls180.v:6304$1909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6498$2049_Y - connect \Y $and$ls180.v:6498$2050_Y + connect \B $not$ls180.v:6304$1908_Y + connect \Y $and$ls180.v:6304$1909_Y end - attribute \src "ls180.v:6498.39-6498.146" - cell $and $and$ls180.v:6498$2052 + attribute \src "ls180.v:6304.39-6304.146" + cell $and $and$ls180.v:6304$1911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6498$2050_Y - connect \B $eq$ls180.v:6498$2051_Y - connect \Y $and$ls180.v:6498$2052_Y + connect \A $and$ls180.v:6304$1909_Y + connect \B $eq$ls180.v:6304$1910_Y + connect \Y $and$ls180.v:6304$1911_Y end - attribute \src "ls180.v:6500.50-6500.103" - cell $and $and$ls180.v:6500$2053 + attribute \src "ls180.v:6306.50-6306.103" + cell $and $and$ls180.v:6306$1912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264950,43 +263238,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6500$2053_Y + connect \Y $and$ls180.v:6306$1912_Y end - attribute \src "ls180.v:6500.49-6500.153" - cell $and $and$ls180.v:6500$2055 + attribute \src "ls180.v:6306.49-6306.153" + cell $and $and$ls180.v:6306$1914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6500$2053_Y - connect \B $eq$ls180.v:6500$2054_Y - connect \Y $and$ls180.v:6500$2055_Y + connect \A $and$ls180.v:6306$1912_Y + connect \B $eq$ls180.v:6306$1913_Y + connect \Y $and$ls180.v:6306$1914_Y end - attribute \src "ls180.v:6501.50-6501.106" - cell $and $and$ls180.v:6501$2057 + attribute \src "ls180.v:6307.50-6307.106" + cell $and $and$ls180.v:6307$1916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6501$2056_Y - connect \Y $and$ls180.v:6501$2057_Y + connect \B $not$ls180.v:6307$1915_Y + connect \Y $and$ls180.v:6307$1916_Y end - attribute \src "ls180.v:6501.49-6501.156" - cell $and $and$ls180.v:6501$2059 + attribute \src "ls180.v:6307.49-6307.156" + cell $and $and$ls180.v:6307$1918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6501$2057_Y - connect \B $eq$ls180.v:6501$2058_Y - connect \Y $and$ls180.v:6501$2059_Y + connect \A $and$ls180.v:6307$1916_Y + connect \B $eq$ls180.v:6307$1917_Y + connect \Y $and$ls180.v:6307$1918_Y end - attribute \src "ls180.v:6503.50-6503.103" - cell $and $and$ls180.v:6503$2060 + attribute \src "ls180.v:6309.50-6309.103" + cell $and $and$ls180.v:6309$1919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -264994,43 +263282,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6503$2060_Y + connect \Y $and$ls180.v:6309$1919_Y end - attribute \src "ls180.v:6503.49-6503.153" - cell $and $and$ls180.v:6503$2062 + attribute \src "ls180.v:6309.49-6309.153" + cell $and $and$ls180.v:6309$1921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6503$2060_Y - connect \B $eq$ls180.v:6503$2061_Y - connect \Y $and$ls180.v:6503$2062_Y + connect \A $and$ls180.v:6309$1919_Y + connect \B $eq$ls180.v:6309$1920_Y + connect \Y $and$ls180.v:6309$1921_Y end - attribute \src "ls180.v:6504.50-6504.106" - cell $and $and$ls180.v:6504$2064 + attribute \src "ls180.v:6310.50-6310.106" + cell $and $and$ls180.v:6310$1923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6504$2063_Y - connect \Y $and$ls180.v:6504$2064_Y + connect \B $not$ls180.v:6310$1922_Y + connect \Y $and$ls180.v:6310$1923_Y end - attribute \src "ls180.v:6504.49-6504.156" - cell $and $and$ls180.v:6504$2066 + attribute \src "ls180.v:6310.49-6310.156" + cell $and $and$ls180.v:6310$1925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6504$2064_Y - connect \B $eq$ls180.v:6504$2065_Y - connect \Y $and$ls180.v:6504$2066_Y + connect \A $and$ls180.v:6310$1923_Y + connect \B $eq$ls180.v:6310$1924_Y + connect \Y $and$ls180.v:6310$1925_Y end - attribute \src "ls180.v:6506.51-6506.104" - cell $and $and$ls180.v:6506$2067 + attribute \src "ls180.v:6312.51-6312.104" + cell $and $and$ls180.v:6312$1926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265038,43 +263326,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6506$2067_Y + connect \Y $and$ls180.v:6312$1926_Y end - attribute \src "ls180.v:6506.50-6506.154" - cell $and $and$ls180.v:6506$2069 + attribute \src "ls180.v:6312.50-6312.154" + cell $and $and$ls180.v:6312$1928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6506$2067_Y - connect \B $eq$ls180.v:6506$2068_Y - connect \Y $and$ls180.v:6506$2069_Y + connect \A $and$ls180.v:6312$1926_Y + connect \B $eq$ls180.v:6312$1927_Y + connect \Y $and$ls180.v:6312$1928_Y end - attribute \src "ls180.v:6507.51-6507.107" - cell $and $and$ls180.v:6507$2071 + attribute \src "ls180.v:6313.51-6313.107" + cell $and $and$ls180.v:6313$1930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6507$2070_Y - connect \Y $and$ls180.v:6507$2071_Y + connect \B $not$ls180.v:6313$1929_Y + connect \Y $and$ls180.v:6313$1930_Y end - attribute \src "ls180.v:6507.50-6507.157" - cell $and $and$ls180.v:6507$2073 + attribute \src "ls180.v:6313.50-6313.157" + cell $and $and$ls180.v:6313$1932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6507$2071_Y - connect \B $eq$ls180.v:6507$2072_Y - connect \Y $and$ls180.v:6507$2073_Y + connect \A $and$ls180.v:6313$1930_Y + connect \B $eq$ls180.v:6313$1931_Y + connect \Y $and$ls180.v:6313$1932_Y end - attribute \src "ls180.v:6509.49-6509.102" - cell $and $and$ls180.v:6509$2074 + attribute \src "ls180.v:6315.49-6315.102" + cell $and $and$ls180.v:6315$1933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265082,43 +263370,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6509$2074_Y + connect \Y $and$ls180.v:6315$1933_Y end - attribute \src "ls180.v:6509.48-6509.152" - cell $and $and$ls180.v:6509$2076 + attribute \src "ls180.v:6315.48-6315.152" + cell $and $and$ls180.v:6315$1935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6509$2074_Y - connect \B $eq$ls180.v:6509$2075_Y - connect \Y $and$ls180.v:6509$2076_Y + connect \A $and$ls180.v:6315$1933_Y + connect \B $eq$ls180.v:6315$1934_Y + connect \Y $and$ls180.v:6315$1935_Y end - attribute \src "ls180.v:6510.49-6510.105" - cell $and $and$ls180.v:6510$2078 + attribute \src "ls180.v:6316.49-6316.105" + cell $and $and$ls180.v:6316$1937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6510$2077_Y - connect \Y $and$ls180.v:6510$2078_Y + connect \B $not$ls180.v:6316$1936_Y + connect \Y $and$ls180.v:6316$1937_Y end - attribute \src "ls180.v:6510.48-6510.155" - cell $and $and$ls180.v:6510$2080 + attribute \src "ls180.v:6316.48-6316.155" + cell $and $and$ls180.v:6316$1939 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6510$2078_Y - connect \B $eq$ls180.v:6510$2079_Y - connect \Y $and$ls180.v:6510$2080_Y + connect \A $and$ls180.v:6316$1937_Y + connect \B $eq$ls180.v:6316$1938_Y + connect \Y $and$ls180.v:6316$1939_Y end - attribute \src "ls180.v:6512.49-6512.102" - cell $and $and$ls180.v:6512$2081 + attribute \src "ls180.v:6318.49-6318.102" + cell $and $and$ls180.v:6318$1940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265126,43 +263414,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6512$2081_Y + connect \Y $and$ls180.v:6318$1940_Y end - attribute \src "ls180.v:6512.48-6512.152" - cell $and $and$ls180.v:6512$2083 + attribute \src "ls180.v:6318.48-6318.152" + cell $and $and$ls180.v:6318$1942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6512$2081_Y - connect \B $eq$ls180.v:6512$2082_Y - connect \Y $and$ls180.v:6512$2083_Y + connect \A $and$ls180.v:6318$1940_Y + connect \B $eq$ls180.v:6318$1941_Y + connect \Y $and$ls180.v:6318$1942_Y end - attribute \src "ls180.v:6513.49-6513.105" - cell $and $and$ls180.v:6513$2085 + attribute \src "ls180.v:6319.49-6319.105" + cell $and $and$ls180.v:6319$1944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6513$2084_Y - connect \Y $and$ls180.v:6513$2085_Y + connect \B $not$ls180.v:6319$1943_Y + connect \Y $and$ls180.v:6319$1944_Y end - attribute \src "ls180.v:6513.48-6513.155" - cell $and $and$ls180.v:6513$2087 + attribute \src "ls180.v:6319.48-6319.155" + cell $and $and$ls180.v:6319$1946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6513$2085_Y - connect \B $eq$ls180.v:6513$2086_Y - connect \Y $and$ls180.v:6513$2087_Y + connect \A $and$ls180.v:6319$1944_Y + connect \B $eq$ls180.v:6319$1945_Y + connect \Y $and$ls180.v:6319$1946_Y end - attribute \src "ls180.v:6515.49-6515.102" - cell $and $and$ls180.v:6515$2088 + attribute \src "ls180.v:6321.49-6321.102" + cell $and $and$ls180.v:6321$1947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265170,43 +263458,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6515$2088_Y + connect \Y $and$ls180.v:6321$1947_Y end - attribute \src "ls180.v:6515.48-6515.152" - cell $and $and$ls180.v:6515$2090 + attribute \src "ls180.v:6321.48-6321.152" + cell $and $and$ls180.v:6321$1949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6515$2088_Y - connect \B $eq$ls180.v:6515$2089_Y - connect \Y $and$ls180.v:6515$2090_Y + connect \A $and$ls180.v:6321$1947_Y + connect \B $eq$ls180.v:6321$1948_Y + connect \Y $and$ls180.v:6321$1949_Y end - attribute \src "ls180.v:6516.49-6516.105" - cell $and $and$ls180.v:6516$2092 + attribute \src "ls180.v:6322.49-6322.105" + cell $and $and$ls180.v:6322$1951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6516$2091_Y - connect \Y $and$ls180.v:6516$2092_Y + connect \B $not$ls180.v:6322$1950_Y + connect \Y $and$ls180.v:6322$1951_Y end - attribute \src "ls180.v:6516.48-6516.155" - cell $and $and$ls180.v:6516$2094 + attribute \src "ls180.v:6322.48-6322.155" + cell $and $and$ls180.v:6322$1953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6516$2092_Y - connect \B $eq$ls180.v:6516$2093_Y - connect \Y $and$ls180.v:6516$2094_Y + connect \A $and$ls180.v:6322$1951_Y + connect \B $eq$ls180.v:6322$1952_Y + connect \Y $and$ls180.v:6322$1953_Y end - attribute \src "ls180.v:6518.49-6518.102" - cell $and $and$ls180.v:6518$2095 + attribute \src "ls180.v:6324.49-6324.102" + cell $and $and$ls180.v:6324$1954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265214,43 +263502,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6518$2095_Y + connect \Y $and$ls180.v:6324$1954_Y end - attribute \src "ls180.v:6518.48-6518.152" - cell $and $and$ls180.v:6518$2097 + attribute \src "ls180.v:6324.48-6324.152" + cell $and $and$ls180.v:6324$1956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6518$2095_Y - connect \B $eq$ls180.v:6518$2096_Y - connect \Y $and$ls180.v:6518$2097_Y + connect \A $and$ls180.v:6324$1954_Y + connect \B $eq$ls180.v:6324$1955_Y + connect \Y $and$ls180.v:6324$1956_Y end - attribute \src "ls180.v:6519.49-6519.105" - cell $and $and$ls180.v:6519$2099 + attribute \src "ls180.v:6325.49-6325.105" + cell $and $and$ls180.v:6325$1958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6519$2098_Y - connect \Y $and$ls180.v:6519$2099_Y + connect \B $not$ls180.v:6325$1957_Y + connect \Y $and$ls180.v:6325$1958_Y end - attribute \src "ls180.v:6519.48-6519.155" - cell $and $and$ls180.v:6519$2101 + attribute \src "ls180.v:6325.48-6325.155" + cell $and $and$ls180.v:6325$1960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6519$2099_Y - connect \B $eq$ls180.v:6519$2100_Y - connect \Y $and$ls180.v:6519$2101_Y + connect \A $and$ls180.v:6325$1958_Y + connect \B $eq$ls180.v:6325$1959_Y + connect \Y $and$ls180.v:6325$1960_Y end - attribute \src "ls180.v:6536.42-6536.97" - cell $and $and$ls180.v:6536$2103 + attribute \src "ls180.v:6342.42-6342.97" + cell $and $and$ls180.v:6342$1962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265258,43 +263546,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6536$2103_Y + connect \Y $and$ls180.v:6342$1962_Y end - attribute \src "ls180.v:6536.41-6536.148" - cell $and $and$ls180.v:6536$2105 + attribute \src "ls180.v:6342.41-6342.148" + cell $and $and$ls180.v:6342$1964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6536$2103_Y - connect \B $eq$ls180.v:6536$2104_Y - connect \Y $and$ls180.v:6536$2105_Y + connect \A $and$ls180.v:6342$1962_Y + connect \B $eq$ls180.v:6342$1963_Y + connect \Y $and$ls180.v:6342$1964_Y end - attribute \src "ls180.v:6537.42-6537.100" - cell $and $and$ls180.v:6537$2107 + attribute \src "ls180.v:6343.42-6343.100" + cell $and $and$ls180.v:6343$1966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6537$2106_Y - connect \Y $and$ls180.v:6537$2107_Y + connect \B $not$ls180.v:6343$1965_Y + connect \Y $and$ls180.v:6343$1966_Y end - attribute \src "ls180.v:6537.41-6537.151" - cell $and $and$ls180.v:6537$2109 + attribute \src "ls180.v:6343.41-6343.151" + cell $and $and$ls180.v:6343$1968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6537$2107_Y - connect \B $eq$ls180.v:6537$2108_Y - connect \Y $and$ls180.v:6537$2109_Y + connect \A $and$ls180.v:6343$1966_Y + connect \B $eq$ls180.v:6343$1967_Y + connect \Y $and$ls180.v:6343$1968_Y end - attribute \src "ls180.v:6539.42-6539.97" - cell $and $and$ls180.v:6539$2110 + attribute \src "ls180.v:6345.42-6345.97" + cell $and $and$ls180.v:6345$1969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265302,43 +263590,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6539$2110_Y + connect \Y $and$ls180.v:6345$1969_Y end - attribute \src "ls180.v:6539.41-6539.148" - cell $and $and$ls180.v:6539$2112 + attribute \src "ls180.v:6345.41-6345.148" + cell $and $and$ls180.v:6345$1971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6539$2110_Y - connect \B $eq$ls180.v:6539$2111_Y - connect \Y $and$ls180.v:6539$2112_Y + connect \A $and$ls180.v:6345$1969_Y + connect \B $eq$ls180.v:6345$1970_Y + connect \Y $and$ls180.v:6345$1971_Y end - attribute \src "ls180.v:6540.42-6540.100" - cell $and $and$ls180.v:6540$2114 + attribute \src "ls180.v:6346.42-6346.100" + cell $and $and$ls180.v:6346$1973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6540$2113_Y - connect \Y $and$ls180.v:6540$2114_Y + connect \B $not$ls180.v:6346$1972_Y + connect \Y $and$ls180.v:6346$1973_Y end - attribute \src "ls180.v:6540.41-6540.151" - cell $and $and$ls180.v:6540$2116 + attribute \src "ls180.v:6346.41-6346.151" + cell $and $and$ls180.v:6346$1975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6540$2114_Y - connect \B $eq$ls180.v:6540$2115_Y - connect \Y $and$ls180.v:6540$2116_Y + connect \A $and$ls180.v:6346$1973_Y + connect \B $eq$ls180.v:6346$1974_Y + connect \Y $and$ls180.v:6346$1975_Y end - attribute \src "ls180.v:6542.40-6542.95" - cell $and $and$ls180.v:6542$2117 + attribute \src "ls180.v:6348.40-6348.95" + cell $and $and$ls180.v:6348$1976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265346,43 +263634,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6542$2117_Y + connect \Y $and$ls180.v:6348$1976_Y end - attribute \src "ls180.v:6542.39-6542.146" - cell $and $and$ls180.v:6542$2119 + attribute \src "ls180.v:6348.39-6348.146" + cell $and $and$ls180.v:6348$1978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6542$2117_Y - connect \B $eq$ls180.v:6542$2118_Y - connect \Y $and$ls180.v:6542$2119_Y + connect \A $and$ls180.v:6348$1976_Y + connect \B $eq$ls180.v:6348$1977_Y + connect \Y $and$ls180.v:6348$1978_Y end - attribute \src "ls180.v:6543.40-6543.98" - cell $and $and$ls180.v:6543$2121 + attribute \src "ls180.v:6349.40-6349.98" + cell $and $and$ls180.v:6349$1980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6543$2120_Y - connect \Y $and$ls180.v:6543$2121_Y + connect \B $not$ls180.v:6349$1979_Y + connect \Y $and$ls180.v:6349$1980_Y end - attribute \src "ls180.v:6543.39-6543.149" - cell $and $and$ls180.v:6543$2123 + attribute \src "ls180.v:6349.39-6349.149" + cell $and $and$ls180.v:6349$1982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6543$2121_Y - connect \B $eq$ls180.v:6543$2122_Y - connect \Y $and$ls180.v:6543$2123_Y + connect \A $and$ls180.v:6349$1980_Y + connect \B $eq$ls180.v:6349$1981_Y + connect \Y $and$ls180.v:6349$1982_Y end - attribute \src "ls180.v:6545.39-6545.94" - cell $and $and$ls180.v:6545$2124 + attribute \src "ls180.v:6351.39-6351.94" + cell $and $and$ls180.v:6351$1983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265390,43 +263678,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6545$2124_Y + connect \Y $and$ls180.v:6351$1983_Y end - attribute \src "ls180.v:6545.38-6545.145" - cell $and $and$ls180.v:6545$2126 + attribute \src "ls180.v:6351.38-6351.145" + cell $and $and$ls180.v:6351$1985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6545$2124_Y - connect \B $eq$ls180.v:6545$2125_Y - connect \Y $and$ls180.v:6545$2126_Y + connect \A $and$ls180.v:6351$1983_Y + connect \B $eq$ls180.v:6351$1984_Y + connect \Y $and$ls180.v:6351$1985_Y end - attribute \src "ls180.v:6546.39-6546.97" - cell $and $and$ls180.v:6546$2128 + attribute \src "ls180.v:6352.39-6352.97" + cell $and $and$ls180.v:6352$1987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6546$2127_Y - connect \Y $and$ls180.v:6546$2128_Y + connect \B $not$ls180.v:6352$1986_Y + connect \Y $and$ls180.v:6352$1987_Y end - attribute \src "ls180.v:6546.38-6546.148" - cell $and $and$ls180.v:6546$2130 + attribute \src "ls180.v:6352.38-6352.148" + cell $and $and$ls180.v:6352$1989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6546$2128_Y - connect \B $eq$ls180.v:6546$2129_Y - connect \Y $and$ls180.v:6546$2130_Y + connect \A $and$ls180.v:6352$1987_Y + connect \B $eq$ls180.v:6352$1988_Y + connect \Y $and$ls180.v:6352$1989_Y end - attribute \src "ls180.v:6548.38-6548.93" - cell $and $and$ls180.v:6548$2131 + attribute \src "ls180.v:6354.38-6354.93" + cell $and $and$ls180.v:6354$1990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265434,43 +263722,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6548$2131_Y + connect \Y $and$ls180.v:6354$1990_Y end - attribute \src "ls180.v:6548.37-6548.144" - cell $and $and$ls180.v:6548$2133 + attribute \src "ls180.v:6354.37-6354.144" + cell $and $and$ls180.v:6354$1992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6548$2131_Y - connect \B $eq$ls180.v:6548$2132_Y - connect \Y $and$ls180.v:6548$2133_Y + connect \A $and$ls180.v:6354$1990_Y + connect \B $eq$ls180.v:6354$1991_Y + connect \Y $and$ls180.v:6354$1992_Y end - attribute \src "ls180.v:6549.38-6549.96" - cell $and $and$ls180.v:6549$2135 + attribute \src "ls180.v:6355.38-6355.96" + cell $and $and$ls180.v:6355$1994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6549$2134_Y - connect \Y $and$ls180.v:6549$2135_Y + connect \B $not$ls180.v:6355$1993_Y + connect \Y $and$ls180.v:6355$1994_Y end - attribute \src "ls180.v:6549.37-6549.147" - cell $and $and$ls180.v:6549$2137 + attribute \src "ls180.v:6355.37-6355.147" + cell $and $and$ls180.v:6355$1996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6549$2135_Y - connect \B $eq$ls180.v:6549$2136_Y - connect \Y $and$ls180.v:6549$2137_Y + connect \A $and$ls180.v:6355$1994_Y + connect \B $eq$ls180.v:6355$1995_Y + connect \Y $and$ls180.v:6355$1996_Y end - attribute \src "ls180.v:6551.37-6551.92" - cell $and $and$ls180.v:6551$2138 + attribute \src "ls180.v:6357.37-6357.92" + cell $and $and$ls180.v:6357$1997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265478,43 +263766,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6551$2138_Y + connect \Y $and$ls180.v:6357$1997_Y end - attribute \src "ls180.v:6551.36-6551.143" - cell $and $and$ls180.v:6551$2140 + attribute \src "ls180.v:6357.36-6357.143" + cell $and $and$ls180.v:6357$1999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6551$2138_Y - connect \B $eq$ls180.v:6551$2139_Y - connect \Y $and$ls180.v:6551$2140_Y + connect \A $and$ls180.v:6357$1997_Y + connect \B $eq$ls180.v:6357$1998_Y + connect \Y $and$ls180.v:6357$1999_Y end - attribute \src "ls180.v:6552.37-6552.95" - cell $and $and$ls180.v:6552$2142 + attribute \src "ls180.v:6358.37-6358.95" + cell $and $and$ls180.v:6358$2001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6552$2141_Y - connect \Y $and$ls180.v:6552$2142_Y + connect \B $not$ls180.v:6358$2000_Y + connect \Y $and$ls180.v:6358$2001_Y end - attribute \src "ls180.v:6552.36-6552.146" - cell $and $and$ls180.v:6552$2144 + attribute \src "ls180.v:6358.36-6358.146" + cell $and $and$ls180.v:6358$2003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6552$2142_Y - connect \B $eq$ls180.v:6552$2143_Y - connect \Y $and$ls180.v:6552$2144_Y + connect \A $and$ls180.v:6358$2001_Y + connect \B $eq$ls180.v:6358$2002_Y + connect \Y $and$ls180.v:6358$2003_Y end - attribute \src "ls180.v:6554.43-6554.98" - cell $and $and$ls180.v:6554$2145 + attribute \src "ls180.v:6360.43-6360.98" + cell $and $and$ls180.v:6360$2004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265522,43 +263810,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6554$2145_Y + connect \Y $and$ls180.v:6360$2004_Y end - attribute \src "ls180.v:6554.42-6554.149" - cell $and $and$ls180.v:6554$2147 + attribute \src "ls180.v:6360.42-6360.149" + cell $and $and$ls180.v:6360$2006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6554$2145_Y - connect \B $eq$ls180.v:6554$2146_Y - connect \Y $and$ls180.v:6554$2147_Y + connect \A $and$ls180.v:6360$2004_Y + connect \B $eq$ls180.v:6360$2005_Y + connect \Y $and$ls180.v:6360$2006_Y end - attribute \src "ls180.v:6555.43-6555.101" - cell $and $and$ls180.v:6555$2149 + attribute \src "ls180.v:6361.43-6361.101" + cell $and $and$ls180.v:6361$2008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6555$2148_Y - connect \Y $and$ls180.v:6555$2149_Y + connect \B $not$ls180.v:6361$2007_Y + connect \Y $and$ls180.v:6361$2008_Y end - attribute \src "ls180.v:6555.42-6555.152" - cell $and $and$ls180.v:6555$2151 + attribute \src "ls180.v:6361.42-6361.152" + cell $and $and$ls180.v:6361$2010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6555$2149_Y - connect \B $eq$ls180.v:6555$2150_Y - connect \Y $and$ls180.v:6555$2151_Y + connect \A $and$ls180.v:6361$2008_Y + connect \B $eq$ls180.v:6361$2009_Y + connect \Y $and$ls180.v:6361$2010_Y end - attribute \src "ls180.v:6576.42-6576.97" - cell $and $and$ls180.v:6576$2154 + attribute \src "ls180.v:6382.42-6382.97" + cell $and $and$ls180.v:6382$2013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265566,43 +263854,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6576$2154_Y + connect \Y $and$ls180.v:6382$2013_Y end - attribute \src "ls180.v:6576.41-6576.148" - cell $and $and$ls180.v:6576$2156 + attribute \src "ls180.v:6382.41-6382.148" + cell $and $and$ls180.v:6382$2015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6576$2154_Y - connect \B $eq$ls180.v:6576$2155_Y - connect \Y $and$ls180.v:6576$2156_Y + connect \A $and$ls180.v:6382$2013_Y + connect \B $eq$ls180.v:6382$2014_Y + connect \Y $and$ls180.v:6382$2015_Y end - attribute \src "ls180.v:6577.42-6577.100" - cell $and $and$ls180.v:6577$2158 + attribute \src "ls180.v:6383.42-6383.100" + cell $and $and$ls180.v:6383$2017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6577$2157_Y - connect \Y $and$ls180.v:6577$2158_Y + connect \B $not$ls180.v:6383$2016_Y + connect \Y $and$ls180.v:6383$2017_Y end - attribute \src "ls180.v:6577.41-6577.151" - cell $and $and$ls180.v:6577$2160 + attribute \src "ls180.v:6383.41-6383.151" + cell $and $and$ls180.v:6383$2019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6577$2158_Y - connect \B $eq$ls180.v:6577$2159_Y - connect \Y $and$ls180.v:6577$2160_Y + connect \A $and$ls180.v:6383$2017_Y + connect \B $eq$ls180.v:6383$2018_Y + connect \Y $and$ls180.v:6383$2019_Y end - attribute \src "ls180.v:6579.42-6579.97" - cell $and $and$ls180.v:6579$2161 + attribute \src "ls180.v:6385.42-6385.97" + cell $and $and$ls180.v:6385$2020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265610,43 +263898,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6579$2161_Y + connect \Y $and$ls180.v:6385$2020_Y end - attribute \src "ls180.v:6579.41-6579.148" - cell $and $and$ls180.v:6579$2163 + attribute \src "ls180.v:6385.41-6385.148" + cell $and $and$ls180.v:6385$2022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6579$2161_Y - connect \B $eq$ls180.v:6579$2162_Y - connect \Y $and$ls180.v:6579$2163_Y + connect \A $and$ls180.v:6385$2020_Y + connect \B $eq$ls180.v:6385$2021_Y + connect \Y $and$ls180.v:6385$2022_Y end - attribute \src "ls180.v:6580.42-6580.100" - cell $and $and$ls180.v:6580$2165 + attribute \src "ls180.v:6386.42-6386.100" + cell $and $and$ls180.v:6386$2024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6580$2164_Y - connect \Y $and$ls180.v:6580$2165_Y + connect \B $not$ls180.v:6386$2023_Y + connect \Y $and$ls180.v:6386$2024_Y end - attribute \src "ls180.v:6580.41-6580.151" - cell $and $and$ls180.v:6580$2167 + attribute \src "ls180.v:6386.41-6386.151" + cell $and $and$ls180.v:6386$2026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6580$2165_Y - connect \B $eq$ls180.v:6580$2166_Y - connect \Y $and$ls180.v:6580$2167_Y + connect \A $and$ls180.v:6386$2024_Y + connect \B $eq$ls180.v:6386$2025_Y + connect \Y $and$ls180.v:6386$2026_Y end - attribute \src "ls180.v:6582.40-6582.95" - cell $and $and$ls180.v:6582$2168 + attribute \src "ls180.v:6388.40-6388.95" + cell $and $and$ls180.v:6388$2027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265654,43 +263942,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6582$2168_Y + connect \Y $and$ls180.v:6388$2027_Y end - attribute \src "ls180.v:6582.39-6582.146" - cell $and $and$ls180.v:6582$2170 + attribute \src "ls180.v:6388.39-6388.146" + cell $and $and$ls180.v:6388$2029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6582$2168_Y - connect \B $eq$ls180.v:6582$2169_Y - connect \Y $and$ls180.v:6582$2170_Y + connect \A $and$ls180.v:6388$2027_Y + connect \B $eq$ls180.v:6388$2028_Y + connect \Y $and$ls180.v:6388$2029_Y end - attribute \src "ls180.v:6583.40-6583.98" - cell $and $and$ls180.v:6583$2172 + attribute \src "ls180.v:6389.40-6389.98" + cell $and $and$ls180.v:6389$2031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6583$2171_Y - connect \Y $and$ls180.v:6583$2172_Y + connect \B $not$ls180.v:6389$2030_Y + connect \Y $and$ls180.v:6389$2031_Y end - attribute \src "ls180.v:6583.39-6583.149" - cell $and $and$ls180.v:6583$2174 + attribute \src "ls180.v:6389.39-6389.149" + cell $and $and$ls180.v:6389$2033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6583$2172_Y - connect \B $eq$ls180.v:6583$2173_Y - connect \Y $and$ls180.v:6583$2174_Y + connect \A $and$ls180.v:6389$2031_Y + connect \B $eq$ls180.v:6389$2032_Y + connect \Y $and$ls180.v:6389$2033_Y end - attribute \src "ls180.v:6585.39-6585.94" - cell $and $and$ls180.v:6585$2175 + attribute \src "ls180.v:6391.39-6391.94" + cell $and $and$ls180.v:6391$2034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265698,43 +263986,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6585$2175_Y + connect \Y $and$ls180.v:6391$2034_Y end - attribute \src "ls180.v:6585.38-6585.145" - cell $and $and$ls180.v:6585$2177 + attribute \src "ls180.v:6391.38-6391.145" + cell $and $and$ls180.v:6391$2036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6585$2175_Y - connect \B $eq$ls180.v:6585$2176_Y - connect \Y $and$ls180.v:6585$2177_Y + connect \A $and$ls180.v:6391$2034_Y + connect \B $eq$ls180.v:6391$2035_Y + connect \Y $and$ls180.v:6391$2036_Y end - attribute \src "ls180.v:6586.39-6586.97" - cell $and $and$ls180.v:6586$2179 + attribute \src "ls180.v:6392.39-6392.97" + cell $and $and$ls180.v:6392$2038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6586$2178_Y - connect \Y $and$ls180.v:6586$2179_Y + connect \B $not$ls180.v:6392$2037_Y + connect \Y $and$ls180.v:6392$2038_Y end - attribute \src "ls180.v:6586.38-6586.148" - cell $and $and$ls180.v:6586$2181 + attribute \src "ls180.v:6392.38-6392.148" + cell $and $and$ls180.v:6392$2040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6586$2179_Y - connect \B $eq$ls180.v:6586$2180_Y - connect \Y $and$ls180.v:6586$2181_Y + connect \A $and$ls180.v:6392$2038_Y + connect \B $eq$ls180.v:6392$2039_Y + connect \Y $and$ls180.v:6392$2040_Y end - attribute \src "ls180.v:6588.38-6588.93" - cell $and $and$ls180.v:6588$2182 + attribute \src "ls180.v:6394.38-6394.93" + cell $and $and$ls180.v:6394$2041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265742,43 +264030,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6588$2182_Y + connect \Y $and$ls180.v:6394$2041_Y end - attribute \src "ls180.v:6588.37-6588.144" - cell $and $and$ls180.v:6588$2184 + attribute \src "ls180.v:6394.37-6394.144" + cell $and $and$ls180.v:6394$2043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6588$2182_Y - connect \B $eq$ls180.v:6588$2183_Y - connect \Y $and$ls180.v:6588$2184_Y + connect \A $and$ls180.v:6394$2041_Y + connect \B $eq$ls180.v:6394$2042_Y + connect \Y $and$ls180.v:6394$2043_Y end - attribute \src "ls180.v:6589.38-6589.96" - cell $and $and$ls180.v:6589$2186 + attribute \src "ls180.v:6395.38-6395.96" + cell $and $and$ls180.v:6395$2045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6589$2185_Y - connect \Y $and$ls180.v:6589$2186_Y + connect \B $not$ls180.v:6395$2044_Y + connect \Y $and$ls180.v:6395$2045_Y end - attribute \src "ls180.v:6589.37-6589.147" - cell $and $and$ls180.v:6589$2188 + attribute \src "ls180.v:6395.37-6395.147" + cell $and $and$ls180.v:6395$2047 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6589$2186_Y - connect \B $eq$ls180.v:6589$2187_Y - connect \Y $and$ls180.v:6589$2188_Y + connect \A $and$ls180.v:6395$2045_Y + connect \B $eq$ls180.v:6395$2046_Y + connect \Y $and$ls180.v:6395$2047_Y end - attribute \src "ls180.v:6591.37-6591.92" - cell $and $and$ls180.v:6591$2189 + attribute \src "ls180.v:6397.37-6397.92" + cell $and $and$ls180.v:6397$2048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265786,43 +264074,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6591$2189_Y + connect \Y $and$ls180.v:6397$2048_Y end - attribute \src "ls180.v:6591.36-6591.143" - cell $and $and$ls180.v:6591$2191 + attribute \src "ls180.v:6397.36-6397.143" + cell $and $and$ls180.v:6397$2050 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6591$2189_Y - connect \B $eq$ls180.v:6591$2190_Y - connect \Y $and$ls180.v:6591$2191_Y + connect \A $and$ls180.v:6397$2048_Y + connect \B $eq$ls180.v:6397$2049_Y + connect \Y $and$ls180.v:6397$2050_Y end - attribute \src "ls180.v:6592.37-6592.95" - cell $and $and$ls180.v:6592$2193 + attribute \src "ls180.v:6398.37-6398.95" + cell $and $and$ls180.v:6398$2052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6592$2192_Y - connect \Y $and$ls180.v:6592$2193_Y + connect \B $not$ls180.v:6398$2051_Y + connect \Y $and$ls180.v:6398$2052_Y end - attribute \src "ls180.v:6592.36-6592.146" - cell $and $and$ls180.v:6592$2195 + attribute \src "ls180.v:6398.36-6398.146" + cell $and $and$ls180.v:6398$2054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6592$2193_Y - connect \B $eq$ls180.v:6592$2194_Y - connect \Y $and$ls180.v:6592$2195_Y + connect \A $and$ls180.v:6398$2052_Y + connect \B $eq$ls180.v:6398$2053_Y + connect \Y $and$ls180.v:6398$2054_Y end - attribute \src "ls180.v:6594.43-6594.98" - cell $and $and$ls180.v:6594$2196 + attribute \src "ls180.v:6400.43-6400.98" + cell $and $and$ls180.v:6400$2055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265830,43 +264118,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6594$2196_Y + connect \Y $and$ls180.v:6400$2055_Y end - attribute \src "ls180.v:6594.42-6594.149" - cell $and $and$ls180.v:6594$2198 + attribute \src "ls180.v:6400.42-6400.149" + cell $and $and$ls180.v:6400$2057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6594$2196_Y - connect \B $eq$ls180.v:6594$2197_Y - connect \Y $and$ls180.v:6594$2198_Y + connect \A $and$ls180.v:6400$2055_Y + connect \B $eq$ls180.v:6400$2056_Y + connect \Y $and$ls180.v:6400$2057_Y end - attribute \src "ls180.v:6595.43-6595.101" - cell $and $and$ls180.v:6595$2200 + attribute \src "ls180.v:6401.43-6401.101" + cell $and $and$ls180.v:6401$2059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6595$2199_Y - connect \Y $and$ls180.v:6595$2200_Y + connect \B $not$ls180.v:6401$2058_Y + connect \Y $and$ls180.v:6401$2059_Y end - attribute \src "ls180.v:6595.42-6595.152" - cell $and $and$ls180.v:6595$2202 + attribute \src "ls180.v:6401.42-6401.152" + cell $and $and$ls180.v:6401$2061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6595$2200_Y - connect \B $eq$ls180.v:6595$2201_Y - connect \Y $and$ls180.v:6595$2202_Y + connect \A $and$ls180.v:6401$2059_Y + connect \B $eq$ls180.v:6401$2060_Y + connect \Y $and$ls180.v:6401$2061_Y end - attribute \src "ls180.v:6597.46-6597.101" - cell $and $and$ls180.v:6597$2203 + attribute \src "ls180.v:6403.46-6403.101" + cell $and $and$ls180.v:6403$2062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265874,43 +264162,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6597$2203_Y + connect \Y $and$ls180.v:6403$2062_Y end - attribute \src "ls180.v:6597.45-6597.152" - cell $and $and$ls180.v:6597$2205 + attribute \src "ls180.v:6403.45-6403.152" + cell $and $and$ls180.v:6403$2064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6597$2203_Y - connect \B $eq$ls180.v:6597$2204_Y - connect \Y $and$ls180.v:6597$2205_Y + connect \A $and$ls180.v:6403$2062_Y + connect \B $eq$ls180.v:6403$2063_Y + connect \Y $and$ls180.v:6403$2064_Y end - attribute \src "ls180.v:6598.46-6598.104" - cell $and $and$ls180.v:6598$2207 + attribute \src "ls180.v:6404.46-6404.104" + cell $and $and$ls180.v:6404$2066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6598$2206_Y - connect \Y $and$ls180.v:6598$2207_Y + connect \B $not$ls180.v:6404$2065_Y + connect \Y $and$ls180.v:6404$2066_Y end - attribute \src "ls180.v:6598.45-6598.155" - cell $and $and$ls180.v:6598$2209 + attribute \src "ls180.v:6404.45-6404.155" + cell $and $and$ls180.v:6404$2068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6598$2207_Y - connect \B $eq$ls180.v:6598$2208_Y - connect \Y $and$ls180.v:6598$2209_Y + connect \A $and$ls180.v:6404$2066_Y + connect \B $eq$ls180.v:6404$2067_Y + connect \Y $and$ls180.v:6404$2068_Y end - attribute \src "ls180.v:6600.46-6600.101" - cell $and $and$ls180.v:6600$2210 + attribute \src "ls180.v:6406.46-6406.101" + cell $and $and$ls180.v:6406$2069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265918,43 +264206,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6600$2210_Y + connect \Y $and$ls180.v:6406$2069_Y end - attribute \src "ls180.v:6600.45-6600.152" - cell $and $and$ls180.v:6600$2212 + attribute \src "ls180.v:6406.45-6406.152" + cell $and $and$ls180.v:6406$2071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6600$2210_Y - connect \B $eq$ls180.v:6600$2211_Y - connect \Y $and$ls180.v:6600$2212_Y + connect \A $and$ls180.v:6406$2069_Y + connect \B $eq$ls180.v:6406$2070_Y + connect \Y $and$ls180.v:6406$2071_Y end - attribute \src "ls180.v:6601.46-6601.104" - cell $and $and$ls180.v:6601$2214 + attribute \src "ls180.v:6407.46-6407.104" + cell $and $and$ls180.v:6407$2073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6601$2213_Y - connect \Y $and$ls180.v:6601$2214_Y + connect \B $not$ls180.v:6407$2072_Y + connect \Y $and$ls180.v:6407$2073_Y end - attribute \src "ls180.v:6601.45-6601.155" - cell $and $and$ls180.v:6601$2216 + attribute \src "ls180.v:6407.45-6407.155" + cell $and $and$ls180.v:6407$2075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6601$2214_Y - connect \B $eq$ls180.v:6601$2215_Y - connect \Y $and$ls180.v:6601$2216_Y + connect \A $and$ls180.v:6407$2073_Y + connect \B $eq$ls180.v:6407$2074_Y + connect \Y $and$ls180.v:6407$2075_Y end - attribute \src "ls180.v:6624.39-6624.94" - cell $and $and$ls180.v:6624$2219 + attribute \src "ls180.v:6430.39-6430.94" + cell $and $and$ls180.v:6430$2078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -265962,43 +264250,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6624$2219_Y + connect \Y $and$ls180.v:6430$2078_Y end - attribute \src "ls180.v:6624.38-6624.145" - cell $and $and$ls180.v:6624$2221 + attribute \src "ls180.v:6430.38-6430.145" + cell $and $and$ls180.v:6430$2080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6624$2219_Y - connect \B $eq$ls180.v:6624$2220_Y - connect \Y $and$ls180.v:6624$2221_Y + connect \A $and$ls180.v:6430$2078_Y + connect \B $eq$ls180.v:6430$2079_Y + connect \Y $and$ls180.v:6430$2080_Y end - attribute \src "ls180.v:6625.39-6625.97" - cell $and $and$ls180.v:6625$2223 + attribute \src "ls180.v:6431.39-6431.97" + cell $and $and$ls180.v:6431$2082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6625$2222_Y - connect \Y $and$ls180.v:6625$2223_Y + connect \B $not$ls180.v:6431$2081_Y + connect \Y $and$ls180.v:6431$2082_Y end - attribute \src "ls180.v:6625.38-6625.148" - cell $and $and$ls180.v:6625$2225 + attribute \src "ls180.v:6431.38-6431.148" + cell $and $and$ls180.v:6431$2084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6625$2223_Y - connect \B $eq$ls180.v:6625$2224_Y - connect \Y $and$ls180.v:6625$2225_Y + connect \A $and$ls180.v:6431$2082_Y + connect \B $eq$ls180.v:6431$2083_Y + connect \Y $and$ls180.v:6431$2084_Y end - attribute \src "ls180.v:6627.39-6627.94" - cell $and $and$ls180.v:6627$2226 + attribute \src "ls180.v:6433.39-6433.94" + cell $and $and$ls180.v:6433$2085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266006,43 +264294,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6627$2226_Y + connect \Y $and$ls180.v:6433$2085_Y end - attribute \src "ls180.v:6627.38-6627.145" - cell $and $and$ls180.v:6627$2228 + attribute \src "ls180.v:6433.38-6433.145" + cell $and $and$ls180.v:6433$2087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6627$2226_Y - connect \B $eq$ls180.v:6627$2227_Y - connect \Y $and$ls180.v:6627$2228_Y + connect \A $and$ls180.v:6433$2085_Y + connect \B $eq$ls180.v:6433$2086_Y + connect \Y $and$ls180.v:6433$2087_Y end - attribute \src "ls180.v:6628.39-6628.97" - cell $and $and$ls180.v:6628$2230 + attribute \src "ls180.v:6434.39-6434.97" + cell $and $and$ls180.v:6434$2089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6628$2229_Y - connect \Y $and$ls180.v:6628$2230_Y + connect \B $not$ls180.v:6434$2088_Y + connect \Y $and$ls180.v:6434$2089_Y end - attribute \src "ls180.v:6628.38-6628.148" - cell $and $and$ls180.v:6628$2232 + attribute \src "ls180.v:6434.38-6434.148" + cell $and $and$ls180.v:6434$2091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6628$2230_Y - connect \B $eq$ls180.v:6628$2231_Y - connect \Y $and$ls180.v:6628$2232_Y + connect \A $and$ls180.v:6434$2089_Y + connect \B $eq$ls180.v:6434$2090_Y + connect \Y $and$ls180.v:6434$2091_Y end - attribute \src "ls180.v:6630.39-6630.94" - cell $and $and$ls180.v:6630$2233 + attribute \src "ls180.v:6436.39-6436.94" + cell $and $and$ls180.v:6436$2092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266050,43 +264338,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6630$2233_Y + connect \Y $and$ls180.v:6436$2092_Y end - attribute \src "ls180.v:6630.38-6630.145" - cell $and $and$ls180.v:6630$2235 + attribute \src "ls180.v:6436.38-6436.145" + cell $and $and$ls180.v:6436$2094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6630$2233_Y - connect \B $eq$ls180.v:6630$2234_Y - connect \Y $and$ls180.v:6630$2235_Y + connect \A $and$ls180.v:6436$2092_Y + connect \B $eq$ls180.v:6436$2093_Y + connect \Y $and$ls180.v:6436$2094_Y end - attribute \src "ls180.v:6631.39-6631.97" - cell $and $and$ls180.v:6631$2237 + attribute \src "ls180.v:6437.39-6437.97" + cell $and $and$ls180.v:6437$2096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6631$2236_Y - connect \Y $and$ls180.v:6631$2237_Y + connect \B $not$ls180.v:6437$2095_Y + connect \Y $and$ls180.v:6437$2096_Y end - attribute \src "ls180.v:6631.38-6631.148" - cell $and $and$ls180.v:6631$2239 + attribute \src "ls180.v:6437.38-6437.148" + cell $and $and$ls180.v:6437$2098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6631$2237_Y - connect \B $eq$ls180.v:6631$2238_Y - connect \Y $and$ls180.v:6631$2239_Y + connect \A $and$ls180.v:6437$2096_Y + connect \B $eq$ls180.v:6437$2097_Y + connect \Y $and$ls180.v:6437$2098_Y end - attribute \src "ls180.v:6633.39-6633.94" - cell $and $and$ls180.v:6633$2240 + attribute \src "ls180.v:6439.39-6439.94" + cell $and $and$ls180.v:6439$2099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266094,43 +264382,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6633$2240_Y + connect \Y $and$ls180.v:6439$2099_Y end - attribute \src "ls180.v:6633.38-6633.145" - cell $and $and$ls180.v:6633$2242 + attribute \src "ls180.v:6439.38-6439.145" + cell $and $and$ls180.v:6439$2101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6633$2240_Y - connect \B $eq$ls180.v:6633$2241_Y - connect \Y $and$ls180.v:6633$2242_Y + connect \A $and$ls180.v:6439$2099_Y + connect \B $eq$ls180.v:6439$2100_Y + connect \Y $and$ls180.v:6439$2101_Y end - attribute \src "ls180.v:6634.39-6634.97" - cell $and $and$ls180.v:6634$2244 + attribute \src "ls180.v:6440.39-6440.97" + cell $and $and$ls180.v:6440$2103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6634$2243_Y - connect \Y $and$ls180.v:6634$2244_Y + connect \B $not$ls180.v:6440$2102_Y + connect \Y $and$ls180.v:6440$2103_Y end - attribute \src "ls180.v:6634.38-6634.148" - cell $and $and$ls180.v:6634$2246 + attribute \src "ls180.v:6440.38-6440.148" + cell $and $and$ls180.v:6440$2105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6634$2244_Y - connect \B $eq$ls180.v:6634$2245_Y - connect \Y $and$ls180.v:6634$2246_Y + connect \A $and$ls180.v:6440$2103_Y + connect \B $eq$ls180.v:6440$2104_Y + connect \Y $and$ls180.v:6440$2105_Y end - attribute \src "ls180.v:6636.41-6636.96" - cell $and $and$ls180.v:6636$2247 + attribute \src "ls180.v:6442.41-6442.96" + cell $and $and$ls180.v:6442$2106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266138,43 +264426,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6636$2247_Y + connect \Y $and$ls180.v:6442$2106_Y end - attribute \src "ls180.v:6636.40-6636.147" - cell $and $and$ls180.v:6636$2249 + attribute \src "ls180.v:6442.40-6442.147" + cell $and $and$ls180.v:6442$2108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6636$2247_Y - connect \B $eq$ls180.v:6636$2248_Y - connect \Y $and$ls180.v:6636$2249_Y + connect \A $and$ls180.v:6442$2106_Y + connect \B $eq$ls180.v:6442$2107_Y + connect \Y $and$ls180.v:6442$2108_Y end - attribute \src "ls180.v:6637.41-6637.99" - cell $and $and$ls180.v:6637$2251 + attribute \src "ls180.v:6443.41-6443.99" + cell $and $and$ls180.v:6443$2110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6637$2250_Y - connect \Y $and$ls180.v:6637$2251_Y + connect \B $not$ls180.v:6443$2109_Y + connect \Y $and$ls180.v:6443$2110_Y end - attribute \src "ls180.v:6637.40-6637.150" - cell $and $and$ls180.v:6637$2253 + attribute \src "ls180.v:6443.40-6443.150" + cell $and $and$ls180.v:6443$2112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6637$2251_Y - connect \B $eq$ls180.v:6637$2252_Y - connect \Y $and$ls180.v:6637$2253_Y + connect \A $and$ls180.v:6443$2110_Y + connect \B $eq$ls180.v:6443$2111_Y + connect \Y $and$ls180.v:6443$2112_Y end - attribute \src "ls180.v:6639.41-6639.96" - cell $and $and$ls180.v:6639$2254 + attribute \src "ls180.v:6445.41-6445.96" + cell $and $and$ls180.v:6445$2113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266182,43 +264470,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6639$2254_Y + connect \Y $and$ls180.v:6445$2113_Y end - attribute \src "ls180.v:6639.40-6639.147" - cell $and $and$ls180.v:6639$2256 + attribute \src "ls180.v:6445.40-6445.147" + cell $and $and$ls180.v:6445$2115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6639$2254_Y - connect \B $eq$ls180.v:6639$2255_Y - connect \Y $and$ls180.v:6639$2256_Y + connect \A $and$ls180.v:6445$2113_Y + connect \B $eq$ls180.v:6445$2114_Y + connect \Y $and$ls180.v:6445$2115_Y end - attribute \src "ls180.v:6640.41-6640.99" - cell $and $and$ls180.v:6640$2258 + attribute \src "ls180.v:6446.41-6446.99" + cell $and $and$ls180.v:6446$2117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6640$2257_Y - connect \Y $and$ls180.v:6640$2258_Y + connect \B $not$ls180.v:6446$2116_Y + connect \Y $and$ls180.v:6446$2117_Y end - attribute \src "ls180.v:6640.40-6640.150" - cell $and $and$ls180.v:6640$2260 + attribute \src "ls180.v:6446.40-6446.150" + cell $and $and$ls180.v:6446$2119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6640$2258_Y - connect \B $eq$ls180.v:6640$2259_Y - connect \Y $and$ls180.v:6640$2260_Y + connect \A $and$ls180.v:6446$2117_Y + connect \B $eq$ls180.v:6446$2118_Y + connect \Y $and$ls180.v:6446$2119_Y end - attribute \src "ls180.v:6642.41-6642.96" - cell $and $and$ls180.v:6642$2261 + attribute \src "ls180.v:6448.41-6448.96" + cell $and $and$ls180.v:6448$2120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266226,43 +264514,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6642$2261_Y + connect \Y $and$ls180.v:6448$2120_Y end - attribute \src "ls180.v:6642.40-6642.147" - cell $and $and$ls180.v:6642$2263 + attribute \src "ls180.v:6448.40-6448.147" + cell $and $and$ls180.v:6448$2122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6642$2261_Y - connect \B $eq$ls180.v:6642$2262_Y - connect \Y $and$ls180.v:6642$2263_Y + connect \A $and$ls180.v:6448$2120_Y + connect \B $eq$ls180.v:6448$2121_Y + connect \Y $and$ls180.v:6448$2122_Y end - attribute \src "ls180.v:6643.41-6643.99" - cell $and $and$ls180.v:6643$2265 + attribute \src "ls180.v:6449.41-6449.99" + cell $and $and$ls180.v:6449$2124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6643$2264_Y - connect \Y $and$ls180.v:6643$2265_Y + connect \B $not$ls180.v:6449$2123_Y + connect \Y $and$ls180.v:6449$2124_Y end - attribute \src "ls180.v:6643.40-6643.150" - cell $and $and$ls180.v:6643$2267 + attribute \src "ls180.v:6449.40-6449.150" + cell $and $and$ls180.v:6449$2126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6643$2265_Y - connect \B $eq$ls180.v:6643$2266_Y - connect \Y $and$ls180.v:6643$2267_Y + connect \A $and$ls180.v:6449$2124_Y + connect \B $eq$ls180.v:6449$2125_Y + connect \Y $and$ls180.v:6449$2126_Y end - attribute \src "ls180.v:6645.41-6645.96" - cell $and $and$ls180.v:6645$2268 + attribute \src "ls180.v:6451.41-6451.96" + cell $and $and$ls180.v:6451$2127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266270,43 +264558,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6645$2268_Y + connect \Y $and$ls180.v:6451$2127_Y end - attribute \src "ls180.v:6645.40-6645.147" - cell $and $and$ls180.v:6645$2270 + attribute \src "ls180.v:6451.40-6451.147" + cell $and $and$ls180.v:6451$2129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6645$2268_Y - connect \B $eq$ls180.v:6645$2269_Y - connect \Y $and$ls180.v:6645$2270_Y + connect \A $and$ls180.v:6451$2127_Y + connect \B $eq$ls180.v:6451$2128_Y + connect \Y $and$ls180.v:6451$2129_Y end - attribute \src "ls180.v:6646.41-6646.99" - cell $and $and$ls180.v:6646$2272 + attribute \src "ls180.v:6452.41-6452.99" + cell $and $and$ls180.v:6452$2131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6646$2271_Y - connect \Y $and$ls180.v:6646$2272_Y + connect \B $not$ls180.v:6452$2130_Y + connect \Y $and$ls180.v:6452$2131_Y end - attribute \src "ls180.v:6646.40-6646.150" - cell $and $and$ls180.v:6646$2274 + attribute \src "ls180.v:6452.40-6452.150" + cell $and $and$ls180.v:6452$2133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6646$2272_Y - connect \B $eq$ls180.v:6646$2273_Y - connect \Y $and$ls180.v:6646$2274_Y + connect \A $and$ls180.v:6452$2131_Y + connect \B $eq$ls180.v:6452$2132_Y + connect \Y $and$ls180.v:6452$2133_Y end - attribute \src "ls180.v:6648.37-6648.92" - cell $and $and$ls180.v:6648$2275 + attribute \src "ls180.v:6454.37-6454.92" + cell $and $and$ls180.v:6454$2134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266314,43 +264602,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6648$2275_Y + connect \Y $and$ls180.v:6454$2134_Y end - attribute \src "ls180.v:6648.36-6648.143" - cell $and $and$ls180.v:6648$2277 + attribute \src "ls180.v:6454.36-6454.143" + cell $and $and$ls180.v:6454$2136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6648$2275_Y - connect \B $eq$ls180.v:6648$2276_Y - connect \Y $and$ls180.v:6648$2277_Y + connect \A $and$ls180.v:6454$2134_Y + connect \B $eq$ls180.v:6454$2135_Y + connect \Y $and$ls180.v:6454$2136_Y end - attribute \src "ls180.v:6649.37-6649.95" - cell $and $and$ls180.v:6649$2279 + attribute \src "ls180.v:6455.37-6455.95" + cell $and $and$ls180.v:6455$2138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6649$2278_Y - connect \Y $and$ls180.v:6649$2279_Y + connect \B $not$ls180.v:6455$2137_Y + connect \Y $and$ls180.v:6455$2138_Y end - attribute \src "ls180.v:6649.36-6649.146" - cell $and $and$ls180.v:6649$2281 + attribute \src "ls180.v:6455.36-6455.146" + cell $and $and$ls180.v:6455$2140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6649$2279_Y - connect \B $eq$ls180.v:6649$2280_Y - connect \Y $and$ls180.v:6649$2281_Y + connect \A $and$ls180.v:6455$2138_Y + connect \B $eq$ls180.v:6455$2139_Y + connect \Y $and$ls180.v:6455$2140_Y end - attribute \src "ls180.v:6651.47-6651.102" - cell $and $and$ls180.v:6651$2282 + attribute \src "ls180.v:6457.47-6457.102" + cell $and $and$ls180.v:6457$2141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266358,43 +264646,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6651$2282_Y + connect \Y $and$ls180.v:6457$2141_Y end - attribute \src "ls180.v:6651.46-6651.153" - cell $and $and$ls180.v:6651$2284 + attribute \src "ls180.v:6457.46-6457.153" + cell $and $and$ls180.v:6457$2143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6651$2282_Y - connect \B $eq$ls180.v:6651$2283_Y - connect \Y $and$ls180.v:6651$2284_Y + connect \A $and$ls180.v:6457$2141_Y + connect \B $eq$ls180.v:6457$2142_Y + connect \Y $and$ls180.v:6457$2143_Y end - attribute \src "ls180.v:6652.47-6652.105" - cell $and $and$ls180.v:6652$2286 + attribute \src "ls180.v:6458.47-6458.105" + cell $and $and$ls180.v:6458$2145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6652$2285_Y - connect \Y $and$ls180.v:6652$2286_Y + connect \B $not$ls180.v:6458$2144_Y + connect \Y $and$ls180.v:6458$2145_Y end - attribute \src "ls180.v:6652.46-6652.156" - cell $and $and$ls180.v:6652$2288 + attribute \src "ls180.v:6458.46-6458.156" + cell $and $and$ls180.v:6458$2147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6652$2286_Y - connect \B $eq$ls180.v:6652$2287_Y - connect \Y $and$ls180.v:6652$2288_Y + connect \A $and$ls180.v:6458$2145_Y + connect \B $eq$ls180.v:6458$2146_Y + connect \Y $and$ls180.v:6458$2147_Y end - attribute \src "ls180.v:6654.40-6654.95" - cell $and $and$ls180.v:6654$2289 + attribute \src "ls180.v:6460.40-6460.95" + cell $and $and$ls180.v:6460$2148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266402,43 +264690,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6654$2289_Y + connect \Y $and$ls180.v:6460$2148_Y end - attribute \src "ls180.v:6654.39-6654.147" - cell $and $and$ls180.v:6654$2291 + attribute \src "ls180.v:6460.39-6460.147" + cell $and $and$ls180.v:6460$2150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6654$2289_Y - connect \B $eq$ls180.v:6654$2290_Y - connect \Y $and$ls180.v:6654$2291_Y + connect \A $and$ls180.v:6460$2148_Y + connect \B $eq$ls180.v:6460$2149_Y + connect \Y $and$ls180.v:6460$2150_Y end - attribute \src "ls180.v:6655.40-6655.98" - cell $and $and$ls180.v:6655$2293 + attribute \src "ls180.v:6461.40-6461.98" + cell $and $and$ls180.v:6461$2152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6655$2292_Y - connect \Y $and$ls180.v:6655$2293_Y + connect \B $not$ls180.v:6461$2151_Y + connect \Y $and$ls180.v:6461$2152_Y end - attribute \src "ls180.v:6655.39-6655.150" - cell $and $and$ls180.v:6655$2295 + attribute \src "ls180.v:6461.39-6461.150" + cell $and $and$ls180.v:6461$2154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6655$2293_Y - connect \B $eq$ls180.v:6655$2294_Y - connect \Y $and$ls180.v:6655$2295_Y + connect \A $and$ls180.v:6461$2152_Y + connect \B $eq$ls180.v:6461$2153_Y + connect \Y $and$ls180.v:6461$2154_Y end - attribute \src "ls180.v:6657.40-6657.95" - cell $and $and$ls180.v:6657$2296 + attribute \src "ls180.v:6463.40-6463.95" + cell $and $and$ls180.v:6463$2155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266446,43 +264734,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6657$2296_Y + connect \Y $and$ls180.v:6463$2155_Y end - attribute \src "ls180.v:6657.39-6657.147" - cell $and $and$ls180.v:6657$2298 + attribute \src "ls180.v:6463.39-6463.147" + cell $and $and$ls180.v:6463$2157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6657$2296_Y - connect \B $eq$ls180.v:6657$2297_Y - connect \Y $and$ls180.v:6657$2298_Y + connect \A $and$ls180.v:6463$2155_Y + connect \B $eq$ls180.v:6463$2156_Y + connect \Y $and$ls180.v:6463$2157_Y end - attribute \src "ls180.v:6658.40-6658.98" - cell $and $and$ls180.v:6658$2300 + attribute \src "ls180.v:6464.40-6464.98" + cell $and $and$ls180.v:6464$2159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6658$2299_Y - connect \Y $and$ls180.v:6658$2300_Y + connect \B $not$ls180.v:6464$2158_Y + connect \Y $and$ls180.v:6464$2159_Y end - attribute \src "ls180.v:6658.39-6658.150" - cell $and $and$ls180.v:6658$2302 + attribute \src "ls180.v:6464.39-6464.150" + cell $and $and$ls180.v:6464$2161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6658$2300_Y - connect \B $eq$ls180.v:6658$2301_Y - connect \Y $and$ls180.v:6658$2302_Y + connect \A $and$ls180.v:6464$2159_Y + connect \B $eq$ls180.v:6464$2160_Y + connect \Y $and$ls180.v:6464$2161_Y end - attribute \src "ls180.v:6660.40-6660.95" - cell $and $and$ls180.v:6660$2303 + attribute \src "ls180.v:6466.40-6466.95" + cell $and $and$ls180.v:6466$2162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266490,43 +264778,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6660$2303_Y + connect \Y $and$ls180.v:6466$2162_Y end - attribute \src "ls180.v:6660.39-6660.147" - cell $and $and$ls180.v:6660$2305 + attribute \src "ls180.v:6466.39-6466.147" + cell $and $and$ls180.v:6466$2164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6660$2303_Y - connect \B $eq$ls180.v:6660$2304_Y - connect \Y $and$ls180.v:6660$2305_Y + connect \A $and$ls180.v:6466$2162_Y + connect \B $eq$ls180.v:6466$2163_Y + connect \Y $and$ls180.v:6466$2164_Y end - attribute \src "ls180.v:6661.40-6661.98" - cell $and $and$ls180.v:6661$2307 + attribute \src "ls180.v:6467.40-6467.98" + cell $and $and$ls180.v:6467$2166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6661$2306_Y - connect \Y $and$ls180.v:6661$2307_Y + connect \B $not$ls180.v:6467$2165_Y + connect \Y $and$ls180.v:6467$2166_Y end - attribute \src "ls180.v:6661.39-6661.150" - cell $and $and$ls180.v:6661$2309 + attribute \src "ls180.v:6467.39-6467.150" + cell $and $and$ls180.v:6467$2168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6661$2307_Y - connect \B $eq$ls180.v:6661$2308_Y - connect \Y $and$ls180.v:6661$2309_Y + connect \A $and$ls180.v:6467$2166_Y + connect \B $eq$ls180.v:6467$2167_Y + connect \Y $and$ls180.v:6467$2168_Y end - attribute \src "ls180.v:6663.40-6663.95" - cell $and $and$ls180.v:6663$2310 + attribute \src "ls180.v:6469.40-6469.95" + cell $and $and$ls180.v:6469$2169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266534,43 +264822,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6663$2310_Y + connect \Y $and$ls180.v:6469$2169_Y end - attribute \src "ls180.v:6663.39-6663.147" - cell $and $and$ls180.v:6663$2312 + attribute \src "ls180.v:6469.39-6469.147" + cell $and $and$ls180.v:6469$2171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6663$2310_Y - connect \B $eq$ls180.v:6663$2311_Y - connect \Y $and$ls180.v:6663$2312_Y + connect \A $and$ls180.v:6469$2169_Y + connect \B $eq$ls180.v:6469$2170_Y + connect \Y $and$ls180.v:6469$2171_Y end - attribute \src "ls180.v:6664.40-6664.98" - cell $and $and$ls180.v:6664$2314 + attribute \src "ls180.v:6470.40-6470.98" + cell $and $and$ls180.v:6470$2173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6664$2313_Y - connect \Y $and$ls180.v:6664$2314_Y + connect \B $not$ls180.v:6470$2172_Y + connect \Y $and$ls180.v:6470$2173_Y end - attribute \src "ls180.v:6664.39-6664.150" - cell $and $and$ls180.v:6664$2316 + attribute \src "ls180.v:6470.39-6470.150" + cell $and $and$ls180.v:6470$2175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6664$2314_Y - connect \B $eq$ls180.v:6664$2315_Y - connect \Y $and$ls180.v:6664$2316_Y + connect \A $and$ls180.v:6470$2173_Y + connect \B $eq$ls180.v:6470$2174_Y + connect \Y $and$ls180.v:6470$2175_Y end - attribute \src "ls180.v:6666.52-6666.107" - cell $and $and$ls180.v:6666$2317 + attribute \src "ls180.v:6472.52-6472.107" + cell $and $and$ls180.v:6472$2176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266578,43 +264866,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6666$2317_Y + connect \Y $and$ls180.v:6472$2176_Y end - attribute \src "ls180.v:6666.51-6666.159" - cell $and $and$ls180.v:6666$2319 + attribute \src "ls180.v:6472.51-6472.159" + cell $and $and$ls180.v:6472$2178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6666$2317_Y - connect \B $eq$ls180.v:6666$2318_Y - connect \Y $and$ls180.v:6666$2319_Y + connect \A $and$ls180.v:6472$2176_Y + connect \B $eq$ls180.v:6472$2177_Y + connect \Y $and$ls180.v:6472$2178_Y end - attribute \src "ls180.v:6667.52-6667.110" - cell $and $and$ls180.v:6667$2321 + attribute \src "ls180.v:6473.52-6473.110" + cell $and $and$ls180.v:6473$2180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6667$2320_Y - connect \Y $and$ls180.v:6667$2321_Y + connect \B $not$ls180.v:6473$2179_Y + connect \Y $and$ls180.v:6473$2180_Y end - attribute \src "ls180.v:6667.51-6667.162" - cell $and $and$ls180.v:6667$2323 + attribute \src "ls180.v:6473.51-6473.162" + cell $and $and$ls180.v:6473$2182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6667$2321_Y - connect \B $eq$ls180.v:6667$2322_Y - connect \Y $and$ls180.v:6667$2323_Y + connect \A $and$ls180.v:6473$2180_Y + connect \B $eq$ls180.v:6473$2181_Y + connect \Y $and$ls180.v:6473$2182_Y end - attribute \src "ls180.v:6669.53-6669.108" - cell $and $and$ls180.v:6669$2324 + attribute \src "ls180.v:6475.53-6475.108" + cell $and $and$ls180.v:6475$2183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266622,43 +264910,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6669$2324_Y + connect \Y $and$ls180.v:6475$2183_Y end - attribute \src "ls180.v:6669.52-6669.160" - cell $and $and$ls180.v:6669$2326 + attribute \src "ls180.v:6475.52-6475.160" + cell $and $and$ls180.v:6475$2185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6669$2324_Y - connect \B $eq$ls180.v:6669$2325_Y - connect \Y $and$ls180.v:6669$2326_Y + connect \A $and$ls180.v:6475$2183_Y + connect \B $eq$ls180.v:6475$2184_Y + connect \Y $and$ls180.v:6475$2185_Y end - attribute \src "ls180.v:6670.53-6670.111" - cell $and $and$ls180.v:6670$2328 + attribute \src "ls180.v:6476.53-6476.111" + cell $and $and$ls180.v:6476$2187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6670$2327_Y - connect \Y $and$ls180.v:6670$2328_Y + connect \B $not$ls180.v:6476$2186_Y + connect \Y $and$ls180.v:6476$2187_Y end - attribute \src "ls180.v:6670.52-6670.163" - cell $and $and$ls180.v:6670$2330 + attribute \src "ls180.v:6476.52-6476.163" + cell $and $and$ls180.v:6476$2189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6670$2328_Y - connect \B $eq$ls180.v:6670$2329_Y - connect \Y $and$ls180.v:6670$2330_Y + connect \A $and$ls180.v:6476$2187_Y + connect \B $eq$ls180.v:6476$2188_Y + connect \Y $and$ls180.v:6476$2189_Y end - attribute \src "ls180.v:6672.44-6672.99" - cell $and $and$ls180.v:6672$2331 + attribute \src "ls180.v:6478.44-6478.99" + cell $and $and$ls180.v:6478$2190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266666,43 +264954,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6672$2331_Y + connect \Y $and$ls180.v:6478$2190_Y end - attribute \src "ls180.v:6672.43-6672.151" - cell $and $and$ls180.v:6672$2333 + attribute \src "ls180.v:6478.43-6478.151" + cell $and $and$ls180.v:6478$2192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6672$2331_Y - connect \B $eq$ls180.v:6672$2332_Y - connect \Y $and$ls180.v:6672$2333_Y + connect \A $and$ls180.v:6478$2190_Y + connect \B $eq$ls180.v:6478$2191_Y + connect \Y $and$ls180.v:6478$2192_Y end - attribute \src "ls180.v:6673.44-6673.102" - cell $and $and$ls180.v:6673$2335 + attribute \src "ls180.v:6479.44-6479.102" + cell $and $and$ls180.v:6479$2194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6673$2334_Y - connect \Y $and$ls180.v:6673$2335_Y + connect \B $not$ls180.v:6479$2193_Y + connect \Y $and$ls180.v:6479$2194_Y end - attribute \src "ls180.v:6673.43-6673.154" - cell $and $and$ls180.v:6673$2337 + attribute \src "ls180.v:6479.43-6479.154" + cell $and $and$ls180.v:6479$2196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6673$2335_Y - connect \B $eq$ls180.v:6673$2336_Y - connect \Y $and$ls180.v:6673$2337_Y + connect \A $and$ls180.v:6479$2194_Y + connect \B $eq$ls180.v:6479$2195_Y + connect \Y $and$ls180.v:6479$2196_Y end - attribute \src "ls180.v:6692.30-6692.85" - cell $and $and$ls180.v:6692$2339 + attribute \src "ls180.v:6498.30-6498.85" + cell $and $and$ls180.v:6498$2198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266710,43 +264998,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6692$2339_Y + connect \Y $and$ls180.v:6498$2198_Y end - attribute \src "ls180.v:6692.29-6692.136" - cell $and $and$ls180.v:6692$2341 + attribute \src "ls180.v:6498.29-6498.136" + cell $and $and$ls180.v:6498$2200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6692$2339_Y - connect \B $eq$ls180.v:6692$2340_Y - connect \Y $and$ls180.v:6692$2341_Y + connect \A $and$ls180.v:6498$2198_Y + connect \B $eq$ls180.v:6498$2199_Y + connect \Y $and$ls180.v:6498$2200_Y end - attribute \src "ls180.v:6693.30-6693.88" - cell $and $and$ls180.v:6693$2343 + attribute \src "ls180.v:6499.30-6499.88" + cell $and $and$ls180.v:6499$2202 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6693$2342_Y - connect \Y $and$ls180.v:6693$2343_Y + connect \B $not$ls180.v:6499$2201_Y + connect \Y $and$ls180.v:6499$2202_Y end - attribute \src "ls180.v:6693.29-6693.139" - cell $and $and$ls180.v:6693$2345 + attribute \src "ls180.v:6499.29-6499.139" + cell $and $and$ls180.v:6499$2204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6693$2343_Y - connect \B $eq$ls180.v:6693$2344_Y - connect \Y $and$ls180.v:6693$2345_Y + connect \A $and$ls180.v:6499$2202_Y + connect \B $eq$ls180.v:6499$2203_Y + connect \Y $and$ls180.v:6499$2204_Y end - attribute \src "ls180.v:6695.40-6695.95" - cell $and $and$ls180.v:6695$2346 + attribute \src "ls180.v:6501.40-6501.95" + cell $and $and$ls180.v:6501$2205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266754,43 +265042,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6695$2346_Y + connect \Y $and$ls180.v:6501$2205_Y end - attribute \src "ls180.v:6695.39-6695.146" - cell $and $and$ls180.v:6695$2348 + attribute \src "ls180.v:6501.39-6501.146" + cell $and $and$ls180.v:6501$2207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6695$2346_Y - connect \B $eq$ls180.v:6695$2347_Y - connect \Y $and$ls180.v:6695$2348_Y + connect \A $and$ls180.v:6501$2205_Y + connect \B $eq$ls180.v:6501$2206_Y + connect \Y $and$ls180.v:6501$2207_Y end - attribute \src "ls180.v:6696.40-6696.98" - cell $and $and$ls180.v:6696$2350 + attribute \src "ls180.v:6502.40-6502.98" + cell $and $and$ls180.v:6502$2209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6696$2349_Y - connect \Y $and$ls180.v:6696$2350_Y + connect \B $not$ls180.v:6502$2208_Y + connect \Y $and$ls180.v:6502$2209_Y end - attribute \src "ls180.v:6696.39-6696.149" - cell $and $and$ls180.v:6696$2352 + attribute \src "ls180.v:6502.39-6502.149" + cell $and $and$ls180.v:6502$2211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6696$2350_Y - connect \B $eq$ls180.v:6696$2351_Y - connect \Y $and$ls180.v:6696$2352_Y + connect \A $and$ls180.v:6502$2209_Y + connect \B $eq$ls180.v:6502$2210_Y + connect \Y $and$ls180.v:6502$2211_Y end - attribute \src "ls180.v:6698.41-6698.96" - cell $and $and$ls180.v:6698$2353 + attribute \src "ls180.v:6504.41-6504.96" + cell $and $and$ls180.v:6504$2212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266798,43 +265086,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6698$2353_Y + connect \Y $and$ls180.v:6504$2212_Y end - attribute \src "ls180.v:6698.40-6698.147" - cell $and $and$ls180.v:6698$2355 + attribute \src "ls180.v:6504.40-6504.147" + cell $and $and$ls180.v:6504$2214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6698$2353_Y - connect \B $eq$ls180.v:6698$2354_Y - connect \Y $and$ls180.v:6698$2355_Y + connect \A $and$ls180.v:6504$2212_Y + connect \B $eq$ls180.v:6504$2213_Y + connect \Y $and$ls180.v:6504$2214_Y end - attribute \src "ls180.v:6699.41-6699.99" - cell $and $and$ls180.v:6699$2357 + attribute \src "ls180.v:6505.41-6505.99" + cell $and $and$ls180.v:6505$2216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6699$2356_Y - connect \Y $and$ls180.v:6699$2357_Y + connect \B $not$ls180.v:6505$2215_Y + connect \Y $and$ls180.v:6505$2216_Y end - attribute \src "ls180.v:6699.40-6699.150" - cell $and $and$ls180.v:6699$2359 + attribute \src "ls180.v:6505.40-6505.150" + cell $and $and$ls180.v:6505$2218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6699$2357_Y - connect \B $eq$ls180.v:6699$2358_Y - connect \Y $and$ls180.v:6699$2359_Y + connect \A $and$ls180.v:6505$2216_Y + connect \B $eq$ls180.v:6505$2217_Y + connect \Y $and$ls180.v:6505$2218_Y end - attribute \src "ls180.v:6701.45-6701.100" - cell $and $and$ls180.v:6701$2360 + attribute \src "ls180.v:6507.45-6507.100" + cell $and $and$ls180.v:6507$2219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266842,43 +265130,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6701$2360_Y + connect \Y $and$ls180.v:6507$2219_Y end - attribute \src "ls180.v:6701.44-6701.151" - cell $and $and$ls180.v:6701$2362 + attribute \src "ls180.v:6507.44-6507.151" + cell $and $and$ls180.v:6507$2221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6701$2360_Y - connect \B $eq$ls180.v:6701$2361_Y - connect \Y $and$ls180.v:6701$2362_Y + connect \A $and$ls180.v:6507$2219_Y + connect \B $eq$ls180.v:6507$2220_Y + connect \Y $and$ls180.v:6507$2221_Y end - attribute \src "ls180.v:6702.45-6702.103" - cell $and $and$ls180.v:6702$2364 + attribute \src "ls180.v:6508.45-6508.103" + cell $and $and$ls180.v:6508$2223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6702$2363_Y - connect \Y $and$ls180.v:6702$2364_Y + connect \B $not$ls180.v:6508$2222_Y + connect \Y $and$ls180.v:6508$2223_Y end - attribute \src "ls180.v:6702.44-6702.154" - cell $and $and$ls180.v:6702$2366 + attribute \src "ls180.v:6508.44-6508.154" + cell $and $and$ls180.v:6508$2225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6702$2364_Y - connect \B $eq$ls180.v:6702$2365_Y - connect \Y $and$ls180.v:6702$2366_Y + connect \A $and$ls180.v:6508$2223_Y + connect \B $eq$ls180.v:6508$2224_Y + connect \Y $and$ls180.v:6508$2225_Y end - attribute \src "ls180.v:6704.46-6704.101" - cell $and $and$ls180.v:6704$2367 + attribute \src "ls180.v:6510.46-6510.101" + cell $and $and$ls180.v:6510$2226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266886,43 +265174,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6704$2367_Y + connect \Y $and$ls180.v:6510$2226_Y end - attribute \src "ls180.v:6704.45-6704.152" - cell $and $and$ls180.v:6704$2369 + attribute \src "ls180.v:6510.45-6510.152" + cell $and $and$ls180.v:6510$2228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6704$2367_Y - connect \B $eq$ls180.v:6704$2368_Y - connect \Y $and$ls180.v:6704$2369_Y + connect \A $and$ls180.v:6510$2226_Y + connect \B $eq$ls180.v:6510$2227_Y + connect \Y $and$ls180.v:6510$2228_Y end - attribute \src "ls180.v:6705.46-6705.104" - cell $and $and$ls180.v:6705$2371 + attribute \src "ls180.v:6511.46-6511.104" + cell $and $and$ls180.v:6511$2230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6705$2370_Y - connect \Y $and$ls180.v:6705$2371_Y + connect \B $not$ls180.v:6511$2229_Y + connect \Y $and$ls180.v:6511$2230_Y end - attribute \src "ls180.v:6705.45-6705.155" - cell $and $and$ls180.v:6705$2373 + attribute \src "ls180.v:6511.45-6511.155" + cell $and $and$ls180.v:6511$2232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6705$2371_Y - connect \B $eq$ls180.v:6705$2372_Y - connect \Y $and$ls180.v:6705$2373_Y + connect \A $and$ls180.v:6511$2230_Y + connect \B $eq$ls180.v:6511$2231_Y + connect \Y $and$ls180.v:6511$2232_Y end - attribute \src "ls180.v:6707.44-6707.99" - cell $and $and$ls180.v:6707$2374 + attribute \src "ls180.v:6513.44-6513.99" + cell $and $and$ls180.v:6513$2233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266930,43 +265218,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6707$2374_Y + connect \Y $and$ls180.v:6513$2233_Y end - attribute \src "ls180.v:6707.43-6707.150" - cell $and $and$ls180.v:6707$2376 + attribute \src "ls180.v:6513.43-6513.150" + cell $and $and$ls180.v:6513$2235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6707$2374_Y - connect \B $eq$ls180.v:6707$2375_Y - connect \Y $and$ls180.v:6707$2376_Y + connect \A $and$ls180.v:6513$2233_Y + connect \B $eq$ls180.v:6513$2234_Y + connect \Y $and$ls180.v:6513$2235_Y end - attribute \src "ls180.v:6708.44-6708.102" - cell $and $and$ls180.v:6708$2378 + attribute \src "ls180.v:6514.44-6514.102" + cell $and $and$ls180.v:6514$2237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6708$2377_Y - connect \Y $and$ls180.v:6708$2378_Y + connect \B $not$ls180.v:6514$2236_Y + connect \Y $and$ls180.v:6514$2237_Y end - attribute \src "ls180.v:6708.43-6708.153" - cell $and $and$ls180.v:6708$2380 + attribute \src "ls180.v:6514.43-6514.153" + cell $and $and$ls180.v:6514$2239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6708$2378_Y - connect \B $eq$ls180.v:6708$2379_Y - connect \Y $and$ls180.v:6708$2380_Y + connect \A $and$ls180.v:6514$2237_Y + connect \B $eq$ls180.v:6514$2238_Y + connect \Y $and$ls180.v:6514$2239_Y end - attribute \src "ls180.v:6710.41-6710.96" - cell $and $and$ls180.v:6710$2381 + attribute \src "ls180.v:6516.41-6516.96" + cell $and $and$ls180.v:6516$2240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -266974,43 +265262,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6710$2381_Y + connect \Y $and$ls180.v:6516$2240_Y end - attribute \src "ls180.v:6710.40-6710.147" - cell $and $and$ls180.v:6710$2383 + attribute \src "ls180.v:6516.40-6516.147" + cell $and $and$ls180.v:6516$2242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6710$2381_Y - connect \B $eq$ls180.v:6710$2382_Y - connect \Y $and$ls180.v:6710$2383_Y + connect \A $and$ls180.v:6516$2240_Y + connect \B $eq$ls180.v:6516$2241_Y + connect \Y $and$ls180.v:6516$2242_Y end - attribute \src "ls180.v:6711.41-6711.99" - cell $and $and$ls180.v:6711$2385 + attribute \src "ls180.v:6517.41-6517.99" + cell $and $and$ls180.v:6517$2244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6711$2384_Y - connect \Y $and$ls180.v:6711$2385_Y + connect \B $not$ls180.v:6517$2243_Y + connect \Y $and$ls180.v:6517$2244_Y end - attribute \src "ls180.v:6711.40-6711.150" - cell $and $and$ls180.v:6711$2387 + attribute \src "ls180.v:6517.40-6517.150" + cell $and $and$ls180.v:6517$2246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6711$2385_Y - connect \B $eq$ls180.v:6711$2386_Y - connect \Y $and$ls180.v:6711$2387_Y + connect \A $and$ls180.v:6517$2244_Y + connect \B $eq$ls180.v:6517$2245_Y + connect \Y $and$ls180.v:6517$2246_Y end - attribute \src "ls180.v:6713.40-6713.95" - cell $and $and$ls180.v:6713$2388 + attribute \src "ls180.v:6519.40-6519.95" + cell $and $and$ls180.v:6519$2247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267018,43 +265306,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6713$2388_Y + connect \Y $and$ls180.v:6519$2247_Y end - attribute \src "ls180.v:6713.39-6713.146" - cell $and $and$ls180.v:6713$2390 + attribute \src "ls180.v:6519.39-6519.146" + cell $and $and$ls180.v:6519$2249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6713$2388_Y - connect \B $eq$ls180.v:6713$2389_Y - connect \Y $and$ls180.v:6713$2390_Y + connect \A $and$ls180.v:6519$2247_Y + connect \B $eq$ls180.v:6519$2248_Y + connect \Y $and$ls180.v:6519$2249_Y end - attribute \src "ls180.v:6714.40-6714.98" - cell $and $and$ls180.v:6714$2392 + attribute \src "ls180.v:6520.40-6520.98" + cell $and $and$ls180.v:6520$2251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6714$2391_Y - connect \Y $and$ls180.v:6714$2392_Y + connect \B $not$ls180.v:6520$2250_Y + connect \Y $and$ls180.v:6520$2251_Y end - attribute \src "ls180.v:6714.39-6714.149" - cell $and $and$ls180.v:6714$2394 + attribute \src "ls180.v:6520.39-6520.149" + cell $and $and$ls180.v:6520$2253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6714$2392_Y - connect \B $eq$ls180.v:6714$2393_Y - connect \Y $and$ls180.v:6714$2394_Y + connect \A $and$ls180.v:6520$2251_Y + connect \B $eq$ls180.v:6520$2252_Y + connect \Y $and$ls180.v:6520$2253_Y end - attribute \src "ls180.v:6726.46-6726.101" - cell $and $and$ls180.v:6726$2396 + attribute \src "ls180.v:6532.46-6532.101" + cell $and $and$ls180.v:6532$2255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267062,43 +265350,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6726$2396_Y + connect \Y $and$ls180.v:6532$2255_Y end - attribute \src "ls180.v:6726.45-6726.152" - cell $and $and$ls180.v:6726$2398 + attribute \src "ls180.v:6532.45-6532.152" + cell $and $and$ls180.v:6532$2257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6726$2396_Y - connect \B $eq$ls180.v:6726$2397_Y - connect \Y $and$ls180.v:6726$2398_Y + connect \A $and$ls180.v:6532$2255_Y + connect \B $eq$ls180.v:6532$2256_Y + connect \Y $and$ls180.v:6532$2257_Y end - attribute \src "ls180.v:6727.46-6727.104" - cell $and $and$ls180.v:6727$2400 + attribute \src "ls180.v:6533.46-6533.104" + cell $and $and$ls180.v:6533$2259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6727$2399_Y - connect \Y $and$ls180.v:6727$2400_Y + connect \B $not$ls180.v:6533$2258_Y + connect \Y $and$ls180.v:6533$2259_Y end - attribute \src "ls180.v:6727.45-6727.155" - cell $and $and$ls180.v:6727$2402 + attribute \src "ls180.v:6533.45-6533.155" + cell $and $and$ls180.v:6533$2261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6727$2400_Y - connect \B $eq$ls180.v:6727$2401_Y - connect \Y $and$ls180.v:6727$2402_Y + connect \A $and$ls180.v:6533$2259_Y + connect \B $eq$ls180.v:6533$2260_Y + connect \Y $and$ls180.v:6533$2261_Y end - attribute \src "ls180.v:6729.46-6729.101" - cell $and $and$ls180.v:6729$2403 + attribute \src "ls180.v:6535.46-6535.101" + cell $and $and$ls180.v:6535$2262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267106,43 +265394,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6729$2403_Y + connect \Y $and$ls180.v:6535$2262_Y end - attribute \src "ls180.v:6729.45-6729.152" - cell $and $and$ls180.v:6729$2405 + attribute \src "ls180.v:6535.45-6535.152" + cell $and $and$ls180.v:6535$2264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6729$2403_Y - connect \B $eq$ls180.v:6729$2404_Y - connect \Y $and$ls180.v:6729$2405_Y + connect \A $and$ls180.v:6535$2262_Y + connect \B $eq$ls180.v:6535$2263_Y + connect \Y $and$ls180.v:6535$2264_Y end - attribute \src "ls180.v:6730.46-6730.104" - cell $and $and$ls180.v:6730$2407 + attribute \src "ls180.v:6536.46-6536.104" + cell $and $and$ls180.v:6536$2266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6730$2406_Y - connect \Y $and$ls180.v:6730$2407_Y + connect \B $not$ls180.v:6536$2265_Y + connect \Y $and$ls180.v:6536$2266_Y end - attribute \src "ls180.v:6730.45-6730.155" - cell $and $and$ls180.v:6730$2409 + attribute \src "ls180.v:6536.45-6536.155" + cell $and $and$ls180.v:6536$2268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6730$2407_Y - connect \B $eq$ls180.v:6730$2408_Y - connect \Y $and$ls180.v:6730$2409_Y + connect \A $and$ls180.v:6536$2266_Y + connect \B $eq$ls180.v:6536$2267_Y + connect \Y $and$ls180.v:6536$2268_Y end - attribute \src "ls180.v:6732.46-6732.101" - cell $and $and$ls180.v:6732$2410 + attribute \src "ls180.v:6538.46-6538.101" + cell $and $and$ls180.v:6538$2269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267150,43 +265438,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6732$2410_Y + connect \Y $and$ls180.v:6538$2269_Y end - attribute \src "ls180.v:6732.45-6732.152" - cell $and $and$ls180.v:6732$2412 + attribute \src "ls180.v:6538.45-6538.152" + cell $and $and$ls180.v:6538$2271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6732$2410_Y - connect \B $eq$ls180.v:6732$2411_Y - connect \Y $and$ls180.v:6732$2412_Y + connect \A $and$ls180.v:6538$2269_Y + connect \B $eq$ls180.v:6538$2270_Y + connect \Y $and$ls180.v:6538$2271_Y end - attribute \src "ls180.v:6733.46-6733.104" - cell $and $and$ls180.v:6733$2414 + attribute \src "ls180.v:6539.46-6539.104" + cell $and $and$ls180.v:6539$2273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6733$2413_Y - connect \Y $and$ls180.v:6733$2414_Y + connect \B $not$ls180.v:6539$2272_Y + connect \Y $and$ls180.v:6539$2273_Y end - attribute \src "ls180.v:6733.45-6733.155" - cell $and $and$ls180.v:6733$2416 + attribute \src "ls180.v:6539.45-6539.155" + cell $and $and$ls180.v:6539$2275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6733$2414_Y - connect \B $eq$ls180.v:6733$2415_Y - connect \Y $and$ls180.v:6733$2416_Y + connect \A $and$ls180.v:6539$2273_Y + connect \B $eq$ls180.v:6539$2274_Y + connect \Y $and$ls180.v:6539$2275_Y end - attribute \src "ls180.v:6735.46-6735.101" - cell $and $and$ls180.v:6735$2417 + attribute \src "ls180.v:6541.46-6541.101" + cell $and $and$ls180.v:6541$2276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267194,263 +265482,263 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6735$2417_Y + connect \Y $and$ls180.v:6541$2276_Y end - attribute \src "ls180.v:6735.45-6735.152" - cell $and $and$ls180.v:6735$2419 + attribute \src "ls180.v:6541.45-6541.152" + cell $and $and$ls180.v:6541$2278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6735$2417_Y - connect \B $eq$ls180.v:6735$2418_Y - connect \Y $and$ls180.v:6735$2419_Y + connect \A $and$ls180.v:6541$2276_Y + connect \B $eq$ls180.v:6541$2277_Y + connect \Y $and$ls180.v:6541$2278_Y end - attribute \src "ls180.v:6736.46-6736.104" - cell $and $and$ls180.v:6736$2421 + attribute \src "ls180.v:6542.46-6542.104" + cell $and $and$ls180.v:6542$2280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6736$2420_Y - connect \Y $and$ls180.v:6736$2421_Y + connect \B $not$ls180.v:6542$2279_Y + connect \Y $and$ls180.v:6542$2280_Y end - attribute \src "ls180.v:6736.45-6736.155" - cell $and $and$ls180.v:6736$2423 + attribute \src "ls180.v:6542.45-6542.155" + cell $and $and$ls180.v:6542$2282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6736$2421_Y - connect \B $eq$ls180.v:6736$2422_Y - connect \Y $and$ls180.v:6736$2423_Y + connect \A $and$ls180.v:6542$2280_Y + connect \B $eq$ls180.v:6542$2281_Y + connect \Y $and$ls180.v:6542$2282_Y end - attribute \src "ls180.v:7117.109-7117.178" - cell $and $and$ls180.v:7117$2461 + attribute \src "ls180.v:6923.109-6923.178" + cell $and $and$ls180.v:6923$2320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:7117$2460_Y - connect \Y $and$ls180.v:7117$2461_Y + connect \B $eq$ls180.v:6923$2319_Y + connect \Y $and$ls180.v:6923$2320_Y end - attribute \src "ls180.v:7117.184-7117.253" - cell $and $and$ls180.v:7117$2464 + attribute \src "ls180.v:6923.184-6923.253" + cell $and $and$ls180.v:6923$2323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:7117$2463_Y - connect \Y $and$ls180.v:7117$2464_Y + connect \B $eq$ls180.v:6923$2322_Y + connect \Y $and$ls180.v:6923$2323_Y end - attribute \src "ls180.v:7117.259-7117.328" - cell $and $and$ls180.v:7117$2467 + attribute \src "ls180.v:6923.259-6923.328" + cell $and $and$ls180.v:6923$2326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:7117$2466_Y - connect \Y $and$ls180.v:7117$2467_Y + connect \B $eq$ls180.v:6923$2325_Y + connect \Y $and$ls180.v:6923$2326_Y end - attribute \src "ls180.v:7117.40-7117.331" - cell $and $and$ls180.v:7117$2470 + attribute \src "ls180.v:6923.40-6923.331" + cell $and $and$ls180.v:6923$2329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7117$2459_Y - connect \B $not$ls180.v:7117$2469_Y - connect \Y $and$ls180.v:7117$2470_Y + connect \A $eq$ls180.v:6923$2318_Y + connect \B $not$ls180.v:6923$2328_Y + connect \Y $and$ls180.v:6923$2329_Y end - attribute \src "ls180.v:7117.39-7117.354" - cell $and $and$ls180.v:7117$2471 + attribute \src "ls180.v:6923.39-6923.354" + cell $and $and$ls180.v:6923$2330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7117$2470_Y + connect \A $and$ls180.v:6923$2329_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7117$2471_Y + connect \Y $and$ls180.v:6923$2330_Y end - attribute \src "ls180.v:7141.109-7141.178" - cell $and $and$ls180.v:7141$2477 + attribute \src "ls180.v:6947.109-6947.178" + cell $and $and$ls180.v:6947$2336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:7141$2476_Y - connect \Y $and$ls180.v:7141$2477_Y + connect \B $eq$ls180.v:6947$2335_Y + connect \Y $and$ls180.v:6947$2336_Y end - attribute \src "ls180.v:7141.184-7141.253" - cell $and $and$ls180.v:7141$2480 + attribute \src "ls180.v:6947.184-6947.253" + cell $and $and$ls180.v:6947$2339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:7141$2479_Y - connect \Y $and$ls180.v:7141$2480_Y + connect \B $eq$ls180.v:6947$2338_Y + connect \Y $and$ls180.v:6947$2339_Y end - attribute \src "ls180.v:7141.259-7141.328" - cell $and $and$ls180.v:7141$2483 + attribute \src "ls180.v:6947.259-6947.328" + cell $and $and$ls180.v:6947$2342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:7141$2482_Y - connect \Y $and$ls180.v:7141$2483_Y + connect \B $eq$ls180.v:6947$2341_Y + connect \Y $and$ls180.v:6947$2342_Y end - attribute \src "ls180.v:7141.40-7141.331" - cell $and $and$ls180.v:7141$2486 + attribute \src "ls180.v:6947.40-6947.331" + cell $and $and$ls180.v:6947$2345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7141$2475_Y - connect \B $not$ls180.v:7141$2485_Y - connect \Y $and$ls180.v:7141$2486_Y + connect \A $eq$ls180.v:6947$2334_Y + connect \B $not$ls180.v:6947$2344_Y + connect \Y $and$ls180.v:6947$2345_Y end - attribute \src "ls180.v:7141.39-7141.354" - cell $and $and$ls180.v:7141$2487 + attribute \src "ls180.v:6947.39-6947.354" + cell $and $and$ls180.v:6947$2346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7141$2486_Y + connect \A $and$ls180.v:6947$2345_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7141$2487_Y + connect \Y $and$ls180.v:6947$2346_Y end - attribute \src "ls180.v:7165.109-7165.178" - cell $and $and$ls180.v:7165$2493 + attribute \src "ls180.v:6971.109-6971.178" + cell $and $and$ls180.v:6971$2352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:7165$2492_Y - connect \Y $and$ls180.v:7165$2493_Y + connect \B $eq$ls180.v:6971$2351_Y + connect \Y $and$ls180.v:6971$2352_Y end - attribute \src "ls180.v:7165.184-7165.253" - cell $and $and$ls180.v:7165$2496 + attribute \src "ls180.v:6971.184-6971.253" + cell $and $and$ls180.v:6971$2355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:7165$2495_Y - connect \Y $and$ls180.v:7165$2496_Y + connect \B $eq$ls180.v:6971$2354_Y + connect \Y $and$ls180.v:6971$2355_Y end - attribute \src "ls180.v:7165.259-7165.328" - cell $and $and$ls180.v:7165$2499 + attribute \src "ls180.v:6971.259-6971.328" + cell $and $and$ls180.v:6971$2358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:7165$2498_Y - connect \Y $and$ls180.v:7165$2499_Y + connect \B $eq$ls180.v:6971$2357_Y + connect \Y $and$ls180.v:6971$2358_Y end - attribute \src "ls180.v:7165.40-7165.331" - cell $and $and$ls180.v:7165$2502 + attribute \src "ls180.v:6971.40-6971.331" + cell $and $and$ls180.v:6971$2361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7165$2491_Y - connect \B $not$ls180.v:7165$2501_Y - connect \Y $and$ls180.v:7165$2502_Y + connect \A $eq$ls180.v:6971$2350_Y + connect \B $not$ls180.v:6971$2360_Y + connect \Y $and$ls180.v:6971$2361_Y end - attribute \src "ls180.v:7165.39-7165.354" - cell $and $and$ls180.v:7165$2503 + attribute \src "ls180.v:6971.39-6971.354" + cell $and $and$ls180.v:6971$2362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7165$2502_Y + connect \A $and$ls180.v:6971$2361_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7165$2503_Y + connect \Y $and$ls180.v:6971$2362_Y end - attribute \src "ls180.v:7189.109-7189.178" - cell $and $and$ls180.v:7189$2509 + attribute \src "ls180.v:6995.109-6995.178" + cell $and $and$ls180.v:6995$2368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:7189$2508_Y - connect \Y $and$ls180.v:7189$2509_Y + connect \B $eq$ls180.v:6995$2367_Y + connect \Y $and$ls180.v:6995$2368_Y end - attribute \src "ls180.v:7189.184-7189.253" - cell $and $and$ls180.v:7189$2512 + attribute \src "ls180.v:6995.184-6995.253" + cell $and $and$ls180.v:6995$2371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:7189$2511_Y - connect \Y $and$ls180.v:7189$2512_Y + connect \B $eq$ls180.v:6995$2370_Y + connect \Y $and$ls180.v:6995$2371_Y end - attribute \src "ls180.v:7189.259-7189.328" - cell $and $and$ls180.v:7189$2515 + attribute \src "ls180.v:6995.259-6995.328" + cell $and $and$ls180.v:6995$2374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:7189$2514_Y - connect \Y $and$ls180.v:7189$2515_Y + connect \B $eq$ls180.v:6995$2373_Y + connect \Y $and$ls180.v:6995$2374_Y end - attribute \src "ls180.v:7189.40-7189.331" - cell $and $and$ls180.v:7189$2518 + attribute \src "ls180.v:6995.40-6995.331" + cell $and $and$ls180.v:6995$2377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7189$2507_Y - connect \B $not$ls180.v:7189$2517_Y - connect \Y $and$ls180.v:7189$2518_Y + connect \A $eq$ls180.v:6995$2366_Y + connect \B $not$ls180.v:6995$2376_Y + connect \Y $and$ls180.v:6995$2377_Y end - attribute \src "ls180.v:7189.39-7189.354" - cell $and $and$ls180.v:7189$2519 + attribute \src "ls180.v:6995.39-6995.354" + cell $and $and$ls180.v:6995$2378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7189$2518_Y + connect \A $and$ls180.v:6995$2377_Y connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:7189$2519_Y + connect \Y $and$ls180.v:6995$2378_Y end - attribute \src "ls180.v:7394.39-7394.104" - cell $and $and$ls180.v:7394$2531 + attribute \src "ls180.v:7200.39-7200.104" + cell $and $and$ls180.v:7200$2390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267458,21 +265746,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7394$2531_Y + connect \Y $and$ls180.v:7200$2390_Y end - attribute \src "ls180.v:7394.38-7394.145" - cell $and $and$ls180.v:7394$2532 + attribute \src "ls180.v:7200.38-7200.145" + cell $and $and$ls180.v:7200$2391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7394$2531_Y + connect \A $and$ls180.v:7200$2390_Y connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7394$2532_Y + connect \Y $and$ls180.v:7200$2391_Y end - attribute \src "ls180.v:7397.39-7397.104" - cell $and $and$ls180.v:7397$2533 + attribute \src "ls180.v:7203.39-7203.104" + cell $and $and$ls180.v:7203$2392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267480,21 +265768,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7397$2533_Y + connect \Y $and$ls180.v:7203$2392_Y end - attribute \src "ls180.v:7397.38-7397.145" - cell $and $and$ls180.v:7397$2534 + attribute \src "ls180.v:7203.38-7203.145" + cell $and $and$ls180.v:7203$2393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7397$2533_Y + connect \A $and$ls180.v:7203$2392_Y connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7397$2534_Y + connect \Y $and$ls180.v:7203$2393_Y end - attribute \src "ls180.v:7400.39-7400.82" - cell $and $and$ls180.v:7400$2535 + attribute \src "ls180.v:7206.39-7206.82" + cell $and $and$ls180.v:7206$2394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267502,21 +265790,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7400$2535_Y + connect \Y $and$ls180.v:7206$2394_Y end - attribute \src "ls180.v:7400.38-7400.112" - cell $and $and$ls180.v:7400$2536 + attribute \src "ls180.v:7206.38-7206.112" + cell $and $and$ls180.v:7206$2395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7400$2535_Y + connect \A $and$ls180.v:7206$2394_Y connect \B \main_sdram_cmd_payload_cas - connect \Y $and$ls180.v:7400$2536_Y + connect \Y $and$ls180.v:7206$2395_Y end - attribute \src "ls180.v:7411.39-7411.104" - cell $and $and$ls180.v:7411$2538 + attribute \src "ls180.v:7217.39-7217.104" + cell $and $and$ls180.v:7217$2397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267524,21 +265812,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7411$2538_Y + connect \Y $and$ls180.v:7217$2397_Y end - attribute \src "ls180.v:7411.38-7411.145" - cell $and $and$ls180.v:7411$2539 + attribute \src "ls180.v:7217.38-7217.145" + cell $and $and$ls180.v:7217$2398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7411$2538_Y + connect \A $and$ls180.v:7217$2397_Y connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7411$2539_Y + connect \Y $and$ls180.v:7217$2398_Y end - attribute \src "ls180.v:7414.39-7414.104" - cell $and $and$ls180.v:7414$2540 + attribute \src "ls180.v:7220.39-7220.104" + cell $and $and$ls180.v:7220$2399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267546,21 +265834,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7414$2540_Y + connect \Y $and$ls180.v:7220$2399_Y end - attribute \src "ls180.v:7414.38-7414.145" - cell $and $and$ls180.v:7414$2541 + attribute \src "ls180.v:7220.38-7220.145" + cell $and $and$ls180.v:7220$2400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7414$2540_Y + connect \A $and$ls180.v:7220$2399_Y connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7414$2541_Y + connect \Y $and$ls180.v:7220$2400_Y end - attribute \src "ls180.v:7417.39-7417.82" - cell $and $and$ls180.v:7417$2542 + attribute \src "ls180.v:7223.39-7223.82" + cell $and $and$ls180.v:7223$2401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267568,21 +265856,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7417$2542_Y + connect \Y $and$ls180.v:7223$2401_Y end - attribute \src "ls180.v:7417.38-7417.112" - cell $and $and$ls180.v:7417$2543 + attribute \src "ls180.v:7223.38-7223.112" + cell $and $and$ls180.v:7223$2402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7417$2542_Y + connect \A $and$ls180.v:7223$2401_Y connect \B \main_sdram_cmd_payload_ras - connect \Y $and$ls180.v:7417$2543_Y + connect \Y $and$ls180.v:7223$2402_Y end - attribute \src "ls180.v:7428.39-7428.104" - cell $and $and$ls180.v:7428$2545 + attribute \src "ls180.v:7234.39-7234.104" + cell $and $and$ls180.v:7234$2404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267590,21 +265878,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7428$2545_Y + connect \Y $and$ls180.v:7234$2404_Y end - attribute \src "ls180.v:7428.38-7428.144" - cell $and $and$ls180.v:7428$2546 + attribute \src "ls180.v:7234.38-7234.144" + cell $and $and$ls180.v:7234$2405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7428$2545_Y + connect \A $and$ls180.v:7234$2404_Y connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7428$2546_Y + connect \Y $and$ls180.v:7234$2405_Y end - attribute \src "ls180.v:7431.39-7431.104" - cell $and $and$ls180.v:7431$2547 + attribute \src "ls180.v:7237.39-7237.104" + cell $and $and$ls180.v:7237$2406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267612,21 +265900,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7431$2547_Y + connect \Y $and$ls180.v:7237$2406_Y end - attribute \src "ls180.v:7431.38-7431.144" - cell $and $and$ls180.v:7431$2548 + attribute \src "ls180.v:7237.38-7237.144" + cell $and $and$ls180.v:7237$2407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7431$2547_Y + connect \A $and$ls180.v:7237$2406_Y connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7431$2548_Y + connect \Y $and$ls180.v:7237$2407_Y end - attribute \src "ls180.v:7434.39-7434.82" - cell $and $and$ls180.v:7434$2549 + attribute \src "ls180.v:7240.39-7240.82" + cell $and $and$ls180.v:7240$2408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267634,21 +265922,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7434$2549_Y + connect \Y $and$ls180.v:7240$2408_Y end - attribute \src "ls180.v:7434.38-7434.111" - cell $and $and$ls180.v:7434$2550 + attribute \src "ls180.v:7240.38-7240.111" + cell $and $and$ls180.v:7240$2409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7434$2549_Y + connect \A $and$ls180.v:7240$2408_Y connect \B \main_sdram_cmd_payload_we - connect \Y $and$ls180.v:7434$2550_Y + connect \Y $and$ls180.v:7240$2409_Y end - attribute \src "ls180.v:7445.39-7445.104" - cell $and $and$ls180.v:7445$2552 + attribute \src "ls180.v:7251.39-7251.104" + cell $and $and$ls180.v:7251$2411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267656,21 +265944,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7445$2552_Y + connect \Y $and$ls180.v:7251$2411_Y end - attribute \src "ls180.v:7445.38-7445.149" - cell $and $and$ls180.v:7445$2553 + attribute \src "ls180.v:7251.38-7251.149" + cell $and $and$ls180.v:7251$2412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7445$2552_Y + connect \A $and$ls180.v:7251$2411_Y connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7445$2553_Y + connect \Y $and$ls180.v:7251$2412_Y end - attribute \src "ls180.v:7448.39-7448.104" - cell $and $and$ls180.v:7448$2554 + attribute \src "ls180.v:7254.39-7254.104" + cell $and $and$ls180.v:7254$2413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267678,21 +265966,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7448$2554_Y + connect \Y $and$ls180.v:7254$2413_Y end - attribute \src "ls180.v:7448.38-7448.149" - cell $and $and$ls180.v:7448$2555 + attribute \src "ls180.v:7254.38-7254.149" + cell $and $and$ls180.v:7254$2414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7448$2554_Y + connect \A $and$ls180.v:7254$2413_Y connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7448$2555_Y + connect \Y $and$ls180.v:7254$2414_Y end - attribute \src "ls180.v:7451.39-7451.82" - cell $and $and$ls180.v:7451$2556 + attribute \src "ls180.v:7257.39-7257.82" + cell $and $and$ls180.v:7257$2415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267700,21 +265988,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7451$2556_Y + connect \Y $and$ls180.v:7257$2415_Y end - attribute \src "ls180.v:7451.38-7451.116" - cell $and $and$ls180.v:7451$2557 + attribute \src "ls180.v:7257.38-7257.116" + cell $and $and$ls180.v:7257$2416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7451$2556_Y + connect \A $and$ls180.v:7257$2415_Y connect \B \main_sdram_cmd_payload_is_read - connect \Y $and$ls180.v:7451$2557_Y + connect \Y $and$ls180.v:7257$2416_Y end - attribute \src "ls180.v:7462.39-7462.104" - cell $and $and$ls180.v:7462$2559 + attribute \src "ls180.v:7268.39-7268.104" + cell $and $and$ls180.v:7268$2418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267722,21 +266010,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7462$2559_Y + connect \Y $and$ls180.v:7268$2418_Y end - attribute \src "ls180.v:7462.38-7462.150" - cell $and $and$ls180.v:7462$2560 + attribute \src "ls180.v:7268.38-7268.150" + cell $and $and$ls180.v:7268$2419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7462$2559_Y + connect \A $and$ls180.v:7268$2418_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7462$2560_Y + connect \Y $and$ls180.v:7268$2419_Y end - attribute \src "ls180.v:7465.39-7465.104" - cell $and $and$ls180.v:7465$2561 + attribute \src "ls180.v:7271.39-7271.104" + cell $and $and$ls180.v:7271$2420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267744,21 +266032,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7465$2561_Y + connect \Y $and$ls180.v:7271$2420_Y end - attribute \src "ls180.v:7465.38-7465.150" - cell $and $and$ls180.v:7465$2562 + attribute \src "ls180.v:7271.38-7271.150" + cell $and $and$ls180.v:7271$2421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7465$2561_Y + connect \A $and$ls180.v:7271$2420_Y connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7465$2562_Y + connect \Y $and$ls180.v:7271$2421_Y end - attribute \src "ls180.v:7468.39-7468.82" - cell $and $and$ls180.v:7468$2563 + attribute \src "ls180.v:7274.39-7274.82" + cell $and $and$ls180.v:7274$2422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267766,21 +266054,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_cmd_valid connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7468$2563_Y + connect \Y $and$ls180.v:7274$2422_Y end - attribute \src "ls180.v:7468.38-7468.117" - cell $and $and$ls180.v:7468$2564 + attribute \src "ls180.v:7274.38-7274.117" + cell $and $and$ls180.v:7274$2423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7468$2563_Y + connect \A $and$ls180.v:7274$2422_Y connect \B \main_sdram_cmd_payload_is_write - connect \Y $and$ls180.v:7468$2564_Y + connect \Y $and$ls180.v:7274$2423_Y end - attribute \src "ls180.v:7687.18-7687.68" - cell $and $and$ls180.v:7687$2571 + attribute \src "ls180.v:7493.18-7493.68" + cell $and $and$ls180.v:7493$2430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267788,10 +266076,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_dfi_p0_wrdata_en connect \B \main_dfi_p0_wrdata_mask [0] - connect \Y $and$ls180.v:7687$2571_Y + connect \Y $and$ls180.v:7493$2430_Y end - attribute \src "ls180.v:7688.18-7688.68" - cell $and $and$ls180.v:7688$2572 + attribute \src "ls180.v:7494.18-7494.68" + cell $and $and$ls180.v:7494$2431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267799,21 +266087,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_dfi_p0_wrdata_en connect \B \main_dfi_p0_wrdata_mask [1] - connect \Y $and$ls180.v:7688$2572_Y + connect \Y $and$ls180.v:7494$2431_Y end - attribute \src "ls180.v:7690.17-7690.67" - cell $and $and$ls180.v:7690$2574 + attribute \src "ls180.v:7496.17-7496.67" + cell $and $and$ls180.v:7496$2433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7690$2573_Y + connect \A $not$ls180.v:7496$2432_Y connect \B \main_sdphy_sdpads_clk - connect \Y $and$ls180.v:7690$2574_Y + connect \Y $and$ls180.v:7496$2433_Y end - attribute \src "ls180.v:7769.8-7769.67" - cell $and $and$ls180.v:7769$2605 + attribute \src "ls180.v:7575.8-7575.67" + cell $and $and$ls180.v:7575$2464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267821,142 +266109,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_cyc connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:7769$2605_Y + connect \Y $and$ls180.v:7575$2464_Y end - attribute \src "ls180.v:7769.7-7769.102" - cell $and $and$ls180.v:7769$2607 + attribute \src "ls180.v:7575.7-7575.102" + cell $and $and$ls180.v:7575$2466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7769$2605_Y - connect \B $not$ls180.v:7769$2606_Y - connect \Y $and$ls180.v:7769$2607_Y + connect \A $and$ls180.v:7575$2464_Y + connect \B $not$ls180.v:7575$2465_Y + connect \Y $and$ls180.v:7575$2466_Y end - attribute \src "ls180.v:7788.7-7788.75" - cell $and $and$ls180.v:7788$2611 + attribute \src "ls180.v:7594.7-7594.75" + cell $and $and$ls180.v:7594$2470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7788$2610_Y + connect \A $not$ls180.v:7594$2469_Y connect \B \main_libresocsim_zero_old_trigger - connect \Y $and$ls180.v:7788$2611_Y - end - attribute \src "ls180.v:7792.8-7792.65" - cell $and $and$ls180.v:7792$2612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_cyc - connect \B \main_interface0_ram_bus_stb - connect \Y $and$ls180.v:7792$2612_Y - end - attribute \src "ls180.v:7792.7-7792.99" - cell $and $and$ls180.v:7792$2614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7792$2612_Y - connect \B $not$ls180.v:7792$2613_Y - connect \Y $and$ls180.v:7792$2614_Y - end - attribute \src "ls180.v:7796.8-7796.65" - cell $and $and$ls180.v:7796$2615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_cyc - connect \B \main_interface1_ram_bus_stb - connect \Y $and$ls180.v:7796$2615_Y - end - attribute \src "ls180.v:7796.7-7796.99" - cell $and $and$ls180.v:7796$2617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7796$2615_Y - connect \B $not$ls180.v:7796$2616_Y - connect \Y $and$ls180.v:7796$2617_Y + connect \Y $and$ls180.v:7594$2470_Y end - attribute \src "ls180.v:7800.8-7800.65" - cell $and $and$ls180.v:7800$2618 + attribute \src "ls180.v:7598.8-7598.59" + cell $and $and$ls180.v:7598$2471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_cyc - connect \B \main_interface2_ram_bus_stb - connect \Y $and$ls180.v:7800$2618_Y + connect \A \main_ram_bus_ram_bus_cyc + connect \B \main_ram_bus_ram_bus_stb + connect \Y $and$ls180.v:7598$2471_Y end - attribute \src "ls180.v:7800.7-7800.99" - cell $and $and$ls180.v:7800$2620 + attribute \src "ls180.v:7598.7-7598.90" + cell $and $and$ls180.v:7598$2473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7800$2618_Y - connect \B $not$ls180.v:7800$2619_Y - connect \Y $and$ls180.v:7800$2620_Y + connect \A $and$ls180.v:7598$2471_Y + connect \B $not$ls180.v:7598$2472_Y + connect \Y $and$ls180.v:7598$2473_Y end - attribute \src "ls180.v:7804.8-7804.65" - cell $and $and$ls180.v:7804$2621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_cyc - connect \B \main_interface3_ram_bus_stb - connect \Y $and$ls180.v:7804$2621_Y - end - attribute \src "ls180.v:7804.7-7804.99" - cell $and $and$ls180.v:7804$2623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7804$2621_Y - connect \B $not$ls180.v:7804$2622_Y - connect \Y $and$ls180.v:7804$2623_Y - end - attribute \src "ls180.v:7812.7-7812.56" - cell $and $and$ls180.v:7812$2625 + attribute \src "ls180.v:7606.7-7606.56" + cell $and $and$ls180.v:7606$2475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_wait - connect \B $not$ls180.v:7812$2624_Y - connect \Y $and$ls180.v:7812$2625_Y + connect \B $not$ls180.v:7606$2474_Y + connect \Y $and$ls180.v:7606$2475_Y end - attribute \src "ls180.v:7840.7-7840.75" - cell $and $and$ls180.v:7840$2632 + attribute \src "ls180.v:7634.7-7634.75" + cell $and $and$ls180.v:7634$2482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_start1 - connect \B $eq$ls180.v:7840$2631_Y - connect \Y $and$ls180.v:7840$2632_Y + connect \B $eq$ls180.v:7634$2481_Y + connect \Y $and$ls180.v:7634$2482_Y end - attribute \src "ls180.v:7882.8-7882.131" - cell $and $and$ls180.v:7882$2638 + attribute \src "ls180.v:7676.8-7676.131" + cell $and $and$ls180.v:7676$2488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267964,21 +266186,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7882$2638_Y + connect \Y $and$ls180.v:7676$2488_Y end - attribute \src "ls180.v:7882.7-7882.190" - cell $and $and$ls180.v:7882$2640 + attribute \src "ls180.v:7676.7-7676.190" + cell $and $and$ls180.v:7676$2490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7882$2638_Y - connect \B $not$ls180.v:7882$2639_Y - connect \Y $and$ls180.v:7882$2640_Y + connect \A $and$ls180.v:7676$2488_Y + connect \B $not$ls180.v:7676$2489_Y + connect \Y $and$ls180.v:7676$2490_Y end - attribute \src "ls180.v:7888.8-7888.131" - cell $and $and$ls180.v:7888$2643 + attribute \src "ls180.v:7682.8-7682.131" + cell $and $and$ls180.v:7682$2493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -267986,21 +266208,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7888$2643_Y + connect \Y $and$ls180.v:7682$2493_Y end - attribute \src "ls180.v:7888.7-7888.190" - cell $and $and$ls180.v:7888$2645 + attribute \src "ls180.v:7682.7-7682.190" + cell $and $and$ls180.v:7682$2495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7888$2643_Y - connect \B $not$ls180.v:7888$2644_Y - connect \Y $and$ls180.v:7888$2645_Y + connect \A $and$ls180.v:7682$2493_Y + connect \B $not$ls180.v:7682$2494_Y + connect \Y $and$ls180.v:7682$2495_Y end - attribute \src "ls180.v:7928.8-7928.131" - cell $and $and$ls180.v:7928$2654 + attribute \src "ls180.v:7722.8-7722.131" + cell $and $and$ls180.v:7722$2504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268008,21 +266230,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7928$2654_Y + connect \Y $and$ls180.v:7722$2504_Y end - attribute \src "ls180.v:7928.7-7928.190" - cell $and $and$ls180.v:7928$2656 + attribute \src "ls180.v:7722.7-7722.190" + cell $and $and$ls180.v:7722$2506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7928$2654_Y - connect \B $not$ls180.v:7928$2655_Y - connect \Y $and$ls180.v:7928$2656_Y + connect \A $and$ls180.v:7722$2504_Y + connect \B $not$ls180.v:7722$2505_Y + connect \Y $and$ls180.v:7722$2506_Y end - attribute \src "ls180.v:7934.8-7934.131" - cell $and $and$ls180.v:7934$2659 + attribute \src "ls180.v:7728.8-7728.131" + cell $and $and$ls180.v:7728$2509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268030,21 +266252,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7934$2659_Y + connect \Y $and$ls180.v:7728$2509_Y end - attribute \src "ls180.v:7934.7-7934.190" - cell $and $and$ls180.v:7934$2661 + attribute \src "ls180.v:7728.7-7728.190" + cell $and $and$ls180.v:7728$2511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7934$2659_Y - connect \B $not$ls180.v:7934$2660_Y - connect \Y $and$ls180.v:7934$2661_Y + connect \A $and$ls180.v:7728$2509_Y + connect \B $not$ls180.v:7728$2510_Y + connect \Y $and$ls180.v:7728$2511_Y end - attribute \src "ls180.v:7974.8-7974.131" - cell $and $and$ls180.v:7974$2670 + attribute \src "ls180.v:7768.8-7768.131" + cell $and $and$ls180.v:7768$2520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268052,21 +266274,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7974$2670_Y + connect \Y $and$ls180.v:7768$2520_Y end - attribute \src "ls180.v:7974.7-7974.190" - cell $and $and$ls180.v:7974$2672 + attribute \src "ls180.v:7768.7-7768.190" + cell $and $and$ls180.v:7768$2522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7974$2670_Y - connect \B $not$ls180.v:7974$2671_Y - connect \Y $and$ls180.v:7974$2672_Y + connect \A $and$ls180.v:7768$2520_Y + connect \B $not$ls180.v:7768$2521_Y + connect \Y $and$ls180.v:7768$2522_Y end - attribute \src "ls180.v:7980.8-7980.131" - cell $and $and$ls180.v:7980$2675 + attribute \src "ls180.v:7774.8-7774.131" + cell $and $and$ls180.v:7774$2525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268074,21 +266296,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7980$2675_Y + connect \Y $and$ls180.v:7774$2525_Y end - attribute \src "ls180.v:7980.7-7980.190" - cell $and $and$ls180.v:7980$2677 + attribute \src "ls180.v:7774.7-7774.190" + cell $and $and$ls180.v:7774$2527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7980$2675_Y - connect \B $not$ls180.v:7980$2676_Y - connect \Y $and$ls180.v:7980$2677_Y + connect \A $and$ls180.v:7774$2525_Y + connect \B $not$ls180.v:7774$2526_Y + connect \Y $and$ls180.v:7774$2527_Y end - attribute \src "ls180.v:8020.8-8020.131" - cell $and $and$ls180.v:8020$2686 + attribute \src "ls180.v:7814.8-7814.131" + cell $and $and$ls180.v:7814$2536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268096,21 +266318,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:8020$2686_Y + connect \Y $and$ls180.v:7814$2536_Y end - attribute \src "ls180.v:8020.7-8020.190" - cell $and $and$ls180.v:8020$2688 + attribute \src "ls180.v:7814.7-7814.190" + cell $and $and$ls180.v:7814$2538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8020$2686_Y - connect \B $not$ls180.v:8020$2687_Y - connect \Y $and$ls180.v:8020$2688_Y + connect \A $and$ls180.v:7814$2536_Y + connect \B $not$ls180.v:7814$2537_Y + connect \Y $and$ls180.v:7814$2538_Y end - attribute \src "ls180.v:8026.8-8026.131" - cell $and $and$ls180.v:8026$2691 + attribute \src "ls180.v:7820.8-7820.131" + cell $and $and$ls180.v:7820$2541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268118,109 +266340,109 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:8026$2691_Y + connect \Y $and$ls180.v:7820$2541_Y end - attribute \src "ls180.v:8026.7-8026.190" - cell $and $and$ls180.v:8026$2693 + attribute \src "ls180.v:7820.7-7820.190" + cell $and $and$ls180.v:7820$2543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8026$2691_Y - connect \B $not$ls180.v:8026$2692_Y - connect \Y $and$ls180.v:8026$2693_Y + connect \A $and$ls180.v:7820$2541_Y + connect \B $not$ls180.v:7820$2542_Y + connect \Y $and$ls180.v:7820$2543_Y end - attribute \src "ls180.v:8223.48-8223.124" - cell $and $and$ls180.v:8223$2718 + attribute \src "ls180.v:8017.48-8017.124" + cell $and $and$ls180.v:8017$2568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8223$2717_Y + connect \A $eq$ls180.v:8017$2567_Y connect \B \main_sdram_interface_bank0_wdata_ready - connect \Y $and$ls180.v:8223$2718_Y + connect \Y $and$ls180.v:8017$2568_Y end - attribute \src "ls180.v:8223.130-8223.206" - cell $and $and$ls180.v:8223$2721 + attribute \src "ls180.v:8017.130-8017.206" + cell $and $and$ls180.v:8017$2571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8223$2720_Y + connect \A $eq$ls180.v:8017$2570_Y connect \B \main_sdram_interface_bank1_wdata_ready - connect \Y $and$ls180.v:8223$2721_Y + connect \Y $and$ls180.v:8017$2571_Y end - attribute \src "ls180.v:8223.212-8223.288" - cell $and $and$ls180.v:8223$2724 + attribute \src "ls180.v:8017.212-8017.288" + cell $and $and$ls180.v:8017$2574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8223$2723_Y + connect \A $eq$ls180.v:8017$2573_Y connect \B \main_sdram_interface_bank2_wdata_ready - connect \Y $and$ls180.v:8223$2724_Y + connect \Y $and$ls180.v:8017$2574_Y end - attribute \src "ls180.v:8223.294-8223.370" - cell $and $and$ls180.v:8223$2727 + attribute \src "ls180.v:8017.294-8017.370" + cell $and $and$ls180.v:8017$2577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8223$2726_Y + connect \A $eq$ls180.v:8017$2576_Y connect \B \main_sdram_interface_bank3_wdata_ready - connect \Y $and$ls180.v:8223$2727_Y + connect \Y $and$ls180.v:8017$2577_Y end - attribute \src "ls180.v:8224.49-8224.125" - cell $and $and$ls180.v:8224$2730 + attribute \src "ls180.v:8018.49-8018.125" + cell $and $and$ls180.v:8018$2580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8224$2729_Y + connect \A $eq$ls180.v:8018$2579_Y connect \B \main_sdram_interface_bank0_rdata_valid - connect \Y $and$ls180.v:8224$2730_Y + connect \Y $and$ls180.v:8018$2580_Y end - attribute \src "ls180.v:8224.131-8224.207" - cell $and $and$ls180.v:8224$2733 + attribute \src "ls180.v:8018.131-8018.207" + cell $and $and$ls180.v:8018$2583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8224$2732_Y + connect \A $eq$ls180.v:8018$2582_Y connect \B \main_sdram_interface_bank1_rdata_valid - connect \Y $and$ls180.v:8224$2733_Y + connect \Y $and$ls180.v:8018$2583_Y end - attribute \src "ls180.v:8224.213-8224.289" - cell $and $and$ls180.v:8224$2736 + attribute \src "ls180.v:8018.213-8018.289" + cell $and $and$ls180.v:8018$2586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8224$2735_Y + connect \A $eq$ls180.v:8018$2585_Y connect \B \main_sdram_interface_bank2_rdata_valid - connect \Y $and$ls180.v:8224$2736_Y + connect \Y $and$ls180.v:8018$2586_Y end - attribute \src "ls180.v:8224.295-8224.371" - cell $and $and$ls180.v:8224$2739 + attribute \src "ls180.v:8018.295-8018.371" + cell $and $and$ls180.v:8018$2589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8224$2738_Y + connect \A $eq$ls180.v:8018$2588_Y connect \B \main_sdram_interface_bank3_rdata_valid - connect \Y $and$ls180.v:8224$2739_Y + connect \Y $and$ls180.v:8018$2589_Y end - attribute \src "ls180.v:8243.8-8243.49" - cell $and $and$ls180.v:8243$2742 + attribute \src "ls180.v:8037.8-8037.49" + cell $and $and$ls180.v:8037$2592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268228,10 +266450,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:8243$2742_Y + connect \Y $and$ls180.v:8037$2592_Y end - attribute \src "ls180.v:8246.8-8246.53" - cell $and $and$ls180.v:8246$2743 + attribute \src "ls180.v:8040.8-8040.53" + cell $and $and$ls180.v:8040$2593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268239,32 +266461,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_wdata_valid connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:8246$2743_Y + connect \Y $and$ls180.v:8040$2593_Y end - attribute \src "ls180.v:8251.8-8251.59" - cell $and $and$ls180.v:8251$2745 + attribute \src "ls180.v:8045.8-8045.59" + cell $and $and$ls180.v:8045$2595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_sink_valid - connect \B $not$ls180.v:8251$2744_Y - connect \Y $and$ls180.v:8251$2745_Y + connect \B $not$ls180.v:8045$2594_Y + connect \Y $and$ls180.v:8045$2595_Y end - attribute \src "ls180.v:8251.7-8251.90" - cell $and $and$ls180.v:8251$2747 + attribute \src "ls180.v:8045.7-8045.90" + cell $and $and$ls180.v:8045$2597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8251$2745_Y - connect \B $not$ls180.v:8251$2746_Y - connect \Y $and$ls180.v:8251$2747_Y + connect \A $and$ls180.v:8045$2595_Y + connect \B $not$ls180.v:8045$2596_Y + connect \Y $and$ls180.v:8045$2597_Y end - attribute \src "ls180.v:8257.8-8257.59" - cell $and $and$ls180.v:8257$2748 + attribute \src "ls180.v:8051.8-8051.59" + cell $and $and$ls180.v:8051$2598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268272,43 +266494,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_uart_clk_txen connect \B \main_uart_phy_tx_busy - connect \Y $and$ls180.v:8257$2748_Y + connect \Y $and$ls180.v:8051$2598_Y end - attribute \src "ls180.v:8281.8-8281.48" - cell $and $and$ls180.v:8281$2755 + attribute \src "ls180.v:8075.8-8075.48" + cell $and $and$ls180.v:8075$2605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8281$2754_Y + connect \A $not$ls180.v:8075$2604_Y connect \B \main_uart_phy_rx_r - connect \Y $and$ls180.v:8281$2755_Y + connect \Y $and$ls180.v:8075$2605_Y end - attribute \src "ls180.v:8314.7-8314.57" - cell $and $and$ls180.v:8314$2761 + attribute \src "ls180.v:8108.7-8108.57" + cell $and $and$ls180.v:8108$2611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8314$2760_Y + connect \A $not$ls180.v:8108$2610_Y connect \B \main_uart_tx_old_trigger - connect \Y $and$ls180.v:8314$2761_Y + connect \Y $and$ls180.v:8108$2611_Y end - attribute \src "ls180.v:8321.7-8321.57" - cell $and $and$ls180.v:8321$2763 + attribute \src "ls180.v:8115.7-8115.57" + cell $and $and$ls180.v:8115$2613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8321$2762_Y + connect \A $not$ls180.v:8115$2612_Y connect \B \main_uart_rx_old_trigger - connect \Y $and$ls180.v:8321$2763_Y + connect \Y $and$ls180.v:8115$2613_Y end - attribute \src "ls180.v:8331.8-8331.75" - cell $and $and$ls180.v:8331$2764 + attribute \src "ls180.v:8125.8-8125.75" + cell $and $and$ls180.v:8125$2614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268316,21 +266538,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8331$2764_Y + connect \Y $and$ls180.v:8125$2614_Y end - attribute \src "ls180.v:8331.7-8331.107" - cell $and $and$ls180.v:8331$2766 + attribute \src "ls180.v:8125.7-8125.107" + cell $and $and$ls180.v:8125$2616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8331$2764_Y - connect \B $not$ls180.v:8331$2765_Y - connect \Y $and$ls180.v:8331$2766_Y + connect \A $and$ls180.v:8125$2614_Y + connect \B $not$ls180.v:8125$2615_Y + connect \Y $and$ls180.v:8125$2616_Y end - attribute \src "ls180.v:8337.8-8337.75" - cell $and $and$ls180.v:8337$2769 + attribute \src "ls180.v:8131.8-8131.75" + cell $and $and$ls180.v:8131$2619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268338,21 +266560,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_we connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8337$2769_Y + connect \Y $and$ls180.v:8131$2619_Y end - attribute \src "ls180.v:8337.7-8337.107" - cell $and $and$ls180.v:8337$2771 + attribute \src "ls180.v:8131.7-8131.107" + cell $and $and$ls180.v:8131$2621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8337$2769_Y - connect \B $not$ls180.v:8337$2770_Y - connect \Y $and$ls180.v:8337$2771_Y + connect \A $and$ls180.v:8131$2619_Y + connect \B $not$ls180.v:8131$2620_Y + connect \Y $and$ls180.v:8131$2621_Y end - attribute \src "ls180.v:8353.8-8353.75" - cell $and $and$ls180.v:8353$2775 + attribute \src "ls180.v:8147.8-8147.75" + cell $and $and$ls180.v:8147$2625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268360,21 +266582,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8353$2775_Y + connect \Y $and$ls180.v:8147$2625_Y end - attribute \src "ls180.v:8353.7-8353.107" - cell $and $and$ls180.v:8353$2777 + attribute \src "ls180.v:8147.7-8147.107" + cell $and $and$ls180.v:8147$2627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8353$2775_Y - connect \B $not$ls180.v:8353$2776_Y - connect \Y $and$ls180.v:8353$2777_Y + connect \A $and$ls180.v:8147$2625_Y + connect \B $not$ls180.v:8147$2626_Y + connect \Y $and$ls180.v:8147$2627_Y end - attribute \src "ls180.v:8359.8-8359.75" - cell $and $and$ls180.v:8359$2780 + attribute \src "ls180.v:8153.8-8153.75" + cell $and $and$ls180.v:8153$2630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268382,21 +266604,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_we connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8359$2780_Y + connect \Y $and$ls180.v:8153$2630_Y end - attribute \src "ls180.v:8359.7-8359.107" - cell $and $and$ls180.v:8359$2782 + attribute \src "ls180.v:8153.7-8153.107" + cell $and $and$ls180.v:8153$2632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8359$2780_Y - connect \B $not$ls180.v:8359$2781_Y - connect \Y $and$ls180.v:8359$2782_Y + connect \A $and$ls180.v:8153$2630_Y + connect \B $not$ls180.v:8153$2631_Y + connect \Y $and$ls180.v:8153$2632_Y end - attribute \src "ls180.v:8507.7-8507.96" - cell $and $and$ls180.v:8507$2810 + attribute \src "ls180.v:8301.7-8301.96" + cell $and $and$ls180.v:8301$2660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268404,10 +266626,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_source_valid connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $and$ls180.v:8507$2810_Y + connect \Y $and$ls180.v:8301$2660_Y end - attribute \src "ls180.v:8508.8-8508.93" - cell $and $and$ls180.v:8508$2811 + attribute \src "ls180.v:8302.8-8302.93" + cell $and $and$ls180.v:8302$2661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268415,10 +266637,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8508$2811_Y + connect \Y $and$ls180.v:8302$2661_Y end - attribute \src "ls180.v:8516.8-8516.93" - cell $and $and$ls180.v:8516$2812 + attribute \src "ls180.v:8310.8-8310.93" + cell $and $and$ls180.v:8310$2662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268426,10 +266648,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8516$2812_Y + connect \Y $and$ls180.v:8310$2662_Y end - attribute \src "ls180.v:8588.7-8588.98" - cell $and $and$ls180.v:8588$2822 + attribute \src "ls180.v:8382.7-8382.98" + cell $and $and$ls180.v:8382$2672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268437,10 +266659,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_source_valid connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $and$ls180.v:8588$2822_Y + connect \Y $and$ls180.v:8382$2672_Y end - attribute \src "ls180.v:8589.8-8589.95" - cell $and $and$ls180.v:8589$2823 + attribute \src "ls180.v:8383.8-8383.95" + cell $and $and$ls180.v:8383$2673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268448,10 +266670,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8589$2823_Y + connect \Y $and$ls180.v:8383$2673_Y end - attribute \src "ls180.v:8597.8-8597.95" - cell $and $and$ls180.v:8597$2824 + attribute \src "ls180.v:8391.8-8391.95" + cell $and $and$ls180.v:8391$2674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268459,10 +266681,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_valid connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8597$2824_Y + connect \Y $and$ls180.v:8391$2674_Y end - attribute \src "ls180.v:8667.7-8667.100" - cell $and $and$ls180.v:8667$2834 + attribute \src "ls180.v:8461.7-8461.100" + cell $and $and$ls180.v:8461$2684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268470,10 +266692,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_source_valid connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $and$ls180.v:8667$2834_Y + connect \Y $and$ls180.v:8461$2684_Y end - attribute \src "ls180.v:8668.8-8668.97" - cell $and $and$ls180.v:8668$2835 + attribute \src "ls180.v:8462.8-8462.97" + cell $and $and$ls180.v:8462$2685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268481,10 +266703,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8668$2835_Y + connect \Y $and$ls180.v:8462$2685_Y end - attribute \src "ls180.v:8676.8-8676.97" - cell $and $and$ls180.v:8676$2836 + attribute \src "ls180.v:8470.8-8470.97" + cell $and $and$ls180.v:8470$2686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268492,10 +266714,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_valid connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8676$2836_Y + connect \Y $and$ls180.v:8470$2686_Y end - attribute \src "ls180.v:8767.7-8767.82" - cell $and $and$ls180.v:8767$2842 + attribute \src "ls180.v:8561.7-8561.82" + cell $and $and$ls180.v:8561$2692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268503,10 +266725,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8767$2842_Y + connect \Y $and$ls180.v:8561$2692_Y end - attribute \src "ls180.v:8770.7-8770.82" - cell $and $and$ls180.v:8770$2843 + attribute \src "ls180.v:8564.7-8564.82" + cell $and $and$ls180.v:8564$2693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268514,10 +266736,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8770$2843_Y + connect \Y $and$ls180.v:8564$2693_Y end - attribute \src "ls180.v:8773.7-8773.82" - cell $and $and$ls180.v:8773$2844 + attribute \src "ls180.v:8567.7-8567.82" + cell $and $and$ls180.v:8567$2694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268525,10 +266747,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8773$2844_Y + connect \Y $and$ls180.v:8567$2694_Y end - attribute \src "ls180.v:8776.7-8776.82" - cell $and $and$ls180.v:8776$2845 + attribute \src "ls180.v:8570.7-8570.82" + cell $and $and$ls180.v:8570$2695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268536,10 +266758,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_ready connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8776$2845_Y + connect \Y $and$ls180.v:8570$2695_Y end - attribute \src "ls180.v:8779.7-8779.82" - cell $and $and$ls180.v:8779$2846 + attribute \src "ls180.v:8573.7-8573.82" + cell $and $and$ls180.v:8573$2696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268547,10 +266769,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8779$2846_Y + connect \Y $and$ls180.v:8573$2696_Y end - attribute \src "ls180.v:8784.7-8784.82" - cell $and $and$ls180.v:8784$2847 + attribute \src "ls180.v:8578.7-8578.82" + cell $and $and$ls180.v:8578$2697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268558,10 +266780,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8784$2847_Y + connect \Y $and$ls180.v:8578$2697_Y end - attribute \src "ls180.v:8789.7-8789.82" - cell $and $and$ls180.v:8789$2848 + attribute \src "ls180.v:8583.7-8583.82" + cell $and $and$ls180.v:8583$2698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268569,10 +266791,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8789$2848_Y + connect \Y $and$ls180.v:8583$2698_Y end - attribute \src "ls180.v:8794.7-8794.82" - cell $and $and$ls180.v:8794$2849 + attribute \src "ls180.v:8588.7-8588.82" + cell $and $and$ls180.v:8588$2699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268580,10 +266802,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8794$2849_Y + connect \Y $and$ls180.v:8588$2699_Y end - attribute \src "ls180.v:8799.7-8799.82" - cell $and $and$ls180.v:8799$2850 + attribute \src "ls180.v:8593.7-8593.82" + cell $and $and$ls180.v:8593$2700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268591,10 +266813,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_sink_valid connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8799$2850_Y + connect \Y $and$ls180.v:8593$2700_Y end - attribute \src "ls180.v:8864.8-8864.83" - cell $and $and$ls180.v:8864$2853 + attribute \src "ls180.v:8658.8-8658.83" + cell $and $and$ls180.v:8658$2703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268602,21 +266824,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8864$2853_Y + connect \Y $and$ls180.v:8658$2703_Y end - attribute \src "ls180.v:8864.7-8864.119" - cell $and $and$ls180.v:8864$2855 + attribute \src "ls180.v:8658.7-8658.119" + cell $and $and$ls180.v:8658$2705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8864$2853_Y - connect \B $not$ls180.v:8864$2854_Y - connect \Y $and$ls180.v:8864$2855_Y + connect \A $and$ls180.v:8658$2703_Y + connect \B $not$ls180.v:8658$2704_Y + connect \Y $and$ls180.v:8658$2705_Y end - attribute \src "ls180.v:8870.8-8870.83" - cell $and $and$ls180.v:8870$2858 + attribute \src "ls180.v:8664.8-8664.83" + cell $and $and$ls180.v:8664$2708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268624,21 +266846,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_we connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8870$2858_Y + connect \Y $and$ls180.v:8664$2708_Y end - attribute \src "ls180.v:8870.7-8870.119" - cell $and $and$ls180.v:8870$2860 + attribute \src "ls180.v:8664.7-8664.119" + cell $and $and$ls180.v:8664$2710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8870$2858_Y - connect \B $not$ls180.v:8870$2859_Y - connect \Y $and$ls180.v:8870$2860_Y + connect \A $and$ls180.v:8664$2708_Y + connect \B $not$ls180.v:8664$2709_Y + connect \Y $and$ls180.v:8664$2710_Y end - attribute \src "ls180.v:8890.7-8890.88" - cell $and $and$ls180.v:8890$2867 + attribute \src "ls180.v:8684.7-8684.88" + cell $and $and$ls180.v:8684$2717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268646,10 +266868,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_source_valid connect \B \main_sdblock2mem_converter_source_ready - connect \Y $and$ls180.v:8890$2867_Y + connect \Y $and$ls180.v:8684$2717_Y end - attribute \src "ls180.v:8891.8-8891.85" - cell $and $and$ls180.v:8891$2868 + attribute \src "ls180.v:8685.8-8685.85" + cell $and $and$ls180.v:8685$2718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268657,10 +266879,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8891$2868_Y + connect \Y $and$ls180.v:8685$2718_Y end - attribute \src "ls180.v:8899.8-8899.85" - cell $and $and$ls180.v:8899$2869 + attribute \src "ls180.v:8693.8-8693.85" + cell $and $and$ls180.v:8693$2719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268668,10 +266890,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_valid connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8899$2869_Y + connect \Y $and$ls180.v:8693$2719_Y end - attribute \src "ls180.v:8955.7-8955.88" - cell $and $and$ls180.v:8955$2873 + attribute \src "ls180.v:8749.7-8749.88" + cell $and $and$ls180.v:8749$2723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268679,10 +266901,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_source_valid connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:8955$2873_Y + connect \Y $and$ls180.v:8749$2723_Y end - attribute \src "ls180.v:8962.8-8962.83" - cell $and $and$ls180.v:8962$2875 + attribute \src "ls180.v:8756.8-8756.83" + cell $and $and$ls180.v:8756$2725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268690,21 +266912,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8962$2875_Y + connect \Y $and$ls180.v:8756$2725_Y end - attribute \src "ls180.v:8962.7-8962.119" - cell $and $and$ls180.v:8962$2877 + attribute \src "ls180.v:8756.7-8756.119" + cell $and $and$ls180.v:8756$2727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8962$2875_Y - connect \B $not$ls180.v:8962$2876_Y - connect \Y $and$ls180.v:8962$2877_Y + connect \A $and$ls180.v:8756$2725_Y + connect \B $not$ls180.v:8756$2726_Y + connect \Y $and$ls180.v:8756$2727_Y end - attribute \src "ls180.v:8968.8-8968.83" - cell $and $and$ls180.v:8968$2880 + attribute \src "ls180.v:8762.8-8762.83" + cell $and $and$ls180.v:8762$2730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268712,21 +266934,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_we connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8968$2880_Y + connect \Y $and$ls180.v:8762$2730_Y end - attribute \src "ls180.v:8968.7-8968.119" - cell $and $and$ls180.v:8968$2882 + attribute \src "ls180.v:8762.7-8762.119" + cell $and $and$ls180.v:8762$2732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8968$2880_Y - connect \B $not$ls180.v:8968$2881_Y - connect \Y $and$ls180.v:8968$2882_Y + connect \A $and$ls180.v:8762$2730_Y + connect \B $not$ls180.v:8762$2731_Y + connect \Y $and$ls180.v:8762$2732_Y end - attribute \src "ls180.v:2930.30-2930.76" - cell $eq $eq$ls180.v:2930$54 + attribute \src "ls180.v:2841.30-2841.76" + cell $eq $eq$ls180.v:2841$30 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268734,10 +266956,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_xics_icp_sel connect \B 1'0 - connect \Y $eq$ls180.v:2930$54_Y + connect \Y $eq$ls180.v:2841$30_Y end - attribute \src "ls180.v:2937.11-2937.42" - cell $eq $eq$ls180.v:2937$59 + attribute \src "ls180.v:2848.11-2848.42" + cell $eq $eq$ls180.v:2848$35 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268745,10 +266967,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter0_counter connect \B 1'1 - connect \Y $eq$ls180.v:2937$59_Y + connect \Y $eq$ls180.v:2848$35_Y end - attribute \src "ls180.v:2990.30-2990.76" - cell $eq $eq$ls180.v:2990$65 + attribute \src "ls180.v:2901.30-2901.76" + cell $eq $eq$ls180.v:2901$41 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268756,10 +266978,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_xics_ics_sel connect \B 1'0 - connect \Y $eq$ls180.v:2990$65_Y + connect \Y $eq$ls180.v:2901$41_Y end - attribute \src "ls180.v:2997.11-2997.42" - cell $eq $eq$ls180.v:2997$70 + attribute \src "ls180.v:2908.11-2908.42" + cell $eq $eq$ls180.v:2908$46 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268767,10 +266989,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter1_counter connect \B 1'1 - connect \Y $eq$ls180.v:2997$70_Y + connect \Y $eq$ls180.v:2908$46_Y end - attribute \src "ls180.v:3050.33-3050.58" - cell $eq $eq$ls180.v:3050$76 + attribute \src "ls180.v:2961.33-2961.58" + cell $eq $eq$ls180.v:2961$52 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268778,10 +267000,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_sel connect \B 1'0 - connect \Y $eq$ls180.v:3050$76_Y + connect \Y $eq$ls180.v:2961$52_Y end - attribute \src "ls180.v:3057.11-3057.45" - cell $eq $eq$ls180.v:3057$81 + attribute \src "ls180.v:2968.11-2968.45" + cell $eq $eq$ls180.v:2968$57 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268789,10 +267011,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_socbushandler_counter connect \B 1'1 - connect \Y $eq$ls180.v:3057$81_Y + connect \Y $eq$ls180.v:2968$57_Y end - attribute \src "ls180.v:3303.34-3303.65" - cell $eq $eq$ls180.v:3303$221 + attribute \src "ls180.v:3172.34-3172.65" + cell $eq $eq$ls180.v:3172$122 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -268800,10 +267022,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_count1 connect \B 1'0 - connect \Y $eq$ls180.v:3303$221_Y + connect \Y $eq$ls180.v:3172$122_Y end - attribute \src "ls180.v:3307.68-3307.102" - cell $eq $eq$ls180.v:3307$224 + attribute \src "ls180.v:3176.68-3176.102" + cell $eq $eq$ls180.v:3176$125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268811,10 +267033,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $eq$ls180.v:3307$224_Y + connect \Y $eq$ls180.v:3176$125_Y end - attribute \src "ls180.v:3351.43-3351.134" - cell $eq $eq$ls180.v:3351$229 + attribute \src "ls180.v:3220.43-3220.134" + cell $eq $eq$ls180.v:3220$130 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -268822,10 +267044,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_row connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3351$229_Y + connect \Y $eq$ls180.v:3220$130_Y end - attribute \src "ls180.v:3368.47-3368.88" - cell $eq $eq$ls180.v:3368$242 + attribute \src "ls180.v:3237.47-3237.88" + cell $eq $eq$ls180.v:3237$143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268833,10 +267055,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3368$242_Y + connect \Y $eq$ls180.v:3237$143_Y end - attribute \src "ls180.v:3508.43-3508.134" - cell $eq $eq$ls180.v:3508$259 + attribute \src "ls180.v:3377.43-3377.134" + cell $eq $eq$ls180.v:3377$160 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -268844,10 +267066,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_row connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3508$259_Y + connect \Y $eq$ls180.v:3377$160_Y end - attribute \src "ls180.v:3525.47-3525.88" - cell $eq $eq$ls180.v:3525$272 + attribute \src "ls180.v:3394.47-3394.88" + cell $eq $eq$ls180.v:3394$173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268855,10 +267077,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3525$272_Y + connect \Y $eq$ls180.v:3394$173_Y end - attribute \src "ls180.v:3665.43-3665.134" - cell $eq $eq$ls180.v:3665$289 + attribute \src "ls180.v:3534.43-3534.134" + cell $eq $eq$ls180.v:3534$190 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -268866,10 +267088,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_row connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3665$289_Y + connect \Y $eq$ls180.v:3534$190_Y end - attribute \src "ls180.v:3682.47-3682.88" - cell $eq $eq$ls180.v:3682$302 + attribute \src "ls180.v:3551.47-3551.88" + cell $eq $eq$ls180.v:3551$203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268877,10 +267099,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3682$302_Y + connect \Y $eq$ls180.v:3551$203_Y end - attribute \src "ls180.v:3822.43-3822.134" - cell $eq $eq$ls180.v:3822$319 + attribute \src "ls180.v:3691.43-3691.134" + cell $eq $eq$ls180.v:3691$220 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -268888,10 +267110,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_row connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3822$319_Y + connect \Y $eq$ls180.v:3691$220_Y end - attribute \src "ls180.v:3839.47-3839.88" - cell $eq $eq$ls180.v:3839$332 + attribute \src "ls180.v:3708.47-3708.88" + cell $eq $eq$ls180.v:3708$233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268899,10 +267121,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_row_close connect \B 1'0 - connect \Y $eq$ls180.v:3839$332_Y + connect \Y $eq$ls180.v:3708$233_Y end - attribute \src "ls180.v:3976.32-3976.56" - cell $eq $eq$ls180.v:3976$379 + attribute \src "ls180.v:3845.32-3845.56" + cell $eq $eq$ls180.v:3845$280 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -268910,10 +267132,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_time0 connect \B 1'0 - connect \Y $eq$ls180.v:3976$379_Y + connect \Y $eq$ls180.v:3845$280_Y end - attribute \src "ls180.v:3977.32-3977.56" - cell $eq $eq$ls180.v:3977$380 + attribute \src "ls180.v:3846.32-3846.56" + cell $eq $eq$ls180.v:3846$281 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -268921,10 +267143,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_time1 connect \B 1'0 - connect \Y $eq$ls180.v:3977$380_Y + connect \Y $eq$ls180.v:3846$281_Y end - attribute \src "ls180.v:3988.339-3988.418" - cell $eq $eq$ls180.v:3988$394 + attribute \src "ls180.v:3857.339-3857.418" + cell $eq $eq$ls180.v:3857$295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268932,10 +267154,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3988$394_Y + connect \Y $eq$ls180.v:3857$295_Y end - attribute \src "ls180.v:3988.423-3988.504" - cell $eq $eq$ls180.v:3988$395 + attribute \src "ls180.v:3857.423-3857.504" + cell $eq $eq$ls180.v:3857$296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268943,10 +267165,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3988$395_Y + connect \Y $eq$ls180.v:3857$296_Y end - attribute \src "ls180.v:3989.339-3989.418" - cell $eq $eq$ls180.v:3989$407 + attribute \src "ls180.v:3858.339-3858.418" + cell $eq $eq$ls180.v:3858$308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268954,10 +267176,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3989$407_Y + connect \Y $eq$ls180.v:3858$308_Y end - attribute \src "ls180.v:3989.423-3989.504" - cell $eq $eq$ls180.v:3989$408 + attribute \src "ls180.v:3858.423-3858.504" + cell $eq $eq$ls180.v:3858$309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268965,10 +267187,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3989$408_Y + connect \Y $eq$ls180.v:3858$309_Y end - attribute \src "ls180.v:3990.339-3990.418" - cell $eq $eq$ls180.v:3990$420 + attribute \src "ls180.v:3859.339-3859.418" + cell $eq $eq$ls180.v:3859$321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268976,10 +267198,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3990$420_Y + connect \Y $eq$ls180.v:3859$321_Y end - attribute \src "ls180.v:3990.423-3990.504" - cell $eq $eq$ls180.v:3990$421 + attribute \src "ls180.v:3859.423-3859.504" + cell $eq $eq$ls180.v:3859$322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268987,10 +267209,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3990$421_Y + connect \Y $eq$ls180.v:3859$322_Y end - attribute \src "ls180.v:3991.339-3991.418" - cell $eq $eq$ls180.v:3991$433 + attribute \src "ls180.v:3860.339-3860.418" + cell $eq $eq$ls180.v:3860$334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -268998,10 +267220,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_read connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3991$433_Y + connect \Y $eq$ls180.v:3860$334_Y end - attribute \src "ls180.v:3991.423-3991.504" - cell $eq $eq$ls180.v:3991$434 + attribute \src "ls180.v:3860.423-3860.504" + cell $eq $eq$ls180.v:3860$335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269009,10 +267231,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_write connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3991$434_Y + connect \Y $eq$ls180.v:3860$335_Y end - attribute \src "ls180.v:4021.339-4021.418" - cell $eq $eq$ls180.v:4021$452 + attribute \src "ls180.v:3890.339-3890.418" + cell $eq $eq$ls180.v:3890$353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269020,10 +267242,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:4021$452_Y + connect \Y $eq$ls180.v:3890$353_Y end - attribute \src "ls180.v:4021.423-4021.504" - cell $eq $eq$ls180.v:4021$453 + attribute \src "ls180.v:3890.423-3890.504" + cell $eq $eq$ls180.v:3890$354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269031,10 +267253,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:4021$453_Y + connect \Y $eq$ls180.v:3890$354_Y end - attribute \src "ls180.v:4022.339-4022.418" - cell $eq $eq$ls180.v:4022$465 + attribute \src "ls180.v:3891.339-3891.418" + cell $eq $eq$ls180.v:3891$366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269042,10 +267264,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:4022$465_Y + connect \Y $eq$ls180.v:3891$366_Y end - attribute \src "ls180.v:4022.423-4022.504" - cell $eq $eq$ls180.v:4022$466 + attribute \src "ls180.v:3891.423-3891.504" + cell $eq $eq$ls180.v:3891$367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269053,10 +267275,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:4022$466_Y + connect \Y $eq$ls180.v:3891$367_Y end - attribute \src "ls180.v:4023.339-4023.418" - cell $eq $eq$ls180.v:4023$478 + attribute \src "ls180.v:3892.339-3892.418" + cell $eq $eq$ls180.v:3892$379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269064,10 +267286,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:4023$478_Y + connect \Y $eq$ls180.v:3892$379_Y end - attribute \src "ls180.v:4023.423-4023.504" - cell $eq $eq$ls180.v:4023$479 + attribute \src "ls180.v:3892.423-3892.504" + cell $eq $eq$ls180.v:3892$380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269075,10 +267297,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:4023$479_Y + connect \Y $eq$ls180.v:3892$380_Y end - attribute \src "ls180.v:4024.339-4024.418" - cell $eq $eq$ls180.v:4024$491 + attribute \src "ls180.v:3893.339-3893.418" + cell $eq $eq$ls180.v:3893$392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269086,10 +267308,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_read connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:4024$491_Y + connect \Y $eq$ls180.v:3893$392_Y end - attribute \src "ls180.v:4024.423-4024.504" - cell $eq $eq$ls180.v:4024$492 + attribute \src "ls180.v:3893.423-3893.504" + cell $eq $eq$ls180.v:3893$393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269097,10 +267319,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_is_write connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:4024$492_Y + connect \Y $eq$ls180.v:3893$393_Y end - attribute \src "ls180.v:4053.78-4053.113" - cell $eq $eq$ls180.v:4053$501 + attribute \src "ls180.v:3922.78-3922.113" + cell $eq $eq$ls180.v:3922$402 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269108,10 +267330,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 1'0 - connect \Y $eq$ls180.v:4053$501_Y + connect \Y $eq$ls180.v:3922$402_Y end - attribute \src "ls180.v:4056.78-4056.113" - cell $eq $eq$ls180.v:4056$504 + attribute \src "ls180.v:3925.78-3925.113" + cell $eq $eq$ls180.v:3925$405 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269119,10 +267341,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 1'0 - connect \Y $eq$ls180.v:4056$504_Y + connect \Y $eq$ls180.v:3925$405_Y end - attribute \src "ls180.v:4062.78-4062.113" - cell $eq $eq$ls180.v:4062$508 + attribute \src "ls180.v:3931.78-3931.113" + cell $eq $eq$ls180.v:3931$409 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269130,10 +267352,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 1'1 - connect \Y $eq$ls180.v:4062$508_Y + connect \Y $eq$ls180.v:3931$409_Y end - attribute \src "ls180.v:4065.78-4065.113" - cell $eq $eq$ls180.v:4065$511 + attribute \src "ls180.v:3934.78-3934.113" + cell $eq $eq$ls180.v:3934$412 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269141,10 +267363,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 1'1 - connect \Y $eq$ls180.v:4065$511_Y + connect \Y $eq$ls180.v:3934$412_Y end - attribute \src "ls180.v:4071.78-4071.113" - cell $eq $eq$ls180.v:4071$515 + attribute \src "ls180.v:3940.78-3940.113" + cell $eq $eq$ls180.v:3940$416 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269152,10 +267374,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 2'10 - connect \Y $eq$ls180.v:4071$515_Y + connect \Y $eq$ls180.v:3940$416_Y end - attribute \src "ls180.v:4074.78-4074.113" - cell $eq $eq$ls180.v:4074$518 + attribute \src "ls180.v:3943.78-3943.113" + cell $eq $eq$ls180.v:3943$419 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269163,10 +267385,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 2'10 - connect \Y $eq$ls180.v:4074$518_Y + connect \Y $eq$ls180.v:3943$419_Y end - attribute \src "ls180.v:4080.78-4080.113" - cell $eq $eq$ls180.v:4080$522 + attribute \src "ls180.v:3949.78-3949.113" + cell $eq $eq$ls180.v:3949$423 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269174,10 +267396,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_grant connect \B 2'11 - connect \Y $eq$ls180.v:4080$522_Y + connect \Y $eq$ls180.v:3949$423_Y end - attribute \src "ls180.v:4083.78-4083.113" - cell $eq $eq$ls180.v:4083$525 + attribute \src "ls180.v:3952.78-3952.113" + cell $eq $eq$ls180.v:3952$426 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269185,10 +267407,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_grant connect \B 2'11 - connect \Y $eq$ls180.v:4083$525_Y + connect \Y $eq$ls180.v:3952$426_Y end - attribute \src "ls180.v:4164.42-4164.82" - cell $eq $eq$ls180.v:4164$548 + attribute \src "ls180.v:4033.42-4033.82" + cell $eq $eq$ls180.v:4033$449 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269196,10 +267418,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:4164$548_Y + connect \Y $eq$ls180.v:4033$449_Y end - attribute \src "ls180.v:4164.145-4164.178" - cell $eq $eq$ls180.v:4164$549 + attribute \src "ls180.v:4033.145-4033.178" + cell $eq $eq$ls180.v:4033$450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269207,10 +267429,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4164$549_Y + connect \Y $eq$ls180.v:4033$450_Y end - attribute \src "ls180.v:4164.220-4164.253" - cell $eq $eq$ls180.v:4164$552 + attribute \src "ls180.v:4033.220-4033.253" + cell $eq $eq$ls180.v:4033$453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269218,10 +267440,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4164$552_Y + connect \Y $eq$ls180.v:4033$453_Y end - attribute \src "ls180.v:4164.295-4164.328" - cell $eq $eq$ls180.v:4164$555 + attribute \src "ls180.v:4033.295-4033.328" + cell $eq $eq$ls180.v:4033$456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269229,10 +267451,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4164$555_Y + connect \Y $eq$ls180.v:4033$456_Y end - attribute \src "ls180.v:4169.42-4169.82" - cell $eq $eq$ls180.v:4169$564 + attribute \src "ls180.v:4038.42-4038.82" + cell $eq $eq$ls180.v:4038$465 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269240,10 +267462,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:4169$564_Y + connect \Y $eq$ls180.v:4038$465_Y end - attribute \src "ls180.v:4169.145-4169.178" - cell $eq $eq$ls180.v:4169$565 + attribute \src "ls180.v:4038.145-4038.178" + cell $eq $eq$ls180.v:4038$466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269251,10 +267473,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4169$565_Y + connect \Y $eq$ls180.v:4038$466_Y end - attribute \src "ls180.v:4169.220-4169.253" - cell $eq $eq$ls180.v:4169$568 + attribute \src "ls180.v:4038.220-4038.253" + cell $eq $eq$ls180.v:4038$469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269262,10 +267484,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4169$568_Y + connect \Y $eq$ls180.v:4038$469_Y end - attribute \src "ls180.v:4169.295-4169.328" - cell $eq $eq$ls180.v:4169$571 + attribute \src "ls180.v:4038.295-4038.328" + cell $eq $eq$ls180.v:4038$472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269273,10 +267495,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4169$571_Y + connect \Y $eq$ls180.v:4038$472_Y end - attribute \src "ls180.v:4174.42-4174.82" - cell $eq $eq$ls180.v:4174$580 + attribute \src "ls180.v:4043.42-4043.82" + cell $eq $eq$ls180.v:4043$481 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269284,10 +267506,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:4174$580_Y + connect \Y $eq$ls180.v:4043$481_Y end - attribute \src "ls180.v:4174.145-4174.178" - cell $eq $eq$ls180.v:4174$581 + attribute \src "ls180.v:4043.145-4043.178" + cell $eq $eq$ls180.v:4043$482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269295,10 +267517,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4174$581_Y + connect \Y $eq$ls180.v:4043$482_Y end - attribute \src "ls180.v:4174.220-4174.253" - cell $eq $eq$ls180.v:4174$584 + attribute \src "ls180.v:4043.220-4043.253" + cell $eq $eq$ls180.v:4043$485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269306,10 +267528,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4174$584_Y + connect \Y $eq$ls180.v:4043$485_Y end - attribute \src "ls180.v:4174.295-4174.328" - cell $eq $eq$ls180.v:4174$587 + attribute \src "ls180.v:4043.295-4043.328" + cell $eq $eq$ls180.v:4043$488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269317,10 +267539,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4174$587_Y + connect \Y $eq$ls180.v:4043$488_Y end - attribute \src "ls180.v:4179.42-4179.82" - cell $eq $eq$ls180.v:4179$596 + attribute \src "ls180.v:4048.42-4048.82" + cell $eq $eq$ls180.v:4048$497 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269328,10 +267550,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:4179$596_Y + connect \Y $eq$ls180.v:4048$497_Y end - attribute \src "ls180.v:4179.145-4179.178" - cell $eq $eq$ls180.v:4179$597 + attribute \src "ls180.v:4048.145-4048.178" + cell $eq $eq$ls180.v:4048$498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269339,10 +267561,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4179$597_Y + connect \Y $eq$ls180.v:4048$498_Y end - attribute \src "ls180.v:4179.220-4179.253" - cell $eq $eq$ls180.v:4179$600 + attribute \src "ls180.v:4048.220-4048.253" + cell $eq $eq$ls180.v:4048$501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269350,10 +267572,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4179$600_Y + connect \Y $eq$ls180.v:4048$501_Y end - attribute \src "ls180.v:4179.295-4179.328" - cell $eq $eq$ls180.v:4179$603 + attribute \src "ls180.v:4048.295-4048.328" + cell $eq $eq$ls180.v:4048$504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269361,10 +267583,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4179$603_Y + connect \Y $eq$ls180.v:4048$504_Y end - attribute \src "ls180.v:4184.44-4184.77" - cell $eq $eq$ls180.v:4184$612 + attribute \src "ls180.v:4053.44-4053.77" + cell $eq $eq$ls180.v:4053$513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269372,10 +267594,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4184$612_Y + connect \Y $eq$ls180.v:4053$513_Y end - attribute \src "ls180.v:4184.83-4184.123" - cell $eq $eq$ls180.v:4184$613 + attribute \src "ls180.v:4053.83-4053.123" + cell $eq $eq$ls180.v:4053$514 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269383,10 +267605,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:4184$613_Y + connect \Y $eq$ls180.v:4053$514_Y end - attribute \src "ls180.v:4184.186-4184.219" - cell $eq $eq$ls180.v:4184$614 + attribute \src "ls180.v:4053.186-4053.219" + cell $eq $eq$ls180.v:4053$515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269394,10 +267616,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4184$614_Y + connect \Y $eq$ls180.v:4053$515_Y end - attribute \src "ls180.v:4184.261-4184.294" - cell $eq $eq$ls180.v:4184$617 + attribute \src "ls180.v:4053.261-4053.294" + cell $eq $eq$ls180.v:4053$518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269405,10 +267627,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4184$617_Y + connect \Y $eq$ls180.v:4053$518_Y end - attribute \src "ls180.v:4184.336-4184.369" - cell $eq $eq$ls180.v:4184$620 + attribute \src "ls180.v:4053.336-4053.369" + cell $eq $eq$ls180.v:4053$521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269416,10 +267638,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4184$620_Y + connect \Y $eq$ls180.v:4053$521_Y end - attribute \src "ls180.v:4184.418-4184.451" - cell $eq $eq$ls180.v:4184$628 + attribute \src "ls180.v:4053.418-4053.451" + cell $eq $eq$ls180.v:4053$529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269427,10 +267649,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4184$628_Y + connect \Y $eq$ls180.v:4053$529_Y end - attribute \src "ls180.v:4184.457-4184.497" - cell $eq $eq$ls180.v:4184$629 + attribute \src "ls180.v:4053.457-4053.497" + cell $eq $eq$ls180.v:4053$530 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269438,10 +267660,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:4184$629_Y + connect \Y $eq$ls180.v:4053$530_Y end - attribute \src "ls180.v:4184.560-4184.593" - cell $eq $eq$ls180.v:4184$630 + attribute \src "ls180.v:4053.560-4053.593" + cell $eq $eq$ls180.v:4053$531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269449,10 +267671,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4184$630_Y + connect \Y $eq$ls180.v:4053$531_Y end - attribute \src "ls180.v:4184.635-4184.668" - cell $eq $eq$ls180.v:4184$633 + attribute \src "ls180.v:4053.635-4053.668" + cell $eq $eq$ls180.v:4053$534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269460,10 +267682,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4184$633_Y + connect \Y $eq$ls180.v:4053$534_Y end - attribute \src "ls180.v:4184.710-4184.743" - cell $eq $eq$ls180.v:4184$636 + attribute \src "ls180.v:4053.710-4053.743" + cell $eq $eq$ls180.v:4053$537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269471,10 +267693,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4184$636_Y + connect \Y $eq$ls180.v:4053$537_Y end - attribute \src "ls180.v:4184.792-4184.825" - cell $eq $eq$ls180.v:4184$644 + attribute \src "ls180.v:4053.792-4053.825" + cell $eq $eq$ls180.v:4053$545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269482,10 +267704,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4184$644_Y + connect \Y $eq$ls180.v:4053$545_Y end - attribute \src "ls180.v:4184.831-4184.871" - cell $eq $eq$ls180.v:4184$645 + attribute \src "ls180.v:4053.831-4053.871" + cell $eq $eq$ls180.v:4053$546 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269493,10 +267715,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:4184$645_Y + connect \Y $eq$ls180.v:4053$546_Y end - attribute \src "ls180.v:4184.934-4184.967" - cell $eq $eq$ls180.v:4184$646 + attribute \src "ls180.v:4053.934-4053.967" + cell $eq $eq$ls180.v:4053$547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269504,10 +267726,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4184$646_Y + connect \Y $eq$ls180.v:4053$547_Y end - attribute \src "ls180.v:4184.1009-4184.1042" - cell $eq $eq$ls180.v:4184$649 + attribute \src "ls180.v:4053.1009-4053.1042" + cell $eq $eq$ls180.v:4053$550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269515,10 +267737,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4184$649_Y + connect \Y $eq$ls180.v:4053$550_Y end - attribute \src "ls180.v:4184.1084-4184.1117" - cell $eq $eq$ls180.v:4184$652 + attribute \src "ls180.v:4053.1084-4053.1117" + cell $eq $eq$ls180.v:4053$553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269526,10 +267748,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4184$652_Y + connect \Y $eq$ls180.v:4053$553_Y end - attribute \src "ls180.v:4184.1166-4184.1199" - cell $eq $eq$ls180.v:4184$660 + attribute \src "ls180.v:4053.1166-4053.1199" + cell $eq $eq$ls180.v:4053$561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269537,10 +267759,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:4184$660_Y + connect \Y $eq$ls180.v:4053$561_Y end - attribute \src "ls180.v:4184.1205-4184.1245" - cell $eq $eq$ls180.v:4184$661 + attribute \src "ls180.v:4053.1205-4053.1245" + cell $eq $eq$ls180.v:4053$562 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269548,10 +267770,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:4184$661_Y + connect \Y $eq$ls180.v:4053$562_Y end - attribute \src "ls180.v:4184.1308-4184.1341" - cell $eq $eq$ls180.v:4184$662 + attribute \src "ls180.v:4053.1308-4053.1341" + cell $eq $eq$ls180.v:4053$563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269559,10 +267781,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:4184$662_Y + connect \Y $eq$ls180.v:4053$563_Y end - attribute \src "ls180.v:4184.1383-4184.1416" - cell $eq $eq$ls180.v:4184$665 + attribute \src "ls180.v:4053.1383-4053.1416" + cell $eq $eq$ls180.v:4053$566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269570,10 +267792,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:4184$665_Y + connect \Y $eq$ls180.v:4053$566_Y end - attribute \src "ls180.v:4184.1458-4184.1491" - cell $eq $eq$ls180.v:4184$668 + attribute \src "ls180.v:4053.1458-4053.1491" + cell $eq $eq$ls180.v:4053$569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269581,10 +267803,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:4184$668_Y + connect \Y $eq$ls180.v:4053$569_Y end - attribute \src "ls180.v:4243.29-4243.57" - cell $eq $eq$ls180.v:4243$681 + attribute \src "ls180.v:4112.29-4112.57" + cell $eq $eq$ls180.v:4112$582 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269592,10 +267814,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_sel connect \B 1'0 - connect \Y $eq$ls180.v:4243$681_Y + connect \Y $eq$ls180.v:4112$582_Y end - attribute \src "ls180.v:4250.11-4250.41" - cell $eq $eq$ls180.v:4250$686 + attribute \src "ls180.v:4119.11-4119.41" + cell $eq $eq$ls180.v:4119$587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269603,76 +267825,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_converter_counter connect \B 1'1 - connect \Y $eq$ls180.v:4250$686_Y + connect \Y $eq$ls180.v:4119$587_Y end - attribute \src "ls180.v:4418.37-4418.111" - cell $eq $eq$ls180.v:4418$753 + attribute \src "ls180.v:4287.37-4287.111" + cell $eq $eq$ls180.v:4287$654 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4418$752_Y - connect \Y $eq$ls180.v:4418$753_Y + connect \B $sub$ls180.v:4287$653_Y + connect \Y $eq$ls180.v:4287$654_Y end - attribute \src "ls180.v:4419.37-4419.105" - cell $eq $eq$ls180.v:4419$755 + attribute \src "ls180.v:4288.37-4288.105" + cell $eq $eq$ls180.v:4288$656 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4419$754_Y - connect \Y $eq$ls180.v:4419$755_Y + connect \B $sub$ls180.v:4288$655_Y + connect \Y $eq$ls180.v:4288$656_Y end - attribute \src "ls180.v:4446.10-4446.67" - cell $eq $eq$ls180.v:4446$759 + attribute \src "ls180.v:4315.10-4315.67" + cell $eq $eq$ls180.v:4315$660 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_spimaster27_count - connect \B $sub$ls180.v:4446$758_Y - connect \Y $eq$ls180.v:4446$759_Y + connect \B $sub$ls180.v:4315$659_Y + connect \Y $eq$ls180.v:4315$660_Y end - attribute \src "ls180.v:4476.35-4476.108" - cell $eq $eq$ls180.v:4476$761 + attribute \src "ls180.v:4345.35-4345.108" + cell $eq $eq$ls180.v:4345$662 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4476$760_Y - connect \Y $eq$ls180.v:4476$761_Y + connect \B $sub$ls180.v:4345$661_Y + connect \Y $eq$ls180.v:4345$662_Y end - attribute \src "ls180.v:4477.35-4477.102" - cell $eq $eq$ls180.v:4477$763 + attribute \src "ls180.v:4346.35-4346.102" + cell $eq $eq$ls180.v:4346$664 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 parameter \B_WIDTH 16 parameter \Y_WIDTH 1 connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4477$762_Y - connect \Y $eq$ls180.v:4477$763_Y + connect \B $sub$ls180.v:4346$663_Y + connect \Y $eq$ls180.v:4346$664_Y end - attribute \src "ls180.v:4505.10-4505.65" - cell $eq $eq$ls180.v:4505$767 + attribute \src "ls180.v:4374.10-4374.65" + cell $eq $eq$ls180.v:4374$668 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_spisdcard_count - connect \B $sub$ls180.v:4505$766_Y - connect \Y $eq$ls180.v:4505$767_Y + connect \B $sub$ls180.v:4374$667_Y + connect \Y $eq$ls180.v:4374$668_Y end - attribute \src "ls180.v:4609.10-4609.40" - cell $eq $eq$ls180.v:4609$794 + attribute \src "ls180.v:4478.10-4478.40" + cell $eq $eq$ls180.v:4478$695 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -269680,10 +267902,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_count connect \B 7'1001111 - connect \Y $eq$ls180.v:4609$794_Y + connect \Y $eq$ls180.v:4478$695_Y end - attribute \src "ls180.v:4666.10-4666.39" - cell $eq $eq$ls180.v:4666$797 + attribute \src "ls180.v:4535.10-4535.39" + cell $eq $eq$ls180.v:4535$698 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -269691,10 +267913,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_count connect \B 3'111 - connect \Y $eq$ls180.v:4666$797_Y + connect \Y $eq$ls180.v:4535$698_Y end - attribute \src "ls180.v:4683.10-4683.39" - cell $eq $eq$ls180.v:4683$799 + attribute \src "ls180.v:4552.10-4552.39" + cell $eq $eq$ls180.v:4552$700 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -269702,10 +267924,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdw_count connect \B 3'111 - connect \Y $eq$ls180.v:4683$799_Y + connect \Y $eq$ls180.v:4552$700_Y end - attribute \src "ls180.v:4711.38-4711.88" - cell $eq $eq$ls180.v:4711$801 + attribute \src "ls180.v:4580.38-4580.88" + cell $eq $eq$ls180.v:4580$702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269713,10 +267935,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i connect \B 1'0 - connect \Y $eq$ls180.v:4711$801_Y + connect \Y $eq$ls180.v:4580$702_Y end - attribute \src "ls180.v:4761.9-4761.40" - cell $eq $eq$ls180.v:4761$811 + attribute \src "ls180.v:4630.9-4630.40" + cell $eq $eq$ls180.v:4630$712 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -269724,21 +267946,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4761$811_Y + connect \Y $eq$ls180.v:4630$712_Y end - attribute \src "ls180.v:4770.36-4770.105" - cell $eq $eq$ls180.v:4770$813 + attribute \src "ls180.v:4639.36-4639.105" + cell $eq $eq$ls180.v:4639$714 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_count - connect \B $sub$ls180.v:4770$812_Y - connect \Y $eq$ls180.v:4770$813_Y + connect \B $sub$ls180.v:4639$713_Y + connect \Y $eq$ls180.v:4639$714_Y end - attribute \src "ls180.v:4789.9-4789.40" - cell $eq $eq$ls180.v:4789$817 + attribute \src "ls180.v:4658.9-4658.40" + cell $eq $eq$ls180.v:4658$718 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -269746,10 +267968,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_timeout connect \B 1'0 - connect \Y $eq$ls180.v:4789$817_Y + connect \Y $eq$ls180.v:4658$718_Y end - attribute \src "ls180.v:4801.10-4801.39" - cell $eq $eq$ls180.v:4801$819 + attribute \src "ls180.v:4670.10-4670.39" + cell $eq $eq$ls180.v:4670$720 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -269757,10 +267979,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_count connect \B 3'111 - connect \Y $eq$ls180.v:4801$819_Y + connect \Y $eq$ls180.v:4670$720_Y end - attribute \src "ls180.v:4838.39-4838.94" - cell $eq $eq$ls180.v:4838$823 + attribute \src "ls180.v:4707.39-4707.94" + cell $eq $eq$ls180.v:4707$724 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -269768,10 +267990,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] connect \B 1'0 - connect \Y $eq$ls180.v:4838$823_Y + connect \Y $eq$ls180.v:4707$724_Y end - attribute \src "ls180.v:4875.32-4875.89" - cell $eq $eq$ls180.v:4875$832 + attribute \src "ls180.v:4744.32-4744.89" + cell $eq $eq$ls180.v:4744$733 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -269779,10 +268001,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 connect \B 3'101 - connect \Y $eq$ls180.v:4875$832_Y + connect \Y $eq$ls180.v:4744$733_Y end - attribute \src "ls180.v:4923.10-4923.40" - cell $eq $eq$ls180.v:4923$836 + attribute \src "ls180.v:4792.10-4792.40" + cell $eq $eq$ls180.v:4792$737 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -269790,10 +268012,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_count connect \B 1'1 - connect \Y $eq$ls180.v:4923$836_Y + connect \Y $eq$ls180.v:4792$737_Y end - attribute \src "ls180.v:4972.40-4972.98" - cell $eq $eq$ls180.v:4972$838 + attribute \src "ls180.v:4841.40-4841.98" + cell $eq $eq$ls180.v:4841$739 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -269801,10 +268023,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_pads_in_payload_data_i connect \B 1'0 - connect \Y $eq$ls180.v:4972$838_Y + connect \Y $eq$ls180.v:4841$739_Y end - attribute \src "ls180.v:5023.9-5023.41" - cell $eq $eq$ls180.v:5023$848 + attribute \src "ls180.v:4892.9-4892.41" + cell $eq $eq$ls180.v:4892$749 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -269812,21 +268034,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_timeout connect \B 1'0 - connect \Y $eq$ls180.v:5023$848_Y + connect \Y $eq$ls180.v:4892$749_Y end - attribute \src "ls180.v:5032.37-5032.123" - cell $eq $eq$ls180.v:5032$851 + attribute \src "ls180.v:4901.37-4901.123" + cell $eq $eq$ls180.v:4901$752 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 10 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_count - connect \B $sub$ls180.v:5032$850_Y - connect \Y $eq$ls180.v:5032$851_Y + connect \B $sub$ls180.v:4901$751_Y + connect \Y $eq$ls180.v:4901$752_Y end - attribute \src "ls180.v:5055.9-5055.41" - cell $eq $eq$ls180.v:5055$854 + attribute \src "ls180.v:4924.9-4924.41" + cell $eq $eq$ls180.v:4924$755 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -269834,10 +268056,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_timeout connect \B 1'0 - connect \Y $eq$ls180.v:5055$854_Y + connect \Y $eq$ls180.v:4924$755_Y end - attribute \src "ls180.v:5065.10-5065.41" - cell $eq $eq$ls180.v:5065$856 + attribute \src "ls180.v:4934.10-4934.41" + cell $eq $eq$ls180.v:4934$757 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -269845,10 +268067,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_count connect \B 6'100111 - connect \Y $eq$ls180.v:5065$856_Y + connect \Y $eq$ls180.v:4934$757_Y end - attribute \src "ls180.v:5234.9-5234.47" - cell $eq $eq$ls180.v:5234$1038 + attribute \src "ls180.v:5103.9-5103.47" + cell $eq $eq$ls180.v:5103$939 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -269856,10 +268078,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5234$1038_Y + connect \Y $eq$ls180.v:5103$939_Y end - attribute \src "ls180.v:5264.10-5264.48" - cell $eq $eq$ls180.v:5264$1039 + attribute \src "ls180.v:5133.10-5133.48" + cell $eq $eq$ls180.v:5133$940 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -269867,10 +268089,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5264$1039_Y + connect \Y $eq$ls180.v:5133$940_Y end - attribute \src "ls180.v:5295.10-5295.78" - cell $eq $eq$ls180.v:5295$1044 + attribute \src "ls180.v:5164.10-5164.78" + cell $eq $eq$ls180.v:5164$945 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -269878,10 +268100,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo0 connect \B \main_sdcore_crc16_checker_crctmp0 - connect \Y $eq$ls180.v:5295$1044_Y + connect \Y $eq$ls180.v:5164$945_Y end - attribute \src "ls180.v:5295.83-5295.151" - cell $eq $eq$ls180.v:5295$1045 + attribute \src "ls180.v:5164.83-5164.151" + cell $eq $eq$ls180.v:5164$946 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -269889,10 +268111,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo1 connect \B \main_sdcore_crc16_checker_crctmp1 - connect \Y $eq$ls180.v:5295$1045_Y + connect \Y $eq$ls180.v:5164$946_Y end - attribute \src "ls180.v:5295.157-5295.225" - cell $eq $eq$ls180.v:5295$1047 + attribute \src "ls180.v:5164.157-5164.225" + cell $eq $eq$ls180.v:5164$948 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -269900,10 +268122,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo2 connect \B \main_sdcore_crc16_checker_crctmp2 - connect \Y $eq$ls180.v:5295$1047_Y + connect \Y $eq$ls180.v:5164$948_Y end - attribute \src "ls180.v:5295.231-5295.299" - cell $eq $eq$ls180.v:5295$1049 + attribute \src "ls180.v:5164.231-5164.299" + cell $eq $eq$ls180.v:5164$950 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -269911,10 +268133,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_fifo3 connect \B \main_sdcore_crc16_checker_crctmp3 - connect \Y $eq$ls180.v:5295$1049_Y + connect \Y $eq$ls180.v:5164$950_Y end - attribute \src "ls180.v:5303.7-5303.44" - cell $eq $eq$ls180.v:5303$1053 + attribute \src "ls180.v:5172.7-5172.44" + cell $eq $eq$ls180.v:5172$954 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -269922,10 +268144,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5303$1053_Y + connect \Y $eq$ls180.v:5172$954_Y end - attribute \src "ls180.v:5313.7-5313.44" - cell $eq $eq$ls180.v:5313$1056 + attribute \src "ls180.v:5182.7-5182.44" + cell $eq $eq$ls180.v:5182$957 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -269933,10 +268155,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5313$1056_Y + connect \Y $eq$ls180.v:5182$957_Y end - attribute \src "ls180.v:5323.7-5323.44" - cell $eq $eq$ls180.v:5323$1059 + attribute \src "ls180.v:5192.7-5192.44" + cell $eq $eq$ls180.v:5192$960 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -269944,10 +268166,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5323$1059_Y + connect \Y $eq$ls180.v:5192$960_Y end - attribute \src "ls180.v:5333.7-5333.44" - cell $eq $eq$ls180.v:5333$1062 + attribute \src "ls180.v:5202.7-5202.44" + cell $eq $eq$ls180.v:5202$963 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -269955,10 +268177,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $eq$ls180.v:5333$1062_Y + connect \Y $eq$ls180.v:5202$963_Y end - attribute \src "ls180.v:5457.36-5457.64" - cell $eq $eq$ls180.v:5457$1113 + attribute \src "ls180.v:5326.36-5326.64" + cell $eq $eq$ls180.v:5326$1014 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269966,10 +268188,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 1'0 - connect \Y $eq$ls180.v:5457$1113_Y + connect \Y $eq$ls180.v:5326$1014_Y end - attribute \src "ls180.v:5463.10-5463.39" - cell $eq $eq$ls180.v:5463$1116 + attribute \src "ls180.v:5332.10-5332.39" + cell $eq $eq$ls180.v:5332$1017 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -269977,10 +268199,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_count connect \B 3'101 - connect \Y $eq$ls180.v:5463$1116_Y + connect \Y $eq$ls180.v:5332$1017_Y end - attribute \src "ls180.v:5464.11-5464.39" - cell $eq $eq$ls180.v:5464$1117 + attribute \src "ls180.v:5333.11-5333.39" + cell $eq $eq$ls180.v:5333$1018 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269988,10 +268210,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 1'0 - connect \Y $eq$ls180.v:5464$1117_Y + connect \Y $eq$ls180.v:5333$1018_Y end - attribute \src "ls180.v:5476.34-5476.63" - cell $eq $eq$ls180.v:5476$1118 + attribute \src "ls180.v:5345.34-5345.63" + cell $eq $eq$ls180.v:5345$1019 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -269999,10 +268221,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 1'0 - connect \Y $eq$ls180.v:5476$1118_Y + connect \Y $eq$ls180.v:5345$1019_Y end - attribute \src "ls180.v:5477.9-5477.37" - cell $eq $eq$ls180.v:5477$1119 + attribute \src "ls180.v:5346.9-5346.37" + cell $eq $eq$ls180.v:5346$1020 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -270010,10 +268232,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_cmd_type connect \B 2'10 - connect \Y $eq$ls180.v:5477$1119_Y + connect \Y $eq$ls180.v:5346$1020_Y end - attribute \src "ls180.v:5484.10-5484.55" - cell $eq $eq$ls180.v:5484$1120 + attribute \src "ls180.v:5353.10-5353.55" + cell $eq $eq$ls180.v:5353$1021 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270021,10 +268243,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_source_payload_status connect \B 1'1 - connect \Y $eq$ls180.v:5484$1120_Y + connect \Y $eq$ls180.v:5353$1021_Y end - attribute \src "ls180.v:5490.12-5490.41" - cell $eq $eq$ls180.v:5490$1121 + attribute \src "ls180.v:5359.12-5359.41" + cell $eq $eq$ls180.v:5359$1022 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -270032,10 +268254,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 2'10 - connect \Y $eq$ls180.v:5490$1121_Y + connect \Y $eq$ls180.v:5359$1022_Y end - attribute \src "ls180.v:5493.13-5493.42" - cell $eq $eq$ls180.v:5493$1122 + attribute \src "ls180.v:5362.13-5362.42" + cell $eq $eq$ls180.v:5362$1023 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -270043,32 +268265,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_type connect \B 1'1 - connect \Y $eq$ls180.v:5493$1122_Y + connect \Y $eq$ls180.v:5362$1023_Y end - attribute \src "ls180.v:5515.10-5515.76" - cell $eq $eq$ls180.v:5515$1127 + attribute \src "ls180.v:5384.10-5384.76" + cell $eq $eq$ls180.v:5384$1028 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5515$1126_Y - connect \Y $eq$ls180.v:5515$1127_Y + connect \B $sub$ls180.v:5384$1027_Y + connect \Y $eq$ls180.v:5384$1028_Y end - attribute \src "ls180.v:5530.35-5530.101" - cell $eq $eq$ls180.v:5530$1130 + attribute \src "ls180.v:5399.35-5399.101" + cell $eq $eq$ls180.v:5399$1031 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5530$1129_Y - connect \Y $eq$ls180.v:5530$1130_Y + connect \B $sub$ls180.v:5399$1030_Y + connect \Y $eq$ls180.v:5399$1031_Y end - attribute \src "ls180.v:5532.10-5532.56" - cell $eq $eq$ls180.v:5532$1131 + attribute \src "ls180.v:5401.10-5401.56" + cell $eq $eq$ls180.v:5401$1032 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270076,21 +268298,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 1'0 - connect \Y $eq$ls180.v:5532$1131_Y + connect \Y $eq$ls180.v:5401$1032_Y end - attribute \src "ls180.v:5541.12-5541.78" - cell $eq $eq$ls180.v:5541$1135 + attribute \src "ls180.v:5410.12-5410.78" + cell $eq $eq$ls180.v:5410$1036 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5541$1134_Y - connect \Y $eq$ls180.v:5541$1135_Y + connect \B $sub$ls180.v:5410$1035_Y + connect \Y $eq$ls180.v:5410$1036_Y end - attribute \src "ls180.v:5548.11-5548.57" - cell $eq $eq$ls180.v:5548$1136 + attribute \src "ls180.v:5417.11-5417.57" + cell $eq $eq$ls180.v:5417$1037 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270098,32 +268320,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 1'1 - connect \Y $eq$ls180.v:5548$1136_Y + connect \Y $eq$ls180.v:5417$1037_Y end - attribute \src "ls180.v:5665.10-5665.105" - cell $eq $eq$ls180.v:5665$1153 + attribute \src "ls180.v:5534.10-5534.105" + cell $eq $eq$ls180.v:5534$1054 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_offset - connect \B $sub$ls180.v:5665$1152_Y - connect \Y $eq$ls180.v:5665$1153_Y + connect \B $sub$ls180.v:5534$1053_Y + connect \Y $eq$ls180.v:5534$1054_Y end - attribute \src "ls180.v:5755.39-5755.106" - cell $eq $eq$ls180.v:5755$1159 + attribute \src "ls180.v:5624.39-5624.106" + cell $eq $eq$ls180.v:5624$1060 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_dma_offset - connect \B $sub$ls180.v:5755$1158_Y - connect \Y $eq$ls180.v:5755$1159_Y + connect \B $sub$ls180.v:5624$1059_Y + connect \Y $eq$ls180.v:5624$1060_Y end - attribute \src "ls180.v:5785.44-5785.82" - cell $eq $eq$ls180.v:5785$1162 + attribute \src "ls180.v:5654.44-5654.82" + cell $eq $eq$ls180.v:5654$1063 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270131,10 +268353,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_mux connect \B 1'0 - connect \Y $eq$ls180.v:5785$1162_Y + connect \Y $eq$ls180.v:5654$1063_Y end - attribute \src "ls180.v:5786.43-5786.81" - cell $eq $eq$ls180.v:5786$1163 + attribute \src "ls180.v:5655.43-5655.81" + cell $eq $eq$ls180.v:5655$1064 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270142,10 +268364,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_converter_mux connect \B 3'111 - connect \Y $eq$ls180.v:5786$1163_Y + connect \Y $eq$ls180.v:5655$1064_Y end - attribute \src "ls180.v:5898.68-5898.89" - cell $eq $eq$ls180.v:5898$1179 + attribute \src "ls180.v:5767.68-5767.89" + cell $eq $eq$ls180.v:5767$1080 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270153,10 +268375,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'0 - connect \Y $eq$ls180.v:5898$1179_Y + connect \Y $eq$ls180.v:5767$1080_Y end - attribute \src "ls180.v:5899.68-5899.89" - cell $eq $eq$ls180.v:5899$1181 + attribute \src "ls180.v:5768.68-5768.89" + cell $eq $eq$ls180.v:5768$1082 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270164,10 +268386,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'1 - connect \Y $eq$ls180.v:5899$1181_Y + connect \Y $eq$ls180.v:5768$1082_Y end - attribute \src "ls180.v:5900.71-5900.92" - cell $eq $eq$ls180.v:5900$1183 + attribute \src "ls180.v:5769.71-5769.92" + cell $eq $eq$ls180.v:5769$1084 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270175,10 +268397,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'10 - connect \Y $eq$ls180.v:5900$1183_Y + connect \Y $eq$ls180.v:5769$1084_Y end - attribute \src "ls180.v:5901.57-5901.78" - cell $eq $eq$ls180.v:5901$1185 + attribute \src "ls180.v:5770.57-5770.78" + cell $eq $eq$ls180.v:5770$1086 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270186,10 +268408,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'11 - connect \Y $eq$ls180.v:5901$1185_Y + connect \Y $eq$ls180.v:5770$1086_Y end - attribute \src "ls180.v:5902.57-5902.78" - cell $eq $eq$ls180.v:5902$1187 + attribute \src "ls180.v:5771.57-5771.78" + cell $eq $eq$ls180.v:5771$1088 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270197,10 +268419,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 3'100 - connect \Y $eq$ls180.v:5902$1187_Y + connect \Y $eq$ls180.v:5771$1088_Y end - attribute \src "ls180.v:5903.68-5903.89" - cell $eq $eq$ls180.v:5903$1189 + attribute \src "ls180.v:5772.68-5772.89" + cell $eq $eq$ls180.v:5772$1090 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270208,10 +268430,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'0 - connect \Y $eq$ls180.v:5903$1189_Y + connect \Y $eq$ls180.v:5772$1090_Y end - attribute \src "ls180.v:5904.68-5904.89" - cell $eq $eq$ls180.v:5904$1191 + attribute \src "ls180.v:5773.68-5773.89" + cell $eq $eq$ls180.v:5773$1092 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270219,10 +268441,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 1'1 - connect \Y $eq$ls180.v:5904$1191_Y + connect \Y $eq$ls180.v:5773$1092_Y end - attribute \src "ls180.v:5905.71-5905.92" - cell $eq $eq$ls180.v:5905$1193 + attribute \src "ls180.v:5774.71-5774.92" + cell $eq $eq$ls180.v:5774$1094 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270230,10 +268452,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'10 - connect \Y $eq$ls180.v:5905$1193_Y + connect \Y $eq$ls180.v:5774$1094_Y end - attribute \src "ls180.v:5906.57-5906.78" - cell $eq $eq$ls180.v:5906$1195 + attribute \src "ls180.v:5775.57-5775.78" + cell $eq $eq$ls180.v:5775$1096 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270241,10 +268463,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 2'11 - connect \Y $eq$ls180.v:5906$1195_Y + connect \Y $eq$ls180.v:5775$1096_Y end - attribute \src "ls180.v:5907.57-5907.78" - cell $eq $eq$ls180.v:5907$1197 + attribute \src "ls180.v:5776.57-5776.78" + cell $eq $eq$ls180.v:5776$1098 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270252,65 +268474,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_grant connect \B 3'100 - connect \Y $eq$ls180.v:5907$1197_Y + connect \Y $eq$ls180.v:5776$1098_Y end - attribute \src "ls180.v:5911.27-5911.59" - cell $eq $eq$ls180.v:5911$1200 + attribute \src "ls180.v:5780.27-5780.59" + cell $eq $eq$ls180.v:5780$1101 parameter \A_SIGNED 0 - parameter \A_WIDTH 24 + parameter \A_WIDTH 26 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:6] + connect \A \builder_shared_adr [29:4] connect \B 1'0 - connect \Y $eq$ls180.v:5911$1200_Y - end - attribute \src "ls180.v:5912.27-5912.59" - cell $eq $eq$ls180.v:5912$1201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:6] - connect \B 1'1 - connect \Y $eq$ls180.v:5912$1201_Y - end - attribute \src "ls180.v:5913.27-5913.59" - cell $eq $eq$ls180.v:5913$1202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:6] - connect \B 2'10 - connect \Y $eq$ls180.v:5913$1202_Y + connect \Y $eq$ls180.v:5780$1101_Y end - attribute \src "ls180.v:5914.27-5914.59" - cell $eq $eq$ls180.v:5914$1203 + attribute \src "ls180.v:5781.27-5781.60" + cell $eq $eq$ls180.v:5781$1102 parameter \A_SIGNED 0 - parameter \A_WIDTH 24 + parameter \A_WIDTH 26 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:6] - connect \B 2'11 - connect \Y $eq$ls180.v:5914$1203_Y - end - attribute \src "ls180.v:5915.27-5915.59" - cell $eq $eq$ls180.v:5915$1204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:6] - connect \B 3'100 - connect \Y $eq$ls180.v:5915$1204_Y + connect \A \builder_shared_adr [29:4] + connect \B 4'1110 + connect \Y $eq$ls180.v:5781$1102_Y end - attribute \src "ls180.v:5916.27-5916.68" - cell $eq $eq$ls180.v:5916$1205 + attribute \src "ls180.v:5782.27-5782.68" + cell $eq $eq$ls180.v:5782$1103 parameter \A_SIGNED 0 parameter \A_WIDTH 28 parameter \B_SIGNED 0 @@ -270318,10 +268507,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:2] connect \B 27'110000000000000100000000000 - connect \Y $eq$ls180.v:5916$1205_Y + connect \Y $eq$ls180.v:5782$1103_Y end - attribute \src "ls180.v:5917.27-5917.65" - cell $eq $eq$ls180.v:5917$1206 + attribute \src "ls180.v:5783.27-5783.65" + cell $eq $eq$ls180.v:5783$1104 parameter \A_SIGNED 0 parameter \A_WIDTH 21 parameter \B_SIGNED 0 @@ -270329,54 +268518,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:9] connect \B 20'11000000000000010001 - connect \Y $eq$ls180.v:5917$1206_Y - end - attribute \src "ls180.v:5918.27-5918.59" - cell $eq $eq$ls180.v:5918$1207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 21 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:9] - connect \B 1'1 - connect \Y $eq$ls180.v:5918$1207_Y - end - attribute \src "ls180.v:5919.27-5919.59" - cell $eq $eq$ls180.v:5919$1208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 21 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:9] - connect \B 2'10 - connect \Y $eq$ls180.v:5919$1208_Y - end - attribute \src "ls180.v:5920.27-5920.59" - cell $eq $eq$ls180.v:5920$1209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 21 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:9] - connect \B 2'11 - connect \Y $eq$ls180.v:5920$1209_Y - end - attribute \src "ls180.v:5921.28-5921.60" - cell $eq $eq$ls180.v:5921$1210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 21 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:9] - connect \B 3'100 - connect \Y $eq$ls180.v:5921$1210_Y + connect \Y $eq$ls180.v:5783$1104_Y end - attribute \src "ls180.v:5922.28-5922.62" - cell $eq $eq$ls180.v:5922$1211 + attribute \src "ls180.v:5784.27-5784.61" + cell $eq $eq$ls180.v:5784$1105 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -270384,10 +268529,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:22] connect \B 7'1001000 - connect \Y $eq$ls180.v:5922$1211_Y + connect \Y $eq$ls180.v:5784$1105_Y end - attribute \src "ls180.v:5923.28-5923.66" - cell $eq $eq$ls180.v:5923$1212 + attribute \src "ls180.v:5785.27-5785.65" + cell $eq $eq$ls180.v:5785$1106 parameter \A_SIGNED 0 parameter \A_WIDTH 17 parameter \B_SIGNED 0 @@ -270395,10 +268540,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_shared_adr [29:13] connect \B 16'1100000000000000 - connect \Y $eq$ls180.v:5923$1212_Y + connect \Y $eq$ls180.v:5785$1106_Y end - attribute \src "ls180.v:6043.24-6043.45" - cell $eq $eq$ls180.v:6043$1279 + attribute \src "ls180.v:5849.24-5849.45" + cell $eq $eq$ls180.v:5849$1138 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -270406,10 +268551,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_count connect \B 1'0 - connect \Y $eq$ls180.v:6043$1279_Y + connect \Y $eq$ls180.v:5849$1138_Y end - attribute \src "ls180.v:6044.32-6044.77" - cell $eq $eq$ls180.v:6044$1280 + attribute \src "ls180.v:5850.32-5850.77" + cell $eq $eq$ls180.v:5850$1139 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -270417,10 +268562,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [13:8] connect \B 1'0 - connect \Y $eq$ls180.v:6044$1280_Y + connect \Y $eq$ls180.v:5850$1139_Y end - attribute \src "ls180.v:6046.97-6046.141" - cell $eq $eq$ls180.v:6046$1282 + attribute \src "ls180.v:5852.97-5852.141" + cell $eq $eq$ls180.v:5852$1141 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270428,10 +268573,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6046$1282_Y + connect \Y $eq$ls180.v:5852$1141_Y end - attribute \src "ls180.v:6047.100-6047.144" - cell $eq $eq$ls180.v:6047$1286 + attribute \src "ls180.v:5853.100-5853.144" + cell $eq $eq$ls180.v:5853$1145 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270439,10 +268584,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6047$1286_Y + connect \Y $eq$ls180.v:5853$1145_Y end - attribute \src "ls180.v:6049.99-6049.143" - cell $eq $eq$ls180.v:6049$1289 + attribute \src "ls180.v:5855.99-5855.143" + cell $eq $eq$ls180.v:5855$1148 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270450,10 +268595,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6049$1289_Y + connect \Y $eq$ls180.v:5855$1148_Y end - attribute \src "ls180.v:6050.102-6050.146" - cell $eq $eq$ls180.v:6050$1293 + attribute \src "ls180.v:5856.102-5856.146" + cell $eq $eq$ls180.v:5856$1152 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270461,10 +268606,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6050$1293_Y + connect \Y $eq$ls180.v:5856$1152_Y end - attribute \src "ls180.v:6052.99-6052.143" - cell $eq $eq$ls180.v:6052$1296 + attribute \src "ls180.v:5858.99-5858.143" + cell $eq $eq$ls180.v:5858$1155 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270472,10 +268617,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6052$1296_Y + connect \Y $eq$ls180.v:5858$1155_Y end - attribute \src "ls180.v:6053.102-6053.146" - cell $eq $eq$ls180.v:6053$1300 + attribute \src "ls180.v:5859.102-5859.146" + cell $eq $eq$ls180.v:5859$1159 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270483,10 +268628,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6053$1300_Y + connect \Y $eq$ls180.v:5859$1159_Y end - attribute \src "ls180.v:6055.99-6055.143" - cell $eq $eq$ls180.v:6055$1303 + attribute \src "ls180.v:5861.99-5861.143" + cell $eq $eq$ls180.v:5861$1162 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270494,10 +268639,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6055$1303_Y + connect \Y $eq$ls180.v:5861$1162_Y end - attribute \src "ls180.v:6056.102-6056.146" - cell $eq $eq$ls180.v:6056$1307 + attribute \src "ls180.v:5862.102-5862.146" + cell $eq $eq$ls180.v:5862$1166 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270505,10 +268650,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6056$1307_Y + connect \Y $eq$ls180.v:5862$1166_Y end - attribute \src "ls180.v:6058.99-6058.143" - cell $eq $eq$ls180.v:6058$1310 + attribute \src "ls180.v:5864.99-5864.143" + cell $eq $eq$ls180.v:5864$1169 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270516,10 +268661,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6058$1310_Y + connect \Y $eq$ls180.v:5864$1169_Y end - attribute \src "ls180.v:6059.102-6059.146" - cell $eq $eq$ls180.v:6059$1314 + attribute \src "ls180.v:5865.102-5865.146" + cell $eq $eq$ls180.v:5865$1173 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270527,10 +268672,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6059$1314_Y + connect \Y $eq$ls180.v:5865$1173_Y end - attribute \src "ls180.v:6061.102-6061.146" - cell $eq $eq$ls180.v:6061$1317 + attribute \src "ls180.v:5867.102-5867.146" + cell $eq $eq$ls180.v:5867$1176 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270538,10 +268683,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6061$1317_Y + connect \Y $eq$ls180.v:5867$1176_Y end - attribute \src "ls180.v:6062.105-6062.149" - cell $eq $eq$ls180.v:6062$1321 + attribute \src "ls180.v:5868.105-5868.149" + cell $eq $eq$ls180.v:5868$1180 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270549,10 +268694,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6062$1321_Y + connect \Y $eq$ls180.v:5868$1180_Y end - attribute \src "ls180.v:6064.102-6064.146" - cell $eq $eq$ls180.v:6064$1324 + attribute \src "ls180.v:5870.102-5870.146" + cell $eq $eq$ls180.v:5870$1183 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270560,10 +268705,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6064$1324_Y + connect \Y $eq$ls180.v:5870$1183_Y end - attribute \src "ls180.v:6065.105-6065.149" - cell $eq $eq$ls180.v:6065$1328 + attribute \src "ls180.v:5871.105-5871.149" + cell $eq $eq$ls180.v:5871$1187 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270571,10 +268716,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6065$1328_Y + connect \Y $eq$ls180.v:5871$1187_Y end - attribute \src "ls180.v:6067.102-6067.146" - cell $eq $eq$ls180.v:6067$1331 + attribute \src "ls180.v:5873.102-5873.146" + cell $eq $eq$ls180.v:5873$1190 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270582,10 +268727,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6067$1331_Y + connect \Y $eq$ls180.v:5873$1190_Y end - attribute \src "ls180.v:6068.105-6068.149" - cell $eq $eq$ls180.v:6068$1335 + attribute \src "ls180.v:5874.105-5874.149" + cell $eq $eq$ls180.v:5874$1194 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270593,10 +268738,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6068$1335_Y + connect \Y $eq$ls180.v:5874$1194_Y end - attribute \src "ls180.v:6070.102-6070.146" - cell $eq $eq$ls180.v:6070$1338 + attribute \src "ls180.v:5876.102-5876.146" + cell $eq $eq$ls180.v:5876$1197 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270604,10 +268749,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6070$1338_Y + connect \Y $eq$ls180.v:5876$1197_Y end - attribute \src "ls180.v:6071.105-6071.149" - cell $eq $eq$ls180.v:6071$1342 + attribute \src "ls180.v:5877.105-5877.149" + cell $eq $eq$ls180.v:5877$1201 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270615,10 +268760,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6071$1342_Y + connect \Y $eq$ls180.v:5877$1201_Y end - attribute \src "ls180.v:6082.32-6082.77" - cell $eq $eq$ls180.v:6082$1344 + attribute \src "ls180.v:5888.32-5888.77" + cell $eq $eq$ls180.v:5888$1203 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -270626,10 +268771,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [13:8] connect \B 3'110 - connect \Y $eq$ls180.v:6082$1344_Y + connect \Y $eq$ls180.v:5888$1203_Y end - attribute \src "ls180.v:6084.94-6084.138" - cell $eq $eq$ls180.v:6084$1346 + attribute \src "ls180.v:5890.94-5890.138" + cell $eq $eq$ls180.v:5890$1205 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270637,10 +268782,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6084$1346_Y + connect \Y $eq$ls180.v:5890$1205_Y end - attribute \src "ls180.v:6085.97-6085.141" - cell $eq $eq$ls180.v:6085$1350 + attribute \src "ls180.v:5891.97-5891.141" + cell $eq $eq$ls180.v:5891$1209 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270648,10 +268793,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6085$1350_Y + connect \Y $eq$ls180.v:5891$1209_Y end - attribute \src "ls180.v:6087.94-6087.138" - cell $eq $eq$ls180.v:6087$1353 + attribute \src "ls180.v:5893.94-5893.138" + cell $eq $eq$ls180.v:5893$1212 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270659,10 +268804,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6087$1353_Y + connect \Y $eq$ls180.v:5893$1212_Y end - attribute \src "ls180.v:6088.97-6088.141" - cell $eq $eq$ls180.v:6088$1357 + attribute \src "ls180.v:5894.97-5894.141" + cell $eq $eq$ls180.v:5894$1216 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270670,10 +268815,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6088$1357_Y + connect \Y $eq$ls180.v:5894$1216_Y end - attribute \src "ls180.v:6090.94-6090.138" - cell $eq $eq$ls180.v:6090$1360 + attribute \src "ls180.v:5896.94-5896.138" + cell $eq $eq$ls180.v:5896$1219 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270681,10 +268826,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6090$1360_Y + connect \Y $eq$ls180.v:5896$1219_Y end - attribute \src "ls180.v:6091.97-6091.141" - cell $eq $eq$ls180.v:6091$1364 + attribute \src "ls180.v:5897.97-5897.141" + cell $eq $eq$ls180.v:5897$1223 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270692,10 +268837,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6091$1364_Y + connect \Y $eq$ls180.v:5897$1223_Y end - attribute \src "ls180.v:6093.94-6093.138" - cell $eq $eq$ls180.v:6093$1367 + attribute \src "ls180.v:5899.94-5899.138" + cell $eq $eq$ls180.v:5899$1226 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270703,10 +268848,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6093$1367_Y + connect \Y $eq$ls180.v:5899$1226_Y end - attribute \src "ls180.v:6094.97-6094.141" - cell $eq $eq$ls180.v:6094$1371 + attribute \src "ls180.v:5900.97-5900.141" + cell $eq $eq$ls180.v:5900$1230 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270714,10 +268859,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6094$1371_Y + connect \Y $eq$ls180.v:5900$1230_Y end - attribute \src "ls180.v:6096.95-6096.139" - cell $eq $eq$ls180.v:6096$1374 + attribute \src "ls180.v:5902.95-5902.139" + cell $eq $eq$ls180.v:5902$1233 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270725,10 +268870,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6096$1374_Y + connect \Y $eq$ls180.v:5902$1233_Y end - attribute \src "ls180.v:6097.98-6097.142" - cell $eq $eq$ls180.v:6097$1378 + attribute \src "ls180.v:5903.98-5903.142" + cell $eq $eq$ls180.v:5903$1237 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270736,10 +268881,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6097$1378_Y + connect \Y $eq$ls180.v:5903$1237_Y end - attribute \src "ls180.v:6099.95-6099.139" - cell $eq $eq$ls180.v:6099$1381 + attribute \src "ls180.v:5905.95-5905.139" + cell $eq $eq$ls180.v:5905$1240 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270747,10 +268892,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6099$1381_Y + connect \Y $eq$ls180.v:5905$1240_Y end - attribute \src "ls180.v:6100.98-6100.142" - cell $eq $eq$ls180.v:6100$1385 + attribute \src "ls180.v:5906.98-5906.142" + cell $eq $eq$ls180.v:5906$1244 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -270758,10 +268903,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6100$1385_Y + connect \Y $eq$ls180.v:5906$1244_Y end - attribute \src "ls180.v:6108.32-6108.78" - cell $eq $eq$ls180.v:6108$1387 + attribute \src "ls180.v:5914.32-5914.78" + cell $eq $eq$ls180.v:5914$1246 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -270769,10 +268914,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [13:8] connect \B 4'1100 - connect \Y $eq$ls180.v:6108$1387_Y + connect \Y $eq$ls180.v:5914$1246_Y end - attribute \src "ls180.v:6110.93-6110.135" - cell $eq $eq$ls180.v:6110$1389 + attribute \src "ls180.v:5916.93-5916.135" + cell $eq $eq$ls180.v:5916$1248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -270780,10 +268925,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'0 - connect \Y $eq$ls180.v:6110$1389_Y + connect \Y $eq$ls180.v:5916$1248_Y end - attribute \src "ls180.v:6111.96-6111.138" - cell $eq $eq$ls180.v:6111$1393 + attribute \src "ls180.v:5917.96-5917.138" + cell $eq $eq$ls180.v:5917$1252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -270791,10 +268936,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'0 - connect \Y $eq$ls180.v:6111$1393_Y + connect \Y $eq$ls180.v:5917$1252_Y end - attribute \src "ls180.v:6113.92-6113.134" - cell $eq $eq$ls180.v:6113$1396 + attribute \src "ls180.v:5919.92-5919.134" + cell $eq $eq$ls180.v:5919$1255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -270802,10 +268947,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'1 - connect \Y $eq$ls180.v:6113$1396_Y + connect \Y $eq$ls180.v:5919$1255_Y end - attribute \src "ls180.v:6114.95-6114.137" - cell $eq $eq$ls180.v:6114$1400 + attribute \src "ls180.v:5920.95-5920.137" + cell $eq $eq$ls180.v:5920$1259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -270813,10 +268958,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_adr [0] connect \B 1'1 - connect \Y $eq$ls180.v:6114$1400_Y + connect \Y $eq$ls180.v:5920$1259_Y end - attribute \src "ls180.v:6122.32-6122.78" - cell $eq $eq$ls180.v:6122$1402 + attribute \src "ls180.v:5928.32-5928.78" + cell $eq $eq$ls180.v:5928$1261 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -270824,10 +268969,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [13:8] connect \B 4'1010 - connect \Y $eq$ls180.v:6122$1402_Y + connect \Y $eq$ls180.v:5928$1261_Y end - attribute \src "ls180.v:6124.98-6124.142" - cell $eq $eq$ls180.v:6124$1404 + attribute \src "ls180.v:5930.98-5930.142" + cell $eq $eq$ls180.v:5930$1263 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270835,10 +268980,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6124$1404_Y + connect \Y $eq$ls180.v:5930$1263_Y end - attribute \src "ls180.v:6125.101-6125.145" - cell $eq $eq$ls180.v:6125$1408 + attribute \src "ls180.v:5931.101-5931.145" + cell $eq $eq$ls180.v:5931$1267 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270846,10 +268991,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6125$1408_Y + connect \Y $eq$ls180.v:5931$1267_Y end - attribute \src "ls180.v:6127.97-6127.141" - cell $eq $eq$ls180.v:6127$1411 + attribute \src "ls180.v:5933.97-5933.141" + cell $eq $eq$ls180.v:5933$1270 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270857,10 +269002,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6127$1411_Y + connect \Y $eq$ls180.v:5933$1270_Y end - attribute \src "ls180.v:6128.100-6128.144" - cell $eq $eq$ls180.v:6128$1415 + attribute \src "ls180.v:5934.100-5934.144" + cell $eq $eq$ls180.v:5934$1274 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270868,10 +269013,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6128$1415_Y + connect \Y $eq$ls180.v:5934$1274_Y end - attribute \src "ls180.v:6130.97-6130.141" - cell $eq $eq$ls180.v:6130$1418 + attribute \src "ls180.v:5936.97-5936.141" + cell $eq $eq$ls180.v:5936$1277 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270879,10 +269024,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6130$1418_Y + connect \Y $eq$ls180.v:5936$1277_Y end - attribute \src "ls180.v:6131.100-6131.144" - cell $eq $eq$ls180.v:6131$1422 + attribute \src "ls180.v:5937.100-5937.144" + cell $eq $eq$ls180.v:5937$1281 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270890,10 +269035,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6131$1422_Y + connect \Y $eq$ls180.v:5937$1281_Y end - attribute \src "ls180.v:6133.97-6133.141" - cell $eq $eq$ls180.v:6133$1425 + attribute \src "ls180.v:5939.97-5939.141" + cell $eq $eq$ls180.v:5939$1284 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270901,10 +269046,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6133$1425_Y + connect \Y $eq$ls180.v:5939$1284_Y end - attribute \src "ls180.v:6134.100-6134.144" - cell $eq $eq$ls180.v:6134$1429 + attribute \src "ls180.v:5940.100-5940.144" + cell $eq $eq$ls180.v:5940$1288 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270912,10 +269057,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6134$1429_Y + connect \Y $eq$ls180.v:5940$1288_Y end - attribute \src "ls180.v:6136.97-6136.141" - cell $eq $eq$ls180.v:6136$1432 + attribute \src "ls180.v:5942.97-5942.141" + cell $eq $eq$ls180.v:5942$1291 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270923,10 +269068,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6136$1432_Y + connect \Y $eq$ls180.v:5942$1291_Y end - attribute \src "ls180.v:6137.100-6137.144" - cell $eq $eq$ls180.v:6137$1436 + attribute \src "ls180.v:5943.100-5943.144" + cell $eq $eq$ls180.v:5943$1295 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270934,10 +269079,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6137$1436_Y + connect \Y $eq$ls180.v:5943$1295_Y end - attribute \src "ls180.v:6139.98-6139.142" - cell $eq $eq$ls180.v:6139$1439 + attribute \src "ls180.v:5945.98-5945.142" + cell $eq $eq$ls180.v:5945$1298 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270945,10 +269090,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6139$1439_Y + connect \Y $eq$ls180.v:5945$1298_Y end - attribute \src "ls180.v:6140.101-6140.145" - cell $eq $eq$ls180.v:6140$1443 + attribute \src "ls180.v:5946.101-5946.145" + cell $eq $eq$ls180.v:5946$1302 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270956,10 +269101,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6140$1443_Y + connect \Y $eq$ls180.v:5946$1302_Y end - attribute \src "ls180.v:6142.98-6142.142" - cell $eq $eq$ls180.v:6142$1446 + attribute \src "ls180.v:5948.98-5948.142" + cell $eq $eq$ls180.v:5948$1305 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270967,10 +269112,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6142$1446_Y + connect \Y $eq$ls180.v:5948$1305_Y end - attribute \src "ls180.v:6143.101-6143.145" - cell $eq $eq$ls180.v:6143$1450 + attribute \src "ls180.v:5949.101-5949.145" + cell $eq $eq$ls180.v:5949$1309 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270978,10 +269123,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6143$1450_Y + connect \Y $eq$ls180.v:5949$1309_Y end - attribute \src "ls180.v:6145.98-6145.142" - cell $eq $eq$ls180.v:6145$1453 + attribute \src "ls180.v:5951.98-5951.142" + cell $eq $eq$ls180.v:5951$1312 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -270989,10 +269134,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6145$1453_Y + connect \Y $eq$ls180.v:5951$1312_Y end - attribute \src "ls180.v:6146.101-6146.145" - cell $eq $eq$ls180.v:6146$1457 + attribute \src "ls180.v:5952.101-5952.145" + cell $eq $eq$ls180.v:5952$1316 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271000,10 +269145,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6146$1457_Y + connect \Y $eq$ls180.v:5952$1316_Y end - attribute \src "ls180.v:6148.98-6148.142" - cell $eq $eq$ls180.v:6148$1460 + attribute \src "ls180.v:5954.98-5954.142" + cell $eq $eq$ls180.v:5954$1319 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271011,10 +269156,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6148$1460_Y + connect \Y $eq$ls180.v:5954$1319_Y end - attribute \src "ls180.v:6149.101-6149.145" - cell $eq $eq$ls180.v:6149$1464 + attribute \src "ls180.v:5955.101-5955.145" + cell $eq $eq$ls180.v:5955$1323 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271022,10 +269167,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6149$1464_Y + connect \Y $eq$ls180.v:5955$1323_Y end - attribute \src "ls180.v:6159.32-6159.78" - cell $eq $eq$ls180.v:6159$1466 + attribute \src "ls180.v:5965.32-5965.78" + cell $eq $eq$ls180.v:5965$1325 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271033,10 +269178,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [13:8] connect \B 4'1011 - connect \Y $eq$ls180.v:6159$1466_Y + connect \Y $eq$ls180.v:5965$1325_Y end - attribute \src "ls180.v:6161.98-6161.142" - cell $eq $eq$ls180.v:6161$1468 + attribute \src "ls180.v:5967.98-5967.142" + cell $eq $eq$ls180.v:5967$1327 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271044,10 +269189,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6161$1468_Y + connect \Y $eq$ls180.v:5967$1327_Y end - attribute \src "ls180.v:6162.101-6162.145" - cell $eq $eq$ls180.v:6162$1472 + attribute \src "ls180.v:5968.101-5968.145" + cell $eq $eq$ls180.v:5968$1331 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271055,10 +269200,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6162$1472_Y + connect \Y $eq$ls180.v:5968$1331_Y end - attribute \src "ls180.v:6164.97-6164.141" - cell $eq $eq$ls180.v:6164$1475 + attribute \src "ls180.v:5970.97-5970.141" + cell $eq $eq$ls180.v:5970$1334 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271066,10 +269211,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6164$1475_Y + connect \Y $eq$ls180.v:5970$1334_Y end - attribute \src "ls180.v:6165.100-6165.144" - cell $eq $eq$ls180.v:6165$1479 + attribute \src "ls180.v:5971.100-5971.144" + cell $eq $eq$ls180.v:5971$1338 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271077,10 +269222,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6165$1479_Y + connect \Y $eq$ls180.v:5971$1338_Y end - attribute \src "ls180.v:6167.97-6167.141" - cell $eq $eq$ls180.v:6167$1482 + attribute \src "ls180.v:5973.97-5973.141" + cell $eq $eq$ls180.v:5973$1341 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271088,10 +269233,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6167$1482_Y + connect \Y $eq$ls180.v:5973$1341_Y end - attribute \src "ls180.v:6168.100-6168.144" - cell $eq $eq$ls180.v:6168$1486 + attribute \src "ls180.v:5974.100-5974.144" + cell $eq $eq$ls180.v:5974$1345 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271099,10 +269244,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6168$1486_Y + connect \Y $eq$ls180.v:5974$1345_Y end - attribute \src "ls180.v:6170.97-6170.141" - cell $eq $eq$ls180.v:6170$1489 + attribute \src "ls180.v:5976.97-5976.141" + cell $eq $eq$ls180.v:5976$1348 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271110,10 +269255,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6170$1489_Y + connect \Y $eq$ls180.v:5976$1348_Y end - attribute \src "ls180.v:6171.100-6171.144" - cell $eq $eq$ls180.v:6171$1493 + attribute \src "ls180.v:5977.100-5977.144" + cell $eq $eq$ls180.v:5977$1352 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271121,10 +269266,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6171$1493_Y + connect \Y $eq$ls180.v:5977$1352_Y end - attribute \src "ls180.v:6173.97-6173.141" - cell $eq $eq$ls180.v:6173$1496 + attribute \src "ls180.v:5979.97-5979.141" + cell $eq $eq$ls180.v:5979$1355 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271132,10 +269277,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6173$1496_Y + connect \Y $eq$ls180.v:5979$1355_Y end - attribute \src "ls180.v:6174.100-6174.144" - cell $eq $eq$ls180.v:6174$1500 + attribute \src "ls180.v:5980.100-5980.144" + cell $eq $eq$ls180.v:5980$1359 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271143,10 +269288,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6174$1500_Y + connect \Y $eq$ls180.v:5980$1359_Y end - attribute \src "ls180.v:6176.98-6176.142" - cell $eq $eq$ls180.v:6176$1503 + attribute \src "ls180.v:5982.98-5982.142" + cell $eq $eq$ls180.v:5982$1362 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271154,10 +269299,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6176$1503_Y + connect \Y $eq$ls180.v:5982$1362_Y end - attribute \src "ls180.v:6177.101-6177.145" - cell $eq $eq$ls180.v:6177$1507 + attribute \src "ls180.v:5983.101-5983.145" + cell $eq $eq$ls180.v:5983$1366 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271165,10 +269310,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6177$1507_Y + connect \Y $eq$ls180.v:5983$1366_Y end - attribute \src "ls180.v:6179.98-6179.142" - cell $eq $eq$ls180.v:6179$1510 + attribute \src "ls180.v:5985.98-5985.142" + cell $eq $eq$ls180.v:5985$1369 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271176,10 +269321,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6179$1510_Y + connect \Y $eq$ls180.v:5985$1369_Y end - attribute \src "ls180.v:6180.101-6180.145" - cell $eq $eq$ls180.v:6180$1514 + attribute \src "ls180.v:5986.101-5986.145" + cell $eq $eq$ls180.v:5986$1373 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271187,10 +269332,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6180$1514_Y + connect \Y $eq$ls180.v:5986$1373_Y end - attribute \src "ls180.v:6182.98-6182.142" - cell $eq $eq$ls180.v:6182$1517 + attribute \src "ls180.v:5988.98-5988.142" + cell $eq $eq$ls180.v:5988$1376 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271198,10 +269343,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6182$1517_Y + connect \Y $eq$ls180.v:5988$1376_Y end - attribute \src "ls180.v:6183.101-6183.145" - cell $eq $eq$ls180.v:6183$1521 + attribute \src "ls180.v:5989.101-5989.145" + cell $eq $eq$ls180.v:5989$1380 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271209,10 +269354,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6183$1521_Y + connect \Y $eq$ls180.v:5989$1380_Y end - attribute \src "ls180.v:6185.98-6185.142" - cell $eq $eq$ls180.v:6185$1524 + attribute \src "ls180.v:5991.98-5991.142" + cell $eq $eq$ls180.v:5991$1383 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271220,10 +269365,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6185$1524_Y + connect \Y $eq$ls180.v:5991$1383_Y end - attribute \src "ls180.v:6186.101-6186.145" - cell $eq $eq$ls180.v:6186$1528 + attribute \src "ls180.v:5992.101-5992.145" + cell $eq $eq$ls180.v:5992$1387 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271231,10 +269376,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6186$1528_Y + connect \Y $eq$ls180.v:5992$1387_Y end - attribute \src "ls180.v:6196.32-6196.78" - cell $eq $eq$ls180.v:6196$1530 + attribute \src "ls180.v:6002.32-6002.78" + cell $eq $eq$ls180.v:6002$1389 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271242,10 +269387,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [13:8] connect \B 4'1111 - connect \Y $eq$ls180.v:6196$1530_Y + connect \Y $eq$ls180.v:6002$1389_Y end - attribute \src "ls180.v:6198.100-6198.144" - cell $eq $eq$ls180.v:6198$1532 + attribute \src "ls180.v:6004.100-6004.144" + cell $eq $eq$ls180.v:6004$1391 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271253,10 +269398,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6198$1532_Y + connect \Y $eq$ls180.v:6004$1391_Y end - attribute \src "ls180.v:6199.103-6199.147" - cell $eq $eq$ls180.v:6199$1536 + attribute \src "ls180.v:6005.103-6005.147" + cell $eq $eq$ls180.v:6005$1395 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271264,10 +269409,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6199$1536_Y + connect \Y $eq$ls180.v:6005$1395_Y end - attribute \src "ls180.v:6201.100-6201.144" - cell $eq $eq$ls180.v:6201$1539 + attribute \src "ls180.v:6007.100-6007.144" + cell $eq $eq$ls180.v:6007$1398 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271275,10 +269420,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6201$1539_Y + connect \Y $eq$ls180.v:6007$1398_Y end - attribute \src "ls180.v:6202.103-6202.147" - cell $eq $eq$ls180.v:6202$1543 + attribute \src "ls180.v:6008.103-6008.147" + cell $eq $eq$ls180.v:6008$1402 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271286,10 +269431,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6202$1543_Y + connect \Y $eq$ls180.v:6008$1402_Y end - attribute \src "ls180.v:6204.100-6204.144" - cell $eq $eq$ls180.v:6204$1546 + attribute \src "ls180.v:6010.100-6010.144" + cell $eq $eq$ls180.v:6010$1405 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271297,10 +269442,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6204$1546_Y + connect \Y $eq$ls180.v:6010$1405_Y end - attribute \src "ls180.v:6205.103-6205.147" - cell $eq $eq$ls180.v:6205$1550 + attribute \src "ls180.v:6011.103-6011.147" + cell $eq $eq$ls180.v:6011$1409 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271308,10 +269453,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6205$1550_Y + connect \Y $eq$ls180.v:6011$1409_Y end - attribute \src "ls180.v:6207.100-6207.144" - cell $eq $eq$ls180.v:6207$1553 + attribute \src "ls180.v:6013.100-6013.144" + cell $eq $eq$ls180.v:6013$1412 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271319,10 +269464,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6207$1553_Y + connect \Y $eq$ls180.v:6013$1412_Y end - attribute \src "ls180.v:6208.103-6208.147" - cell $eq $eq$ls180.v:6208$1557 + attribute \src "ls180.v:6014.103-6014.147" + cell $eq $eq$ls180.v:6014$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271330,10 +269475,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6208$1557_Y + connect \Y $eq$ls180.v:6014$1416_Y end - attribute \src "ls180.v:6210.100-6210.144" - cell $eq $eq$ls180.v:6210$1560 + attribute \src "ls180.v:6016.100-6016.144" + cell $eq $eq$ls180.v:6016$1419 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271341,10 +269486,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6210$1560_Y + connect \Y $eq$ls180.v:6016$1419_Y end - attribute \src "ls180.v:6211.103-6211.147" - cell $eq $eq$ls180.v:6211$1564 + attribute \src "ls180.v:6017.103-6017.147" + cell $eq $eq$ls180.v:6017$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271352,10 +269497,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6211$1564_Y + connect \Y $eq$ls180.v:6017$1423_Y end - attribute \src "ls180.v:6213.100-6213.144" - cell $eq $eq$ls180.v:6213$1567 + attribute \src "ls180.v:6019.100-6019.144" + cell $eq $eq$ls180.v:6019$1426 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271363,10 +269508,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6213$1567_Y + connect \Y $eq$ls180.v:6019$1426_Y end - attribute \src "ls180.v:6214.103-6214.147" - cell $eq $eq$ls180.v:6214$1571 + attribute \src "ls180.v:6020.103-6020.147" + cell $eq $eq$ls180.v:6020$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271374,10 +269519,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6214$1571_Y + connect \Y $eq$ls180.v:6020$1430_Y end - attribute \src "ls180.v:6216.100-6216.144" - cell $eq $eq$ls180.v:6216$1574 + attribute \src "ls180.v:6022.100-6022.144" + cell $eq $eq$ls180.v:6022$1433 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271385,10 +269530,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6216$1574_Y + connect \Y $eq$ls180.v:6022$1433_Y end - attribute \src "ls180.v:6217.103-6217.147" - cell $eq $eq$ls180.v:6217$1578 + attribute \src "ls180.v:6023.103-6023.147" + cell $eq $eq$ls180.v:6023$1437 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271396,10 +269541,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6217$1578_Y + connect \Y $eq$ls180.v:6023$1437_Y end - attribute \src "ls180.v:6219.100-6219.144" - cell $eq $eq$ls180.v:6219$1581 + attribute \src "ls180.v:6025.100-6025.144" + cell $eq $eq$ls180.v:6025$1440 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271407,10 +269552,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6219$1581_Y + connect \Y $eq$ls180.v:6025$1440_Y end - attribute \src "ls180.v:6220.103-6220.147" - cell $eq $eq$ls180.v:6220$1585 + attribute \src "ls180.v:6026.103-6026.147" + cell $eq $eq$ls180.v:6026$1444 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271418,10 +269563,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6220$1585_Y + connect \Y $eq$ls180.v:6026$1444_Y end - attribute \src "ls180.v:6222.102-6222.146" - cell $eq $eq$ls180.v:6222$1588 + attribute \src "ls180.v:6028.102-6028.146" + cell $eq $eq$ls180.v:6028$1447 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271429,10 +269574,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6222$1588_Y + connect \Y $eq$ls180.v:6028$1447_Y end - attribute \src "ls180.v:6223.105-6223.149" - cell $eq $eq$ls180.v:6223$1592 + attribute \src "ls180.v:6029.105-6029.149" + cell $eq $eq$ls180.v:6029$1451 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271440,10 +269585,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6223$1592_Y + connect \Y $eq$ls180.v:6029$1451_Y end - attribute \src "ls180.v:6225.102-6225.146" - cell $eq $eq$ls180.v:6225$1595 + attribute \src "ls180.v:6031.102-6031.146" + cell $eq $eq$ls180.v:6031$1454 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271451,10 +269596,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6225$1595_Y + connect \Y $eq$ls180.v:6031$1454_Y end - attribute \src "ls180.v:6226.105-6226.149" - cell $eq $eq$ls180.v:6226$1599 + attribute \src "ls180.v:6032.105-6032.149" + cell $eq $eq$ls180.v:6032$1458 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271462,10 +269607,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6226$1599_Y + connect \Y $eq$ls180.v:6032$1458_Y end - attribute \src "ls180.v:6228.102-6228.147" - cell $eq $eq$ls180.v:6228$1602 + attribute \src "ls180.v:6034.102-6034.147" + cell $eq $eq$ls180.v:6034$1461 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271473,10 +269618,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6228$1602_Y + connect \Y $eq$ls180.v:6034$1461_Y end - attribute \src "ls180.v:6229.105-6229.150" - cell $eq $eq$ls180.v:6229$1606 + attribute \src "ls180.v:6035.105-6035.150" + cell $eq $eq$ls180.v:6035$1465 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271484,10 +269629,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6229$1606_Y + connect \Y $eq$ls180.v:6035$1465_Y end - attribute \src "ls180.v:6231.102-6231.147" - cell $eq $eq$ls180.v:6231$1609 + attribute \src "ls180.v:6037.102-6037.147" + cell $eq $eq$ls180.v:6037$1468 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271495,10 +269640,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6231$1609_Y + connect \Y $eq$ls180.v:6037$1468_Y end - attribute \src "ls180.v:6232.105-6232.150" - cell $eq $eq$ls180.v:6232$1613 + attribute \src "ls180.v:6038.105-6038.150" + cell $eq $eq$ls180.v:6038$1472 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271506,10 +269651,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6232$1613_Y + connect \Y $eq$ls180.v:6038$1472_Y end - attribute \src "ls180.v:6234.102-6234.147" - cell $eq $eq$ls180.v:6234$1616 + attribute \src "ls180.v:6040.102-6040.147" + cell $eq $eq$ls180.v:6040$1475 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271517,10 +269662,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6234$1616_Y + connect \Y $eq$ls180.v:6040$1475_Y end - attribute \src "ls180.v:6235.105-6235.150" - cell $eq $eq$ls180.v:6235$1620 + attribute \src "ls180.v:6041.105-6041.150" + cell $eq $eq$ls180.v:6041$1479 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271528,10 +269673,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6235$1620_Y + connect \Y $eq$ls180.v:6041$1479_Y end - attribute \src "ls180.v:6237.99-6237.144" - cell $eq $eq$ls180.v:6237$1623 + attribute \src "ls180.v:6043.99-6043.144" + cell $eq $eq$ls180.v:6043$1482 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271539,10 +269684,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6237$1623_Y + connect \Y $eq$ls180.v:6043$1482_Y end - attribute \src "ls180.v:6238.102-6238.147" - cell $eq $eq$ls180.v:6238$1627 + attribute \src "ls180.v:6044.102-6044.147" + cell $eq $eq$ls180.v:6044$1486 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271550,10 +269695,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6238$1627_Y + connect \Y $eq$ls180.v:6044$1486_Y end - attribute \src "ls180.v:6240.100-6240.145" - cell $eq $eq$ls180.v:6240$1630 + attribute \src "ls180.v:6046.100-6046.145" + cell $eq $eq$ls180.v:6046$1489 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271561,10 +269706,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6240$1630_Y + connect \Y $eq$ls180.v:6046$1489_Y end - attribute \src "ls180.v:6241.103-6241.148" - cell $eq $eq$ls180.v:6241$1634 + attribute \src "ls180.v:6047.103-6047.148" + cell $eq $eq$ls180.v:6047$1493 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -271572,10 +269717,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_adr [3:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6241$1634_Y + connect \Y $eq$ls180.v:6047$1493_Y end - attribute \src "ls180.v:6258.32-6258.78" - cell $eq $eq$ls180.v:6258$1636 + attribute \src "ls180.v:6064.32-6064.78" + cell $eq $eq$ls180.v:6064$1495 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271583,10 +269728,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [13:8] connect \B 4'1110 - connect \Y $eq$ls180.v:6258$1636_Y + connect \Y $eq$ls180.v:6064$1495_Y end - attribute \src "ls180.v:6260.104-6260.148" - cell $eq $eq$ls180.v:6260$1638 + attribute \src "ls180.v:6066.104-6066.148" + cell $eq $eq$ls180.v:6066$1497 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271594,10 +269739,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'0 - connect \Y $eq$ls180.v:6260$1638_Y + connect \Y $eq$ls180.v:6066$1497_Y end - attribute \src "ls180.v:6261.107-6261.151" - cell $eq $eq$ls180.v:6261$1642 + attribute \src "ls180.v:6067.107-6067.151" + cell $eq $eq$ls180.v:6067$1501 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271605,10 +269750,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'0 - connect \Y $eq$ls180.v:6261$1642_Y + connect \Y $eq$ls180.v:6067$1501_Y end - attribute \src "ls180.v:6263.104-6263.148" - cell $eq $eq$ls180.v:6263$1645 + attribute \src "ls180.v:6069.104-6069.148" + cell $eq $eq$ls180.v:6069$1504 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271616,10 +269761,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'1 - connect \Y $eq$ls180.v:6263$1645_Y + connect \Y $eq$ls180.v:6069$1504_Y end - attribute \src "ls180.v:6264.107-6264.151" - cell $eq $eq$ls180.v:6264$1649 + attribute \src "ls180.v:6070.107-6070.151" + cell $eq $eq$ls180.v:6070$1508 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271627,10 +269772,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 1'1 - connect \Y $eq$ls180.v:6264$1649_Y + connect \Y $eq$ls180.v:6070$1508_Y end - attribute \src "ls180.v:6266.104-6266.148" - cell $eq $eq$ls180.v:6266$1652 + attribute \src "ls180.v:6072.104-6072.148" + cell $eq $eq$ls180.v:6072$1511 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271638,10 +269783,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'10 - connect \Y $eq$ls180.v:6266$1652_Y + connect \Y $eq$ls180.v:6072$1511_Y end - attribute \src "ls180.v:6267.107-6267.151" - cell $eq $eq$ls180.v:6267$1656 + attribute \src "ls180.v:6073.107-6073.151" + cell $eq $eq$ls180.v:6073$1515 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271649,10 +269794,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'10 - connect \Y $eq$ls180.v:6267$1656_Y + connect \Y $eq$ls180.v:6073$1515_Y end - attribute \src "ls180.v:6269.104-6269.148" - cell $eq $eq$ls180.v:6269$1659 + attribute \src "ls180.v:6075.104-6075.148" + cell $eq $eq$ls180.v:6075$1518 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271660,10 +269805,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'11 - connect \Y $eq$ls180.v:6269$1659_Y + connect \Y $eq$ls180.v:6075$1518_Y end - attribute \src "ls180.v:6270.107-6270.151" - cell $eq $eq$ls180.v:6270$1663 + attribute \src "ls180.v:6076.107-6076.151" + cell $eq $eq$ls180.v:6076$1522 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271671,10 +269816,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 2'11 - connect \Y $eq$ls180.v:6270$1663_Y + connect \Y $eq$ls180.v:6076$1522_Y end - attribute \src "ls180.v:6272.103-6272.147" - cell $eq $eq$ls180.v:6272$1666 + attribute \src "ls180.v:6078.103-6078.147" + cell $eq $eq$ls180.v:6078$1525 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271682,10 +269827,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'100 - connect \Y $eq$ls180.v:6272$1666_Y + connect \Y $eq$ls180.v:6078$1525_Y end - attribute \src "ls180.v:6273.106-6273.150" - cell $eq $eq$ls180.v:6273$1670 + attribute \src "ls180.v:6079.106-6079.150" + cell $eq $eq$ls180.v:6079$1529 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271693,10 +269838,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'100 - connect \Y $eq$ls180.v:6273$1670_Y + connect \Y $eq$ls180.v:6079$1529_Y end - attribute \src "ls180.v:6275.103-6275.147" - cell $eq $eq$ls180.v:6275$1673 + attribute \src "ls180.v:6081.103-6081.147" + cell $eq $eq$ls180.v:6081$1532 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271704,10 +269849,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'101 - connect \Y $eq$ls180.v:6275$1673_Y + connect \Y $eq$ls180.v:6081$1532_Y end - attribute \src "ls180.v:6276.106-6276.150" - cell $eq $eq$ls180.v:6276$1677 + attribute \src "ls180.v:6082.106-6082.150" + cell $eq $eq$ls180.v:6082$1536 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271715,10 +269860,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'101 - connect \Y $eq$ls180.v:6276$1677_Y + connect \Y $eq$ls180.v:6082$1536_Y end - attribute \src "ls180.v:6278.103-6278.147" - cell $eq $eq$ls180.v:6278$1680 + attribute \src "ls180.v:6084.103-6084.147" + cell $eq $eq$ls180.v:6084$1539 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271726,10 +269871,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'110 - connect \Y $eq$ls180.v:6278$1680_Y + connect \Y $eq$ls180.v:6084$1539_Y end - attribute \src "ls180.v:6279.106-6279.150" - cell $eq $eq$ls180.v:6279$1684 + attribute \src "ls180.v:6085.106-6085.150" + cell $eq $eq$ls180.v:6085$1543 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271737,10 +269882,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'110 - connect \Y $eq$ls180.v:6279$1684_Y + connect \Y $eq$ls180.v:6085$1543_Y end - attribute \src "ls180.v:6281.103-6281.147" - cell $eq $eq$ls180.v:6281$1687 + attribute \src "ls180.v:6087.103-6087.147" + cell $eq $eq$ls180.v:6087$1546 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271748,10 +269893,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'111 - connect \Y $eq$ls180.v:6281$1687_Y + connect \Y $eq$ls180.v:6087$1546_Y end - attribute \src "ls180.v:6282.106-6282.150" - cell $eq $eq$ls180.v:6282$1691 + attribute \src "ls180.v:6088.106-6088.150" + cell $eq $eq$ls180.v:6088$1550 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271759,10 +269904,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 3'111 - connect \Y $eq$ls180.v:6282$1691_Y + connect \Y $eq$ls180.v:6088$1550_Y end - attribute \src "ls180.v:6284.94-6284.138" - cell $eq $eq$ls180.v:6284$1694 + attribute \src "ls180.v:6090.94-6090.138" + cell $eq $eq$ls180.v:6090$1553 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271770,10 +269915,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6284$1694_Y + connect \Y $eq$ls180.v:6090$1553_Y end - attribute \src "ls180.v:6285.97-6285.141" - cell $eq $eq$ls180.v:6285$1698 + attribute \src "ls180.v:6091.97-6091.141" + cell $eq $eq$ls180.v:6091$1557 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271781,10 +269926,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6285$1698_Y + connect \Y $eq$ls180.v:6091$1557_Y end - attribute \src "ls180.v:6287.105-6287.149" - cell $eq $eq$ls180.v:6287$1701 + attribute \src "ls180.v:6093.105-6093.149" + cell $eq $eq$ls180.v:6093$1560 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271792,10 +269937,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6287$1701_Y + connect \Y $eq$ls180.v:6093$1560_Y end - attribute \src "ls180.v:6288.108-6288.152" - cell $eq $eq$ls180.v:6288$1705 + attribute \src "ls180.v:6094.108-6094.152" + cell $eq $eq$ls180.v:6094$1564 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271803,10 +269948,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6288$1705_Y + connect \Y $eq$ls180.v:6094$1564_Y end - attribute \src "ls180.v:6290.105-6290.150" - cell $eq $eq$ls180.v:6290$1708 + attribute \src "ls180.v:6096.105-6096.150" + cell $eq $eq$ls180.v:6096$1567 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271814,10 +269959,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6290$1708_Y + connect \Y $eq$ls180.v:6096$1567_Y end - attribute \src "ls180.v:6291.108-6291.153" - cell $eq $eq$ls180.v:6291$1712 + attribute \src "ls180.v:6097.108-6097.153" + cell $eq $eq$ls180.v:6097$1571 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271825,10 +269970,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6291$1712_Y + connect \Y $eq$ls180.v:6097$1571_Y end - attribute \src "ls180.v:6293.105-6293.150" - cell $eq $eq$ls180.v:6293$1715 + attribute \src "ls180.v:6099.105-6099.150" + cell $eq $eq$ls180.v:6099$1574 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271836,10 +269981,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6293$1715_Y + connect \Y $eq$ls180.v:6099$1574_Y end - attribute \src "ls180.v:6294.108-6294.153" - cell $eq $eq$ls180.v:6294$1719 + attribute \src "ls180.v:6100.108-6100.153" + cell $eq $eq$ls180.v:6100$1578 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271847,10 +269992,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6294$1719_Y + connect \Y $eq$ls180.v:6100$1578_Y end - attribute \src "ls180.v:6296.105-6296.150" - cell $eq $eq$ls180.v:6296$1722 + attribute \src "ls180.v:6102.105-6102.150" + cell $eq $eq$ls180.v:6102$1581 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271858,10 +270003,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6296$1722_Y + connect \Y $eq$ls180.v:6102$1581_Y end - attribute \src "ls180.v:6297.108-6297.153" - cell $eq $eq$ls180.v:6297$1726 + attribute \src "ls180.v:6103.108-6103.153" + cell $eq $eq$ls180.v:6103$1585 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271869,10 +270014,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6297$1726_Y + connect \Y $eq$ls180.v:6103$1585_Y end - attribute \src "ls180.v:6299.105-6299.150" - cell $eq $eq$ls180.v:6299$1729 + attribute \src "ls180.v:6105.105-6105.150" + cell $eq $eq$ls180.v:6105$1588 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271880,10 +270025,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6299$1729_Y + connect \Y $eq$ls180.v:6105$1588_Y end - attribute \src "ls180.v:6300.108-6300.153" - cell $eq $eq$ls180.v:6300$1733 + attribute \src "ls180.v:6106.108-6106.153" + cell $eq $eq$ls180.v:6106$1592 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271891,10 +270036,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6300$1733_Y + connect \Y $eq$ls180.v:6106$1592_Y end - attribute \src "ls180.v:6302.105-6302.150" - cell $eq $eq$ls180.v:6302$1736 + attribute \src "ls180.v:6108.105-6108.150" + cell $eq $eq$ls180.v:6108$1595 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271902,10 +270047,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6302$1736_Y + connect \Y $eq$ls180.v:6108$1595_Y end - attribute \src "ls180.v:6303.108-6303.153" - cell $eq $eq$ls180.v:6303$1740 + attribute \src "ls180.v:6109.108-6109.153" + cell $eq $eq$ls180.v:6109$1599 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271913,10 +270058,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6303$1740_Y + connect \Y $eq$ls180.v:6109$1599_Y end - attribute \src "ls180.v:6305.104-6305.149" - cell $eq $eq$ls180.v:6305$1743 + attribute \src "ls180.v:6111.104-6111.149" + cell $eq $eq$ls180.v:6111$1602 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271924,10 +270069,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6305$1743_Y + connect \Y $eq$ls180.v:6111$1602_Y end - attribute \src "ls180.v:6306.107-6306.152" - cell $eq $eq$ls180.v:6306$1747 + attribute \src "ls180.v:6112.107-6112.152" + cell $eq $eq$ls180.v:6112$1606 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271935,10 +270080,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6306$1747_Y + connect \Y $eq$ls180.v:6112$1606_Y end - attribute \src "ls180.v:6308.104-6308.149" - cell $eq $eq$ls180.v:6308$1750 + attribute \src "ls180.v:6114.104-6114.149" + cell $eq $eq$ls180.v:6114$1609 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271946,10 +270091,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6308$1750_Y + connect \Y $eq$ls180.v:6114$1609_Y end - attribute \src "ls180.v:6309.107-6309.152" - cell $eq $eq$ls180.v:6309$1754 + attribute \src "ls180.v:6115.107-6115.152" + cell $eq $eq$ls180.v:6115$1613 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271957,10 +270102,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6309$1754_Y + connect \Y $eq$ls180.v:6115$1613_Y end - attribute \src "ls180.v:6311.104-6311.149" - cell $eq $eq$ls180.v:6311$1757 + attribute \src "ls180.v:6117.104-6117.149" + cell $eq $eq$ls180.v:6117$1616 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271968,10 +270113,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6311$1757_Y + connect \Y $eq$ls180.v:6117$1616_Y end - attribute \src "ls180.v:6312.107-6312.152" - cell $eq $eq$ls180.v:6312$1761 + attribute \src "ls180.v:6118.107-6118.152" + cell $eq $eq$ls180.v:6118$1620 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271979,10 +270124,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6312$1761_Y + connect \Y $eq$ls180.v:6118$1620_Y end - attribute \src "ls180.v:6314.104-6314.149" - cell $eq $eq$ls180.v:6314$1764 + attribute \src "ls180.v:6120.104-6120.149" + cell $eq $eq$ls180.v:6120$1623 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -271990,10 +270135,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6314$1764_Y + connect \Y $eq$ls180.v:6120$1623_Y end - attribute \src "ls180.v:6315.107-6315.152" - cell $eq $eq$ls180.v:6315$1768 + attribute \src "ls180.v:6121.107-6121.152" + cell $eq $eq$ls180.v:6121$1627 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272001,10 +270146,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6315$1768_Y + connect \Y $eq$ls180.v:6121$1627_Y end - attribute \src "ls180.v:6317.104-6317.149" - cell $eq $eq$ls180.v:6317$1771 + attribute \src "ls180.v:6123.104-6123.149" + cell $eq $eq$ls180.v:6123$1630 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272012,10 +270157,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10011 - connect \Y $eq$ls180.v:6317$1771_Y + connect \Y $eq$ls180.v:6123$1630_Y end - attribute \src "ls180.v:6318.107-6318.152" - cell $eq $eq$ls180.v:6318$1775 + attribute \src "ls180.v:6124.107-6124.152" + cell $eq $eq$ls180.v:6124$1634 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272023,10 +270168,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10011 - connect \Y $eq$ls180.v:6318$1775_Y + connect \Y $eq$ls180.v:6124$1634_Y end - attribute \src "ls180.v:6320.104-6320.149" - cell $eq $eq$ls180.v:6320$1778 + attribute \src "ls180.v:6126.104-6126.149" + cell $eq $eq$ls180.v:6126$1637 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272034,10 +270179,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10100 - connect \Y $eq$ls180.v:6320$1778_Y + connect \Y $eq$ls180.v:6126$1637_Y end - attribute \src "ls180.v:6321.107-6321.152" - cell $eq $eq$ls180.v:6321$1782 + attribute \src "ls180.v:6127.107-6127.152" + cell $eq $eq$ls180.v:6127$1641 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272045,10 +270190,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10100 - connect \Y $eq$ls180.v:6321$1782_Y + connect \Y $eq$ls180.v:6127$1641_Y end - attribute \src "ls180.v:6323.104-6323.149" - cell $eq $eq$ls180.v:6323$1785 + attribute \src "ls180.v:6129.104-6129.149" + cell $eq $eq$ls180.v:6129$1644 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272056,10 +270201,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10101 - connect \Y $eq$ls180.v:6323$1785_Y + connect \Y $eq$ls180.v:6129$1644_Y end - attribute \src "ls180.v:6324.107-6324.152" - cell $eq $eq$ls180.v:6324$1789 + attribute \src "ls180.v:6130.107-6130.152" + cell $eq $eq$ls180.v:6130$1648 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272067,10 +270212,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10101 - connect \Y $eq$ls180.v:6324$1789_Y + connect \Y $eq$ls180.v:6130$1648_Y end - attribute \src "ls180.v:6326.104-6326.149" - cell $eq $eq$ls180.v:6326$1792 + attribute \src "ls180.v:6132.104-6132.149" + cell $eq $eq$ls180.v:6132$1651 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272078,10 +270223,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10110 - connect \Y $eq$ls180.v:6326$1792_Y + connect \Y $eq$ls180.v:6132$1651_Y end - attribute \src "ls180.v:6327.107-6327.152" - cell $eq $eq$ls180.v:6327$1796 + attribute \src "ls180.v:6133.107-6133.152" + cell $eq $eq$ls180.v:6133$1655 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272089,10 +270234,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10110 - connect \Y $eq$ls180.v:6327$1796_Y + connect \Y $eq$ls180.v:6133$1655_Y end - attribute \src "ls180.v:6329.104-6329.149" - cell $eq $eq$ls180.v:6329$1799 + attribute \src "ls180.v:6135.104-6135.149" + cell $eq $eq$ls180.v:6135$1658 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272100,10 +270245,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10111 - connect \Y $eq$ls180.v:6329$1799_Y + connect \Y $eq$ls180.v:6135$1658_Y end - attribute \src "ls180.v:6330.107-6330.152" - cell $eq $eq$ls180.v:6330$1803 + attribute \src "ls180.v:6136.107-6136.152" + cell $eq $eq$ls180.v:6136$1662 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272111,10 +270256,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'10111 - connect \Y $eq$ls180.v:6330$1803_Y + connect \Y $eq$ls180.v:6136$1662_Y end - attribute \src "ls180.v:6332.104-6332.149" - cell $eq $eq$ls180.v:6332$1806 + attribute \src "ls180.v:6138.104-6138.149" + cell $eq $eq$ls180.v:6138$1665 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272122,10 +270267,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11000 - connect \Y $eq$ls180.v:6332$1806_Y + connect \Y $eq$ls180.v:6138$1665_Y end - attribute \src "ls180.v:6333.107-6333.152" - cell $eq $eq$ls180.v:6333$1810 + attribute \src "ls180.v:6139.107-6139.152" + cell $eq $eq$ls180.v:6139$1669 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272133,10 +270278,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11000 - connect \Y $eq$ls180.v:6333$1810_Y + connect \Y $eq$ls180.v:6139$1669_Y end - attribute \src "ls180.v:6335.100-6335.145" - cell $eq $eq$ls180.v:6335$1813 + attribute \src "ls180.v:6141.100-6141.145" + cell $eq $eq$ls180.v:6141$1672 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272144,10 +270289,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11001 - connect \Y $eq$ls180.v:6335$1813_Y + connect \Y $eq$ls180.v:6141$1672_Y end - attribute \src "ls180.v:6336.103-6336.148" - cell $eq $eq$ls180.v:6336$1817 + attribute \src "ls180.v:6142.103-6142.148" + cell $eq $eq$ls180.v:6142$1676 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272155,10 +270300,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11001 - connect \Y $eq$ls180.v:6336$1817_Y + connect \Y $eq$ls180.v:6142$1676_Y end - attribute \src "ls180.v:6338.101-6338.146" - cell $eq $eq$ls180.v:6338$1820 + attribute \src "ls180.v:6144.101-6144.146" + cell $eq $eq$ls180.v:6144$1679 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272166,10 +270311,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11010 - connect \Y $eq$ls180.v:6338$1820_Y + connect \Y $eq$ls180.v:6144$1679_Y end - attribute \src "ls180.v:6339.104-6339.149" - cell $eq $eq$ls180.v:6339$1824 + attribute \src "ls180.v:6145.104-6145.149" + cell $eq $eq$ls180.v:6145$1683 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272177,10 +270322,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11010 - connect \Y $eq$ls180.v:6339$1824_Y + connect \Y $eq$ls180.v:6145$1683_Y end - attribute \src "ls180.v:6341.104-6341.149" - cell $eq $eq$ls180.v:6341$1827 + attribute \src "ls180.v:6147.104-6147.149" + cell $eq $eq$ls180.v:6147$1686 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272188,10 +270333,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11011 - connect \Y $eq$ls180.v:6341$1827_Y + connect \Y $eq$ls180.v:6147$1686_Y end - attribute \src "ls180.v:6342.107-6342.152" - cell $eq $eq$ls180.v:6342$1831 + attribute \src "ls180.v:6148.107-6148.152" + cell $eq $eq$ls180.v:6148$1690 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272199,10 +270344,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11011 - connect \Y $eq$ls180.v:6342$1831_Y + connect \Y $eq$ls180.v:6148$1690_Y end - attribute \src "ls180.v:6344.104-6344.149" - cell $eq $eq$ls180.v:6344$1834 + attribute \src "ls180.v:6150.104-6150.149" + cell $eq $eq$ls180.v:6150$1693 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272210,10 +270355,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11100 - connect \Y $eq$ls180.v:6344$1834_Y + connect \Y $eq$ls180.v:6150$1693_Y end - attribute \src "ls180.v:6345.107-6345.152" - cell $eq $eq$ls180.v:6345$1838 + attribute \src "ls180.v:6151.107-6151.152" + cell $eq $eq$ls180.v:6151$1697 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272221,10 +270366,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11100 - connect \Y $eq$ls180.v:6345$1838_Y + connect \Y $eq$ls180.v:6151$1697_Y end - attribute \src "ls180.v:6347.103-6347.148" - cell $eq $eq$ls180.v:6347$1841 + attribute \src "ls180.v:6153.103-6153.148" + cell $eq $eq$ls180.v:6153$1700 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272232,10 +270377,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11101 - connect \Y $eq$ls180.v:6347$1841_Y + connect \Y $eq$ls180.v:6153$1700_Y end - attribute \src "ls180.v:6348.106-6348.151" - cell $eq $eq$ls180.v:6348$1845 + attribute \src "ls180.v:6154.106-6154.151" + cell $eq $eq$ls180.v:6154$1704 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272243,10 +270388,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11101 - connect \Y $eq$ls180.v:6348$1845_Y + connect \Y $eq$ls180.v:6154$1704_Y end - attribute \src "ls180.v:6350.103-6350.148" - cell $eq $eq$ls180.v:6350$1848 + attribute \src "ls180.v:6156.103-6156.148" + cell $eq $eq$ls180.v:6156$1707 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272254,10 +270399,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11110 - connect \Y $eq$ls180.v:6350$1848_Y + connect \Y $eq$ls180.v:6156$1707_Y end - attribute \src "ls180.v:6351.106-6351.151" - cell $eq $eq$ls180.v:6351$1852 + attribute \src "ls180.v:6157.106-6157.151" + cell $eq $eq$ls180.v:6157$1711 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272265,10 +270410,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11110 - connect \Y $eq$ls180.v:6351$1852_Y + connect \Y $eq$ls180.v:6157$1711_Y end - attribute \src "ls180.v:6353.103-6353.148" - cell $eq $eq$ls180.v:6353$1855 + attribute \src "ls180.v:6159.103-6159.148" + cell $eq $eq$ls180.v:6159$1714 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272276,10 +270421,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11111 - connect \Y $eq$ls180.v:6353$1855_Y + connect \Y $eq$ls180.v:6159$1714_Y end - attribute \src "ls180.v:6354.106-6354.151" - cell $eq $eq$ls180.v:6354$1859 + attribute \src "ls180.v:6160.106-6160.151" + cell $eq $eq$ls180.v:6160$1718 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272287,10 +270432,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 5'11111 - connect \Y $eq$ls180.v:6354$1859_Y + connect \Y $eq$ls180.v:6160$1718_Y end - attribute \src "ls180.v:6356.103-6356.148" - cell $eq $eq$ls180.v:6356$1862 + attribute \src "ls180.v:6162.103-6162.148" + cell $eq $eq$ls180.v:6162$1721 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272298,10 +270443,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 6'100000 - connect \Y $eq$ls180.v:6356$1862_Y + connect \Y $eq$ls180.v:6162$1721_Y end - attribute \src "ls180.v:6357.106-6357.151" - cell $eq $eq$ls180.v:6357$1866 + attribute \src "ls180.v:6163.106-6163.151" + cell $eq $eq$ls180.v:6163$1725 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272309,10 +270454,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_adr [5:0] connect \B 6'100000 - connect \Y $eq$ls180.v:6357$1866_Y + connect \Y $eq$ls180.v:6163$1725_Y end - attribute \src "ls180.v:6393.32-6393.78" - cell $eq $eq$ls180.v:6393$1868 + attribute \src "ls180.v:6199.32-6199.78" + cell $eq $eq$ls180.v:6199$1727 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272320,10 +270465,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [13:8] connect \B 5'10000 - connect \Y $eq$ls180.v:6393$1868_Y + connect \Y $eq$ls180.v:6199$1727_Y end - attribute \src "ls180.v:6395.100-6395.144" - cell $eq $eq$ls180.v:6395$1870 + attribute \src "ls180.v:6201.100-6201.144" + cell $eq $eq$ls180.v:6201$1729 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272331,10 +270476,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6395$1870_Y + connect \Y $eq$ls180.v:6201$1729_Y end - attribute \src "ls180.v:6396.103-6396.147" - cell $eq $eq$ls180.v:6396$1874 + attribute \src "ls180.v:6202.103-6202.147" + cell $eq $eq$ls180.v:6202$1733 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272342,10 +270487,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6396$1874_Y + connect \Y $eq$ls180.v:6202$1733_Y end - attribute \src "ls180.v:6398.100-6398.144" - cell $eq $eq$ls180.v:6398$1877 + attribute \src "ls180.v:6204.100-6204.144" + cell $eq $eq$ls180.v:6204$1736 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272353,10 +270498,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6398$1877_Y + connect \Y $eq$ls180.v:6204$1736_Y end - attribute \src "ls180.v:6399.103-6399.147" - cell $eq $eq$ls180.v:6399$1881 + attribute \src "ls180.v:6205.103-6205.147" + cell $eq $eq$ls180.v:6205$1740 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272364,10 +270509,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6399$1881_Y + connect \Y $eq$ls180.v:6205$1740_Y end - attribute \src "ls180.v:6401.100-6401.144" - cell $eq $eq$ls180.v:6401$1884 + attribute \src "ls180.v:6207.100-6207.144" + cell $eq $eq$ls180.v:6207$1743 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272375,10 +270520,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6401$1884_Y + connect \Y $eq$ls180.v:6207$1743_Y end - attribute \src "ls180.v:6402.103-6402.147" - cell $eq $eq$ls180.v:6402$1888 + attribute \src "ls180.v:6208.103-6208.147" + cell $eq $eq$ls180.v:6208$1747 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272386,10 +270531,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6402$1888_Y + connect \Y $eq$ls180.v:6208$1747_Y end - attribute \src "ls180.v:6404.100-6404.144" - cell $eq $eq$ls180.v:6404$1891 + attribute \src "ls180.v:6210.100-6210.144" + cell $eq $eq$ls180.v:6210$1750 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272397,10 +270542,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6404$1891_Y + connect \Y $eq$ls180.v:6210$1750_Y end - attribute \src "ls180.v:6405.103-6405.147" - cell $eq $eq$ls180.v:6405$1895 + attribute \src "ls180.v:6211.103-6211.147" + cell $eq $eq$ls180.v:6211$1754 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272408,10 +270553,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6405$1895_Y + connect \Y $eq$ls180.v:6211$1754_Y end - attribute \src "ls180.v:6407.100-6407.144" - cell $eq $eq$ls180.v:6407$1898 + attribute \src "ls180.v:6213.100-6213.144" + cell $eq $eq$ls180.v:6213$1757 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272419,10 +270564,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6407$1898_Y + connect \Y $eq$ls180.v:6213$1757_Y end - attribute \src "ls180.v:6408.103-6408.147" - cell $eq $eq$ls180.v:6408$1902 + attribute \src "ls180.v:6214.103-6214.147" + cell $eq $eq$ls180.v:6214$1761 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272430,10 +270575,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6408$1902_Y + connect \Y $eq$ls180.v:6214$1761_Y end - attribute \src "ls180.v:6410.100-6410.144" - cell $eq $eq$ls180.v:6410$1905 + attribute \src "ls180.v:6216.100-6216.144" + cell $eq $eq$ls180.v:6216$1764 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272441,10 +270586,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6410$1905_Y + connect \Y $eq$ls180.v:6216$1764_Y end - attribute \src "ls180.v:6411.103-6411.147" - cell $eq $eq$ls180.v:6411$1909 + attribute \src "ls180.v:6217.103-6217.147" + cell $eq $eq$ls180.v:6217$1768 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272452,10 +270597,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6411$1909_Y + connect \Y $eq$ls180.v:6217$1768_Y end - attribute \src "ls180.v:6413.100-6413.144" - cell $eq $eq$ls180.v:6413$1912 + attribute \src "ls180.v:6219.100-6219.144" + cell $eq $eq$ls180.v:6219$1771 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272463,10 +270608,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6413$1912_Y + connect \Y $eq$ls180.v:6219$1771_Y end - attribute \src "ls180.v:6414.103-6414.147" - cell $eq $eq$ls180.v:6414$1916 + attribute \src "ls180.v:6220.103-6220.147" + cell $eq $eq$ls180.v:6220$1775 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272474,10 +270619,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6414$1916_Y + connect \Y $eq$ls180.v:6220$1775_Y end - attribute \src "ls180.v:6416.100-6416.144" - cell $eq $eq$ls180.v:6416$1919 + attribute \src "ls180.v:6222.100-6222.144" + cell $eq $eq$ls180.v:6222$1778 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272485,10 +270630,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6416$1919_Y + connect \Y $eq$ls180.v:6222$1778_Y end - attribute \src "ls180.v:6417.103-6417.147" - cell $eq $eq$ls180.v:6417$1923 + attribute \src "ls180.v:6223.103-6223.147" + cell $eq $eq$ls180.v:6223$1782 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272496,10 +270641,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6417$1923_Y + connect \Y $eq$ls180.v:6223$1782_Y end - attribute \src "ls180.v:6419.102-6419.146" - cell $eq $eq$ls180.v:6419$1926 + attribute \src "ls180.v:6225.102-6225.146" + cell $eq $eq$ls180.v:6225$1785 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272507,10 +270652,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6419$1926_Y + connect \Y $eq$ls180.v:6225$1785_Y end - attribute \src "ls180.v:6420.105-6420.149" - cell $eq $eq$ls180.v:6420$1930 + attribute \src "ls180.v:6226.105-6226.149" + cell $eq $eq$ls180.v:6226$1789 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272518,10 +270663,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6420$1930_Y + connect \Y $eq$ls180.v:6226$1789_Y end - attribute \src "ls180.v:6422.102-6422.146" - cell $eq $eq$ls180.v:6422$1933 + attribute \src "ls180.v:6228.102-6228.146" + cell $eq $eq$ls180.v:6228$1792 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272529,10 +270674,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6422$1933_Y + connect \Y $eq$ls180.v:6228$1792_Y end - attribute \src "ls180.v:6423.105-6423.149" - cell $eq $eq$ls180.v:6423$1937 + attribute \src "ls180.v:6229.105-6229.149" + cell $eq $eq$ls180.v:6229$1796 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272540,10 +270685,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6423$1937_Y + connect \Y $eq$ls180.v:6229$1796_Y end - attribute \src "ls180.v:6425.102-6425.147" - cell $eq $eq$ls180.v:6425$1940 + attribute \src "ls180.v:6231.102-6231.147" + cell $eq $eq$ls180.v:6231$1799 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272551,10 +270696,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6425$1940_Y + connect \Y $eq$ls180.v:6231$1799_Y end - attribute \src "ls180.v:6426.105-6426.150" - cell $eq $eq$ls180.v:6426$1944 + attribute \src "ls180.v:6232.105-6232.150" + cell $eq $eq$ls180.v:6232$1803 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272562,10 +270707,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6426$1944_Y + connect \Y $eq$ls180.v:6232$1803_Y end - attribute \src "ls180.v:6428.102-6428.147" - cell $eq $eq$ls180.v:6428$1947 + attribute \src "ls180.v:6234.102-6234.147" + cell $eq $eq$ls180.v:6234$1806 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272573,10 +270718,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6428$1947_Y + connect \Y $eq$ls180.v:6234$1806_Y end - attribute \src "ls180.v:6429.105-6429.150" - cell $eq $eq$ls180.v:6429$1951 + attribute \src "ls180.v:6235.105-6235.150" + cell $eq $eq$ls180.v:6235$1810 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272584,10 +270729,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6429$1951_Y + connect \Y $eq$ls180.v:6235$1810_Y end - attribute \src "ls180.v:6431.102-6431.147" - cell $eq $eq$ls180.v:6431$1954 + attribute \src "ls180.v:6237.102-6237.147" + cell $eq $eq$ls180.v:6237$1813 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272595,10 +270740,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6431$1954_Y + connect \Y $eq$ls180.v:6237$1813_Y end - attribute \src "ls180.v:6432.105-6432.150" - cell $eq $eq$ls180.v:6432$1958 + attribute \src "ls180.v:6238.105-6238.150" + cell $eq $eq$ls180.v:6238$1817 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272606,10 +270751,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6432$1958_Y + connect \Y $eq$ls180.v:6238$1817_Y end - attribute \src "ls180.v:6434.99-6434.144" - cell $eq $eq$ls180.v:6434$1961 + attribute \src "ls180.v:6240.99-6240.144" + cell $eq $eq$ls180.v:6240$1820 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272617,10 +270762,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6434$1961_Y + connect \Y $eq$ls180.v:6240$1820_Y end - attribute \src "ls180.v:6435.102-6435.147" - cell $eq $eq$ls180.v:6435$1965 + attribute \src "ls180.v:6241.102-6241.147" + cell $eq $eq$ls180.v:6241$1824 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272628,10 +270773,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6435$1965_Y + connect \Y $eq$ls180.v:6241$1824_Y end - attribute \src "ls180.v:6437.100-6437.145" - cell $eq $eq$ls180.v:6437$1968 + attribute \src "ls180.v:6243.100-6243.145" + cell $eq $eq$ls180.v:6243$1827 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272639,10 +270784,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6437$1968_Y + connect \Y $eq$ls180.v:6243$1827_Y end - attribute \src "ls180.v:6438.103-6438.148" - cell $eq $eq$ls180.v:6438$1972 + attribute \src "ls180.v:6244.103-6244.148" + cell $eq $eq$ls180.v:6244$1831 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272650,10 +270795,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6438$1972_Y + connect \Y $eq$ls180.v:6244$1831_Y end - attribute \src "ls180.v:6440.102-6440.147" - cell $eq $eq$ls180.v:6440$1975 + attribute \src "ls180.v:6246.102-6246.147" + cell $eq $eq$ls180.v:6246$1834 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272661,10 +270806,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6440$1975_Y + connect \Y $eq$ls180.v:6246$1834_Y end - attribute \src "ls180.v:6441.105-6441.150" - cell $eq $eq$ls180.v:6441$1979 + attribute \src "ls180.v:6247.105-6247.150" + cell $eq $eq$ls180.v:6247$1838 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272672,10 +270817,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6441$1979_Y + connect \Y $eq$ls180.v:6247$1838_Y end - attribute \src "ls180.v:6443.102-6443.147" - cell $eq $eq$ls180.v:6443$1982 + attribute \src "ls180.v:6249.102-6249.147" + cell $eq $eq$ls180.v:6249$1841 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272683,10 +270828,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6443$1982_Y + connect \Y $eq$ls180.v:6249$1841_Y end - attribute \src "ls180.v:6444.105-6444.150" - cell $eq $eq$ls180.v:6444$1986 + attribute \src "ls180.v:6250.105-6250.150" + cell $eq $eq$ls180.v:6250$1845 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272694,10 +270839,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6444$1986_Y + connect \Y $eq$ls180.v:6250$1845_Y end - attribute \src "ls180.v:6446.102-6446.147" - cell $eq $eq$ls180.v:6446$1989 + attribute \src "ls180.v:6252.102-6252.147" + cell $eq $eq$ls180.v:6252$1848 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272705,10 +270850,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6446$1989_Y + connect \Y $eq$ls180.v:6252$1848_Y end - attribute \src "ls180.v:6447.105-6447.150" - cell $eq $eq$ls180.v:6447$1993 + attribute \src "ls180.v:6253.105-6253.150" + cell $eq $eq$ls180.v:6253$1852 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272716,10 +270861,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10001 - connect \Y $eq$ls180.v:6447$1993_Y + connect \Y $eq$ls180.v:6253$1852_Y end - attribute \src "ls180.v:6449.102-6449.147" - cell $eq $eq$ls180.v:6449$1996 + attribute \src "ls180.v:6255.102-6255.147" + cell $eq $eq$ls180.v:6255$1855 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272727,10 +270872,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6449$1996_Y + connect \Y $eq$ls180.v:6255$1855_Y end - attribute \src "ls180.v:6450.105-6450.150" - cell $eq $eq$ls180.v:6450$2000 + attribute \src "ls180.v:6256.105-6256.150" + cell $eq $eq$ls180.v:6256$1859 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -272738,10 +270883,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_adr [4:0] connect \B 5'10010 - connect \Y $eq$ls180.v:6450$2000_Y + connect \Y $eq$ls180.v:6256$1859_Y end - attribute \src "ls180.v:6472.32-6472.78" - cell $eq $eq$ls180.v:6472$2002 + attribute \src "ls180.v:6278.32-6278.78" + cell $eq $eq$ls180.v:6278$1861 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272749,10 +270894,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [13:8] connect \B 4'1101 - connect \Y $eq$ls180.v:6472$2002_Y + connect \Y $eq$ls180.v:6278$1861_Y end - attribute \src "ls180.v:6474.102-6474.146" - cell $eq $eq$ls180.v:6474$2004 + attribute \src "ls180.v:6280.102-6280.146" + cell $eq $eq$ls180.v:6280$1863 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -272760,10 +270905,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6474$2004_Y + connect \Y $eq$ls180.v:6280$1863_Y end - attribute \src "ls180.v:6475.105-6475.149" - cell $eq $eq$ls180.v:6475$2008 + attribute \src "ls180.v:6281.105-6281.149" + cell $eq $eq$ls180.v:6281$1867 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -272771,10 +270916,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6475$2008_Y + connect \Y $eq$ls180.v:6281$1867_Y end - attribute \src "ls180.v:6477.107-6477.151" - cell $eq $eq$ls180.v:6477$2011 + attribute \src "ls180.v:6283.107-6283.151" + cell $eq $eq$ls180.v:6283$1870 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -272782,10 +270927,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6477$2011_Y + connect \Y $eq$ls180.v:6283$1870_Y end - attribute \src "ls180.v:6478.110-6478.154" - cell $eq $eq$ls180.v:6478$2015 + attribute \src "ls180.v:6284.110-6284.154" + cell $eq $eq$ls180.v:6284$1874 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -272793,10 +270938,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6478$2015_Y + connect \Y $eq$ls180.v:6284$1874_Y end - attribute \src "ls180.v:6480.107-6480.151" - cell $eq $eq$ls180.v:6480$2018 + attribute \src "ls180.v:6286.107-6286.151" + cell $eq $eq$ls180.v:6286$1877 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -272804,10 +270949,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6480$2018_Y + connect \Y $eq$ls180.v:6286$1877_Y end - attribute \src "ls180.v:6481.110-6481.154" - cell $eq $eq$ls180.v:6481$2022 + attribute \src "ls180.v:6287.110-6287.154" + cell $eq $eq$ls180.v:6287$1881 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -272815,10 +270960,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6481$2022_Y + connect \Y $eq$ls180.v:6287$1881_Y end - attribute \src "ls180.v:6483.100-6483.144" - cell $eq $eq$ls180.v:6483$2025 + attribute \src "ls180.v:6289.100-6289.144" + cell $eq $eq$ls180.v:6289$1884 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -272826,10 +270971,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6483$2025_Y + connect \Y $eq$ls180.v:6289$1884_Y end - attribute \src "ls180.v:6484.103-6484.147" - cell $eq $eq$ls180.v:6484$2029 + attribute \src "ls180.v:6290.103-6290.147" + cell $eq $eq$ls180.v:6290$1888 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -272837,10 +270982,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6484$2029_Y + connect \Y $eq$ls180.v:6290$1888_Y end - attribute \src "ls180.v:6489.32-6489.77" - cell $eq $eq$ls180.v:6489$2031 + attribute \src "ls180.v:6295.32-6295.77" + cell $eq $eq$ls180.v:6295$1890 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -272848,10 +270993,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [13:8] connect \B 2'11 - connect \Y $eq$ls180.v:6489$2031_Y + connect \Y $eq$ls180.v:6295$1890_Y end - attribute \src "ls180.v:6491.104-6491.148" - cell $eq $eq$ls180.v:6491$2033 + attribute \src "ls180.v:6297.104-6297.148" + cell $eq $eq$ls180.v:6297$1892 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -272859,10 +271004,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6491$2033_Y + connect \Y $eq$ls180.v:6297$1892_Y end - attribute \src "ls180.v:6492.107-6492.151" - cell $eq $eq$ls180.v:6492$2037 + attribute \src "ls180.v:6298.107-6298.151" + cell $eq $eq$ls180.v:6298$1896 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -272870,10 +271015,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6492$2037_Y + connect \Y $eq$ls180.v:6298$1896_Y end - attribute \src "ls180.v:6494.108-6494.152" - cell $eq $eq$ls180.v:6494$2040 + attribute \src "ls180.v:6300.108-6300.152" + cell $eq $eq$ls180.v:6300$1899 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -272881,10 +271026,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6494$2040_Y + connect \Y $eq$ls180.v:6300$1899_Y end - attribute \src "ls180.v:6495.111-6495.155" - cell $eq $eq$ls180.v:6495$2044 + attribute \src "ls180.v:6301.111-6301.155" + cell $eq $eq$ls180.v:6301$1903 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -272892,10 +271037,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6495$2044_Y + connect \Y $eq$ls180.v:6301$1903_Y end - attribute \src "ls180.v:6497.98-6497.142" - cell $eq $eq$ls180.v:6497$2047 + attribute \src "ls180.v:6303.98-6303.142" + cell $eq $eq$ls180.v:6303$1906 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -272903,10 +271048,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6497$2047_Y + connect \Y $eq$ls180.v:6303$1906_Y end - attribute \src "ls180.v:6498.101-6498.145" - cell $eq $eq$ls180.v:6498$2051 + attribute \src "ls180.v:6304.101-6304.145" + cell $eq $eq$ls180.v:6304$1910 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -272914,10 +271059,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6498$2051_Y + connect \Y $eq$ls180.v:6304$1910_Y end - attribute \src "ls180.v:6500.108-6500.152" - cell $eq $eq$ls180.v:6500$2054 + attribute \src "ls180.v:6306.108-6306.152" + cell $eq $eq$ls180.v:6306$1913 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -272925,10 +271070,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6500$2054_Y + connect \Y $eq$ls180.v:6306$1913_Y end - attribute \src "ls180.v:6501.111-6501.155" - cell $eq $eq$ls180.v:6501$2058 + attribute \src "ls180.v:6307.111-6307.155" + cell $eq $eq$ls180.v:6307$1917 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -272936,10 +271081,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6501$2058_Y + connect \Y $eq$ls180.v:6307$1917_Y end - attribute \src "ls180.v:6503.108-6503.152" - cell $eq $eq$ls180.v:6503$2061 + attribute \src "ls180.v:6309.108-6309.152" + cell $eq $eq$ls180.v:6309$1920 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -272947,10 +271092,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6503$2061_Y + connect \Y $eq$ls180.v:6309$1920_Y end - attribute \src "ls180.v:6504.111-6504.155" - cell $eq $eq$ls180.v:6504$2065 + attribute \src "ls180.v:6310.111-6310.155" + cell $eq $eq$ls180.v:6310$1924 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -272958,10 +271103,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6504$2065_Y + connect \Y $eq$ls180.v:6310$1924_Y end - attribute \src "ls180.v:6506.109-6506.153" - cell $eq $eq$ls180.v:6506$2068 + attribute \src "ls180.v:6312.109-6312.153" + cell $eq $eq$ls180.v:6312$1927 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -272969,10 +271114,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6506$2068_Y + connect \Y $eq$ls180.v:6312$1927_Y end - attribute \src "ls180.v:6507.112-6507.156" - cell $eq $eq$ls180.v:6507$2072 + attribute \src "ls180.v:6313.112-6313.156" + cell $eq $eq$ls180.v:6313$1931 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -272980,10 +271125,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6507$2072_Y + connect \Y $eq$ls180.v:6313$1931_Y end - attribute \src "ls180.v:6509.107-6509.151" - cell $eq $eq$ls180.v:6509$2075 + attribute \src "ls180.v:6315.107-6315.151" + cell $eq $eq$ls180.v:6315$1934 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -272991,10 +271136,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6509$2075_Y + connect \Y $eq$ls180.v:6315$1934_Y end - attribute \src "ls180.v:6510.110-6510.154" - cell $eq $eq$ls180.v:6510$2079 + attribute \src "ls180.v:6316.110-6316.154" + cell $eq $eq$ls180.v:6316$1938 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273002,10 +271147,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6510$2079_Y + connect \Y $eq$ls180.v:6316$1938_Y end - attribute \src "ls180.v:6512.107-6512.151" - cell $eq $eq$ls180.v:6512$2082 + attribute \src "ls180.v:6318.107-6318.151" + cell $eq $eq$ls180.v:6318$1941 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273013,10 +271158,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6512$2082_Y + connect \Y $eq$ls180.v:6318$1941_Y end - attribute \src "ls180.v:6513.110-6513.154" - cell $eq $eq$ls180.v:6513$2086 + attribute \src "ls180.v:6319.110-6319.154" + cell $eq $eq$ls180.v:6319$1945 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273024,10 +271169,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6513$2086_Y + connect \Y $eq$ls180.v:6319$1945_Y end - attribute \src "ls180.v:6515.107-6515.151" - cell $eq $eq$ls180.v:6515$2089 + attribute \src "ls180.v:6321.107-6321.151" + cell $eq $eq$ls180.v:6321$1948 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273035,10 +271180,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6515$2089_Y + connect \Y $eq$ls180.v:6321$1948_Y end - attribute \src "ls180.v:6516.110-6516.154" - cell $eq $eq$ls180.v:6516$2093 + attribute \src "ls180.v:6322.110-6322.154" + cell $eq $eq$ls180.v:6322$1952 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273046,10 +271191,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6516$2093_Y + connect \Y $eq$ls180.v:6322$1952_Y end - attribute \src "ls180.v:6518.107-6518.151" - cell $eq $eq$ls180.v:6518$2096 + attribute \src "ls180.v:6324.107-6324.151" + cell $eq $eq$ls180.v:6324$1955 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273057,10 +271202,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6518$2096_Y + connect \Y $eq$ls180.v:6324$1955_Y end - attribute \src "ls180.v:6519.110-6519.154" - cell $eq $eq$ls180.v:6519$2100 + attribute \src "ls180.v:6325.110-6325.154" + cell $eq $eq$ls180.v:6325$1959 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273068,10 +271213,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_adr [3:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6519$2100_Y + connect \Y $eq$ls180.v:6325$1959_Y end - attribute \src "ls180.v:6534.33-6534.79" - cell $eq $eq$ls180.v:6534$2102 + attribute \src "ls180.v:6340.33-6340.79" + cell $eq $eq$ls180.v:6340$1961 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -273079,10 +271224,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [13:8] connect \B 4'1000 - connect \Y $eq$ls180.v:6534$2102_Y + connect \Y $eq$ls180.v:6340$1961_Y end - attribute \src "ls180.v:6536.102-6536.147" - cell $eq $eq$ls180.v:6536$2104 + attribute \src "ls180.v:6342.102-6342.147" + cell $eq $eq$ls180.v:6342$1963 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273090,10 +271235,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6536$2104_Y + connect \Y $eq$ls180.v:6342$1963_Y end - attribute \src "ls180.v:6537.105-6537.150" - cell $eq $eq$ls180.v:6537$2108 + attribute \src "ls180.v:6343.105-6343.150" + cell $eq $eq$ls180.v:6343$1967 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273101,10 +271246,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6537$2108_Y + connect \Y $eq$ls180.v:6343$1967_Y end - attribute \src "ls180.v:6539.102-6539.147" - cell $eq $eq$ls180.v:6539$2111 + attribute \src "ls180.v:6345.102-6345.147" + cell $eq $eq$ls180.v:6345$1970 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273112,10 +271257,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6539$2111_Y + connect \Y $eq$ls180.v:6345$1970_Y end - attribute \src "ls180.v:6540.105-6540.150" - cell $eq $eq$ls180.v:6540$2115 + attribute \src "ls180.v:6346.105-6346.150" + cell $eq $eq$ls180.v:6346$1974 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273123,10 +271268,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6540$2115_Y + connect \Y $eq$ls180.v:6346$1974_Y end - attribute \src "ls180.v:6542.100-6542.145" - cell $eq $eq$ls180.v:6542$2118 + attribute \src "ls180.v:6348.100-6348.145" + cell $eq $eq$ls180.v:6348$1977 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273134,10 +271279,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6542$2118_Y + connect \Y $eq$ls180.v:6348$1977_Y end - attribute \src "ls180.v:6543.103-6543.148" - cell $eq $eq$ls180.v:6543$2122 + attribute \src "ls180.v:6349.103-6349.148" + cell $eq $eq$ls180.v:6349$1981 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273145,10 +271290,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6543$2122_Y + connect \Y $eq$ls180.v:6349$1981_Y end - attribute \src "ls180.v:6545.99-6545.144" - cell $eq $eq$ls180.v:6545$2125 + attribute \src "ls180.v:6351.99-6351.144" + cell $eq $eq$ls180.v:6351$1984 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273156,10 +271301,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6545$2125_Y + connect \Y $eq$ls180.v:6351$1984_Y end - attribute \src "ls180.v:6546.102-6546.147" - cell $eq $eq$ls180.v:6546$2129 + attribute \src "ls180.v:6352.102-6352.147" + cell $eq $eq$ls180.v:6352$1988 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273167,10 +271312,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6546$2129_Y + connect \Y $eq$ls180.v:6352$1988_Y end - attribute \src "ls180.v:6548.98-6548.143" - cell $eq $eq$ls180.v:6548$2132 + attribute \src "ls180.v:6354.98-6354.143" + cell $eq $eq$ls180.v:6354$1991 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273178,10 +271323,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6548$2132_Y + connect \Y $eq$ls180.v:6354$1991_Y end - attribute \src "ls180.v:6549.101-6549.146" - cell $eq $eq$ls180.v:6549$2136 + attribute \src "ls180.v:6355.101-6355.146" + cell $eq $eq$ls180.v:6355$1995 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273189,10 +271334,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6549$2136_Y + connect \Y $eq$ls180.v:6355$1995_Y end - attribute \src "ls180.v:6551.97-6551.142" - cell $eq $eq$ls180.v:6551$2139 + attribute \src "ls180.v:6357.97-6357.142" + cell $eq $eq$ls180.v:6357$1998 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273200,10 +271345,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6551$2139_Y + connect \Y $eq$ls180.v:6357$1998_Y end - attribute \src "ls180.v:6552.100-6552.145" - cell $eq $eq$ls180.v:6552$2143 + attribute \src "ls180.v:6358.100-6358.145" + cell $eq $eq$ls180.v:6358$2002 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273211,10 +271356,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6552$2143_Y + connect \Y $eq$ls180.v:6358$2002_Y end - attribute \src "ls180.v:6554.103-6554.148" - cell $eq $eq$ls180.v:6554$2146 + attribute \src "ls180.v:6360.103-6360.148" + cell $eq $eq$ls180.v:6360$2005 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273222,10 +271367,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6554$2146_Y + connect \Y $eq$ls180.v:6360$2005_Y end - attribute \src "ls180.v:6555.106-6555.151" - cell $eq $eq$ls180.v:6555$2150 + attribute \src "ls180.v:6361.106-6361.151" + cell $eq $eq$ls180.v:6361$2009 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273233,10 +271378,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6555$2150_Y + connect \Y $eq$ls180.v:6361$2009_Y end - attribute \src "ls180.v:6574.33-6574.79" - cell $eq $eq$ls180.v:6574$2153 + attribute \src "ls180.v:6380.33-6380.79" + cell $eq $eq$ls180.v:6380$2012 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -273244,10 +271389,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [13:8] connect \B 4'1001 - connect \Y $eq$ls180.v:6574$2153_Y + connect \Y $eq$ls180.v:6380$2012_Y end - attribute \src "ls180.v:6576.102-6576.147" - cell $eq $eq$ls180.v:6576$2155 + attribute \src "ls180.v:6382.102-6382.147" + cell $eq $eq$ls180.v:6382$2014 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273255,10 +271400,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6576$2155_Y + connect \Y $eq$ls180.v:6382$2014_Y end - attribute \src "ls180.v:6577.105-6577.150" - cell $eq $eq$ls180.v:6577$2159 + attribute \src "ls180.v:6383.105-6383.150" + cell $eq $eq$ls180.v:6383$2018 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273266,10 +271411,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'0 - connect \Y $eq$ls180.v:6577$2159_Y + connect \Y $eq$ls180.v:6383$2018_Y end - attribute \src "ls180.v:6579.102-6579.147" - cell $eq $eq$ls180.v:6579$2162 + attribute \src "ls180.v:6385.102-6385.147" + cell $eq $eq$ls180.v:6385$2021 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273277,10 +271422,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6579$2162_Y + connect \Y $eq$ls180.v:6385$2021_Y end - attribute \src "ls180.v:6580.105-6580.150" - cell $eq $eq$ls180.v:6580$2166 + attribute \src "ls180.v:6386.105-6386.150" + cell $eq $eq$ls180.v:6386$2025 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273288,10 +271433,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 1'1 - connect \Y $eq$ls180.v:6580$2166_Y + connect \Y $eq$ls180.v:6386$2025_Y end - attribute \src "ls180.v:6582.100-6582.145" - cell $eq $eq$ls180.v:6582$2169 + attribute \src "ls180.v:6388.100-6388.145" + cell $eq $eq$ls180.v:6388$2028 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273299,10 +271444,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6582$2169_Y + connect \Y $eq$ls180.v:6388$2028_Y end - attribute \src "ls180.v:6583.103-6583.148" - cell $eq $eq$ls180.v:6583$2173 + attribute \src "ls180.v:6389.103-6389.148" + cell $eq $eq$ls180.v:6389$2032 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273310,10 +271455,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'10 - connect \Y $eq$ls180.v:6583$2173_Y + connect \Y $eq$ls180.v:6389$2032_Y end - attribute \src "ls180.v:6585.99-6585.144" - cell $eq $eq$ls180.v:6585$2176 + attribute \src "ls180.v:6391.99-6391.144" + cell $eq $eq$ls180.v:6391$2035 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273321,10 +271466,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6585$2176_Y + connect \Y $eq$ls180.v:6391$2035_Y end - attribute \src "ls180.v:6586.102-6586.147" - cell $eq $eq$ls180.v:6586$2180 + attribute \src "ls180.v:6392.102-6392.147" + cell $eq $eq$ls180.v:6392$2039 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273332,10 +271477,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 2'11 - connect \Y $eq$ls180.v:6586$2180_Y + connect \Y $eq$ls180.v:6392$2039_Y end - attribute \src "ls180.v:6588.98-6588.143" - cell $eq $eq$ls180.v:6588$2183 + attribute \src "ls180.v:6394.98-6394.143" + cell $eq $eq$ls180.v:6394$2042 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273343,10 +271488,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6588$2183_Y + connect \Y $eq$ls180.v:6394$2042_Y end - attribute \src "ls180.v:6589.101-6589.146" - cell $eq $eq$ls180.v:6589$2187 + attribute \src "ls180.v:6395.101-6395.146" + cell $eq $eq$ls180.v:6395$2046 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273354,10 +271499,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'100 - connect \Y $eq$ls180.v:6589$2187_Y + connect \Y $eq$ls180.v:6395$2046_Y end - attribute \src "ls180.v:6591.97-6591.142" - cell $eq $eq$ls180.v:6591$2190 + attribute \src "ls180.v:6397.97-6397.142" + cell $eq $eq$ls180.v:6397$2049 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273365,10 +271510,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6591$2190_Y + connect \Y $eq$ls180.v:6397$2049_Y end - attribute \src "ls180.v:6592.100-6592.145" - cell $eq $eq$ls180.v:6592$2194 + attribute \src "ls180.v:6398.100-6398.145" + cell $eq $eq$ls180.v:6398$2053 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273376,10 +271521,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'101 - connect \Y $eq$ls180.v:6592$2194_Y + connect \Y $eq$ls180.v:6398$2053_Y end - attribute \src "ls180.v:6594.103-6594.148" - cell $eq $eq$ls180.v:6594$2197 + attribute \src "ls180.v:6400.103-6400.148" + cell $eq $eq$ls180.v:6400$2056 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273387,10 +271532,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6594$2197_Y + connect \Y $eq$ls180.v:6400$2056_Y end - attribute \src "ls180.v:6595.106-6595.151" - cell $eq $eq$ls180.v:6595$2201 + attribute \src "ls180.v:6401.106-6401.151" + cell $eq $eq$ls180.v:6401$2060 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273398,10 +271543,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'110 - connect \Y $eq$ls180.v:6595$2201_Y + connect \Y $eq$ls180.v:6401$2060_Y end - attribute \src "ls180.v:6597.106-6597.151" - cell $eq $eq$ls180.v:6597$2204 + attribute \src "ls180.v:6403.106-6403.151" + cell $eq $eq$ls180.v:6403$2063 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273409,10 +271554,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6597$2204_Y + connect \Y $eq$ls180.v:6403$2063_Y end - attribute \src "ls180.v:6598.109-6598.154" - cell $eq $eq$ls180.v:6598$2208 + attribute \src "ls180.v:6404.109-6404.154" + cell $eq $eq$ls180.v:6404$2067 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273420,10 +271565,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 3'111 - connect \Y $eq$ls180.v:6598$2208_Y + connect \Y $eq$ls180.v:6404$2067_Y end - attribute \src "ls180.v:6600.106-6600.151" - cell $eq $eq$ls180.v:6600$2211 + attribute \src "ls180.v:6406.106-6406.151" + cell $eq $eq$ls180.v:6406$2070 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273431,10 +271576,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6600$2211_Y + connect \Y $eq$ls180.v:6406$2070_Y end - attribute \src "ls180.v:6601.109-6601.154" - cell $eq $eq$ls180.v:6601$2215 + attribute \src "ls180.v:6407.109-6407.154" + cell $eq $eq$ls180.v:6407$2074 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -273442,10 +271587,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_adr [3:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6601$2215_Y + connect \Y $eq$ls180.v:6407$2074_Y end - attribute \src "ls180.v:6622.33-6622.79" - cell $eq $eq$ls180.v:6622$2218 + attribute \src "ls180.v:6428.33-6428.79" + cell $eq $eq$ls180.v:6428$2077 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -273453,10 +271598,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [13:8] connect \B 2'10 - connect \Y $eq$ls180.v:6622$2218_Y + connect \Y $eq$ls180.v:6428$2077_Y end - attribute \src "ls180.v:6624.99-6624.144" - cell $eq $eq$ls180.v:6624$2220 + attribute \src "ls180.v:6430.99-6430.144" + cell $eq $eq$ls180.v:6430$2079 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273464,10 +271609,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6624$2220_Y + connect \Y $eq$ls180.v:6430$2079_Y end - attribute \src "ls180.v:6625.102-6625.147" - cell $eq $eq$ls180.v:6625$2224 + attribute \src "ls180.v:6431.102-6431.147" + cell $eq $eq$ls180.v:6431$2083 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273475,10 +271620,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'0 - connect \Y $eq$ls180.v:6625$2224_Y + connect \Y $eq$ls180.v:6431$2083_Y end - attribute \src "ls180.v:6627.99-6627.144" - cell $eq $eq$ls180.v:6627$2227 + attribute \src "ls180.v:6433.99-6433.144" + cell $eq $eq$ls180.v:6433$2086 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273486,10 +271631,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6627$2227_Y + connect \Y $eq$ls180.v:6433$2086_Y end - attribute \src "ls180.v:6628.102-6628.147" - cell $eq $eq$ls180.v:6628$2231 + attribute \src "ls180.v:6434.102-6434.147" + cell $eq $eq$ls180.v:6434$2090 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273497,10 +271642,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 1'1 - connect \Y $eq$ls180.v:6628$2231_Y + connect \Y $eq$ls180.v:6434$2090_Y end - attribute \src "ls180.v:6630.99-6630.144" - cell $eq $eq$ls180.v:6630$2234 + attribute \src "ls180.v:6436.99-6436.144" + cell $eq $eq$ls180.v:6436$2093 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273508,10 +271653,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6630$2234_Y + connect \Y $eq$ls180.v:6436$2093_Y end - attribute \src "ls180.v:6631.102-6631.147" - cell $eq $eq$ls180.v:6631$2238 + attribute \src "ls180.v:6437.102-6437.147" + cell $eq $eq$ls180.v:6437$2097 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273519,10 +271664,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'10 - connect \Y $eq$ls180.v:6631$2238_Y + connect \Y $eq$ls180.v:6437$2097_Y end - attribute \src "ls180.v:6633.99-6633.144" - cell $eq $eq$ls180.v:6633$2241 + attribute \src "ls180.v:6439.99-6439.144" + cell $eq $eq$ls180.v:6439$2100 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273530,10 +271675,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6633$2241_Y + connect \Y $eq$ls180.v:6439$2100_Y end - attribute \src "ls180.v:6634.102-6634.147" - cell $eq $eq$ls180.v:6634$2245 + attribute \src "ls180.v:6440.102-6440.147" + cell $eq $eq$ls180.v:6440$2104 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273541,10 +271686,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 2'11 - connect \Y $eq$ls180.v:6634$2245_Y + connect \Y $eq$ls180.v:6440$2104_Y end - attribute \src "ls180.v:6636.101-6636.146" - cell $eq $eq$ls180.v:6636$2248 + attribute \src "ls180.v:6442.101-6442.146" + cell $eq $eq$ls180.v:6442$2107 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273552,10 +271697,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6636$2248_Y + connect \Y $eq$ls180.v:6442$2107_Y end - attribute \src "ls180.v:6637.104-6637.149" - cell $eq $eq$ls180.v:6637$2252 + attribute \src "ls180.v:6443.104-6443.149" + cell $eq $eq$ls180.v:6443$2111 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273563,10 +271708,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'100 - connect \Y $eq$ls180.v:6637$2252_Y + connect \Y $eq$ls180.v:6443$2111_Y end - attribute \src "ls180.v:6639.101-6639.146" - cell $eq $eq$ls180.v:6639$2255 + attribute \src "ls180.v:6445.101-6445.146" + cell $eq $eq$ls180.v:6445$2114 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273574,10 +271719,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6639$2255_Y + connect \Y $eq$ls180.v:6445$2114_Y end - attribute \src "ls180.v:6640.104-6640.149" - cell $eq $eq$ls180.v:6640$2259 + attribute \src "ls180.v:6446.104-6446.149" + cell $eq $eq$ls180.v:6446$2118 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273585,10 +271730,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'101 - connect \Y $eq$ls180.v:6640$2259_Y + connect \Y $eq$ls180.v:6446$2118_Y end - attribute \src "ls180.v:6642.101-6642.146" - cell $eq $eq$ls180.v:6642$2262 + attribute \src "ls180.v:6448.101-6448.146" + cell $eq $eq$ls180.v:6448$2121 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273596,10 +271741,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6642$2262_Y + connect \Y $eq$ls180.v:6448$2121_Y end - attribute \src "ls180.v:6643.104-6643.149" - cell $eq $eq$ls180.v:6643$2266 + attribute \src "ls180.v:6449.104-6449.149" + cell $eq $eq$ls180.v:6449$2125 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273607,10 +271752,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'110 - connect \Y $eq$ls180.v:6643$2266_Y + connect \Y $eq$ls180.v:6449$2125_Y end - attribute \src "ls180.v:6645.101-6645.146" - cell $eq $eq$ls180.v:6645$2269 + attribute \src "ls180.v:6451.101-6451.146" + cell $eq $eq$ls180.v:6451$2128 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273618,10 +271763,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6645$2269_Y + connect \Y $eq$ls180.v:6451$2128_Y end - attribute \src "ls180.v:6646.104-6646.149" - cell $eq $eq$ls180.v:6646$2273 + attribute \src "ls180.v:6452.104-6452.149" + cell $eq $eq$ls180.v:6452$2132 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273629,10 +271774,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 3'111 - connect \Y $eq$ls180.v:6646$2273_Y + connect \Y $eq$ls180.v:6452$2132_Y end - attribute \src "ls180.v:6648.97-6648.142" - cell $eq $eq$ls180.v:6648$2276 + attribute \src "ls180.v:6454.97-6454.142" + cell $eq $eq$ls180.v:6454$2135 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273640,10 +271785,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6648$2276_Y + connect \Y $eq$ls180.v:6454$2135_Y end - attribute \src "ls180.v:6649.100-6649.145" - cell $eq $eq$ls180.v:6649$2280 + attribute \src "ls180.v:6455.100-6455.145" + cell $eq $eq$ls180.v:6455$2139 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273651,10 +271796,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1000 - connect \Y $eq$ls180.v:6649$2280_Y + connect \Y $eq$ls180.v:6455$2139_Y end - attribute \src "ls180.v:6651.107-6651.152" - cell $eq $eq$ls180.v:6651$2283 + attribute \src "ls180.v:6457.107-6457.152" + cell $eq $eq$ls180.v:6457$2142 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273662,10 +271807,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6651$2283_Y + connect \Y $eq$ls180.v:6457$2142_Y end - attribute \src "ls180.v:6652.110-6652.155" - cell $eq $eq$ls180.v:6652$2287 + attribute \src "ls180.v:6458.110-6458.155" + cell $eq $eq$ls180.v:6458$2146 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273673,10 +271818,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1001 - connect \Y $eq$ls180.v:6652$2287_Y + connect \Y $eq$ls180.v:6458$2146_Y end - attribute \src "ls180.v:6654.100-6654.146" - cell $eq $eq$ls180.v:6654$2290 + attribute \src "ls180.v:6460.100-6460.146" + cell $eq $eq$ls180.v:6460$2149 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273684,10 +271829,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6654$2290_Y + connect \Y $eq$ls180.v:6460$2149_Y end - attribute \src "ls180.v:6655.103-6655.149" - cell $eq $eq$ls180.v:6655$2294 + attribute \src "ls180.v:6461.103-6461.149" + cell $eq $eq$ls180.v:6461$2153 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273695,10 +271840,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1010 - connect \Y $eq$ls180.v:6655$2294_Y + connect \Y $eq$ls180.v:6461$2153_Y end - attribute \src "ls180.v:6657.100-6657.146" - cell $eq $eq$ls180.v:6657$2297 + attribute \src "ls180.v:6463.100-6463.146" + cell $eq $eq$ls180.v:6463$2156 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273706,10 +271851,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6657$2297_Y + connect \Y $eq$ls180.v:6463$2156_Y end - attribute \src "ls180.v:6658.103-6658.149" - cell $eq $eq$ls180.v:6658$2301 + attribute \src "ls180.v:6464.103-6464.149" + cell $eq $eq$ls180.v:6464$2160 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273717,10 +271862,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1011 - connect \Y $eq$ls180.v:6658$2301_Y + connect \Y $eq$ls180.v:6464$2160_Y end - attribute \src "ls180.v:6660.100-6660.146" - cell $eq $eq$ls180.v:6660$2304 + attribute \src "ls180.v:6466.100-6466.146" + cell $eq $eq$ls180.v:6466$2163 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273728,10 +271873,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6660$2304_Y + connect \Y $eq$ls180.v:6466$2163_Y end - attribute \src "ls180.v:6661.103-6661.149" - cell $eq $eq$ls180.v:6661$2308 + attribute \src "ls180.v:6467.103-6467.149" + cell $eq $eq$ls180.v:6467$2167 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273739,10 +271884,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1100 - connect \Y $eq$ls180.v:6661$2308_Y + connect \Y $eq$ls180.v:6467$2167_Y end - attribute \src "ls180.v:6663.100-6663.146" - cell $eq $eq$ls180.v:6663$2311 + attribute \src "ls180.v:6469.100-6469.146" + cell $eq $eq$ls180.v:6469$2170 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273750,10 +271895,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6663$2311_Y + connect \Y $eq$ls180.v:6469$2170_Y end - attribute \src "ls180.v:6664.103-6664.149" - cell $eq $eq$ls180.v:6664$2315 + attribute \src "ls180.v:6470.103-6470.149" + cell $eq $eq$ls180.v:6470$2174 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273761,10 +271906,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1101 - connect \Y $eq$ls180.v:6664$2315_Y + connect \Y $eq$ls180.v:6470$2174_Y end - attribute \src "ls180.v:6666.112-6666.158" - cell $eq $eq$ls180.v:6666$2318 + attribute \src "ls180.v:6472.112-6472.158" + cell $eq $eq$ls180.v:6472$2177 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273772,10 +271917,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6666$2318_Y + connect \Y $eq$ls180.v:6472$2177_Y end - attribute \src "ls180.v:6667.115-6667.161" - cell $eq $eq$ls180.v:6667$2322 + attribute \src "ls180.v:6473.115-6473.161" + cell $eq $eq$ls180.v:6473$2181 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273783,10 +271928,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1110 - connect \Y $eq$ls180.v:6667$2322_Y + connect \Y $eq$ls180.v:6473$2181_Y end - attribute \src "ls180.v:6669.113-6669.159" - cell $eq $eq$ls180.v:6669$2325 + attribute \src "ls180.v:6475.113-6475.159" + cell $eq $eq$ls180.v:6475$2184 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273794,10 +271939,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6669$2325_Y + connect \Y $eq$ls180.v:6475$2184_Y end - attribute \src "ls180.v:6670.116-6670.162" - cell $eq $eq$ls180.v:6670$2329 + attribute \src "ls180.v:6476.116-6476.162" + cell $eq $eq$ls180.v:6476$2188 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273805,10 +271950,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 4'1111 - connect \Y $eq$ls180.v:6670$2329_Y + connect \Y $eq$ls180.v:6476$2188_Y end - attribute \src "ls180.v:6672.104-6672.150" - cell $eq $eq$ls180.v:6672$2332 + attribute \src "ls180.v:6478.104-6478.150" + cell $eq $eq$ls180.v:6478$2191 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273816,10 +271961,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6672$2332_Y + connect \Y $eq$ls180.v:6478$2191_Y end - attribute \src "ls180.v:6673.107-6673.153" - cell $eq $eq$ls180.v:6673$2336 + attribute \src "ls180.v:6479.107-6479.153" + cell $eq $eq$ls180.v:6479$2195 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -273827,10 +271972,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_adr [4:0] connect \B 5'10000 - connect \Y $eq$ls180.v:6673$2336_Y + connect \Y $eq$ls180.v:6479$2195_Y end - attribute \src "ls180.v:6690.33-6690.79" - cell $eq $eq$ls180.v:6690$2338 + attribute \src "ls180.v:6496.33-6496.79" + cell $eq $eq$ls180.v:6496$2197 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -273838,10 +271983,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [13:8] connect \B 3'101 - connect \Y $eq$ls180.v:6690$2338_Y + connect \Y $eq$ls180.v:6496$2197_Y end - attribute \src "ls180.v:6692.90-6692.135" - cell $eq $eq$ls180.v:6692$2340 + attribute \src "ls180.v:6498.90-6498.135" + cell $eq $eq$ls180.v:6498$2199 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273849,10 +271994,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6692$2340_Y + connect \Y $eq$ls180.v:6498$2199_Y end - attribute \src "ls180.v:6693.93-6693.138" - cell $eq $eq$ls180.v:6693$2344 + attribute \src "ls180.v:6499.93-6499.138" + cell $eq $eq$ls180.v:6499$2203 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273860,10 +272005,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'0 - connect \Y $eq$ls180.v:6693$2344_Y + connect \Y $eq$ls180.v:6499$2203_Y end - attribute \src "ls180.v:6695.100-6695.145" - cell $eq $eq$ls180.v:6695$2347 + attribute \src "ls180.v:6501.100-6501.145" + cell $eq $eq$ls180.v:6501$2206 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273871,10 +272016,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6695$2347_Y + connect \Y $eq$ls180.v:6501$2206_Y end - attribute \src "ls180.v:6696.103-6696.148" - cell $eq $eq$ls180.v:6696$2351 + attribute \src "ls180.v:6502.103-6502.148" + cell $eq $eq$ls180.v:6502$2210 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273882,10 +272027,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 1'1 - connect \Y $eq$ls180.v:6696$2351_Y + connect \Y $eq$ls180.v:6502$2210_Y end - attribute \src "ls180.v:6698.101-6698.146" - cell $eq $eq$ls180.v:6698$2354 + attribute \src "ls180.v:6504.101-6504.146" + cell $eq $eq$ls180.v:6504$2213 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273893,10 +272038,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6698$2354_Y + connect \Y $eq$ls180.v:6504$2213_Y end - attribute \src "ls180.v:6699.104-6699.149" - cell $eq $eq$ls180.v:6699$2358 + attribute \src "ls180.v:6505.104-6505.149" + cell $eq $eq$ls180.v:6505$2217 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273904,10 +272049,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'10 - connect \Y $eq$ls180.v:6699$2358_Y + connect \Y $eq$ls180.v:6505$2217_Y end - attribute \src "ls180.v:6701.105-6701.150" - cell $eq $eq$ls180.v:6701$2361 + attribute \src "ls180.v:6507.105-6507.150" + cell $eq $eq$ls180.v:6507$2220 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273915,10 +272060,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6701$2361_Y + connect \Y $eq$ls180.v:6507$2220_Y end - attribute \src "ls180.v:6702.108-6702.153" - cell $eq $eq$ls180.v:6702$2365 + attribute \src "ls180.v:6508.108-6508.153" + cell $eq $eq$ls180.v:6508$2224 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273926,10 +272071,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 2'11 - connect \Y $eq$ls180.v:6702$2365_Y + connect \Y $eq$ls180.v:6508$2224_Y end - attribute \src "ls180.v:6704.106-6704.151" - cell $eq $eq$ls180.v:6704$2368 + attribute \src "ls180.v:6510.106-6510.151" + cell $eq $eq$ls180.v:6510$2227 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273937,10 +272082,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6704$2368_Y + connect \Y $eq$ls180.v:6510$2227_Y end - attribute \src "ls180.v:6705.109-6705.154" - cell $eq $eq$ls180.v:6705$2372 + attribute \src "ls180.v:6511.109-6511.154" + cell $eq $eq$ls180.v:6511$2231 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273948,10 +272093,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'100 - connect \Y $eq$ls180.v:6705$2372_Y + connect \Y $eq$ls180.v:6511$2231_Y end - attribute \src "ls180.v:6707.104-6707.149" - cell $eq $eq$ls180.v:6707$2375 + attribute \src "ls180.v:6513.104-6513.149" + cell $eq $eq$ls180.v:6513$2234 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273959,10 +272104,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6707$2375_Y + connect \Y $eq$ls180.v:6513$2234_Y end - attribute \src "ls180.v:6708.107-6708.152" - cell $eq $eq$ls180.v:6708$2379 + attribute \src "ls180.v:6514.107-6514.152" + cell $eq $eq$ls180.v:6514$2238 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273970,10 +272115,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'101 - connect \Y $eq$ls180.v:6708$2379_Y + connect \Y $eq$ls180.v:6514$2238_Y end - attribute \src "ls180.v:6710.101-6710.146" - cell $eq $eq$ls180.v:6710$2382 + attribute \src "ls180.v:6516.101-6516.146" + cell $eq $eq$ls180.v:6516$2241 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273981,10 +272126,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6710$2382_Y + connect \Y $eq$ls180.v:6516$2241_Y end - attribute \src "ls180.v:6711.104-6711.149" - cell $eq $eq$ls180.v:6711$2386 + attribute \src "ls180.v:6517.104-6517.149" + cell $eq $eq$ls180.v:6517$2245 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -273992,10 +272137,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'110 - connect \Y $eq$ls180.v:6711$2386_Y + connect \Y $eq$ls180.v:6517$2245_Y end - attribute \src "ls180.v:6713.100-6713.145" - cell $eq $eq$ls180.v:6713$2389 + attribute \src "ls180.v:6519.100-6519.145" + cell $eq $eq$ls180.v:6519$2248 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274003,10 +272148,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'111 - connect \Y $eq$ls180.v:6713$2389_Y + connect \Y $eq$ls180.v:6519$2248_Y end - attribute \src "ls180.v:6714.103-6714.148" - cell $eq $eq$ls180.v:6714$2393 + attribute \src "ls180.v:6520.103-6520.148" + cell $eq $eq$ls180.v:6520$2252 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274014,10 +272159,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_adr [2:0] connect \B 3'111 - connect \Y $eq$ls180.v:6714$2393_Y + connect \Y $eq$ls180.v:6520$2252_Y end - attribute \src "ls180.v:6724.33-6724.79" - cell $eq $eq$ls180.v:6724$2395 + attribute \src "ls180.v:6530.33-6530.79" + cell $eq $eq$ls180.v:6530$2254 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -274025,10 +272170,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [13:8] connect \B 3'100 - connect \Y $eq$ls180.v:6724$2395_Y + connect \Y $eq$ls180.v:6530$2254_Y end - attribute \src "ls180.v:6726.106-6726.151" - cell $eq $eq$ls180.v:6726$2397 + attribute \src "ls180.v:6532.106-6532.151" + cell $eq $eq$ls180.v:6532$2256 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -274036,10 +272181,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6726$2397_Y + connect \Y $eq$ls180.v:6532$2256_Y end - attribute \src "ls180.v:6727.109-6727.154" - cell $eq $eq$ls180.v:6727$2401 + attribute \src "ls180.v:6533.109-6533.154" + cell $eq $eq$ls180.v:6533$2260 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -274047,10 +272192,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'0 - connect \Y $eq$ls180.v:6727$2401_Y + connect \Y $eq$ls180.v:6533$2260_Y end - attribute \src "ls180.v:6729.106-6729.151" - cell $eq $eq$ls180.v:6729$2404 + attribute \src "ls180.v:6535.106-6535.151" + cell $eq $eq$ls180.v:6535$2263 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -274058,10 +272203,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6729$2404_Y + connect \Y $eq$ls180.v:6535$2263_Y end - attribute \src "ls180.v:6730.109-6730.154" - cell $eq $eq$ls180.v:6730$2408 + attribute \src "ls180.v:6536.109-6536.154" + cell $eq $eq$ls180.v:6536$2267 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -274069,10 +272214,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 1'1 - connect \Y $eq$ls180.v:6730$2408_Y + connect \Y $eq$ls180.v:6536$2267_Y end - attribute \src "ls180.v:6732.106-6732.151" - cell $eq $eq$ls180.v:6732$2411 + attribute \src "ls180.v:6538.106-6538.151" + cell $eq $eq$ls180.v:6538$2270 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -274080,10 +272225,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6732$2411_Y + connect \Y $eq$ls180.v:6538$2270_Y end - attribute \src "ls180.v:6733.109-6733.154" - cell $eq $eq$ls180.v:6733$2415 + attribute \src "ls180.v:6539.109-6539.154" + cell $eq $eq$ls180.v:6539$2274 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -274091,10 +272236,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'10 - connect \Y $eq$ls180.v:6733$2415_Y + connect \Y $eq$ls180.v:6539$2274_Y end - attribute \src "ls180.v:6735.106-6735.151" - cell $eq $eq$ls180.v:6735$2418 + attribute \src "ls180.v:6541.106-6541.151" + cell $eq $eq$ls180.v:6541$2277 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -274102,10 +272247,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6735$2418_Y + connect \Y $eq$ls180.v:6541$2277_Y end - attribute \src "ls180.v:6736.109-6736.154" - cell $eq $eq$ls180.v:6736$2422 + attribute \src "ls180.v:6542.109-6542.154" + cell $eq $eq$ls180.v:6542$2281 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -274113,10 +272258,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_adr [1:0] connect \B 2'11 - connect \Y $eq$ls180.v:6736$2422_Y + connect \Y $eq$ls180.v:6542$2281_Y end - attribute \src "ls180.v:7117.41-7117.81" - cell $eq $eq$ls180.v:7117$2459 + attribute \src "ls180.v:6923.41-6923.81" + cell $eq $eq$ls180.v:6923$2318 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -274124,10 +272269,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'0 - connect \Y $eq$ls180.v:7117$2459_Y + connect \Y $eq$ls180.v:6923$2318_Y end - attribute \src "ls180.v:7117.144-7117.177" - cell $eq $eq$ls180.v:7117$2460 + attribute \src "ls180.v:6923.144-6923.177" + cell $eq $eq$ls180.v:6923$2319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274135,10 +272280,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:7117$2460_Y + connect \Y $eq$ls180.v:6923$2319_Y end - attribute \src "ls180.v:7117.219-7117.252" - cell $eq $eq$ls180.v:7117$2463 + attribute \src "ls180.v:6923.219-6923.252" + cell $eq $eq$ls180.v:6923$2322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274146,10 +272291,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:7117$2463_Y + connect \Y $eq$ls180.v:6923$2322_Y end - attribute \src "ls180.v:7117.294-7117.327" - cell $eq $eq$ls180.v:7117$2466 + attribute \src "ls180.v:6923.294-6923.327" + cell $eq $eq$ls180.v:6923$2325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274157,10 +272302,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:7117$2466_Y + connect \Y $eq$ls180.v:6923$2325_Y end - attribute \src "ls180.v:7141.41-7141.81" - cell $eq $eq$ls180.v:7141$2475 + attribute \src "ls180.v:6947.41-6947.81" + cell $eq $eq$ls180.v:6947$2334 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -274168,10 +272313,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 1'1 - connect \Y $eq$ls180.v:7141$2475_Y + connect \Y $eq$ls180.v:6947$2334_Y end - attribute \src "ls180.v:7141.144-7141.177" - cell $eq $eq$ls180.v:7141$2476 + attribute \src "ls180.v:6947.144-6947.177" + cell $eq $eq$ls180.v:6947$2335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274179,10 +272324,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:7141$2476_Y + connect \Y $eq$ls180.v:6947$2335_Y end - attribute \src "ls180.v:7141.219-7141.252" - cell $eq $eq$ls180.v:7141$2479 + attribute \src "ls180.v:6947.219-6947.252" + cell $eq $eq$ls180.v:6947$2338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274190,10 +272335,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:7141$2479_Y + connect \Y $eq$ls180.v:6947$2338_Y end - attribute \src "ls180.v:7141.294-7141.327" - cell $eq $eq$ls180.v:7141$2482 + attribute \src "ls180.v:6947.294-6947.327" + cell $eq $eq$ls180.v:6947$2341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274201,10 +272346,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:7141$2482_Y + connect \Y $eq$ls180.v:6947$2341_Y end - attribute \src "ls180.v:7165.41-7165.81" - cell $eq $eq$ls180.v:7165$2491 + attribute \src "ls180.v:6971.41-6971.81" + cell $eq $eq$ls180.v:6971$2350 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -274212,10 +272357,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'10 - connect \Y $eq$ls180.v:7165$2491_Y + connect \Y $eq$ls180.v:6971$2350_Y end - attribute \src "ls180.v:7165.144-7165.177" - cell $eq $eq$ls180.v:7165$2492 + attribute \src "ls180.v:6971.144-6971.177" + cell $eq $eq$ls180.v:6971$2351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274223,10 +272368,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:7165$2492_Y + connect \Y $eq$ls180.v:6971$2351_Y end - attribute \src "ls180.v:7165.219-7165.252" - cell $eq $eq$ls180.v:7165$2495 + attribute \src "ls180.v:6971.219-6971.252" + cell $eq $eq$ls180.v:6971$2354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274234,10 +272379,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:7165$2495_Y + connect \Y $eq$ls180.v:6971$2354_Y end - attribute \src "ls180.v:7165.294-7165.327" - cell $eq $eq$ls180.v:7165$2498 + attribute \src "ls180.v:6971.294-6971.327" + cell $eq $eq$ls180.v:6971$2357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274245,10 +272390,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:7165$2498_Y + connect \Y $eq$ls180.v:6971$2357_Y end - attribute \src "ls180.v:7189.41-7189.81" - cell $eq $eq$ls180.v:7189$2507 + attribute \src "ls180.v:6995.41-6995.81" + cell $eq $eq$ls180.v:6995$2366 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -274256,10 +272401,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_addr [10:9] connect \B 2'11 - connect \Y $eq$ls180.v:7189$2507_Y + connect \Y $eq$ls180.v:6995$2366_Y end - attribute \src "ls180.v:7189.144-7189.177" - cell $eq $eq$ls180.v:7189$2508 + attribute \src "ls180.v:6995.144-6995.177" + cell $eq $eq$ls180.v:6995$2367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274267,10 +272412,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:7189$2508_Y + connect \Y $eq$ls180.v:6995$2367_Y end - attribute \src "ls180.v:7189.219-7189.252" - cell $eq $eq$ls180.v:7189$2511 + attribute \src "ls180.v:6995.219-6995.252" + cell $eq $eq$ls180.v:6995$2370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274278,10 +272423,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:7189$2511_Y + connect \Y $eq$ls180.v:6995$2370_Y end - attribute \src "ls180.v:7189.294-7189.327" - cell $eq $eq$ls180.v:7189$2514 + attribute \src "ls180.v:6995.294-6995.327" + cell $eq $eq$ls180.v:6995$2373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274289,10 +272434,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:7189$2514_Y + connect \Y $eq$ls180.v:6995$2373_Y end - attribute \src "ls180.v:7773.8-7773.38" - cell $eq $eq$ls180.v:7773$2608 + attribute \src "ls180.v:7579.8-7579.38" + cell $eq $eq$ls180.v:7579$2467 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -274300,10 +272445,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_value connect \B 1'0 - connect \Y $eq$ls180.v:7773$2608_Y + connect \Y $eq$ls180.v:7579$2467_Y end - attribute \src "ls180.v:7820.8-7820.42" - cell $eq $eq$ls180.v:7820$2628 + attribute \src "ls180.v:7614.8-7614.42" + cell $eq $eq$ls180.v:7614$2478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274311,10 +272456,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'0 - connect \Y $eq$ls180.v:7820$2628_Y + connect \Y $eq$ls180.v:7614$2478_Y end - attribute \src "ls180.v:7840.38-7840.74" - cell $eq $eq$ls180.v:7840$2631 + attribute \src "ls180.v:7634.38-7634.74" + cell $eq $eq$ls180.v:7634$2481 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274322,10 +272467,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $eq$ls180.v:7840$2631_Y + connect \Y $eq$ls180.v:7634$2481_Y end - attribute \src "ls180.v:7847.7-7847.43" - cell $eq $eq$ls180.v:7847$2633 + attribute \src "ls180.v:7641.7-7641.43" + cell $eq $eq$ls180.v:7641$2483 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274333,10 +272478,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 2'10 - connect \Y $eq$ls180.v:7847$2633_Y + connect \Y $eq$ls180.v:7641$2483_Y end - attribute \src "ls180.v:7854.7-7854.43" - cell $eq $eq$ls180.v:7854$2634 + attribute \src "ls180.v:7648.7-7648.43" + cell $eq $eq$ls180.v:7648$2484 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274344,10 +272489,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7854$2634_Y + connect \Y $eq$ls180.v:7648$2484_Y end - attribute \src "ls180.v:7862.7-7862.43" - cell $eq $eq$ls180.v:7862$2635 + attribute \src "ls180.v:7656.7-7656.43" + cell $eq $eq$ls180.v:7656$2485 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274355,10 +272500,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 4'1000 - connect \Y $eq$ls180.v:7862$2635_Y + connect \Y $eq$ls180.v:7656$2485_Y end - attribute \src "ls180.v:7914.9-7914.54" - cell $eq $eq$ls180.v:7914$2653 + attribute \src "ls180.v:7708.9-7708.54" + cell $eq $eq$ls180.v:7708$2503 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274366,10 +272511,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7914$2653_Y + connect \Y $eq$ls180.v:7708$2503_Y end - attribute \src "ls180.v:7960.9-7960.54" - cell $eq $eq$ls180.v:7960$2669 + attribute \src "ls180.v:7754.9-7754.54" + cell $eq $eq$ls180.v:7754$2519 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274377,10 +272522,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:7960$2669_Y + connect \Y $eq$ls180.v:7754$2519_Y end - attribute \src "ls180.v:8006.9-8006.54" - cell $eq $eq$ls180.v:8006$2685 + attribute \src "ls180.v:7800.9-7800.54" + cell $eq $eq$ls180.v:7800$2535 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274388,10 +272533,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8006$2685_Y + connect \Y $eq$ls180.v:7800$2535_Y end - attribute \src "ls180.v:8052.9-8052.54" - cell $eq $eq$ls180.v:8052$2701 + attribute \src "ls180.v:7846.9-7846.54" + cell $eq $eq$ls180.v:7846$2551 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274399,10 +272544,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8052$2701_Y + connect \Y $eq$ls180.v:7846$2551_Y end - attribute \src "ls180.v:8202.9-8202.41" - cell $eq $eq$ls180.v:8202$2713 + attribute \src "ls180.v:7996.9-7996.41" + cell $eq $eq$ls180.v:7996$2563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274410,10 +272555,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8202$2713_Y + connect \Y $eq$ls180.v:7996$2563_Y end - attribute \src "ls180.v:8217.9-8217.41" - cell $eq $eq$ls180.v:8217$2716 + attribute \src "ls180.v:8011.9-8011.41" + cell $eq $eq$ls180.v:8011$2566 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274421,10 +272566,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $eq$ls180.v:8217$2716_Y + connect \Y $eq$ls180.v:8011$2566_Y end - attribute \src "ls180.v:8223.49-8223.82" - cell $eq $eq$ls180.v:8223$2717 + attribute \src "ls180.v:8017.49-8017.82" + cell $eq $eq$ls180.v:8017$2567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274432,10 +272577,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:8223$2717_Y + connect \Y $eq$ls180.v:8017$2567_Y end - attribute \src "ls180.v:8223.131-8223.164" - cell $eq $eq$ls180.v:8223$2720 + attribute \src "ls180.v:8017.131-8017.164" + cell $eq $eq$ls180.v:8017$2570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274443,10 +272588,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:8223$2720_Y + connect \Y $eq$ls180.v:8017$2570_Y end - attribute \src "ls180.v:8223.213-8223.246" - cell $eq $eq$ls180.v:8223$2723 + attribute \src "ls180.v:8017.213-8017.246" + cell $eq $eq$ls180.v:8017$2573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274454,10 +272599,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:8223$2723_Y + connect \Y $eq$ls180.v:8017$2573_Y end - attribute \src "ls180.v:8223.295-8223.328" - cell $eq $eq$ls180.v:8223$2726 + attribute \src "ls180.v:8017.295-8017.328" + cell $eq $eq$ls180.v:8017$2576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274465,10 +272610,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:8223$2726_Y + connect \Y $eq$ls180.v:8017$2576_Y end - attribute \src "ls180.v:8224.50-8224.83" - cell $eq $eq$ls180.v:8224$2729 + attribute \src "ls180.v:8018.50-8018.83" + cell $eq $eq$ls180.v:8018$2579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274476,10 +272621,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin0_grant connect \B 1'0 - connect \Y $eq$ls180.v:8224$2729_Y + connect \Y $eq$ls180.v:8018$2579_Y end - attribute \src "ls180.v:8224.132-8224.165" - cell $eq $eq$ls180.v:8224$2732 + attribute \src "ls180.v:8018.132-8018.165" + cell $eq $eq$ls180.v:8018$2582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274487,10 +272632,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin1_grant connect \B 1'0 - connect \Y $eq$ls180.v:8224$2732_Y + connect \Y $eq$ls180.v:8018$2582_Y end - attribute \src "ls180.v:8224.214-8224.247" - cell $eq $eq$ls180.v:8224$2735 + attribute \src "ls180.v:8018.214-8018.247" + cell $eq $eq$ls180.v:8018$2585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274498,10 +272643,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin2_grant connect \B 1'0 - connect \Y $eq$ls180.v:8224$2735_Y + connect \Y $eq$ls180.v:8018$2585_Y end - attribute \src "ls180.v:8224.296-8224.329" - cell $eq $eq$ls180.v:8224$2738 + attribute \src "ls180.v:8018.296-8018.329" + cell $eq $eq$ls180.v:8018$2588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274509,10 +272654,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_roundrobin3_grant connect \B 1'0 - connect \Y $eq$ls180.v:8224$2738_Y + connect \Y $eq$ls180.v:8018$2588_Y end - attribute \src "ls180.v:8259.9-8259.42" - cell $eq $eq$ls180.v:8259$2750 + attribute \src "ls180.v:8053.9-8053.42" + cell $eq $eq$ls180.v:8053$2600 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274520,10 +272665,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_bitcount connect \B 4'1000 - connect \Y $eq$ls180.v:8259$2750_Y + connect \Y $eq$ls180.v:8053$2600_Y end - attribute \src "ls180.v:8262.10-8262.43" - cell $eq $eq$ls180.v:8262$2751 + attribute \src "ls180.v:8056.10-8056.43" + cell $eq $eq$ls180.v:8056$2601 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274531,10 +272676,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:8262$2751_Y + connect \Y $eq$ls180.v:8056$2601_Y end - attribute \src "ls180.v:8288.9-8288.42" - cell $eq $eq$ls180.v:8288$2757 + attribute \src "ls180.v:8082.9-8082.42" + cell $eq $eq$ls180.v:8082$2607 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274542,10 +272687,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_bitcount connect \B 1'0 - connect \Y $eq$ls180.v:8288$2757_Y + connect \Y $eq$ls180.v:8082$2607_Y end - attribute \src "ls180.v:8293.10-8293.43" - cell $eq $eq$ls180.v:8293$2758 + attribute \src "ls180.v:8087.10-8087.43" + cell $eq $eq$ls180.v:8087$2608 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274553,10 +272698,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_bitcount connect \B 4'1001 - connect \Y $eq$ls180.v:8293$2758_Y + connect \Y $eq$ls180.v:8087$2608_Y end - attribute \src "ls180.v:8500.9-8500.53" - cell $eq $eq$ls180.v:8500$2807 + attribute \src "ls180.v:8294.9-8294.53" + cell $eq $eq$ls180.v:8294$2657 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274564,10 +272709,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8500$2807_Y + connect \Y $eq$ls180.v:8294$2657_Y end - attribute \src "ls180.v:8581.9-8581.54" - cell $eq $eq$ls180.v:8581$2819 + attribute \src "ls180.v:8375.9-8375.54" + cell $eq $eq$ls180.v:8375$2669 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274575,10 +272720,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8581$2819_Y + connect \Y $eq$ls180.v:8375$2669_Y end - attribute \src "ls180.v:8660.9-8660.55" - cell $eq $eq$ls180.v:8660$2831 + attribute \src "ls180.v:8454.9-8454.55" + cell $eq $eq$ls180.v:8454$2681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -274586,10 +272731,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_demux connect \B 1'1 - connect \Y $eq$ls180.v:8660$2831_Y + connect \Y $eq$ls180.v:8454$2681_Y end - attribute \src "ls180.v:8883.9-8883.49" - cell $eq $eq$ls180.v:8883$2864 + attribute \src "ls180.v:8677.9-8677.49" + cell $eq $eq$ls180.v:8677$2714 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -274597,32 +272742,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_demux connect \B 3'111 - connect \Y $eq$ls180.v:8883$2864_Y + connect \Y $eq$ls180.v:8677$2714_Y end - attribute \src "ls180.v:8459.8-8459.54" - cell $ge $ge$ls180.v:8459$2799 + attribute \src "ls180.v:8253.8-8253.54" + cell $ge $ge$ls180.v:8253$2649 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter - connect \B $sub$ls180.v:8459$2798_Y - connect \Y $ge$ls180.v:8459$2799_Y + connect \B $sub$ls180.v:8253$2648_Y + connect \Y $ge$ls180.v:8253$2649_Y end - attribute \src "ls180.v:8473.8-8473.54" - cell $ge $ge$ls180.v:8473$2803 + attribute \src "ls180.v:8267.8-8267.54" + cell $ge $ge$ls180.v:8267$2653 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter - connect \B $sub$ls180.v:8473$2802_Y - connect \Y $ge$ls180.v:8473$2803_Y + connect \B $sub$ls180.v:8267$2652_Y + connect \Y $ge$ls180.v:8267$2653_Y end - attribute \src "ls180.v:5342.47-5342.83" - cell $gt $gt$ls180.v:5342$1064 + attribute \src "ls180.v:5211.47-5211.83" + cell $gt $gt$ls180.v:5211$965 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274630,10 +272775,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 3'111 - connect \Y $gt$ls180.v:5342$1064_Y + connect \Y $gt$ls180.v:5211$965_Y end - attribute \src "ls180.v:5348.7-5348.43" - cell $lt $lt$ls180.v:5348$1067 + attribute \src "ls180.v:5217.7-5217.43" + cell $lt $lt$ls180.v:5217$968 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -274641,10 +272786,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 4'1000 - connect \Y $lt$ls180.v:5348$1067_Y + connect \Y $lt$ls180.v:5217$968_Y end - attribute \src "ls180.v:8454.8-8454.43" - cell $lt $lt$ls180.v:8454$2797 + attribute \src "ls180.v:8248.8-8248.43" + cell $lt $lt$ls180.v:8248$2647 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -274652,10 +272797,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm0_counter connect \B \main_pwm0_width - connect \Y $lt$ls180.v:8454$2797_Y + connect \Y $lt$ls180.v:8248$2647_Y end - attribute \src "ls180.v:8468.8-8468.43" - cell $lt $lt$ls180.v:8468$2801 + attribute \src "ls180.v:8262.8-8262.43" + cell $lt $lt$ls180.v:8262$2651 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -274663,11 +272808,11 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_pwm1_counter connect \B \main_pwm1_width - connect \Y $lt$ls180.v:8468$2801_Y + connect \Y $lt$ls180.v:8262$2651_Y end - attribute \src "ls180.v:10373.33-10373.36" - cell $memrd $memrd$\mem$ls180.v:10373$2918 - parameter \ABITS 6 + attribute \src "ls180.v:10164.33-10164.36" + cell $memrd $memrd$\mem$ls180.v:10164$2768 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" @@ -274675,12 +272820,12 @@ module \ls180 parameter \WIDTH 64 connect \ADDR \memadr connect \CLK 1'x - connect \DATA $memrd$\mem$ls180.v:10373$2918_DATA + connect \DATA $memrd$\mem$ls180.v:10164$2768_DATA connect \EN 1'x end - attribute \src "ls180.v:10401.27-10401.32" - cell $memrd $memrd$\mem_1$ls180.v:10401$2944 - parameter \ABITS 6 + attribute \src "ls180.v:10192.25-10192.30" + cell $memrd $memrd$\mem_1$ls180.v:10192$2794 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" @@ -274688,50 +272833,11 @@ module \ls180 parameter \WIDTH 64 connect \ADDR \memadr_1 connect \CLK 1'x - connect \DATA $memrd$\mem_1$ls180.v:10401$2944_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10429.27-10429.32" - cell $memrd $memrd$\mem_2$ls180.v:10429$2970 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \memadr_2 - connect \CLK 1'x - connect \DATA $memrd$\mem_2$ls180.v:10429$2970_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10457.27-10457.32" - cell $memrd $memrd$\mem_3$ls180.v:10457$2996 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \memadr_3 - connect \CLK 1'x - connect \DATA $memrd$\mem_3$ls180.v:10457$2996_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10485.27-10485.32" - cell $memrd $memrd$\mem_4$ls180.v:10485$3022 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \memadr_4 - connect \CLK 1'x - connect \DATA $memrd$\mem_4$ls180.v:10485$3022_DATA + connect \DATA $memrd$\mem_1$ls180.v:10192$2794_DATA connect \EN 1'x end - attribute \src "ls180.v:10496.12-10496.19" - cell $memrd $memrd$\storage$ls180.v:10496$3027 + attribute \src "ls180.v:10203.12-10203.19" + cell $memrd $memrd$\storage$ls180.v:10203$2799 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274740,11 +272846,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10496$3027_DATA + connect \DATA $memrd$\storage$ls180.v:10203$2799_DATA connect \EN 1'x end - attribute \src "ls180.v:10503.68-10503.75" - cell $memrd $memrd$\storage$ls180.v:10503$3029 + attribute \src "ls180.v:10210.68-10210.75" + cell $memrd $memrd$\storage$ls180.v:10210$2801 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274753,11 +272859,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10503$3029_DATA + connect \DATA $memrd$\storage$ls180.v:10210$2801_DATA connect \EN 1'x end - attribute \src "ls180.v:10510.14-10510.23" - cell $memrd $memrd$\storage_1$ls180.v:10510$3034 + attribute \src "ls180.v:10217.14-10217.23" + cell $memrd $memrd$\storage_1$ls180.v:10217$2806 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274766,11 +272872,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10510$3034_DATA + connect \DATA $memrd$\storage_1$ls180.v:10217$2806_DATA connect \EN 1'x end - attribute \src "ls180.v:10517.68-10517.77" - cell $memrd $memrd$\storage_1$ls180.v:10517$3036 + attribute \src "ls180.v:10224.68-10224.77" + cell $memrd $memrd$\storage_1$ls180.v:10224$2808 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274779,11 +272885,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10517$3036_DATA + connect \DATA $memrd$\storage_1$ls180.v:10224$2808_DATA connect \EN 1'x end - attribute \src "ls180.v:10524.14-10524.23" - cell $memrd $memrd$\storage_2$ls180.v:10524$3041 + attribute \src "ls180.v:10231.14-10231.23" + cell $memrd $memrd$\storage_2$ls180.v:10231$2813 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274792,11 +272898,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10524$3041_DATA + connect \DATA $memrd$\storage_2$ls180.v:10231$2813_DATA connect \EN 1'x end - attribute \src "ls180.v:10531.68-10531.77" - cell $memrd $memrd$\storage_2$ls180.v:10531$3043 + attribute \src "ls180.v:10238.68-10238.77" + cell $memrd $memrd$\storage_2$ls180.v:10238$2815 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274805,11 +272911,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10531$3043_DATA + connect \DATA $memrd$\storage_2$ls180.v:10238$2815_DATA connect \EN 1'x end - attribute \src "ls180.v:10538.14-10538.23" - cell $memrd $memrd$\storage_3$ls180.v:10538$3048 + attribute \src "ls180.v:10245.14-10245.23" + cell $memrd $memrd$\storage_3$ls180.v:10245$2820 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274818,11 +272924,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10538$3048_DATA + connect \DATA $memrd$\storage_3$ls180.v:10245$2820_DATA connect \EN 1'x end - attribute \src "ls180.v:10545.68-10545.77" - cell $memrd $memrd$\storage_3$ls180.v:10545$3050 + attribute \src "ls180.v:10252.68-10252.77" + cell $memrd $memrd$\storage_3$ls180.v:10252$2822 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274831,11 +272937,11 @@ module \ls180 parameter \WIDTH 25 connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10545$3050_DATA + connect \DATA $memrd$\storage_3$ls180.v:10252$2822_DATA connect \EN 1'x end - attribute \src "ls180.v:10553.14-10553.23" - cell $memrd $memrd$\storage_4$ls180.v:10553$3055 + attribute \src "ls180.v:10260.14-10260.23" + cell $memrd $memrd$\storage_4$ls180.v:10260$2827 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274844,11 +272950,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10553$3055_DATA + connect \DATA $memrd$\storage_4$ls180.v:10260$2827_DATA connect \EN 1'x end - attribute \src "ls180.v:10558.15-10558.24" - cell $memrd $memrd$\storage_4$ls180.v:10558$3057 + attribute \src "ls180.v:10265.15-10265.24" + cell $memrd $memrd$\storage_4$ls180.v:10265$2829 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274857,11 +272963,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_tx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10558$3057_DATA + connect \DATA $memrd$\storage_4$ls180.v:10265$2829_DATA connect \EN 1'x end - attribute \src "ls180.v:10570.14-10570.23" - cell $memrd $memrd$\storage_5$ls180.v:10570$3062 + attribute \src "ls180.v:10277.14-10277.23" + cell $memrd $memrd$\storage_5$ls180.v:10277$2834 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274870,11 +272976,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10570$3062_DATA + connect \DATA $memrd$\storage_5$ls180.v:10277$2834_DATA connect \EN 1'x end - attribute \src "ls180.v:10575.15-10575.24" - cell $memrd $memrd$\storage_5$ls180.v:10575$3064 + attribute \src "ls180.v:10282.15-10282.24" + cell $memrd $memrd$\storage_5$ls180.v:10282$2836 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274883,11 +272989,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_uart_rx_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10575$3064_DATA + connect \DATA $memrd$\storage_5$ls180.v:10282$2836_DATA connect \EN 1'x end - attribute \src "ls180.v:10586.14-10586.23" - cell $memrd $memrd$\storage_6$ls180.v:10586$3069 + attribute \src "ls180.v:10293.14-10293.23" + cell $memrd $memrd$\storage_6$ls180.v:10293$2841 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274896,11 +273002,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10586$3069_DATA + connect \DATA $memrd$\storage_6$ls180.v:10293$2841_DATA connect \EN 1'x end - attribute \src "ls180.v:10593.45-10593.54" - cell $memrd $memrd$\storage_6$ls180.v:10593$3071 + attribute \src "ls180.v:10300.45-10300.54" + cell $memrd $memrd$\storage_6$ls180.v:10300$2843 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274909,11 +273015,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdblock2mem_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10593$3071_DATA + connect \DATA $memrd$\storage_6$ls180.v:10300$2843_DATA connect \EN 1'x end - attribute \src "ls180.v:10600.14-10600.23" - cell $memrd $memrd$\storage_7$ls180.v:10600$3076 + attribute \src "ls180.v:10307.14-10307.23" + cell $memrd $memrd$\storage_7$ls180.v:10307$2848 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274922,11 +273028,11 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_wrport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10600$3076_DATA + connect \DATA $memrd$\storage_7$ls180.v:10307$2848_DATA connect \EN 1'x end - attribute \src "ls180.v:10607.45-10607.54" - cell $memrd $memrd$\storage_7$ls180.v:10607$3078 + attribute \src "ls180.v:10314.45-10314.54" + cell $memrd $memrd$\storage_7$ls180.v:10314$2850 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -274935,635 +273041,323 @@ module \ls180 parameter \WIDTH 10 connect \ADDR \main_sdmem2block_fifo_rdport_adr connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10607$3078_DATA + connect \DATA $memrd$\storage_7$ls180.v:10314$2850_DATA connect \EN 1'x end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3080 - parameter \ABITS 6 + cell $memwr $memwr$\mem$ls180.v:0$2852 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3080 + parameter \PRIORITY 2852 parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10355$1_ADDR + connect \ADDR $memwr$\mem$ls180.v:10146$1_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10355$1_DATA - connect \EN $memwr$\mem$ls180.v:10355$1_EN + connect \DATA $memwr$\mem$ls180.v:10146$1_DATA + connect \EN $memwr$\mem$ls180.v:10146$1_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3081 - parameter \ABITS 6 + cell $memwr $memwr$\mem$ls180.v:0$2853 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3081 + parameter \PRIORITY 2853 parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10357$2_ADDR + connect \ADDR $memwr$\mem$ls180.v:10148$2_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10357$2_DATA - connect \EN $memwr$\mem$ls180.v:10357$2_EN + connect \DATA $memwr$\mem$ls180.v:10148$2_DATA + connect \EN $memwr$\mem$ls180.v:10148$2_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3082 - parameter \ABITS 6 + cell $memwr $memwr$\mem$ls180.v:0$2854 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3082 + parameter \PRIORITY 2854 parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10359$3_ADDR + connect \ADDR $memwr$\mem$ls180.v:10150$3_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10359$3_DATA - connect \EN $memwr$\mem$ls180.v:10359$3_EN + connect \DATA $memwr$\mem$ls180.v:10150$3_DATA + connect \EN $memwr$\mem$ls180.v:10150$3_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3083 - parameter \ABITS 6 + cell $memwr $memwr$\mem$ls180.v:0$2855 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3083 + parameter \PRIORITY 2855 parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10361$4_ADDR + connect \ADDR $memwr$\mem$ls180.v:10152$4_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10361$4_DATA - connect \EN $memwr$\mem$ls180.v:10361$4_EN + connect \DATA $memwr$\mem$ls180.v:10152$4_DATA + connect \EN $memwr$\mem$ls180.v:10152$4_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3084 - parameter \ABITS 6 + cell $memwr $memwr$\mem$ls180.v:0$2856 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3084 + parameter \PRIORITY 2856 parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10363$5_ADDR + connect \ADDR $memwr$\mem$ls180.v:10154$5_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10363$5_DATA - connect \EN $memwr$\mem$ls180.v:10363$5_EN + connect \DATA $memwr$\mem$ls180.v:10154$5_DATA + connect \EN $memwr$\mem$ls180.v:10154$5_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3085 - parameter \ABITS 6 + cell $memwr $memwr$\mem$ls180.v:0$2857 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3085 + parameter \PRIORITY 2857 parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10365$6_ADDR + connect \ADDR $memwr$\mem$ls180.v:10156$6_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10365$6_DATA - connect \EN $memwr$\mem$ls180.v:10365$6_EN + connect \DATA $memwr$\mem$ls180.v:10156$6_DATA + connect \EN $memwr$\mem$ls180.v:10156$6_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3086 - parameter \ABITS 6 + cell $memwr $memwr$\mem$ls180.v:0$2858 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3086 + parameter \PRIORITY 2858 parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10367$7_ADDR + connect \ADDR $memwr$\mem$ls180.v:10158$7_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10367$7_DATA - connect \EN $memwr$\mem$ls180.v:10367$7_EN + connect \DATA $memwr$\mem$ls180.v:10158$7_DATA + connect \EN $memwr$\mem$ls180.v:10158$7_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$3087 - parameter \ABITS 6 + cell $memwr $memwr$\mem$ls180.v:0$2859 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem" - parameter \PRIORITY 3087 + parameter \PRIORITY 2859 parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10369$8_ADDR + connect \ADDR $memwr$\mem$ls180.v:10160$8_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10369$8_DATA - connect \EN $memwr$\mem$ls180.v:10369$8_EN + connect \DATA $memwr$\mem$ls180.v:10160$8_DATA + connect \EN $memwr$\mem$ls180.v:10160$8_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3088 - parameter \ABITS 6 + cell $memwr $memwr$\mem_1$ls180.v:0$2860 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3088 + parameter \PRIORITY 2860 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10383$9_ADDR + connect \ADDR $memwr$\mem_1$ls180.v:10174$9_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10383$9_DATA - connect \EN $memwr$\mem_1$ls180.v:10383$9_EN + connect \DATA $memwr$\mem_1$ls180.v:10174$9_DATA + connect \EN $memwr$\mem_1$ls180.v:10174$9_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3089 - parameter \ABITS 6 + cell $memwr $memwr$\mem_1$ls180.v:0$2861 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3089 + parameter \PRIORITY 2861 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10385$10_ADDR + connect \ADDR $memwr$\mem_1$ls180.v:10176$10_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10385$10_DATA - connect \EN $memwr$\mem_1$ls180.v:10385$10_EN + connect \DATA $memwr$\mem_1$ls180.v:10176$10_DATA + connect \EN $memwr$\mem_1$ls180.v:10176$10_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3090 - parameter \ABITS 6 + cell $memwr $memwr$\mem_1$ls180.v:0$2862 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3090 + parameter \PRIORITY 2862 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10387$11_ADDR + connect \ADDR $memwr$\mem_1$ls180.v:10178$11_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10387$11_DATA - connect \EN $memwr$\mem_1$ls180.v:10387$11_EN + connect \DATA $memwr$\mem_1$ls180.v:10178$11_DATA + connect \EN $memwr$\mem_1$ls180.v:10178$11_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3091 - parameter \ABITS 6 + cell $memwr $memwr$\mem_1$ls180.v:0$2863 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3091 + parameter \PRIORITY 2863 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10389$12_ADDR + connect \ADDR $memwr$\mem_1$ls180.v:10180$12_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10389$12_DATA - connect \EN $memwr$\mem_1$ls180.v:10389$12_EN + connect \DATA $memwr$\mem_1$ls180.v:10180$12_DATA + connect \EN $memwr$\mem_1$ls180.v:10180$12_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3092 - parameter \ABITS 6 + cell $memwr $memwr$\mem_1$ls180.v:0$2864 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3092 + parameter \PRIORITY 2864 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10391$13_ADDR + connect \ADDR $memwr$\mem_1$ls180.v:10182$13_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10391$13_DATA - connect \EN $memwr$\mem_1$ls180.v:10391$13_EN + connect \DATA $memwr$\mem_1$ls180.v:10182$13_DATA + connect \EN $memwr$\mem_1$ls180.v:10182$13_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3093 - parameter \ABITS 6 + cell $memwr $memwr$\mem_1$ls180.v:0$2865 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3093 + parameter \PRIORITY 2865 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10393$14_ADDR + connect \ADDR $memwr$\mem_1$ls180.v:10184$14_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10393$14_DATA - connect \EN $memwr$\mem_1$ls180.v:10393$14_EN + connect \DATA $memwr$\mem_1$ls180.v:10184$14_DATA + connect \EN $memwr$\mem_1$ls180.v:10184$14_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3094 - parameter \ABITS 6 + cell $memwr $memwr$\mem_1$ls180.v:0$2866 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3094 + parameter \PRIORITY 2866 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10395$15_ADDR + connect \ADDR $memwr$\mem_1$ls180.v:10186$15_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10395$15_DATA - connect \EN $memwr$\mem_1$ls180.v:10395$15_EN + connect \DATA $memwr$\mem_1$ls180.v:10186$15_DATA + connect \EN $memwr$\mem_1$ls180.v:10186$15_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$3095 - parameter \ABITS 6 + cell $memwr $memwr$\mem_1$ls180.v:0$2867 + parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\mem_1" - parameter \PRIORITY 3095 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10397$16_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10397$16_DATA - connect \EN $memwr$\mem_1$ls180.v:10397$16_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3096 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3096 + parameter \PRIORITY 2867 parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10411$17_ADDR + connect \ADDR $memwr$\mem_1$ls180.v:10188$16_ADDR connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10411$17_DATA - connect \EN $memwr$\mem_2$ls180.v:10411$17_EN + connect \DATA $memwr$\mem_1$ls180.v:10188$16_DATA + connect \EN $memwr$\mem_1$ls180.v:10188$16_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3097 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3097 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10413$18_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10413$18_DATA - connect \EN $memwr$\mem_2$ls180.v:10413$18_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3098 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3098 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10415$19_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10415$19_DATA - connect \EN $memwr$\mem_2$ls180.v:10415$19_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3099 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3099 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10417$20_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10417$20_DATA - connect \EN $memwr$\mem_2$ls180.v:10417$20_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3100 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3100 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10419$21_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10419$21_DATA - connect \EN $memwr$\mem_2$ls180.v:10419$21_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3101 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3101 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10421$22_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10421$22_DATA - connect \EN $memwr$\mem_2$ls180.v:10421$22_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3102 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3102 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10423$23_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10423$23_DATA - connect \EN $memwr$\mem_2$ls180.v:10423$23_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_2$ls180.v:0$3103 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_2" - parameter \PRIORITY 3103 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_2$ls180.v:10425$24_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_2$ls180.v:10425$24_DATA - connect \EN $memwr$\mem_2$ls180.v:10425$24_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3104 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3104 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10439$25_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10439$25_DATA - connect \EN $memwr$\mem_3$ls180.v:10439$25_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3105 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3105 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10441$26_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10441$26_DATA - connect \EN $memwr$\mem_3$ls180.v:10441$26_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3106 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3106 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10443$27_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10443$27_DATA - connect \EN $memwr$\mem_3$ls180.v:10443$27_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3107 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3107 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10445$28_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10445$28_DATA - connect \EN $memwr$\mem_3$ls180.v:10445$28_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3108 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3108 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10447$29_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10447$29_DATA - connect \EN $memwr$\mem_3$ls180.v:10447$29_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3109 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3109 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10449$30_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10449$30_DATA - connect \EN $memwr$\mem_3$ls180.v:10449$30_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3110 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3110 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10451$31_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10451$31_DATA - connect \EN $memwr$\mem_3$ls180.v:10451$31_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_3$ls180.v:0$3111 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_3" - parameter \PRIORITY 3111 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_3$ls180.v:10453$32_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_3$ls180.v:10453$32_DATA - connect \EN $memwr$\mem_3$ls180.v:10453$32_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3112 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3112 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10467$33_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10467$33_DATA - connect \EN $memwr$\mem_4$ls180.v:10467$33_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3113 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3113 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10469$34_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10469$34_DATA - connect \EN $memwr$\mem_4$ls180.v:10469$34_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3114 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3114 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10471$35_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10471$35_DATA - connect \EN $memwr$\mem_4$ls180.v:10471$35_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3115 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3115 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10473$36_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10473$36_DATA - connect \EN $memwr$\mem_4$ls180.v:10473$36_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3116 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3116 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10475$37_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10475$37_DATA - connect \EN $memwr$\mem_4$ls180.v:10475$37_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3117 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3117 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10477$38_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10477$38_DATA - connect \EN $memwr$\mem_4$ls180.v:10477$38_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3118 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3118 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10479$39_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10479$39_DATA - connect \EN $memwr$\mem_4$ls180.v:10479$39_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_4$ls180.v:0$3119 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_4" - parameter \PRIORITY 3119 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_4$ls180.v:10481$40_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_4$ls180.v:10481$40_DATA - connect \EN $memwr$\mem_4$ls180.v:10481$40_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage$ls180.v:0$3120 + cell $memwr $memwr$\storage$ls180.v:0$2868 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage" - parameter \PRIORITY 3120 + parameter \PRIORITY 2868 parameter \WIDTH 25 - connect \ADDR $memwr$\storage$ls180.v:10495$41_ADDR + connect \ADDR $memwr$\storage$ls180.v:10202$17_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage$ls180.v:10495$41_DATA - connect \EN $memwr$\storage$ls180.v:10495$41_EN + connect \DATA $memwr$\storage$ls180.v:10202$17_DATA + connect \EN $memwr$\storage$ls180.v:10202$17_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_1$ls180.v:0$3121 + cell $memwr $memwr$\storage_1$ls180.v:0$2869 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_1" - parameter \PRIORITY 3121 + parameter \PRIORITY 2869 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_1$ls180.v:10509$42_ADDR + connect \ADDR $memwr$\storage_1$ls180.v:10216$18_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_1$ls180.v:10509$42_DATA - connect \EN $memwr$\storage_1$ls180.v:10509$42_EN + connect \DATA $memwr$\storage_1$ls180.v:10216$18_DATA + connect \EN $memwr$\storage_1$ls180.v:10216$18_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_2$ls180.v:0$3122 + cell $memwr $memwr$\storage_2$ls180.v:0$2870 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_2" - parameter \PRIORITY 3122 + parameter \PRIORITY 2870 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_2$ls180.v:10523$43_ADDR + connect \ADDR $memwr$\storage_2$ls180.v:10230$19_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_2$ls180.v:10523$43_DATA - connect \EN $memwr$\storage_2$ls180.v:10523$43_EN + connect \DATA $memwr$\storage_2$ls180.v:10230$19_DATA + connect \EN $memwr$\storage_2$ls180.v:10230$19_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_3$ls180.v:0$3123 + cell $memwr $memwr$\storage_3$ls180.v:0$2871 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_3" - parameter \PRIORITY 3123 + parameter \PRIORITY 2871 parameter \WIDTH 25 - connect \ADDR $memwr$\storage_3$ls180.v:10537$44_ADDR + connect \ADDR $memwr$\storage_3$ls180.v:10244$20_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_3$ls180.v:10537$44_DATA - connect \EN $memwr$\storage_3$ls180.v:10537$44_EN + connect \DATA $memwr$\storage_3$ls180.v:10244$20_DATA + connect \EN $memwr$\storage_3$ls180.v:10244$20_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_4$ls180.v:0$3124 + cell $memwr $memwr$\storage_4$ls180.v:0$2872 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_4" - parameter \PRIORITY 3124 + parameter \PRIORITY 2872 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_4$ls180.v:10552$45_ADDR + connect \ADDR $memwr$\storage_4$ls180.v:10259$21_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_4$ls180.v:10552$45_DATA - connect \EN $memwr$\storage_4$ls180.v:10552$45_EN + connect \DATA $memwr$\storage_4$ls180.v:10259$21_DATA + connect \EN $memwr$\storage_4$ls180.v:10259$21_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_5$ls180.v:0$3125 + cell $memwr $memwr$\storage_5$ls180.v:0$2873 parameter \ABITS 4 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_5" - parameter \PRIORITY 3125 + parameter \PRIORITY 2873 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_5$ls180.v:10569$46_ADDR + connect \ADDR $memwr$\storage_5$ls180.v:10276$22_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_5$ls180.v:10569$46_DATA - connect \EN $memwr$\storage_5$ls180.v:10569$46_EN + connect \DATA $memwr$\storage_5$ls180.v:10276$22_DATA + connect \EN $memwr$\storage_5$ls180.v:10276$22_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_6$ls180.v:0$3126 + cell $memwr $memwr$\storage_6$ls180.v:0$2874 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_6" - parameter \PRIORITY 3126 + parameter \PRIORITY 2874 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_6$ls180.v:10585$47_ADDR + connect \ADDR $memwr$\storage_6$ls180.v:10292$23_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_6$ls180.v:10585$47_DATA - connect \EN $memwr$\storage_6$ls180.v:10585$47_EN + connect \DATA $memwr$\storage_6$ls180.v:10292$23_DATA + connect \EN $memwr$\storage_6$ls180.v:10292$23_EN end attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_7$ls180.v:0$3127 + cell $memwr $memwr$\storage_7$ls180.v:0$2875 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 parameter \MEMID "\\storage_7" - parameter \PRIORITY 3127 + parameter \PRIORITY 2875 parameter \WIDTH 10 - connect \ADDR $memwr$\storage_7$ls180.v:10599$48_ADDR + connect \ADDR $memwr$\storage_7$ls180.v:10306$24_ADDR connect \CLK 1'x - connect \DATA $memwr$\storage_7$ls180.v:10599$48_DATA - connect \EN $memwr$\storage_7$ls180.v:10599$48_EN + connect \DATA $memwr$\storage_7$ls180.v:10306$24_DATA + connect \EN $memwr$\storage_7$ls180.v:10306$24_EN end - attribute \src "ls180.v:3089.41-3089.71" - cell $ne $ne$ls180.v:3089$108 + attribute \src "ls180.v:3000.41-3000.71" + cell $ne $ne$ls180.v:3000$84 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -275571,10 +273365,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_value connect \B 1'0 - connect \Y $ne$ls180.v:3089$108_Y + connect \Y $ne$ls180.v:3000$84_Y end - attribute \src "ls180.v:3306.70-3306.104" - cell $ne $ne$ls180.v:3306$222 + attribute \src "ls180.v:3175.70-3175.104" + cell $ne $ne$ls180.v:3175$123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275582,10 +273376,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:3306$222_Y + connect \Y $ne$ls180.v:3175$123_Y end - attribute \src "ls180.v:3367.8-3367.142" - cell $ne $ne$ls180.v:3367$241 + attribute \src "ls180.v:3236.8-3236.142" + cell $ne $ne$ls180.v:3236$142 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -275593,10 +273387,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3367$241_Y + connect \Y $ne$ls180.v:3236$142_Y end - attribute \src "ls180.v:3399.75-3399.133" - cell $ne $ne$ls180.v:3399$248 + attribute \src "ls180.v:3268.75-3268.133" + cell $ne $ne$ls180.v:3268$149 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -275604,10 +273398,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3399$248_Y + connect \Y $ne$ls180.v:3268$149_Y end - attribute \src "ls180.v:3400.75-3400.133" - cell $ne $ne$ls180.v:3400$249 + attribute \src "ls180.v:3269.75-3269.133" + cell $ne $ne$ls180.v:3269$150 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -275615,10 +273409,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3400$249_Y + connect \Y $ne$ls180.v:3269$150_Y end - attribute \src "ls180.v:3524.8-3524.142" - cell $ne $ne$ls180.v:3524$271 + attribute \src "ls180.v:3393.8-3393.142" + cell $ne $ne$ls180.v:3393$172 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -275626,10 +273420,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3524$271_Y + connect \Y $ne$ls180.v:3393$172_Y end - attribute \src "ls180.v:3556.75-3556.133" - cell $ne $ne$ls180.v:3556$278 + attribute \src "ls180.v:3425.75-3425.133" + cell $ne $ne$ls180.v:3425$179 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -275637,10 +273431,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3556$278_Y + connect \Y $ne$ls180.v:3425$179_Y end - attribute \src "ls180.v:3557.75-3557.133" - cell $ne $ne$ls180.v:3557$279 + attribute \src "ls180.v:3426.75-3426.133" + cell $ne $ne$ls180.v:3426$180 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -275648,10 +273442,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3557$279_Y + connect \Y $ne$ls180.v:3426$180_Y end - attribute \src "ls180.v:3681.8-3681.142" - cell $ne $ne$ls180.v:3681$301 + attribute \src "ls180.v:3550.8-3550.142" + cell $ne $ne$ls180.v:3550$202 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -275659,10 +273453,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3681$301_Y + connect \Y $ne$ls180.v:3550$202_Y end - attribute \src "ls180.v:3713.75-3713.133" - cell $ne $ne$ls180.v:3713$308 + attribute \src "ls180.v:3582.75-3582.133" + cell $ne $ne$ls180.v:3582$209 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -275670,10 +273464,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3713$308_Y + connect \Y $ne$ls180.v:3582$209_Y end - attribute \src "ls180.v:3714.75-3714.133" - cell $ne $ne$ls180.v:3714$309 + attribute \src "ls180.v:3583.75-3583.133" + cell $ne $ne$ls180.v:3583$210 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -275681,10 +273475,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3714$309_Y + connect \Y $ne$ls180.v:3583$210_Y end - attribute \src "ls180.v:3838.8-3838.142" - cell $ne $ne$ls180.v:3838$331 + attribute \src "ls180.v:3707.8-3707.142" + cell $ne $ne$ls180.v:3707$232 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -275692,10 +273486,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3838$331_Y + connect \Y $ne$ls180.v:3707$232_Y end - attribute \src "ls180.v:3870.75-3870.133" - cell $ne $ne$ls180.v:3870$338 + attribute \src "ls180.v:3739.75-3739.133" + cell $ne $ne$ls180.v:3739$239 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -275703,10 +273497,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 4'1000 - connect \Y $ne$ls180.v:3870$338_Y + connect \Y $ne$ls180.v:3739$239_Y end - attribute \src "ls180.v:3871.75-3871.133" - cell $ne $ne$ls180.v:3871$339 + attribute \src "ls180.v:3740.75-3740.133" + cell $ne $ne$ls180.v:3740$240 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -275714,10 +273508,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'0 - connect \Y $ne$ls180.v:3871$339_Y + connect \Y $ne$ls180.v:3740$240_Y end - attribute \src "ls180.v:4363.47-4363.80" - cell $ne $ne$ls180.v:4363$737 + attribute \src "ls180.v:4232.47-4232.80" + cell $ne $ne$ls180.v:4232$638 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -275725,10 +273519,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_level0 connect \B 5'10000 - connect \Y $ne$ls180.v:4363$737_Y + connect \Y $ne$ls180.v:4232$638_Y end - attribute \src "ls180.v:4364.47-4364.79" - cell $ne $ne$ls180.v:4364$738 + attribute \src "ls180.v:4233.47-4233.79" + cell $ne $ne$ls180.v:4233$639 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -275736,10 +273530,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_level0 connect \B 1'0 - connect \Y $ne$ls180.v:4364$738_Y + connect \Y $ne$ls180.v:4233$639_Y end - attribute \src "ls180.v:4393.47-4393.80" - cell $ne $ne$ls180.v:4393$748 + attribute \src "ls180.v:4262.47-4262.80" + cell $ne $ne$ls180.v:4262$649 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -275747,10 +273541,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_level0 connect \B 5'10000 - connect \Y $ne$ls180.v:4393$748_Y + connect \Y $ne$ls180.v:4262$649_Y end - attribute \src "ls180.v:4394.47-4394.79" - cell $ne $ne$ls180.v:4394$749 + attribute \src "ls180.v:4263.47-4263.79" + cell $ne $ne$ls180.v:4263$650 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -275758,10 +273552,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_level0 connect \B 1'0 - connect \Y $ne$ls180.v:4394$749_Y + connect \Y $ne$ls180.v:4263$650_Y end - attribute \src "ls180.v:4874.32-4874.89" - cell $ne $ne$ls180.v:4874$831 + attribute \src "ls180.v:4743.32-4743.89" + cell $ne $ne$ls180.v:4743$732 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -275769,10 +273563,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 connect \B 3'101 - connect \Y $ne$ls180.v:4874$831_Y + connect \Y $ne$ls180.v:4743$732_Y end - attribute \src "ls180.v:5521.10-5521.56" - cell $ne $ne$ls180.v:5521$1128 + attribute \src "ls180.v:5390.10-5390.56" + cell $ne $ne$ls180.v:5390$1029 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -275780,10 +273574,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_source_payload_status connect \B 2'10 - connect \Y $ne$ls180.v:5521$1128_Y + connect \Y $ne$ls180.v:5390$1029_Y end - attribute \src "ls180.v:5626.51-5626.87" - cell $ne $ne$ls180.v:5626$1142 + attribute \src "ls180.v:5495.51-5495.87" + cell $ne $ne$ls180.v:5495$1043 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -275791,10 +273585,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_level connect \B 6'100000 - connect \Y $ne$ls180.v:5626$1142_Y + connect \Y $ne$ls180.v:5495$1043_Y end - attribute \src "ls180.v:5627.51-5627.86" - cell $ne $ne$ls180.v:5627$1143 + attribute \src "ls180.v:5496.51-5496.86" + cell $ne $ne$ls180.v:5496$1044 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -275802,10 +273596,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_level connect \B 1'0 - connect \Y $ne$ls180.v:5627$1143_Y + connect \Y $ne$ls180.v:5496$1044_Y end - attribute \src "ls180.v:5846.51-5846.87" - cell $ne $ne$ls180.v:5846$1173 + attribute \src "ls180.v:5715.51-5715.87" + cell $ne $ne$ls180.v:5715$1074 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -275813,10 +273607,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_level connect \B 6'100000 - connect \Y $ne$ls180.v:5846$1173_Y + connect \Y $ne$ls180.v:5715$1074_Y end - attribute \src "ls180.v:5847.51-5847.86" - cell $ne $ne$ls180.v:5847$1174 + attribute \src "ls180.v:5716.51-5716.86" + cell $ne $ne$ls180.v:5716$1075 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -275824,10 +273618,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_level connect \B 1'0 - connect \Y $ne$ls180.v:5847$1174_Y + connect \Y $ne$ls180.v:5716$1075_Y end - attribute \src "ls180.v:5878.79-5878.119" - cell $ne $ne$ls180.v:5878$1177 + attribute \src "ls180.v:5747.79-5747.119" + cell $ne $ne$ls180.v:5747$1078 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -275835,10 +273629,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \builder_libresocsim_wishbone_sel connect \B 1'0 - connect \Y $ne$ls180.v:5878$1177_Y + connect \Y $ne$ls180.v:5747$1078_Y end - attribute \src "ls180.v:7763.7-7763.52" - cell $ne $ne$ls180.v:7763$2603 + attribute \src "ls180.v:7569.7-7569.52" + cell $ne $ne$ls180.v:7569$2462 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -275846,10 +273640,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_bus_errors connect \B 32'11111111111111111111111111111111 - connect \Y $ne$ls180.v:7763$2603_Y + connect \Y $ne$ls180.v:7569$2462_Y end - attribute \src "ls180.v:7829.9-7829.43" - cell $ne $ne$ls180.v:7829$2629 + attribute \src "ls180.v:7623.9-7623.43" + cell $ne $ne$ls180.v:7623$2479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -275857,10 +273651,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'0 - connect \Y $ne$ls180.v:7829$2629_Y + connect \Y $ne$ls180.v:7623$2479_Y end - attribute \src "ls180.v:7865.8-7865.44" - cell $ne $ne$ls180.v:7865$2636 + attribute \src "ls180.v:7659.8-7659.44" + cell $ne $ne$ls180.v:7659$2486 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -275868,10 +273662,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_counter connect \B 1'0 - connect \Y $ne$ls180.v:7865$2636_Y + connect \Y $ne$ls180.v:7659$2486_Y end - attribute \src "ls180.v:8803.9-8803.47" - cell $ne $ne$ls180.v:8803$2851 + attribute \src "ls180.v:8597.9-8597.47" + cell $ne $ne$ls180.v:8597$2701 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -275879,2738 +273673,2714 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_cnt connect \B 4'1010 - connect \Y $ne$ls180.v:8803$2851_Y + connect \Y $ne$ls180.v:8597$2701_Y end - attribute \src "ls180.v:2893.33-2893.73" - cell $not $not$ls180.v:2893$50 + attribute \src "ls180.v:2804.33-2804.73" + cell $not $not$ls180.v:2804$26 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface0_converted_interface_cyc - connect \Y $not$ls180.v:2893$50_Y + connect \Y $not$ls180.v:2804$26_Y end - attribute \src "ls180.v:2932.48-2932.69" - cell $not $not$ls180.v:2932$55 + attribute \src "ls180.v:2843.48-2843.69" + cell $not $not$ls180.v:2843$31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter0_skip - connect \Y $not$ls180.v:2932$55_Y + connect \Y $not$ls180.v:2843$31_Y end - attribute \src "ls180.v:2933.48-2933.69" - cell $not $not$ls180.v:2933$56 + attribute \src "ls180.v:2844.48-2844.69" + cell $not $not$ls180.v:2844$32 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter0_skip - connect \Y $not$ls180.v:2933$56_Y + connect \Y $not$ls180.v:2844$32_Y end - attribute \src "ls180.v:2953.33-2953.73" - cell $not $not$ls180.v:2953$61 + attribute \src "ls180.v:2864.33-2864.73" + cell $not $not$ls180.v:2864$37 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_interface1_converted_interface_cyc - connect \Y $not$ls180.v:2953$61_Y + connect \Y $not$ls180.v:2864$37_Y end - attribute \src "ls180.v:2992.48-2992.69" - cell $not $not$ls180.v:2992$66 + attribute \src "ls180.v:2903.48-2903.69" + cell $not $not$ls180.v:2903$42 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter1_skip - connect \Y $not$ls180.v:2992$66_Y + connect \Y $not$ls180.v:2903$42_Y end - attribute \src "ls180.v:2993.48-2993.69" - cell $not $not$ls180.v:2993$67 + attribute \src "ls180.v:2904.48-2904.69" + cell $not $not$ls180.v:2904$43 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter1_skip - connect \Y $not$ls180.v:2993$67_Y + connect \Y $not$ls180.v:2904$43_Y end - attribute \src "ls180.v:3013.36-3013.79" - cell $not $not$ls180.v:3013$72 + attribute \src "ls180.v:2924.36-2924.79" + cell $not $not$ls180.v:2924$48 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_socbushandler_converted_interface_cyc - connect \Y $not$ls180.v:3013$72_Y + connect \Y $not$ls180.v:2924$48_Y end - attribute \src "ls180.v:3052.27-3052.51" - cell $not $not$ls180.v:3052$77 + attribute \src "ls180.v:2963.27-2963.51" + cell $not $not$ls180.v:2963$53 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_socbushandler_skip - connect \Y $not$ls180.v:3052$77_Y + connect \Y $not$ls180.v:2963$53_Y end - attribute \src "ls180.v:3053.27-3053.51" - cell $not $not$ls180.v:3053$78 + attribute \src "ls180.v:2964.27-2964.51" + cell $not $not$ls180.v:2964$54 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_socbushandler_skip - connect \Y $not$ls180.v:3053$78_Y + connect \Y $not$ls180.v:2964$54_Y end - attribute \src "ls180.v:3255.34-3255.64" - cell $not $not$ls180.v:3255$214 + attribute \src "ls180.v:3124.34-3124.64" + cell $not $not$ls180.v:3124$115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [0] - connect \Y $not$ls180.v:3255$214_Y + connect \Y $not$ls180.v:3124$115_Y end - attribute \src "ls180.v:3256.31-3256.61" - cell $not $not$ls180.v:3256$215 + attribute \src "ls180.v:3125.31-3125.61" + cell $not $not$ls180.v:3125$116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [1] - connect \Y $not$ls180.v:3256$215_Y + connect \Y $not$ls180.v:3125$116_Y end - attribute \src "ls180.v:3257.32-3257.62" - cell $not $not$ls180.v:3257$216 + attribute \src "ls180.v:3126.32-3126.62" + cell $not $not$ls180.v:3126$117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [2] - connect \Y $not$ls180.v:3257$216_Y + connect \Y $not$ls180.v:3126$117_Y end - attribute \src "ls180.v:3258.32-3258.62" - cell $not $not$ls180.v:3258$217 + attribute \src "ls180.v:3127.32-3127.62" + cell $not $not$ls180.v:3127$118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_command_storage [3] - connect \Y $not$ls180.v:3258$217_Y + connect \Y $not$ls180.v:3127$118_Y end - attribute \src "ls180.v:3300.33-3300.56" - cell $not $not$ls180.v:3300$220 + attribute \src "ls180.v:3169.33-3169.56" + cell $not $not$ls180.v:3169$121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:3300$220_Y + connect \Y $not$ls180.v:3169$121_Y end - attribute \src "ls180.v:3401.58-3401.106" - cell $not $not$ls180.v:3401$250 + attribute \src "ls180.v:3270.58-3270.106" + cell $not $not$ls180.v:3270$151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:3401$250_Y + connect \Y $not$ls180.v:3270$151_Y end - attribute \src "ls180.v:3455.9-3455.45" - cell $not $not$ls180.v:3455$255 + attribute \src "ls180.v:3324.9-3324.45" + cell $not $not$ls180.v:3324$156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_refresh_req - connect \Y $not$ls180.v:3455$255_Y + connect \Y $not$ls180.v:3324$156_Y end - attribute \src "ls180.v:3558.58-3558.106" - cell $not $not$ls180.v:3558$280 + attribute \src "ls180.v:3427.58-3427.106" + cell $not $not$ls180.v:3427$181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:3558$280_Y + connect \Y $not$ls180.v:3427$181_Y end - attribute \src "ls180.v:3612.9-3612.45" - cell $not $not$ls180.v:3612$285 + attribute \src "ls180.v:3481.9-3481.45" + cell $not $not$ls180.v:3481$186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_refresh_req - connect \Y $not$ls180.v:3612$285_Y + connect \Y $not$ls180.v:3481$186_Y end - attribute \src "ls180.v:3715.58-3715.106" - cell $not $not$ls180.v:3715$310 + attribute \src "ls180.v:3584.58-3584.106" + cell $not $not$ls180.v:3584$211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:3715$310_Y + connect \Y $not$ls180.v:3584$211_Y end - attribute \src "ls180.v:3769.9-3769.45" - cell $not $not$ls180.v:3769$315 + attribute \src "ls180.v:3638.9-3638.45" + cell $not $not$ls180.v:3638$216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_refresh_req - connect \Y $not$ls180.v:3769$315_Y + connect \Y $not$ls180.v:3638$216_Y end - attribute \src "ls180.v:3872.58-3872.106" - cell $not $not$ls180.v:3872$340 + attribute \src "ls180.v:3741.58-3741.106" + cell $not $not$ls180.v:3741$241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:3872$340_Y + connect \Y $not$ls180.v:3741$241_Y end - attribute \src "ls180.v:3926.9-3926.45" - cell $not $not$ls180.v:3926$345 + attribute \src "ls180.v:3795.9-3795.45" + cell $not $not$ls180.v:3795$246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_refresh_req - connect \Y $not$ls180.v:3926$345_Y + connect \Y $not$ls180.v:3795$246_Y end - attribute \src "ls180.v:3968.149-3968.187" - cell $not $not$ls180.v:3968$348 + attribute \src "ls180.v:3837.149-3837.187" + cell $not $not$ls180.v:3837$249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3968$348_Y + connect \Y $not$ls180.v:3837$249_Y end - attribute \src "ls180.v:3968.193-3968.230" - cell $not $not$ls180.v:3968$350 + attribute \src "ls180.v:3837.193-3837.230" + cell $not $not$ls180.v:3837$251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3968$350_Y + connect \Y $not$ls180.v:3837$251_Y end - attribute \src "ls180.v:3969.149-3969.187" - cell $not $not$ls180.v:3969$354 + attribute \src "ls180.v:3838.149-3838.187" + cell $not $not$ls180.v:3838$255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3969$354_Y + connect \Y $not$ls180.v:3838$255_Y end - attribute \src "ls180.v:3969.193-3969.230" - cell $not $not$ls180.v:3969$356 + attribute \src "ls180.v:3838.193-3838.230" + cell $not $not$ls180.v:3838$257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3969$356_Y + connect \Y $not$ls180.v:3838$257_Y end - attribute \src "ls180.v:3985.43-3985.73" - cell $not $not$ls180.v:3985$384 + attribute \src "ls180.v:3854.43-3854.73" + cell $not $not$ls180.v:3854$285 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \main_sdram_interface_wdata_we - connect \Y $not$ls180.v:3985$384_Y + connect \Y $not$ls180.v:3854$285_Y end - attribute \src "ls180.v:3988.205-3988.245" - cell $not $not$ls180.v:3988$387 + attribute \src "ls180.v:3857.205-3857.245" + cell $not $not$ls180.v:3857$288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3988$387_Y + connect \Y $not$ls180.v:3857$288_Y end - attribute \src "ls180.v:3988.251-3988.290" - cell $not $not$ls180.v:3988$389 + attribute \src "ls180.v:3857.251-3857.290" + cell $not $not$ls180.v:3857$290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3988$389_Y + connect \Y $not$ls180.v:3857$290_Y end - attribute \src "ls180.v:3988.159-3988.292" - cell $not $not$ls180.v:3988$391 + attribute \src "ls180.v:3857.159-3857.292" + cell $not $not$ls180.v:3857$292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$390_Y - connect \Y $not$ls180.v:3988$391_Y + connect \A $and$ls180.v:3857$291_Y + connect \Y $not$ls180.v:3857$292_Y end - attribute \src "ls180.v:3989.205-3989.245" - cell $not $not$ls180.v:3989$400 + attribute \src "ls180.v:3858.205-3858.245" + cell $not $not$ls180.v:3858$301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3989$400_Y + connect \Y $not$ls180.v:3858$301_Y end - attribute \src "ls180.v:3989.251-3989.290" - cell $not $not$ls180.v:3989$402 + attribute \src "ls180.v:3858.251-3858.290" + cell $not $not$ls180.v:3858$303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3989$402_Y + connect \Y $not$ls180.v:3858$303_Y end - attribute \src "ls180.v:3989.159-3989.292" - cell $not $not$ls180.v:3989$404 + attribute \src "ls180.v:3858.159-3858.292" + cell $not $not$ls180.v:3858$305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3989$403_Y - connect \Y $not$ls180.v:3989$404_Y + connect \A $and$ls180.v:3858$304_Y + connect \Y $not$ls180.v:3858$305_Y end - attribute \src "ls180.v:3990.205-3990.245" - cell $not $not$ls180.v:3990$413 + attribute \src "ls180.v:3859.205-3859.245" + cell $not $not$ls180.v:3859$314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3990$413_Y + connect \Y $not$ls180.v:3859$314_Y end - attribute \src "ls180.v:3990.251-3990.290" - cell $not $not$ls180.v:3990$415 + attribute \src "ls180.v:3859.251-3859.290" + cell $not $not$ls180.v:3859$316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3990$415_Y + connect \Y $not$ls180.v:3859$316_Y end - attribute \src "ls180.v:3990.159-3990.292" - cell $not $not$ls180.v:3990$417 + attribute \src "ls180.v:3859.159-3859.292" + cell $not $not$ls180.v:3859$318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3990$416_Y - connect \Y $not$ls180.v:3990$417_Y + connect \A $and$ls180.v:3859$317_Y + connect \Y $not$ls180.v:3859$318_Y end - attribute \src "ls180.v:3991.205-3991.245" - cell $not $not$ls180.v:3991$426 + attribute \src "ls180.v:3860.205-3860.245" + cell $not $not$ls180.v:3860$327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3991$426_Y + connect \Y $not$ls180.v:3860$327_Y end - attribute \src "ls180.v:3991.251-3991.290" - cell $not $not$ls180.v:3991$428 + attribute \src "ls180.v:3860.251-3860.290" + cell $not $not$ls180.v:3860$329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3991$428_Y + connect \Y $not$ls180.v:3860$329_Y end - attribute \src "ls180.v:3991.159-3991.292" - cell $not $not$ls180.v:3991$430 + attribute \src "ls180.v:3860.159-3860.292" + cell $not $not$ls180.v:3860$331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3991$429_Y - connect \Y $not$ls180.v:3991$430_Y + connect \A $and$ls180.v:3860$330_Y + connect \Y $not$ls180.v:3860$331_Y end - attribute \src "ls180.v:4018.71-4018.103" - cell $not $not$ls180.v:4018$441 + attribute \src "ls180.v:3887.71-3887.103" + cell $not $not$ls180.v:3887$342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_valid - connect \Y $not$ls180.v:4018$441_Y + connect \Y $not$ls180.v:3887$342_Y end - attribute \src "ls180.v:4021.205-4021.245" - cell $not $not$ls180.v:4021$445 + attribute \src "ls180.v:3890.205-3890.245" + cell $not $not$ls180.v:3890$346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:4021$445_Y + connect \Y $not$ls180.v:3890$346_Y end - attribute \src "ls180.v:4021.251-4021.290" - cell $not $not$ls180.v:4021$447 + attribute \src "ls180.v:3890.251-3890.290" + cell $not $not$ls180.v:3890$348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:4021$447_Y + connect \Y $not$ls180.v:3890$348_Y end - attribute \src "ls180.v:4021.159-4021.292" - cell $not $not$ls180.v:4021$449 + attribute \src "ls180.v:3890.159-3890.292" + cell $not $not$ls180.v:3890$350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4021$448_Y - connect \Y $not$ls180.v:4021$449_Y + connect \A $and$ls180.v:3890$349_Y + connect \Y $not$ls180.v:3890$350_Y end - attribute \src "ls180.v:4022.205-4022.245" - cell $not $not$ls180.v:4022$458 + attribute \src "ls180.v:3891.205-3891.245" + cell $not $not$ls180.v:3891$359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:4022$458_Y + connect \Y $not$ls180.v:3891$359_Y end - attribute \src "ls180.v:4022.251-4022.290" - cell $not $not$ls180.v:4022$460 + attribute \src "ls180.v:3891.251-3891.290" + cell $not $not$ls180.v:3891$361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:4022$460_Y + connect \Y $not$ls180.v:3891$361_Y end - attribute \src "ls180.v:4022.159-4022.292" - cell $not $not$ls180.v:4022$462 + attribute \src "ls180.v:3891.159-3891.292" + cell $not $not$ls180.v:3891$363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4022$461_Y - connect \Y $not$ls180.v:4022$462_Y + connect \A $and$ls180.v:3891$362_Y + connect \Y $not$ls180.v:3891$363_Y end - attribute \src "ls180.v:4023.205-4023.245" - cell $not $not$ls180.v:4023$471 + attribute \src "ls180.v:3892.205-3892.245" + cell $not $not$ls180.v:3892$372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:4023$471_Y + connect \Y $not$ls180.v:3892$372_Y end - attribute \src "ls180.v:4023.251-4023.290" - cell $not $not$ls180.v:4023$473 + attribute \src "ls180.v:3892.251-3892.290" + cell $not $not$ls180.v:3892$374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:4023$473_Y + connect \Y $not$ls180.v:3892$374_Y end - attribute \src "ls180.v:4023.159-4023.292" - cell $not $not$ls180.v:4023$475 + attribute \src "ls180.v:3892.159-3892.292" + cell $not $not$ls180.v:3892$376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4023$474_Y - connect \Y $not$ls180.v:4023$475_Y + connect \A $and$ls180.v:3892$375_Y + connect \Y $not$ls180.v:3892$376_Y end - attribute \src "ls180.v:4024.205-4024.245" - cell $not $not$ls180.v:4024$484 + attribute \src "ls180.v:3893.205-3893.245" + cell $not $not$ls180.v:3893$385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:4024$484_Y + connect \Y $not$ls180.v:3893$385_Y end - attribute \src "ls180.v:4024.251-4024.290" - cell $not $not$ls180.v:4024$486 + attribute \src "ls180.v:3893.251-3893.290" + cell $not $not$ls180.v:3893$387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:4024$486_Y + connect \Y $not$ls180.v:3893$387_Y end - attribute \src "ls180.v:4024.159-4024.292" - cell $not $not$ls180.v:4024$488 + attribute \src "ls180.v:3893.159-3893.292" + cell $not $not$ls180.v:3893$389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4024$487_Y - connect \Y $not$ls180.v:4024$488_Y + connect \A $and$ls180.v:3893$388_Y + connect \Y $not$ls180.v:3893$389_Y end - attribute \src "ls180.v:4087.71-4087.103" - cell $not $not$ls180.v:4087$527 + attribute \src "ls180.v:3956.71-3956.103" + cell $not $not$ls180.v:3956$428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_valid - connect \Y $not$ls180.v:4087$527_Y + connect \Y $not$ls180.v:3956$428_Y end - attribute \src "ls180.v:4108.112-4108.150" - cell $not $not$ls180.v:4108$530 + attribute \src "ls180.v:3977.112-3977.150" + cell $not $not$ls180.v:3977$431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:4108$530_Y + connect \Y $not$ls180.v:3977$431_Y end - attribute \src "ls180.v:4108.156-4108.193" - cell $not $not$ls180.v:4108$532 + attribute \src "ls180.v:3977.156-3977.193" + cell $not $not$ls180.v:3977$433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:4108$532_Y + connect \Y $not$ls180.v:3977$433_Y end - attribute \src "ls180.v:4108.68-4108.195" - cell $not $not$ls180.v:4108$534 + attribute \src "ls180.v:3977.68-3977.195" + cell $not $not$ls180.v:3977$435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4108$533_Y - connect \Y $not$ls180.v:4108$534_Y + connect \A $and$ls180.v:3977$434_Y + connect \Y $not$ls180.v:3977$435_Y end - attribute \src "ls180.v:4116.11-4116.38" - cell $not $not$ls180.v:4116$537 + attribute \src "ls180.v:3985.11-3985.38" + cell $not $not$ls180.v:3985$438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_write_available - connect \Y $not$ls180.v:4116$537_Y + connect \Y $not$ls180.v:3985$438_Y end - attribute \src "ls180.v:4146.112-4146.150" - cell $not $not$ls180.v:4146$539 + attribute \src "ls180.v:4015.112-4015.150" + cell $not $not$ls180.v:4015$440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:4146$539_Y + connect \Y $not$ls180.v:4015$440_Y end - attribute \src "ls180.v:4146.156-4146.193" - cell $not $not$ls180.v:4146$541 + attribute \src "ls180.v:4015.156-4015.193" + cell $not $not$ls180.v:4015$442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:4146$541_Y + connect \Y $not$ls180.v:4015$442_Y end - attribute \src "ls180.v:4146.68-4146.195" - cell $not $not$ls180.v:4146$543 + attribute \src "ls180.v:4015.68-4015.195" + cell $not $not$ls180.v:4015$444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4146$542_Y - connect \Y $not$ls180.v:4146$543_Y + connect \A $and$ls180.v:4015$443_Y + connect \Y $not$ls180.v:4015$444_Y end - attribute \src "ls180.v:4154.11-4154.37" - cell $not $not$ls180.v:4154$546 + attribute \src "ls180.v:4023.11-4023.37" + cell $not $not$ls180.v:4023$447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_read_available - connect \Y $not$ls180.v:4154$546_Y + connect \Y $not$ls180.v:4023$447_Y end - attribute \src "ls180.v:4164.87-4164.331" - cell $not $not$ls180.v:4164$558 + attribute \src "ls180.v:4033.87-4033.331" + cell $not $not$ls180.v:4033$459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4164$557_Y - connect \Y $not$ls180.v:4164$558_Y + connect \A $or$ls180.v:4033$458_Y + connect \Y $not$ls180.v:4033$459_Y end - attribute \src "ls180.v:4165.35-4165.68" - cell $not $not$ls180.v:4165$561 + attribute \src "ls180.v:4034.35-4034.68" + cell $not $not$ls180.v:4034$462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_valid - connect \Y $not$ls180.v:4165$561_Y + connect \Y $not$ls180.v:4034$462_Y end - attribute \src "ls180.v:4165.73-4165.105" - cell $not $not$ls180.v:4165$562 + attribute \src "ls180.v:4034.73-4034.105" + cell $not $not$ls180.v:4034$463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank0_lock - connect \Y $not$ls180.v:4165$562_Y + connect \Y $not$ls180.v:4034$463_Y end - attribute \src "ls180.v:4169.87-4169.331" - cell $not $not$ls180.v:4169$574 + attribute \src "ls180.v:4038.87-4038.331" + cell $not $not$ls180.v:4038$475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4169$573_Y - connect \Y $not$ls180.v:4169$574_Y + connect \A $or$ls180.v:4038$474_Y + connect \Y $not$ls180.v:4038$475_Y end - attribute \src "ls180.v:4170.35-4170.68" - cell $not $not$ls180.v:4170$577 + attribute \src "ls180.v:4039.35-4039.68" + cell $not $not$ls180.v:4039$478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_valid - connect \Y $not$ls180.v:4170$577_Y + connect \Y $not$ls180.v:4039$478_Y end - attribute \src "ls180.v:4170.73-4170.105" - cell $not $not$ls180.v:4170$578 + attribute \src "ls180.v:4039.73-4039.105" + cell $not $not$ls180.v:4039$479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank1_lock - connect \Y $not$ls180.v:4170$578_Y + connect \Y $not$ls180.v:4039$479_Y end - attribute \src "ls180.v:4174.87-4174.331" - cell $not $not$ls180.v:4174$590 + attribute \src "ls180.v:4043.87-4043.331" + cell $not $not$ls180.v:4043$491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4174$589_Y - connect \Y $not$ls180.v:4174$590_Y + connect \A $or$ls180.v:4043$490_Y + connect \Y $not$ls180.v:4043$491_Y end - attribute \src "ls180.v:4175.35-4175.68" - cell $not $not$ls180.v:4175$593 + attribute \src "ls180.v:4044.35-4044.68" + cell $not $not$ls180.v:4044$494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_valid - connect \Y $not$ls180.v:4175$593_Y + connect \Y $not$ls180.v:4044$494_Y end - attribute \src "ls180.v:4175.73-4175.105" - cell $not $not$ls180.v:4175$594 + attribute \src "ls180.v:4044.73-4044.105" + cell $not $not$ls180.v:4044$495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank2_lock - connect \Y $not$ls180.v:4175$594_Y + connect \Y $not$ls180.v:4044$495_Y end - attribute \src "ls180.v:4179.87-4179.331" - cell $not $not$ls180.v:4179$606 + attribute \src "ls180.v:4048.87-4048.331" + cell $not $not$ls180.v:4048$507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4179$605_Y - connect \Y $not$ls180.v:4179$606_Y + connect \A $or$ls180.v:4048$506_Y + connect \Y $not$ls180.v:4048$507_Y end - attribute \src "ls180.v:4180.35-4180.68" - cell $not $not$ls180.v:4180$609 + attribute \src "ls180.v:4049.35-4049.68" + cell $not $not$ls180.v:4049$510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_valid - connect \Y $not$ls180.v:4180$609_Y + connect \Y $not$ls180.v:4049$510_Y end - attribute \src "ls180.v:4180.73-4180.105" - cell $not $not$ls180.v:4180$610 + attribute \src "ls180.v:4049.73-4049.105" + cell $not $not$ls180.v:4049$511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_interface_bank3_lock - connect \Y $not$ls180.v:4180$610_Y + connect \Y $not$ls180.v:4049$511_Y end - attribute \src "ls180.v:4184.128-4184.372" - cell $not $not$ls180.v:4184$623 + attribute \src "ls180.v:4053.128-4053.372" + cell $not $not$ls180.v:4053$524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$622_Y - connect \Y $not$ls180.v:4184$623_Y + connect \A $or$ls180.v:4053$523_Y + connect \Y $not$ls180.v:4053$524_Y end - attribute \src "ls180.v:4184.502-4184.746" - cell $not $not$ls180.v:4184$639 + attribute \src "ls180.v:4053.502-4053.746" + cell $not $not$ls180.v:4053$540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$638_Y - connect \Y $not$ls180.v:4184$639_Y + connect \A $or$ls180.v:4053$539_Y + connect \Y $not$ls180.v:4053$540_Y end - attribute \src "ls180.v:4184.876-4184.1120" - cell $not $not$ls180.v:4184$655 + attribute \src "ls180.v:4053.876-4053.1120" + cell $not $not$ls180.v:4053$556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$654_Y - connect \Y $not$ls180.v:4184$655_Y + connect \A $or$ls180.v:4053$555_Y + connect \Y $not$ls180.v:4053$556_Y end - attribute \src "ls180.v:4184.1250-4184.1494" - cell $not $not$ls180.v:4184$671 + attribute \src "ls180.v:4053.1250-4053.1494" + cell $not $not$ls180.v:4053$572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$670_Y - connect \Y $not$ls180.v:4184$671_Y + connect \A $or$ls180.v:4053$571_Y + connect \Y $not$ls180.v:4053$572_Y end - attribute \src "ls180.v:4206.32-4206.50" - cell $not $not$ls180.v:4206$677 + attribute \src "ls180.v:4075.32-4075.50" + cell $not $not$ls180.v:4075$578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_cyc - connect \Y $not$ls180.v:4206$677_Y + connect \Y $not$ls180.v:4075$578_Y end - attribute \src "ls180.v:4245.30-4245.50" - cell $not $not$ls180.v:4245$682 + attribute \src "ls180.v:4114.30-4114.50" + cell $not $not$ls180.v:4114$583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter_skip - connect \Y $not$ls180.v:4245$682_Y + connect \Y $not$ls180.v:4114$583_Y end - attribute \src "ls180.v:4246.30-4246.50" - cell $not $not$ls180.v:4246$683 + attribute \src "ls180.v:4115.30-4115.50" + cell $not $not$ls180.v:4115$584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_converter_skip - connect \Y $not$ls180.v:4246$683_Y + connect \Y $not$ls180.v:4115$584_Y end - attribute \src "ls180.v:4271.27-4271.48" - cell $not $not$ls180.v:4271$689 + attribute \src "ls180.v:4140.27-4140.48" + cell $not $not$ls180.v:4140$590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_cyc - connect \Y $not$ls180.v:4271$689_Y + connect \Y $not$ls180.v:4140$590_Y end - attribute \src "ls180.v:4272.30-4272.50" - cell $not $not$ls180.v:4272$690 + attribute \src "ls180.v:4141.30-4141.50" + cell $not $not$ls180.v:4141$591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4272$690_Y + connect \Y $not$ls180.v:4141$591_Y end - attribute \src "ls180.v:4273.80-4273.98" - cell $not $not$ls180.v:4273$692 + attribute \src "ls180.v:4142.80-4142.98" + cell $not $not$ls180.v:4142$593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_cmd_consumed - connect \Y $not$ls180.v:4273$692_Y + connect \Y $not$ls180.v:4142$593_Y end - attribute \src "ls180.v:4274.107-4274.127" - cell $not $not$ls180.v:4274$696 + attribute \src "ls180.v:4143.107-4143.127" + cell $not $not$ls180.v:4143$597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_wdata_consumed - connect \Y $not$ls180.v:4274$696_Y + connect \Y $not$ls180.v:4143$597_Y end - attribute \src "ls180.v:4275.78-4275.103" - cell $not $not$ls180.v:4275$699 + attribute \src "ls180.v:4144.78-4144.103" + cell $not $not$ls180.v:4144$600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_port_cmd_payload_we - connect \Y $not$ls180.v:4275$699_Y + connect \Y $not$ls180.v:4144$600_Y end - attribute \src "ls180.v:4276.91-4276.111" - cell $not $not$ls180.v:4276$702 + attribute \src "ls180.v:4145.91-4145.111" + cell $not $not$ls180.v:4145$603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4276$702_Y + connect \Y $not$ls180.v:4145$603_Y end - attribute \src "ls180.v:4292.35-4292.64" - cell $not $not$ls180.v:4292$711 + attribute \src "ls180.v:4161.35-4161.64" + cell $not $not$ls180.v:4161$612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4292$711_Y + connect \Y $not$ls180.v:4161$612_Y end - attribute \src "ls180.v:4293.36-4293.67" - cell $not $not$ls180.v:4293$712 + attribute \src "ls180.v:4162.36-4162.67" + cell $not $not$ls180.v:4162$613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_source_valid - connect \Y $not$ls180.v:4293$712_Y + connect \Y $not$ls180.v:4162$613_Y end - attribute \src "ls180.v:4299.32-4299.61" - cell $not $not$ls180.v:4299$713 + attribute \src "ls180.v:4168.32-4168.61" + cell $not $not$ls180.v:4168$614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4299$713_Y + connect \Y $not$ls180.v:4168$614_Y end - attribute \src "ls180.v:4305.36-4305.67" - cell $not $not$ls180.v:4305$714 + attribute \src "ls180.v:4174.36-4174.67" + cell $not $not$ls180.v:4174$615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4305$714_Y + connect \Y $not$ls180.v:4174$615_Y end - attribute \src "ls180.v:4306.35-4306.64" - cell $not $not$ls180.v:4306$715 + attribute \src "ls180.v:4175.35-4175.64" + cell $not $not$ls180.v:4175$616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_sink_ready - connect \Y $not$ls180.v:4306$715_Y + connect \Y $not$ls180.v:4175$616_Y end - attribute \src "ls180.v:4309.32-4309.63" - cell $not $not$ls180.v:4309$718 + attribute \src "ls180.v:4178.32-4178.63" + cell $not $not$ls180.v:4178$619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4309$718_Y + connect \Y $not$ls180.v:4178$619_Y end - attribute \src "ls180.v:4347.81-4347.108" - cell $not $not$ls180.v:4347$728 + attribute \src "ls180.v:4216.81-4216.108" + cell $not $not$ls180.v:4216$629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_readable - connect \Y $not$ls180.v:4347$728_Y + connect \Y $not$ls180.v:4216$629_Y end - attribute \src "ls180.v:4377.81-4377.108" - cell $not $not$ls180.v:4377$739 + attribute \src "ls180.v:4246.81-4246.108" + cell $not $not$ls180.v:4246$640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_readable - connect \Y $not$ls180.v:4377$739_Y + connect \Y $not$ls180.v:4246$640_Y end - attribute \src "ls180.v:4588.60-4588.85" - cell $not $not$ls180.v:4588$790 + attribute \src "ls180.v:4457.60-4457.85" + cell $not $not$ls180.v:4457$691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk_d - connect \Y $not$ls180.v:4588$790_Y + connect \Y $not$ls180.v:4457$691_Y end - attribute \src "ls180.v:4729.54-4729.96" - cell $not $not$ls180.v:4729$804 + attribute \src "ls180.v:4598.54-4598.96" + cell $not $not$ls180.v:4598$705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \Y $not$ls180.v:4729$804_Y + connect \Y $not$ls180.v:4598$705_Y end - attribute \src "ls180.v:4732.48-4732.86" - cell $not $not$ls180.v:4732$807 + attribute \src "ls180.v:4601.48-4601.86" + cell $not $not$ls180.v:4601$708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:4732$807_Y + connect \Y $not$ls180.v:4601$708_Y end - attribute \src "ls180.v:4856.55-4856.98" - cell $not $not$ls180.v:4856$825 + attribute \src "ls180.v:4725.55-4725.98" + cell $not $not$ls180.v:4725$726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_strobe_all - connect \Y $not$ls180.v:4856$825_Y + connect \Y $not$ls180.v:4725$726_Y end - attribute \src "ls180.v:4859.49-4859.88" - cell $not $not$ls180.v:4859$828 + attribute \src "ls180.v:4728.49-4728.88" + cell $not $not$ls180.v:4728$729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:4859$828_Y + connect \Y $not$ls180.v:4728$729_Y end - attribute \src "ls180.v:4909.30-4909.58" - cell $not $not$ls180.v:4909$834 + attribute \src "ls180.v:4778.30-4778.58" + cell $not $not$ls180.v:4778$735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_sink_valid - connect \Y $not$ls180.v:4909$834_Y + connect \Y $not$ls180.v:4778$735_Y end - attribute \src "ls180.v:4990.56-4990.100" - cell $not $not$ls180.v:4990$840 + attribute \src "ls180.v:4859.56-4859.100" + cell $not $not$ls180.v:4859$741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_strobe_all - connect \Y $not$ls180.v:4990$840_Y + connect \Y $not$ls180.v:4859$741_Y end - attribute \src "ls180.v:4993.50-4993.90" - cell $not $not$ls180.v:4993$843 + attribute \src "ls180.v:4862.50-4862.90" + cell $not $not$ls180.v:4862$744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:4993$843_Y + connect \Y $not$ls180.v:4862$744_Y end - attribute \src "ls180.v:5109.42-5109.74" - cell $not $not$ls180.v:5109$859 + attribute \src "ls180.v:4978.42-4978.74" + cell $not $not$ls180.v:4978$760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_valid - connect \Y $not$ls180.v:5109$859_Y + connect \Y $not$ls180.v:4978$760_Y end - attribute \src "ls180.v:5633.50-5633.88" - cell $not $not$ls180.v:5633$1144 + attribute \src "ls180.v:5502.50-5502.88" + cell $not $not$ls180.v:5502$1045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_strobe_all - connect \Y $not$ls180.v:5633$1144_Y + connect \Y $not$ls180.v:5502$1045_Y end - attribute \src "ls180.v:5645.52-5645.102" - cell $not $not$ls180.v:5645$1147 + attribute \src "ls180.v:5514.52-5514.102" + cell $not $not$ls180.v:5514$1048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \Y $not$ls180.v:5645$1147_Y + connect \Y $not$ls180.v:5514$1048_Y end - attribute \src "ls180.v:5704.38-5704.74" - cell $not $not$ls180.v:5704$1154 + attribute \src "ls180.v:5573.38-5573.74" + cell $not $not$ls180.v:5573$1055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_dma_enable_storage - connect \Y $not$ls180.v:5704$1154_Y + connect \Y $not$ls180.v:5573$1055_Y end - attribute \src "ls180.v:6030.69-6030.88" - cell $not $not$ls180.v:6030$1239 + attribute \src "ls180.v:5836.69-5836.88" + cell $not $not$ls180.v:5836$1119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_shared_ack - connect \Y $not$ls180.v:6030$1239_Y + connect \Y $not$ls180.v:5836$1119_Y end - attribute \src "ls180.v:6047.63-6047.94" - cell $not $not$ls180.v:6047$1284 + attribute \src "ls180.v:5853.63-5853.94" + cell $not $not$ls180.v:5853$1143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6047$1284_Y + connect \Y $not$ls180.v:5853$1143_Y end - attribute \src "ls180.v:6050.65-6050.96" - cell $not $not$ls180.v:6050$1291 + attribute \src "ls180.v:5856.65-5856.96" + cell $not $not$ls180.v:5856$1150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6050$1291_Y + connect \Y $not$ls180.v:5856$1150_Y end - attribute \src "ls180.v:6053.65-6053.96" - cell $not $not$ls180.v:6053$1298 + attribute \src "ls180.v:5859.65-5859.96" + cell $not $not$ls180.v:5859$1157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6053$1298_Y + connect \Y $not$ls180.v:5859$1157_Y end - attribute \src "ls180.v:6056.65-6056.96" - cell $not $not$ls180.v:6056$1305 + attribute \src "ls180.v:5862.65-5862.96" + cell $not $not$ls180.v:5862$1164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6056$1305_Y + connect \Y $not$ls180.v:5862$1164_Y end - attribute \src "ls180.v:6059.65-6059.96" - cell $not $not$ls180.v:6059$1312 + attribute \src "ls180.v:5865.65-5865.96" + cell $not $not$ls180.v:5865$1171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6059$1312_Y + connect \Y $not$ls180.v:5865$1171_Y end - attribute \src "ls180.v:6062.68-6062.99" - cell $not $not$ls180.v:6062$1319 + attribute \src "ls180.v:5868.68-5868.99" + cell $not $not$ls180.v:5868$1178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6062$1319_Y + connect \Y $not$ls180.v:5868$1178_Y end - attribute \src "ls180.v:6065.68-6065.99" - cell $not $not$ls180.v:6065$1326 + attribute \src "ls180.v:5871.68-5871.99" + cell $not $not$ls180.v:5871$1185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6065$1326_Y + connect \Y $not$ls180.v:5871$1185_Y end - attribute \src "ls180.v:6068.68-6068.99" - cell $not $not$ls180.v:6068$1333 + attribute \src "ls180.v:5874.68-5874.99" + cell $not $not$ls180.v:5874$1192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6068$1333_Y + connect \Y $not$ls180.v:5874$1192_Y end - attribute \src "ls180.v:6071.68-6071.99" - cell $not $not$ls180.v:6071$1340 + attribute \src "ls180.v:5877.68-5877.99" + cell $not $not$ls180.v:5877$1199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:6071$1340_Y + connect \Y $not$ls180.v:5877$1199_Y end - attribute \src "ls180.v:6085.60-6085.91" - cell $not $not$ls180.v:6085$1348 + attribute \src "ls180.v:5891.60-5891.91" + cell $not $not$ls180.v:5891$1207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6085$1348_Y + connect \Y $not$ls180.v:5891$1207_Y end - attribute \src "ls180.v:6088.60-6088.91" - cell $not $not$ls180.v:6088$1355 + attribute \src "ls180.v:5894.60-5894.91" + cell $not $not$ls180.v:5894$1214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6088$1355_Y + connect \Y $not$ls180.v:5894$1214_Y end - attribute \src "ls180.v:6091.60-6091.91" - cell $not $not$ls180.v:6091$1362 + attribute \src "ls180.v:5897.60-5897.91" + cell $not $not$ls180.v:5897$1221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6091$1362_Y + connect \Y $not$ls180.v:5897$1221_Y end - attribute \src "ls180.v:6094.60-6094.91" - cell $not $not$ls180.v:6094$1369 + attribute \src "ls180.v:5900.60-5900.91" + cell $not $not$ls180.v:5900$1228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6094$1369_Y + connect \Y $not$ls180.v:5900$1228_Y end - attribute \src "ls180.v:6097.61-6097.92" - cell $not $not$ls180.v:6097$1376 + attribute \src "ls180.v:5903.61-5903.92" + cell $not $not$ls180.v:5903$1235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6097$1376_Y + connect \Y $not$ls180.v:5903$1235_Y end - attribute \src "ls180.v:6100.61-6100.92" - cell $not $not$ls180.v:6100$1383 + attribute \src "ls180.v:5906.61-5906.92" + cell $not $not$ls180.v:5906$1242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:6100$1383_Y + connect \Y $not$ls180.v:5906$1242_Y end - attribute \src "ls180.v:6111.59-6111.90" - cell $not $not$ls180.v:6111$1391 + attribute \src "ls180.v:5917.59-5917.90" + cell $not $not$ls180.v:5917$1250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:6111$1391_Y + connect \Y $not$ls180.v:5917$1250_Y end - attribute \src "ls180.v:6114.58-6114.89" - cell $not $not$ls180.v:6114$1398 + attribute \src "ls180.v:5920.58-5920.89" + cell $not $not$ls180.v:5920$1257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:6114$1398_Y + connect \Y $not$ls180.v:5920$1257_Y end - attribute \src "ls180.v:6125.64-6125.95" - cell $not $not$ls180.v:6125$1406 + attribute \src "ls180.v:5931.64-5931.95" + cell $not $not$ls180.v:5931$1265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6125$1406_Y + connect \Y $not$ls180.v:5931$1265_Y end - attribute \src "ls180.v:6128.63-6128.94" - cell $not $not$ls180.v:6128$1413 + attribute \src "ls180.v:5934.63-5934.94" + cell $not $not$ls180.v:5934$1272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6128$1413_Y + connect \Y $not$ls180.v:5934$1272_Y end - attribute \src "ls180.v:6131.63-6131.94" - cell $not $not$ls180.v:6131$1420 + attribute \src "ls180.v:5937.63-5937.94" + cell $not $not$ls180.v:5937$1279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6131$1420_Y + connect \Y $not$ls180.v:5937$1279_Y end - attribute \src "ls180.v:6134.63-6134.94" - cell $not $not$ls180.v:6134$1427 + attribute \src "ls180.v:5940.63-5940.94" + cell $not $not$ls180.v:5940$1286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6134$1427_Y + connect \Y $not$ls180.v:5940$1286_Y end - attribute \src "ls180.v:6137.63-6137.94" - cell $not $not$ls180.v:6137$1434 + attribute \src "ls180.v:5943.63-5943.94" + cell $not $not$ls180.v:5943$1293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6137$1434_Y + connect \Y $not$ls180.v:5943$1293_Y end - attribute \src "ls180.v:6140.64-6140.95" - cell $not $not$ls180.v:6140$1441 + attribute \src "ls180.v:5946.64-5946.95" + cell $not $not$ls180.v:5946$1300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6140$1441_Y + connect \Y $not$ls180.v:5946$1300_Y end - attribute \src "ls180.v:6143.64-6143.95" - cell $not $not$ls180.v:6143$1448 + attribute \src "ls180.v:5949.64-5949.95" + cell $not $not$ls180.v:5949$1307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6143$1448_Y + connect \Y $not$ls180.v:5949$1307_Y end - attribute \src "ls180.v:6146.64-6146.95" - cell $not $not$ls180.v:6146$1455 + attribute \src "ls180.v:5952.64-5952.95" + cell $not $not$ls180.v:5952$1314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6146$1455_Y + connect \Y $not$ls180.v:5952$1314_Y end - attribute \src "ls180.v:6149.64-6149.95" - cell $not $not$ls180.v:6149$1462 + attribute \src "ls180.v:5955.64-5955.95" + cell $not $not$ls180.v:5955$1321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:6149$1462_Y + connect \Y $not$ls180.v:5955$1321_Y end - attribute \src "ls180.v:6162.64-6162.95" - cell $not $not$ls180.v:6162$1470 + attribute \src "ls180.v:5968.64-5968.95" + cell $not $not$ls180.v:5968$1329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6162$1470_Y + connect \Y $not$ls180.v:5968$1329_Y end - attribute \src "ls180.v:6165.63-6165.94" - cell $not $not$ls180.v:6165$1477 + attribute \src "ls180.v:5971.63-5971.94" + cell $not $not$ls180.v:5971$1336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6165$1477_Y + connect \Y $not$ls180.v:5971$1336_Y end - attribute \src "ls180.v:6168.63-6168.94" - cell $not $not$ls180.v:6168$1484 + attribute \src "ls180.v:5974.63-5974.94" + cell $not $not$ls180.v:5974$1343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6168$1484_Y + connect \Y $not$ls180.v:5974$1343_Y end - attribute \src "ls180.v:6171.63-6171.94" - cell $not $not$ls180.v:6171$1491 + attribute \src "ls180.v:5977.63-5977.94" + cell $not $not$ls180.v:5977$1350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6171$1491_Y + connect \Y $not$ls180.v:5977$1350_Y end - attribute \src "ls180.v:6174.63-6174.94" - cell $not $not$ls180.v:6174$1498 + attribute \src "ls180.v:5980.63-5980.94" + cell $not $not$ls180.v:5980$1357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6174$1498_Y + connect \Y $not$ls180.v:5980$1357_Y end - attribute \src "ls180.v:6177.64-6177.95" - cell $not $not$ls180.v:6177$1505 + attribute \src "ls180.v:5983.64-5983.95" + cell $not $not$ls180.v:5983$1364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6177$1505_Y + connect \Y $not$ls180.v:5983$1364_Y end - attribute \src "ls180.v:6180.64-6180.95" - cell $not $not$ls180.v:6180$1512 + attribute \src "ls180.v:5986.64-5986.95" + cell $not $not$ls180.v:5986$1371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6180$1512_Y + connect \Y $not$ls180.v:5986$1371_Y end - attribute \src "ls180.v:6183.64-6183.95" - cell $not $not$ls180.v:6183$1519 + attribute \src "ls180.v:5989.64-5989.95" + cell $not $not$ls180.v:5989$1378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6183$1519_Y + connect \Y $not$ls180.v:5989$1378_Y end - attribute \src "ls180.v:6186.64-6186.95" - cell $not $not$ls180.v:6186$1526 + attribute \src "ls180.v:5992.64-5992.95" + cell $not $not$ls180.v:5992$1385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:6186$1526_Y + connect \Y $not$ls180.v:5992$1385_Y end - attribute \src "ls180.v:6199.66-6199.97" - cell $not $not$ls180.v:6199$1534 + attribute \src "ls180.v:6005.66-6005.97" + cell $not $not$ls180.v:6005$1393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6199$1534_Y + connect \Y $not$ls180.v:6005$1393_Y end - attribute \src "ls180.v:6202.66-6202.97" - cell $not $not$ls180.v:6202$1541 + attribute \src "ls180.v:6008.66-6008.97" + cell $not $not$ls180.v:6008$1400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6202$1541_Y + connect \Y $not$ls180.v:6008$1400_Y end - attribute \src "ls180.v:6205.66-6205.97" - cell $not $not$ls180.v:6205$1548 + attribute \src "ls180.v:6011.66-6011.97" + cell $not $not$ls180.v:6011$1407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6205$1548_Y + connect \Y $not$ls180.v:6011$1407_Y end - attribute \src "ls180.v:6208.66-6208.97" - cell $not $not$ls180.v:6208$1555 + attribute \src "ls180.v:6014.66-6014.97" + cell $not $not$ls180.v:6014$1414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6208$1555_Y + connect \Y $not$ls180.v:6014$1414_Y end - attribute \src "ls180.v:6211.66-6211.97" - cell $not $not$ls180.v:6211$1562 + attribute \src "ls180.v:6017.66-6017.97" + cell $not $not$ls180.v:6017$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6211$1562_Y + connect \Y $not$ls180.v:6017$1421_Y end - attribute \src "ls180.v:6214.66-6214.97" - cell $not $not$ls180.v:6214$1569 + attribute \src "ls180.v:6020.66-6020.97" + cell $not $not$ls180.v:6020$1428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6214$1569_Y + connect \Y $not$ls180.v:6020$1428_Y end - attribute \src "ls180.v:6217.66-6217.97" - cell $not $not$ls180.v:6217$1576 + attribute \src "ls180.v:6023.66-6023.97" + cell $not $not$ls180.v:6023$1435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6217$1576_Y + connect \Y $not$ls180.v:6023$1435_Y end - attribute \src "ls180.v:6220.66-6220.97" - cell $not $not$ls180.v:6220$1583 + attribute \src "ls180.v:6026.66-6026.97" + cell $not $not$ls180.v:6026$1442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6220$1583_Y + connect \Y $not$ls180.v:6026$1442_Y end - attribute \src "ls180.v:6223.68-6223.99" - cell $not $not$ls180.v:6223$1590 + attribute \src "ls180.v:6029.68-6029.99" + cell $not $not$ls180.v:6029$1449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6223$1590_Y + connect \Y $not$ls180.v:6029$1449_Y end - attribute \src "ls180.v:6226.68-6226.99" - cell $not $not$ls180.v:6226$1597 + attribute \src "ls180.v:6032.68-6032.99" + cell $not $not$ls180.v:6032$1456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6226$1597_Y + connect \Y $not$ls180.v:6032$1456_Y end - attribute \src "ls180.v:6229.68-6229.99" - cell $not $not$ls180.v:6229$1604 + attribute \src "ls180.v:6035.68-6035.99" + cell $not $not$ls180.v:6035$1463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6229$1604_Y + connect \Y $not$ls180.v:6035$1463_Y end - attribute \src "ls180.v:6232.68-6232.99" - cell $not $not$ls180.v:6232$1611 + attribute \src "ls180.v:6038.68-6038.99" + cell $not $not$ls180.v:6038$1470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6232$1611_Y + connect \Y $not$ls180.v:6038$1470_Y end - attribute \src "ls180.v:6235.68-6235.99" - cell $not $not$ls180.v:6235$1618 + attribute \src "ls180.v:6041.68-6041.99" + cell $not $not$ls180.v:6041$1477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6235$1618_Y + connect \Y $not$ls180.v:6041$1477_Y end - attribute \src "ls180.v:6238.65-6238.96" - cell $not $not$ls180.v:6238$1625 + attribute \src "ls180.v:6044.65-6044.96" + cell $not $not$ls180.v:6044$1484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6238$1625_Y + connect \Y $not$ls180.v:6044$1484_Y end - attribute \src "ls180.v:6241.66-6241.97" - cell $not $not$ls180.v:6241$1632 + attribute \src "ls180.v:6047.66-6047.97" + cell $not $not$ls180.v:6047$1491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6241$1632_Y + connect \Y $not$ls180.v:6047$1491_Y end - attribute \src "ls180.v:6261.70-6261.101" - cell $not $not$ls180.v:6261$1640 + attribute \src "ls180.v:6067.70-6067.101" + cell $not $not$ls180.v:6067$1499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6261$1640_Y + connect \Y $not$ls180.v:6067$1499_Y end - attribute \src "ls180.v:6264.70-6264.101" - cell $not $not$ls180.v:6264$1647 + attribute \src "ls180.v:6070.70-6070.101" + cell $not $not$ls180.v:6070$1506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6264$1647_Y + connect \Y $not$ls180.v:6070$1506_Y end - attribute \src "ls180.v:6267.70-6267.101" - cell $not $not$ls180.v:6267$1654 + attribute \src "ls180.v:6073.70-6073.101" + cell $not $not$ls180.v:6073$1513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6267$1654_Y + connect \Y $not$ls180.v:6073$1513_Y end - attribute \src "ls180.v:6270.70-6270.101" - cell $not $not$ls180.v:6270$1661 + attribute \src "ls180.v:6076.70-6076.101" + cell $not $not$ls180.v:6076$1520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6270$1661_Y + connect \Y $not$ls180.v:6076$1520_Y end - attribute \src "ls180.v:6273.69-6273.100" - cell $not $not$ls180.v:6273$1668 + attribute \src "ls180.v:6079.69-6079.100" + cell $not $not$ls180.v:6079$1527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6273$1668_Y + connect \Y $not$ls180.v:6079$1527_Y end - attribute \src "ls180.v:6276.69-6276.100" - cell $not $not$ls180.v:6276$1675 + attribute \src "ls180.v:6082.69-6082.100" + cell $not $not$ls180.v:6082$1534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6276$1675_Y + connect \Y $not$ls180.v:6082$1534_Y end - attribute \src "ls180.v:6279.69-6279.100" - cell $not $not$ls180.v:6279$1682 + attribute \src "ls180.v:6085.69-6085.100" + cell $not $not$ls180.v:6085$1541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6279$1682_Y + connect \Y $not$ls180.v:6085$1541_Y end - attribute \src "ls180.v:6282.69-6282.100" - cell $not $not$ls180.v:6282$1689 + attribute \src "ls180.v:6088.69-6088.100" + cell $not $not$ls180.v:6088$1548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6282$1689_Y + connect \Y $not$ls180.v:6088$1548_Y end - attribute \src "ls180.v:6285.60-6285.91" - cell $not $not$ls180.v:6285$1696 + attribute \src "ls180.v:6091.60-6091.91" + cell $not $not$ls180.v:6091$1555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6285$1696_Y + connect \Y $not$ls180.v:6091$1555_Y end - attribute \src "ls180.v:6288.71-6288.102" - cell $not $not$ls180.v:6288$1703 + attribute \src "ls180.v:6094.71-6094.102" + cell $not $not$ls180.v:6094$1562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6288$1703_Y + connect \Y $not$ls180.v:6094$1562_Y end - attribute \src "ls180.v:6291.71-6291.102" - cell $not $not$ls180.v:6291$1710 + attribute \src "ls180.v:6097.71-6097.102" + cell $not $not$ls180.v:6097$1569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6291$1710_Y + connect \Y $not$ls180.v:6097$1569_Y end - attribute \src "ls180.v:6294.71-6294.102" - cell $not $not$ls180.v:6294$1717 + attribute \src "ls180.v:6100.71-6100.102" + cell $not $not$ls180.v:6100$1576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6294$1717_Y + connect \Y $not$ls180.v:6100$1576_Y end - attribute \src "ls180.v:6297.71-6297.102" - cell $not $not$ls180.v:6297$1724 + attribute \src "ls180.v:6103.71-6103.102" + cell $not $not$ls180.v:6103$1583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6297$1724_Y + connect \Y $not$ls180.v:6103$1583_Y end - attribute \src "ls180.v:6300.71-6300.102" - cell $not $not$ls180.v:6300$1731 + attribute \src "ls180.v:6106.71-6106.102" + cell $not $not$ls180.v:6106$1590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6300$1731_Y + connect \Y $not$ls180.v:6106$1590_Y end - attribute \src "ls180.v:6303.71-6303.102" - cell $not $not$ls180.v:6303$1738 + attribute \src "ls180.v:6109.71-6109.102" + cell $not $not$ls180.v:6109$1597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6303$1738_Y + connect \Y $not$ls180.v:6109$1597_Y end - attribute \src "ls180.v:6306.70-6306.101" - cell $not $not$ls180.v:6306$1745 + attribute \src "ls180.v:6112.70-6112.101" + cell $not $not$ls180.v:6112$1604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6306$1745_Y + connect \Y $not$ls180.v:6112$1604_Y end - attribute \src "ls180.v:6309.70-6309.101" - cell $not $not$ls180.v:6309$1752 + attribute \src "ls180.v:6115.70-6115.101" + cell $not $not$ls180.v:6115$1611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6309$1752_Y + connect \Y $not$ls180.v:6115$1611_Y end - attribute \src "ls180.v:6312.70-6312.101" - cell $not $not$ls180.v:6312$1759 + attribute \src "ls180.v:6118.70-6118.101" + cell $not $not$ls180.v:6118$1618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6312$1759_Y + connect \Y $not$ls180.v:6118$1618_Y end - attribute \src "ls180.v:6315.70-6315.101" - cell $not $not$ls180.v:6315$1766 + attribute \src "ls180.v:6121.70-6121.101" + cell $not $not$ls180.v:6121$1625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6315$1766_Y + connect \Y $not$ls180.v:6121$1625_Y end - attribute \src "ls180.v:6318.70-6318.101" - cell $not $not$ls180.v:6318$1773 + attribute \src "ls180.v:6124.70-6124.101" + cell $not $not$ls180.v:6124$1632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6318$1773_Y + connect \Y $not$ls180.v:6124$1632_Y end - attribute \src "ls180.v:6321.70-6321.101" - cell $not $not$ls180.v:6321$1780 + attribute \src "ls180.v:6127.70-6127.101" + cell $not $not$ls180.v:6127$1639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6321$1780_Y + connect \Y $not$ls180.v:6127$1639_Y end - attribute \src "ls180.v:6324.70-6324.101" - cell $not $not$ls180.v:6324$1787 + attribute \src "ls180.v:6130.70-6130.101" + cell $not $not$ls180.v:6130$1646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6324$1787_Y + connect \Y $not$ls180.v:6130$1646_Y end - attribute \src "ls180.v:6327.70-6327.101" - cell $not $not$ls180.v:6327$1794 + attribute \src "ls180.v:6133.70-6133.101" + cell $not $not$ls180.v:6133$1653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6327$1794_Y + connect \Y $not$ls180.v:6133$1653_Y end - attribute \src "ls180.v:6330.70-6330.101" - cell $not $not$ls180.v:6330$1801 + attribute \src "ls180.v:6136.70-6136.101" + cell $not $not$ls180.v:6136$1660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6330$1801_Y + connect \Y $not$ls180.v:6136$1660_Y end - attribute \src "ls180.v:6333.70-6333.101" - cell $not $not$ls180.v:6333$1808 + attribute \src "ls180.v:6139.70-6139.101" + cell $not $not$ls180.v:6139$1667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6333$1808_Y + connect \Y $not$ls180.v:6139$1667_Y end - attribute \src "ls180.v:6336.66-6336.97" - cell $not $not$ls180.v:6336$1815 + attribute \src "ls180.v:6142.66-6142.97" + cell $not $not$ls180.v:6142$1674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6336$1815_Y + connect \Y $not$ls180.v:6142$1674_Y end - attribute \src "ls180.v:6339.67-6339.98" - cell $not $not$ls180.v:6339$1822 + attribute \src "ls180.v:6145.67-6145.98" + cell $not $not$ls180.v:6145$1681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6339$1822_Y + connect \Y $not$ls180.v:6145$1681_Y end - attribute \src "ls180.v:6342.70-6342.101" - cell $not $not$ls180.v:6342$1829 + attribute \src "ls180.v:6148.70-6148.101" + cell $not $not$ls180.v:6148$1688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6342$1829_Y + connect \Y $not$ls180.v:6148$1688_Y end - attribute \src "ls180.v:6345.70-6345.101" - cell $not $not$ls180.v:6345$1836 + attribute \src "ls180.v:6151.70-6151.101" + cell $not $not$ls180.v:6151$1695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6345$1836_Y + connect \Y $not$ls180.v:6151$1695_Y end - attribute \src "ls180.v:6348.69-6348.100" - cell $not $not$ls180.v:6348$1843 + attribute \src "ls180.v:6154.69-6154.100" + cell $not $not$ls180.v:6154$1702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6348$1843_Y + connect \Y $not$ls180.v:6154$1702_Y end - attribute \src "ls180.v:6351.69-6351.100" - cell $not $not$ls180.v:6351$1850 + attribute \src "ls180.v:6157.69-6157.100" + cell $not $not$ls180.v:6157$1709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6351$1850_Y + connect \Y $not$ls180.v:6157$1709_Y end - attribute \src "ls180.v:6354.69-6354.100" - cell $not $not$ls180.v:6354$1857 + attribute \src "ls180.v:6160.69-6160.100" + cell $not $not$ls180.v:6160$1716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6354$1857_Y + connect \Y $not$ls180.v:6160$1716_Y end - attribute \src "ls180.v:6357.69-6357.100" - cell $not $not$ls180.v:6357$1864 + attribute \src "ls180.v:6163.69-6163.100" + cell $not $not$ls180.v:6163$1723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6357$1864_Y + connect \Y $not$ls180.v:6163$1723_Y end - attribute \src "ls180.v:6396.66-6396.97" - cell $not $not$ls180.v:6396$1872 + attribute \src "ls180.v:6202.66-6202.97" + cell $not $not$ls180.v:6202$1731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6396$1872_Y + connect \Y $not$ls180.v:6202$1731_Y end - attribute \src "ls180.v:6399.66-6399.97" - cell $not $not$ls180.v:6399$1879 + attribute \src "ls180.v:6205.66-6205.97" + cell $not $not$ls180.v:6205$1738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6399$1879_Y + connect \Y $not$ls180.v:6205$1738_Y end - attribute \src "ls180.v:6402.66-6402.97" - cell $not $not$ls180.v:6402$1886 + attribute \src "ls180.v:6208.66-6208.97" + cell $not $not$ls180.v:6208$1745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6402$1886_Y + connect \Y $not$ls180.v:6208$1745_Y end - attribute \src "ls180.v:6405.66-6405.97" - cell $not $not$ls180.v:6405$1893 + attribute \src "ls180.v:6211.66-6211.97" + cell $not $not$ls180.v:6211$1752 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6405$1893_Y + connect \Y $not$ls180.v:6211$1752_Y end - attribute \src "ls180.v:6408.66-6408.97" - cell $not $not$ls180.v:6408$1900 + attribute \src "ls180.v:6214.66-6214.97" + cell $not $not$ls180.v:6214$1759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6408$1900_Y + connect \Y $not$ls180.v:6214$1759_Y end - attribute \src "ls180.v:6411.66-6411.97" - cell $not $not$ls180.v:6411$1907 + attribute \src "ls180.v:6217.66-6217.97" + cell $not $not$ls180.v:6217$1766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6411$1907_Y + connect \Y $not$ls180.v:6217$1766_Y end - attribute \src "ls180.v:6414.66-6414.97" - cell $not $not$ls180.v:6414$1914 + attribute \src "ls180.v:6220.66-6220.97" + cell $not $not$ls180.v:6220$1773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6414$1914_Y + connect \Y $not$ls180.v:6220$1773_Y end - attribute \src "ls180.v:6417.66-6417.97" - cell $not $not$ls180.v:6417$1921 + attribute \src "ls180.v:6223.66-6223.97" + cell $not $not$ls180.v:6223$1780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6417$1921_Y + connect \Y $not$ls180.v:6223$1780_Y end - attribute \src "ls180.v:6420.68-6420.99" - cell $not $not$ls180.v:6420$1928 + attribute \src "ls180.v:6226.68-6226.99" + cell $not $not$ls180.v:6226$1787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6420$1928_Y + connect \Y $not$ls180.v:6226$1787_Y end - attribute \src "ls180.v:6423.68-6423.99" - cell $not $not$ls180.v:6423$1935 + attribute \src "ls180.v:6229.68-6229.99" + cell $not $not$ls180.v:6229$1794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6423$1935_Y + connect \Y $not$ls180.v:6229$1794_Y end - attribute \src "ls180.v:6426.68-6426.99" - cell $not $not$ls180.v:6426$1942 + attribute \src "ls180.v:6232.68-6232.99" + cell $not $not$ls180.v:6232$1801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6426$1942_Y + connect \Y $not$ls180.v:6232$1801_Y end - attribute \src "ls180.v:6429.68-6429.99" - cell $not $not$ls180.v:6429$1949 + attribute \src "ls180.v:6235.68-6235.99" + cell $not $not$ls180.v:6235$1808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6429$1949_Y + connect \Y $not$ls180.v:6235$1808_Y end - attribute \src "ls180.v:6432.68-6432.99" - cell $not $not$ls180.v:6432$1956 + attribute \src "ls180.v:6238.68-6238.99" + cell $not $not$ls180.v:6238$1815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6432$1956_Y + connect \Y $not$ls180.v:6238$1815_Y end - attribute \src "ls180.v:6435.65-6435.96" - cell $not $not$ls180.v:6435$1963 + attribute \src "ls180.v:6241.65-6241.96" + cell $not $not$ls180.v:6241$1822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6435$1963_Y + connect \Y $not$ls180.v:6241$1822_Y end - attribute \src "ls180.v:6438.66-6438.97" - cell $not $not$ls180.v:6438$1970 + attribute \src "ls180.v:6244.66-6244.97" + cell $not $not$ls180.v:6244$1829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6438$1970_Y + connect \Y $not$ls180.v:6244$1829_Y end - attribute \src "ls180.v:6441.68-6441.99" - cell $not $not$ls180.v:6441$1977 + attribute \src "ls180.v:6247.68-6247.99" + cell $not $not$ls180.v:6247$1836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6441$1977_Y + connect \Y $not$ls180.v:6247$1836_Y end - attribute \src "ls180.v:6444.68-6444.99" - cell $not $not$ls180.v:6444$1984 + attribute \src "ls180.v:6250.68-6250.99" + cell $not $not$ls180.v:6250$1843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6444$1984_Y + connect \Y $not$ls180.v:6250$1843_Y end - attribute \src "ls180.v:6447.68-6447.99" - cell $not $not$ls180.v:6447$1991 + attribute \src "ls180.v:6253.68-6253.99" + cell $not $not$ls180.v:6253$1850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6447$1991_Y + connect \Y $not$ls180.v:6253$1850_Y end - attribute \src "ls180.v:6450.68-6450.99" - cell $not $not$ls180.v:6450$1998 + attribute \src "ls180.v:6256.68-6256.99" + cell $not $not$ls180.v:6256$1857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6450$1998_Y + connect \Y $not$ls180.v:6256$1857_Y end - attribute \src "ls180.v:6475.68-6475.99" - cell $not $not$ls180.v:6475$2006 + attribute \src "ls180.v:6281.68-6281.99" + cell $not $not$ls180.v:6281$1865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6475$2006_Y + connect \Y $not$ls180.v:6281$1865_Y end - attribute \src "ls180.v:6478.73-6478.104" - cell $not $not$ls180.v:6478$2013 + attribute \src "ls180.v:6284.73-6284.104" + cell $not $not$ls180.v:6284$1872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6478$2013_Y + connect \Y $not$ls180.v:6284$1872_Y end - attribute \src "ls180.v:6481.73-6481.104" - cell $not $not$ls180.v:6481$2020 + attribute \src "ls180.v:6287.73-6287.104" + cell $not $not$ls180.v:6287$1879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6481$2020_Y + connect \Y $not$ls180.v:6287$1879_Y end - attribute \src "ls180.v:6484.66-6484.97" - cell $not $not$ls180.v:6484$2027 + attribute \src "ls180.v:6290.66-6290.97" + cell $not $not$ls180.v:6290$1886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6484$2027_Y + connect \Y $not$ls180.v:6290$1886_Y end - attribute \src "ls180.v:6492.70-6492.101" - cell $not $not$ls180.v:6492$2035 + attribute \src "ls180.v:6298.70-6298.101" + cell $not $not$ls180.v:6298$1894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6492$2035_Y + connect \Y $not$ls180.v:6298$1894_Y end - attribute \src "ls180.v:6495.74-6495.105" - cell $not $not$ls180.v:6495$2042 + attribute \src "ls180.v:6301.74-6301.105" + cell $not $not$ls180.v:6301$1901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6495$2042_Y + connect \Y $not$ls180.v:6301$1901_Y end - attribute \src "ls180.v:6498.64-6498.95" - cell $not $not$ls180.v:6498$2049 + attribute \src "ls180.v:6304.64-6304.95" + cell $not $not$ls180.v:6304$1908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6498$2049_Y + connect \Y $not$ls180.v:6304$1908_Y end - attribute \src "ls180.v:6501.74-6501.105" - cell $not $not$ls180.v:6501$2056 + attribute \src "ls180.v:6307.74-6307.105" + cell $not $not$ls180.v:6307$1915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6501$2056_Y + connect \Y $not$ls180.v:6307$1915_Y end - attribute \src "ls180.v:6504.74-6504.105" - cell $not $not$ls180.v:6504$2063 + attribute \src "ls180.v:6310.74-6310.105" + cell $not $not$ls180.v:6310$1922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6504$2063_Y + connect \Y $not$ls180.v:6310$1922_Y end - attribute \src "ls180.v:6507.75-6507.106" - cell $not $not$ls180.v:6507$2070 + attribute \src "ls180.v:6313.75-6313.106" + cell $not $not$ls180.v:6313$1929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6507$2070_Y + connect \Y $not$ls180.v:6313$1929_Y end - attribute \src "ls180.v:6510.73-6510.104" - cell $not $not$ls180.v:6510$2077 + attribute \src "ls180.v:6316.73-6316.104" + cell $not $not$ls180.v:6316$1936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6510$2077_Y + connect \Y $not$ls180.v:6316$1936_Y end - attribute \src "ls180.v:6513.73-6513.104" - cell $not $not$ls180.v:6513$2084 + attribute \src "ls180.v:6319.73-6319.104" + cell $not $not$ls180.v:6319$1943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6513$2084_Y + connect \Y $not$ls180.v:6319$1943_Y end - attribute \src "ls180.v:6516.73-6516.104" - cell $not $not$ls180.v:6516$2091 + attribute \src "ls180.v:6322.73-6322.104" + cell $not $not$ls180.v:6322$1950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6516$2091_Y + connect \Y $not$ls180.v:6322$1950_Y end - attribute \src "ls180.v:6519.73-6519.104" - cell $not $not$ls180.v:6519$2098 + attribute \src "ls180.v:6325.73-6325.104" + cell $not $not$ls180.v:6325$1957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6519$2098_Y + connect \Y $not$ls180.v:6325$1957_Y end - attribute \src "ls180.v:6537.67-6537.99" - cell $not $not$ls180.v:6537$2106 + attribute \src "ls180.v:6343.67-6343.99" + cell $not $not$ls180.v:6343$1965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6537$2106_Y + connect \Y $not$ls180.v:6343$1965_Y end - attribute \src "ls180.v:6540.67-6540.99" - cell $not $not$ls180.v:6540$2113 + attribute \src "ls180.v:6346.67-6346.99" + cell $not $not$ls180.v:6346$1972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6540$2113_Y + connect \Y $not$ls180.v:6346$1972_Y end - attribute \src "ls180.v:6543.65-6543.97" - cell $not $not$ls180.v:6543$2120 + attribute \src "ls180.v:6349.65-6349.97" + cell $not $not$ls180.v:6349$1979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6543$2120_Y + connect \Y $not$ls180.v:6349$1979_Y end - attribute \src "ls180.v:6546.64-6546.96" - cell $not $not$ls180.v:6546$2127 + attribute \src "ls180.v:6352.64-6352.96" + cell $not $not$ls180.v:6352$1986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6546$2127_Y + connect \Y $not$ls180.v:6352$1986_Y end - attribute \src "ls180.v:6549.63-6549.95" - cell $not $not$ls180.v:6549$2134 + attribute \src "ls180.v:6355.63-6355.95" + cell $not $not$ls180.v:6355$1993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6549$2134_Y + connect \Y $not$ls180.v:6355$1993_Y end - attribute \src "ls180.v:6552.62-6552.94" - cell $not $not$ls180.v:6552$2141 + attribute \src "ls180.v:6358.62-6358.94" + cell $not $not$ls180.v:6358$2000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6552$2141_Y + connect \Y $not$ls180.v:6358$2000_Y end - attribute \src "ls180.v:6555.68-6555.100" - cell $not $not$ls180.v:6555$2148 + attribute \src "ls180.v:6361.68-6361.100" + cell $not $not$ls180.v:6361$2007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6555$2148_Y + connect \Y $not$ls180.v:6361$2007_Y end - attribute \src "ls180.v:6577.67-6577.99" - cell $not $not$ls180.v:6577$2157 + attribute \src "ls180.v:6383.67-6383.99" + cell $not $not$ls180.v:6383$2016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6577$2157_Y + connect \Y $not$ls180.v:6383$2016_Y end - attribute \src "ls180.v:6580.67-6580.99" - cell $not $not$ls180.v:6580$2164 + attribute \src "ls180.v:6386.67-6386.99" + cell $not $not$ls180.v:6386$2023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6580$2164_Y + connect \Y $not$ls180.v:6386$2023_Y end - attribute \src "ls180.v:6583.65-6583.97" - cell $not $not$ls180.v:6583$2171 + attribute \src "ls180.v:6389.65-6389.97" + cell $not $not$ls180.v:6389$2030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6583$2171_Y + connect \Y $not$ls180.v:6389$2030_Y end - attribute \src "ls180.v:6586.64-6586.96" - cell $not $not$ls180.v:6586$2178 + attribute \src "ls180.v:6392.64-6392.96" + cell $not $not$ls180.v:6392$2037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6586$2178_Y + connect \Y $not$ls180.v:6392$2037_Y end - attribute \src "ls180.v:6589.63-6589.95" - cell $not $not$ls180.v:6589$2185 + attribute \src "ls180.v:6395.63-6395.95" + cell $not $not$ls180.v:6395$2044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6589$2185_Y + connect \Y $not$ls180.v:6395$2044_Y end - attribute \src "ls180.v:6592.62-6592.94" - cell $not $not$ls180.v:6592$2192 + attribute \src "ls180.v:6398.62-6398.94" + cell $not $not$ls180.v:6398$2051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6592$2192_Y + connect \Y $not$ls180.v:6398$2051_Y end - attribute \src "ls180.v:6595.68-6595.100" - cell $not $not$ls180.v:6595$2199 + attribute \src "ls180.v:6401.68-6401.100" + cell $not $not$ls180.v:6401$2058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6595$2199_Y + connect \Y $not$ls180.v:6401$2058_Y end - attribute \src "ls180.v:6598.71-6598.103" - cell $not $not$ls180.v:6598$2206 + attribute \src "ls180.v:6404.71-6404.103" + cell $not $not$ls180.v:6404$2065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6598$2206_Y + connect \Y $not$ls180.v:6404$2065_Y end - attribute \src "ls180.v:6601.71-6601.103" - cell $not $not$ls180.v:6601$2213 + attribute \src "ls180.v:6407.71-6407.103" + cell $not $not$ls180.v:6407$2072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6601$2213_Y + connect \Y $not$ls180.v:6407$2072_Y end - attribute \src "ls180.v:6625.64-6625.96" - cell $not $not$ls180.v:6625$2222 + attribute \src "ls180.v:6431.64-6431.96" + cell $not $not$ls180.v:6431$2081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6625$2222_Y + connect \Y $not$ls180.v:6431$2081_Y end - attribute \src "ls180.v:6628.64-6628.96" - cell $not $not$ls180.v:6628$2229 + attribute \src "ls180.v:6434.64-6434.96" + cell $not $not$ls180.v:6434$2088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6628$2229_Y + connect \Y $not$ls180.v:6434$2088_Y end - attribute \src "ls180.v:6631.64-6631.96" - cell $not $not$ls180.v:6631$2236 + attribute \src "ls180.v:6437.64-6437.96" + cell $not $not$ls180.v:6437$2095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6631$2236_Y + connect \Y $not$ls180.v:6437$2095_Y end - attribute \src "ls180.v:6634.64-6634.96" - cell $not $not$ls180.v:6634$2243 + attribute \src "ls180.v:6440.64-6440.96" + cell $not $not$ls180.v:6440$2102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6634$2243_Y + connect \Y $not$ls180.v:6440$2102_Y end - attribute \src "ls180.v:6637.66-6637.98" - cell $not $not$ls180.v:6637$2250 + attribute \src "ls180.v:6443.66-6443.98" + cell $not $not$ls180.v:6443$2109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6637$2250_Y + connect \Y $not$ls180.v:6443$2109_Y end - attribute \src "ls180.v:6640.66-6640.98" - cell $not $not$ls180.v:6640$2257 + attribute \src "ls180.v:6446.66-6446.98" + cell $not $not$ls180.v:6446$2116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6640$2257_Y + connect \Y $not$ls180.v:6446$2116_Y end - attribute \src "ls180.v:6643.66-6643.98" - cell $not $not$ls180.v:6643$2264 + attribute \src "ls180.v:6449.66-6449.98" + cell $not $not$ls180.v:6449$2123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6643$2264_Y + connect \Y $not$ls180.v:6449$2123_Y end - attribute \src "ls180.v:6646.66-6646.98" - cell $not $not$ls180.v:6646$2271 + attribute \src "ls180.v:6452.66-6452.98" + cell $not $not$ls180.v:6452$2130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6646$2271_Y + connect \Y $not$ls180.v:6452$2130_Y end - attribute \src "ls180.v:6649.62-6649.94" - cell $not $not$ls180.v:6649$2278 + attribute \src "ls180.v:6455.62-6455.94" + cell $not $not$ls180.v:6455$2137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6649$2278_Y + connect \Y $not$ls180.v:6455$2137_Y end - attribute \src "ls180.v:6652.72-6652.104" - cell $not $not$ls180.v:6652$2285 + attribute \src "ls180.v:6458.72-6458.104" + cell $not $not$ls180.v:6458$2144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6652$2285_Y + connect \Y $not$ls180.v:6458$2144_Y end - attribute \src "ls180.v:6655.65-6655.97" - cell $not $not$ls180.v:6655$2292 + attribute \src "ls180.v:6461.65-6461.97" + cell $not $not$ls180.v:6461$2151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6655$2292_Y + connect \Y $not$ls180.v:6461$2151_Y end - attribute \src "ls180.v:6658.65-6658.97" - cell $not $not$ls180.v:6658$2299 + attribute \src "ls180.v:6464.65-6464.97" + cell $not $not$ls180.v:6464$2158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6658$2299_Y + connect \Y $not$ls180.v:6464$2158_Y end - attribute \src "ls180.v:6661.65-6661.97" - cell $not $not$ls180.v:6661$2306 + attribute \src "ls180.v:6467.65-6467.97" + cell $not $not$ls180.v:6467$2165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6661$2306_Y + connect \Y $not$ls180.v:6467$2165_Y end - attribute \src "ls180.v:6664.65-6664.97" - cell $not $not$ls180.v:6664$2313 + attribute \src "ls180.v:6470.65-6470.97" + cell $not $not$ls180.v:6470$2172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6664$2313_Y + connect \Y $not$ls180.v:6470$2172_Y end - attribute \src "ls180.v:6667.77-6667.109" - cell $not $not$ls180.v:6667$2320 + attribute \src "ls180.v:6473.77-6473.109" + cell $not $not$ls180.v:6473$2179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6667$2320_Y + connect \Y $not$ls180.v:6473$2179_Y end - attribute \src "ls180.v:6670.78-6670.110" - cell $not $not$ls180.v:6670$2327 + attribute \src "ls180.v:6476.78-6476.110" + cell $not $not$ls180.v:6476$2186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6670$2327_Y + connect \Y $not$ls180.v:6476$2186_Y end - attribute \src "ls180.v:6673.69-6673.101" - cell $not $not$ls180.v:6673$2334 + attribute \src "ls180.v:6479.69-6479.101" + cell $not $not$ls180.v:6479$2193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6673$2334_Y + connect \Y $not$ls180.v:6479$2193_Y end - attribute \src "ls180.v:6693.55-6693.87" - cell $not $not$ls180.v:6693$2342 + attribute \src "ls180.v:6499.55-6499.87" + cell $not $not$ls180.v:6499$2201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6693$2342_Y + connect \Y $not$ls180.v:6499$2201_Y end - attribute \src "ls180.v:6696.65-6696.97" - cell $not $not$ls180.v:6696$2349 + attribute \src "ls180.v:6502.65-6502.97" + cell $not $not$ls180.v:6502$2208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6696$2349_Y + connect \Y $not$ls180.v:6502$2208_Y end - attribute \src "ls180.v:6699.66-6699.98" - cell $not $not$ls180.v:6699$2356 + attribute \src "ls180.v:6505.66-6505.98" + cell $not $not$ls180.v:6505$2215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6699$2356_Y + connect \Y $not$ls180.v:6505$2215_Y end - attribute \src "ls180.v:6702.70-6702.102" - cell $not $not$ls180.v:6702$2363 + attribute \src "ls180.v:6508.70-6508.102" + cell $not $not$ls180.v:6508$2222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6702$2363_Y + connect \Y $not$ls180.v:6508$2222_Y end - attribute \src "ls180.v:6705.71-6705.103" - cell $not $not$ls180.v:6705$2370 + attribute \src "ls180.v:6511.71-6511.103" + cell $not $not$ls180.v:6511$2229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6705$2370_Y + connect \Y $not$ls180.v:6511$2229_Y end - attribute \src "ls180.v:6708.69-6708.101" - cell $not $not$ls180.v:6708$2377 + attribute \src "ls180.v:6514.69-6514.101" + cell $not $not$ls180.v:6514$2236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6708$2377_Y + connect \Y $not$ls180.v:6514$2236_Y end - attribute \src "ls180.v:6711.66-6711.98" - cell $not $not$ls180.v:6711$2384 + attribute \src "ls180.v:6517.66-6517.98" + cell $not $not$ls180.v:6517$2243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6711$2384_Y + connect \Y $not$ls180.v:6517$2243_Y end - attribute \src "ls180.v:6714.65-6714.97" - cell $not $not$ls180.v:6714$2391 + attribute \src "ls180.v:6520.65-6520.97" + cell $not $not$ls180.v:6520$2250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6714$2391_Y + connect \Y $not$ls180.v:6520$2250_Y end - attribute \src "ls180.v:6727.71-6727.103" - cell $not $not$ls180.v:6727$2399 + attribute \src "ls180.v:6533.71-6533.103" + cell $not $not$ls180.v:6533$2258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6727$2399_Y + connect \Y $not$ls180.v:6533$2258_Y end - attribute \src "ls180.v:6730.71-6730.103" - cell $not $not$ls180.v:6730$2406 + attribute \src "ls180.v:6536.71-6536.103" + cell $not $not$ls180.v:6536$2265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6730$2406_Y + connect \Y $not$ls180.v:6536$2265_Y end - attribute \src "ls180.v:6733.71-6733.103" - cell $not $not$ls180.v:6733$2413 + attribute \src "ls180.v:6539.71-6539.103" + cell $not $not$ls180.v:6539$2272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6733$2413_Y + connect \Y $not$ls180.v:6539$2272_Y end - attribute \src "ls180.v:6736.71-6736.103" - cell $not $not$ls180.v:6736$2420 + attribute \src "ls180.v:6542.71-6542.103" + cell $not $not$ls180.v:6542$2279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6736$2420_Y + connect \Y $not$ls180.v:6542$2279_Y end - attribute \src "ls180.v:7117.86-7117.330" - cell $not $not$ls180.v:7117$2469 + attribute \src "ls180.v:6923.86-6923.330" + cell $not $not$ls180.v:6923$2328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7117$2468_Y - connect \Y $not$ls180.v:7117$2469_Y + connect \A $or$ls180.v:6923$2327_Y + connect \Y $not$ls180.v:6923$2328_Y end - attribute \src "ls180.v:7141.86-7141.330" - cell $not $not$ls180.v:7141$2485 + attribute \src "ls180.v:6947.86-6947.330" + cell $not $not$ls180.v:6947$2344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7141$2484_Y - connect \Y $not$ls180.v:7141$2485_Y + connect \A $or$ls180.v:6947$2343_Y + connect \Y $not$ls180.v:6947$2344_Y end - attribute \src "ls180.v:7165.86-7165.330" - cell $not $not$ls180.v:7165$2501 + attribute \src "ls180.v:6971.86-6971.330" + cell $not $not$ls180.v:6971$2360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7165$2500_Y - connect \Y $not$ls180.v:7165$2501_Y + connect \A $or$ls180.v:6971$2359_Y + connect \Y $not$ls180.v:6971$2360_Y end - attribute \src "ls180.v:7189.86-7189.330" - cell $not $not$ls180.v:7189$2517 + attribute \src "ls180.v:6995.86-6995.330" + cell $not $not$ls180.v:6995$2376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7189$2516_Y - connect \Y $not$ls180.v:7189$2517_Y + connect \A $or$ls180.v:6995$2375_Y + connect \Y $not$ls180.v:6995$2376_Y end - attribute \src "ls180.v:7690.18-7690.42" - cell $not $not$ls180.v:7690$2573 + attribute \src "ls180.v:7496.18-7496.42" + cell $not $not$ls180.v:7496$2432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_clk0 - connect \Y $not$ls180.v:7690$2573_Y + connect \Y $not$ls180.v:7496$2432_Y end - attribute \src "ls180.v:7769.72-7769.101" - cell $not $not$ls180.v:7769$2606 + attribute \src "ls180.v:7575.72-7575.101" + cell $not $not$ls180.v:7575$2465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_ack - connect \Y $not$ls180.v:7769$2606_Y + connect \Y $not$ls180.v:7575$2465_Y end - attribute \src "ls180.v:7788.8-7788.38" - cell $not $not$ls180.v:7788$2610 + attribute \src "ls180.v:7594.8-7594.38" + cell $not $not$ls180.v:7594$2469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_zero_trigger - connect \Y $not$ls180.v:7788$2610_Y - end - attribute \src "ls180.v:7792.70-7792.98" - cell $not $not$ls180.v:7792$2613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_ram_bus_ack - connect \Y $not$ls180.v:7792$2613_Y - end - attribute \src "ls180.v:7796.70-7796.98" - cell $not $not$ls180.v:7796$2616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_ram_bus_ack - connect \Y $not$ls180.v:7796$2616_Y - end - attribute \src "ls180.v:7800.70-7800.98" - cell $not $not$ls180.v:7800$2619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface2_ram_bus_ack - connect \Y $not$ls180.v:7800$2619_Y + connect \Y $not$ls180.v:7594$2469_Y end - attribute \src "ls180.v:7804.70-7804.98" - cell $not $not$ls180.v:7804$2622 + attribute \src "ls180.v:7598.64-7598.89" + cell $not $not$ls180.v:7598$2472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface3_ram_bus_ack - connect \Y $not$ls180.v:7804$2622_Y + connect \A \main_ram_bus_ram_bus_ack + connect \Y $not$ls180.v:7598$2472_Y end - attribute \src "ls180.v:7812.32-7812.55" - cell $not $not$ls180.v:7812$2624 + attribute \src "ls180.v:7606.32-7606.55" + cell $not $not$ls180.v:7606$2474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:7812$2624_Y + connect \Y $not$ls180.v:7606$2474_Y end - attribute \src "ls180.v:7882.136-7882.189" - cell $not $not$ls180.v:7882$2639 + attribute \src "ls180.v:7676.136-7676.189" + cell $not $not$ls180.v:7676$2489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7882$2639_Y + connect \Y $not$ls180.v:7676$2489_Y end - attribute \src "ls180.v:7888.136-7888.189" - cell $not $not$ls180.v:7888$2644 + attribute \src "ls180.v:7682.136-7682.189" + cell $not $not$ls180.v:7682$2494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7888$2644_Y + connect \Y $not$ls180.v:7682$2494_Y end - attribute \src "ls180.v:7889.8-7889.61" - cell $not $not$ls180.v:7889$2646 + attribute \src "ls180.v:7683.8-7683.61" + cell $not $not$ls180.v:7683$2496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7889$2646_Y + connect \Y $not$ls180.v:7683$2496_Y end - attribute \src "ls180.v:7897.8-7897.56" - cell $not $not$ls180.v:7897$2649 + attribute \src "ls180.v:7691.8-7691.56" + cell $not $not$ls180.v:7691$2499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:7897$2649_Y + connect \Y $not$ls180.v:7691$2499_Y end - attribute \src "ls180.v:7912.8-7912.46" - cell $not $not$ls180.v:7912$2651 + attribute \src "ls180.v:7706.8-7706.46" + cell $not $not$ls180.v:7706$2501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \Y $not$ls180.v:7912$2651_Y + connect \Y $not$ls180.v:7706$2501_Y end - attribute \src "ls180.v:7928.136-7928.189" - cell $not $not$ls180.v:7928$2655 + attribute \src "ls180.v:7722.136-7722.189" + cell $not $not$ls180.v:7722$2505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7928$2655_Y + connect \Y $not$ls180.v:7722$2505_Y end - attribute \src "ls180.v:7934.136-7934.189" - cell $not $not$ls180.v:7934$2660 + attribute \src "ls180.v:7728.136-7728.189" + cell $not $not$ls180.v:7728$2510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7934$2660_Y + connect \Y $not$ls180.v:7728$2510_Y end - attribute \src "ls180.v:7935.8-7935.61" - cell $not $not$ls180.v:7935$2662 + attribute \src "ls180.v:7729.8-7729.61" + cell $not $not$ls180.v:7729$2512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7935$2662_Y + connect \Y $not$ls180.v:7729$2512_Y end - attribute \src "ls180.v:7943.8-7943.56" - cell $not $not$ls180.v:7943$2665 + attribute \src "ls180.v:7737.8-7737.56" + cell $not $not$ls180.v:7737$2515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:7943$2665_Y + connect \Y $not$ls180.v:7737$2515_Y end - attribute \src "ls180.v:7958.8-7958.46" - cell $not $not$ls180.v:7958$2667 + attribute \src "ls180.v:7752.8-7752.46" + cell $not $not$ls180.v:7752$2517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \Y $not$ls180.v:7958$2667_Y + connect \Y $not$ls180.v:7752$2517_Y end - attribute \src "ls180.v:7974.136-7974.189" - cell $not $not$ls180.v:7974$2671 + attribute \src "ls180.v:7768.136-7768.189" + cell $not $not$ls180.v:7768$2521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7974$2671_Y + connect \Y $not$ls180.v:7768$2521_Y end - attribute \src "ls180.v:7980.136-7980.189" - cell $not $not$ls180.v:7980$2676 + attribute \src "ls180.v:7774.136-7774.189" + cell $not $not$ls180.v:7774$2526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7980$2676_Y + connect \Y $not$ls180.v:7774$2526_Y end - attribute \src "ls180.v:7981.8-7981.61" - cell $not $not$ls180.v:7981$2678 + attribute \src "ls180.v:7775.8-7775.61" + cell $not $not$ls180.v:7775$2528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7981$2678_Y + connect \Y $not$ls180.v:7775$2528_Y end - attribute \src "ls180.v:7989.8-7989.56" - cell $not $not$ls180.v:7989$2681 + attribute \src "ls180.v:7783.8-7783.56" + cell $not $not$ls180.v:7783$2531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:7989$2681_Y + connect \Y $not$ls180.v:7783$2531_Y end - attribute \src "ls180.v:8004.8-8004.46" - cell $not $not$ls180.v:8004$2683 + attribute \src "ls180.v:7798.8-7798.46" + cell $not $not$ls180.v:7798$2533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \Y $not$ls180.v:8004$2683_Y + connect \Y $not$ls180.v:7798$2533_Y end - attribute \src "ls180.v:8020.136-8020.189" - cell $not $not$ls180.v:8020$2687 + attribute \src "ls180.v:7814.136-7814.189" + cell $not $not$ls180.v:7814$2537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:8020$2687_Y + connect \Y $not$ls180.v:7814$2537_Y end - attribute \src "ls180.v:8026.136-8026.189" - cell $not $not$ls180.v:8026$2692 + attribute \src "ls180.v:7820.136-7820.189" + cell $not $not$ls180.v:7820$2542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:8026$2692_Y + connect \Y $not$ls180.v:7820$2542_Y end - attribute \src "ls180.v:8027.8-8027.61" - cell $not $not$ls180.v:8027$2694 + attribute \src "ls180.v:7821.8-7821.61" + cell $not $not$ls180.v:7821$2544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:8027$2694_Y + connect \Y $not$ls180.v:7821$2544_Y end - attribute \src "ls180.v:8035.8-8035.56" - cell $not $not$ls180.v:8035$2697 + attribute \src "ls180.v:7829.8-7829.56" + cell $not $not$ls180.v:7829$2547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:8035$2697_Y + connect \Y $not$ls180.v:7829$2547_Y end - attribute \src "ls180.v:8050.8-8050.46" - cell $not $not$ls180.v:8050$2699 + attribute \src "ls180.v:7844.8-7844.46" + cell $not $not$ls180.v:7844$2549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \Y $not$ls180.v:8050$2699_Y + connect \Y $not$ls180.v:7844$2549_Y end - attribute \src "ls180.v:8058.7-8058.22" - cell $not $not$ls180.v:8058$2702 + attribute \src "ls180.v:7852.7-7852.22" + cell $not $not$ls180.v:7852$2552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en0 - connect \Y $not$ls180.v:8058$2702_Y + connect \Y $not$ls180.v:7852$2552_Y end - attribute \src "ls180.v:8061.8-8061.29" - cell $not $not$ls180.v:8061$2703 + attribute \src "ls180.v:7855.8-7855.29" + cell $not $not$ls180.v:7855$2553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time0 - connect \Y $not$ls180.v:8061$2703_Y + connect \Y $not$ls180.v:7855$2553_Y end - attribute \src "ls180.v:8065.7-8065.22" - cell $not $not$ls180.v:8065$2705 + attribute \src "ls180.v:7859.7-7859.22" + cell $not $not$ls180.v:7859$2555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_en1 - connect \Y $not$ls180.v:8065$2705_Y + connect \Y $not$ls180.v:7859$2555_Y end - attribute \src "ls180.v:8068.8-8068.29" - cell $not $not$ls180.v:8068$2706 + attribute \src "ls180.v:7862.8-7862.29" + cell $not $not$ls180.v:7862$2556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_max_time1 - connect \Y $not$ls180.v:8068$2706_Y + connect \Y $not$ls180.v:7862$2556_Y end - attribute \src "ls180.v:8187.30-8187.60" - cell $not $not$ls180.v:8187$2708 + attribute \src "ls180.v:7981.30-7981.60" + cell $not $not$ls180.v:7981$2558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed2 - connect \Y $not$ls180.v:8187$2708_Y + connect \Y $not$ls180.v:7981$2558_Y end - attribute \src "ls180.v:8188.30-8188.60" - cell $not $not$ls180.v:8188$2709 + attribute \src "ls180.v:7982.30-7982.60" + cell $not $not$ls180.v:7982$2559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed3 - connect \Y $not$ls180.v:8188$2709_Y + connect \Y $not$ls180.v:7982$2559_Y end - attribute \src "ls180.v:8189.29-8189.59" - cell $not $not$ls180.v:8189$2710 + attribute \src "ls180.v:7983.29-7983.59" + cell $not $not$ls180.v:7983$2560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_sync_rhs_array_muxed4 - connect \Y $not$ls180.v:8189$2710_Y + connect \Y $not$ls180.v:7983$2560_Y end - attribute \src "ls180.v:8200.8-8200.33" - cell $not $not$ls180.v:8200$2711 + attribute \src "ls180.v:7994.8-7994.33" + cell $not $not$ls180.v:7994$2561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_ready - connect \Y $not$ls180.v:8200$2711_Y + connect \Y $not$ls180.v:7994$2561_Y end - attribute \src "ls180.v:8215.8-8215.33" - cell $not $not$ls180.v:8215$2714 + attribute \src "ls180.v:8009.8-8009.33" + cell $not $not$ls180.v:8009$2564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_twtrcon_ready - connect \Y $not$ls180.v:8215$2714_Y + connect \Y $not$ls180.v:8009$2564_Y end - attribute \src "ls180.v:8251.36-8251.58" - cell $not $not$ls180.v:8251$2744 + attribute \src "ls180.v:8045.36-8045.58" + cell $not $not$ls180.v:8045$2594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_tx_busy - connect \Y $not$ls180.v:8251$2744_Y + connect \Y $not$ls180.v:8045$2594_Y end - attribute \src "ls180.v:8251.64-8251.89" - cell $not $not$ls180.v:8251$2746 + attribute \src "ls180.v:8045.64-8045.89" + cell $not $not$ls180.v:8045$2596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_sink_ready - connect \Y $not$ls180.v:8251$2746_Y + connect \Y $not$ls180.v:8045$2596_Y end - attribute \src "ls180.v:8280.7-8280.29" - cell $not $not$ls180.v:8280$2753 + attribute \src "ls180.v:8074.7-8074.29" + cell $not $not$ls180.v:8074$2603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx_busy - connect \Y $not$ls180.v:8280$2753_Y + connect \Y $not$ls180.v:8074$2603_Y end - attribute \src "ls180.v:8281.9-8281.26" - cell $not $not$ls180.v:8281$2754 + attribute \src "ls180.v:8075.9-8075.26" + cell $not $not$ls180.v:8075$2604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_phy_rx - connect \Y $not$ls180.v:8281$2754_Y + connect \Y $not$ls180.v:8075$2604_Y end - attribute \src "ls180.v:8314.8-8314.29" - cell $not $not$ls180.v:8314$2760 + attribute \src "ls180.v:8108.8-8108.29" + cell $not $not$ls180.v:8108$2610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_trigger - connect \Y $not$ls180.v:8314$2760_Y + connect \Y $not$ls180.v:8108$2610_Y end - attribute \src "ls180.v:8321.8-8321.29" - cell $not $not$ls180.v:8321$2762 + attribute \src "ls180.v:8115.8-8115.29" + cell $not $not$ls180.v:8115$2612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_trigger - connect \Y $not$ls180.v:8321$2762_Y + connect \Y $not$ls180.v:8115$2612_Y end - attribute \src "ls180.v:8331.80-8331.106" - cell $not $not$ls180.v:8331$2765 + attribute \src "ls180.v:8125.80-8125.106" + cell $not $not$ls180.v:8125$2615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8331$2765_Y + connect \Y $not$ls180.v:8125$2615_Y end - attribute \src "ls180.v:8337.80-8337.106" - cell $not $not$ls180.v:8337$2770 + attribute \src "ls180.v:8131.80-8131.106" + cell $not $not$ls180.v:8131$2620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8337$2770_Y + connect \Y $not$ls180.v:8131$2620_Y end - attribute \src "ls180.v:8338.8-8338.34" - cell $not $not$ls180.v:8338$2772 + attribute \src "ls180.v:8132.8-8132.34" + cell $not $not$ls180.v:8132$2622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_do_read - connect \Y $not$ls180.v:8338$2772_Y + connect \Y $not$ls180.v:8132$2622_Y end - attribute \src "ls180.v:8353.80-8353.106" - cell $not $not$ls180.v:8353$2776 + attribute \src "ls180.v:8147.80-8147.106" + cell $not $not$ls180.v:8147$2626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8353$2776_Y + connect \Y $not$ls180.v:8147$2626_Y end - attribute \src "ls180.v:8359.80-8359.106" - cell $not $not$ls180.v:8359$2781 + attribute \src "ls180.v:8153.80-8153.106" + cell $not $not$ls180.v:8153$2631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8359$2781_Y + connect \Y $not$ls180.v:8153$2631_Y end - attribute \src "ls180.v:8360.8-8360.34" - cell $not $not$ls180.v:8360$2783 + attribute \src "ls180.v:8154.8-8154.34" + cell $not $not$ls180.v:8154$2633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_do_read - connect \Y $not$ls180.v:8360$2783_Y + connect \Y $not$ls180.v:8154$2633_Y end - attribute \src "ls180.v:8391.22-8391.41" - cell $not $not$ls180.v:8391$2787 + attribute \src "ls180.v:8185.22-8185.41" + cell $not $not$ls180.v:8185$2637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spimaster6_cs - connect \Y $not$ls180.v:8391$2787_Y + connect \Y $not$ls180.v:8185$2637_Y end - attribute \src "ls180.v:8391.46-8391.73" - cell $not $not$ls180.v:8391$2788 + attribute \src "ls180.v:8185.46-8185.73" + cell $not $not$ls180.v:8185$2638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spimaster26_cs_enable - connect \Y $not$ls180.v:8391$2788_Y + connect \Y $not$ls180.v:8185$2638_Y end - attribute \src "ls180.v:8426.22-8426.40" - cell $not $not$ls180.v:8426$2792 + attribute \src "ls180.v:8220.22-8220.40" + cell $not $not$ls180.v:8220$2642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spisdcard_cs - connect \Y $not$ls180.v:8426$2792_Y + connect \Y $not$ls180.v:8220$2642_Y end - attribute \src "ls180.v:8426.45-8426.70" - cell $not $not$ls180.v:8426$2793 + attribute \src "ls180.v:8220.45-8220.70" + cell $not $not$ls180.v:8220$2643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_spisdcard_cs_enable - connect \Y $not$ls180.v:8426$2793_Y + connect \Y $not$ls180.v:8220$2643_Y end - attribute \src "ls180.v:8480.7-8480.31" - cell $not $not$ls180.v:8480$2804 + attribute \src "ls180.v:8274.7-8274.31" + cell $not $not$ls180.v:8274$2654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_clocker_stop - connect \Y $not$ls180.v:8480$2804_Y + connect \Y $not$ls180.v:8274$2654_Y end - attribute \src "ls180.v:8552.8-8552.46" - cell $not $not$ls180.v:8552$2816 + attribute \src "ls180.v:8346.8-8346.46" + cell $not $not$ls180.v:8346$2666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:8552$2816_Y + connect \Y $not$ls180.v:8346$2666_Y end - attribute \src "ls180.v:8633.8-8633.47" - cell $not $not$ls180.v:8633$2828 + attribute \src "ls180.v:8427.8-8427.47" + cell $not $not$ls180.v:8427$2678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:8633$2828_Y + connect \Y $not$ls180.v:8427$2678_Y end - attribute \src "ls180.v:8694.8-8694.48" - cell $not $not$ls180.v:8694$2840 + attribute \src "ls180.v:8488.8-8488.48" + cell $not $not$ls180.v:8488$2690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:8694$2840_Y + connect \Y $not$ls180.v:8488$2690_Y end - attribute \src "ls180.v:8864.88-8864.118" - cell $not $not$ls180.v:8864$2854 + attribute \src "ls180.v:8658.88-8658.118" + cell $not $not$ls180.v:8658$2704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8864$2854_Y + connect \Y $not$ls180.v:8658$2704_Y end - attribute \src "ls180.v:8870.88-8870.118" - cell $not $not$ls180.v:8870$2859 + attribute \src "ls180.v:8664.88-8664.118" + cell $not $not$ls180.v:8664$2709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8870$2859_Y + connect \Y $not$ls180.v:8664$2709_Y end - attribute \src "ls180.v:8871.8-8871.38" - cell $not $not$ls180.v:8871$2861 + attribute \src "ls180.v:8665.8-8665.38" + cell $not $not$ls180.v:8665$2711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_do_read - connect \Y $not$ls180.v:8871$2861_Y + connect \Y $not$ls180.v:8665$2711_Y end - attribute \src "ls180.v:8962.88-8962.118" - cell $not $not$ls180.v:8962$2876 + attribute \src "ls180.v:8756.88-8756.118" + cell $not $not$ls180.v:8756$2726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8962$2876_Y + connect \Y $not$ls180.v:8756$2726_Y end - attribute \src "ls180.v:8968.88-8968.118" - cell $not $not$ls180.v:8968$2881 + attribute \src "ls180.v:8762.88-8762.118" + cell $not $not$ls180.v:8762$2731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8968$2881_Y + connect \Y $not$ls180.v:8762$2731_Y end - attribute \src "ls180.v:8969.8-8969.38" - cell $not $not$ls180.v:8969$2883 + attribute \src "ls180.v:8763.8-8763.38" + cell $not $not$ls180.v:8763$2733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_do_read - connect \Y $not$ls180.v:8969$2883_Y + connect \Y $not$ls180.v:8763$2733_Y end - attribute \src "ls180.v:8989.9-8989.28" - cell $not $not$ls180.v:8989$2886 + attribute \src "ls180.v:8783.9-8783.28" + cell $not $not$ls180.v:8783$2736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [0] - connect \Y $not$ls180.v:8989$2886_Y + connect \Y $not$ls180.v:8783$2736_Y end - attribute \src "ls180.v:9008.9-9008.28" - cell $not $not$ls180.v:9008$2887 + attribute \src "ls180.v:8802.9-8802.28" + cell $not $not$ls180.v:8802$2737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [1] - connect \Y $not$ls180.v:9008$2887_Y + connect \Y $not$ls180.v:8802$2737_Y end - attribute \src "ls180.v:9027.9-9027.28" - cell $not $not$ls180.v:9027$2888 + attribute \src "ls180.v:8821.9-8821.28" + cell $not $not$ls180.v:8821$2738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [2] - connect \Y $not$ls180.v:9027$2888_Y + connect \Y $not$ls180.v:8821$2738_Y end - attribute \src "ls180.v:9046.9-9046.28" - cell $not $not$ls180.v:9046$2889 + attribute \src "ls180.v:8840.9-8840.28" + cell $not $not$ls180.v:8840$2739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [3] - connect \Y $not$ls180.v:9046$2889_Y + connect \Y $not$ls180.v:8840$2739_Y end - attribute \src "ls180.v:9065.9-9065.28" - cell $not $not$ls180.v:9065$2890 + attribute \src "ls180.v:8859.9-8859.28" + cell $not $not$ls180.v:8859$2740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_request [4] - connect \Y $not$ls180.v:9065$2890_Y + connect \Y $not$ls180.v:8859$2740_Y end - attribute \src "ls180.v:9086.8-9086.21" - cell $not $not$ls180.v:9086$2891 + attribute \src "ls180.v:8880.8-8880.21" + cell $not $not$ls180.v:8880$2741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_done - connect \Y $not$ls180.v:9086$2891_Y + connect \Y $not$ls180.v:8880$2741_Y end - attribute \src "ls180.v:10709.8-10709.51" - cell $or $or$ls180.v:10709$3079 + attribute \src "ls180.v:10416.8-10416.51" + cell $or $or$ls180.v:10416$2851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278618,10 +276388,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \sys_rst_1 connect \B \main_libresocsim_libresoc_reset - connect \Y $or$ls180.v:10709$3079_Y + connect \Y $or$ls180.v:10416$2851_Y end - attribute \src "ls180.v:2934.10-2934.71" - cell $or $or$ls180.v:2934$57 + attribute \src "ls180.v:2845.10-2845.71" + cell $or $or$ls180.v:2845$33 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278629,10 +276399,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_xics_icp_ack connect \B \main_converter0_skip - connect \Y $or$ls180.v:2934$57_Y + connect \Y $or$ls180.v:2845$33_Y end - attribute \src "ls180.v:2994.10-2994.71" - cell $or $or$ls180.v:2994$68 + attribute \src "ls180.v:2905.10-2905.71" + cell $or $or$ls180.v:2905$44 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278640,10 +276410,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_xics_ics_ack connect \B \main_converter1_skip - connect \Y $or$ls180.v:2994$68_Y + connect \Y $or$ls180.v:2905$44_Y end - attribute \src "ls180.v:3054.10-3054.53" - cell $or $or$ls180.v:3054$79 + attribute \src "ls180.v:2965.10-2965.53" + cell $or $or$ls180.v:2965$55 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278651,21 +276421,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_ack connect \B \main_socbushandler_skip - connect \Y $or$ls180.v:3054$79_Y + connect \Y $or$ls180.v:2965$55_Y end - attribute \src "ls180.v:3306.39-3306.105" - cell $or $or$ls180.v:3306$223 + attribute \src "ls180.v:3175.39-3175.105" + cell $or $or$ls180.v:3175$124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_start0 - connect \B $ne$ls180.v:3306$222_Y - connect \Y $or$ls180.v:3306$223_Y + connect \B $ne$ls180.v:3175$123_Y + connect \Y $or$ls180.v:3175$124_Y end - attribute \src "ls180.v:3349.59-3349.140" - cell $or $or$ls180.v:3349$227 + attribute \src "ls180.v:3218.59-3218.140" + cell $or $or$ls180.v:3218$128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278673,10 +276443,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_req_wdata_ready connect \B \main_sdram_bankmachine0_req_rdata_valid - connect \Y $or$ls180.v:3349$227_Y + connect \Y $or$ls180.v:3218$128_Y end - attribute \src "ls180.v:3350.44-3350.151" - cell $or $or$ls180.v:3350$228 + attribute \src "ls180.v:3219.44-3219.151" + cell $or $or$ls180.v:3219$129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278684,21 +276454,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $or$ls180.v:3350$228_Y + connect \Y $or$ls180.v:3219$129_Y end - attribute \src "ls180.v:3358.45-3358.170" - cell $or $or$ls180.v:3358$232 + attribute \src "ls180.v:3227.45-3227.170" + cell $or $or$ls180.v:3227$133 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3358$231_Y + connect \A $sshl$ls180.v:3227$132_Y connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3358$232_Y + connect \Y $or$ls180.v:3227$133_Y end - attribute \src "ls180.v:3395.127-3395.245" - cell $or $or$ls180.v:3395$245 + attribute \src "ls180.v:3264.127-3264.245" + cell $or $or$ls180.v:3264$146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278706,21 +276476,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3395$245_Y + connect \Y $or$ls180.v:3264$146_Y end - attribute \src "ls180.v:3401.57-3401.157" - cell $or $or$ls180.v:3401$251 + attribute \src "ls180.v:3270.57-3270.157" + cell $or $or$ls180.v:3270$152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3401$250_Y + connect \A $not$ls180.v:3270$151_Y connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:3401$251_Y + connect \Y $or$ls180.v:3270$152_Y end - attribute \src "ls180.v:3506.59-3506.140" - cell $or $or$ls180.v:3506$257 + attribute \src "ls180.v:3375.59-3375.140" + cell $or $or$ls180.v:3375$158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278728,10 +276498,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_req_wdata_ready connect \B \main_sdram_bankmachine1_req_rdata_valid - connect \Y $or$ls180.v:3506$257_Y + connect \Y $or$ls180.v:3375$158_Y end - attribute \src "ls180.v:3507.44-3507.151" - cell $or $or$ls180.v:3507$258 + attribute \src "ls180.v:3376.44-3376.151" + cell $or $or$ls180.v:3376$159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278739,21 +276509,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $or$ls180.v:3507$258_Y + connect \Y $or$ls180.v:3376$159_Y end - attribute \src "ls180.v:3515.45-3515.170" - cell $or $or$ls180.v:3515$262 + attribute \src "ls180.v:3384.45-3384.170" + cell $or $or$ls180.v:3384$163 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3515$261_Y + connect \A $sshl$ls180.v:3384$162_Y connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3515$262_Y + connect \Y $or$ls180.v:3384$163_Y end - attribute \src "ls180.v:3552.127-3552.245" - cell $or $or$ls180.v:3552$275 + attribute \src "ls180.v:3421.127-3421.245" + cell $or $or$ls180.v:3421$176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278761,21 +276531,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3552$275_Y + connect \Y $or$ls180.v:3421$176_Y end - attribute \src "ls180.v:3558.57-3558.157" - cell $or $or$ls180.v:3558$281 + attribute \src "ls180.v:3427.57-3427.157" + cell $or $or$ls180.v:3427$182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3558$280_Y + connect \A $not$ls180.v:3427$181_Y connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:3558$281_Y + connect \Y $or$ls180.v:3427$182_Y end - attribute \src "ls180.v:3663.59-3663.140" - cell $or $or$ls180.v:3663$287 + attribute \src "ls180.v:3532.59-3532.140" + cell $or $or$ls180.v:3532$188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278783,10 +276553,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_req_wdata_ready connect \B \main_sdram_bankmachine2_req_rdata_valid - connect \Y $or$ls180.v:3663$287_Y + connect \Y $or$ls180.v:3532$188_Y end - attribute \src "ls180.v:3664.44-3664.151" - cell $or $or$ls180.v:3664$288 + attribute \src "ls180.v:3533.44-3533.151" + cell $or $or$ls180.v:3533$189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278794,21 +276564,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $or$ls180.v:3664$288_Y + connect \Y $or$ls180.v:3533$189_Y end - attribute \src "ls180.v:3672.45-3672.170" - cell $or $or$ls180.v:3672$292 + attribute \src "ls180.v:3541.45-3541.170" + cell $or $or$ls180.v:3541$193 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3672$291_Y + connect \A $sshl$ls180.v:3541$192_Y connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3672$292_Y + connect \Y $or$ls180.v:3541$193_Y end - attribute \src "ls180.v:3709.127-3709.245" - cell $or $or$ls180.v:3709$305 + attribute \src "ls180.v:3578.127-3578.245" + cell $or $or$ls180.v:3578$206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278816,21 +276586,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3709$305_Y + connect \Y $or$ls180.v:3578$206_Y end - attribute \src "ls180.v:3715.57-3715.157" - cell $or $or$ls180.v:3715$311 + attribute \src "ls180.v:3584.57-3584.157" + cell $or $or$ls180.v:3584$212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3715$310_Y + connect \A $not$ls180.v:3584$211_Y connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:3715$311_Y + connect \Y $or$ls180.v:3584$212_Y end - attribute \src "ls180.v:3820.59-3820.140" - cell $or $or$ls180.v:3820$317 + attribute \src "ls180.v:3689.59-3689.140" + cell $or $or$ls180.v:3689$218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278838,10 +276608,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_req_wdata_ready connect \B \main_sdram_bankmachine3_req_rdata_valid - connect \Y $or$ls180.v:3820$317_Y + connect \Y $or$ls180.v:3689$218_Y end - attribute \src "ls180.v:3821.44-3821.151" - cell $or $or$ls180.v:3821$318 + attribute \src "ls180.v:3690.44-3690.151" + cell $or $or$ls180.v:3690$219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278849,21 +276619,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $or$ls180.v:3821$318_Y + connect \Y $or$ls180.v:3690$219_Y end - attribute \src "ls180.v:3829.45-3829.170" - cell $or $or$ls180.v:3829$322 + attribute \src "ls180.v:3698.45-3698.170" + cell $or $or$ls180.v:3698$223 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 parameter \B_WIDTH 13 parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3829$321_Y + connect \A $sshl$ls180.v:3698$222_Y connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3829$322_Y + connect \Y $or$ls180.v:3698$223_Y end - attribute \src "ls180.v:3866.127-3866.245" - cell $or $or$ls180.v:3866$335 + attribute \src "ls180.v:3735.127-3735.245" + cell $or $or$ls180.v:3735$236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278871,21 +276641,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3866$335_Y + connect \Y $or$ls180.v:3735$236_Y end - attribute \src "ls180.v:3872.57-3872.157" - cell $or $or$ls180.v:3872$341 + attribute \src "ls180.v:3741.57-3741.157" + cell $or $or$ls180.v:3741$242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3872$340_Y + connect \A $not$ls180.v:3741$241_Y connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:3872$341_Y + connect \Y $or$ls180.v:3741$242_Y end - attribute \src "ls180.v:3971.107-3971.193" - cell $or $or$ls180.v:3971$361 + attribute \src "ls180.v:3840.107-3840.193" + cell $or $or$ls180.v:3840$262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -278893,626 +276663,626 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_payload_is_write connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $or$ls180.v:3971$361_Y + connect \Y $or$ls180.v:3840$262_Y end - attribute \src "ls180.v:3974.39-3974.204" - cell $or $or$ls180.v:3974$367 + attribute \src "ls180.v:3843.39-3843.204" + cell $or $or$ls180.v:3843$268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3974$365_Y - connect \B $and$ls180.v:3974$366_Y - connect \Y $or$ls180.v:3974$367_Y + connect \A $and$ls180.v:3843$266_Y + connect \B $and$ls180.v:3843$267_Y + connect \Y $or$ls180.v:3843$268_Y end - attribute \src "ls180.v:3974.38-3974.289" - cell $or $or$ls180.v:3974$369 + attribute \src "ls180.v:3843.38-3843.289" + cell $or $or$ls180.v:3843$270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3974$367_Y - connect \B $and$ls180.v:3974$368_Y - connect \Y $or$ls180.v:3974$369_Y + connect \A $or$ls180.v:3843$268_Y + connect \B $and$ls180.v:3843$269_Y + connect \Y $or$ls180.v:3843$270_Y end - attribute \src "ls180.v:3974.37-3974.374" - cell $or $or$ls180.v:3974$371 + attribute \src "ls180.v:3843.37-3843.374" + cell $or $or$ls180.v:3843$272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3974$369_Y - connect \B $and$ls180.v:3974$370_Y - connect \Y $or$ls180.v:3974$371_Y + connect \A $or$ls180.v:3843$270_Y + connect \B $and$ls180.v:3843$271_Y + connect \Y $or$ls180.v:3843$272_Y end - attribute \src "ls180.v:3975.40-3975.207" - cell $or $or$ls180.v:3975$374 + attribute \src "ls180.v:3844.40-3844.207" + cell $or $or$ls180.v:3844$275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3975$372_Y - connect \B $and$ls180.v:3975$373_Y - connect \Y $or$ls180.v:3975$374_Y + connect \A $and$ls180.v:3844$273_Y + connect \B $and$ls180.v:3844$274_Y + connect \Y $or$ls180.v:3844$275_Y end - attribute \src "ls180.v:3975.39-3975.293" - cell $or $or$ls180.v:3975$376 + attribute \src "ls180.v:3844.39-3844.293" + cell $or $or$ls180.v:3844$277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3975$374_Y - connect \B $and$ls180.v:3975$375_Y - connect \Y $or$ls180.v:3975$376_Y + connect \A $or$ls180.v:3844$275_Y + connect \B $and$ls180.v:3844$276_Y + connect \Y $or$ls180.v:3844$277_Y end - attribute \src "ls180.v:3975.38-3975.379" - cell $or $or$ls180.v:3975$378 + attribute \src "ls180.v:3844.38-3844.379" + cell $or $or$ls180.v:3844$279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3975$376_Y - connect \B $and$ls180.v:3975$377_Y - connect \Y $or$ls180.v:3975$378_Y + connect \A $or$ls180.v:3844$277_Y + connect \B $and$ls180.v:3844$278_Y + connect \Y $or$ls180.v:3844$279_Y end - attribute \src "ls180.v:3988.158-3988.332" - cell $or $or$ls180.v:3988$392 + attribute \src "ls180.v:3857.158-3857.332" + cell $or $or$ls180.v:3857$293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3988$391_Y + connect \A $not$ls180.v:3857$292_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3988$392_Y + connect \Y $or$ls180.v:3857$293_Y end - attribute \src "ls180.v:3988.75-3988.506" - cell $or $or$ls180.v:3988$397 + attribute \src "ls180.v:3857.75-3857.506" + cell $or $or$ls180.v:3857$298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3988$393_Y - connect \B $and$ls180.v:3988$396_Y - connect \Y $or$ls180.v:3988$397_Y + connect \A $and$ls180.v:3857$294_Y + connect \B $and$ls180.v:3857$297_Y + connect \Y $or$ls180.v:3857$298_Y end - attribute \src "ls180.v:3989.158-3989.332" - cell $or $or$ls180.v:3989$405 + attribute \src "ls180.v:3858.158-3858.332" + cell $or $or$ls180.v:3858$306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3989$404_Y + connect \A $not$ls180.v:3858$305_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3989$405_Y + connect \Y $or$ls180.v:3858$306_Y end - attribute \src "ls180.v:3989.75-3989.506" - cell $or $or$ls180.v:3989$410 + attribute \src "ls180.v:3858.75-3858.506" + cell $or $or$ls180.v:3858$311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3989$406_Y - connect \B $and$ls180.v:3989$409_Y - connect \Y $or$ls180.v:3989$410_Y + connect \A $and$ls180.v:3858$307_Y + connect \B $and$ls180.v:3858$310_Y + connect \Y $or$ls180.v:3858$311_Y end - attribute \src "ls180.v:3990.158-3990.332" - cell $or $or$ls180.v:3990$418 + attribute \src "ls180.v:3859.158-3859.332" + cell $or $or$ls180.v:3859$319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3990$417_Y + connect \A $not$ls180.v:3859$318_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3990$418_Y + connect \Y $or$ls180.v:3859$319_Y end - attribute \src "ls180.v:3990.75-3990.506" - cell $or $or$ls180.v:3990$423 + attribute \src "ls180.v:3859.75-3859.506" + cell $or $or$ls180.v:3859$324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3990$419_Y - connect \B $and$ls180.v:3990$422_Y - connect \Y $or$ls180.v:3990$423_Y + connect \A $and$ls180.v:3859$320_Y + connect \B $and$ls180.v:3859$323_Y + connect \Y $or$ls180.v:3859$324_Y end - attribute \src "ls180.v:3991.158-3991.332" - cell $or $or$ls180.v:3991$431 + attribute \src "ls180.v:3860.158-3860.332" + cell $or $or$ls180.v:3860$332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3991$430_Y + connect \A $not$ls180.v:3860$331_Y connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3991$431_Y + connect \Y $or$ls180.v:3860$332_Y end - attribute \src "ls180.v:3991.75-3991.506" - cell $or $or$ls180.v:3991$436 + attribute \src "ls180.v:3860.75-3860.506" + cell $or $or$ls180.v:3860$337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3991$432_Y - connect \B $and$ls180.v:3991$435_Y - connect \Y $or$ls180.v:3991$436_Y + connect \A $and$ls180.v:3860$333_Y + connect \B $and$ls180.v:3860$336_Y + connect \Y $or$ls180.v:3860$337_Y end - attribute \src "ls180.v:4018.36-4018.104" - cell $or $or$ls180.v:4018$442 + attribute \src "ls180.v:3887.36-3887.104" + cell $or $or$ls180.v:3887$343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_cmd_cmd_ready - connect \B $not$ls180.v:4018$441_Y - connect \Y $or$ls180.v:4018$442_Y + connect \B $not$ls180.v:3887$342_Y + connect \Y $or$ls180.v:3887$343_Y end - attribute \src "ls180.v:4021.158-4021.332" - cell $or $or$ls180.v:4021$450 + attribute \src "ls180.v:3890.158-3890.332" + cell $or $or$ls180.v:3890$351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4021$449_Y + connect \A $not$ls180.v:3890$350_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:4021$450_Y + connect \Y $or$ls180.v:3890$351_Y end - attribute \src "ls180.v:4021.75-4021.506" - cell $or $or$ls180.v:4021$455 + attribute \src "ls180.v:3890.75-3890.506" + cell $or $or$ls180.v:3890$356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4021$451_Y - connect \B $and$ls180.v:4021$454_Y - connect \Y $or$ls180.v:4021$455_Y + connect \A $and$ls180.v:3890$352_Y + connect \B $and$ls180.v:3890$355_Y + connect \Y $or$ls180.v:3890$356_Y end - attribute \src "ls180.v:4022.158-4022.332" - cell $or $or$ls180.v:4022$463 + attribute \src "ls180.v:3891.158-3891.332" + cell $or $or$ls180.v:3891$364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4022$462_Y + connect \A $not$ls180.v:3891$363_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:4022$463_Y + connect \Y $or$ls180.v:3891$364_Y end - attribute \src "ls180.v:4022.75-4022.506" - cell $or $or$ls180.v:4022$468 + attribute \src "ls180.v:3891.75-3891.506" + cell $or $or$ls180.v:3891$369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4022$464_Y - connect \B $and$ls180.v:4022$467_Y - connect \Y $or$ls180.v:4022$468_Y + connect \A $and$ls180.v:3891$365_Y + connect \B $and$ls180.v:3891$368_Y + connect \Y $or$ls180.v:3891$369_Y end - attribute \src "ls180.v:4023.158-4023.332" - cell $or $or$ls180.v:4023$476 + attribute \src "ls180.v:3892.158-3892.332" + cell $or $or$ls180.v:3892$377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4023$475_Y + connect \A $not$ls180.v:3892$376_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:4023$476_Y + connect \Y $or$ls180.v:3892$377_Y end - attribute \src "ls180.v:4023.75-4023.506" - cell $or $or$ls180.v:4023$481 + attribute \src "ls180.v:3892.75-3892.506" + cell $or $or$ls180.v:3892$382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4023$477_Y - connect \B $and$ls180.v:4023$480_Y - connect \Y $or$ls180.v:4023$481_Y + connect \A $and$ls180.v:3892$378_Y + connect \B $and$ls180.v:3892$381_Y + connect \Y $or$ls180.v:3892$382_Y end - attribute \src "ls180.v:4024.158-4024.332" - cell $or $or$ls180.v:4024$489 + attribute \src "ls180.v:3893.158-3893.332" + cell $or $or$ls180.v:3893$390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4024$488_Y + connect \A $not$ls180.v:3893$389_Y connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:4024$489_Y + connect \Y $or$ls180.v:3893$390_Y end - attribute \src "ls180.v:4024.75-4024.506" - cell $or $or$ls180.v:4024$494 + attribute \src "ls180.v:3893.75-3893.506" + cell $or $or$ls180.v:3893$395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4024$490_Y - connect \B $and$ls180.v:4024$493_Y - connect \Y $or$ls180.v:4024$494_Y + connect \A $and$ls180.v:3893$391_Y + connect \B $and$ls180.v:3893$394_Y + connect \Y $or$ls180.v:3893$395_Y end - attribute \src "ls180.v:4087.36-4087.104" - cell $or $or$ls180.v:4087$528 + attribute \src "ls180.v:3956.36-3956.104" + cell $or $or$ls180.v:3956$429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdram_choose_req_cmd_ready - connect \B $not$ls180.v:4087$527_Y - connect \Y $or$ls180.v:4087$528_Y + connect \B $not$ls180.v:3956$428_Y + connect \Y $or$ls180.v:3956$429_Y end - attribute \src "ls180.v:4108.67-4108.221" - cell $or $or$ls180.v:4108$535 + attribute \src "ls180.v:3977.67-3977.221" + cell $or $or$ls180.v:3977$436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4108$534_Y + connect \A $not$ls180.v:3977$435_Y connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:4108$535_Y + connect \Y $or$ls180.v:3977$436_Y end - attribute \src "ls180.v:4116.10-4116.62" - cell $or $or$ls180.v:4116$538 + attribute \src "ls180.v:3985.10-3985.62" + cell $or $or$ls180.v:3985$439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4116$537_Y + connect \A $not$ls180.v:3985$438_Y connect \B \main_sdram_max_time1 - connect \Y $or$ls180.v:4116$538_Y + connect \Y $or$ls180.v:3985$439_Y end - attribute \src "ls180.v:4146.67-4146.221" - cell $or $or$ls180.v:4146$544 + attribute \src "ls180.v:4015.67-4015.221" + cell $or $or$ls180.v:4015$445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4146$543_Y + connect \A $not$ls180.v:4015$444_Y connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:4146$544_Y + connect \Y $or$ls180.v:4015$445_Y end - attribute \src "ls180.v:4154.10-4154.61" - cell $or $or$ls180.v:4154$547 + attribute \src "ls180.v:4023.10-4023.61" + cell $or $or$ls180.v:4023$448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4154$546_Y + connect \A $not$ls180.v:4023$447_Y connect \B \main_sdram_max_time0 - connect \Y $or$ls180.v:4154$547_Y + connect \Y $or$ls180.v:4023$448_Y end - attribute \src "ls180.v:4164.91-4164.180" - cell $or $or$ls180.v:4164$551 + attribute \src "ls180.v:4033.91-4033.180" + cell $or $or$ls180.v:4033$452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:4164$550_Y - connect \Y $or$ls180.v:4164$551_Y + connect \B $and$ls180.v:4033$451_Y + connect \Y $or$ls180.v:4033$452_Y end - attribute \src "ls180.v:4164.90-4164.255" - cell $or $or$ls180.v:4164$554 + attribute \src "ls180.v:4033.90-4033.255" + cell $or $or$ls180.v:4033$455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4164$551_Y - connect \B $and$ls180.v:4164$553_Y - connect \Y $or$ls180.v:4164$554_Y + connect \A $or$ls180.v:4033$452_Y + connect \B $and$ls180.v:4033$454_Y + connect \Y $or$ls180.v:4033$455_Y end - attribute \src "ls180.v:4164.89-4164.330" - cell $or $or$ls180.v:4164$557 + attribute \src "ls180.v:4033.89-4033.330" + cell $or $or$ls180.v:4033$458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4164$554_Y - connect \B $and$ls180.v:4164$556_Y - connect \Y $or$ls180.v:4164$557_Y + connect \A $or$ls180.v:4033$455_Y + connect \B $and$ls180.v:4033$457_Y + connect \Y $or$ls180.v:4033$458_Y end - attribute \src "ls180.v:4169.91-4169.180" - cell $or $or$ls180.v:4169$567 + attribute \src "ls180.v:4038.91-4038.180" + cell $or $or$ls180.v:4038$468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:4169$566_Y - connect \Y $or$ls180.v:4169$567_Y + connect \B $and$ls180.v:4038$467_Y + connect \Y $or$ls180.v:4038$468_Y end - attribute \src "ls180.v:4169.90-4169.255" - cell $or $or$ls180.v:4169$570 + attribute \src "ls180.v:4038.90-4038.255" + cell $or $or$ls180.v:4038$471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4169$567_Y - connect \B $and$ls180.v:4169$569_Y - connect \Y $or$ls180.v:4169$570_Y + connect \A $or$ls180.v:4038$468_Y + connect \B $and$ls180.v:4038$470_Y + connect \Y $or$ls180.v:4038$471_Y end - attribute \src "ls180.v:4169.89-4169.330" - cell $or $or$ls180.v:4169$573 + attribute \src "ls180.v:4038.89-4038.330" + cell $or $or$ls180.v:4038$474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4169$570_Y - connect \B $and$ls180.v:4169$572_Y - connect \Y $or$ls180.v:4169$573_Y + connect \A $or$ls180.v:4038$471_Y + connect \B $and$ls180.v:4038$473_Y + connect \Y $or$ls180.v:4038$474_Y end - attribute \src "ls180.v:4174.91-4174.180" - cell $or $or$ls180.v:4174$583 + attribute \src "ls180.v:4043.91-4043.180" + cell $or $or$ls180.v:4043$484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:4174$582_Y - connect \Y $or$ls180.v:4174$583_Y + connect \B $and$ls180.v:4043$483_Y + connect \Y $or$ls180.v:4043$484_Y end - attribute \src "ls180.v:4174.90-4174.255" - cell $or $or$ls180.v:4174$586 + attribute \src "ls180.v:4043.90-4043.255" + cell $or $or$ls180.v:4043$487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4174$583_Y - connect \B $and$ls180.v:4174$585_Y - connect \Y $or$ls180.v:4174$586_Y + connect \A $or$ls180.v:4043$484_Y + connect \B $and$ls180.v:4043$486_Y + connect \Y $or$ls180.v:4043$487_Y end - attribute \src "ls180.v:4174.89-4174.330" - cell $or $or$ls180.v:4174$589 + attribute \src "ls180.v:4043.89-4043.330" + cell $or $or$ls180.v:4043$490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4174$586_Y - connect \B $and$ls180.v:4174$588_Y - connect \Y $or$ls180.v:4174$589_Y + connect \A $or$ls180.v:4043$487_Y + connect \B $and$ls180.v:4043$489_Y + connect \Y $or$ls180.v:4043$490_Y end - attribute \src "ls180.v:4179.91-4179.180" - cell $or $or$ls180.v:4179$599 + attribute \src "ls180.v:4048.91-4048.180" + cell $or $or$ls180.v:4048$500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:4179$598_Y - connect \Y $or$ls180.v:4179$599_Y + connect \B $and$ls180.v:4048$499_Y + connect \Y $or$ls180.v:4048$500_Y end - attribute \src "ls180.v:4179.90-4179.255" - cell $or $or$ls180.v:4179$602 + attribute \src "ls180.v:4048.90-4048.255" + cell $or $or$ls180.v:4048$503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4179$599_Y - connect \B $and$ls180.v:4179$601_Y - connect \Y $or$ls180.v:4179$602_Y + connect \A $or$ls180.v:4048$500_Y + connect \B $and$ls180.v:4048$502_Y + connect \Y $or$ls180.v:4048$503_Y end - attribute \src "ls180.v:4179.89-4179.330" - cell $or $or$ls180.v:4179$605 + attribute \src "ls180.v:4048.89-4048.330" + cell $or $or$ls180.v:4048$506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4179$602_Y - connect \B $and$ls180.v:4179$604_Y - connect \Y $or$ls180.v:4179$605_Y + connect \A $or$ls180.v:4048$503_Y + connect \B $and$ls180.v:4048$505_Y + connect \Y $or$ls180.v:4048$506_Y end - attribute \src "ls180.v:4184.132-4184.221" - cell $or $or$ls180.v:4184$616 + attribute \src "ls180.v:4053.132-4053.221" + cell $or $or$ls180.v:4053$517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:4184$615_Y - connect \Y $or$ls180.v:4184$616_Y + connect \B $and$ls180.v:4053$516_Y + connect \Y $or$ls180.v:4053$517_Y end - attribute \src "ls180.v:4184.131-4184.296" - cell $or $or$ls180.v:4184$619 + attribute \src "ls180.v:4053.131-4053.296" + cell $or $or$ls180.v:4053$520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$616_Y - connect \B $and$ls180.v:4184$618_Y - connect \Y $or$ls180.v:4184$619_Y + connect \A $or$ls180.v:4053$517_Y + connect \B $and$ls180.v:4053$519_Y + connect \Y $or$ls180.v:4053$520_Y end - attribute \src "ls180.v:4184.130-4184.371" - cell $or $or$ls180.v:4184$622 + attribute \src "ls180.v:4053.130-4053.371" + cell $or $or$ls180.v:4053$523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$619_Y - connect \B $and$ls180.v:4184$621_Y - connect \Y $or$ls180.v:4184$622_Y + connect \A $or$ls180.v:4053$520_Y + connect \B $and$ls180.v:4053$522_Y + connect \Y $or$ls180.v:4053$523_Y end - attribute \src "ls180.v:4184.34-4184.411" - cell $or $or$ls180.v:4184$627 + attribute \src "ls180.v:4053.34-4053.411" + cell $or $or$ls180.v:4053$528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:4184$626_Y - connect \Y $or$ls180.v:4184$627_Y + connect \B $and$ls180.v:4053$527_Y + connect \Y $or$ls180.v:4053$528_Y end - attribute \src "ls180.v:4184.506-4184.595" - cell $or $or$ls180.v:4184$632 + attribute \src "ls180.v:4053.506-4053.595" + cell $or $or$ls180.v:4053$533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:4184$631_Y - connect \Y $or$ls180.v:4184$632_Y + connect \B $and$ls180.v:4053$532_Y + connect \Y $or$ls180.v:4053$533_Y end - attribute \src "ls180.v:4184.505-4184.670" - cell $or $or$ls180.v:4184$635 + attribute \src "ls180.v:4053.505-4053.670" + cell $or $or$ls180.v:4053$536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$632_Y - connect \B $and$ls180.v:4184$634_Y - connect \Y $or$ls180.v:4184$635_Y + connect \A $or$ls180.v:4053$533_Y + connect \B $and$ls180.v:4053$535_Y + connect \Y $or$ls180.v:4053$536_Y end - attribute \src "ls180.v:4184.504-4184.745" - cell $or $or$ls180.v:4184$638 + attribute \src "ls180.v:4053.504-4053.745" + cell $or $or$ls180.v:4053$539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$635_Y - connect \B $and$ls180.v:4184$637_Y - connect \Y $or$ls180.v:4184$638_Y + connect \A $or$ls180.v:4053$536_Y + connect \B $and$ls180.v:4053$538_Y + connect \Y $or$ls180.v:4053$539_Y end - attribute \src "ls180.v:4184.33-4184.785" - cell $or $or$ls180.v:4184$643 + attribute \src "ls180.v:4053.33-4053.785" + cell $or $or$ls180.v:4053$544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$627_Y - connect \B $and$ls180.v:4184$642_Y - connect \Y $or$ls180.v:4184$643_Y + connect \A $or$ls180.v:4053$528_Y + connect \B $and$ls180.v:4053$543_Y + connect \Y $or$ls180.v:4053$544_Y end - attribute \src "ls180.v:4184.880-4184.969" - cell $or $or$ls180.v:4184$648 + attribute \src "ls180.v:4053.880-4053.969" + cell $or $or$ls180.v:4053$549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:4184$647_Y - connect \Y $or$ls180.v:4184$648_Y + connect \B $and$ls180.v:4053$548_Y + connect \Y $or$ls180.v:4053$549_Y end - attribute \src "ls180.v:4184.879-4184.1044" - cell $or $or$ls180.v:4184$651 + attribute \src "ls180.v:4053.879-4053.1044" + cell $or $or$ls180.v:4053$552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$648_Y - connect \B $and$ls180.v:4184$650_Y - connect \Y $or$ls180.v:4184$651_Y + connect \A $or$ls180.v:4053$549_Y + connect \B $and$ls180.v:4053$551_Y + connect \Y $or$ls180.v:4053$552_Y end - attribute \src "ls180.v:4184.878-4184.1119" - cell $or $or$ls180.v:4184$654 + attribute \src "ls180.v:4053.878-4053.1119" + cell $or $or$ls180.v:4053$555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$651_Y - connect \B $and$ls180.v:4184$653_Y - connect \Y $or$ls180.v:4184$654_Y + connect \A $or$ls180.v:4053$552_Y + connect \B $and$ls180.v:4053$554_Y + connect \Y $or$ls180.v:4053$555_Y end - attribute \src "ls180.v:4184.32-4184.1159" - cell $or $or$ls180.v:4184$659 + attribute \src "ls180.v:4053.32-4053.1159" + cell $or $or$ls180.v:4053$560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$643_Y - connect \B $and$ls180.v:4184$658_Y - connect \Y $or$ls180.v:4184$659_Y + connect \A $or$ls180.v:4053$544_Y + connect \B $and$ls180.v:4053$559_Y + connect \Y $or$ls180.v:4053$560_Y end - attribute \src "ls180.v:4184.1254-4184.1343" - cell $or $or$ls180.v:4184$664 + attribute \src "ls180.v:4053.1254-4053.1343" + cell $or $or$ls180.v:4053$565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:4184$663_Y - connect \Y $or$ls180.v:4184$664_Y + connect \B $and$ls180.v:4053$564_Y + connect \Y $or$ls180.v:4053$565_Y end - attribute \src "ls180.v:4184.1253-4184.1418" - cell $or $or$ls180.v:4184$667 + attribute \src "ls180.v:4053.1253-4053.1418" + cell $or $or$ls180.v:4053$568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$664_Y - connect \B $and$ls180.v:4184$666_Y - connect \Y $or$ls180.v:4184$667_Y + connect \A $or$ls180.v:4053$565_Y + connect \B $and$ls180.v:4053$567_Y + connect \Y $or$ls180.v:4053$568_Y end - attribute \src "ls180.v:4184.1252-4184.1493" - cell $or $or$ls180.v:4184$670 + attribute \src "ls180.v:4053.1252-4053.1493" + cell $or $or$ls180.v:4053$571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$667_Y - connect \B $and$ls180.v:4184$669_Y - connect \Y $or$ls180.v:4184$670_Y + connect \A $or$ls180.v:4053$568_Y + connect \B $and$ls180.v:4053$570_Y + connect \Y $or$ls180.v:4053$571_Y end - attribute \src "ls180.v:4184.31-4184.1533" - cell $or $or$ls180.v:4184$675 + attribute \src "ls180.v:4053.31-4053.1533" + cell $or $or$ls180.v:4053$576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4184$659_Y - connect \B $and$ls180.v:4184$674_Y - connect \Y $or$ls180.v:4184$675_Y + connect \A $or$ls180.v:4053$560_Y + connect \B $and$ls180.v:4053$575_Y + connect \Y $or$ls180.v:4053$576_Y end - attribute \src "ls180.v:4247.10-4247.52" - cell $or $or$ls180.v:4247$684 + attribute \src "ls180.v:4116.10-4116.52" + cell $or $or$ls180.v:4116$585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279520,10 +277290,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_ack connect \B \main_converter_skip - connect \Y $or$ls180.v:4247$684_Y + connect \Y $or$ls180.v:4116$585_Y end - attribute \src "ls180.v:4274.35-4274.74" - cell $or $or$ls180.v:4274$694 + attribute \src "ls180.v:4143.35-4143.74" + cell $or $or$ls180.v:4143$595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279531,10 +277301,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4274$694_Y + connect \Y $or$ls180.v:4143$595_Y end - attribute \src "ls180.v:4275.34-4275.73" - cell $or $or$ls180.v:4275$698 + attribute \src "ls180.v:4144.34-4144.73" + cell $or $or$ls180.v:4144$599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279542,76 +277312,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_port_cmd_valid connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4275$698_Y + connect \Y $or$ls180.v:4144$599_Y end - attribute \src "ls180.v:4276.48-4276.130" - cell $or $or$ls180.v:4276$704 + attribute \src "ls180.v:4145.48-4145.130" + cell $or $or$ls180.v:4145$605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4276$701_Y - connect \B $and$ls180.v:4276$703_Y - connect \Y $or$ls180.v:4276$704_Y + connect \A $and$ls180.v:4145$602_Y + connect \B $and$ls180.v:4145$604_Y + connect \Y $or$ls180.v:4145$605_Y end - attribute \src "ls180.v:4277.24-4277.87" - cell $or $or$ls180.v:4277$707 + attribute \src "ls180.v:4146.24-4146.87" + cell $or $or$ls180.v:4146$608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4277$706_Y + connect \A $and$ls180.v:4146$607_Y connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4277$707_Y + connect \Y $or$ls180.v:4146$608_Y end - attribute \src "ls180.v:4278.26-4278.95" - cell $or $or$ls180.v:4278$709 + attribute \src "ls180.v:4147.26-4147.95" + cell $or $or$ls180.v:4147$610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4278$708_Y + connect \A $and$ls180.v:4147$609_Y connect \B \main_wdata_consumed - connect \Y $or$ls180.v:4278$709_Y + connect \Y $or$ls180.v:4147$610_Y end - attribute \src "ls180.v:4308.42-4308.89" - cell $or $or$ls180.v:4308$717 + attribute \src "ls180.v:4177.42-4177.89" + cell $or $or$ls180.v:4177$618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_uart_rx_clear - connect \B $and$ls180.v:4308$716_Y - connect \Y $or$ls180.v:4308$717_Y + connect \B $and$ls180.v:4177$617_Y + connect \Y $or$ls180.v:4177$618_Y end - attribute \src "ls180.v:4332.25-4332.174" - cell $or $or$ls180.v:4332$727 + attribute \src "ls180.v:4201.25-4201.174" + cell $or $or$ls180.v:4201$628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4332$725_Y - connect \B $and$ls180.v:4332$726_Y - connect \Y $or$ls180.v:4332$727_Y + connect \A $and$ls180.v:4201$626_Y + connect \B $and$ls180.v:4201$627_Y + connect \Y $or$ls180.v:4201$628_Y end - attribute \src "ls180.v:4347.80-4347.132" - cell $or $or$ls180.v:4347$729 + attribute \src "ls180.v:4216.80-4216.132" + cell $or $or$ls180.v:4216$630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4347$728_Y + connect \A $not$ls180.v:4216$629_Y connect \B \main_uart_tx_fifo_re - connect \Y $or$ls180.v:4347$729_Y + connect \Y $or$ls180.v:4216$630_Y end - attribute \src "ls180.v:4358.72-4358.135" - cell $or $or$ls180.v:4358$734 + attribute \src "ls180.v:4227.72-4227.135" + cell $or $or$ls180.v:4227$635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279619,21 +277389,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_tx_fifo_syncfifo_writable connect \B \main_uart_tx_fifo_replace - connect \Y $or$ls180.v:4358$734_Y + connect \Y $or$ls180.v:4227$635_Y end - attribute \src "ls180.v:4377.80-4377.132" - cell $or $or$ls180.v:4377$740 + attribute \src "ls180.v:4246.80-4246.132" + cell $or $or$ls180.v:4246$641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4377$739_Y + connect \A $not$ls180.v:4246$640_Y connect \B \main_uart_rx_fifo_re - connect \Y $or$ls180.v:4377$740_Y + connect \Y $or$ls180.v:4246$641_Y end - attribute \src "ls180.v:4388.72-4388.135" - cell $or $or$ls180.v:4388$745 + attribute \src "ls180.v:4257.72-4257.135" + cell $or $or$ls180.v:4257$646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279641,10 +277411,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_uart_rx_fifo_syncfifo_writable connect \B \main_uart_rx_fifo_replace - connect \Y $or$ls180.v:4388$745_Y + connect \Y $or$ls180.v:4257$646_Y end - attribute \src "ls180.v:4533.36-4533.111" - cell $or $or$ls180.v:4533$768 + attribute \src "ls180.v:4402.36-4402.111" + cell $or $or$ls180.v:4402$669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279652,43 +277422,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_clk connect \B \main_sdphy_cmdw_pads_out_payload_clk - connect \Y $or$ls180.v:4533$768_Y + connect \Y $or$ls180.v:4402$669_Y end - attribute \src "ls180.v:4533.35-4533.151" - cell $or $or$ls180.v:4533$769 + attribute \src "ls180.v:4402.35-4402.151" + cell $or $or$ls180.v:4402$670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4533$768_Y + connect \A $or$ls180.v:4402$669_Y connect \B \main_sdphy_cmdr_pads_out_payload_clk - connect \Y $or$ls180.v:4533$769_Y + connect \Y $or$ls180.v:4402$670_Y end - attribute \src "ls180.v:4533.34-4533.192" - cell $or $or$ls180.v:4533$770 + attribute \src "ls180.v:4402.34-4402.192" + cell $or $or$ls180.v:4402$671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4533$769_Y + connect \A $or$ls180.v:4402$670_Y connect \B \main_sdphy_dataw_pads_out_payload_clk - connect \Y $or$ls180.v:4533$770_Y + connect \Y $or$ls180.v:4402$671_Y end - attribute \src "ls180.v:4533.33-4533.233" - cell $or $or$ls180.v:4533$771 + attribute \src "ls180.v:4402.33-4402.233" + cell $or $or$ls180.v:4402$672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4533$770_Y + connect \A $or$ls180.v:4402$671_Y connect \B \main_sdphy_datar_pads_out_payload_clk - connect \Y $or$ls180.v:4533$771_Y + connect \Y $or$ls180.v:4402$672_Y end - attribute \src "ls180.v:4534.39-4534.120" - cell $or $or$ls180.v:4534$772 + attribute \src "ls180.v:4403.39-4403.120" + cell $or $or$ls180.v:4403$673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279696,43 +277466,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_cmd_oe connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4534$772_Y + connect \Y $or$ls180.v:4403$673_Y end - attribute \src "ls180.v:4534.38-4534.163" - cell $or $or$ls180.v:4534$773 + attribute \src "ls180.v:4403.38-4403.163" + cell $or $or$ls180.v:4403$674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4534$772_Y + connect \A $or$ls180.v:4403$673_Y connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4534$773_Y + connect \Y $or$ls180.v:4403$674_Y end - attribute \src "ls180.v:4534.37-4534.207" - cell $or $or$ls180.v:4534$774 + attribute \src "ls180.v:4403.37-4403.207" + cell $or $or$ls180.v:4403$675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4534$773_Y + connect \A $or$ls180.v:4403$674_Y connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4534$774_Y + connect \Y $or$ls180.v:4403$675_Y end - attribute \src "ls180.v:4534.36-4534.251" - cell $or $or$ls180.v:4534$775 + attribute \src "ls180.v:4403.36-4403.251" + cell $or $or$ls180.v:4403$676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4534$774_Y + connect \A $or$ls180.v:4403$675_Y connect \B \main_sdphy_datar_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4534$775_Y + connect \Y $or$ls180.v:4403$676_Y end - attribute \src "ls180.v:4535.38-4535.117" - cell $or $or$ls180.v:4535$776 + attribute \src "ls180.v:4404.38-4404.117" + cell $or $or$ls180.v:4404$677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279740,43 +277510,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_cmd_o connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4535$776_Y + connect \Y $or$ls180.v:4404$677_Y end - attribute \src "ls180.v:4535.37-4535.159" - cell $or $or$ls180.v:4535$777 + attribute \src "ls180.v:4404.37-4404.159" + cell $or $or$ls180.v:4404$678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4535$776_Y + connect \A $or$ls180.v:4404$677_Y connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4535$777_Y + connect \Y $or$ls180.v:4404$678_Y end - attribute \src "ls180.v:4535.36-4535.202" - cell $or $or$ls180.v:4535$778 + attribute \src "ls180.v:4404.36-4404.202" + cell $or $or$ls180.v:4404$679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4535$777_Y + connect \A $or$ls180.v:4404$678_Y connect \B \main_sdphy_dataw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4535$778_Y + connect \Y $or$ls180.v:4404$679_Y end - attribute \src "ls180.v:4535.35-4535.245" - cell $or $or$ls180.v:4535$779 + attribute \src "ls180.v:4404.35-4404.245" + cell $or $or$ls180.v:4404$680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4535$778_Y + connect \A $or$ls180.v:4404$679_Y connect \B \main_sdphy_datar_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4535$779_Y + connect \Y $or$ls180.v:4404$680_Y end - attribute \src "ls180.v:4536.40-4536.123" - cell $or $or$ls180.v:4536$780 + attribute \src "ls180.v:4405.40-4405.123" + cell $or $or$ls180.v:4405$681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279784,43 +277554,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_init_pads_out_payload_data_oe connect \B \main_sdphy_cmdw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4536$780_Y + connect \Y $or$ls180.v:4405$681_Y end - attribute \src "ls180.v:4536.39-4536.167" - cell $or $or$ls180.v:4536$781 + attribute \src "ls180.v:4405.39-4405.167" + cell $or $or$ls180.v:4405$682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4536$780_Y + connect \A $or$ls180.v:4405$681_Y connect \B \main_sdphy_cmdr_pads_out_payload_data_oe - connect \Y $or$ls180.v:4536$781_Y + connect \Y $or$ls180.v:4405$682_Y end - attribute \src "ls180.v:4536.38-4536.212" - cell $or $or$ls180.v:4536$782 + attribute \src "ls180.v:4405.38-4405.212" + cell $or $or$ls180.v:4405$683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4536$781_Y + connect \A $or$ls180.v:4405$682_Y connect \B \main_sdphy_dataw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4536$782_Y + connect \Y $or$ls180.v:4405$683_Y end - attribute \src "ls180.v:4536.37-4536.257" - cell $or $or$ls180.v:4536$783 + attribute \src "ls180.v:4405.37-4405.257" + cell $or $or$ls180.v:4405$684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4536$782_Y + connect \A $or$ls180.v:4405$683_Y connect \B \main_sdphy_datar_pads_out_payload_data_oe - connect \Y $or$ls180.v:4536$783_Y + connect \Y $or$ls180.v:4405$684_Y end - attribute \src "ls180.v:4537.39-4537.120" - cell $or $or$ls180.v:4537$784 + attribute \src "ls180.v:4406.39-4406.120" + cell $or $or$ls180.v:4406$685 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -279828,43 +277598,43 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdphy_init_pads_out_payload_data_o connect \B \main_sdphy_cmdw_pads_out_payload_data_o - connect \Y $or$ls180.v:4537$784_Y + connect \Y $or$ls180.v:4406$685_Y end - attribute \src "ls180.v:4537.38-4537.163" - cell $or $or$ls180.v:4537$785 + attribute \src "ls180.v:4406.38-4406.163" + cell $or $or$ls180.v:4406$686 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4537$784_Y + connect \A $or$ls180.v:4406$685_Y connect \B \main_sdphy_cmdr_pads_out_payload_data_o - connect \Y $or$ls180.v:4537$785_Y + connect \Y $or$ls180.v:4406$686_Y end - attribute \src "ls180.v:4537.37-4537.207" - cell $or $or$ls180.v:4537$786 + attribute \src "ls180.v:4406.37-4406.207" + cell $or $or$ls180.v:4406$687 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4537$785_Y + connect \A $or$ls180.v:4406$686_Y connect \B \main_sdphy_dataw_pads_out_payload_data_o - connect \Y $or$ls180.v:4537$786_Y + connect \Y $or$ls180.v:4406$687_Y end - attribute \src "ls180.v:4537.36-4537.251" - cell $or $or$ls180.v:4537$787 + attribute \src "ls180.v:4406.36-4406.251" + cell $or $or$ls180.v:4406$688 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4537$786_Y + connect \A $or$ls180.v:4406$687_Y connect \B \main_sdphy_datar_pads_out_payload_data_o - connect \Y $or$ls180.v:4537$787_Y + connect \Y $or$ls180.v:4406$688_Y end - attribute \src "ls180.v:4558.35-4558.80" - cell $or $or$ls180.v:4558$788 + attribute \src "ls180.v:4427.35-4427.80" + cell $or $or$ls180.v:4427$689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279872,10 +277642,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_stop connect \B \main_sdphy_datar_stop - connect \Y $or$ls180.v:4558$788_Y + connect \Y $or$ls180.v:4427$689_Y end - attribute \src "ls180.v:4712.91-4712.144" - cell $or $or$ls180.v:4712$802 + attribute \src "ls180.v:4581.91-4581.144" + cell $or $or$ls180.v:4581$703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279883,76 +277653,76 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_start connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:4712$802_Y + connect \Y $or$ls180.v:4581$703_Y end - attribute \src "ls180.v:4729.53-4729.143" - cell $or $or$ls180.v:4729$805 + attribute \src "ls180.v:4598.53-4598.143" + cell $or $or$ls180.v:4598$706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4729$804_Y + connect \A $not$ls180.v:4598$705_Y connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $or$ls180.v:4729$805_Y + connect \Y $or$ls180.v:4598$706_Y end - attribute \src "ls180.v:4732.47-4732.127" - cell $or $or$ls180.v:4732$808 + attribute \src "ls180.v:4601.47-4601.127" + cell $or $or$ls180.v:4601$709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4732$807_Y + connect \A $not$ls180.v:4601$708_Y connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:4732$808_Y + connect \Y $or$ls180.v:4601$709_Y end - attribute \src "ls180.v:4856.54-4856.146" - cell $or $or$ls180.v:4856$826 + attribute \src "ls180.v:4725.54-4725.146" + cell $or $or$ls180.v:4725$727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4856$825_Y + connect \A $not$ls180.v:4725$726_Y connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $or$ls180.v:4856$826_Y + connect \Y $or$ls180.v:4725$727_Y end - attribute \src "ls180.v:4859.48-4859.130" - cell $or $or$ls180.v:4859$829 + attribute \src "ls180.v:4728.48-4728.130" + cell $or $or$ls180.v:4728$730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4859$828_Y + connect \A $not$ls180.v:4728$729_Y connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:4859$829_Y + connect \Y $or$ls180.v:4728$730_Y end - attribute \src "ls180.v:4990.55-4990.149" - cell $or $or$ls180.v:4990$841 + attribute \src "ls180.v:4859.55-4859.149" + cell $or $or$ls180.v:4859$742 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4990$840_Y + connect \A $not$ls180.v:4859$741_Y connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $or$ls180.v:4990$841_Y + connect \Y $or$ls180.v:4859$742_Y end - attribute \src "ls180.v:4993.49-4993.133" - cell $or $or$ls180.v:4993$844 + attribute \src "ls180.v:4862.49-4862.133" + cell $or $or$ls180.v:4862$745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4993$843_Y + connect \A $not$ls180.v:4862$744_Y connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:4993$844_Y + connect \Y $or$ls180.v:4862$745_Y end - attribute \src "ls180.v:5622.80-5622.151" - cell $or $or$ls180.v:5622$1139 + attribute \src "ls180.v:5491.80-5491.151" + cell $or $or$ls180.v:5491$1040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279960,21 +277730,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_fifo_syncfifo_writable connect \B \main_sdblock2mem_fifo_replace - connect \Y $or$ls180.v:5622$1139_Y + connect \Y $or$ls180.v:5491$1040_Y end - attribute \src "ls180.v:5633.49-5633.131" - cell $or $or$ls180.v:5633$1145 + attribute \src "ls180.v:5502.49-5502.131" + cell $or $or$ls180.v:5502$1046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:5633$1144_Y + connect \A $not$ls180.v:5502$1045_Y connect \B \main_sdblock2mem_converter_source_ready - connect \Y $or$ls180.v:5633$1145_Y + connect \Y $or$ls180.v:5502$1046_Y end - attribute \src "ls180.v:5842.80-5842.151" - cell $or $or$ls180.v:5842$1170 + attribute \src "ls180.v:5711.80-5711.151" + cell $or $or$ls180.v:5711$1071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -279982,406 +277752,175 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdmem2block_fifo_syncfifo_writable connect \B \main_sdmem2block_fifo_replace - connect \Y $or$ls180.v:5842$1170_Y + connect \Y $or$ls180.v:5711$1071_Y end - attribute \src "ls180.v:6029.41-6029.99" - cell $or $or$ls180.v:6029$1226 + attribute \src "ls180.v:5835.34-5835.89" + cell $or $or$ls180.v:5835$1113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_err - connect \B \main_interface0_ram_bus_err - connect \Y $or$ls180.v:6029$1226_Y + connect \B \main_ram_bus_ram_bus_err + connect \Y $or$ls180.v:5835$1113_Y end - attribute \src "ls180.v:6029.40-6029.130" - cell $or $or$ls180.v:6029$1227 + attribute \src "ls180.v:5835.33-5835.132" + cell $or $or$ls180.v:5835$1114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1226_Y - connect \B \main_interface1_ram_bus_err - connect \Y $or$ls180.v:6029$1227_Y - end - attribute \src "ls180.v:6029.39-6029.161" - cell $or $or$ls180.v:6029$1228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1227_Y - connect \B \main_interface2_ram_bus_err - connect \Y $or$ls180.v:6029$1228_Y - end - attribute \src "ls180.v:6029.38-6029.192" - cell $or $or$ls180.v:6029$1229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1228_Y - connect \B \main_interface3_ram_bus_err - connect \Y $or$ls180.v:6029$1229_Y - end - attribute \src "ls180.v:6029.37-6029.235" - cell $or $or$ls180.v:6029$1230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1229_Y + connect \A $or$ls180.v:5835$1113_Y connect \B \main_interface0_converted_interface_err - connect \Y $or$ls180.v:6029$1230_Y + connect \Y $or$ls180.v:5835$1114_Y end - attribute \src "ls180.v:6029.36-6029.278" - cell $or $or$ls180.v:6029$1231 + attribute \src "ls180.v:5835.32-5835.175" + cell $or $or$ls180.v:5835$1115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1230_Y + connect \A $or$ls180.v:5835$1114_Y connect \B \main_interface1_converted_interface_err - connect \Y $or$ls180.v:6029$1231_Y - end - attribute \src "ls180.v:6029.35-6029.322" - cell $or $or$ls180.v:6029$1232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1231_Y - connect \B \main_libresocsim_libresoc_interface0_err - connect \Y $or$ls180.v:6029$1232_Y - end - attribute \src "ls180.v:6029.34-6029.366" - cell $or $or$ls180.v:6029$1233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1232_Y - connect \B \main_libresocsim_libresoc_interface1_err - connect \Y $or$ls180.v:6029$1233_Y + connect \Y $or$ls180.v:5835$1115_Y end - attribute \src "ls180.v:6029.33-6029.410" - cell $or $or$ls180.v:6029$1234 + attribute \src "ls180.v:5835.31-5835.221" + cell $or $or$ls180.v:5835$1116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1233_Y - connect \B \main_libresocsim_libresoc_interface2_err - connect \Y $or$ls180.v:6029$1234_Y - end - attribute \src "ls180.v:6029.32-6029.454" - cell $or $or$ls180.v:6029$1235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1234_Y - connect \B \main_libresocsim_libresoc_interface3_err - connect \Y $or$ls180.v:6029$1235_Y - end - attribute \src "ls180.v:6029.31-6029.500" - cell $or $or$ls180.v:6029$1236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1235_Y + connect \A $or$ls180.v:5835$1115_Y connect \B \main_socbushandler_converted_interface_err - connect \Y $or$ls180.v:6029$1236_Y + connect \Y $or$ls180.v:5835$1116_Y end - attribute \src "ls180.v:6029.30-6029.547" - cell $or $or$ls180.v:6029$1237 + attribute \src "ls180.v:5835.30-5835.268" + cell $or $or$ls180.v:5835$1117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6029$1236_Y + connect \A $or$ls180.v:5835$1116_Y connect \B \builder_libresocsim_converted_interface_err - connect \Y $or$ls180.v:6029$1237_Y + connect \Y $or$ls180.v:5835$1117_Y end - attribute \src "ls180.v:6035.36-6035.94" - cell $or $or$ls180.v:6035$1242 + attribute \src "ls180.v:5841.29-5841.84" + cell $or $or$ls180.v:5841$1122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_libresocsim_ram_bus_ack - connect \B \main_interface0_ram_bus_ack - connect \Y $or$ls180.v:6035$1242_Y - end - attribute \src "ls180.v:6035.35-6035.125" - cell $or $or$ls180.v:6035$1243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1242_Y - connect \B \main_interface1_ram_bus_ack - connect \Y $or$ls180.v:6035$1243_Y - end - attribute \src "ls180.v:6035.34-6035.156" - cell $or $or$ls180.v:6035$1244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1243_Y - connect \B \main_interface2_ram_bus_ack - connect \Y $or$ls180.v:6035$1244_Y - end - attribute \src "ls180.v:6035.33-6035.187" - cell $or $or$ls180.v:6035$1245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1244_Y - connect \B \main_interface3_ram_bus_ack - connect \Y $or$ls180.v:6035$1245_Y + connect \B \main_ram_bus_ram_bus_ack + connect \Y $or$ls180.v:5841$1122_Y end - attribute \src "ls180.v:6035.32-6035.230" - cell $or $or$ls180.v:6035$1246 + attribute \src "ls180.v:5841.28-5841.127" + cell $or $or$ls180.v:5841$1123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1245_Y + connect \A $or$ls180.v:5841$1122_Y connect \B \main_interface0_converted_interface_ack - connect \Y $or$ls180.v:6035$1246_Y + connect \Y $or$ls180.v:5841$1123_Y end - attribute \src "ls180.v:6035.31-6035.273" - cell $or $or$ls180.v:6035$1247 + attribute \src "ls180.v:5841.27-5841.170" + cell $or $or$ls180.v:5841$1124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1246_Y + connect \A $or$ls180.v:5841$1123_Y connect \B \main_interface1_converted_interface_ack - connect \Y $or$ls180.v:6035$1247_Y - end - attribute \src "ls180.v:6035.30-6035.317" - cell $or $or$ls180.v:6035$1248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1247_Y - connect \B \main_libresocsim_libresoc_interface0_ack - connect \Y $or$ls180.v:6035$1248_Y + connect \Y $or$ls180.v:5841$1124_Y end - attribute \src "ls180.v:6035.29-6035.361" - cell $or $or$ls180.v:6035$1249 + attribute \src "ls180.v:5841.26-5841.216" + cell $or $or$ls180.v:5841$1125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1248_Y - connect \B \main_libresocsim_libresoc_interface1_ack - connect \Y $or$ls180.v:6035$1249_Y - end - attribute \src "ls180.v:6035.28-6035.405" - cell $or $or$ls180.v:6035$1250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1249_Y - connect \B \main_libresocsim_libresoc_interface2_ack - connect \Y $or$ls180.v:6035$1250_Y - end - attribute \src "ls180.v:6035.27-6035.449" - cell $or $or$ls180.v:6035$1251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1250_Y - connect \B \main_libresocsim_libresoc_interface3_ack - connect \Y $or$ls180.v:6035$1251_Y - end - attribute \src "ls180.v:6035.26-6035.495" - cell $or $or$ls180.v:6035$1252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1251_Y + connect \A $or$ls180.v:5841$1124_Y connect \B \main_socbushandler_converted_interface_ack - connect \Y $or$ls180.v:6035$1252_Y + connect \Y $or$ls180.v:5841$1125_Y end - attribute \src "ls180.v:6035.25-6035.542" - cell $or $or$ls180.v:6035$1253 + attribute \src "ls180.v:5841.25-5841.263" + cell $or $or$ls180.v:5841$1126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6035$1252_Y + connect \A $or$ls180.v:5841$1125_Y connect \B \builder_libresocsim_converted_interface_ack - connect \Y $or$ls180.v:6035$1253_Y - end - attribute \src "ls180.v:6036.38-6036.166" - cell $or $or$ls180.v:6036$1256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $and$ls180.v:6036$1254_Y - connect \B $and$ls180.v:6036$1255_Y - connect \Y $or$ls180.v:6036$1256_Y + connect \Y $or$ls180.v:5841$1126_Y end - attribute \src "ls180.v:6036.37-6036.232" - cell $or $or$ls180.v:6036$1258 + attribute \src "ls180.v:5842.31-5842.156" + cell $or $or$ls180.v:5842$1129 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1256_Y - connect \B $and$ls180.v:6036$1257_Y - connect \Y $or$ls180.v:6036$1258_Y + connect \A $and$ls180.v:5842$1127_Y + connect \B $and$ls180.v:5842$1128_Y + connect \Y $or$ls180.v:5842$1129_Y end - attribute \src "ls180.v:6036.36-6036.298" - cell $or $or$ls180.v:6036$1260 + attribute \src "ls180.v:5842.30-5842.234" + cell $or $or$ls180.v:5842$1131 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1258_Y - connect \B $and$ls180.v:6036$1259_Y - connect \Y $or$ls180.v:6036$1260_Y + connect \A $or$ls180.v:5842$1129_Y + connect \B $and$ls180.v:5842$1130_Y + connect \Y $or$ls180.v:5842$1131_Y end - attribute \src "ls180.v:6036.35-6036.364" - cell $or $or$ls180.v:6036$1262 + attribute \src "ls180.v:5842.29-5842.312" + cell $or $or$ls180.v:5842$1133 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1260_Y - connect \B $and$ls180.v:6036$1261_Y - connect \Y $or$ls180.v:6036$1262_Y + connect \A $or$ls180.v:5842$1131_Y + connect \B $and$ls180.v:5842$1132_Y + connect \Y $or$ls180.v:5842$1133_Y end - attribute \src "ls180.v:6036.34-6036.442" - cell $or $or$ls180.v:6036$1264 + attribute \src "ls180.v:5842.28-5842.393" + cell $or $or$ls180.v:5842$1135 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1262_Y - connect \B $and$ls180.v:6036$1263_Y - connect \Y $or$ls180.v:6036$1264_Y + connect \A $or$ls180.v:5842$1133_Y + connect \B $and$ls180.v:5842$1134_Y + connect \Y $or$ls180.v:5842$1135_Y end - attribute \src "ls180.v:6036.33-6036.520" - cell $or $or$ls180.v:6036$1266 + attribute \src "ls180.v:5842.27-5842.475" + cell $or $or$ls180.v:5842$1137 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 parameter \B_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1264_Y - connect \B $and$ls180.v:6036$1265_Y - connect \Y $or$ls180.v:6036$1266_Y + connect \A $or$ls180.v:5842$1135_Y + connect \B $and$ls180.v:5842$1136_Y + connect \Y $or$ls180.v:5842$1137_Y end - attribute \src "ls180.v:6036.32-6036.599" - cell $or $or$ls180.v:6036$1268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1266_Y - connect \B $and$ls180.v:6036$1267_Y - connect \Y $or$ls180.v:6036$1268_Y - end - attribute \src "ls180.v:6036.31-6036.678" - cell $or $or$ls180.v:6036$1270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1268_Y - connect \B $and$ls180.v:6036$1269_Y - connect \Y $or$ls180.v:6036$1270_Y - end - attribute \src "ls180.v:6036.30-6036.757" - cell $or $or$ls180.v:6036$1272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1270_Y - connect \B $and$ls180.v:6036$1271_Y - connect \Y $or$ls180.v:6036$1272_Y - end - attribute \src "ls180.v:6036.29-6036.837" - cell $or $or$ls180.v:6036$1274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1272_Y - connect \B $and$ls180.v:6036$1273_Y - connect \Y $or$ls180.v:6036$1274_Y - end - attribute \src "ls180.v:6036.28-6036.919" - cell $or $or$ls180.v:6036$1276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1274_Y - connect \B $and$ls180.v:6036$1275_Y - connect \Y $or$ls180.v:6036$1276_Y - end - attribute \src "ls180.v:6036.27-6036.1002" - cell $or $or$ls180.v:6036$1278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:6036$1276_Y - connect \B $and$ls180.v:6036$1277_Y - connect \Y $or$ls180.v:6036$1278_Y - end - attribute \src "ls180.v:6790.55-6790.124" - cell $or $or$ls180.v:6790$2424 + attribute \src "ls180.v:6596.55-6596.124" + cell $or $or$ls180.v:6596$2283 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -280389,285 +277928,285 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \builder_interface0_bank_bus_dat_r connect \B \builder_interface1_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2424_Y + connect \Y $or$ls180.v:6596$2283_Y end - attribute \src "ls180.v:6790.54-6790.161" - cell $or $or$ls180.v:6790$2425 + attribute \src "ls180.v:6596.54-6596.161" + cell $or $or$ls180.v:6596$2284 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2424_Y + connect \A $or$ls180.v:6596$2283_Y connect \B \builder_interface2_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2425_Y + connect \Y $or$ls180.v:6596$2284_Y end - attribute \src "ls180.v:6790.53-6790.198" - cell $or $or$ls180.v:6790$2426 + attribute \src "ls180.v:6596.53-6596.198" + cell $or $or$ls180.v:6596$2285 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2425_Y + connect \A $or$ls180.v:6596$2284_Y connect \B \builder_interface3_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2426_Y + connect \Y $or$ls180.v:6596$2285_Y end - attribute \src "ls180.v:6790.52-6790.235" - cell $or $or$ls180.v:6790$2427 + attribute \src "ls180.v:6596.52-6596.235" + cell $or $or$ls180.v:6596$2286 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2426_Y + connect \A $or$ls180.v:6596$2285_Y connect \B \builder_interface4_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2427_Y + connect \Y $or$ls180.v:6596$2286_Y end - attribute \src "ls180.v:6790.51-6790.272" - cell $or $or$ls180.v:6790$2428 + attribute \src "ls180.v:6596.51-6596.272" + cell $or $or$ls180.v:6596$2287 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2427_Y + connect \A $or$ls180.v:6596$2286_Y connect \B \builder_interface5_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2428_Y + connect \Y $or$ls180.v:6596$2287_Y end - attribute \src "ls180.v:6790.50-6790.309" - cell $or $or$ls180.v:6790$2429 + attribute \src "ls180.v:6596.50-6596.309" + cell $or $or$ls180.v:6596$2288 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2428_Y + connect \A $or$ls180.v:6596$2287_Y connect \B \builder_interface6_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2429_Y + connect \Y $or$ls180.v:6596$2288_Y end - attribute \src "ls180.v:6790.49-6790.346" - cell $or $or$ls180.v:6790$2430 + attribute \src "ls180.v:6596.49-6596.346" + cell $or $or$ls180.v:6596$2289 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2429_Y + connect \A $or$ls180.v:6596$2288_Y connect \B \builder_interface7_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2430_Y + connect \Y $or$ls180.v:6596$2289_Y end - attribute \src "ls180.v:6790.48-6790.383" - cell $or $or$ls180.v:6790$2431 + attribute \src "ls180.v:6596.48-6596.383" + cell $or $or$ls180.v:6596$2290 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2430_Y + connect \A $or$ls180.v:6596$2289_Y connect \B \builder_interface8_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2431_Y + connect \Y $or$ls180.v:6596$2290_Y end - attribute \src "ls180.v:6790.47-6790.420" - cell $or $or$ls180.v:6790$2432 + attribute \src "ls180.v:6596.47-6596.420" + cell $or $or$ls180.v:6596$2291 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2431_Y + connect \A $or$ls180.v:6596$2290_Y connect \B \builder_interface9_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2432_Y + connect \Y $or$ls180.v:6596$2291_Y end - attribute \src "ls180.v:6790.46-6790.458" - cell $or $or$ls180.v:6790$2433 + attribute \src "ls180.v:6596.46-6596.458" + cell $or $or$ls180.v:6596$2292 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2432_Y + connect \A $or$ls180.v:6596$2291_Y connect \B \builder_interface10_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2433_Y + connect \Y $or$ls180.v:6596$2292_Y end - attribute \src "ls180.v:6790.45-6790.496" - cell $or $or$ls180.v:6790$2434 + attribute \src "ls180.v:6596.45-6596.496" + cell $or $or$ls180.v:6596$2293 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2433_Y + connect \A $or$ls180.v:6596$2292_Y connect \B \builder_interface11_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2434_Y + connect \Y $or$ls180.v:6596$2293_Y end - attribute \src "ls180.v:6790.44-6790.534" - cell $or $or$ls180.v:6790$2435 + attribute \src "ls180.v:6596.44-6596.534" + cell $or $or$ls180.v:6596$2294 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2434_Y + connect \A $or$ls180.v:6596$2293_Y connect \B \builder_interface12_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2435_Y + connect \Y $or$ls180.v:6596$2294_Y end - attribute \src "ls180.v:6790.43-6790.572" - cell $or $or$ls180.v:6790$2436 + attribute \src "ls180.v:6596.43-6596.572" + cell $or $or$ls180.v:6596$2295 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2435_Y + connect \A $or$ls180.v:6596$2294_Y connect \B \builder_interface13_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2436_Y + connect \Y $or$ls180.v:6596$2295_Y end - attribute \src "ls180.v:6790.42-6790.610" - cell $or $or$ls180.v:6790$2437 + attribute \src "ls180.v:6596.42-6596.610" + cell $or $or$ls180.v:6596$2296 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6790$2436_Y + connect \A $or$ls180.v:6596$2295_Y connect \B \builder_interface14_bank_bus_dat_r - connect \Y $or$ls180.v:6790$2437_Y + connect \Y $or$ls180.v:6596$2296_Y end - attribute \src "ls180.v:7117.90-7117.179" - cell $or $or$ls180.v:7117$2462 + attribute \src "ls180.v:6923.90-6923.179" + cell $or $or$ls180.v:6923$2321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked0 - connect \B $and$ls180.v:7117$2461_Y - connect \Y $or$ls180.v:7117$2462_Y + connect \B $and$ls180.v:6923$2320_Y + connect \Y $or$ls180.v:6923$2321_Y end - attribute \src "ls180.v:7117.89-7117.254" - cell $or $or$ls180.v:7117$2465 + attribute \src "ls180.v:6923.89-6923.254" + cell $or $or$ls180.v:6923$2324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7117$2462_Y - connect \B $and$ls180.v:7117$2464_Y - connect \Y $or$ls180.v:7117$2465_Y + connect \A $or$ls180.v:6923$2321_Y + connect \B $and$ls180.v:6923$2323_Y + connect \Y $or$ls180.v:6923$2324_Y end - attribute \src "ls180.v:7117.88-7117.329" - cell $or $or$ls180.v:7117$2468 + attribute \src "ls180.v:6923.88-6923.329" + cell $or $or$ls180.v:6923$2327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7117$2465_Y - connect \B $and$ls180.v:7117$2467_Y - connect \Y $or$ls180.v:7117$2468_Y + connect \A $or$ls180.v:6923$2324_Y + connect \B $and$ls180.v:6923$2326_Y + connect \Y $or$ls180.v:6923$2327_Y end - attribute \src "ls180.v:7141.90-7141.179" - cell $or $or$ls180.v:7141$2478 + attribute \src "ls180.v:6947.90-6947.179" + cell $or $or$ls180.v:6947$2337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked1 - connect \B $and$ls180.v:7141$2477_Y - connect \Y $or$ls180.v:7141$2478_Y + connect \B $and$ls180.v:6947$2336_Y + connect \Y $or$ls180.v:6947$2337_Y end - attribute \src "ls180.v:7141.89-7141.254" - cell $or $or$ls180.v:7141$2481 + attribute \src "ls180.v:6947.89-6947.254" + cell $or $or$ls180.v:6947$2340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7141$2478_Y - connect \B $and$ls180.v:7141$2480_Y - connect \Y $or$ls180.v:7141$2481_Y + connect \A $or$ls180.v:6947$2337_Y + connect \B $and$ls180.v:6947$2339_Y + connect \Y $or$ls180.v:6947$2340_Y end - attribute \src "ls180.v:7141.88-7141.329" - cell $or $or$ls180.v:7141$2484 + attribute \src "ls180.v:6947.88-6947.329" + cell $or $or$ls180.v:6947$2343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7141$2481_Y - connect \B $and$ls180.v:7141$2483_Y - connect \Y $or$ls180.v:7141$2484_Y + connect \A $or$ls180.v:6947$2340_Y + connect \B $and$ls180.v:6947$2342_Y + connect \Y $or$ls180.v:6947$2343_Y end - attribute \src "ls180.v:7165.90-7165.179" - cell $or $or$ls180.v:7165$2494 + attribute \src "ls180.v:6971.90-6971.179" + cell $or $or$ls180.v:6971$2353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked2 - connect \B $and$ls180.v:7165$2493_Y - connect \Y $or$ls180.v:7165$2494_Y + connect \B $and$ls180.v:6971$2352_Y + connect \Y $or$ls180.v:6971$2353_Y end - attribute \src "ls180.v:7165.89-7165.254" - cell $or $or$ls180.v:7165$2497 + attribute \src "ls180.v:6971.89-6971.254" + cell $or $or$ls180.v:6971$2356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7165$2494_Y - connect \B $and$ls180.v:7165$2496_Y - connect \Y $or$ls180.v:7165$2497_Y + connect \A $or$ls180.v:6971$2353_Y + connect \B $and$ls180.v:6971$2355_Y + connect \Y $or$ls180.v:6971$2356_Y end - attribute \src "ls180.v:7165.88-7165.329" - cell $or $or$ls180.v:7165$2500 + attribute \src "ls180.v:6971.88-6971.329" + cell $or $or$ls180.v:6971$2359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7165$2497_Y - connect \B $and$ls180.v:7165$2499_Y - connect \Y $or$ls180.v:7165$2500_Y + connect \A $or$ls180.v:6971$2356_Y + connect \B $and$ls180.v:6971$2358_Y + connect \Y $or$ls180.v:6971$2359_Y end - attribute \src "ls180.v:7189.90-7189.179" - cell $or $or$ls180.v:7189$2510 + attribute \src "ls180.v:6995.90-6995.179" + cell $or $or$ls180.v:6995$2369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \builder_locked3 - connect \B $and$ls180.v:7189$2509_Y - connect \Y $or$ls180.v:7189$2510_Y + connect \B $and$ls180.v:6995$2368_Y + connect \Y $or$ls180.v:6995$2369_Y end - attribute \src "ls180.v:7189.89-7189.254" - cell $or $or$ls180.v:7189$2513 + attribute \src "ls180.v:6995.89-6995.254" + cell $or $or$ls180.v:6995$2372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7189$2510_Y - connect \B $and$ls180.v:7189$2512_Y - connect \Y $or$ls180.v:7189$2513_Y + connect \A $or$ls180.v:6995$2369_Y + connect \B $and$ls180.v:6995$2371_Y + connect \Y $or$ls180.v:6995$2372_Y end - attribute \src "ls180.v:7189.88-7189.329" - cell $or $or$ls180.v:7189$2516 + attribute \src "ls180.v:6995.88-6995.329" + cell $or $or$ls180.v:6995$2375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7189$2513_Y - connect \B $and$ls180.v:7189$2515_Y - connect \Y $or$ls180.v:7189$2516_Y + connect \A $or$ls180.v:6995$2372_Y + connect \B $and$ls180.v:6995$2374_Y + connect \Y $or$ls180.v:6995$2375_Y end - attribute \src "ls180.v:7706.20-7706.71" - cell $or $or$ls180.v:7706$2576 + attribute \src "ls180.v:7512.20-7512.71" + cell $or $or$ls180.v:7512$2435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280675,10 +278214,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [0] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7706$2576_Y + connect \Y $or$ls180.v:7512$2435_Y end - attribute \src "ls180.v:7707.20-7707.71" - cell $or $or$ls180.v:7707$2577 + attribute \src "ls180.v:7513.20-7513.71" + cell $or $or$ls180.v:7513$2436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280686,10 +278225,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [1] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7707$2577_Y + connect \Y $or$ls180.v:7513$2436_Y end - attribute \src "ls180.v:7708.20-7708.71" - cell $or $or$ls180.v:7708$2578 + attribute \src "ls180.v:7514.20-7514.71" + cell $or $or$ls180.v:7514$2437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280697,10 +278236,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [2] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7708$2578_Y + connect \Y $or$ls180.v:7514$2437_Y end - attribute \src "ls180.v:7709.20-7709.71" - cell $or $or$ls180.v:7709$2579 + attribute \src "ls180.v:7515.20-7515.71" + cell $or $or$ls180.v:7515$2438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280708,10 +278247,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [3] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7709$2579_Y + connect \Y $or$ls180.v:7515$2438_Y end - attribute \src "ls180.v:7710.20-7710.71" - cell $or $or$ls180.v:7710$2580 + attribute \src "ls180.v:7516.20-7516.71" + cell $or $or$ls180.v:7516$2439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280719,10 +278258,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [4] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7710$2580_Y + connect \Y $or$ls180.v:7516$2439_Y end - attribute \src "ls180.v:7711.20-7711.71" - cell $or $or$ls180.v:7711$2581 + attribute \src "ls180.v:7517.20-7517.71" + cell $or $or$ls180.v:7517$2440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280730,10 +278269,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [5] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7711$2581_Y + connect \Y $or$ls180.v:7517$2440_Y end - attribute \src "ls180.v:7712.20-7712.71" - cell $or $or$ls180.v:7712$2582 + attribute \src "ls180.v:7518.20-7518.71" + cell $or $or$ls180.v:7518$2441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280741,10 +278280,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [6] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7712$2582_Y + connect \Y $or$ls180.v:7518$2441_Y end - attribute \src "ls180.v:7713.20-7713.71" - cell $or $or$ls180.v:7713$2583 + attribute \src "ls180.v:7519.20-7519.71" + cell $or $or$ls180.v:7519$2442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280752,10 +278291,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [7] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7713$2583_Y + connect \Y $or$ls180.v:7519$2442_Y end - attribute \src "ls180.v:7714.20-7714.71" - cell $or $or$ls180.v:7714$2584 + attribute \src "ls180.v:7520.20-7520.71" + cell $or $or$ls180.v:7520$2443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280763,10 +278302,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [8] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7714$2584_Y + connect \Y $or$ls180.v:7520$2443_Y end - attribute \src "ls180.v:7715.20-7715.71" - cell $or $or$ls180.v:7715$2585 + attribute \src "ls180.v:7521.20-7521.71" + cell $or $or$ls180.v:7521$2444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280774,10 +278313,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [9] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7715$2585_Y + connect \Y $or$ls180.v:7521$2444_Y end - attribute \src "ls180.v:7716.21-7716.73" - cell $or $or$ls180.v:7716$2586 + attribute \src "ls180.v:7522.21-7522.73" + cell $or $or$ls180.v:7522$2445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280785,10 +278324,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [10] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7716$2586_Y + connect \Y $or$ls180.v:7522$2445_Y end - attribute \src "ls180.v:7717.21-7717.73" - cell $or $or$ls180.v:7717$2587 + attribute \src "ls180.v:7523.21-7523.73" + cell $or $or$ls180.v:7523$2446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280796,10 +278335,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [11] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7717$2587_Y + connect \Y $or$ls180.v:7523$2446_Y end - attribute \src "ls180.v:7718.21-7718.73" - cell $or $or$ls180.v:7718$2588 + attribute \src "ls180.v:7524.21-7524.73" + cell $or $or$ls180.v:7524$2447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280807,10 +278346,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [12] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7718$2588_Y + connect \Y $or$ls180.v:7524$2447_Y end - attribute \src "ls180.v:7719.21-7719.73" - cell $or $or$ls180.v:7719$2589 + attribute \src "ls180.v:7525.21-7525.73" + cell $or $or$ls180.v:7525$2448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280818,10 +278357,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [13] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7719$2589_Y + connect \Y $or$ls180.v:7525$2448_Y end - attribute \src "ls180.v:7720.21-7720.73" - cell $or $or$ls180.v:7720$2590 + attribute \src "ls180.v:7526.21-7526.73" + cell $or $or$ls180.v:7526$2449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280829,10 +278368,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [14] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7720$2590_Y + connect \Y $or$ls180.v:7526$2449_Y end - attribute \src "ls180.v:7721.21-7721.73" - cell $or $or$ls180.v:7721$2591 + attribute \src "ls180.v:7527.21-7527.73" + cell $or $or$ls180.v:7527$2450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280840,10 +278379,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [15] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7721$2591_Y + connect \Y $or$ls180.v:7527$2450_Y end - attribute \src "ls180.v:7722.21-7722.73" - cell $or $or$ls180.v:7722$2592 + attribute \src "ls180.v:7528.21-7528.73" + cell $or $or$ls180.v:7528$2451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280851,10 +278390,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [16] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7722$2592_Y + connect \Y $or$ls180.v:7528$2451_Y end - attribute \src "ls180.v:7723.21-7723.73" - cell $or $or$ls180.v:7723$2593 + attribute \src "ls180.v:7529.21-7529.73" + cell $or $or$ls180.v:7529$2452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280862,10 +278401,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [17] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7723$2593_Y + connect \Y $or$ls180.v:7529$2452_Y end - attribute \src "ls180.v:7724.21-7724.73" - cell $or $or$ls180.v:7724$2594 + attribute \src "ls180.v:7530.21-7530.73" + cell $or $or$ls180.v:7530$2453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280873,10 +278412,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [18] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7724$2594_Y + connect \Y $or$ls180.v:7530$2453_Y end - attribute \src "ls180.v:7725.21-7725.73" - cell $or $or$ls180.v:7725$2595 + attribute \src "ls180.v:7531.21-7531.73" + cell $or $or$ls180.v:7531$2454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280884,10 +278423,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [19] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7725$2595_Y + connect \Y $or$ls180.v:7531$2454_Y end - attribute \src "ls180.v:7726.21-7726.73" - cell $or $or$ls180.v:7726$2596 + attribute \src "ls180.v:7532.21-7532.73" + cell $or $or$ls180.v:7532$2455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280895,10 +278434,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [20] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7726$2596_Y + connect \Y $or$ls180.v:7532$2455_Y end - attribute \src "ls180.v:7727.21-7727.73" - cell $or $or$ls180.v:7727$2597 + attribute \src "ls180.v:7533.21-7533.73" + cell $or $or$ls180.v:7533$2456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280906,10 +278445,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [21] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7727$2597_Y + connect \Y $or$ls180.v:7533$2456_Y end - attribute \src "ls180.v:7728.21-7728.73" - cell $or $or$ls180.v:7728$2598 + attribute \src "ls180.v:7534.21-7534.73" + cell $or $or$ls180.v:7534$2457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280917,10 +278456,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [22] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7728$2598_Y + connect \Y $or$ls180.v:7534$2457_Y end - attribute \src "ls180.v:7729.21-7729.73" - cell $or $or$ls180.v:7729$2599 + attribute \src "ls180.v:7535.21-7535.73" + cell $or $or$ls180.v:7535$2458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280928,10 +278467,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_nc [23] connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7729$2599_Y + connect \Y $or$ls180.v:7535$2458_Y end - attribute \src "ls180.v:7730.7-7730.68" - cell $or $or$ls180.v:7730$2600 + attribute \src "ls180.v:7536.7-7536.68" + cell $or $or$ls180.v:7536$2459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280939,10 +278478,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_xics_icp_ack connect \B \main_converter0_skip - connect \Y $or$ls180.v:7730$2600_Y + connect \Y $or$ls180.v:7536$2459_Y end - attribute \src "ls180.v:7741.7-7741.68" - cell $or $or$ls180.v:7741$2601 + attribute \src "ls180.v:7547.7-7547.68" + cell $or $or$ls180.v:7547$2460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280950,10 +278489,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_libresocsim_libresoc_xics_ics_ack connect \B \main_converter1_skip - connect \Y $or$ls180.v:7741$2601_Y + connect \Y $or$ls180.v:7547$2460_Y end - attribute \src "ls180.v:7752.7-7752.50" - cell $or $or$ls180.v:7752$2602 + attribute \src "ls180.v:7558.7-7558.50" + cell $or $or$ls180.v:7558$2461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -280961,142 +278500,142 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_wb_sdram_ack connect \B \main_socbushandler_skip - connect \Y $or$ls180.v:7752$2602_Y + connect \Y $or$ls180.v:7558$2461_Y end - attribute \src "ls180.v:7897.7-7897.107" - cell $or $or$ls180.v:7897$2650 + attribute \src "ls180.v:7691.7-7691.107" + cell $or $or$ls180.v:7691$2500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7897$2649_Y + connect \A $not$ls180.v:7691$2499_Y connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:7897$2650_Y + connect \Y $or$ls180.v:7691$2500_Y end - attribute \src "ls180.v:7943.7-7943.107" - cell $or $or$ls180.v:7943$2666 + attribute \src "ls180.v:7737.7-7737.107" + cell $or $or$ls180.v:7737$2516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7943$2665_Y + connect \A $not$ls180.v:7737$2515_Y connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:7943$2666_Y + connect \Y $or$ls180.v:7737$2516_Y end - attribute \src "ls180.v:7989.7-7989.107" - cell $or $or$ls180.v:7989$2682 + attribute \src "ls180.v:7783.7-7783.107" + cell $or $or$ls180.v:7783$2532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7989$2681_Y + connect \A $not$ls180.v:7783$2531_Y connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:7989$2682_Y + connect \Y $or$ls180.v:7783$2532_Y end - attribute \src "ls180.v:8035.7-8035.107" - cell $or $or$ls180.v:8035$2698 + attribute \src "ls180.v:7829.7-7829.107" + cell $or $or$ls180.v:7829$2548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8035$2697_Y + connect \A $not$ls180.v:7829$2547_Y connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:8035$2698_Y + connect \Y $or$ls180.v:7829$2548_Y end - attribute \src "ls180.v:8223.40-8223.125" - cell $or $or$ls180.v:8223$2719 + attribute \src "ls180.v:8017.40-8017.125" + cell $or $or$ls180.v:8017$2569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:8223$2718_Y - connect \Y $or$ls180.v:8223$2719_Y + connect \B $and$ls180.v:8017$2568_Y + connect \Y $or$ls180.v:8017$2569_Y end - attribute \src "ls180.v:8223.39-8223.207" - cell $or $or$ls180.v:8223$2722 + attribute \src "ls180.v:8017.39-8017.207" + cell $or $or$ls180.v:8017$2572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8223$2719_Y - connect \B $and$ls180.v:8223$2721_Y - connect \Y $or$ls180.v:8223$2722_Y + connect \A $or$ls180.v:8017$2569_Y + connect \B $and$ls180.v:8017$2571_Y + connect \Y $or$ls180.v:8017$2572_Y end - attribute \src "ls180.v:8223.38-8223.289" - cell $or $or$ls180.v:8223$2725 + attribute \src "ls180.v:8017.38-8017.289" + cell $or $or$ls180.v:8017$2575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8223$2722_Y - connect \B $and$ls180.v:8223$2724_Y - connect \Y $or$ls180.v:8223$2725_Y + connect \A $or$ls180.v:8017$2572_Y + connect \B $and$ls180.v:8017$2574_Y + connect \Y $or$ls180.v:8017$2575_Y end - attribute \src "ls180.v:8223.37-8223.371" - cell $or $or$ls180.v:8223$2728 + attribute \src "ls180.v:8017.37-8017.371" + cell $or $or$ls180.v:8017$2578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8223$2725_Y - connect \B $and$ls180.v:8223$2727_Y - connect \Y $or$ls180.v:8223$2728_Y + connect \A $or$ls180.v:8017$2575_Y + connect \B $and$ls180.v:8017$2577_Y + connect \Y $or$ls180.v:8017$2578_Y end - attribute \src "ls180.v:8224.41-8224.126" - cell $or $or$ls180.v:8224$2731 + attribute \src "ls180.v:8018.41-8018.126" + cell $or $or$ls180.v:8018$2581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A 1'0 - connect \B $and$ls180.v:8224$2730_Y - connect \Y $or$ls180.v:8224$2731_Y + connect \B $and$ls180.v:8018$2580_Y + connect \Y $or$ls180.v:8018$2581_Y end - attribute \src "ls180.v:8224.40-8224.208" - cell $or $or$ls180.v:8224$2734 + attribute \src "ls180.v:8018.40-8018.208" + cell $or $or$ls180.v:8018$2584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8224$2731_Y - connect \B $and$ls180.v:8224$2733_Y - connect \Y $or$ls180.v:8224$2734_Y + connect \A $or$ls180.v:8018$2581_Y + connect \B $and$ls180.v:8018$2583_Y + connect \Y $or$ls180.v:8018$2584_Y end - attribute \src "ls180.v:8224.39-8224.290" - cell $or $or$ls180.v:8224$2737 + attribute \src "ls180.v:8018.39-8018.290" + cell $or $or$ls180.v:8018$2587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8224$2734_Y - connect \B $and$ls180.v:8224$2736_Y - connect \Y $or$ls180.v:8224$2737_Y + connect \A $or$ls180.v:8018$2584_Y + connect \B $and$ls180.v:8018$2586_Y + connect \Y $or$ls180.v:8018$2587_Y end - attribute \src "ls180.v:8224.38-8224.372" - cell $or $or$ls180.v:8224$2740 + attribute \src "ls180.v:8018.38-8018.372" + cell $or $or$ls180.v:8018$2590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8224$2737_Y - connect \B $and$ls180.v:8224$2739_Y - connect \Y $or$ls180.v:8224$2740_Y + connect \A $or$ls180.v:8018$2587_Y + connect \B $and$ls180.v:8018$2589_Y + connect \Y $or$ls180.v:8018$2590_Y end - attribute \src "ls180.v:8228.7-8228.49" - cell $or $or$ls180.v:8228$2741 + attribute \src "ls180.v:8022.7-8022.49" + cell $or $or$ls180.v:8022$2591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281104,32 +278643,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_litedram_wb_ack connect \B \main_converter_skip - connect \Y $or$ls180.v:8228$2741_Y + connect \Y $or$ls180.v:8022$2591_Y end - attribute \src "ls180.v:8391.21-8391.74" - cell $or $or$ls180.v:8391$2789 + attribute \src "ls180.v:8185.21-8185.74" + cell $or $or$ls180.v:8185$2639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8391$2787_Y - connect \B $not$ls180.v:8391$2788_Y - connect \Y $or$ls180.v:8391$2789_Y + connect \A $not$ls180.v:8185$2637_Y + connect \B $not$ls180.v:8185$2638_Y + connect \Y $or$ls180.v:8185$2639_Y end - attribute \src "ls180.v:8426.21-8426.71" - cell $or $or$ls180.v:8426$2794 + attribute \src "ls180.v:8220.21-8220.71" + cell $or $or$ls180.v:8220$2644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8426$2792_Y - connect \B $not$ls180.v:8426$2793_Y - connect \Y $or$ls180.v:8426$2794_Y + connect \A $not$ls180.v:8220$2642_Y + connect \B $not$ls180.v:8220$2643_Y + connect \Y $or$ls180.v:8220$2644_Y end - attribute \src "ls180.v:8494.32-8494.85" - cell $or $or$ls180.v:8494$2806 + attribute \src "ls180.v:8288.32-8288.85" + cell $or $or$ls180.v:8288$2656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281137,21 +278676,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_start connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:8494$2806_Y + connect \Y $or$ls180.v:8288$2656_Y end - attribute \src "ls180.v:8500.8-8500.97" - cell $or $or$ls180.v:8500$2808 + attribute \src "ls180.v:8294.8-8294.97" + cell $or $or$ls180.v:8294$2658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8500$2807_Y + connect \A $eq$ls180.v:8294$2657_Y connect \B \main_sdphy_cmdr_cmdr_converter_sink_last - connect \Y $or$ls180.v:8500$2808_Y + connect \Y $or$ls180.v:8294$2658_Y end - attribute \src "ls180.v:8517.52-8517.139" - cell $or $or$ls180.v:8517$2813 + attribute \src "ls180.v:8311.52-8311.139" + cell $or $or$ls180.v:8311$2663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281159,10 +278698,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_first connect \B \main_sdphy_cmdr_cmdr_converter_source_first - connect \Y $or$ls180.v:8517$2813_Y + connect \Y $or$ls180.v:8311$2663_Y end - attribute \src "ls180.v:8518.51-8518.136" - cell $or $or$ls180.v:8518$2814 + attribute \src "ls180.v:8312.51-8312.136" + cell $or $or$ls180.v:8312$2664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281170,21 +278709,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_cmdr_cmdr_converter_sink_last connect \B \main_sdphy_cmdr_cmdr_converter_source_last - connect \Y $or$ls180.v:8518$2814_Y + connect \Y $or$ls180.v:8312$2664_Y end - attribute \src "ls180.v:8552.7-8552.87" - cell $or $or$ls180.v:8552$2817 + attribute \src "ls180.v:8346.7-8346.87" + cell $or $or$ls180.v:8346$2667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8552$2816_Y + connect \A $not$ls180.v:8346$2666_Y connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:8552$2817_Y + connect \Y $or$ls180.v:8346$2667_Y end - attribute \src "ls180.v:8575.33-8575.88" - cell $or $or$ls180.v:8575$2818 + attribute \src "ls180.v:8369.33-8369.88" + cell $or $or$ls180.v:8369$2668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281192,21 +278731,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_start connect \B \main_sdphy_dataw_crcr_run - connect \Y $or$ls180.v:8575$2818_Y + connect \Y $or$ls180.v:8369$2668_Y end - attribute \src "ls180.v:8581.8-8581.99" - cell $or $or$ls180.v:8581$2820 + attribute \src "ls180.v:8375.8-8375.99" + cell $or $or$ls180.v:8375$2670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8581$2819_Y + connect \A $eq$ls180.v:8375$2669_Y connect \B \main_sdphy_dataw_crcr_converter_sink_last - connect \Y $or$ls180.v:8581$2820_Y + connect \Y $or$ls180.v:8375$2670_Y end - attribute \src "ls180.v:8598.53-8598.142" - cell $or $or$ls180.v:8598$2825 + attribute \src "ls180.v:8392.53-8392.142" + cell $or $or$ls180.v:8392$2675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281214,10 +278753,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_first connect \B \main_sdphy_dataw_crcr_converter_source_first - connect \Y $or$ls180.v:8598$2825_Y + connect \Y $or$ls180.v:8392$2675_Y end - attribute \src "ls180.v:8599.52-8599.139" - cell $or $or$ls180.v:8599$2826 + attribute \src "ls180.v:8393.52-8393.139" + cell $or $or$ls180.v:8393$2676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281225,21 +278764,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_dataw_crcr_converter_sink_last connect \B \main_sdphy_dataw_crcr_converter_source_last - connect \Y $or$ls180.v:8599$2826_Y + connect \Y $or$ls180.v:8393$2676_Y end - attribute \src "ls180.v:8633.7-8633.89" - cell $or $or$ls180.v:8633$2829 + attribute \src "ls180.v:8427.7-8427.89" + cell $or $or$ls180.v:8427$2679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8633$2828_Y + connect \A $not$ls180.v:8427$2678_Y connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:8633$2829_Y + connect \Y $or$ls180.v:8427$2679_Y end - attribute \src "ls180.v:8654.34-8654.91" - cell $or $or$ls180.v:8654$2830 + attribute \src "ls180.v:8448.34-8448.91" + cell $or $or$ls180.v:8448$2680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281247,21 +278786,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_start connect \B \main_sdphy_datar_datar_run - connect \Y $or$ls180.v:8654$2830_Y + connect \Y $or$ls180.v:8448$2680_Y end - attribute \src "ls180.v:8660.8-8660.101" - cell $or $or$ls180.v:8660$2832 + attribute \src "ls180.v:8454.8-8454.101" + cell $or $or$ls180.v:8454$2682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8660$2831_Y + connect \A $eq$ls180.v:8454$2681_Y connect \B \main_sdphy_datar_datar_converter_sink_last - connect \Y $or$ls180.v:8660$2832_Y + connect \Y $or$ls180.v:8454$2682_Y end - attribute \src "ls180.v:8677.54-8677.145" - cell $or $or$ls180.v:8677$2837 + attribute \src "ls180.v:8471.54-8471.145" + cell $or $or$ls180.v:8471$2687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281269,10 +278808,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_first connect \B \main_sdphy_datar_datar_converter_source_first - connect \Y $or$ls180.v:8677$2837_Y + connect \Y $or$ls180.v:8471$2687_Y end - attribute \src "ls180.v:8678.53-8678.142" - cell $or $or$ls180.v:8678$2838 + attribute \src "ls180.v:8472.53-8472.142" + cell $or $or$ls180.v:8472$2688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281280,32 +278819,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdphy_datar_datar_converter_sink_last connect \B \main_sdphy_datar_datar_converter_source_last - connect \Y $or$ls180.v:8678$2838_Y + connect \Y $or$ls180.v:8472$2688_Y end - attribute \src "ls180.v:8694.7-8694.91" - cell $or $or$ls180.v:8694$2841 + attribute \src "ls180.v:8488.7-8488.91" + cell $or $or$ls180.v:8488$2691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8694$2840_Y + connect \A $not$ls180.v:8488$2690_Y connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:8694$2841_Y + connect \Y $or$ls180.v:8488$2691_Y end - attribute \src "ls180.v:8883.8-8883.89" - cell $or $or$ls180.v:8883$2865 + attribute \src "ls180.v:8677.8-8677.89" + cell $or $or$ls180.v:8677$2715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8883$2864_Y + connect \A $eq$ls180.v:8677$2714_Y connect \B \main_sdblock2mem_converter_sink_last - connect \Y $or$ls180.v:8883$2865_Y + connect \Y $or$ls180.v:8677$2715_Y end - attribute \src "ls180.v:8900.48-8900.127" - cell $or $or$ls180.v:8900$2870 + attribute \src "ls180.v:8694.48-8694.127" + cell $or $or$ls180.v:8694$2720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281313,10 +278852,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_first connect \B \main_sdblock2mem_converter_source_first - connect \Y $or$ls180.v:8900$2870_Y + connect \Y $or$ls180.v:8694$2720_Y end - attribute \src "ls180.v:8901.47-8901.124" - cell $or $or$ls180.v:8901$2871 + attribute \src "ls180.v:8695.47-8695.124" + cell $or $or$ls180.v:8695$2721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281324,10 +278863,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdblock2mem_converter_sink_last connect \B \main_sdblock2mem_converter_source_last - connect \Y $or$ls180.v:8901$2871_Y + connect \Y $or$ls180.v:8695$2721_Y end - attribute \src "ls180.v:3358.46-3358.94" - cell $sshl $sshl$ls180.v:3358$231 + attribute \src "ls180.v:3227.46-3227.94" + cell $sshl $sshl$ls180.v:3227$132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281335,10 +278874,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine0_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3358$231_Y + connect \Y $sshl$ls180.v:3227$132_Y end - attribute \src "ls180.v:3515.46-3515.94" - cell $sshl $sshl$ls180.v:3515$261 + attribute \src "ls180.v:3384.46-3384.94" + cell $sshl $sshl$ls180.v:3384$162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281346,10 +278885,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine1_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3515$261_Y + connect \Y $sshl$ls180.v:3384$162_Y end - attribute \src "ls180.v:3672.46-3672.94" - cell $sshl $sshl$ls180.v:3672$291 + attribute \src "ls180.v:3541.46-3541.94" + cell $sshl $sshl$ls180.v:3541$192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281357,10 +278896,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine2_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3672$291_Y + connect \Y $sshl$ls180.v:3541$192_Y end - attribute \src "ls180.v:3829.46-3829.94" - cell $sshl $sshl$ls180.v:3829$321 + attribute \src "ls180.v:3698.46-3698.94" + cell $sshl $sshl$ls180.v:3698$222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281368,10 +278907,10 @@ module \ls180 parameter \Y_WIDTH 13 connect \A \main_sdram_bankmachine3_auto_precharge connect \B 4'1010 - connect \Y $sshl$ls180.v:3829$321_Y + connect \Y $sshl$ls180.v:3698$222_Y end - attribute \src "ls180.v:3389.63-3389.122" - cell $sub $sub$ls180.v:3389$244 + attribute \src "ls180.v:3258.63-3258.122" + cell $sub $sub$ls180.v:3258$145 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281379,10 +278918,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3389$244_Y + connect \Y $sub$ls180.v:3258$145_Y end - attribute \src "ls180.v:3546.63-3546.122" - cell $sub $sub$ls180.v:3546$274 + attribute \src "ls180.v:3415.63-3415.122" + cell $sub $sub$ls180.v:3415$175 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281390,10 +278929,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3546$274_Y + connect \Y $sub$ls180.v:3415$175_Y end - attribute \src "ls180.v:3703.63-3703.122" - cell $sub $sub$ls180.v:3703$304 + attribute \src "ls180.v:3572.63-3572.122" + cell $sub $sub$ls180.v:3572$205 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281401,10 +278940,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3703$304_Y + connect \Y $sub$ls180.v:3572$205_Y end - attribute \src "ls180.v:3860.63-3860.122" - cell $sub $sub$ls180.v:3860$334 + attribute \src "ls180.v:3729.63-3729.122" + cell $sub $sub$ls180.v:3729$235 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281412,10 +278951,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $sub$ls180.v:3860$334_Y + connect \Y $sub$ls180.v:3729$235_Y end - attribute \src "ls180.v:4266.38-4266.75" - cell $sub $sub$ls180.v:4266$688 + attribute \src "ls180.v:4135.38-4135.75" + cell $sub $sub$ls180.v:4135$589 parameter \A_SIGNED 0 parameter \A_WIDTH 30 parameter \B_SIGNED 0 @@ -281423,10 +278962,10 @@ module \ls180 parameter \Y_WIDTH 31 connect \A \main_litedram_wb_adr connect \B 31'1001000000000000000000000000000 - connect \Y $sub$ls180.v:4266$688_Y + connect \Y $sub$ls180.v:4135$589_Y end - attribute \src "ls180.v:4352.36-4352.68" - cell $sub $sub$ls180.v:4352$733 + attribute \src "ls180.v:4221.36-4221.68" + cell $sub $sub$ls180.v:4221$634 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -281434,10 +278973,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_tx_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:4352$733_Y + connect \Y $sub$ls180.v:4221$634_Y end - attribute \src "ls180.v:4382.36-4382.68" - cell $sub $sub$ls180.v:4382$744 + attribute \src "ls180.v:4251.36-4251.68" + cell $sub $sub$ls180.v:4251$645 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -281445,10 +278984,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_uart_rx_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:4382$744_Y + connect \Y $sub$ls180.v:4251$645_Y end - attribute \src "ls180.v:4418.70-4418.110" - cell $sub $sub$ls180.v:4418$752 + attribute \src "ls180.v:4287.70-4287.110" + cell $sub $sub$ls180.v:4287$653 parameter \A_SIGNED 0 parameter \A_WIDTH 15 parameter \B_SIGNED 0 @@ -281456,10 +278995,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spimaster8_clk_divider [15:1] connect \B 1'1 - connect \Y $sub$ls180.v:4418$752_Y + connect \Y $sub$ls180.v:4287$653_Y end - attribute \src "ls180.v:4419.70-4419.104" - cell $sub $sub$ls180.v:4419$754 + attribute \src "ls180.v:4288.70-4288.104" + cell $sub $sub$ls180.v:4288$655 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -281467,10 +279006,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spimaster8_clk_divider connect \B 1'1 - connect \Y $sub$ls180.v:4419$754_Y + connect \Y $sub$ls180.v:4288$655_Y end - attribute \src "ls180.v:4446.37-4446.66" - cell $sub $sub$ls180.v:4446$758 + attribute \src "ls180.v:4315.37-4315.66" + cell $sub $sub$ls180.v:4315$659 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -281478,10 +279017,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_spimaster1_length connect \B 1'1 - connect \Y $sub$ls180.v:4446$758_Y + connect \Y $sub$ls180.v:4315$659_Y end - attribute \src "ls180.v:4476.67-4476.107" - cell $sub $sub$ls180.v:4476$760 + attribute \src "ls180.v:4345.67-4345.107" + cell $sub $sub$ls180.v:4345$661 parameter \A_SIGNED 0 parameter \A_WIDTH 15 parameter \B_SIGNED 0 @@ -281489,10 +279028,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spisdcard_clk_divider0 [15:1] connect \B 1'1 - connect \Y $sub$ls180.v:4476$760_Y + connect \Y $sub$ls180.v:4345$661_Y end - attribute \src "ls180.v:4477.67-4477.101" - cell $sub $sub$ls180.v:4477$762 + attribute \src "ls180.v:4346.67-4346.101" + cell $sub $sub$ls180.v:4346$663 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -281500,10 +279039,10 @@ module \ls180 parameter \Y_WIDTH 16 connect \A \main_spisdcard_clk_divider0 connect \B 1'1 - connect \Y $sub$ls180.v:4477$762_Y + connect \Y $sub$ls180.v:4346$663_Y end - attribute \src "ls180.v:4505.35-4505.64" - cell $sub $sub$ls180.v:4505$766 + attribute \src "ls180.v:4374.35-4374.64" + cell $sub $sub$ls180.v:4374$667 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -281511,10 +279050,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_spisdcard_length0 connect \B 1'1 - connect \Y $sub$ls180.v:4505$766_Y + connect \Y $sub$ls180.v:4374$667_Y end - attribute \src "ls180.v:4759.60-4759.90" - cell $sub $sub$ls180.v:4759$810 + attribute \src "ls180.v:4628.60-4628.90" + cell $sub $sub$ls180.v:4628$711 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281522,10 +279061,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_cmdr_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4759$810_Y + connect \Y $sub$ls180.v:4628$711_Y end - attribute \src "ls180.v:4770.62-4770.104" - cell $sub $sub$ls180.v:4770$812 + attribute \src "ls180.v:4639.62-4639.104" + cell $sub $sub$ls180.v:4639$713 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -281533,10 +279072,10 @@ module \ls180 parameter \Y_WIDTH 8 connect \A \main_sdphy_cmdr_sink_payload_length connect \B 1'1 - connect \Y $sub$ls180.v:4770$812_Y + connect \Y $sub$ls180.v:4639$713_Y end - attribute \src "ls180.v:4787.60-4787.90" - cell $sub $sub$ls180.v:4787$816 + attribute \src "ls180.v:4656.60-4656.90" + cell $sub $sub$ls180.v:4656$717 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281544,10 +279083,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_cmdr_timeout connect \B 1'1 - connect \Y $sub$ls180.v:4787$816_Y + connect \Y $sub$ls180.v:4656$717_Y end - attribute \src "ls180.v:5016.62-5016.93" - cell $sub $sub$ls180.v:5016$846 + attribute \src "ls180.v:4885.62-4885.93" + cell $sub $sub$ls180.v:4885$747 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281555,10 +279094,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:5016$846_Y + connect \Y $sub$ls180.v:4885$747_Y end - attribute \src "ls180.v:5021.62-5021.93" - cell $sub $sub$ls180.v:5021$847 + attribute \src "ls180.v:4890.62-4890.93" + cell $sub $sub$ls180.v:4890$748 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281566,21 +279105,21 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:5021$847_Y + connect \Y $sub$ls180.v:4890$748_Y end - attribute \src "ls180.v:5032.64-5032.122" - cell $sub $sub$ls180.v:5032$850 + attribute \src "ls180.v:4901.64-4901.122" + cell $sub $sub$ls180.v:4901$751 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 10 - connect \A $add$ls180.v:5032$849_Y + connect \A $add$ls180.v:4901$750_Y connect \B 1'1 - connect \Y $sub$ls180.v:5032$850_Y + connect \Y $sub$ls180.v:4901$751_Y end - attribute \src "ls180.v:5053.62-5053.93" - cell $sub $sub$ls180.v:5053$853 + attribute \src "ls180.v:4922.62-4922.93" + cell $sub $sub$ls180.v:4922$754 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281588,10 +279127,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdphy_datar_timeout connect \B 1'1 - connect \Y $sub$ls180.v:5053$853_Y + connect \Y $sub$ls180.v:4922$754_Y end - attribute \src "ls180.v:5515.37-5515.75" - cell $sub $sub$ls180.v:5515$1126 + attribute \src "ls180.v:5384.37-5384.75" + cell $sub $sub$ls180.v:5384$1027 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281599,10 +279138,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5515$1126_Y + connect \Y $sub$ls180.v:5384$1027_Y end - attribute \src "ls180.v:5530.62-5530.100" - cell $sub $sub$ls180.v:5530$1129 + attribute \src "ls180.v:5399.62-5399.100" + cell $sub $sub$ls180.v:5399$1030 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281610,10 +279149,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5530$1129_Y + connect \Y $sub$ls180.v:5399$1030_Y end - attribute \src "ls180.v:5541.39-5541.77" - cell $sub $sub$ls180.v:5541$1134 + attribute \src "ls180.v:5410.39-5410.77" + cell $sub $sub$ls180.v:5410$1035 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281621,10 +279160,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdcore_block_count_storage connect \B 1'1 - connect \Y $sub$ls180.v:5541$1134_Y + connect \Y $sub$ls180.v:5410$1035_Y end - attribute \src "ls180.v:5616.40-5616.76" - cell $sub $sub$ls180.v:5616$1138 + attribute \src "ls180.v:5485.40-5485.76" + cell $sub $sub$ls180.v:5485$1039 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -281632,10 +279171,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdblock2mem_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:5616$1138_Y + connect \Y $sub$ls180.v:5485$1039_Y end - attribute \src "ls180.v:5665.56-5665.104" - cell $sub $sub$ls180.v:5665$1152 + attribute \src "ls180.v:5534.56-5534.104" + cell $sub $sub$ls180.v:5534$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281643,10 +279182,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdblock2mem_wishbonedmawriter_length connect \B 1'1 - connect \Y $sub$ls180.v:5665$1152_Y + connect \Y $sub$ls180.v:5534$1053_Y end - attribute \src "ls180.v:5755.71-5755.105" - cell $sub $sub$ls180.v:5755$1158 + attribute \src "ls180.v:5624.71-5624.105" + cell $sub $sub$ls180.v:5624$1059 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281654,10 +279193,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_sdmem2block_dma_length connect \B 1'1 - connect \Y $sub$ls180.v:5755$1158_Y + connect \Y $sub$ls180.v:5624$1059_Y end - attribute \src "ls180.v:5836.40-5836.76" - cell $sub $sub$ls180.v:5836$1169 + attribute \src "ls180.v:5705.40-5705.76" + cell $sub $sub$ls180.v:5705$1070 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -281665,10 +279204,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdmem2block_fifo_produce connect \B 1'1 - connect \Y $sub$ls180.v:5836$1169_Y + connect \Y $sub$ls180.v:5705$1070_Y end - attribute \src "ls180.v:7776.31-7776.60" - cell $sub $sub$ls180.v:7776$2609 + attribute \src "ls180.v:7582.31-7582.60" + cell $sub $sub$ls180.v:7582$2468 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281676,10 +279215,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_libresocsim_value connect \B 1'1 - connect \Y $sub$ls180.v:7776$2609_Y + connect \Y $sub$ls180.v:7582$2468_Y end - attribute \src "ls180.v:7813.31-7813.61" - cell $sub $sub$ls180.v:7813$2626 + attribute \src "ls180.v:7607.31-7607.61" + cell $sub $sub$ls180.v:7607$2476 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -281687,10 +279226,10 @@ module \ls180 parameter \Y_WIDTH 10 connect \A \main_sdram_timer_count1 connect \B 1'1 - connect \Y $sub$ls180.v:7813$2626_Y + connect \Y $sub$ls180.v:7607$2476_Y end - attribute \src "ls180.v:7819.34-7819.67" - cell $sub $sub$ls180.v:7819$2627 + attribute \src "ls180.v:7613.34-7613.67" + cell $sub $sub$ls180.v:7613$2477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281698,10 +279237,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_postponer_count connect \B 1'1 - connect \Y $sub$ls180.v:7819$2627_Y + connect \Y $sub$ls180.v:7613$2477_Y end - attribute \src "ls180.v:7830.36-7830.69" - cell $sub $sub$ls180.v:7830$2630 + attribute \src "ls180.v:7624.36-7624.69" + cell $sub $sub$ls180.v:7624$2480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281709,10 +279248,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_sequencer_count connect \B 1'1 - connect \Y $sub$ls180.v:7830$2630_Y + connect \Y $sub$ls180.v:7624$2480_Y end - attribute \src "ls180.v:7894.59-7894.116" - cell $sub $sub$ls180.v:7894$2648 + attribute \src "ls180.v:7688.59-7688.116" + cell $sub $sub$ls180.v:7688$2498 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -281720,10 +279259,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7894$2648_Y + connect \Y $sub$ls180.v:7688$2498_Y end - attribute \src "ls180.v:7913.46-7913.90" - cell $sub $sub$ls180.v:7913$2652 + attribute \src "ls180.v:7707.46-7707.90" + cell $sub $sub$ls180.v:7707$2502 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281731,10 +279270,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine0_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7913$2652_Y + connect \Y $sub$ls180.v:7707$2502_Y end - attribute \src "ls180.v:7940.59-7940.116" - cell $sub $sub$ls180.v:7940$2664 + attribute \src "ls180.v:7734.59-7734.116" + cell $sub $sub$ls180.v:7734$2514 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -281742,10 +279281,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7940$2664_Y + connect \Y $sub$ls180.v:7734$2514_Y end - attribute \src "ls180.v:7959.46-7959.90" - cell $sub $sub$ls180.v:7959$2668 + attribute \src "ls180.v:7753.46-7753.90" + cell $sub $sub$ls180.v:7753$2518 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281753,10 +279292,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:7959$2668_Y + connect \Y $sub$ls180.v:7753$2518_Y end - attribute \src "ls180.v:7986.59-7986.116" - cell $sub $sub$ls180.v:7986$2680 + attribute \src "ls180.v:7780.59-7780.116" + cell $sub $sub$ls180.v:7780$2530 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -281764,10 +279303,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:7986$2680_Y + connect \Y $sub$ls180.v:7780$2530_Y end - attribute \src "ls180.v:8005.46-8005.90" - cell $sub $sub$ls180.v:8005$2684 + attribute \src "ls180.v:7799.46-7799.90" + cell $sub $sub$ls180.v:7799$2534 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281775,10 +279314,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine2_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8005$2684_Y + connect \Y $sub$ls180.v:7799$2534_Y end - attribute \src "ls180.v:8032.59-8032.116" - cell $sub $sub$ls180.v:8032$2696 + attribute \src "ls180.v:7826.59-7826.116" + cell $sub $sub$ls180.v:7826$2546 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -281786,10 +279325,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $sub$ls180.v:8032$2696_Y + connect \Y $sub$ls180.v:7826$2546_Y end - attribute \src "ls180.v:8051.46-8051.90" - cell $sub $sub$ls180.v:8051$2700 + attribute \src "ls180.v:7845.46-7845.90" + cell $sub $sub$ls180.v:7845$2550 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281797,10 +279336,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_bankmachine3_twtpcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8051$2700_Y + connect \Y $sub$ls180.v:7845$2550_Y end - attribute \src "ls180.v:8062.25-8062.48" - cell $sub $sub$ls180.v:8062$2704 + attribute \src "ls180.v:7856.25-7856.48" + cell $sub $sub$ls180.v:7856$2554 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -281808,10 +279347,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_sdram_time0 connect \B 1'1 - connect \Y $sub$ls180.v:8062$2704_Y + connect \Y $sub$ls180.v:7856$2554_Y end - attribute \src "ls180.v:8069.25-8069.48" - cell $sub $sub$ls180.v:8069$2707 + attribute \src "ls180.v:7863.25-7863.48" + cell $sub $sub$ls180.v:7863$2557 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -281819,10 +279358,10 @@ module \ls180 parameter \Y_WIDTH 4 connect \A \main_sdram_time1 connect \B 1'1 - connect \Y $sub$ls180.v:8069$2707_Y + connect \Y $sub$ls180.v:7863$2557_Y end - attribute \src "ls180.v:8201.33-8201.64" - cell $sub $sub$ls180.v:8201$2712 + attribute \src "ls180.v:7995.33-7995.64" + cell $sub $sub$ls180.v:7995$2562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281830,10 +279369,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdram_tccdcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8201$2712_Y + connect \Y $sub$ls180.v:7995$2562_Y end - attribute \src "ls180.v:8216.33-8216.64" - cell $sub $sub$ls180.v:8216$2715 + attribute \src "ls180.v:8010.33-8010.64" + cell $sub $sub$ls180.v:8010$2565 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281841,10 +279380,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_sdram_twtrcon_count connect \B 1'1 - connect \Y $sub$ls180.v:8216$2715_Y + connect \Y $sub$ls180.v:8010$2565_Y end - attribute \src "ls180.v:8343.33-8343.64" - cell $sub $sub$ls180.v:8343$2774 + attribute \src "ls180.v:8137.33-8137.64" + cell $sub $sub$ls180.v:8137$2624 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -281852,10 +279391,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_tx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:8343$2774_Y + connect \Y $sub$ls180.v:8137$2624_Y end - attribute \src "ls180.v:8365.33-8365.64" - cell $sub $sub$ls180.v:8365$2785 + attribute \src "ls180.v:8159.33-8159.64" + cell $sub $sub$ls180.v:8159$2635 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -281863,10 +279402,10 @@ module \ls180 parameter \Y_WIDTH 5 connect \A \main_uart_rx_fifo_level0 connect \B 1'1 - connect \Y $sub$ls180.v:8365$2785_Y + connect \Y $sub$ls180.v:8159$2635_Y end - attribute \src "ls180.v:8400.34-8400.66" - cell $sub $sub$ls180.v:8400$2790 + attribute \src "ls180.v:8194.34-8194.66" + cell $sub $sub$ls180.v:8194$2640 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281874,10 +279413,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spimaster34_mosi_sel connect \B 1'1 - connect \Y $sub$ls180.v:8400$2790_Y + connect \Y $sub$ls180.v:8194$2640_Y end - attribute \src "ls180.v:8435.32-8435.62" - cell $sub $sub$ls180.v:8435$2795 + attribute \src "ls180.v:8229.32-8229.62" + cell $sub $sub$ls180.v:8229$2645 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -281885,10 +279424,10 @@ module \ls180 parameter \Y_WIDTH 3 connect \A \main_spisdcard_mosi_sel connect \B 1'1 - connect \Y $sub$ls180.v:8435$2795_Y + connect \Y $sub$ls180.v:8229$2645_Y end - attribute \src "ls180.v:8459.30-8459.53" - cell $sub $sub$ls180.v:8459$2798 + attribute \src "ls180.v:8253.30-8253.53" + cell $sub $sub$ls180.v:8253$2648 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281896,10 +279435,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm0_period connect \B 1'1 - connect \Y $sub$ls180.v:8459$2798_Y + connect \Y $sub$ls180.v:8253$2648_Y end - attribute \src "ls180.v:8473.30-8473.53" - cell $sub $sub$ls180.v:8473$2802 + attribute \src "ls180.v:8267.30-8267.53" + cell $sub $sub$ls180.v:8267$2652 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -281907,10 +279446,10 @@ module \ls180 parameter \Y_WIDTH 32 connect \A \main_pwm1_period connect \B 1'1 - connect \Y $sub$ls180.v:8473$2802_Y + connect \Y $sub$ls180.v:8267$2652_Y end - attribute \src "ls180.v:8876.36-8876.70" - cell $sub $sub$ls180.v:8876$2863 + attribute \src "ls180.v:8670.36-8670.70" + cell $sub $sub$ls180.v:8670$2713 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -281918,10 +279457,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdblock2mem_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8876$2863_Y + connect \Y $sub$ls180.v:8670$2713_Y end - attribute \src "ls180.v:8974.36-8974.70" - cell $sub $sub$ls180.v:8974$2885 + attribute \src "ls180.v:8768.36-8768.70" + cell $sub $sub$ls180.v:8768$2735 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -281929,10 +279468,10 @@ module \ls180 parameter \Y_WIDTH 6 connect \A \main_sdmem2block_fifo_level connect \B 1'1 - connect \Y $sub$ls180.v:8974$2885_Y + connect \Y $sub$ls180.v:8768$2735_Y end - attribute \src "ls180.v:9087.22-9087.42" - cell $sub $sub$ls180.v:9087$2892 + attribute \src "ls180.v:8881.22-8881.42" + cell $sub $sub$ls180.v:8881$2742 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -281940,10 +279479,10 @@ module \ls180 parameter \Y_WIDTH 20 connect \A \builder_count connect \B 1'1 - connect \Y $sub$ls180.v:9087$2892_Y + connect \Y $sub$ls180.v:8881$2742_Y end - attribute \src "ls180.v:5113.353-5113.425" - cell $xor $xor$ls180.v:5113$860 + attribute \src "ls180.v:4982.353-4982.425" + cell $xor $xor$ls180.v:4982$761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281951,10 +279490,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [39] connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:5113$860_Y + connect \Y $xor$ls180.v:4982$761_Y end - attribute \src "ls180.v:5113.200-5113.272" - cell $xor $xor$ls180.v:5113$861 + attribute \src "ls180.v:4982.200-4982.272" + cell $xor $xor$ls180.v:4982$762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281962,21 +279501,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [39] connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:5113$861_Y + connect \Y $xor$ls180.v:4982$762_Y end - attribute \src "ls180.v:5113.160-5113.273" - cell $xor $xor$ls180.v:5113$862 + attribute \src "ls180.v:4982.160-4982.273" + cell $xor $xor$ls180.v:4982$763 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg0 [2] - connect \B $xor$ls180.v:5113$861_Y - connect \Y $xor$ls180.v:5113$862_Y + connect \B $xor$ls180.v:4982$762_Y + connect \Y $xor$ls180.v:4982$763_Y end - attribute \src "ls180.v:5114.353-5114.425" - cell $xor $xor$ls180.v:5114$863 + attribute \src "ls180.v:4983.353-4983.425" + cell $xor $xor$ls180.v:4983$764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281984,10 +279523,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [38] connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:5114$863_Y + connect \Y $xor$ls180.v:4983$764_Y end - attribute \src "ls180.v:5114.200-5114.272" - cell $xor $xor$ls180.v:5114$864 + attribute \src "ls180.v:4983.200-4983.272" + cell $xor $xor$ls180.v:4983$765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -281995,21 +279534,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [38] connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:5114$864_Y + connect \Y $xor$ls180.v:4983$765_Y end - attribute \src "ls180.v:5114.160-5114.273" - cell $xor $xor$ls180.v:5114$865 + attribute \src "ls180.v:4983.160-4983.273" + cell $xor $xor$ls180.v:4983$766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg1 [2] - connect \B $xor$ls180.v:5114$864_Y - connect \Y $xor$ls180.v:5114$865_Y + connect \B $xor$ls180.v:4983$765_Y + connect \Y $xor$ls180.v:4983$766_Y end - attribute \src "ls180.v:5115.353-5115.425" - cell $xor $xor$ls180.v:5115$866 + attribute \src "ls180.v:4984.353-4984.425" + cell $xor $xor$ls180.v:4984$767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282017,10 +279556,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [37] connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:5115$866_Y + connect \Y $xor$ls180.v:4984$767_Y end - attribute \src "ls180.v:5115.200-5115.272" - cell $xor $xor$ls180.v:5115$867 + attribute \src "ls180.v:4984.200-4984.272" + cell $xor $xor$ls180.v:4984$768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282028,21 +279567,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [37] connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:5115$867_Y + connect \Y $xor$ls180.v:4984$768_Y end - attribute \src "ls180.v:5115.160-5115.273" - cell $xor $xor$ls180.v:5115$868 + attribute \src "ls180.v:4984.160-4984.273" + cell $xor $xor$ls180.v:4984$769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg2 [2] - connect \B $xor$ls180.v:5115$867_Y - connect \Y $xor$ls180.v:5115$868_Y + connect \B $xor$ls180.v:4984$768_Y + connect \Y $xor$ls180.v:4984$769_Y end - attribute \src "ls180.v:5116.353-5116.425" - cell $xor $xor$ls180.v:5116$869 + attribute \src "ls180.v:4985.353-4985.425" + cell $xor $xor$ls180.v:4985$770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282050,10 +279589,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [36] connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:5116$869_Y + connect \Y $xor$ls180.v:4985$770_Y end - attribute \src "ls180.v:5116.200-5116.272" - cell $xor $xor$ls180.v:5116$870 + attribute \src "ls180.v:4985.200-4985.272" + cell $xor $xor$ls180.v:4985$771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282061,21 +279600,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [36] connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:5116$870_Y + connect \Y $xor$ls180.v:4985$771_Y end - attribute \src "ls180.v:5116.160-5116.273" - cell $xor $xor$ls180.v:5116$871 + attribute \src "ls180.v:4985.160-4985.273" + cell $xor $xor$ls180.v:4985$772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg3 [2] - connect \B $xor$ls180.v:5116$870_Y - connect \Y $xor$ls180.v:5116$871_Y + connect \B $xor$ls180.v:4985$771_Y + connect \Y $xor$ls180.v:4985$772_Y end - attribute \src "ls180.v:5117.353-5117.425" - cell $xor $xor$ls180.v:5117$872 + attribute \src "ls180.v:4986.353-4986.425" + cell $xor $xor$ls180.v:4986$773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282083,10 +279622,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [35] connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:5117$872_Y + connect \Y $xor$ls180.v:4986$773_Y end - attribute \src "ls180.v:5117.200-5117.272" - cell $xor $xor$ls180.v:5117$873 + attribute \src "ls180.v:4986.200-4986.272" + cell $xor $xor$ls180.v:4986$774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282094,21 +279633,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [35] connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:5117$873_Y + connect \Y $xor$ls180.v:4986$774_Y end - attribute \src "ls180.v:5117.160-5117.273" - cell $xor $xor$ls180.v:5117$874 + attribute \src "ls180.v:4986.160-4986.273" + cell $xor $xor$ls180.v:4986$775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg4 [2] - connect \B $xor$ls180.v:5117$873_Y - connect \Y $xor$ls180.v:5117$874_Y + connect \B $xor$ls180.v:4986$774_Y + connect \Y $xor$ls180.v:4986$775_Y end - attribute \src "ls180.v:5118.353-5118.425" - cell $xor $xor$ls180.v:5118$875 + attribute \src "ls180.v:4987.353-4987.425" + cell $xor $xor$ls180.v:4987$776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282116,10 +279655,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [34] connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:5118$875_Y + connect \Y $xor$ls180.v:4987$776_Y end - attribute \src "ls180.v:5118.200-5118.272" - cell $xor $xor$ls180.v:5118$876 + attribute \src "ls180.v:4987.200-4987.272" + cell $xor $xor$ls180.v:4987$777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282127,21 +279666,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [34] connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:5118$876_Y + connect \Y $xor$ls180.v:4987$777_Y end - attribute \src "ls180.v:5118.160-5118.273" - cell $xor $xor$ls180.v:5118$877 + attribute \src "ls180.v:4987.160-4987.273" + cell $xor $xor$ls180.v:4987$778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg5 [2] - connect \B $xor$ls180.v:5118$876_Y - connect \Y $xor$ls180.v:5118$877_Y + connect \B $xor$ls180.v:4987$777_Y + connect \Y $xor$ls180.v:4987$778_Y end - attribute \src "ls180.v:5119.353-5119.425" - cell $xor $xor$ls180.v:5119$878 + attribute \src "ls180.v:4988.353-4988.425" + cell $xor $xor$ls180.v:4988$779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282149,10 +279688,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [33] connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:5119$878_Y + connect \Y $xor$ls180.v:4988$779_Y end - attribute \src "ls180.v:5119.200-5119.272" - cell $xor $xor$ls180.v:5119$879 + attribute \src "ls180.v:4988.200-4988.272" + cell $xor $xor$ls180.v:4988$780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282160,21 +279699,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [33] connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:5119$879_Y + connect \Y $xor$ls180.v:4988$780_Y end - attribute \src "ls180.v:5119.160-5119.273" - cell $xor $xor$ls180.v:5119$880 + attribute \src "ls180.v:4988.160-4988.273" + cell $xor $xor$ls180.v:4988$781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg6 [2] - connect \B $xor$ls180.v:5119$879_Y - connect \Y $xor$ls180.v:5119$880_Y + connect \B $xor$ls180.v:4988$780_Y + connect \Y $xor$ls180.v:4988$781_Y end - attribute \src "ls180.v:5120.353-5120.425" - cell $xor $xor$ls180.v:5120$881 + attribute \src "ls180.v:4989.353-4989.425" + cell $xor $xor$ls180.v:4989$782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282182,10 +279721,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [32] connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:5120$881_Y + connect \Y $xor$ls180.v:4989$782_Y end - attribute \src "ls180.v:5120.200-5120.272" - cell $xor $xor$ls180.v:5120$882 + attribute \src "ls180.v:4989.200-4989.272" + cell $xor $xor$ls180.v:4989$783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282193,21 +279732,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [32] connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:5120$882_Y + connect \Y $xor$ls180.v:4989$783_Y end - attribute \src "ls180.v:5120.160-5120.273" - cell $xor $xor$ls180.v:5120$883 + attribute \src "ls180.v:4989.160-4989.273" + cell $xor $xor$ls180.v:4989$784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg7 [2] - connect \B $xor$ls180.v:5120$882_Y - connect \Y $xor$ls180.v:5120$883_Y + connect \B $xor$ls180.v:4989$783_Y + connect \Y $xor$ls180.v:4989$784_Y end - attribute \src "ls180.v:5121.353-5121.425" - cell $xor $xor$ls180.v:5121$884 + attribute \src "ls180.v:4990.353-4990.425" + cell $xor $xor$ls180.v:4990$785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282215,10 +279754,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [31] connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:5121$884_Y + connect \Y $xor$ls180.v:4990$785_Y end - attribute \src "ls180.v:5121.200-5121.272" - cell $xor $xor$ls180.v:5121$885 + attribute \src "ls180.v:4990.200-4990.272" + cell $xor $xor$ls180.v:4990$786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282226,21 +279765,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [31] connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:5121$885_Y + connect \Y $xor$ls180.v:4990$786_Y end - attribute \src "ls180.v:5121.160-5121.273" - cell $xor $xor$ls180.v:5121$886 + attribute \src "ls180.v:4990.160-4990.273" + cell $xor $xor$ls180.v:4990$787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg8 [2] - connect \B $xor$ls180.v:5121$885_Y - connect \Y $xor$ls180.v:5121$886_Y + connect \B $xor$ls180.v:4990$786_Y + connect \Y $xor$ls180.v:4990$787_Y end - attribute \src "ls180.v:5122.354-5122.426" - cell $xor $xor$ls180.v:5122$887 + attribute \src "ls180.v:4991.354-4991.426" + cell $xor $xor$ls180.v:4991$788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282248,10 +279787,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [30] connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:5122$887_Y + connect \Y $xor$ls180.v:4991$788_Y end - attribute \src "ls180.v:5122.201-5122.273" - cell $xor $xor$ls180.v:5122$888 + attribute \src "ls180.v:4991.201-4991.273" + cell $xor $xor$ls180.v:4991$789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282259,21 +279798,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [30] connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:5122$888_Y + connect \Y $xor$ls180.v:4991$789_Y end - attribute \src "ls180.v:5122.161-5122.274" - cell $xor $xor$ls180.v:5122$889 + attribute \src "ls180.v:4991.161-4991.274" + cell $xor $xor$ls180.v:4991$790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg9 [2] - connect \B $xor$ls180.v:5122$888_Y - connect \Y $xor$ls180.v:5122$889_Y + connect \B $xor$ls180.v:4991$789_Y + connect \Y $xor$ls180.v:4991$790_Y end - attribute \src "ls180.v:5123.361-5123.434" - cell $xor $xor$ls180.v:5123$890 + attribute \src "ls180.v:4992.361-4992.434" + cell $xor $xor$ls180.v:4992$791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282281,10 +279820,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [29] connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:5123$890_Y + connect \Y $xor$ls180.v:4992$791_Y end - attribute \src "ls180.v:5123.205-5123.278" - cell $xor $xor$ls180.v:5123$891 + attribute \src "ls180.v:4992.205-4992.278" + cell $xor $xor$ls180.v:4992$792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282292,21 +279831,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [29] connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:5123$891_Y + connect \Y $xor$ls180.v:4992$792_Y end - attribute \src "ls180.v:5123.164-5123.279" - cell $xor $xor$ls180.v:5123$892 + attribute \src "ls180.v:4992.164-4992.279" + cell $xor $xor$ls180.v:4992$793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg10 [2] - connect \B $xor$ls180.v:5123$891_Y - connect \Y $xor$ls180.v:5123$892_Y + connect \B $xor$ls180.v:4992$792_Y + connect \Y $xor$ls180.v:4992$793_Y end - attribute \src "ls180.v:5124.361-5124.434" - cell $xor $xor$ls180.v:5124$893 + attribute \src "ls180.v:4993.361-4993.434" + cell $xor $xor$ls180.v:4993$794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282314,10 +279853,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [28] connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:5124$893_Y + connect \Y $xor$ls180.v:4993$794_Y end - attribute \src "ls180.v:5124.205-5124.278" - cell $xor $xor$ls180.v:5124$894 + attribute \src "ls180.v:4993.205-4993.278" + cell $xor $xor$ls180.v:4993$795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282325,21 +279864,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [28] connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:5124$894_Y + connect \Y $xor$ls180.v:4993$795_Y end - attribute \src "ls180.v:5124.164-5124.279" - cell $xor $xor$ls180.v:5124$895 + attribute \src "ls180.v:4993.164-4993.279" + cell $xor $xor$ls180.v:4993$796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg11 [2] - connect \B $xor$ls180.v:5124$894_Y - connect \Y $xor$ls180.v:5124$895_Y + connect \B $xor$ls180.v:4993$795_Y + connect \Y $xor$ls180.v:4993$796_Y end - attribute \src "ls180.v:5125.361-5125.434" - cell $xor $xor$ls180.v:5125$896 + attribute \src "ls180.v:4994.361-4994.434" + cell $xor $xor$ls180.v:4994$797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282347,10 +279886,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [27] connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:5125$896_Y + connect \Y $xor$ls180.v:4994$797_Y end - attribute \src "ls180.v:5125.205-5125.278" - cell $xor $xor$ls180.v:5125$897 + attribute \src "ls180.v:4994.205-4994.278" + cell $xor $xor$ls180.v:4994$798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282358,21 +279897,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [27] connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:5125$897_Y + connect \Y $xor$ls180.v:4994$798_Y end - attribute \src "ls180.v:5125.164-5125.279" - cell $xor $xor$ls180.v:5125$898 + attribute \src "ls180.v:4994.164-4994.279" + cell $xor $xor$ls180.v:4994$799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg12 [2] - connect \B $xor$ls180.v:5125$897_Y - connect \Y $xor$ls180.v:5125$898_Y + connect \B $xor$ls180.v:4994$798_Y + connect \Y $xor$ls180.v:4994$799_Y end - attribute \src "ls180.v:5126.361-5126.434" - cell $xor $xor$ls180.v:5126$899 + attribute \src "ls180.v:4995.361-4995.434" + cell $xor $xor$ls180.v:4995$800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282380,10 +279919,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [26] connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:5126$899_Y + connect \Y $xor$ls180.v:4995$800_Y end - attribute \src "ls180.v:5126.205-5126.278" - cell $xor $xor$ls180.v:5126$900 + attribute \src "ls180.v:4995.205-4995.278" + cell $xor $xor$ls180.v:4995$801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282391,21 +279930,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [26] connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:5126$900_Y + connect \Y $xor$ls180.v:4995$801_Y end - attribute \src "ls180.v:5126.164-5126.279" - cell $xor $xor$ls180.v:5126$901 + attribute \src "ls180.v:4995.164-4995.279" + cell $xor $xor$ls180.v:4995$802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg13 [2] - connect \B $xor$ls180.v:5126$900_Y - connect \Y $xor$ls180.v:5126$901_Y + connect \B $xor$ls180.v:4995$801_Y + connect \Y $xor$ls180.v:4995$802_Y end - attribute \src "ls180.v:5127.361-5127.434" - cell $xor $xor$ls180.v:5127$902 + attribute \src "ls180.v:4996.361-4996.434" + cell $xor $xor$ls180.v:4996$803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282413,10 +279952,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [25] connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:5127$902_Y + connect \Y $xor$ls180.v:4996$803_Y end - attribute \src "ls180.v:5127.205-5127.278" - cell $xor $xor$ls180.v:5127$903 + attribute \src "ls180.v:4996.205-4996.278" + cell $xor $xor$ls180.v:4996$804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282424,21 +279963,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [25] connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:5127$903_Y + connect \Y $xor$ls180.v:4996$804_Y end - attribute \src "ls180.v:5127.164-5127.279" - cell $xor $xor$ls180.v:5127$904 + attribute \src "ls180.v:4996.164-4996.279" + cell $xor $xor$ls180.v:4996$805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg14 [2] - connect \B $xor$ls180.v:5127$903_Y - connect \Y $xor$ls180.v:5127$904_Y + connect \B $xor$ls180.v:4996$804_Y + connect \Y $xor$ls180.v:4996$805_Y end - attribute \src "ls180.v:5128.361-5128.434" - cell $xor $xor$ls180.v:5128$905 + attribute \src "ls180.v:4997.361-4997.434" + cell $xor $xor$ls180.v:4997$806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282446,10 +279985,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [24] connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:5128$905_Y + connect \Y $xor$ls180.v:4997$806_Y end - attribute \src "ls180.v:5128.205-5128.278" - cell $xor $xor$ls180.v:5128$906 + attribute \src "ls180.v:4997.205-4997.278" + cell $xor $xor$ls180.v:4997$807 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282457,21 +279996,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [24] connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:5128$906_Y + connect \Y $xor$ls180.v:4997$807_Y end - attribute \src "ls180.v:5128.164-5128.279" - cell $xor $xor$ls180.v:5128$907 + attribute \src "ls180.v:4997.164-4997.279" + cell $xor $xor$ls180.v:4997$808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg15 [2] - connect \B $xor$ls180.v:5128$906_Y - connect \Y $xor$ls180.v:5128$907_Y + connect \B $xor$ls180.v:4997$807_Y + connect \Y $xor$ls180.v:4997$808_Y end - attribute \src "ls180.v:5129.361-5129.434" - cell $xor $xor$ls180.v:5129$908 + attribute \src "ls180.v:4998.361-4998.434" + cell $xor $xor$ls180.v:4998$809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282479,10 +280018,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [23] connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:5129$908_Y + connect \Y $xor$ls180.v:4998$809_Y end - attribute \src "ls180.v:5129.205-5129.278" - cell $xor $xor$ls180.v:5129$909 + attribute \src "ls180.v:4998.205-4998.278" + cell $xor $xor$ls180.v:4998$810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282490,21 +280029,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [23] connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:5129$909_Y + connect \Y $xor$ls180.v:4998$810_Y end - attribute \src "ls180.v:5129.164-5129.279" - cell $xor $xor$ls180.v:5129$910 + attribute \src "ls180.v:4998.164-4998.279" + cell $xor $xor$ls180.v:4998$811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg16 [2] - connect \B $xor$ls180.v:5129$909_Y - connect \Y $xor$ls180.v:5129$910_Y + connect \B $xor$ls180.v:4998$810_Y + connect \Y $xor$ls180.v:4998$811_Y end - attribute \src "ls180.v:5130.361-5130.434" - cell $xor $xor$ls180.v:5130$911 + attribute \src "ls180.v:4999.361-4999.434" + cell $xor $xor$ls180.v:4999$812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282512,10 +280051,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [22] connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:5130$911_Y + connect \Y $xor$ls180.v:4999$812_Y end - attribute \src "ls180.v:5130.205-5130.278" - cell $xor $xor$ls180.v:5130$912 + attribute \src "ls180.v:4999.205-4999.278" + cell $xor $xor$ls180.v:4999$813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282523,21 +280062,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [22] connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:5130$912_Y + connect \Y $xor$ls180.v:4999$813_Y end - attribute \src "ls180.v:5130.164-5130.279" - cell $xor $xor$ls180.v:5130$913 + attribute \src "ls180.v:4999.164-4999.279" + cell $xor $xor$ls180.v:4999$814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg17 [2] - connect \B $xor$ls180.v:5130$912_Y - connect \Y $xor$ls180.v:5130$913_Y + connect \B $xor$ls180.v:4999$813_Y + connect \Y $xor$ls180.v:4999$814_Y end - attribute \src "ls180.v:5131.361-5131.434" - cell $xor $xor$ls180.v:5131$914 + attribute \src "ls180.v:5000.361-5000.434" + cell $xor $xor$ls180.v:5000$815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282545,10 +280084,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [21] connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:5131$914_Y + connect \Y $xor$ls180.v:5000$815_Y end - attribute \src "ls180.v:5131.205-5131.278" - cell $xor $xor$ls180.v:5131$915 + attribute \src "ls180.v:5000.205-5000.278" + cell $xor $xor$ls180.v:5000$816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282556,21 +280095,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [21] connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:5131$915_Y + connect \Y $xor$ls180.v:5000$816_Y end - attribute \src "ls180.v:5131.164-5131.279" - cell $xor $xor$ls180.v:5131$916 + attribute \src "ls180.v:5000.164-5000.279" + cell $xor $xor$ls180.v:5000$817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg18 [2] - connect \B $xor$ls180.v:5131$915_Y - connect \Y $xor$ls180.v:5131$916_Y + connect \B $xor$ls180.v:5000$816_Y + connect \Y $xor$ls180.v:5000$817_Y end - attribute \src "ls180.v:5132.361-5132.434" - cell $xor $xor$ls180.v:5132$917 + attribute \src "ls180.v:5001.361-5001.434" + cell $xor $xor$ls180.v:5001$818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282578,10 +280117,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [20] connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:5132$917_Y + connect \Y $xor$ls180.v:5001$818_Y end - attribute \src "ls180.v:5132.205-5132.278" - cell $xor $xor$ls180.v:5132$918 + attribute \src "ls180.v:5001.205-5001.278" + cell $xor $xor$ls180.v:5001$819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282589,21 +280128,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [20] connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:5132$918_Y + connect \Y $xor$ls180.v:5001$819_Y end - attribute \src "ls180.v:5132.164-5132.279" - cell $xor $xor$ls180.v:5132$919 + attribute \src "ls180.v:5001.164-5001.279" + cell $xor $xor$ls180.v:5001$820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg19 [2] - connect \B $xor$ls180.v:5132$918_Y - connect \Y $xor$ls180.v:5132$919_Y + connect \B $xor$ls180.v:5001$819_Y + connect \Y $xor$ls180.v:5001$820_Y end - attribute \src "ls180.v:5133.361-5133.434" - cell $xor $xor$ls180.v:5133$920 + attribute \src "ls180.v:5002.361-5002.434" + cell $xor $xor$ls180.v:5002$821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282611,10 +280150,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [19] connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:5133$920_Y + connect \Y $xor$ls180.v:5002$821_Y end - attribute \src "ls180.v:5133.205-5133.278" - cell $xor $xor$ls180.v:5133$921 + attribute \src "ls180.v:5002.205-5002.278" + cell $xor $xor$ls180.v:5002$822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282622,21 +280161,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [19] connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:5133$921_Y + connect \Y $xor$ls180.v:5002$822_Y end - attribute \src "ls180.v:5133.164-5133.279" - cell $xor $xor$ls180.v:5133$922 + attribute \src "ls180.v:5002.164-5002.279" + cell $xor $xor$ls180.v:5002$823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg20 [2] - connect \B $xor$ls180.v:5133$921_Y - connect \Y $xor$ls180.v:5133$922_Y + connect \B $xor$ls180.v:5002$822_Y + connect \Y $xor$ls180.v:5002$823_Y end - attribute \src "ls180.v:5134.361-5134.434" - cell $xor $xor$ls180.v:5134$923 + attribute \src "ls180.v:5003.361-5003.434" + cell $xor $xor$ls180.v:5003$824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282644,10 +280183,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [18] connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:5134$923_Y + connect \Y $xor$ls180.v:5003$824_Y end - attribute \src "ls180.v:5134.205-5134.278" - cell $xor $xor$ls180.v:5134$924 + attribute \src "ls180.v:5003.205-5003.278" + cell $xor $xor$ls180.v:5003$825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282655,21 +280194,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [18] connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:5134$924_Y + connect \Y $xor$ls180.v:5003$825_Y end - attribute \src "ls180.v:5134.164-5134.279" - cell $xor $xor$ls180.v:5134$925 + attribute \src "ls180.v:5003.164-5003.279" + cell $xor $xor$ls180.v:5003$826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg21 [2] - connect \B $xor$ls180.v:5134$924_Y - connect \Y $xor$ls180.v:5134$925_Y + connect \B $xor$ls180.v:5003$825_Y + connect \Y $xor$ls180.v:5003$826_Y end - attribute \src "ls180.v:5135.361-5135.434" - cell $xor $xor$ls180.v:5135$926 + attribute \src "ls180.v:5004.361-5004.434" + cell $xor $xor$ls180.v:5004$827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282677,10 +280216,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [17] connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:5135$926_Y + connect \Y $xor$ls180.v:5004$827_Y end - attribute \src "ls180.v:5135.205-5135.278" - cell $xor $xor$ls180.v:5135$927 + attribute \src "ls180.v:5004.205-5004.278" + cell $xor $xor$ls180.v:5004$828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282688,21 +280227,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [17] connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:5135$927_Y + connect \Y $xor$ls180.v:5004$828_Y end - attribute \src "ls180.v:5135.164-5135.279" - cell $xor $xor$ls180.v:5135$928 + attribute \src "ls180.v:5004.164-5004.279" + cell $xor $xor$ls180.v:5004$829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg22 [2] - connect \B $xor$ls180.v:5135$927_Y - connect \Y $xor$ls180.v:5135$928_Y + connect \B $xor$ls180.v:5004$828_Y + connect \Y $xor$ls180.v:5004$829_Y end - attribute \src "ls180.v:5136.361-5136.434" - cell $xor $xor$ls180.v:5136$929 + attribute \src "ls180.v:5005.361-5005.434" + cell $xor $xor$ls180.v:5005$830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282710,10 +280249,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [16] connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:5136$929_Y + connect \Y $xor$ls180.v:5005$830_Y end - attribute \src "ls180.v:5136.205-5136.278" - cell $xor $xor$ls180.v:5136$930 + attribute \src "ls180.v:5005.205-5005.278" + cell $xor $xor$ls180.v:5005$831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282721,21 +280260,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [16] connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:5136$930_Y + connect \Y $xor$ls180.v:5005$831_Y end - attribute \src "ls180.v:5136.164-5136.279" - cell $xor $xor$ls180.v:5136$931 + attribute \src "ls180.v:5005.164-5005.279" + cell $xor $xor$ls180.v:5005$832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg23 [2] - connect \B $xor$ls180.v:5136$930_Y - connect \Y $xor$ls180.v:5136$931_Y + connect \B $xor$ls180.v:5005$831_Y + connect \Y $xor$ls180.v:5005$832_Y end - attribute \src "ls180.v:5137.361-5137.434" - cell $xor $xor$ls180.v:5137$932 + attribute \src "ls180.v:5006.361-5006.434" + cell $xor $xor$ls180.v:5006$833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282743,10 +280282,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [15] connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:5137$932_Y + connect \Y $xor$ls180.v:5006$833_Y end - attribute \src "ls180.v:5137.205-5137.278" - cell $xor $xor$ls180.v:5137$933 + attribute \src "ls180.v:5006.205-5006.278" + cell $xor $xor$ls180.v:5006$834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282754,21 +280293,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [15] connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:5137$933_Y + connect \Y $xor$ls180.v:5006$834_Y end - attribute \src "ls180.v:5137.164-5137.279" - cell $xor $xor$ls180.v:5137$934 + attribute \src "ls180.v:5006.164-5006.279" + cell $xor $xor$ls180.v:5006$835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg24 [2] - connect \B $xor$ls180.v:5137$933_Y - connect \Y $xor$ls180.v:5137$934_Y + connect \B $xor$ls180.v:5006$834_Y + connect \Y $xor$ls180.v:5006$835_Y end - attribute \src "ls180.v:5138.361-5138.434" - cell $xor $xor$ls180.v:5138$935 + attribute \src "ls180.v:5007.361-5007.434" + cell $xor $xor$ls180.v:5007$836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282776,10 +280315,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [14] connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:5138$935_Y + connect \Y $xor$ls180.v:5007$836_Y end - attribute \src "ls180.v:5138.205-5138.278" - cell $xor $xor$ls180.v:5138$936 + attribute \src "ls180.v:5007.205-5007.278" + cell $xor $xor$ls180.v:5007$837 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282787,21 +280326,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [14] connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:5138$936_Y + connect \Y $xor$ls180.v:5007$837_Y end - attribute \src "ls180.v:5138.164-5138.279" - cell $xor $xor$ls180.v:5138$937 + attribute \src "ls180.v:5007.164-5007.279" + cell $xor $xor$ls180.v:5007$838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg25 [2] - connect \B $xor$ls180.v:5138$936_Y - connect \Y $xor$ls180.v:5138$937_Y + connect \B $xor$ls180.v:5007$837_Y + connect \Y $xor$ls180.v:5007$838_Y end - attribute \src "ls180.v:5139.361-5139.434" - cell $xor $xor$ls180.v:5139$938 + attribute \src "ls180.v:5008.361-5008.434" + cell $xor $xor$ls180.v:5008$839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282809,10 +280348,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [13] connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:5139$938_Y + connect \Y $xor$ls180.v:5008$839_Y end - attribute \src "ls180.v:5139.205-5139.278" - cell $xor $xor$ls180.v:5139$939 + attribute \src "ls180.v:5008.205-5008.278" + cell $xor $xor$ls180.v:5008$840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282820,21 +280359,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [13] connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:5139$939_Y + connect \Y $xor$ls180.v:5008$840_Y end - attribute \src "ls180.v:5139.164-5139.279" - cell $xor $xor$ls180.v:5139$940 + attribute \src "ls180.v:5008.164-5008.279" + cell $xor $xor$ls180.v:5008$841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg26 [2] - connect \B $xor$ls180.v:5139$939_Y - connect \Y $xor$ls180.v:5139$940_Y + connect \B $xor$ls180.v:5008$840_Y + connect \Y $xor$ls180.v:5008$841_Y end - attribute \src "ls180.v:5140.361-5140.434" - cell $xor $xor$ls180.v:5140$941 + attribute \src "ls180.v:5009.361-5009.434" + cell $xor $xor$ls180.v:5009$842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282842,10 +280381,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [12] connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:5140$941_Y + connect \Y $xor$ls180.v:5009$842_Y end - attribute \src "ls180.v:5140.205-5140.278" - cell $xor $xor$ls180.v:5140$942 + attribute \src "ls180.v:5009.205-5009.278" + cell $xor $xor$ls180.v:5009$843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282853,21 +280392,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [12] connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:5140$942_Y + connect \Y $xor$ls180.v:5009$843_Y end - attribute \src "ls180.v:5140.164-5140.279" - cell $xor $xor$ls180.v:5140$943 + attribute \src "ls180.v:5009.164-5009.279" + cell $xor $xor$ls180.v:5009$844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg27 [2] - connect \B $xor$ls180.v:5140$942_Y - connect \Y $xor$ls180.v:5140$943_Y + connect \B $xor$ls180.v:5009$843_Y + connect \Y $xor$ls180.v:5009$844_Y end - attribute \src "ls180.v:5141.361-5141.434" - cell $xor $xor$ls180.v:5141$944 + attribute \src "ls180.v:5010.361-5010.434" + cell $xor $xor$ls180.v:5010$845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282875,10 +280414,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [11] connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:5141$944_Y + connect \Y $xor$ls180.v:5010$845_Y end - attribute \src "ls180.v:5141.205-5141.278" - cell $xor $xor$ls180.v:5141$945 + attribute \src "ls180.v:5010.205-5010.278" + cell $xor $xor$ls180.v:5010$846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282886,21 +280425,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [11] connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:5141$945_Y + connect \Y $xor$ls180.v:5010$846_Y end - attribute \src "ls180.v:5141.164-5141.279" - cell $xor $xor$ls180.v:5141$946 + attribute \src "ls180.v:5010.164-5010.279" + cell $xor $xor$ls180.v:5010$847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg28 [2] - connect \B $xor$ls180.v:5141$945_Y - connect \Y $xor$ls180.v:5141$946_Y + connect \B $xor$ls180.v:5010$846_Y + connect \Y $xor$ls180.v:5010$847_Y end - attribute \src "ls180.v:5142.361-5142.434" - cell $xor $xor$ls180.v:5142$947 + attribute \src "ls180.v:5011.361-5011.434" + cell $xor $xor$ls180.v:5011$848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282908,10 +280447,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [10] connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:5142$947_Y + connect \Y $xor$ls180.v:5011$848_Y end - attribute \src "ls180.v:5142.205-5142.278" - cell $xor $xor$ls180.v:5142$948 + attribute \src "ls180.v:5011.205-5011.278" + cell $xor $xor$ls180.v:5011$849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282919,21 +280458,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [10] connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:5142$948_Y + connect \Y $xor$ls180.v:5011$849_Y end - attribute \src "ls180.v:5142.164-5142.279" - cell $xor $xor$ls180.v:5142$949 + attribute \src "ls180.v:5011.164-5011.279" + cell $xor $xor$ls180.v:5011$850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg29 [2] - connect \B $xor$ls180.v:5142$948_Y - connect \Y $xor$ls180.v:5142$949_Y + connect \B $xor$ls180.v:5011$849_Y + connect \Y $xor$ls180.v:5011$850_Y end - attribute \src "ls180.v:5143.360-5143.432" - cell $xor $xor$ls180.v:5143$950 + attribute \src "ls180.v:5012.360-5012.432" + cell $xor $xor$ls180.v:5012$851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282941,10 +280480,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [9] connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:5143$950_Y + connect \Y $xor$ls180.v:5012$851_Y end - attribute \src "ls180.v:5143.205-5143.277" - cell $xor $xor$ls180.v:5143$951 + attribute \src "ls180.v:5012.205-5012.277" + cell $xor $xor$ls180.v:5012$852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282952,21 +280491,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [9] connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:5143$951_Y + connect \Y $xor$ls180.v:5012$852_Y end - attribute \src "ls180.v:5143.164-5143.278" - cell $xor $xor$ls180.v:5143$952 + attribute \src "ls180.v:5012.164-5012.278" + cell $xor $xor$ls180.v:5012$853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg30 [2] - connect \B $xor$ls180.v:5143$951_Y - connect \Y $xor$ls180.v:5143$952_Y + connect \B $xor$ls180.v:5012$852_Y + connect \Y $xor$ls180.v:5012$853_Y end - attribute \src "ls180.v:5144.360-5144.432" - cell $xor $xor$ls180.v:5144$953 + attribute \src "ls180.v:5013.360-5013.432" + cell $xor $xor$ls180.v:5013$854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282974,10 +280513,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [8] connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:5144$953_Y + connect \Y $xor$ls180.v:5013$854_Y end - attribute \src "ls180.v:5144.205-5144.277" - cell $xor $xor$ls180.v:5144$954 + attribute \src "ls180.v:5013.205-5013.277" + cell $xor $xor$ls180.v:5013$855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -282985,21 +280524,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [8] connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:5144$954_Y + connect \Y $xor$ls180.v:5013$855_Y end - attribute \src "ls180.v:5144.164-5144.278" - cell $xor $xor$ls180.v:5144$955 + attribute \src "ls180.v:5013.164-5013.278" + cell $xor $xor$ls180.v:5013$856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg31 [2] - connect \B $xor$ls180.v:5144$954_Y - connect \Y $xor$ls180.v:5144$955_Y + connect \B $xor$ls180.v:5013$855_Y + connect \Y $xor$ls180.v:5013$856_Y end - attribute \src "ls180.v:5145.360-5145.432" - cell $xor $xor$ls180.v:5145$956 + attribute \src "ls180.v:5014.360-5014.432" + cell $xor $xor$ls180.v:5014$857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283007,10 +280546,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [7] connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:5145$956_Y + connect \Y $xor$ls180.v:5014$857_Y end - attribute \src "ls180.v:5145.205-5145.277" - cell $xor $xor$ls180.v:5145$957 + attribute \src "ls180.v:5014.205-5014.277" + cell $xor $xor$ls180.v:5014$858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283018,21 +280557,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [7] connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:5145$957_Y + connect \Y $xor$ls180.v:5014$858_Y end - attribute \src "ls180.v:5145.164-5145.278" - cell $xor $xor$ls180.v:5145$958 + attribute \src "ls180.v:5014.164-5014.278" + cell $xor $xor$ls180.v:5014$859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg32 [2] - connect \B $xor$ls180.v:5145$957_Y - connect \Y $xor$ls180.v:5145$958_Y + connect \B $xor$ls180.v:5014$858_Y + connect \Y $xor$ls180.v:5014$859_Y end - attribute \src "ls180.v:5146.360-5146.432" - cell $xor $xor$ls180.v:5146$959 + attribute \src "ls180.v:5015.360-5015.432" + cell $xor $xor$ls180.v:5015$860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283040,10 +280579,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [6] connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:5146$959_Y + connect \Y $xor$ls180.v:5015$860_Y end - attribute \src "ls180.v:5146.205-5146.277" - cell $xor $xor$ls180.v:5146$960 + attribute \src "ls180.v:5015.205-5015.277" + cell $xor $xor$ls180.v:5015$861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283051,21 +280590,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [6] connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:5146$960_Y + connect \Y $xor$ls180.v:5015$861_Y end - attribute \src "ls180.v:5146.164-5146.278" - cell $xor $xor$ls180.v:5146$961 + attribute \src "ls180.v:5015.164-5015.278" + cell $xor $xor$ls180.v:5015$862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg33 [2] - connect \B $xor$ls180.v:5146$960_Y - connect \Y $xor$ls180.v:5146$961_Y + connect \B $xor$ls180.v:5015$861_Y + connect \Y $xor$ls180.v:5015$862_Y end - attribute \src "ls180.v:5147.360-5147.432" - cell $xor $xor$ls180.v:5147$962 + attribute \src "ls180.v:5016.360-5016.432" + cell $xor $xor$ls180.v:5016$863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283073,10 +280612,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [5] connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:5147$962_Y + connect \Y $xor$ls180.v:5016$863_Y end - attribute \src "ls180.v:5147.205-5147.277" - cell $xor $xor$ls180.v:5147$963 + attribute \src "ls180.v:5016.205-5016.277" + cell $xor $xor$ls180.v:5016$864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283084,21 +280623,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [5] connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:5147$963_Y + connect \Y $xor$ls180.v:5016$864_Y end - attribute \src "ls180.v:5147.164-5147.278" - cell $xor $xor$ls180.v:5147$964 + attribute \src "ls180.v:5016.164-5016.278" + cell $xor $xor$ls180.v:5016$865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg34 [2] - connect \B $xor$ls180.v:5147$963_Y - connect \Y $xor$ls180.v:5147$964_Y + connect \B $xor$ls180.v:5016$864_Y + connect \Y $xor$ls180.v:5016$865_Y end - attribute \src "ls180.v:5148.360-5148.432" - cell $xor $xor$ls180.v:5148$965 + attribute \src "ls180.v:5017.360-5017.432" + cell $xor $xor$ls180.v:5017$866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283106,10 +280645,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [4] connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:5148$965_Y + connect \Y $xor$ls180.v:5017$866_Y end - attribute \src "ls180.v:5148.205-5148.277" - cell $xor $xor$ls180.v:5148$966 + attribute \src "ls180.v:5017.205-5017.277" + cell $xor $xor$ls180.v:5017$867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283117,21 +280656,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [4] connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:5148$966_Y + connect \Y $xor$ls180.v:5017$867_Y end - attribute \src "ls180.v:5148.164-5148.278" - cell $xor $xor$ls180.v:5148$967 + attribute \src "ls180.v:5017.164-5017.278" + cell $xor $xor$ls180.v:5017$868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg35 [2] - connect \B $xor$ls180.v:5148$966_Y - connect \Y $xor$ls180.v:5148$967_Y + connect \B $xor$ls180.v:5017$867_Y + connect \Y $xor$ls180.v:5017$868_Y end - attribute \src "ls180.v:5149.360-5149.432" - cell $xor $xor$ls180.v:5149$968 + attribute \src "ls180.v:5018.360-5018.432" + cell $xor $xor$ls180.v:5018$869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283139,10 +280678,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [3] connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:5149$968_Y + connect \Y $xor$ls180.v:5018$869_Y end - attribute \src "ls180.v:5149.205-5149.277" - cell $xor $xor$ls180.v:5149$969 + attribute \src "ls180.v:5018.205-5018.277" + cell $xor $xor$ls180.v:5018$870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283150,21 +280689,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [3] connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:5149$969_Y + connect \Y $xor$ls180.v:5018$870_Y end - attribute \src "ls180.v:5149.164-5149.278" - cell $xor $xor$ls180.v:5149$970 + attribute \src "ls180.v:5018.164-5018.278" + cell $xor $xor$ls180.v:5018$871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg36 [2] - connect \B $xor$ls180.v:5149$969_Y - connect \Y $xor$ls180.v:5149$970_Y + connect \B $xor$ls180.v:5018$870_Y + connect \Y $xor$ls180.v:5018$871_Y end - attribute \src "ls180.v:5150.360-5150.432" - cell $xor $xor$ls180.v:5150$971 + attribute \src "ls180.v:5019.360-5019.432" + cell $xor $xor$ls180.v:5019$872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283172,10 +280711,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [2] connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:5150$971_Y + connect \Y $xor$ls180.v:5019$872_Y end - attribute \src "ls180.v:5150.205-5150.277" - cell $xor $xor$ls180.v:5150$972 + attribute \src "ls180.v:5019.205-5019.277" + cell $xor $xor$ls180.v:5019$873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283183,21 +280722,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [2] connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:5150$972_Y + connect \Y $xor$ls180.v:5019$873_Y end - attribute \src "ls180.v:5150.164-5150.278" - cell $xor $xor$ls180.v:5150$973 + attribute \src "ls180.v:5019.164-5019.278" + cell $xor $xor$ls180.v:5019$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg37 [2] - connect \B $xor$ls180.v:5150$972_Y - connect \Y $xor$ls180.v:5150$973_Y + connect \B $xor$ls180.v:5019$873_Y + connect \Y $xor$ls180.v:5019$874_Y end - attribute \src "ls180.v:5151.360-5151.432" - cell $xor $xor$ls180.v:5151$974 + attribute \src "ls180.v:5020.360-5020.432" + cell $xor $xor$ls180.v:5020$875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283205,10 +280744,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [1] connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:5151$974_Y + connect \Y $xor$ls180.v:5020$875_Y end - attribute \src "ls180.v:5151.205-5151.277" - cell $xor $xor$ls180.v:5151$975 + attribute \src "ls180.v:5020.205-5020.277" + cell $xor $xor$ls180.v:5020$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283216,21 +280755,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [1] connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:5151$975_Y + connect \Y $xor$ls180.v:5020$876_Y end - attribute \src "ls180.v:5151.164-5151.278" - cell $xor $xor$ls180.v:5151$976 + attribute \src "ls180.v:5020.164-5020.278" + cell $xor $xor$ls180.v:5020$877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg38 [2] - connect \B $xor$ls180.v:5151$975_Y - connect \Y $xor$ls180.v:5151$976_Y + connect \B $xor$ls180.v:5020$876_Y + connect \Y $xor$ls180.v:5020$877_Y end - attribute \src "ls180.v:5152.360-5152.432" - cell $xor $xor$ls180.v:5152$977 + attribute \src "ls180.v:5021.360-5021.432" + cell $xor $xor$ls180.v:5021$878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283238,10 +280777,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [0] connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:5152$977_Y + connect \Y $xor$ls180.v:5021$878_Y end - attribute \src "ls180.v:5152.205-5152.277" - cell $xor $xor$ls180.v:5152$978 + attribute \src "ls180.v:5021.205-5021.277" + cell $xor $xor$ls180.v:5021$879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283249,21 +280788,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_val [0] connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:5152$978_Y + connect \Y $xor$ls180.v:5021$879_Y end - attribute \src "ls180.v:5152.164-5152.278" - cell $xor $xor$ls180.v:5152$979 + attribute \src "ls180.v:5021.164-5021.278" + cell $xor $xor$ls180.v:5021$880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc7_inserter_crcreg39 [2] - connect \B $xor$ls180.v:5152$978_Y - connect \Y $xor$ls180.v:5152$979_Y + connect \B $xor$ls180.v:5021$879_Y + connect \Y $xor$ls180.v:5021$880_Y end - attribute \src "ls180.v:5173.899-5173.983" - cell $xor $xor$ls180.v:5173$993 + attribute \src "ls180.v:5042.899-5042.983" + cell $xor $xor$ls180.v:5042$894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283271,10 +280810,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5173$993_Y + connect \Y $xor$ls180.v:5042$894_Y end - attribute \src "ls180.v:5173.634-5173.718" - cell $xor $xor$ls180.v:5173$994 + attribute \src "ls180.v:5042.634-5042.718" + cell $xor $xor$ls180.v:5042$895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283282,21 +280821,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5173$994_Y + connect \Y $xor$ls180.v:5042$895_Y end - attribute \src "ls180.v:5173.588-5173.719" - cell $xor $xor$ls180.v:5173$995 + attribute \src "ls180.v:5042.588-5042.719" + cell $xor $xor$ls180.v:5042$896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5173$994_Y - connect \Y $xor$ls180.v:5173$995_Y + connect \B $xor$ls180.v:5042$895_Y + connect \Y $xor$ls180.v:5042$896_Y end - attribute \src "ls180.v:5173.234-5173.318" - cell $xor $xor$ls180.v:5173$996 + attribute \src "ls180.v:5042.234-5042.318" + cell $xor $xor$ls180.v:5042$897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283304,32 +280843,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [1] connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5173$996_Y + connect \Y $xor$ls180.v:5042$897_Y end - attribute \src "ls180.v:5173.187-5173.319" - cell $xor $xor$ls180.v:5173$997 + attribute \src "ls180.v:5042.187-5042.319" + cell $xor $xor$ls180.v:5042$898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5173$996_Y - connect \Y $xor$ls180.v:5173$997_Y + connect \B $xor$ls180.v:5042$897_Y + connect \Y $xor$ls180.v:5042$898_Y end - attribute \src "ls180.v:5174.588-5174.719" - cell $xor $xor$ls180.v:5174$1000 + attribute \src "ls180.v:5043.899-5043.983" + cell $xor $xor$ls180.v:5043$899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5174$999_Y - connect \Y $xor$ls180.v:5174$1000_Y + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5043$899_Y end - attribute \src "ls180.v:5174.234-5174.318" - cell $xor $xor$ls180.v:5174$1001 + attribute \src "ls180.v:5043.634-5043.718" + cell $xor $xor$ls180.v:5043$900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283337,21 +280876,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5174$1001_Y + connect \Y $xor$ls180.v:5043$900_Y end - attribute \src "ls180.v:5174.187-5174.319" - cell $xor $xor$ls180.v:5174$1002 + attribute \src "ls180.v:5043.588-5043.719" + cell $xor $xor$ls180.v:5043$901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5174$1001_Y - connect \Y $xor$ls180.v:5174$1002_Y + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] + connect \B $xor$ls180.v:5043$900_Y + connect \Y $xor$ls180.v:5043$901_Y end - attribute \src "ls180.v:5174.899-5174.983" - cell $xor $xor$ls180.v:5174$998 + attribute \src "ls180.v:5043.234-5043.318" + cell $xor $xor$ls180.v:5043$902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283359,21 +280898,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc0_val [0] connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5174$998_Y + connect \Y $xor$ls180.v:5043$902_Y end - attribute \src "ls180.v:5174.634-5174.718" - cell $xor $xor$ls180.v:5174$999 + attribute \src "ls180.v:5043.187-5043.319" + cell $xor $xor$ls180.v:5043$903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [0] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5174$999_Y + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] + connect \B $xor$ls180.v:5043$902_Y + connect \Y $xor$ls180.v:5043$903_Y end - attribute \src "ls180.v:5183.899-5183.983" - cell $xor $xor$ls180.v:5183$1004 + attribute \src "ls180.v:5052.899-5052.983" + cell $xor $xor$ls180.v:5052$905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283381,10 +280920,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5183$1004_Y + connect \Y $xor$ls180.v:5052$905_Y end - attribute \src "ls180.v:5183.634-5183.718" - cell $xor $xor$ls180.v:5183$1005 + attribute \src "ls180.v:5052.634-5052.718" + cell $xor $xor$ls180.v:5052$906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283392,21 +280931,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5183$1005_Y + connect \Y $xor$ls180.v:5052$906_Y end - attribute \src "ls180.v:5183.588-5183.719" - cell $xor $xor$ls180.v:5183$1006 + attribute \src "ls180.v:5052.588-5052.719" + cell $xor $xor$ls180.v:5052$907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5183$1005_Y - connect \Y $xor$ls180.v:5183$1006_Y + connect \B $xor$ls180.v:5052$906_Y + connect \Y $xor$ls180.v:5052$907_Y end - attribute \src "ls180.v:5183.234-5183.318" - cell $xor $xor$ls180.v:5183$1007 + attribute \src "ls180.v:5052.234-5052.318" + cell $xor $xor$ls180.v:5052$908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283414,21 +280953,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [1] connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5183$1007_Y + connect \Y $xor$ls180.v:5052$908_Y end - attribute \src "ls180.v:5183.187-5183.319" - cell $xor $xor$ls180.v:5183$1008 + attribute \src "ls180.v:5052.187-5052.319" + cell $xor $xor$ls180.v:5052$909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5183$1007_Y - connect \Y $xor$ls180.v:5183$1008_Y + connect \B $xor$ls180.v:5052$908_Y + connect \Y $xor$ls180.v:5052$909_Y end - attribute \src "ls180.v:5184.899-5184.983" - cell $xor $xor$ls180.v:5184$1009 + attribute \src "ls180.v:5053.899-5053.983" + cell $xor $xor$ls180.v:5053$910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283436,10 +280975,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5184$1009_Y + connect \Y $xor$ls180.v:5053$910_Y end - attribute \src "ls180.v:5184.634-5184.718" - cell $xor $xor$ls180.v:5184$1010 + attribute \src "ls180.v:5053.634-5053.718" + cell $xor $xor$ls180.v:5053$911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283447,21 +280986,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5184$1010_Y + connect \Y $xor$ls180.v:5053$911_Y end - attribute \src "ls180.v:5184.588-5184.719" - cell $xor $xor$ls180.v:5184$1011 + attribute \src "ls180.v:5053.588-5053.719" + cell $xor $xor$ls180.v:5053$912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5184$1010_Y - connect \Y $xor$ls180.v:5184$1011_Y + connect \B $xor$ls180.v:5053$911_Y + connect \Y $xor$ls180.v:5053$912_Y end - attribute \src "ls180.v:5184.234-5184.318" - cell $xor $xor$ls180.v:5184$1012 + attribute \src "ls180.v:5053.234-5053.318" + cell $xor $xor$ls180.v:5053$913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283469,21 +281008,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_val [0] connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5184$1012_Y + connect \Y $xor$ls180.v:5053$913_Y end - attribute \src "ls180.v:5184.187-5184.319" - cell $xor $xor$ls180.v:5184$1013 + attribute \src "ls180.v:5053.187-5053.319" + cell $xor $xor$ls180.v:5053$914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5184$1012_Y - connect \Y $xor$ls180.v:5184$1013_Y + connect \B $xor$ls180.v:5053$913_Y + connect \Y $xor$ls180.v:5053$914_Y end - attribute \src "ls180.v:5193.899-5193.983" - cell $xor $xor$ls180.v:5193$1015 + attribute \src "ls180.v:5062.899-5062.983" + cell $xor $xor$ls180.v:5062$916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283491,10 +281030,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5193$1015_Y + connect \Y $xor$ls180.v:5062$916_Y end - attribute \src "ls180.v:5193.634-5193.718" - cell $xor $xor$ls180.v:5193$1016 + attribute \src "ls180.v:5062.634-5062.718" + cell $xor $xor$ls180.v:5062$917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283502,21 +281041,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5193$1016_Y + connect \Y $xor$ls180.v:5062$917_Y end - attribute \src "ls180.v:5193.588-5193.719" - cell $xor $xor$ls180.v:5193$1017 + attribute \src "ls180.v:5062.588-5062.719" + cell $xor $xor$ls180.v:5062$918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5193$1016_Y - connect \Y $xor$ls180.v:5193$1017_Y + connect \B $xor$ls180.v:5062$917_Y + connect \Y $xor$ls180.v:5062$918_Y end - attribute \src "ls180.v:5193.234-5193.318" - cell $xor $xor$ls180.v:5193$1018 + attribute \src "ls180.v:5062.234-5062.318" + cell $xor $xor$ls180.v:5062$919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283524,21 +281063,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [1] connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5193$1018_Y + connect \Y $xor$ls180.v:5062$919_Y end - attribute \src "ls180.v:5193.187-5193.319" - cell $xor $xor$ls180.v:5193$1019 + attribute \src "ls180.v:5062.187-5062.319" + cell $xor $xor$ls180.v:5062$920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5193$1018_Y - connect \Y $xor$ls180.v:5193$1019_Y + connect \B $xor$ls180.v:5062$919_Y + connect \Y $xor$ls180.v:5062$920_Y end - attribute \src "ls180.v:5194.899-5194.983" - cell $xor $xor$ls180.v:5194$1020 + attribute \src "ls180.v:5063.899-5063.983" + cell $xor $xor$ls180.v:5063$921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283546,10 +281085,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5194$1020_Y + connect \Y $xor$ls180.v:5063$921_Y end - attribute \src "ls180.v:5194.634-5194.718" - cell $xor $xor$ls180.v:5194$1021 + attribute \src "ls180.v:5063.634-5063.718" + cell $xor $xor$ls180.v:5063$922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283557,21 +281096,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5194$1021_Y + connect \Y $xor$ls180.v:5063$922_Y end - attribute \src "ls180.v:5194.588-5194.719" - cell $xor $xor$ls180.v:5194$1022 + attribute \src "ls180.v:5063.588-5063.719" + cell $xor $xor$ls180.v:5063$923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5194$1021_Y - connect \Y $xor$ls180.v:5194$1022_Y + connect \B $xor$ls180.v:5063$922_Y + connect \Y $xor$ls180.v:5063$923_Y end - attribute \src "ls180.v:5194.234-5194.318" - cell $xor $xor$ls180.v:5194$1023 + attribute \src "ls180.v:5063.234-5063.318" + cell $xor $xor$ls180.v:5063$924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283579,21 +281118,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_val [0] connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5194$1023_Y + connect \Y $xor$ls180.v:5063$924_Y end - attribute \src "ls180.v:5194.187-5194.319" - cell $xor $xor$ls180.v:5194$1024 + attribute \src "ls180.v:5063.187-5063.319" + cell $xor $xor$ls180.v:5063$925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5194$1023_Y - connect \Y $xor$ls180.v:5194$1024_Y + connect \B $xor$ls180.v:5063$924_Y + connect \Y $xor$ls180.v:5063$925_Y end - attribute \src "ls180.v:5203.899-5203.983" - cell $xor $xor$ls180.v:5203$1026 + attribute \src "ls180.v:5072.899-5072.983" + cell $xor $xor$ls180.v:5072$927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283601,10 +281140,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5203$1026_Y + connect \Y $xor$ls180.v:5072$927_Y end - attribute \src "ls180.v:5203.634-5203.718" - cell $xor $xor$ls180.v:5203$1027 + attribute \src "ls180.v:5072.634-5072.718" + cell $xor $xor$ls180.v:5072$928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283612,21 +281151,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5203$1027_Y + connect \Y $xor$ls180.v:5072$928_Y end - attribute \src "ls180.v:5203.588-5203.719" - cell $xor $xor$ls180.v:5203$1028 + attribute \src "ls180.v:5072.588-5072.719" + cell $xor $xor$ls180.v:5072$929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5203$1027_Y - connect \Y $xor$ls180.v:5203$1028_Y + connect \B $xor$ls180.v:5072$928_Y + connect \Y $xor$ls180.v:5072$929_Y end - attribute \src "ls180.v:5203.234-5203.318" - cell $xor $xor$ls180.v:5203$1029 + attribute \src "ls180.v:5072.234-5072.318" + cell $xor $xor$ls180.v:5072$930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283634,21 +281173,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [1] connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5203$1029_Y + connect \Y $xor$ls180.v:5072$930_Y end - attribute \src "ls180.v:5203.187-5203.319" - cell $xor $xor$ls180.v:5203$1030 + attribute \src "ls180.v:5072.187-5072.319" + cell $xor $xor$ls180.v:5072$931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5203$1029_Y - connect \Y $xor$ls180.v:5203$1030_Y + connect \B $xor$ls180.v:5072$930_Y + connect \Y $xor$ls180.v:5072$931_Y end - attribute \src "ls180.v:5204.899-5204.983" - cell $xor $xor$ls180.v:5204$1031 + attribute \src "ls180.v:5073.899-5073.983" + cell $xor $xor$ls180.v:5073$932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283656,10 +281195,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5204$1031_Y + connect \Y $xor$ls180.v:5073$932_Y end - attribute \src "ls180.v:5204.634-5204.718" - cell $xor $xor$ls180.v:5204$1032 + attribute \src "ls180.v:5073.634-5073.718" + cell $xor $xor$ls180.v:5073$933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283667,21 +281206,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5204$1032_Y + connect \Y $xor$ls180.v:5073$933_Y end - attribute \src "ls180.v:5204.588-5204.719" - cell $xor $xor$ls180.v:5204$1033 + attribute \src "ls180.v:5073.588-5073.719" + cell $xor $xor$ls180.v:5073$934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5204$1032_Y - connect \Y $xor$ls180.v:5204$1033_Y + connect \B $xor$ls180.v:5073$933_Y + connect \Y $xor$ls180.v:5073$934_Y end - attribute \src "ls180.v:5204.234-5204.318" - cell $xor $xor$ls180.v:5204$1034 + attribute \src "ls180.v:5073.234-5073.318" + cell $xor $xor$ls180.v:5073$935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283689,21 +281228,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_val [0] connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5204$1034_Y + connect \Y $xor$ls180.v:5073$935_Y end - attribute \src "ls180.v:5204.187-5204.319" - cell $xor $xor$ls180.v:5204$1035 + attribute \src "ls180.v:5073.187-5073.319" + cell $xor $xor$ls180.v:5073$936 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5204$1034_Y - connect \Y $xor$ls180.v:5204$1035_Y + connect \B $xor$ls180.v:5073$935_Y + connect \Y $xor$ls180.v:5073$936_Y end - attribute \src "ls180.v:5355.879-5355.961" - cell $xor $xor$ls180.v:5355$1068 + attribute \src "ls180.v:5224.879-5224.961" + cell $xor $xor$ls180.v:5224$969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283711,10 +281250,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5355$1068_Y + connect \Y $xor$ls180.v:5224$969_Y end - attribute \src "ls180.v:5355.620-5355.702" - cell $xor $xor$ls180.v:5355$1069 + attribute \src "ls180.v:5224.620-5224.702" + cell $xor $xor$ls180.v:5224$970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283722,21 +281261,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5355$1069_Y + connect \Y $xor$ls180.v:5224$970_Y end - attribute \src "ls180.v:5355.575-5355.703" - cell $xor $xor$ls180.v:5355$1070 + attribute \src "ls180.v:5224.575-5224.703" + cell $xor $xor$ls180.v:5224$971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5355$1069_Y - connect \Y $xor$ls180.v:5355$1070_Y + connect \B $xor$ls180.v:5224$970_Y + connect \Y $xor$ls180.v:5224$971_Y end - attribute \src "ls180.v:5355.229-5355.311" - cell $xor $xor$ls180.v:5355$1071 + attribute \src "ls180.v:5224.229-5224.311" + cell $xor $xor$ls180.v:5224$972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283744,21 +281283,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [1] connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5355$1071_Y + connect \Y $xor$ls180.v:5224$972_Y end - attribute \src "ls180.v:5355.183-5355.312" - cell $xor $xor$ls180.v:5355$1072 + attribute \src "ls180.v:5224.183-5224.312" + cell $xor $xor$ls180.v:5224$973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5355$1071_Y - connect \Y $xor$ls180.v:5355$1072_Y + connect \B $xor$ls180.v:5224$972_Y + connect \Y $xor$ls180.v:5224$973_Y end - attribute \src "ls180.v:5356.879-5356.961" - cell $xor $xor$ls180.v:5356$1073 + attribute \src "ls180.v:5225.879-5225.961" + cell $xor $xor$ls180.v:5225$974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283766,10 +281305,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5356$1073_Y + connect \Y $xor$ls180.v:5225$974_Y end - attribute \src "ls180.v:5356.620-5356.702" - cell $xor $xor$ls180.v:5356$1074 + attribute \src "ls180.v:5225.620-5225.702" + cell $xor $xor$ls180.v:5225$975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283777,21 +281316,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5356$1074_Y + connect \Y $xor$ls180.v:5225$975_Y end - attribute \src "ls180.v:5356.575-5356.703" - cell $xor $xor$ls180.v:5356$1075 + attribute \src "ls180.v:5225.575-5225.703" + cell $xor $xor$ls180.v:5225$976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5356$1074_Y - connect \Y $xor$ls180.v:5356$1075_Y + connect \B $xor$ls180.v:5225$975_Y + connect \Y $xor$ls180.v:5225$976_Y end - attribute \src "ls180.v:5356.229-5356.311" - cell $xor $xor$ls180.v:5356$1076 + attribute \src "ls180.v:5225.229-5225.311" + cell $xor $xor$ls180.v:5225$977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283799,21 +281338,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_val [0] connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5356$1076_Y + connect \Y $xor$ls180.v:5225$977_Y end - attribute \src "ls180.v:5356.183-5356.312" - cell $xor $xor$ls180.v:5356$1077 + attribute \src "ls180.v:5225.183-5225.312" + cell $xor $xor$ls180.v:5225$978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5356$1076_Y - connect \Y $xor$ls180.v:5356$1077_Y + connect \B $xor$ls180.v:5225$977_Y + connect \Y $xor$ls180.v:5225$978_Y end - attribute \src "ls180.v:5365.879-5365.961" - cell $xor $xor$ls180.v:5365$1079 + attribute \src "ls180.v:5234.879-5234.961" + cell $xor $xor$ls180.v:5234$980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283821,10 +281360,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5365$1079_Y + connect \Y $xor$ls180.v:5234$980_Y end - attribute \src "ls180.v:5365.620-5365.702" - cell $xor $xor$ls180.v:5365$1080 + attribute \src "ls180.v:5234.620-5234.702" + cell $xor $xor$ls180.v:5234$981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283832,21 +281371,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5365$1080_Y + connect \Y $xor$ls180.v:5234$981_Y end - attribute \src "ls180.v:5365.575-5365.703" - cell $xor $xor$ls180.v:5365$1081 + attribute \src "ls180.v:5234.575-5234.703" + cell $xor $xor$ls180.v:5234$982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5365$1080_Y - connect \Y $xor$ls180.v:5365$1081_Y + connect \B $xor$ls180.v:5234$981_Y + connect \Y $xor$ls180.v:5234$982_Y end - attribute \src "ls180.v:5365.229-5365.311" - cell $xor $xor$ls180.v:5365$1082 + attribute \src "ls180.v:5234.229-5234.311" + cell $xor $xor$ls180.v:5234$983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283854,21 +281393,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [1] connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5365$1082_Y + connect \Y $xor$ls180.v:5234$983_Y end - attribute \src "ls180.v:5365.183-5365.312" - cell $xor $xor$ls180.v:5365$1083 + attribute \src "ls180.v:5234.183-5234.312" + cell $xor $xor$ls180.v:5234$984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5365$1082_Y - connect \Y $xor$ls180.v:5365$1083_Y + connect \B $xor$ls180.v:5234$983_Y + connect \Y $xor$ls180.v:5234$984_Y end - attribute \src "ls180.v:5366.879-5366.961" - cell $xor $xor$ls180.v:5366$1084 + attribute \src "ls180.v:5235.879-5235.961" + cell $xor $xor$ls180.v:5235$985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283876,10 +281415,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5366$1084_Y + connect \Y $xor$ls180.v:5235$985_Y end - attribute \src "ls180.v:5366.620-5366.702" - cell $xor $xor$ls180.v:5366$1085 + attribute \src "ls180.v:5235.620-5235.702" + cell $xor $xor$ls180.v:5235$986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283887,21 +281426,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5366$1085_Y + connect \Y $xor$ls180.v:5235$986_Y end - attribute \src "ls180.v:5366.575-5366.703" - cell $xor $xor$ls180.v:5366$1086 + attribute \src "ls180.v:5235.575-5235.703" + cell $xor $xor$ls180.v:5235$987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5366$1085_Y - connect \Y $xor$ls180.v:5366$1086_Y + connect \B $xor$ls180.v:5235$986_Y + connect \Y $xor$ls180.v:5235$987_Y end - attribute \src "ls180.v:5366.229-5366.311" - cell $xor $xor$ls180.v:5366$1087 + attribute \src "ls180.v:5235.229-5235.311" + cell $xor $xor$ls180.v:5235$988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283909,21 +281448,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_val [0] connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5366$1087_Y + connect \Y $xor$ls180.v:5235$988_Y end - attribute \src "ls180.v:5366.183-5366.312" - cell $xor $xor$ls180.v:5366$1088 + attribute \src "ls180.v:5235.183-5235.312" + cell $xor $xor$ls180.v:5235$989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5366$1087_Y - connect \Y $xor$ls180.v:5366$1088_Y + connect \B $xor$ls180.v:5235$988_Y + connect \Y $xor$ls180.v:5235$989_Y end - attribute \src "ls180.v:5375.879-5375.961" - cell $xor $xor$ls180.v:5375$1090 + attribute \src "ls180.v:5244.879-5244.961" + cell $xor $xor$ls180.v:5244$991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283931,10 +281470,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5375$1090_Y + connect \Y $xor$ls180.v:5244$991_Y end - attribute \src "ls180.v:5375.620-5375.702" - cell $xor $xor$ls180.v:5375$1091 + attribute \src "ls180.v:5244.620-5244.702" + cell $xor $xor$ls180.v:5244$992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283942,21 +281481,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5375$1091_Y + connect \Y $xor$ls180.v:5244$992_Y end - attribute \src "ls180.v:5375.575-5375.703" - cell $xor $xor$ls180.v:5375$1092 + attribute \src "ls180.v:5244.575-5244.703" + cell $xor $xor$ls180.v:5244$993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5375$1091_Y - connect \Y $xor$ls180.v:5375$1092_Y + connect \B $xor$ls180.v:5244$992_Y + connect \Y $xor$ls180.v:5244$993_Y end - attribute \src "ls180.v:5375.229-5375.311" - cell $xor $xor$ls180.v:5375$1093 + attribute \src "ls180.v:5244.229-5244.311" + cell $xor $xor$ls180.v:5244$994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283964,32 +281503,32 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [1] connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5375$1093_Y + connect \Y $xor$ls180.v:5244$994_Y end - attribute \src "ls180.v:5375.183-5375.312" - cell $xor $xor$ls180.v:5375$1094 + attribute \src "ls180.v:5244.183-5244.312" + cell $xor $xor$ls180.v:5244$995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5375$1093_Y - connect \Y $xor$ls180.v:5375$1094_Y + connect \B $xor$ls180.v:5244$994_Y + connect \Y $xor$ls180.v:5244$995_Y end - attribute \src "ls180.v:5376.879-5376.961" - cell $xor $xor$ls180.v:5376$1095 + attribute \src "ls180.v:5245.183-5245.312" + cell $xor $xor$ls180.v:5245$1000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5376$1095_Y + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] + connect \B $xor$ls180.v:5245$999_Y + connect \Y $xor$ls180.v:5245$1000_Y end - attribute \src "ls180.v:5376.620-5376.702" - cell $xor $xor$ls180.v:5376$1096 + attribute \src "ls180.v:5245.879-5245.961" + cell $xor $xor$ls180.v:5245$996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -283997,43 +281536,43 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc2_val [0] connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5376$1096_Y + connect \Y $xor$ls180.v:5245$996_Y end - attribute \src "ls180.v:5376.575-5376.703" - cell $xor $xor$ls180.v:5376$1097 + attribute \src "ls180.v:5245.620-5245.702" + cell $xor $xor$ls180.v:5245$997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5376$1096_Y - connect \Y $xor$ls180.v:5376$1097_Y + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5245$997_Y end - attribute \src "ls180.v:5376.229-5376.311" - cell $xor $xor$ls180.v:5376$1098 + attribute \src "ls180.v:5245.575-5245.703" + cell $xor $xor$ls180.v:5245$998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5376$1098_Y + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] + connect \B $xor$ls180.v:5245$997_Y + connect \Y $xor$ls180.v:5245$998_Y end - attribute \src "ls180.v:5376.183-5376.312" - cell $xor $xor$ls180.v:5376$1099 + attribute \src "ls180.v:5245.229-5245.311" + cell $xor $xor$ls180.v:5245$999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5376$1098_Y - connect \Y $xor$ls180.v:5376$1099_Y + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5245$999_Y end - attribute \src "ls180.v:5385.879-5385.961" - cell $xor $xor$ls180.v:5385$1101 + attribute \src "ls180.v:5254.879-5254.961" + cell $xor $xor$ls180.v:5254$1002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284041,10 +281580,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5385$1101_Y + connect \Y $xor$ls180.v:5254$1002_Y end - attribute \src "ls180.v:5385.620-5385.702" - cell $xor $xor$ls180.v:5385$1102 + attribute \src "ls180.v:5254.620-5254.702" + cell $xor $xor$ls180.v:5254$1003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284052,21 +281591,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5385$1102_Y + connect \Y $xor$ls180.v:5254$1003_Y end - attribute \src "ls180.v:5385.575-5385.703" - cell $xor $xor$ls180.v:5385$1103 + attribute \src "ls180.v:5254.575-5254.703" + cell $xor $xor$ls180.v:5254$1004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5385$1102_Y - connect \Y $xor$ls180.v:5385$1103_Y + connect \B $xor$ls180.v:5254$1003_Y + connect \Y $xor$ls180.v:5254$1004_Y end - attribute \src "ls180.v:5385.229-5385.311" - cell $xor $xor$ls180.v:5385$1104 + attribute \src "ls180.v:5254.229-5254.311" + cell $xor $xor$ls180.v:5254$1005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284074,21 +281613,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [1] connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5385$1104_Y + connect \Y $xor$ls180.v:5254$1005_Y end - attribute \src "ls180.v:5385.183-5385.312" - cell $xor $xor$ls180.v:5385$1105 + attribute \src "ls180.v:5254.183-5254.312" + cell $xor $xor$ls180.v:5254$1006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5385$1104_Y - connect \Y $xor$ls180.v:5385$1105_Y + connect \B $xor$ls180.v:5254$1005_Y + connect \Y $xor$ls180.v:5254$1006_Y end - attribute \src "ls180.v:5386.879-5386.961" - cell $xor $xor$ls180.v:5386$1106 + attribute \src "ls180.v:5255.879-5255.961" + cell $xor $xor$ls180.v:5255$1007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284096,10 +281635,10 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5386$1106_Y + connect \Y $xor$ls180.v:5255$1007_Y end - attribute \src "ls180.v:5386.620-5386.702" - cell $xor $xor$ls180.v:5386$1107 + attribute \src "ls180.v:5255.620-5255.702" + cell $xor $xor$ls180.v:5255$1008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284107,21 +281646,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5386$1107_Y + connect \Y $xor$ls180.v:5255$1008_Y end - attribute \src "ls180.v:5386.575-5386.703" - cell $xor $xor$ls180.v:5386$1108 + attribute \src "ls180.v:5255.575-5255.703" + cell $xor $xor$ls180.v:5255$1009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5386$1107_Y - connect \Y $xor$ls180.v:5386$1108_Y + connect \B $xor$ls180.v:5255$1008_Y + connect \Y $xor$ls180.v:5255$1009_Y end - attribute \src "ls180.v:5386.229-5386.311" - cell $xor $xor$ls180.v:5386$1109 + attribute \src "ls180.v:5255.229-5255.311" + cell $xor $xor$ls180.v:5255$1010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -284129,21 +281668,21 @@ module \ls180 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_val [0] connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5386$1109_Y + connect \Y $xor$ls180.v:5255$1010_Y end - attribute \src "ls180.v:5386.183-5386.312" - cell $xor $xor$ls180.v:5386$1110 + attribute \src "ls180.v:5255.183-5255.312" + cell $xor $xor$ls180.v:5255$1011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5386$1109_Y - connect \Y $xor$ls180.v:5386$1110_Y + connect \B $xor$ls180.v:5255$1010_Y + connect \Y $xor$ls180.v:5255$1011_Y end attribute \module_not_derived 1 - attribute \src "ls180.v:10609.13-11015.2" + attribute \src "ls180.v:10316.13-10686.2" cell \test_issuer \test_issuer connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi @@ -284339,7 +281878,7 @@ module \ls180 connect \pwm_0__pad__o \pwm_1 [0] connect \pwm_1__core__o \pwm [1] connect \pwm_1__pad__o \pwm_1 [1] - connect \rst $or$ls180.v:10709$3079_Y + connect \rst $or$ls180.v:10416$2851_Y connect \sd0_clk__core__o \sdcard_clk connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk connect \sd0_cmd__core__i \sdcard_cmd_i @@ -284514,158 +282053,250 @@ module \ls180 connect \sdr_ras_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n connect \sdr_we_n__core__o \sdram_we_n connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - connect \sram4k_0_wb__ack \main_libresocsim_libresoc_interface0_ack - connect \sram4k_0_wb__adr \main_libresocsim_libresoc_interface0_adr - connect \sram4k_0_wb__cyc \main_libresocsim_libresoc_interface0_cyc - connect \sram4k_0_wb__dat_r \main_libresocsim_libresoc_interface0_dat_r - connect \sram4k_0_wb__dat_w \main_libresocsim_libresoc_interface0_dat_w - connect \sram4k_0_wb__err \main_libresocsim_libresoc_interface0_err - connect \sram4k_0_wb__sel \main_libresocsim_libresoc_interface0_sel - connect \sram4k_0_wb__stb \main_libresocsim_libresoc_interface0_stb - connect \sram4k_0_wb__we \main_libresocsim_libresoc_interface0_we - connect \sram4k_1_wb__ack \main_libresocsim_libresoc_interface1_ack - connect \sram4k_1_wb__adr \main_libresocsim_libresoc_interface1_adr - connect \sram4k_1_wb__cyc \main_libresocsim_libresoc_interface1_cyc - connect \sram4k_1_wb__dat_r \main_libresocsim_libresoc_interface1_dat_r - connect \sram4k_1_wb__dat_w \main_libresocsim_libresoc_interface1_dat_w - connect \sram4k_1_wb__err \main_libresocsim_libresoc_interface1_err - connect \sram4k_1_wb__sel \main_libresocsim_libresoc_interface1_sel - connect \sram4k_1_wb__stb \main_libresocsim_libresoc_interface1_stb - connect \sram4k_1_wb__we \main_libresocsim_libresoc_interface1_we - connect \sram4k_2_wb__ack \main_libresocsim_libresoc_interface2_ack - connect \sram4k_2_wb__adr \main_libresocsim_libresoc_interface2_adr - connect \sram4k_2_wb__cyc \main_libresocsim_libresoc_interface2_cyc - connect \sram4k_2_wb__dat_r \main_libresocsim_libresoc_interface2_dat_r - connect \sram4k_2_wb__dat_w \main_libresocsim_libresoc_interface2_dat_w - connect \sram4k_2_wb__err \main_libresocsim_libresoc_interface2_err - connect \sram4k_2_wb__sel \main_libresocsim_libresoc_interface2_sel - connect \sram4k_2_wb__stb \main_libresocsim_libresoc_interface2_stb - connect \sram4k_2_wb__we \main_libresocsim_libresoc_interface2_we - connect \sram4k_3_wb__ack \main_libresocsim_libresoc_interface3_ack - connect \sram4k_3_wb__adr \main_libresocsim_libresoc_interface3_adr - connect \sram4k_3_wb__cyc \main_libresocsim_libresoc_interface3_cyc - connect \sram4k_3_wb__dat_r \main_libresocsim_libresoc_interface3_dat_r - connect \sram4k_3_wb__dat_w \main_libresocsim_libresoc_interface3_dat_w - connect \sram4k_3_wb__err \main_libresocsim_libresoc_interface3_err - connect \sram4k_3_wb__sel \main_libresocsim_libresoc_interface3_sel - connect \sram4k_3_wb__stb \main_libresocsim_libresoc_interface3_stb - connect \sram4k_3_wb__we \main_libresocsim_libresoc_interface3_we end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4093 + process $proc$ls180.v:0$3832 sync always sync init end attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4094 - sync always - sync init - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4095 - sync always - sync init - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4096 - sync always - sync init - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$4097 + process $proc$ls180.v:0$3833 sync always sync init end attribute \src "ls180.v:100.11-100.56" - process $proc$ls180.v:100$3146 + process $proc$ls180.v:100$2894 assign { } { } assign $1\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 sync always sync init update \main_libresocsim_libresoc_xics_ics_sel $1\main_libresocsim_libresoc_xics_ics_sel[3:0] end - attribute \src "ls180.v:101.5-101.50" - process $proc$ls180.v:101$3147 + attribute \src "ls180.v:1002.12-1002.53" + process $proc$ls180.v:1002$3242 assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 + assign $1\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 sync always sync init - update \main_libresocsim_libresoc_xics_ics_cyc $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] + update \main_gpiotristateasic1_oe_storage $1\main_gpiotristateasic1_oe_storage[15:0] end - attribute \src "ls180.v:1012.5-1012.40" - process $proc$ls180.v:1012$3485 + attribute \src "ls180.v:1003.5-1003.40" + process $proc$ls180.v:1003$3243 assign { } { } - assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 + assign $1\main_gpiotristateasic1_oe_re[0:0] 1'0 sync always - update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] sync init + update \main_gpiotristateasic1_oe_re $1\main_gpiotristateasic1_oe_re[0:0] end - attribute \src "ls180.v:1013.5-1013.39" - process $proc$ls180.v:1013$3486 + attribute \src "ls180.v:1004.12-1004.49" + process $proc$ls180.v:1004$3244 assign { } { } - assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 + assign $1\main_gpiotristateasic1_status[15:0] 16'0000000000000000 sync always - update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] sync init + update \main_gpiotristateasic1_status $1\main_gpiotristateasic1_status[15:0] end - attribute \src "ls180.v:102.5-102.50" - process $proc$ls180.v:102$3148 + attribute \src "ls180.v:1006.12-1006.54" + process $proc$ls180.v:1006$3245 assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 + assign $1\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 sync always sync init - update \main_libresocsim_libresoc_xics_ics_stb $1\main_libresocsim_libresoc_xics_ics_stb[0:0] + update \main_gpiotristateasic1_out_storage $1\main_gpiotristateasic1_out_storage[15:0] end - attribute \src "ls180.v:1021.5-1021.38" - process $proc$ls180.v:1021$3487 + attribute \src "ls180.v:1007.5-1007.41" + process $proc$ls180.v:1007$3246 assign { } { } - assign $1\main_uart_tx_fifo_readable[0:0] 1'0 + assign $1\main_gpiotristateasic1_out_re[0:0] 1'0 sync always sync init - update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] + update \main_gpiotristateasic1_out_re $1\main_gpiotristateasic1_out_re[0:0] end - attribute \src "ls180.v:1028.11-1028.42" - process $proc$ls180.v:1028$3488 + attribute \src "ls180.v:101.5-101.50" + process $proc$ls180.v:101$2895 assign { } { } - assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 sync always sync init - update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] + update \main_libresocsim_libresoc_xics_ics_cyc $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] end - attribute \src "ls180.v:1029.5-1029.37" - process $proc$ls180.v:1029$3489 + attribute \src "ls180.v:1013.5-1013.32" + process $proc$ls180.v:1013$3247 assign { } { } - assign $0\main_uart_tx_fifo_replace[0:0] 1'0 + assign $1\main_spimaster2_done[0:0] 1'0 sync always - update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] sync init + update \main_spimaster2_done $1\main_spimaster2_done[0:0] end - attribute \src "ls180.v:1030.11-1030.43" - process $proc$ls180.v:1030$3490 + attribute \src "ls180.v:1014.5-1014.31" + process $proc$ls180.v:1014$3248 assign { } { } - assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $1\main_spimaster3_irq[0:0] 1'0 sync always sync init - update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] + update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] end - attribute \src "ls180.v:1031.11-1031.43" - process $proc$ls180.v:1031$3491 + attribute \src "ls180.v:10144.1-10162.4" + process $proc$ls180.v:10144$2743 assign { } { } - assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 - sync always - sync init - update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] - end - attribute \src "ls180.v:1032.11-1032.46" - process $proc$ls180.v:1032$3492 assign { } { } - assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem$ls180.v:10160$8_ADDR[3:0]$2765 4'xxxx + assign $0$memwr$\mem$ls180.v:10160$8_DATA[63:0]$2766 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10160$8_EN[63:0]$2767 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10158$7_ADDR[3:0]$2762 4'xxxx + assign $0$memwr$\mem$ls180.v:10158$7_DATA[63:0]$2763 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10158$7_EN[63:0]$2764 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10156$6_ADDR[3:0]$2759 4'xxxx + assign $0$memwr$\mem$ls180.v:10156$6_DATA[63:0]$2760 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10156$6_EN[63:0]$2761 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10154$5_ADDR[3:0]$2756 4'xxxx + assign $0$memwr$\mem$ls180.v:10154$5_DATA[63:0]$2757 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10154$5_EN[63:0]$2758 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10152$4_ADDR[3:0]$2753 4'xxxx + assign $0$memwr$\mem$ls180.v:10152$4_DATA[63:0]$2754 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10152$4_EN[63:0]$2755 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10150$3_ADDR[3:0]$2750 4'xxxx + assign $0$memwr$\mem$ls180.v:10150$3_DATA[63:0]$2751 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10150$3_EN[63:0]$2752 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10148$2_ADDR[3:0]$2747 4'xxxx + assign $0$memwr$\mem$ls180.v:10148$2_DATA[63:0]$2748 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10148$2_EN[63:0]$2749 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10146$1_ADDR[3:0]$2744 4'xxxx + assign $0$memwr$\mem$ls180.v:10146$1_DATA[63:0]$2745 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10146$1_EN[63:0]$2746 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr[3:0] \main_libresocsim_adr + attribute \src "ls180.v:10145.2-10146.65" + switch \main_libresocsim_we [0] + attribute \src "ls180.v:10145.6-10145.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10146$1_ADDR[3:0]$2744 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10146$1_DATA[63:0]$2745 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$ls180.v:10146$1_EN[63:0]$2746 64'0000000000000000000000000000000000000000000000000000000011111111 + case + end + attribute \src "ls180.v:10147.2-10148.67" + switch \main_libresocsim_we [1] + attribute \src "ls180.v:10147.6-10147.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10148$2_ADDR[3:0]$2747 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10148$2_DATA[63:0]$2748 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$ls180.v:10148$2_EN[63:0]$2749 64'0000000000000000000000000000000000000000000000001111111100000000 + case + end + attribute \src "ls180.v:10149.2-10150.69" + switch \main_libresocsim_we [2] + attribute \src "ls180.v:10149.6-10149.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10150$3_ADDR[3:0]$2750 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10150$3_DATA[63:0]$2751 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10150$3_EN[63:0]$2752 64'0000000000000000000000000000000000000000111111110000000000000000 + case + end + attribute \src "ls180.v:10151.2-10152.69" + switch \main_libresocsim_we [3] + attribute \src "ls180.v:10151.6-10151.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10152$4_ADDR[3:0]$2753 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10152$4_DATA[63:0]$2754 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10152$4_EN[63:0]$2755 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10153.2-10154.69" + switch \main_libresocsim_we [4] + attribute \src "ls180.v:10153.6-10153.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10154$5_ADDR[3:0]$2756 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10154$5_DATA[63:0]$2757 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10154$5_EN[63:0]$2758 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10155.2-10156.69" + switch \main_libresocsim_we [5] + attribute \src "ls180.v:10155.6-10155.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10156$6_ADDR[3:0]$2759 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10156$6_DATA[63:0]$2760 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10156$6_EN[63:0]$2761 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10157.2-10158.69" + switch \main_libresocsim_we [6] + attribute \src "ls180.v:10157.6-10157.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10158$7_ADDR[3:0]$2762 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10158$7_DATA[63:0]$2763 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10158$7_EN[63:0]$2764 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10159.2-10160.69" + switch \main_libresocsim_we [7] + attribute \src "ls180.v:10159.6-10159.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10160$8_ADDR[3:0]$2765 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10160$8_DATA[63:0]$2766 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10160$8_EN[63:0]$2767 64'1111111100000000000000000000000000000000000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr $0\memadr[3:0] + update $memwr$\mem$ls180.v:10146$1_ADDR $0$memwr$\mem$ls180.v:10146$1_ADDR[3:0]$2744 + update $memwr$\mem$ls180.v:10146$1_DATA $0$memwr$\mem$ls180.v:10146$1_DATA[63:0]$2745 + update $memwr$\mem$ls180.v:10146$1_EN $0$memwr$\mem$ls180.v:10146$1_EN[63:0]$2746 + update $memwr$\mem$ls180.v:10148$2_ADDR $0$memwr$\mem$ls180.v:10148$2_ADDR[3:0]$2747 + update $memwr$\mem$ls180.v:10148$2_DATA $0$memwr$\mem$ls180.v:10148$2_DATA[63:0]$2748 + update $memwr$\mem$ls180.v:10148$2_EN $0$memwr$\mem$ls180.v:10148$2_EN[63:0]$2749 + update $memwr$\mem$ls180.v:10150$3_ADDR $0$memwr$\mem$ls180.v:10150$3_ADDR[3:0]$2750 + update $memwr$\mem$ls180.v:10150$3_DATA $0$memwr$\mem$ls180.v:10150$3_DATA[63:0]$2751 + update $memwr$\mem$ls180.v:10150$3_EN $0$memwr$\mem$ls180.v:10150$3_EN[63:0]$2752 + update $memwr$\mem$ls180.v:10152$4_ADDR $0$memwr$\mem$ls180.v:10152$4_ADDR[3:0]$2753 + update $memwr$\mem$ls180.v:10152$4_DATA $0$memwr$\mem$ls180.v:10152$4_DATA[63:0]$2754 + update $memwr$\mem$ls180.v:10152$4_EN $0$memwr$\mem$ls180.v:10152$4_EN[63:0]$2755 + update $memwr$\mem$ls180.v:10154$5_ADDR $0$memwr$\mem$ls180.v:10154$5_ADDR[3:0]$2756 + update $memwr$\mem$ls180.v:10154$5_DATA $0$memwr$\mem$ls180.v:10154$5_DATA[63:0]$2757 + update $memwr$\mem$ls180.v:10154$5_EN $0$memwr$\mem$ls180.v:10154$5_EN[63:0]$2758 + update $memwr$\mem$ls180.v:10156$6_ADDR $0$memwr$\mem$ls180.v:10156$6_ADDR[3:0]$2759 + update $memwr$\mem$ls180.v:10156$6_DATA $0$memwr$\mem$ls180.v:10156$6_DATA[63:0]$2760 + update $memwr$\mem$ls180.v:10156$6_EN $0$memwr$\mem$ls180.v:10156$6_EN[63:0]$2761 + update $memwr$\mem$ls180.v:10158$7_ADDR $0$memwr$\mem$ls180.v:10158$7_ADDR[3:0]$2762 + update $memwr$\mem$ls180.v:10158$7_DATA $0$memwr$\mem$ls180.v:10158$7_DATA[63:0]$2763 + update $memwr$\mem$ls180.v:10158$7_EN $0$memwr$\mem$ls180.v:10158$7_EN[63:0]$2764 + update $memwr$\mem$ls180.v:10160$8_ADDR $0$memwr$\mem$ls180.v:10160$8_ADDR[3:0]$2765 + update $memwr$\mem$ls180.v:10160$8_DATA $0$memwr$\mem$ls180.v:10160$8_DATA[63:0]$2766 + update $memwr$\mem$ls180.v:10160$8_EN $0$memwr$\mem$ls180.v:10160$8_EN[63:0]$2767 + end + attribute \src "ls180.v:1016.11-1016.38" + process $proc$ls180.v:1016$3249 + assign { } { } + assign $1\main_spimaster5_miso[7:0] 8'00000000 sync always sync init - update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] + update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] end - attribute \src "ls180.v:10353.1-10371.4" - process $proc$ls180.v:10353$2893 + attribute \src "ls180.v:10172.1-10190.4" + process $proc$ls180.v:10172$2769 assign { } { } assign { } { } assign { } { } @@ -284691,6050 +282322,5422 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2915 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2916 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2917 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2912 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2913 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2914 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2909 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2910 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2911 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2906 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2907 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2908 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2903 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2904 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2905 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2900 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2901 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2902 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2897 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2898 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2899 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2894 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2895 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2896 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr[5:0] \main_libresocsim_adr - attribute \src "ls180.v:10354.2-10355.65" - switch \main_libresocsim_we [0] - attribute \src "ls180.v:10354.6-10354.28" + assign $0$memwr$\mem_1$ls180.v:10188$16_ADDR[3:0]$2791 4'xxxx + assign $0$memwr$\mem_1$ls180.v:10188$16_DATA[63:0]$2792 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10188$16_EN[63:0]$2793 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10186$15_ADDR[3:0]$2788 4'xxxx + assign $0$memwr$\mem_1$ls180.v:10186$15_DATA[63:0]$2789 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10186$15_EN[63:0]$2790 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10184$14_ADDR[3:0]$2785 4'xxxx + assign $0$memwr$\mem_1$ls180.v:10184$14_DATA[63:0]$2786 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10184$14_EN[63:0]$2787 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10182$13_ADDR[3:0]$2782 4'xxxx + assign $0$memwr$\mem_1$ls180.v:10182$13_DATA[63:0]$2783 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10182$13_EN[63:0]$2784 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10180$12_ADDR[3:0]$2779 4'xxxx + assign $0$memwr$\mem_1$ls180.v:10180$12_DATA[63:0]$2780 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10180$12_EN[63:0]$2781 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10178$11_ADDR[3:0]$2776 4'xxxx + assign $0$memwr$\mem_1$ls180.v:10178$11_DATA[63:0]$2777 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10178$11_EN[63:0]$2778 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10176$10_ADDR[3:0]$2773 4'xxxx + assign $0$memwr$\mem_1$ls180.v:10176$10_DATA[63:0]$2774 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10176$10_EN[63:0]$2775 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10174$9_ADDR[3:0]$2770 4'xxxx + assign $0$memwr$\mem_1$ls180.v:10174$9_DATA[63:0]$2771 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10174$9_EN[63:0]$2772 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_1[3:0] \main_ram_adr + attribute \src "ls180.v:10173.2-10174.51" + switch \main_ram_we [0] + attribute \src "ls180.v:10173.6-10173.20" case 1'1 - assign $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2894 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2895 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } - assign $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2896 64'0000000000000000000000000000000000000000000000000000000011111111 + assign $0$memwr$\mem_1$ls180.v:10174$9_ADDR[3:0]$2770 \main_ram_adr + assign $0$memwr$\mem_1$ls180.v:10174$9_DATA[63:0]$2771 { 56'00000000000000000000000000000000000000000000000000000000 \main_ram_dat_w [7:0] } + assign $0$memwr$\mem_1$ls180.v:10174$9_EN[63:0]$2772 64'0000000000000000000000000000000000000000000000000000000011111111 case end - attribute \src "ls180.v:10356.2-10357.67" - switch \main_libresocsim_we [1] - attribute \src "ls180.v:10356.6-10356.28" + attribute \src "ls180.v:10175.2-10176.53" + switch \main_ram_we [1] + attribute \src "ls180.v:10175.6-10175.20" case 1'1 - assign $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2897 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2898 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2899 64'0000000000000000000000000000000000000000000000001111111100000000 + assign $0$memwr$\mem_1$ls180.v:10176$10_ADDR[3:0]$2773 \main_ram_adr + assign $0$memwr$\mem_1$ls180.v:10176$10_DATA[63:0]$2774 { 48'000000000000000000000000000000000000000000000000 \main_ram_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10176$10_EN[63:0]$2775 64'0000000000000000000000000000000000000000000000001111111100000000 case end - attribute \src "ls180.v:10358.2-10359.69" - switch \main_libresocsim_we [2] - attribute \src "ls180.v:10358.6-10358.28" + attribute \src "ls180.v:10177.2-10178.55" + switch \main_ram_we [2] + attribute \src "ls180.v:10177.6-10177.20" case 1'1 - assign $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2900 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2901 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2902 64'0000000000000000000000000000000000000000111111110000000000000000 + assign $0$memwr$\mem_1$ls180.v:10178$11_ADDR[3:0]$2776 \main_ram_adr + assign $0$memwr$\mem_1$ls180.v:10178$11_DATA[63:0]$2777 { 40'0000000000000000000000000000000000000000 \main_ram_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10178$11_EN[63:0]$2778 64'0000000000000000000000000000000000000000111111110000000000000000 case end - attribute \src "ls180.v:10360.2-10361.69" - switch \main_libresocsim_we [3] - attribute \src "ls180.v:10360.6-10360.28" + attribute \src "ls180.v:10179.2-10180.55" + switch \main_ram_we [3] + attribute \src "ls180.v:10179.6-10179.20" case 1'1 - assign $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2903 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2904 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2905 64'0000000000000000000000000000000011111111000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10180$12_ADDR[3:0]$2779 \main_ram_adr + assign $0$memwr$\mem_1$ls180.v:10180$12_DATA[63:0]$2780 { 32'00000000000000000000000000000000 \main_ram_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10180$12_EN[63:0]$2781 64'0000000000000000000000000000000011111111000000000000000000000000 case end - attribute \src "ls180.v:10362.2-10363.69" - switch \main_libresocsim_we [4] - attribute \src "ls180.v:10362.6-10362.28" + attribute \src "ls180.v:10181.2-10182.55" + switch \main_ram_we [4] + attribute \src "ls180.v:10181.6-10181.20" case 1'1 - assign $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2906 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2907 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2908 64'0000000000000000000000001111111100000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10182$13_ADDR[3:0]$2782 \main_ram_adr + assign $0$memwr$\mem_1$ls180.v:10182$13_DATA[63:0]$2783 { 24'000000000000000000000000 \main_ram_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10182$13_EN[63:0]$2784 64'0000000000000000000000001111111100000000000000000000000000000000 case end - attribute \src "ls180.v:10364.2-10365.69" - switch \main_libresocsim_we [5] - attribute \src "ls180.v:10364.6-10364.28" + attribute \src "ls180.v:10183.2-10184.55" + switch \main_ram_we [5] + attribute \src "ls180.v:10183.6-10183.20" case 1'1 - assign $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2909 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2910 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2911 64'0000000000000000111111110000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10184$14_ADDR[3:0]$2785 \main_ram_adr + assign $0$memwr$\mem_1$ls180.v:10184$14_DATA[63:0]$2786 { 16'0000000000000000 \main_ram_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10184$14_EN[63:0]$2787 64'0000000000000000111111110000000000000000000000000000000000000000 case end - attribute \src "ls180.v:10366.2-10367.69" - switch \main_libresocsim_we [6] - attribute \src "ls180.v:10366.6-10366.28" + attribute \src "ls180.v:10185.2-10186.55" + switch \main_ram_we [6] + attribute \src "ls180.v:10185.6-10185.20" case 1'1 - assign $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2912 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2913 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2914 64'0000000011111111000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10186$15_ADDR[3:0]$2788 \main_ram_adr + assign $0$memwr$\mem_1$ls180.v:10186$15_DATA[63:0]$2789 { 8'00000000 \main_ram_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10186$15_EN[63:0]$2790 64'0000000011111111000000000000000000000000000000000000000000000000 case end - attribute \src "ls180.v:10368.2-10369.69" - switch \main_libresocsim_we [7] - attribute \src "ls180.v:10368.6-10368.28" + attribute \src "ls180.v:10187.2-10188.55" + switch \main_ram_we [7] + attribute \src "ls180.v:10187.6-10187.20" case 1'1 - assign $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2915 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2916 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2917 64'1111111100000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10188$16_ADDR[3:0]$2791 \main_ram_adr + assign $0$memwr$\mem_1$ls180.v:10188$16_DATA[63:0]$2792 { \main_ram_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10188$16_EN[63:0]$2793 64'1111111100000000000000000000000000000000000000000000000000000000 case end sync posedge \sys_clk_1 - update \memadr $0\memadr[5:0] - update $memwr$\mem$ls180.v:10355$1_ADDR $0$memwr$\mem$ls180.v:10355$1_ADDR[5:0]$2894 - update $memwr$\mem$ls180.v:10355$1_DATA $0$memwr$\mem$ls180.v:10355$1_DATA[63:0]$2895 - update $memwr$\mem$ls180.v:10355$1_EN $0$memwr$\mem$ls180.v:10355$1_EN[63:0]$2896 - update $memwr$\mem$ls180.v:10357$2_ADDR $0$memwr$\mem$ls180.v:10357$2_ADDR[5:0]$2897 - update $memwr$\mem$ls180.v:10357$2_DATA $0$memwr$\mem$ls180.v:10357$2_DATA[63:0]$2898 - update $memwr$\mem$ls180.v:10357$2_EN $0$memwr$\mem$ls180.v:10357$2_EN[63:0]$2899 - update $memwr$\mem$ls180.v:10359$3_ADDR $0$memwr$\mem$ls180.v:10359$3_ADDR[5:0]$2900 - update $memwr$\mem$ls180.v:10359$3_DATA $0$memwr$\mem$ls180.v:10359$3_DATA[63:0]$2901 - update $memwr$\mem$ls180.v:10359$3_EN $0$memwr$\mem$ls180.v:10359$3_EN[63:0]$2902 - update $memwr$\mem$ls180.v:10361$4_ADDR $0$memwr$\mem$ls180.v:10361$4_ADDR[5:0]$2903 - update $memwr$\mem$ls180.v:10361$4_DATA $0$memwr$\mem$ls180.v:10361$4_DATA[63:0]$2904 - update $memwr$\mem$ls180.v:10361$4_EN $0$memwr$\mem$ls180.v:10361$4_EN[63:0]$2905 - update $memwr$\mem$ls180.v:10363$5_ADDR $0$memwr$\mem$ls180.v:10363$5_ADDR[5:0]$2906 - update $memwr$\mem$ls180.v:10363$5_DATA $0$memwr$\mem$ls180.v:10363$5_DATA[63:0]$2907 - update $memwr$\mem$ls180.v:10363$5_EN $0$memwr$\mem$ls180.v:10363$5_EN[63:0]$2908 - update $memwr$\mem$ls180.v:10365$6_ADDR $0$memwr$\mem$ls180.v:10365$6_ADDR[5:0]$2909 - update $memwr$\mem$ls180.v:10365$6_DATA $0$memwr$\mem$ls180.v:10365$6_DATA[63:0]$2910 - update $memwr$\mem$ls180.v:10365$6_EN $0$memwr$\mem$ls180.v:10365$6_EN[63:0]$2911 - update $memwr$\mem$ls180.v:10367$7_ADDR $0$memwr$\mem$ls180.v:10367$7_ADDR[5:0]$2912 - update $memwr$\mem$ls180.v:10367$7_DATA $0$memwr$\mem$ls180.v:10367$7_DATA[63:0]$2913 - update $memwr$\mem$ls180.v:10367$7_EN $0$memwr$\mem$ls180.v:10367$7_EN[63:0]$2914 - update $memwr$\mem$ls180.v:10369$8_ADDR $0$memwr$\mem$ls180.v:10369$8_ADDR[5:0]$2915 - update $memwr$\mem$ls180.v:10369$8_DATA $0$memwr$\mem$ls180.v:10369$8_DATA[63:0]$2916 - update $memwr$\mem$ls180.v:10369$8_EN $0$memwr$\mem$ls180.v:10369$8_EN[63:0]$2917 - end - attribute \src "ls180.v:10381.1-10399.4" - process $proc$ls180.v:10381$2919 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + update \memadr_1 $0\memadr_1[3:0] + update $memwr$\mem_1$ls180.v:10174$9_ADDR $0$memwr$\mem_1$ls180.v:10174$9_ADDR[3:0]$2770 + update $memwr$\mem_1$ls180.v:10174$9_DATA $0$memwr$\mem_1$ls180.v:10174$9_DATA[63:0]$2771 + update $memwr$\mem_1$ls180.v:10174$9_EN $0$memwr$\mem_1$ls180.v:10174$9_EN[63:0]$2772 + update $memwr$\mem_1$ls180.v:10176$10_ADDR $0$memwr$\mem_1$ls180.v:10176$10_ADDR[3:0]$2773 + update $memwr$\mem_1$ls180.v:10176$10_DATA $0$memwr$\mem_1$ls180.v:10176$10_DATA[63:0]$2774 + update $memwr$\mem_1$ls180.v:10176$10_EN $0$memwr$\mem_1$ls180.v:10176$10_EN[63:0]$2775 + update $memwr$\mem_1$ls180.v:10178$11_ADDR $0$memwr$\mem_1$ls180.v:10178$11_ADDR[3:0]$2776 + update $memwr$\mem_1$ls180.v:10178$11_DATA $0$memwr$\mem_1$ls180.v:10178$11_DATA[63:0]$2777 + update $memwr$\mem_1$ls180.v:10178$11_EN $0$memwr$\mem_1$ls180.v:10178$11_EN[63:0]$2778 + update $memwr$\mem_1$ls180.v:10180$12_ADDR $0$memwr$\mem_1$ls180.v:10180$12_ADDR[3:0]$2779 + update $memwr$\mem_1$ls180.v:10180$12_DATA $0$memwr$\mem_1$ls180.v:10180$12_DATA[63:0]$2780 + update $memwr$\mem_1$ls180.v:10180$12_EN $0$memwr$\mem_1$ls180.v:10180$12_EN[63:0]$2781 + update $memwr$\mem_1$ls180.v:10182$13_ADDR $0$memwr$\mem_1$ls180.v:10182$13_ADDR[3:0]$2782 + update $memwr$\mem_1$ls180.v:10182$13_DATA $0$memwr$\mem_1$ls180.v:10182$13_DATA[63:0]$2783 + update $memwr$\mem_1$ls180.v:10182$13_EN $0$memwr$\mem_1$ls180.v:10182$13_EN[63:0]$2784 + update $memwr$\mem_1$ls180.v:10184$14_ADDR $0$memwr$\mem_1$ls180.v:10184$14_ADDR[3:0]$2785 + update $memwr$\mem_1$ls180.v:10184$14_DATA $0$memwr$\mem_1$ls180.v:10184$14_DATA[63:0]$2786 + update $memwr$\mem_1$ls180.v:10184$14_EN $0$memwr$\mem_1$ls180.v:10184$14_EN[63:0]$2787 + update $memwr$\mem_1$ls180.v:10186$15_ADDR $0$memwr$\mem_1$ls180.v:10186$15_ADDR[3:0]$2788 + update $memwr$\mem_1$ls180.v:10186$15_DATA $0$memwr$\mem_1$ls180.v:10186$15_DATA[63:0]$2789 + update $memwr$\mem_1$ls180.v:10186$15_EN $0$memwr$\mem_1$ls180.v:10186$15_EN[63:0]$2790 + update $memwr$\mem_1$ls180.v:10188$16_ADDR $0$memwr$\mem_1$ls180.v:10188$16_ADDR[3:0]$2791 + update $memwr$\mem_1$ls180.v:10188$16_DATA $0$memwr$\mem_1$ls180.v:10188$16_DATA[63:0]$2792 + update $memwr$\mem_1$ls180.v:10188$16_EN $0$memwr$\mem_1$ls180.v:10188$16_EN[63:0]$2793 + end + attribute \src "ls180.v:1019.12-1019.47" + process $proc$ls180.v:1019$3250 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2941 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2942 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2943 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2938 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2939 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2940 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2935 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2936 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2937 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2932 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2933 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2934 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2929 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2930 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2931 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2926 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2927 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2928 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2923 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2924 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2925 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2920 6'xxxxxx - assign $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2921 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2922 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr_1[5:0] \main_sram0_adr - attribute \src "ls180.v:10382.2-10383.55" - switch \main_sram0_we [0] - attribute \src "ls180.v:10382.6-10382.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2920 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2921 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram0_dat_w [7:0] } - assign $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2922 64'0000000000000000000000000000000000000000000000000000000011111111 - case - end - attribute \src "ls180.v:10384.2-10385.57" - switch \main_sram0_we [1] - attribute \src "ls180.v:10384.6-10384.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2923 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2924 { 48'000000000000000000000000000000000000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2925 64'0000000000000000000000000000000000000000000000001111111100000000 - case - end - attribute \src "ls180.v:10386.2-10387.59" - switch \main_sram0_we [2] - attribute \src "ls180.v:10386.6-10386.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2926 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2927 { 40'0000000000000000000000000000000000000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2928 64'0000000000000000000000000000000000000000111111110000000000000000 - case - end - attribute \src "ls180.v:10388.2-10389.59" - switch \main_sram0_we [3] - attribute \src "ls180.v:10388.6-10388.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2929 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2930 { 32'00000000000000000000000000000000 \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2931 64'0000000000000000000000000000000011111111000000000000000000000000 - case - end - attribute \src "ls180.v:10390.2-10391.59" - switch \main_sram0_we [4] - attribute \src "ls180.v:10390.6-10390.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2932 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2933 { 24'000000000000000000000000 \main_sram0_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2934 64'0000000000000000000000001111111100000000000000000000000000000000 - case - end - attribute \src "ls180.v:10392.2-10393.59" - switch \main_sram0_we [5] - attribute \src "ls180.v:10392.6-10392.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2935 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2936 { 16'0000000000000000 \main_sram0_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2937 64'0000000000000000111111110000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10394.2-10395.59" - switch \main_sram0_we [6] - attribute \src "ls180.v:10394.6-10394.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2938 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2939 { 8'00000000 \main_sram0_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2940 64'0000000011111111000000000000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10396.2-10397.59" - switch \main_sram0_we [7] - attribute \src "ls180.v:10396.6-10396.22" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2941 \main_sram0_adr - assign $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2942 { \main_sram0_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2943 64'1111111100000000000000000000000000000000000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr_1 $0\memadr_1[5:0] - update $memwr$\mem_1$ls180.v:10383$9_ADDR $0$memwr$\mem_1$ls180.v:10383$9_ADDR[5:0]$2920 - update $memwr$\mem_1$ls180.v:10383$9_DATA $0$memwr$\mem_1$ls180.v:10383$9_DATA[63:0]$2921 - update $memwr$\mem_1$ls180.v:10383$9_EN $0$memwr$\mem_1$ls180.v:10383$9_EN[63:0]$2922 - update $memwr$\mem_1$ls180.v:10385$10_ADDR $0$memwr$\mem_1$ls180.v:10385$10_ADDR[5:0]$2923 - update $memwr$\mem_1$ls180.v:10385$10_DATA $0$memwr$\mem_1$ls180.v:10385$10_DATA[63:0]$2924 - update $memwr$\mem_1$ls180.v:10385$10_EN $0$memwr$\mem_1$ls180.v:10385$10_EN[63:0]$2925 - update $memwr$\mem_1$ls180.v:10387$11_ADDR $0$memwr$\mem_1$ls180.v:10387$11_ADDR[5:0]$2926 - update $memwr$\mem_1$ls180.v:10387$11_DATA $0$memwr$\mem_1$ls180.v:10387$11_DATA[63:0]$2927 - update $memwr$\mem_1$ls180.v:10387$11_EN $0$memwr$\mem_1$ls180.v:10387$11_EN[63:0]$2928 - update $memwr$\mem_1$ls180.v:10389$12_ADDR $0$memwr$\mem_1$ls180.v:10389$12_ADDR[5:0]$2929 - update $memwr$\mem_1$ls180.v:10389$12_DATA $0$memwr$\mem_1$ls180.v:10389$12_DATA[63:0]$2930 - update $memwr$\mem_1$ls180.v:10389$12_EN $0$memwr$\mem_1$ls180.v:10389$12_EN[63:0]$2931 - update $memwr$\mem_1$ls180.v:10391$13_ADDR $0$memwr$\mem_1$ls180.v:10391$13_ADDR[5:0]$2932 - update $memwr$\mem_1$ls180.v:10391$13_DATA $0$memwr$\mem_1$ls180.v:10391$13_DATA[63:0]$2933 - update $memwr$\mem_1$ls180.v:10391$13_EN $0$memwr$\mem_1$ls180.v:10391$13_EN[63:0]$2934 - update $memwr$\mem_1$ls180.v:10393$14_ADDR $0$memwr$\mem_1$ls180.v:10393$14_ADDR[5:0]$2935 - update $memwr$\mem_1$ls180.v:10393$14_DATA $0$memwr$\mem_1$ls180.v:10393$14_DATA[63:0]$2936 - update $memwr$\mem_1$ls180.v:10393$14_EN $0$memwr$\mem_1$ls180.v:10393$14_EN[63:0]$2937 - update $memwr$\mem_1$ls180.v:10395$15_ADDR $0$memwr$\mem_1$ls180.v:10395$15_ADDR[5:0]$2938 - update $memwr$\mem_1$ls180.v:10395$15_DATA $0$memwr$\mem_1$ls180.v:10395$15_DATA[63:0]$2939 - update $memwr$\mem_1$ls180.v:10395$15_EN $0$memwr$\mem_1$ls180.v:10395$15_EN[63:0]$2940 - update $memwr$\mem_1$ls180.v:10397$16_ADDR $0$memwr$\mem_1$ls180.v:10397$16_ADDR[5:0]$2941 - update $memwr$\mem_1$ls180.v:10397$16_DATA $0$memwr$\mem_1$ls180.v:10397$16_DATA[63:0]$2942 - update $memwr$\mem_1$ls180.v:10397$16_EN $0$memwr$\mem_1$ls180.v:10397$16_EN[63:0]$2943 - end - attribute \src "ls180.v:104.5-104.49" - process $proc$ls180.v:104$3149 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 + assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 sync always + update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0] sync init - update \main_libresocsim_libresoc_xics_ics_we $1\main_libresocsim_libresoc_xics_ics_we[0:0] end - attribute \src "ls180.v:10409.1-10427.4" - process $proc$ls180.v:10409$2945 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "ls180.v:102.5-102.50" + process $proc$ls180.v:102$2896 assign { } { } - assign $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2967 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2968 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2969 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2964 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2965 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2966 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2961 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2962 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2963 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2958 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2959 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2960 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2955 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2956 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2957 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2952 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2953 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2954 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2949 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2950 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2951 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2946 6'xxxxxx - assign $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2947 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2948 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr_2[5:0] \main_sram1_adr - attribute \src "ls180.v:10410.2-10411.55" - switch \main_sram1_we [0] - attribute \src "ls180.v:10410.6-10410.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2946 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2947 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram1_dat_w [7:0] } - assign $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2948 64'0000000000000000000000000000000000000000000000000000000011111111 - case - end - attribute \src "ls180.v:10412.2-10413.57" - switch \main_sram1_we [1] - attribute \src "ls180.v:10412.6-10412.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2949 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2950 { 48'000000000000000000000000000000000000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2951 64'0000000000000000000000000000000000000000000000001111111100000000 - case - end - attribute \src "ls180.v:10414.2-10415.59" - switch \main_sram1_we [2] - attribute \src "ls180.v:10414.6-10414.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2952 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2953 { 40'0000000000000000000000000000000000000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2954 64'0000000000000000000000000000000000000000111111110000000000000000 - case - end - attribute \src "ls180.v:10416.2-10417.59" - switch \main_sram1_we [3] - attribute \src "ls180.v:10416.6-10416.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2955 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2956 { 32'00000000000000000000000000000000 \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2957 64'0000000000000000000000000000000011111111000000000000000000000000 - case - end - attribute \src "ls180.v:10418.2-10419.59" - switch \main_sram1_we [4] - attribute \src "ls180.v:10418.6-10418.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2958 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2959 { 24'000000000000000000000000 \main_sram1_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2960 64'0000000000000000000000001111111100000000000000000000000000000000 - case - end - attribute \src "ls180.v:10420.2-10421.59" - switch \main_sram1_we [5] - attribute \src "ls180.v:10420.6-10420.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2961 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2962 { 16'0000000000000000 \main_sram1_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2963 64'0000000000000000111111110000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10422.2-10423.59" - switch \main_sram1_we [6] - attribute \src "ls180.v:10422.6-10422.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2964 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2965 { 8'00000000 \main_sram1_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2966 64'0000000011111111000000000000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10424.2-10425.59" - switch \main_sram1_we [7] - attribute \src "ls180.v:10424.6-10424.22" - case 1'1 - assign $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2967 \main_sram1_adr - assign $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2968 { \main_sram1_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2969 64'1111111100000000000000000000000000000000000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr_2 $0\memadr_2[5:0] - update $memwr$\mem_2$ls180.v:10411$17_ADDR $0$memwr$\mem_2$ls180.v:10411$17_ADDR[5:0]$2946 - update $memwr$\mem_2$ls180.v:10411$17_DATA $0$memwr$\mem_2$ls180.v:10411$17_DATA[63:0]$2947 - update $memwr$\mem_2$ls180.v:10411$17_EN $0$memwr$\mem_2$ls180.v:10411$17_EN[63:0]$2948 - update $memwr$\mem_2$ls180.v:10413$18_ADDR $0$memwr$\mem_2$ls180.v:10413$18_ADDR[5:0]$2949 - update $memwr$\mem_2$ls180.v:10413$18_DATA $0$memwr$\mem_2$ls180.v:10413$18_DATA[63:0]$2950 - update $memwr$\mem_2$ls180.v:10413$18_EN $0$memwr$\mem_2$ls180.v:10413$18_EN[63:0]$2951 - update $memwr$\mem_2$ls180.v:10415$19_ADDR $0$memwr$\mem_2$ls180.v:10415$19_ADDR[5:0]$2952 - update $memwr$\mem_2$ls180.v:10415$19_DATA $0$memwr$\mem_2$ls180.v:10415$19_DATA[63:0]$2953 - update $memwr$\mem_2$ls180.v:10415$19_EN $0$memwr$\mem_2$ls180.v:10415$19_EN[63:0]$2954 - update $memwr$\mem_2$ls180.v:10417$20_ADDR $0$memwr$\mem_2$ls180.v:10417$20_ADDR[5:0]$2955 - update $memwr$\mem_2$ls180.v:10417$20_DATA $0$memwr$\mem_2$ls180.v:10417$20_DATA[63:0]$2956 - update $memwr$\mem_2$ls180.v:10417$20_EN $0$memwr$\mem_2$ls180.v:10417$20_EN[63:0]$2957 - update $memwr$\mem_2$ls180.v:10419$21_ADDR $0$memwr$\mem_2$ls180.v:10419$21_ADDR[5:0]$2958 - update $memwr$\mem_2$ls180.v:10419$21_DATA $0$memwr$\mem_2$ls180.v:10419$21_DATA[63:0]$2959 - update $memwr$\mem_2$ls180.v:10419$21_EN $0$memwr$\mem_2$ls180.v:10419$21_EN[63:0]$2960 - update $memwr$\mem_2$ls180.v:10421$22_ADDR $0$memwr$\mem_2$ls180.v:10421$22_ADDR[5:0]$2961 - update $memwr$\mem_2$ls180.v:10421$22_DATA $0$memwr$\mem_2$ls180.v:10421$22_DATA[63:0]$2962 - update $memwr$\mem_2$ls180.v:10421$22_EN $0$memwr$\mem_2$ls180.v:10421$22_EN[63:0]$2963 - update $memwr$\mem_2$ls180.v:10423$23_ADDR $0$memwr$\mem_2$ls180.v:10423$23_ADDR[5:0]$2964 - update $memwr$\mem_2$ls180.v:10423$23_DATA $0$memwr$\mem_2$ls180.v:10423$23_DATA[63:0]$2965 - update $memwr$\mem_2$ls180.v:10423$23_EN $0$memwr$\mem_2$ls180.v:10423$23_EN[63:0]$2966 - update $memwr$\mem_2$ls180.v:10425$24_ADDR $0$memwr$\mem_2$ls180.v:10425$24_ADDR[5:0]$2967 - update $memwr$\mem_2$ls180.v:10425$24_DATA $0$memwr$\mem_2$ls180.v:10425$24_DATA[63:0]$2968 - update $memwr$\mem_2$ls180.v:10425$24_EN $0$memwr$\mem_2$ls180.v:10425$24_EN[63:0]$2969 + assign $1\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_stb $1\main_libresocsim_libresoc_xics_ics_stb[0:0] end - attribute \src "ls180.v:10437.1-10455.4" - process $proc$ls180.v:10437$2971 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "ls180.v:1020.5-1020.33" + process $proc$ls180.v:1020$3251 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2993 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2994 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2995 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2990 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2991 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2992 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2987 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2988 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2989 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2984 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2985 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2986 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2981 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2982 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2983 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2978 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2979 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2980 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2975 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2976 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2977 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2972 6'xxxxxx - assign $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2973 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2974 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr_3[5:0] \main_sram2_adr - attribute \src "ls180.v:10438.2-10439.55" - switch \main_sram2_we [0] - attribute \src "ls180.v:10438.6-10438.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2972 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2973 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram2_dat_w [7:0] } - assign $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2974 64'0000000000000000000000000000000000000000000000000000000011111111 - case - end - attribute \src "ls180.v:10440.2-10441.57" - switch \main_sram2_we [1] - attribute \src "ls180.v:10440.6-10440.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2975 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2976 { 48'000000000000000000000000000000000000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2977 64'0000000000000000000000000000000000000000000000001111111100000000 - case - end - attribute \src "ls180.v:10442.2-10443.59" - switch \main_sram2_we [2] - attribute \src "ls180.v:10442.6-10442.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2978 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2979 { 40'0000000000000000000000000000000000000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2980 64'0000000000000000000000000000000000000000111111110000000000000000 - case - end - attribute \src "ls180.v:10444.2-10445.59" - switch \main_sram2_we [3] - attribute \src "ls180.v:10444.6-10444.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2981 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2982 { 32'00000000000000000000000000000000 \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2983 64'0000000000000000000000000000000011111111000000000000000000000000 - case - end - attribute \src "ls180.v:10446.2-10447.59" - switch \main_sram2_we [4] - attribute \src "ls180.v:10446.6-10446.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2984 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2985 { 24'000000000000000000000000 \main_sram2_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2986 64'0000000000000000000000001111111100000000000000000000000000000000 - case - end - attribute \src "ls180.v:10448.2-10449.59" - switch \main_sram2_we [5] - attribute \src "ls180.v:10448.6-10448.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2987 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2988 { 16'0000000000000000 \main_sram2_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2989 64'0000000000000000111111110000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10450.2-10451.59" - switch \main_sram2_we [6] - attribute \src "ls180.v:10450.6-10450.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2990 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2991 { 8'00000000 \main_sram2_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2992 64'0000000011111111000000000000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10452.2-10453.59" - switch \main_sram2_we [7] - attribute \src "ls180.v:10452.6-10452.22" - case 1'1 - assign $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2993 \main_sram2_adr - assign $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2994 { \main_sram2_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2995 64'1111111100000000000000000000000000000000000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr_3 $0\memadr_3[5:0] - update $memwr$\mem_3$ls180.v:10439$25_ADDR $0$memwr$\mem_3$ls180.v:10439$25_ADDR[5:0]$2972 - update $memwr$\mem_3$ls180.v:10439$25_DATA $0$memwr$\mem_3$ls180.v:10439$25_DATA[63:0]$2973 - update $memwr$\mem_3$ls180.v:10439$25_EN $0$memwr$\mem_3$ls180.v:10439$25_EN[63:0]$2974 - update $memwr$\mem_3$ls180.v:10441$26_ADDR $0$memwr$\mem_3$ls180.v:10441$26_ADDR[5:0]$2975 - update $memwr$\mem_3$ls180.v:10441$26_DATA $0$memwr$\mem_3$ls180.v:10441$26_DATA[63:0]$2976 - update $memwr$\mem_3$ls180.v:10441$26_EN $0$memwr$\mem_3$ls180.v:10441$26_EN[63:0]$2977 - update $memwr$\mem_3$ls180.v:10443$27_ADDR $0$memwr$\mem_3$ls180.v:10443$27_ADDR[5:0]$2978 - update $memwr$\mem_3$ls180.v:10443$27_DATA $0$memwr$\mem_3$ls180.v:10443$27_DATA[63:0]$2979 - update $memwr$\mem_3$ls180.v:10443$27_EN $0$memwr$\mem_3$ls180.v:10443$27_EN[63:0]$2980 - update $memwr$\mem_3$ls180.v:10445$28_ADDR $0$memwr$\mem_3$ls180.v:10445$28_ADDR[5:0]$2981 - update $memwr$\mem_3$ls180.v:10445$28_DATA $0$memwr$\mem_3$ls180.v:10445$28_DATA[63:0]$2982 - update $memwr$\mem_3$ls180.v:10445$28_EN $0$memwr$\mem_3$ls180.v:10445$28_EN[63:0]$2983 - update $memwr$\mem_3$ls180.v:10447$29_ADDR $0$memwr$\mem_3$ls180.v:10447$29_ADDR[5:0]$2984 - update $memwr$\mem_3$ls180.v:10447$29_DATA $0$memwr$\mem_3$ls180.v:10447$29_DATA[63:0]$2985 - update $memwr$\mem_3$ls180.v:10447$29_EN $0$memwr$\mem_3$ls180.v:10447$29_EN[63:0]$2986 - update $memwr$\mem_3$ls180.v:10449$30_ADDR $0$memwr$\mem_3$ls180.v:10449$30_ADDR[5:0]$2987 - update $memwr$\mem_3$ls180.v:10449$30_DATA $0$memwr$\mem_3$ls180.v:10449$30_DATA[63:0]$2988 - update $memwr$\mem_3$ls180.v:10449$30_EN $0$memwr$\mem_3$ls180.v:10449$30_EN[63:0]$2989 - update $memwr$\mem_3$ls180.v:10451$31_ADDR $0$memwr$\mem_3$ls180.v:10451$31_ADDR[5:0]$2990 - update $memwr$\mem_3$ls180.v:10451$31_DATA $0$memwr$\mem_3$ls180.v:10451$31_DATA[63:0]$2991 - update $memwr$\mem_3$ls180.v:10451$31_EN $0$memwr$\mem_3$ls180.v:10451$31_EN[63:0]$2992 - update $memwr$\mem_3$ls180.v:10453$32_ADDR $0$memwr$\mem_3$ls180.v:10453$32_ADDR[5:0]$2993 - update $memwr$\mem_3$ls180.v:10453$32_DATA $0$memwr$\mem_3$ls180.v:10453$32_DATA[63:0]$2994 - update $memwr$\mem_3$ls180.v:10453$32_EN $0$memwr$\mem_3$ls180.v:10453$32_EN[63:0]$2995 + assign $1\main_spimaster9_start[0:0] 1'0 + sync always + sync init + update \main_spimaster9_start $1\main_spimaster9_start[0:0] end - attribute \src "ls180.v:10465.1-10483.4" - process $proc$ls180.v:10465$2997 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "ls180.v:10200.1-10204.4" + process $proc$ls180.v:10200$2795 assign { } { } assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3019 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3020 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3021 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3016 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3017 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3018 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3013 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3014 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3015 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3010 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3011 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3012 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3007 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3008 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3009 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3004 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3005 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3006 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$3001 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3002 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3003 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2998 6'xxxxxx - assign $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2999 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$3000 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr_4[5:0] \main_sram3_adr - attribute \src "ls180.v:10466.2-10467.55" - switch \main_sram3_we [0] - attribute \src "ls180.v:10466.6-10466.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2998 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2999 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram3_dat_w [7:0] } - assign $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$3000 64'0000000000000000000000000000000000000000000000000000000011111111 - case - end - attribute \src "ls180.v:10468.2-10469.57" - switch \main_sram3_we [1] - attribute \src "ls180.v:10468.6-10468.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$3001 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3002 { 48'000000000000000000000000000000000000000000000000 \main_sram3_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3003 64'0000000000000000000000000000000000000000000000001111111100000000 - case - end - attribute \src "ls180.v:10470.2-10471.59" - switch \main_sram3_we [2] - attribute \src "ls180.v:10470.6-10470.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3004 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3005 { 40'0000000000000000000000000000000000000000 \main_sram3_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3006 64'0000000000000000000000000000000000000000111111110000000000000000 - case - end - attribute \src "ls180.v:10472.2-10473.59" - switch \main_sram3_we [3] - attribute \src "ls180.v:10472.6-10472.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3007 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3008 { 32'00000000000000000000000000000000 \main_sram3_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3009 64'0000000000000000000000000000000011111111000000000000000000000000 - case - end - attribute \src "ls180.v:10474.2-10475.59" - switch \main_sram3_we [4] - attribute \src "ls180.v:10474.6-10474.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3010 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3011 { 24'000000000000000000000000 \main_sram3_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3012 64'0000000000000000000000001111111100000000000000000000000000000000 - case - end - attribute \src "ls180.v:10476.2-10477.59" - switch \main_sram3_we [5] - attribute \src "ls180.v:10476.6-10476.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3013 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3014 { 16'0000000000000000 \main_sram3_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3015 64'0000000000000000111111110000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10478.2-10479.59" - switch \main_sram3_we [6] - attribute \src "ls180.v:10478.6-10478.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3016 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3017 { 8'00000000 \main_sram3_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3018 64'0000000011111111000000000000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10480.2-10481.59" - switch \main_sram3_we [7] - attribute \src "ls180.v:10480.6-10480.22" - case 1'1 - assign $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3019 \main_sram3_adr - assign $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3020 { \main_sram3_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3021 64'1111111100000000000000000000000000000000000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr_4 $0\memadr_4[5:0] - update $memwr$\mem_4$ls180.v:10467$33_ADDR $0$memwr$\mem_4$ls180.v:10467$33_ADDR[5:0]$2998 - update $memwr$\mem_4$ls180.v:10467$33_DATA $0$memwr$\mem_4$ls180.v:10467$33_DATA[63:0]$2999 - update $memwr$\mem_4$ls180.v:10467$33_EN $0$memwr$\mem_4$ls180.v:10467$33_EN[63:0]$3000 - update $memwr$\mem_4$ls180.v:10469$34_ADDR $0$memwr$\mem_4$ls180.v:10469$34_ADDR[5:0]$3001 - update $memwr$\mem_4$ls180.v:10469$34_DATA $0$memwr$\mem_4$ls180.v:10469$34_DATA[63:0]$3002 - update $memwr$\mem_4$ls180.v:10469$34_EN $0$memwr$\mem_4$ls180.v:10469$34_EN[63:0]$3003 - update $memwr$\mem_4$ls180.v:10471$35_ADDR $0$memwr$\mem_4$ls180.v:10471$35_ADDR[5:0]$3004 - update $memwr$\mem_4$ls180.v:10471$35_DATA $0$memwr$\mem_4$ls180.v:10471$35_DATA[63:0]$3005 - update $memwr$\mem_4$ls180.v:10471$35_EN $0$memwr$\mem_4$ls180.v:10471$35_EN[63:0]$3006 - update $memwr$\mem_4$ls180.v:10473$36_ADDR $0$memwr$\mem_4$ls180.v:10473$36_ADDR[5:0]$3007 - update $memwr$\mem_4$ls180.v:10473$36_DATA $0$memwr$\mem_4$ls180.v:10473$36_DATA[63:0]$3008 - update $memwr$\mem_4$ls180.v:10473$36_EN $0$memwr$\mem_4$ls180.v:10473$36_EN[63:0]$3009 - update $memwr$\mem_4$ls180.v:10475$37_ADDR $0$memwr$\mem_4$ls180.v:10475$37_ADDR[5:0]$3010 - update $memwr$\mem_4$ls180.v:10475$37_DATA $0$memwr$\mem_4$ls180.v:10475$37_DATA[63:0]$3011 - update $memwr$\mem_4$ls180.v:10475$37_EN $0$memwr$\mem_4$ls180.v:10475$37_EN[63:0]$3012 - update $memwr$\mem_4$ls180.v:10477$38_ADDR $0$memwr$\mem_4$ls180.v:10477$38_ADDR[5:0]$3013 - update $memwr$\mem_4$ls180.v:10477$38_DATA $0$memwr$\mem_4$ls180.v:10477$38_DATA[63:0]$3014 - update $memwr$\mem_4$ls180.v:10477$38_EN $0$memwr$\mem_4$ls180.v:10477$38_EN[63:0]$3015 - update $memwr$\mem_4$ls180.v:10479$39_ADDR $0$memwr$\mem_4$ls180.v:10479$39_ADDR[5:0]$3016 - update $memwr$\mem_4$ls180.v:10479$39_DATA $0$memwr$\mem_4$ls180.v:10479$39_DATA[63:0]$3017 - update $memwr$\mem_4$ls180.v:10479$39_EN $0$memwr$\mem_4$ls180.v:10479$39_EN[63:0]$3018 - update $memwr$\mem_4$ls180.v:10481$40_ADDR $0$memwr$\mem_4$ls180.v:10481$40_ADDR[5:0]$3019 - update $memwr$\mem_4$ls180.v:10481$40_DATA $0$memwr$\mem_4$ls180.v:10481$40_DATA[63:0]$3020 - update $memwr$\mem_4$ls180.v:10481$40_EN $0$memwr$\mem_4$ls180.v:10481$40_EN[63:0]$3021 - end - attribute \src "ls180.v:10493.1-10497.4" - process $proc$ls180.v:10493$3023 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3024 3'xxx - assign $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3025 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3026 25'0000000000000000000000000 - assign $0\memdat[24:0] $memrd$\storage$ls180.v:10496$3027_DATA - attribute \src "ls180.v:10494.2-10495.129" + assign $0$memwr$\storage$ls180.v:10202$17_ADDR[2:0]$2796 3'xxx + assign $0$memwr$\storage$ls180.v:10202$17_DATA[24:0]$2797 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage$ls180.v:10202$17_EN[24:0]$2798 25'0000000000000000000000000 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:10203$2799_DATA + attribute \src "ls180.v:10201.2-10202.129" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10494.6-10494.60" + attribute \src "ls180.v:10201.6-10201.60" case 1'1 - assign $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3024 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3025 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3026 25'1111111111111111111111111 + assign $0$memwr$\storage$ls180.v:10202$17_ADDR[2:0]$2796 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage$ls180.v:10202$17_DATA[24:0]$2797 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage$ls180.v:10202$17_EN[24:0]$2798 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat $0\memdat[24:0] - update $memwr$\storage$ls180.v:10495$41_ADDR $0$memwr$\storage$ls180.v:10495$41_ADDR[2:0]$3024 - update $memwr$\storage$ls180.v:10495$41_DATA $0$memwr$\storage$ls180.v:10495$41_DATA[24:0]$3025 - update $memwr$\storage$ls180.v:10495$41_EN $0$memwr$\storage$ls180.v:10495$41_EN[24:0]$3026 + update $memwr$\storage$ls180.v:10202$17_ADDR $0$memwr$\storage$ls180.v:10202$17_ADDR[2:0]$2796 + update $memwr$\storage$ls180.v:10202$17_DATA $0$memwr$\storage$ls180.v:10202$17_DATA[24:0]$2797 + update $memwr$\storage$ls180.v:10202$17_EN $0$memwr$\storage$ls180.v:10202$17_EN[24:0]$2798 end - attribute \src "ls180.v:10499.1-10500.4" - process $proc$ls180.v:10499$3028 + attribute \src "ls180.v:10206.1-10207.4" + process $proc$ls180.v:10206$2800 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10507.1-10511.4" - process $proc$ls180.v:10507$3030 + attribute \src "ls180.v:10214.1-10218.4" + process $proc$ls180.v:10214$2802 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3031 3'xxx - assign $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3032 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3033 25'0000000000000000000000000 - assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10510$3034_DATA - attribute \src "ls180.v:10508.2-10509.131" + assign $0$memwr$\storage_1$ls180.v:10216$18_ADDR[2:0]$2803 3'xxx + assign $0$memwr$\storage_1$ls180.v:10216$18_DATA[24:0]$2804 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_1$ls180.v:10216$18_EN[24:0]$2805 25'0000000000000000000000000 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10217$2806_DATA + attribute \src "ls180.v:10215.2-10216.131" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10508.6-10508.60" + attribute \src "ls180.v:10215.6-10215.60" case 1'1 - assign $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3031 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3032 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3033 25'1111111111111111111111111 + assign $0$memwr$\storage_1$ls180.v:10216$18_ADDR[2:0]$2803 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_1$ls180.v:10216$18_DATA[24:0]$2804 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_1$ls180.v:10216$18_EN[24:0]$2805 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_1 $0\memdat_1[24:0] - update $memwr$\storage_1$ls180.v:10509$42_ADDR $0$memwr$\storage_1$ls180.v:10509$42_ADDR[2:0]$3031 - update $memwr$\storage_1$ls180.v:10509$42_DATA $0$memwr$\storage_1$ls180.v:10509$42_DATA[24:0]$3032 - update $memwr$\storage_1$ls180.v:10509$42_EN $0$memwr$\storage_1$ls180.v:10509$42_EN[24:0]$3033 + update $memwr$\storage_1$ls180.v:10216$18_ADDR $0$memwr$\storage_1$ls180.v:10216$18_ADDR[2:0]$2803 + update $memwr$\storage_1$ls180.v:10216$18_DATA $0$memwr$\storage_1$ls180.v:10216$18_DATA[24:0]$2804 + update $memwr$\storage_1$ls180.v:10216$18_EN $0$memwr$\storage_1$ls180.v:10216$18_EN[24:0]$2805 + end + attribute \src "ls180.v:1022.12-1022.44" + process $proc$ls180.v:1022$3252 + assign { } { } + assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] end - attribute \src "ls180.v:10513.1-10514.4" - process $proc$ls180.v:10513$3035 + attribute \src "ls180.v:10220.1-10221.4" + process $proc$ls180.v:10220$2807 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10521.1-10525.4" - process $proc$ls180.v:10521$3037 + attribute \src "ls180.v:10228.1-10232.4" + process $proc$ls180.v:10228$2809 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3038 3'xxx - assign $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3039 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3040 25'0000000000000000000000000 - assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10524$3041_DATA - attribute \src "ls180.v:10522.2-10523.131" + assign $0$memwr$\storage_2$ls180.v:10230$19_ADDR[2:0]$2810 3'xxx + assign $0$memwr$\storage_2$ls180.v:10230$19_DATA[24:0]$2811 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$ls180.v:10230$19_EN[24:0]$2812 25'0000000000000000000000000 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10231$2813_DATA + attribute \src "ls180.v:10229.2-10230.131" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10522.6-10522.60" + attribute \src "ls180.v:10229.6-10229.60" case 1'1 - assign $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3038 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3039 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3040 25'1111111111111111111111111 + assign $0$memwr$\storage_2$ls180.v:10230$19_ADDR[2:0]$2810 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$ls180.v:10230$19_DATA[24:0]$2811 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$ls180.v:10230$19_EN[24:0]$2812 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_2 $0\memdat_2[24:0] - update $memwr$\storage_2$ls180.v:10523$43_ADDR $0$memwr$\storage_2$ls180.v:10523$43_ADDR[2:0]$3038 - update $memwr$\storage_2$ls180.v:10523$43_DATA $0$memwr$\storage_2$ls180.v:10523$43_DATA[24:0]$3039 - update $memwr$\storage_2$ls180.v:10523$43_EN $0$memwr$\storage_2$ls180.v:10523$43_EN[24:0]$3040 + update $memwr$\storage_2$ls180.v:10230$19_ADDR $0$memwr$\storage_2$ls180.v:10230$19_ADDR[2:0]$2810 + update $memwr$\storage_2$ls180.v:10230$19_DATA $0$memwr$\storage_2$ls180.v:10230$19_DATA[24:0]$2811 + update $memwr$\storage_2$ls180.v:10230$19_EN $0$memwr$\storage_2$ls180.v:10230$19_EN[24:0]$2812 end - attribute \src "ls180.v:10527.1-10528.4" - process $proc$ls180.v:10527$3042 + attribute \src "ls180.v:1023.5-1023.31" + process $proc$ls180.v:1023$3253 + assign { } { } + assign $1\main_spimaster12_re[0:0] 1'0 + sync always + sync init + update \main_spimaster12_re $1\main_spimaster12_re[0:0] + end + attribute \src "ls180.v:10234.1-10235.4" + process $proc$ls180.v:10234$2814 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10535.1-10539.4" - process $proc$ls180.v:10535$3044 + attribute \src "ls180.v:10242.1-10246.4" + process $proc$ls180.v:10242$2816 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3045 3'xxx - assign $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3046 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3047 25'0000000000000000000000000 - assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10538$3048_DATA - attribute \src "ls180.v:10536.2-10537.131" + assign $0$memwr$\storage_3$ls180.v:10244$20_ADDR[2:0]$2817 3'xxx + assign $0$memwr$\storage_3$ls180.v:10244$20_DATA[24:0]$2818 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$ls180.v:10244$20_EN[24:0]$2819 25'0000000000000000000000000 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10245$2820_DATA + attribute \src "ls180.v:10243.2-10244.131" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10536.6-10536.60" + attribute \src "ls180.v:10243.6-10243.60" case 1'1 - assign $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3045 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3046 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3047 25'1111111111111111111111111 + assign $0$memwr$\storage_3$ls180.v:10244$20_ADDR[2:0]$2817 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$ls180.v:10244$20_DATA[24:0]$2818 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$ls180.v:10244$20_EN[24:0]$2819 25'1111111111111111111111111 case end sync posedge \sys_clk_1 update \memdat_3 $0\memdat_3[24:0] - update $memwr$\storage_3$ls180.v:10537$44_ADDR $0$memwr$\storage_3$ls180.v:10537$44_ADDR[2:0]$3045 - update $memwr$\storage_3$ls180.v:10537$44_DATA $0$memwr$\storage_3$ls180.v:10537$44_DATA[24:0]$3046 - update $memwr$\storage_3$ls180.v:10537$44_EN $0$memwr$\storage_3$ls180.v:10537$44_EN[24:0]$3047 + update $memwr$\storage_3$ls180.v:10244$20_ADDR $0$memwr$\storage_3$ls180.v:10244$20_ADDR[2:0]$2817 + update $memwr$\storage_3$ls180.v:10244$20_DATA $0$memwr$\storage_3$ls180.v:10244$20_DATA[24:0]$2818 + update $memwr$\storage_3$ls180.v:10244$20_EN $0$memwr$\storage_3$ls180.v:10244$20_EN[24:0]$2819 end - attribute \src "ls180.v:10541.1-10542.4" - process $proc$ls180.v:10541$3049 + attribute \src "ls180.v:10248.1-10249.4" + process $proc$ls180.v:10248$2821 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10550.1-10554.4" - process $proc$ls180.v:10550$3051 + attribute \src "ls180.v:10257.1-10261.4" + process $proc$ls180.v:10257$2823 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3052 4'xxxx - assign $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3053 10'xxxxxxxxxx - assign $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3054 10'0000000000 - assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10553$3055_DATA - attribute \src "ls180.v:10551.2-10552.77" + assign $0$memwr$\storage_4$ls180.v:10259$21_ADDR[3:0]$2824 4'xxxx + assign $0$memwr$\storage_4$ls180.v:10259$21_DATA[9:0]$2825 10'xxxxxxxxxx + assign $0$memwr$\storage_4$ls180.v:10259$21_EN[9:0]$2826 10'0000000000 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10260$2827_DATA + attribute \src "ls180.v:10258.2-10259.77" switch \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:10551.6-10551.33" + attribute \src "ls180.v:10258.6-10258.33" case 1'1 - assign $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3052 \main_uart_tx_fifo_wrport_adr - assign $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3053 \main_uart_tx_fifo_wrport_dat_w - assign $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3054 10'1111111111 + assign $0$memwr$\storage_4$ls180.v:10259$21_ADDR[3:0]$2824 \main_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage_4$ls180.v:10259$21_DATA[9:0]$2825 \main_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage_4$ls180.v:10259$21_EN[9:0]$2826 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_4 $0\memdat_4[9:0] - update $memwr$\storage_4$ls180.v:10552$45_ADDR $0$memwr$\storage_4$ls180.v:10552$45_ADDR[3:0]$3052 - update $memwr$\storage_4$ls180.v:10552$45_DATA $0$memwr$\storage_4$ls180.v:10552$45_DATA[9:0]$3053 - update $memwr$\storage_4$ls180.v:10552$45_EN $0$memwr$\storage_4$ls180.v:10552$45_EN[9:0]$3054 + update $memwr$\storage_4$ls180.v:10259$21_ADDR $0$memwr$\storage_4$ls180.v:10259$21_ADDR[3:0]$2824 + update $memwr$\storage_4$ls180.v:10259$21_DATA $0$memwr$\storage_4$ls180.v:10259$21_DATA[9:0]$2825 + update $memwr$\storage_4$ls180.v:10259$21_EN $0$memwr$\storage_4$ls180.v:10259$21_EN[9:0]$2826 end - attribute \src "ls180.v:10556.1-10559.4" - process $proc$ls180.v:10556$3056 + attribute \src "ls180.v:10263.1-10266.4" + process $proc$ls180.v:10263$2828 assign $0\memdat_5[9:0] \memdat_5 - attribute \src "ls180.v:10557.2-10558.55" + attribute \src "ls180.v:10264.2-10265.55" switch \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:10557.6-10557.33" + attribute \src "ls180.v:10264.6-10264.33" case 1'1 - assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10558$3057_DATA + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10265$2829_DATA case end sync posedge \sys_clk_1 update \memdat_5 $0\memdat_5[9:0] end - attribute \src "ls180.v:10567.1-10571.4" - process $proc$ls180.v:10567$3058 + attribute \src "ls180.v:1027.11-1027.42" + process $proc$ls180.v:1027$3254 + assign { } { } + assign $1\main_spimaster16_storage[7:0] 8'00000000 + sync always + sync init + update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] + end + attribute \src "ls180.v:10274.1-10278.4" + process $proc$ls180.v:10274$2830 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3059 4'xxxx - assign $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3060 10'xxxxxxxxxx - assign $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3061 10'0000000000 - assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10570$3062_DATA - attribute \src "ls180.v:10568.2-10569.77" + assign $0$memwr$\storage_5$ls180.v:10276$22_ADDR[3:0]$2831 4'xxxx + assign $0$memwr$\storage_5$ls180.v:10276$22_DATA[9:0]$2832 10'xxxxxxxxxx + assign $0$memwr$\storage_5$ls180.v:10276$22_EN[9:0]$2833 10'0000000000 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10277$2834_DATA + attribute \src "ls180.v:10275.2-10276.77" switch \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:10568.6-10568.33" + attribute \src "ls180.v:10275.6-10275.33" case 1'1 - assign $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3059 \main_uart_rx_fifo_wrport_adr - assign $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3060 \main_uart_rx_fifo_wrport_dat_w - assign $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3061 10'1111111111 + assign $0$memwr$\storage_5$ls180.v:10276$22_ADDR[3:0]$2831 \main_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_5$ls180.v:10276$22_DATA[9:0]$2832 \main_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_5$ls180.v:10276$22_EN[9:0]$2833 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_6 $0\memdat_6[9:0] - update $memwr$\storage_5$ls180.v:10569$46_ADDR $0$memwr$\storage_5$ls180.v:10569$46_ADDR[3:0]$3059 - update $memwr$\storage_5$ls180.v:10569$46_DATA $0$memwr$\storage_5$ls180.v:10569$46_DATA[9:0]$3060 - update $memwr$\storage_5$ls180.v:10569$46_EN $0$memwr$\storage_5$ls180.v:10569$46_EN[9:0]$3061 + update $memwr$\storage_5$ls180.v:10276$22_ADDR $0$memwr$\storage_5$ls180.v:10276$22_ADDR[3:0]$2831 + update $memwr$\storage_5$ls180.v:10276$22_DATA $0$memwr$\storage_5$ls180.v:10276$22_DATA[9:0]$2832 + update $memwr$\storage_5$ls180.v:10276$22_EN $0$memwr$\storage_5$ls180.v:10276$22_EN[9:0]$2833 end - attribute \src "ls180.v:10573.1-10576.4" - process $proc$ls180.v:10573$3063 + attribute \src "ls180.v:1028.5-1028.31" + process $proc$ls180.v:1028$3255 + assign { } { } + assign $1\main_spimaster17_re[0:0] 1'0 + sync always + sync init + update \main_spimaster17_re $1\main_spimaster17_re[0:0] + end + attribute \src "ls180.v:10280.1-10283.4" + process $proc$ls180.v:10280$2835 assign $0\memdat_7[9:0] \memdat_7 - attribute \src "ls180.v:10574.2-10575.55" + attribute \src "ls180.v:10281.2-10282.55" switch \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:10574.6-10574.33" + attribute \src "ls180.v:10281.6-10281.33" case 1'1 - assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10575$3064_DATA + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10282$2836_DATA case end sync posedge \sys_clk_1 update \memdat_7 $0\memdat_7[9:0] end - attribute \src "ls180.v:1058.5-1058.38" - process $proc$ls180.v:1058$3493 + attribute \src "ls180.v:10290.1-10294.4" + process $proc$ls180.v:10290$2837 assign { } { } - assign $1\main_uart_rx_fifo_readable[0:0] 1'0 - sync always - sync init - update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] - end - attribute \src "ls180.v:10583.1-10587.4" - process $proc$ls180.v:10583$3065 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3066 5'xxxxx - assign $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3067 10'xxxxxxxxxx - assign $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3068 10'0000000000 - assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10586$3069_DATA - attribute \src "ls180.v:10584.2-10585.85" + assign $0$memwr$\storage_6$ls180.v:10292$23_ADDR[4:0]$2838 5'xxxxx + assign $0$memwr$\storage_6$ls180.v:10292$23_DATA[9:0]$2839 10'xxxxxxxxxx + assign $0$memwr$\storage_6$ls180.v:10292$23_EN[9:0]$2840 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10293$2841_DATA + attribute \src "ls180.v:10291.2-10292.85" switch \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:10584.6-10584.37" + attribute \src "ls180.v:10291.6-10291.37" case 1'1 - assign $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3066 \main_sdblock2mem_fifo_wrport_adr - assign $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3067 \main_sdblock2mem_fifo_wrport_dat_w - assign $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3068 10'1111111111 + assign $0$memwr$\storage_6$ls180.v:10292$23_ADDR[4:0]$2838 \main_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$ls180.v:10292$23_DATA[9:0]$2839 \main_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$ls180.v:10292$23_EN[9:0]$2840 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_8 $0\memdat_8[9:0] - update $memwr$\storage_6$ls180.v:10585$47_ADDR $0$memwr$\storage_6$ls180.v:10585$47_ADDR[4:0]$3066 - update $memwr$\storage_6$ls180.v:10585$47_DATA $0$memwr$\storage_6$ls180.v:10585$47_DATA[9:0]$3067 - update $memwr$\storage_6$ls180.v:10585$47_EN $0$memwr$\storage_6$ls180.v:10585$47_EN[9:0]$3068 + update $memwr$\storage_6$ls180.v:10292$23_ADDR $0$memwr$\storage_6$ls180.v:10292$23_ADDR[4:0]$2838 + update $memwr$\storage_6$ls180.v:10292$23_DATA $0$memwr$\storage_6$ls180.v:10292$23_DATA[9:0]$2839 + update $memwr$\storage_6$ls180.v:10292$23_EN $0$memwr$\storage_6$ls180.v:10292$23_EN[9:0]$2840 end - attribute \src "ls180.v:10589.1-10590.4" - process $proc$ls180.v:10589$3070 + attribute \src "ls180.v:10296.1-10297.4" + process $proc$ls180.v:10296$2842 sync posedge \sys_clk_1 end - attribute \src "ls180.v:10597.1-10601.4" - process $proc$ls180.v:10597$3072 + attribute \src "ls180.v:10304.1-10308.4" + process $proc$ls180.v:10304$2844 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3073 5'xxxxx - assign $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3074 10'xxxxxxxxxx - assign $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3075 10'0000000000 - assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10600$3076_DATA - attribute \src "ls180.v:10598.2-10599.85" + assign $0$memwr$\storage_7$ls180.v:10306$24_ADDR[4:0]$2845 5'xxxxx + assign $0$memwr$\storage_7$ls180.v:10306$24_DATA[9:0]$2846 10'xxxxxxxxxx + assign $0$memwr$\storage_7$ls180.v:10306$24_EN[9:0]$2847 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10307$2848_DATA + attribute \src "ls180.v:10305.2-10306.85" switch \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:10598.6-10598.37" + attribute \src "ls180.v:10305.6-10305.37" case 1'1 - assign $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3073 \main_sdmem2block_fifo_wrport_adr - assign $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3074 \main_sdmem2block_fifo_wrport_dat_w - assign $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3075 10'1111111111 + assign $0$memwr$\storage_7$ls180.v:10306$24_ADDR[4:0]$2845 \main_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$ls180.v:10306$24_DATA[9:0]$2846 \main_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$ls180.v:10306$24_EN[9:0]$2847 10'1111111111 case end sync posedge \sys_clk_1 update \memdat_9 $0\memdat_9[9:0] - update $memwr$\storage_7$ls180.v:10599$48_ADDR $0$memwr$\storage_7$ls180.v:10599$48_ADDR[4:0]$3073 - update $memwr$\storage_7$ls180.v:10599$48_DATA $0$memwr$\storage_7$ls180.v:10599$48_DATA[9:0]$3074 - update $memwr$\storage_7$ls180.v:10599$48_EN $0$memwr$\storage_7$ls180.v:10599$48_EN[9:0]$3075 + update $memwr$\storage_7$ls180.v:10306$24_ADDR $0$memwr$\storage_7$ls180.v:10306$24_ADDR[4:0]$2845 + update $memwr$\storage_7$ls180.v:10306$24_DATA $0$memwr$\storage_7$ls180.v:10306$24_DATA[9:0]$2846 + update $memwr$\storage_7$ls180.v:10306$24_EN $0$memwr$\storage_7$ls180.v:10306$24_EN[9:0]$2847 end - attribute \src "ls180.v:10603.1-10604.4" - process $proc$ls180.v:10603$3077 + attribute \src "ls180.v:10310.1-10311.4" + process $proc$ls180.v:10310$2849 sync posedge \sys_clk_1 end - attribute \src "ls180.v:1065.11-1065.42" - process $proc$ls180.v:1065$3494 - assign { } { } - assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 - sync always - sync init - update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] - end - attribute \src "ls180.v:1066.5-1066.37" - process $proc$ls180.v:1066$3495 - assign { } { } - assign $0\main_uart_rx_fifo_replace[0:0] 1'0 - sync always - update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:1067.11-1067.43" - process $proc$ls180.v:1067$3496 - assign { } { } - assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] - end - attribute \src "ls180.v:1068.11-1068.43" - process $proc$ls180.v:1068$3497 - assign { } { } - assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] - end - attribute \src "ls180.v:1069.11-1069.46" - process $proc$ls180.v:1069$3498 - assign { } { } - assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:1084.5-1084.27" - process $proc$ls180.v:1084$3499 - assign { } { } - assign $0\main_uart_reset[0:0] 1'0 - sync always - update \main_uart_reset $0\main_uart_reset[0:0] - sync init - end - attribute \src "ls180.v:1085.12-1085.53" - process $proc$ls180.v:1085$3500 - assign { } { } - assign $0\main_gpiotristateasic0_oe_storage[15:0] 16'0000000000000000 - sync always - update \main_gpiotristateasic0_oe_storage $0\main_gpiotristateasic0_oe_storage[15:0] - sync init - end - attribute \src "ls180.v:1086.12-1086.49" - process $proc$ls180.v:1086$3501 - assign { } { } - assign $1\main_gpiotristateasic0_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpiotristateasic0_status $1\main_gpiotristateasic0_status[15:0] - end - attribute \src "ls180.v:1087.12-1087.54" - process $proc$ls180.v:1087$3502 - assign { } { } - assign $0\main_gpiotristateasic0_out_storage[15:0] 16'0000000000000000 - sync always - update \main_gpiotristateasic0_out_storage $0\main_gpiotristateasic0_out_storage[15:0] - sync init - end - attribute \src "ls180.v:1091.12-1091.53" - process $proc$ls180.v:1091$3503 - assign { } { } - assign $1\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpiotristateasic1_oe_storage $1\main_gpiotristateasic1_oe_storage[15:0] - end - attribute \src "ls180.v:1092.5-1092.40" - process $proc$ls180.v:1092$3504 - assign { } { } - assign $1\main_gpiotristateasic1_oe_re[0:0] 1'0 - sync always - sync init - update \main_gpiotristateasic1_oe_re $1\main_gpiotristateasic1_oe_re[0:0] - end - attribute \src "ls180.v:1093.12-1093.49" - process $proc$ls180.v:1093$3505 - assign { } { } - assign $1\main_gpiotristateasic1_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpiotristateasic1_status $1\main_gpiotristateasic1_status[15:0] - end - attribute \src "ls180.v:1095.12-1095.54" - process $proc$ls180.v:1095$3506 - assign { } { } - assign $1\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpiotristateasic1_out_storage $1\main_gpiotristateasic1_out_storage[15:0] - end - attribute \src "ls180.v:1096.5-1096.41" - process $proc$ls180.v:1096$3507 - assign { } { } - assign $1\main_gpiotristateasic1_out_re[0:0] 1'0 - sync always - sync init - update \main_gpiotristateasic1_out_re $1\main_gpiotristateasic1_out_re[0:0] - end - attribute \src "ls180.v:1102.5-1102.32" - process $proc$ls180.v:1102$3508 - assign { } { } - assign $1\main_spimaster2_done[0:0] 1'0 - sync always - sync init - update \main_spimaster2_done $1\main_spimaster2_done[0:0] - end - attribute \src "ls180.v:1103.5-1103.31" - process $proc$ls180.v:1103$3509 - assign { } { } - assign $1\main_spimaster3_irq[0:0] 1'0 - sync always - sync init - update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] - end - attribute \src "ls180.v:1105.11-1105.38" - process $proc$ls180.v:1105$3510 - assign { } { } - assign $1\main_spimaster5_miso[7:0] 8'00000000 - sync always - sync init - update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] - end - attribute \src "ls180.v:1108.12-1108.47" - process $proc$ls180.v:1108$3511 - assign { } { } - assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 - sync always - update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0] - sync init - end - attribute \src "ls180.v:1109.5-1109.33" - process $proc$ls180.v:1109$3512 - assign { } { } - assign $1\main_spimaster9_start[0:0] 1'0 - sync always - sync init - update \main_spimaster9_start $1\main_spimaster9_start[0:0] - end - attribute \src "ls180.v:1111.12-1111.44" - process $proc$ls180.v:1111$3513 - assign { } { } - assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] - end - attribute \src "ls180.v:1112.5-1112.31" - process $proc$ls180.v:1112$3514 - assign { } { } - assign $1\main_spimaster12_re[0:0] 1'0 - sync always - sync init - update \main_spimaster12_re $1\main_spimaster12_re[0:0] - end - attribute \src "ls180.v:1116.11-1116.42" - process $proc$ls180.v:1116$3515 - assign { } { } - assign $1\main_spimaster16_storage[7:0] 8'00000000 - sync always - sync init - update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] - end - attribute \src "ls180.v:1117.5-1117.31" - process $proc$ls180.v:1117$3516 - assign { } { } - assign $1\main_spimaster17_re[0:0] 1'0 - sync always - sync init - update \main_spimaster17_re $1\main_spimaster17_re[0:0] - end - attribute \src "ls180.v:1121.5-1121.36" - process $proc$ls180.v:1121$3517 + attribute \src "ls180.v:1032.5-1032.36" + process $proc$ls180.v:1032$3256 assign { } { } assign $1\main_spimaster21_storage[0:0] 1'1 sync always sync init update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] end - attribute \src "ls180.v:1122.5-1122.31" - process $proc$ls180.v:1122$3518 + attribute \src "ls180.v:1033.5-1033.31" + process $proc$ls180.v:1033$3257 assign { } { } assign $1\main_spimaster22_re[0:0] 1'0 sync always sync init update \main_spimaster22_re $1\main_spimaster22_re[0:0] end - attribute \src "ls180.v:1123.5-1123.36" - process $proc$ls180.v:1123$3519 + attribute \src "ls180.v:1034.5-1034.36" + process $proc$ls180.v:1034$3258 assign { } { } assign $1\main_spimaster23_storage[0:0] 1'0 sync always sync init update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] end - attribute \src "ls180.v:1124.5-1124.31" - process $proc$ls180.v:1124$3520 + attribute \src "ls180.v:1035.5-1035.31" + process $proc$ls180.v:1035$3259 assign { } { } assign $1\main_spimaster24_re[0:0] 1'0 sync always sync init update \main_spimaster24_re $1\main_spimaster24_re[0:0] end - attribute \src "ls180.v:1125.5-1125.39" - process $proc$ls180.v:1125$3521 + attribute \src "ls180.v:1036.5-1036.39" + process $proc$ls180.v:1036$3260 assign { } { } assign $1\main_spimaster25_clk_enable[0:0] 1'0 sync always sync init update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] end - attribute \src "ls180.v:1126.5-1126.38" - process $proc$ls180.v:1126$3522 + attribute \src "ls180.v:1037.5-1037.38" + process $proc$ls180.v:1037$3261 assign { } { } assign $1\main_spimaster26_cs_enable[0:0] 1'0 sync always sync init update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] end - attribute \src "ls180.v:1127.11-1127.40" - process $proc$ls180.v:1127$3523 + attribute \src "ls180.v:1038.11-1038.40" + process $proc$ls180.v:1038$3262 assign { } { } assign $1\main_spimaster27_count[2:0] 3'000 sync always sync init update \main_spimaster27_count $1\main_spimaster27_count[2:0] end - attribute \src "ls180.v:1128.5-1128.39" - process $proc$ls180.v:1128$3524 + attribute \src "ls180.v:1039.5-1039.39" + process $proc$ls180.v:1039$3263 assign { } { } assign $1\main_spimaster28_mosi_latch[0:0] 1'0 sync always sync init update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] end - attribute \src "ls180.v:1129.5-1129.39" - process $proc$ls180.v:1129$3525 + attribute \src "ls180.v:104.5-104.49" + process $proc$ls180.v:104$2897 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_we $1\main_libresocsim_libresoc_xics_ics_we[0:0] + end + attribute \src "ls180.v:1040.5-1040.39" + process $proc$ls180.v:1040$3264 assign { } { } assign $1\main_spimaster29_miso_latch[0:0] 1'0 sync always sync init update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0] end - attribute \src "ls180.v:1130.12-1130.48" - process $proc$ls180.v:1130$3526 + attribute \src "ls180.v:1041.12-1041.48" + process $proc$ls180.v:1041$3265 assign { } { } assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000 sync always sync init update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0] end - attribute \src "ls180.v:1133.11-1133.44" - process $proc$ls180.v:1133$3527 + attribute \src "ls180.v:1044.11-1044.44" + process $proc$ls180.v:1044$3266 assign { } { } assign $1\main_spimaster33_mosi_data[7:0] 8'00000000 sync always sync init update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0] end - attribute \src "ls180.v:1134.11-1134.43" - process $proc$ls180.v:1134$3528 + attribute \src "ls180.v:1045.11-1045.43" + process $proc$ls180.v:1045$3267 assign { } { } assign $1\main_spimaster34_mosi_sel[2:0] 3'000 sync always sync init update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0] end - attribute \src "ls180.v:1135.11-1135.44" - process $proc$ls180.v:1135$3529 + attribute \src "ls180.v:1046.11-1046.44" + process $proc$ls180.v:1046$3268 assign { } { } assign $1\main_spimaster35_miso_data[7:0] 8'00000000 sync always sync init update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0] end - attribute \src "ls180.v:1138.5-1138.32" - process $proc$ls180.v:1138$3530 + attribute \src "ls180.v:1049.5-1049.32" + process $proc$ls180.v:1049$3269 assign { } { } assign $1\main_spisdcard_done0[0:0] 1'0 sync always sync init update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0] end - attribute \src "ls180.v:1139.5-1139.30" - process $proc$ls180.v:1139$3531 + attribute \src "ls180.v:1050.5-1050.30" + process $proc$ls180.v:1050$3270 assign { } { } assign $1\main_spisdcard_irq[0:0] 1'0 sync always sync init update \main_spisdcard_irq $1\main_spisdcard_irq[0:0] end - attribute \src "ls180.v:114.11-114.55" - process $proc$ls180.v:114$3150 - assign { } { } - assign $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] 3'000 - sync always - update \main_libresocsim_libresoc_jtag_wb_cti $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] - sync init - end - attribute \src "ls180.v:1141.11-1141.37" - process $proc$ls180.v:1141$3532 + attribute \src "ls180.v:1052.11-1052.37" + process $proc$ls180.v:1052$3271 assign { } { } assign $1\main_spisdcard_miso[7:0] 8'00000000 sync always sync init update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] end - attribute \src "ls180.v:1145.5-1145.33" - process $proc$ls180.v:1145$3533 + attribute \src "ls180.v:1056.5-1056.33" + process $proc$ls180.v:1056$3272 assign { } { } assign $1\main_spisdcard_start1[0:0] 1'0 sync always sync init update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0] end - attribute \src "ls180.v:1147.12-1147.50" - process $proc$ls180.v:1147$3534 + attribute \src "ls180.v:1058.12-1058.50" + process $proc$ls180.v:1058$3273 assign { } { } assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000 sync always sync init update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0] end - attribute \src "ls180.v:1148.5-1148.37" - process $proc$ls180.v:1148$3535 + attribute \src "ls180.v:1059.5-1059.37" + process $proc$ls180.v:1059$3274 assign { } { } assign $1\main_spisdcard_control_re[0:0] 1'0 sync always sync init update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0] end - attribute \src "ls180.v:115.11-115.55" - process $proc$ls180.v:115$3151 - assign { } { } - assign $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] 2'00 - sync always - update \main_libresocsim_libresoc_jtag_wb_bte $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] - sync init - end - attribute \src "ls180.v:1152.11-1152.45" - process $proc$ls180.v:1152$3536 + attribute \src "ls180.v:1063.11-1063.45" + process $proc$ls180.v:1063$3275 assign { } { } assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 sync always sync init update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] end - attribute \src "ls180.v:1153.5-1153.34" - process $proc$ls180.v:1153$3537 + attribute \src "ls180.v:1064.5-1064.34" + process $proc$ls180.v:1064$3276 assign { } { } assign $1\main_spisdcard_mosi_re[0:0] 1'0 sync always sync init update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0] end - attribute \src "ls180.v:1157.5-1157.37" - process $proc$ls180.v:1157$3538 + attribute \src "ls180.v:1068.5-1068.37" + process $proc$ls180.v:1068$3277 assign { } { } assign $1\main_spisdcard_cs_storage[0:0] 1'1 sync always sync init update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0] end - attribute \src "ls180.v:1158.5-1158.32" - process $proc$ls180.v:1158$3539 + attribute \src "ls180.v:1069.5-1069.32" + process $proc$ls180.v:1069$3278 assign { } { } assign $1\main_spisdcard_cs_re[0:0] 1'0 sync always sync init update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0] end - attribute \src "ls180.v:1159.5-1159.43" - process $proc$ls180.v:1159$3540 + attribute \src "ls180.v:1070.5-1070.43" + process $proc$ls180.v:1070$3279 assign { } { } assign $1\main_spisdcard_loopback_storage[0:0] 1'0 sync always sync init update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0] end - attribute \src "ls180.v:1160.5-1160.38" - process $proc$ls180.v:1160$3541 + attribute \src "ls180.v:1071.5-1071.38" + process $proc$ls180.v:1071$3280 assign { } { } assign $1\main_spisdcard_loopback_re[0:0] 1'0 sync always sync init update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0] end - attribute \src "ls180.v:1161.5-1161.37" - process $proc$ls180.v:1161$3542 + attribute \src "ls180.v:1072.5-1072.37" + process $proc$ls180.v:1072$3281 assign { } { } assign $1\main_spisdcard_clk_enable[0:0] 1'0 sync always sync init update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0] end - attribute \src "ls180.v:1162.5-1162.36" - process $proc$ls180.v:1162$3543 + attribute \src "ls180.v:1073.5-1073.36" + process $proc$ls180.v:1073$3282 assign { } { } assign $1\main_spisdcard_cs_enable[0:0] 1'0 sync always sync init update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0] end - attribute \src "ls180.v:1163.11-1163.38" - process $proc$ls180.v:1163$3544 + attribute \src "ls180.v:1074.11-1074.38" + process $proc$ls180.v:1074$3283 assign { } { } assign $1\main_spisdcard_count[2:0] 3'000 sync always sync init update \main_spisdcard_count $1\main_spisdcard_count[2:0] end - attribute \src "ls180.v:1164.5-1164.37" - process $proc$ls180.v:1164$3545 + attribute \src "ls180.v:1075.5-1075.37" + process $proc$ls180.v:1075$3284 assign { } { } assign $1\main_spisdcard_mosi_latch[0:0] 1'0 sync always sync init update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0] end - attribute \src "ls180.v:1165.5-1165.37" - process $proc$ls180.v:1165$3546 + attribute \src "ls180.v:1076.5-1076.37" + process $proc$ls180.v:1076$3285 assign { } { } assign $1\main_spisdcard_miso_latch[0:0] 1'0 sync always sync init update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0] end - attribute \src "ls180.v:1166.12-1166.47" - process $proc$ls180.v:1166$3547 + attribute \src "ls180.v:1077.12-1077.47" + process $proc$ls180.v:1077$3286 assign { } { } assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 sync always sync init update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0] end - attribute \src "ls180.v:1169.11-1169.42" - process $proc$ls180.v:1169$3548 + attribute \src "ls180.v:1080.11-1080.42" + process $proc$ls180.v:1080$3287 assign { } { } assign $1\main_spisdcard_mosi_data[7:0] 8'00000000 sync always sync init update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0] end - attribute \src "ls180.v:1170.11-1170.41" - process $proc$ls180.v:1170$3549 + attribute \src "ls180.v:1081.11-1081.41" + process $proc$ls180.v:1081$3288 assign { } { } assign $1\main_spisdcard_mosi_sel[2:0] 3'000 sync always sync init update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0] end - attribute \src "ls180.v:1171.11-1171.42" - process $proc$ls180.v:1171$3550 + attribute \src "ls180.v:1082.11-1082.42" + process $proc$ls180.v:1082$3289 assign { } { } assign $1\main_spisdcard_miso_data[7:0] 8'00000000 sync always sync init update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0] end - attribute \src "ls180.v:1172.12-1172.45" - process $proc$ls180.v:1172$3551 + attribute \src "ls180.v:1083.12-1083.45" + process $proc$ls180.v:1083$3290 assign { } { } assign $1\main_spimaster1_storage[15:0] 16'0000000001111101 sync always sync init update \main_spimaster1_storage $1\main_spimaster1_storage[15:0] end - attribute \src "ls180.v:1173.5-1173.30" - process $proc$ls180.v:1173$3552 + attribute \src "ls180.v:1084.5-1084.30" + process $proc$ls180.v:1084$3291 assign { } { } assign $1\main_spimaster1_re[0:0] 1'0 sync always sync init update \main_spimaster1_re $1\main_spimaster1_re[0:0] end - attribute \src "ls180.v:1175.12-1175.30" - process $proc$ls180.v:1175$3553 + attribute \src "ls180.v:1086.12-1086.30" + process $proc$ls180.v:1086$3292 assign { } { } assign $1\main_dummy[23:0] 24'000000000000000000000000 sync always sync init update \main_dummy $1\main_dummy[23:0] end - attribute \src "ls180.v:1179.12-1179.37" - process $proc$ls180.v:1179$3554 + attribute \src "ls180.v:1090.12-1090.37" + process $proc$ls180.v:1090$3293 assign { } { } assign $1\main_pwm0_counter[31:0] 0 sync always sync init update \main_pwm0_counter $1\main_pwm0_counter[31:0] end - attribute \src "ls180.v:1180.5-1180.36" - process $proc$ls180.v:1180$3555 + attribute \src "ls180.v:1091.5-1091.36" + process $proc$ls180.v:1091$3294 assign { } { } assign $1\main_pwm0_enable_storage[0:0] 1'0 sync always sync init update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] end - attribute \src "ls180.v:1181.5-1181.31" - process $proc$ls180.v:1181$3556 + attribute \src "ls180.v:1092.5-1092.31" + process $proc$ls180.v:1092$3295 assign { } { } assign $1\main_pwm0_enable_re[0:0] 1'0 sync always sync init update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] end - attribute \src "ls180.v:1182.12-1182.43" - process $proc$ls180.v:1182$3557 + attribute \src "ls180.v:1093.12-1093.43" + process $proc$ls180.v:1093$3296 assign { } { } assign $1\main_pwm0_width_storage[31:0] 0 sync always sync init update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] end - attribute \src "ls180.v:1183.5-1183.30" - process $proc$ls180.v:1183$3558 + attribute \src "ls180.v:1094.5-1094.30" + process $proc$ls180.v:1094$3297 assign { } { } assign $1\main_pwm0_width_re[0:0] 1'0 sync always sync init update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] end - attribute \src "ls180.v:1184.12-1184.44" - process $proc$ls180.v:1184$3559 + attribute \src "ls180.v:1095.12-1095.44" + process $proc$ls180.v:1095$3298 assign { } { } assign $1\main_pwm0_period_storage[31:0] 0 sync always sync init update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] end - attribute \src "ls180.v:1185.5-1185.31" - process $proc$ls180.v:1185$3560 + attribute \src "ls180.v:1096.5-1096.31" + process $proc$ls180.v:1096$3299 assign { } { } assign $1\main_pwm0_period_re[0:0] 1'0 sync always sync init update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] end - attribute \src "ls180.v:1189.12-1189.37" - process $proc$ls180.v:1189$3561 + attribute \src "ls180.v:1100.12-1100.37" + process $proc$ls180.v:1100$3300 assign { } { } assign $1\main_pwm1_counter[31:0] 0 sync always sync init update \main_pwm1_counter $1\main_pwm1_counter[31:0] end - attribute \src "ls180.v:1190.5-1190.36" - process $proc$ls180.v:1190$3562 + attribute \src "ls180.v:1101.5-1101.36" + process $proc$ls180.v:1101$3301 assign { } { } assign $1\main_pwm1_enable_storage[0:0] 1'0 sync always sync init update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] end - attribute \src "ls180.v:1191.5-1191.31" - process $proc$ls180.v:1191$3563 + attribute \src "ls180.v:1102.5-1102.31" + process $proc$ls180.v:1102$3302 assign { } { } assign $1\main_pwm1_enable_re[0:0] 1'0 sync always sync init update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] end - attribute \src "ls180.v:1192.12-1192.43" - process $proc$ls180.v:1192$3564 + attribute \src "ls180.v:1103.12-1103.43" + process $proc$ls180.v:1103$3303 assign { } { } assign $1\main_pwm1_width_storage[31:0] 0 sync always sync init update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] end - attribute \src "ls180.v:1193.5-1193.30" - process $proc$ls180.v:1193$3565 + attribute \src "ls180.v:1104.5-1104.30" + process $proc$ls180.v:1104$3304 assign { } { } assign $1\main_pwm1_width_re[0:0] 1'0 sync always sync init update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] end - attribute \src "ls180.v:1194.12-1194.44" - process $proc$ls180.v:1194$3566 + attribute \src "ls180.v:1105.12-1105.44" + process $proc$ls180.v:1105$3305 assign { } { } assign $1\main_pwm1_period_storage[31:0] 0 sync always sync init update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] end - attribute \src "ls180.v:1195.5-1195.31" - process $proc$ls180.v:1195$3567 + attribute \src "ls180.v:1106.5-1106.31" + process $proc$ls180.v:1106$3306 assign { } { } assign $1\main_pwm1_period_re[0:0] 1'0 sync always sync init update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] end - attribute \src "ls180.v:1199.11-1199.34" - process $proc$ls180.v:1199$3568 + attribute \src "ls180.v:1110.11-1110.34" + process $proc$ls180.v:1110$3307 assign { } { } assign $1\main_i2c_storage[2:0] 3'000 sync always sync init update \main_i2c_storage $1\main_i2c_storage[2:0] end - attribute \src "ls180.v:1200.5-1200.23" - process $proc$ls180.v:1200$3569 + attribute \src "ls180.v:1111.5-1111.23" + process $proc$ls180.v:1111$3308 assign { } { } assign $1\main_i2c_re[0:0] 1'0 sync always sync init update \main_i2c_re $1\main_i2c_re[0:0] end - attribute \src "ls180.v:1206.11-1206.46" - process $proc$ls180.v:1206$3570 + attribute \src "ls180.v:1117.11-1117.46" + process $proc$ls180.v:1117$3309 assign { } { } assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 sync always sync init update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] end - attribute \src "ls180.v:1207.5-1207.33" - process $proc$ls180.v:1207$3571 + attribute \src "ls180.v:1118.5-1118.33" + process $proc$ls180.v:1118$3310 assign { } { } assign $1\main_sdphy_clocker_re[0:0] 1'0 sync always sync init update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] end - attribute \src "ls180.v:1209.5-1209.35" - process $proc$ls180.v:1209$3572 + attribute \src "ls180.v:1120.5-1120.35" + process $proc$ls180.v:1120$3311 assign { } { } assign $1\main_sdphy_clocker_clk0[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] end - attribute \src "ls180.v:1211.11-1211.41" - process $proc$ls180.v:1211$3573 + attribute \src "ls180.v:1122.11-1122.41" + process $proc$ls180.v:1122$3312 assign { } { } assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 sync always sync init update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] end - attribute \src "ls180.v:1212.5-1212.35" - process $proc$ls180.v:1212$3574 + attribute \src "ls180.v:1123.5-1123.35" + process $proc$ls180.v:1123$3313 assign { } { } assign $1\main_sdphy_clocker_clk1[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] end - attribute \src "ls180.v:1213.5-1213.36" - process $proc$ls180.v:1213$3575 + attribute \src "ls180.v:1124.5-1124.36" + process $proc$ls180.v:1124$3314 assign { } { } assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 sync always sync init update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] end - attribute \src "ls180.v:1217.5-1217.40" - process $proc$ls180.v:1217$3576 + attribute \src "ls180.v:1128.5-1128.40" + process $proc$ls180.v:1128$3315 assign { } { } assign $0\main_sdphy_init_initialize_w[0:0] 1'0 sync always update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] sync init end - attribute \src "ls180.v:1222.5-1222.48" - process $proc$ls180.v:1222$3577 + attribute \src "ls180.v:1133.5-1133.48" + process $proc$ls180.v:1133$3316 assign { } { } assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1223.5-1223.50" - process $proc$ls180.v:1223$3578 + attribute \src "ls180.v:1134.5-1134.50" + process $proc$ls180.v:1134$3317 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1224.5-1224.51" - process $proc$ls180.v:1224$3579 + attribute \src "ls180.v:1135.5-1135.51" + process $proc$ls180.v:1135$3318 assign { } { } assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1225.11-1225.57" - process $proc$ls180.v:1225$3580 + attribute \src "ls180.v:1136.11-1136.57" + process $proc$ls180.v:1136$3319 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 sync always sync init update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] end - attribute \src "ls180.v:1226.5-1226.52" - process $proc$ls180.v:1226$3581 + attribute \src "ls180.v:1137.5-1137.52" + process $proc$ls180.v:1137$3320 assign { } { } assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 sync always sync init update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] end - attribute \src "ls180.v:1227.11-1227.39" - process $proc$ls180.v:1227$3582 + attribute \src "ls180.v:1138.11-1138.39" + process $proc$ls180.v:1138$3321 assign { } { } assign $1\main_sdphy_init_count[7:0] 8'00000000 sync always sync init update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] end - attribute \src "ls180.v:1232.5-1232.48" - process $proc$ls180.v:1232$3583 + attribute \src "ls180.v:114.11-114.55" + process $proc$ls180.v:114$2898 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] 3'000 + sync always + update \main_libresocsim_libresoc_jtag_wb_cti $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] + sync init + end + attribute \src "ls180.v:1143.5-1143.48" + process $proc$ls180.v:1143$3322 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1233.5-1233.50" - process $proc$ls180.v:1233$3584 + attribute \src "ls180.v:1144.5-1144.50" + process $proc$ls180.v:1144$3323 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1234.5-1234.51" - process $proc$ls180.v:1234$3585 + attribute \src "ls180.v:1145.5-1145.51" + process $proc$ls180.v:1145$3324 assign { } { } assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1235.11-1235.57" - process $proc$ls180.v:1235$3586 + attribute \src "ls180.v:1146.11-1146.57" + process $proc$ls180.v:1146$3325 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1236.5-1236.52" - process $proc$ls180.v:1236$3587 + attribute \src "ls180.v:1147.5-1147.52" + process $proc$ls180.v:1147$3326 assign { } { } assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1237.5-1237.38" - process $proc$ls180.v:1237$3588 + attribute \src "ls180.v:1148.5-1148.38" + process $proc$ls180.v:1148$3327 assign { } { } assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] end - attribute \src "ls180.v:1238.5-1238.38" - process $proc$ls180.v:1238$3589 + attribute \src "ls180.v:1149.5-1149.38" + process $proc$ls180.v:1149$3328 assign { } { } assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] end - attribute \src "ls180.v:1239.5-1239.37" - process $proc$ls180.v:1239$3590 + attribute \src "ls180.v:115.11-115.55" + process $proc$ls180.v:115$2899 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] 2'00 + sync always + update \main_libresocsim_libresoc_jtag_wb_bte $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] + sync init + end + attribute \src "ls180.v:1150.5-1150.37" + process $proc$ls180.v:1150$3329 assign { } { } assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] end - attribute \src "ls180.v:1240.11-1240.51" - process $proc$ls180.v:1240$3591 + attribute \src "ls180.v:1151.11-1151.51" + process $proc$ls180.v:1151$3330 assign { } { } assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] end - attribute \src "ls180.v:1241.5-1241.32" - process $proc$ls180.v:1241$3592 + attribute \src "ls180.v:1152.5-1152.32" + process $proc$ls180.v:1152$3331 assign { } { } assign $1\main_sdphy_cmdw_done[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] end - attribute \src "ls180.v:1242.11-1242.39" - process $proc$ls180.v:1242$3593 + attribute \src "ls180.v:1153.11-1153.39" + process $proc$ls180.v:1153$3332 assign { } { } assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] end - attribute \src "ls180.v:1245.5-1245.49" - process $proc$ls180.v:1245$3594 + attribute \src "ls180.v:1156.5-1156.49" + process $proc$ls180.v:1156$3333 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1246.5-1246.48" - process $proc$ls180.v:1246$3595 + attribute \src "ls180.v:1157.5-1157.48" + process $proc$ls180.v:1157$3334 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1247.5-1247.55" - process $proc$ls180.v:1247$3596 + attribute \src "ls180.v:1158.5-1158.55" + process $proc$ls180.v:1158$3335 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1249.5-1249.57" - process $proc$ls180.v:1249$3597 + attribute \src "ls180.v:1160.5-1160.57" + process $proc$ls180.v:1160$3336 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1250.5-1250.58" - process $proc$ls180.v:1250$3598 + attribute \src "ls180.v:1161.5-1161.58" + process $proc$ls180.v:1161$3337 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1252.11-1252.64" - process $proc$ls180.v:1252$3599 + attribute \src "ls180.v:1163.11-1163.64" + process $proc$ls180.v:1163$3338 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1253.5-1253.59" - process $proc$ls180.v:1253$3600 + attribute \src "ls180.v:1164.5-1164.59" + process $proc$ls180.v:1164$3339 assign { } { } assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1255.5-1255.48" - process $proc$ls180.v:1255$3601 + attribute \src "ls180.v:1166.5-1166.48" + process $proc$ls180.v:1166$3340 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1256.5-1256.50" - process $proc$ls180.v:1256$3602 + attribute \src "ls180.v:1167.5-1167.50" + process $proc$ls180.v:1167$3341 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] end - attribute \src "ls180.v:1257.5-1257.51" - process $proc$ls180.v:1257$3603 + attribute \src "ls180.v:1168.5-1168.51" + process $proc$ls180.v:1168$3342 assign { } { } assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] end - attribute \src "ls180.v:1258.11-1258.57" - process $proc$ls180.v:1258$3604 + attribute \src "ls180.v:1169.11-1169.57" + process $proc$ls180.v:1169$3343 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1259.5-1259.52" - process $proc$ls180.v:1259$3605 + attribute \src "ls180.v:1170.5-1170.52" + process $proc$ls180.v:1170$3344 assign { } { } assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1260.5-1260.38" - process $proc$ls180.v:1260$3606 + attribute \src "ls180.v:1171.5-1171.38" + process $proc$ls180.v:1171$3345 assign { } { } assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] end - attribute \src "ls180.v:1261.5-1261.38" - process $proc$ls180.v:1261$3607 + attribute \src "ls180.v:1172.5-1172.38" + process $proc$ls180.v:1172$3346 assign { } { } assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] end - attribute \src "ls180.v:1262.5-1262.37" - process $proc$ls180.v:1262$3608 + attribute \src "ls180.v:1173.5-1173.37" + process $proc$ls180.v:1173$3347 assign { } { } assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] end - attribute \src "ls180.v:1263.11-1263.53" - process $proc$ls180.v:1263$3609 + attribute \src "ls180.v:1174.11-1174.53" + process $proc$ls180.v:1174$3348 assign { } { } assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] end - attribute \src "ls180.v:1264.5-1264.40" - process $proc$ls180.v:1264$3610 + attribute \src "ls180.v:1175.5-1175.40" + process $proc$ls180.v:1175$3349 assign { } { } assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] end - attribute \src "ls180.v:1265.5-1265.40" - process $proc$ls180.v:1265$3611 + attribute \src "ls180.v:1176.5-1176.40" + process $proc$ls180.v:1176$3350 assign { } { } assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] end - attribute \src "ls180.v:1266.5-1266.39" - process $proc$ls180.v:1266$3612 + attribute \src "ls180.v:1177.5-1177.39" + process $proc$ls180.v:1177$3351 assign { } { } assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] end - attribute \src "ls180.v:1267.11-1267.53" - process $proc$ls180.v:1267$3613 + attribute \src "ls180.v:1178.11-1178.53" + process $proc$ls180.v:1178$3352 assign { } { } assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] end - attribute \src "ls180.v:1268.11-1268.55" - process $proc$ls180.v:1268$3614 + attribute \src "ls180.v:1179.11-1179.55" + process $proc$ls180.v:1179$3353 assign { } { } assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 sync always sync init update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] end - attribute \src "ls180.v:1269.12-1269.48" - process $proc$ls180.v:1269$3615 + attribute \src "ls180.v:1180.12-1180.48" + process $proc$ls180.v:1180$3354 assign { } { } assign $1\main_sdphy_cmdr_timeout[31:0] 500000 sync always sync init update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] end - attribute \src "ls180.v:1270.11-1270.39" - process $proc$ls180.v:1270$3616 + attribute \src "ls180.v:1181.11-1181.39" + process $proc$ls180.v:1181$3355 assign { } { } assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] end - attribute \src "ls180.v:1272.5-1272.46" - process $proc$ls180.v:1272$3617 + attribute \src "ls180.v:1183.5-1183.46" + process $proc$ls180.v:1183$3356 assign { } { } assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1283.5-1283.53" - process $proc$ls180.v:1283$3618 + attribute \src "ls180.v:1194.5-1194.53" + process $proc$ls180.v:1194$3357 assign { } { } assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] end - attribute \src "ls180.v:1288.5-1288.36" - process $proc$ls180.v:1288$3619 + attribute \src "ls180.v:1199.5-1199.36" + process $proc$ls180.v:1199$3358 assign { } { } assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] end - attribute \src "ls180.v:1291.5-1291.53" - process $proc$ls180.v:1291$3620 + attribute \src "ls180.v:1202.5-1202.53" + process $proc$ls180.v:1202$3359 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1292.5-1292.52" - process $proc$ls180.v:1292$3621 + attribute \src "ls180.v:1203.5-1203.52" + process $proc$ls180.v:1203$3360 assign { } { } assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1296.5-1296.55" - process $proc$ls180.v:1296$3622 + attribute \src "ls180.v:1207.5-1207.55" + process $proc$ls180.v:1207$3361 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] end - attribute \src "ls180.v:1297.5-1297.54" - process $proc$ls180.v:1297$3623 + attribute \src "ls180.v:1208.5-1208.54" + process $proc$ls180.v:1208$3362 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] end - attribute \src "ls180.v:1298.11-1298.68" - process $proc$ls180.v:1298$3624 + attribute \src "ls180.v:1209.11-1209.68" + process $proc$ls180.v:1209$3363 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1299.11-1299.81" - process $proc$ls180.v:1299$3625 + attribute \src "ls180.v:1210.11-1210.81" + process $proc$ls180.v:1210$3364 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1300.11-1300.54" - process $proc$ls180.v:1300$3626 + attribute \src "ls180.v:1211.11-1211.54" + process $proc$ls180.v:1211$3365 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 sync always sync init update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] end - attribute \src "ls180.v:1302.5-1302.53" - process $proc$ls180.v:1302$3627 + attribute \src "ls180.v:1213.5-1213.53" + process $proc$ls180.v:1213$3366 assign { } { } assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] end - attribute \src "ls180.v:1313.5-1313.49" - process $proc$ls180.v:1313$3628 + attribute \src "ls180.v:1224.5-1224.49" + process $proc$ls180.v:1224$3367 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] end - attribute \src "ls180.v:1315.5-1315.49" - process $proc$ls180.v:1315$3629 + attribute \src "ls180.v:1226.5-1226.49" + process $proc$ls180.v:1226$3368 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] end - attribute \src "ls180.v:1316.5-1316.48" - process $proc$ls180.v:1316$3630 + attribute \src "ls180.v:1227.5-1227.48" + process $proc$ls180.v:1227$3369 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] end - attribute \src "ls180.v:1317.11-1317.62" - process $proc$ls180.v:1317$3631 + attribute \src "ls180.v:1228.11-1228.62" + process $proc$ls180.v:1228$3370 assign { } { } assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1318.5-1318.38" - process $proc$ls180.v:1318$3632 + attribute \src "ls180.v:1229.5-1229.38" + process $proc$ls180.v:1229$3371 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] end - attribute \src "ls180.v:1323.5-1323.49" - process $proc$ls180.v:1323$3633 + attribute \src "ls180.v:1234.5-1234.49" + process $proc$ls180.v:1234$3372 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1324.5-1324.51" - process $proc$ls180.v:1324$3634 + attribute \src "ls180.v:1235.5-1235.51" + process $proc$ls180.v:1235$3373 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1325.5-1325.52" - process $proc$ls180.v:1325$3635 + attribute \src "ls180.v:1236.5-1236.52" + process $proc$ls180.v:1236$3374 assign { } { } assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1326.11-1326.58" - process $proc$ls180.v:1326$3636 + attribute \src "ls180.v:1237.11-1237.58" + process $proc$ls180.v:1237$3375 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 sync always sync init update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] end - attribute \src "ls180.v:1327.5-1327.53" - process $proc$ls180.v:1327$3637 + attribute \src "ls180.v:1238.5-1238.53" + process $proc$ls180.v:1238$3376 assign { } { } assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 sync always sync init update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] end - attribute \src "ls180.v:1328.5-1328.39" - process $proc$ls180.v:1328$3638 + attribute \src "ls180.v:1239.5-1239.39" + process $proc$ls180.v:1239$3377 assign { } { } assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] end - attribute \src "ls180.v:1329.5-1329.39" - process $proc$ls180.v:1329$3639 + attribute \src "ls180.v:1240.5-1240.39" + process $proc$ls180.v:1240$3378 assign { } { } assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] end - attribute \src "ls180.v:1330.5-1330.39" - process $proc$ls180.v:1330$3640 + attribute \src "ls180.v:1241.5-1241.39" + process $proc$ls180.v:1241$3379 assign { } { } assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] end - attribute \src "ls180.v:1331.5-1331.38" - process $proc$ls180.v:1331$3641 + attribute \src "ls180.v:1242.5-1242.38" + process $proc$ls180.v:1242$3380 assign { } { } assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] end - attribute \src "ls180.v:1332.11-1332.52" - process $proc$ls180.v:1332$3642 + attribute \src "ls180.v:1243.11-1243.52" + process $proc$ls180.v:1243$3381 assign { } { } assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] end - attribute \src "ls180.v:1333.5-1333.33" - process $proc$ls180.v:1333$3643 + attribute \src "ls180.v:1244.5-1244.33" + process $proc$ls180.v:1244$3382 assign { } { } assign $1\main_sdphy_dataw_stop[0:0] 1'0 sync always sync init update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] end - attribute \src "ls180.v:1334.11-1334.40" - process $proc$ls180.v:1334$3644 + attribute \src "ls180.v:1245.11-1245.40" + process $proc$ls180.v:1245$3383 assign { } { } assign $1\main_sdphy_dataw_count[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] end - attribute \src "ls180.v:1335.5-1335.50" - process $proc$ls180.v:1335$3645 + attribute \src "ls180.v:1246.5-1246.50" + process $proc$ls180.v:1246$3384 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] sync init end - attribute \src "ls180.v:1337.5-1337.50" - process $proc$ls180.v:1337$3646 + attribute \src "ls180.v:1248.5-1248.50" + process $proc$ls180.v:1248$3385 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1338.5-1338.49" - process $proc$ls180.v:1338$3647 + attribute \src "ls180.v:1249.5-1249.49" + process $proc$ls180.v:1249$3386 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1339.5-1339.56" - process $proc$ls180.v:1339$3648 + attribute \src "ls180.v:1250.5-1250.56" + process $proc$ls180.v:1250$3387 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1340.5-1340.58" - process $proc$ls180.v:1340$3649 + attribute \src "ls180.v:1251.5-1251.58" + process $proc$ls180.v:1251$3388 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] sync init end - attribute \src "ls180.v:1341.5-1341.58" - process $proc$ls180.v:1341$3650 + attribute \src "ls180.v:1252.5-1252.58" + process $proc$ls180.v:1252$3389 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1342.5-1342.59" - process $proc$ls180.v:1342$3651 + attribute \src "ls180.v:1253.5-1253.59" + process $proc$ls180.v:1253$3390 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1343.11-1343.65" - process $proc$ls180.v:1343$3652 + attribute \src "ls180.v:1254.11-1254.65" + process $proc$ls180.v:1254$3391 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] sync init end - attribute \src "ls180.v:1344.11-1344.65" - process $proc$ls180.v:1344$3653 + attribute \src "ls180.v:1255.11-1255.65" + process $proc$ls180.v:1255$3392 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1345.5-1345.60" - process $proc$ls180.v:1345$3654 + attribute \src "ls180.v:1256.5-1256.60" + process $proc$ls180.v:1256$3393 assign { } { } assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1346.5-1346.34" - process $proc$ls180.v:1346$3655 + attribute \src "ls180.v:1257.5-1257.34" + process $proc$ls180.v:1257$3394 assign { } { } assign $1\main_sdphy_dataw_start[0:0] 1'0 sync always sync init update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] end - attribute \src "ls180.v:1347.5-1347.34" - process $proc$ls180.v:1347$3656 + attribute \src "ls180.v:1258.5-1258.34" + process $proc$ls180.v:1258$3395 assign { } { } assign $1\main_sdphy_dataw_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] end - attribute \src "ls180.v:1348.5-1348.34" - process $proc$ls180.v:1348$3657 + attribute \src "ls180.v:1259.5-1259.34" + process $proc$ls180.v:1259$3396 assign { } { } assign $1\main_sdphy_dataw_error[0:0] 1'0 sync always sync init update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] end - attribute \src "ls180.v:1350.5-1350.47" - process $proc$ls180.v:1350$3658 + attribute \src "ls180.v:1261.5-1261.47" + process $proc$ls180.v:1261$3397 assign { } { } assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1361.5-1361.54" - process $proc$ls180.v:1361$3659 + attribute \src "ls180.v:1272.5-1272.54" + process $proc$ls180.v:1272$3398 assign { } { } assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] end - attribute \src "ls180.v:1366.5-1366.37" - process $proc$ls180.v:1366$3660 + attribute \src "ls180.v:1277.5-1277.37" + process $proc$ls180.v:1277$3399 assign { } { } assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] end - attribute \src "ls180.v:1369.5-1369.54" - process $proc$ls180.v:1369$3661 + attribute \src "ls180.v:128.5-128.69" + process $proc$ls180.v:128$2900 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] + sync init + end + attribute \src "ls180.v:1280.5-1280.54" + process $proc$ls180.v:1280$3400 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1370.5-1370.53" - process $proc$ls180.v:1370$3662 + attribute \src "ls180.v:1281.5-1281.53" + process $proc$ls180.v:1281$3401 assign { } { } assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1374.5-1374.56" - process $proc$ls180.v:1374$3663 + attribute \src "ls180.v:1285.5-1285.56" + process $proc$ls180.v:1285$3402 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] end - attribute \src "ls180.v:1375.5-1375.55" - process $proc$ls180.v:1375$3664 + attribute \src "ls180.v:1286.5-1286.55" + process $proc$ls180.v:1286$3403 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] end - attribute \src "ls180.v:1376.11-1376.69" - process $proc$ls180.v:1376$3665 + attribute \src "ls180.v:1287.11-1287.69" + process $proc$ls180.v:1287$3404 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1377.11-1377.82" - process $proc$ls180.v:1377$3666 + attribute \src "ls180.v:1288.11-1288.82" + process $proc$ls180.v:1288$3405 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1378.11-1378.55" - process $proc$ls180.v:1378$3667 + attribute \src "ls180.v:1289.11-1289.55" + process $proc$ls180.v:1289$3406 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 sync always sync init update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] end - attribute \src "ls180.v:1380.5-1380.54" - process $proc$ls180.v:1380$3668 + attribute \src "ls180.v:1291.5-1291.54" + process $proc$ls180.v:1291$3407 assign { } { } assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] end - attribute \src "ls180.v:1391.5-1391.50" - process $proc$ls180.v:1391$3669 + attribute \src "ls180.v:1302.5-1302.50" + process $proc$ls180.v:1302$3408 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] end - attribute \src "ls180.v:1393.5-1393.50" - process $proc$ls180.v:1393$3670 + attribute \src "ls180.v:1304.5-1304.50" + process $proc$ls180.v:1304$3409 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] end - attribute \src "ls180.v:1394.5-1394.49" - process $proc$ls180.v:1394$3671 + attribute \src "ls180.v:1305.5-1305.49" + process $proc$ls180.v:1305$3410 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] end - attribute \src "ls180.v:1395.11-1395.63" - process $proc$ls180.v:1395$3672 + attribute \src "ls180.v:1306.11-1306.63" + process $proc$ls180.v:1306$3411 assign { } { } assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1396.5-1396.39" - process $proc$ls180.v:1396$3673 + attribute \src "ls180.v:1307.5-1307.39" + process $proc$ls180.v:1307$3412 assign { } { } assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] end - attribute \src "ls180.v:1399.5-1399.50" - process $proc$ls180.v:1399$3674 + attribute \src "ls180.v:1310.5-1310.50" + process $proc$ls180.v:1310$3413 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] sync init end - attribute \src "ls180.v:1400.5-1400.49" - process $proc$ls180.v:1400$3675 + attribute \src "ls180.v:1311.5-1311.49" + process $proc$ls180.v:1311$3414 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] sync init end - attribute \src "ls180.v:1401.5-1401.56" - process $proc$ls180.v:1401$3676 + attribute \src "ls180.v:1312.5-1312.56" + process $proc$ls180.v:1312$3415 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] sync init end - attribute \src "ls180.v:1403.5-1403.58" - process $proc$ls180.v:1403$3677 + attribute \src "ls180.v:1314.5-1314.58" + process $proc$ls180.v:1314$3416 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1404.5-1404.59" - process $proc$ls180.v:1404$3678 + attribute \src "ls180.v:1315.5-1315.59" + process $proc$ls180.v:1315$3417 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1406.11-1406.65" - process $proc$ls180.v:1406$3679 + attribute \src "ls180.v:1317.11-1317.65" + process $proc$ls180.v:1317$3418 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1407.5-1407.60" - process $proc$ls180.v:1407$3680 + attribute \src "ls180.v:1318.5-1318.60" + process $proc$ls180.v:1318$3419 assign { } { } assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1409.5-1409.49" - process $proc$ls180.v:1409$3681 + attribute \src "ls180.v:132.5-132.72" + process $proc$ls180.v:132$2901 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] + sync init + end + attribute \src "ls180.v:1320.5-1320.49" + process $proc$ls180.v:1320$3420 assign { } { } assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 sync always sync init update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] end - attribute \src "ls180.v:1410.5-1410.51" - process $proc$ls180.v:1410$3682 + attribute \src "ls180.v:1321.5-1321.51" + process $proc$ls180.v:1321$3421 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] sync init end - attribute \src "ls180.v:1411.5-1411.52" - process $proc$ls180.v:1411$3683 + attribute \src "ls180.v:1322.5-1322.52" + process $proc$ls180.v:1322$3422 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] sync init end - attribute \src "ls180.v:1412.11-1412.58" - process $proc$ls180.v:1412$3684 + attribute \src "ls180.v:1323.11-1323.58" + process $proc$ls180.v:1323$3423 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 sync always update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] sync init end - attribute \src "ls180.v:1413.5-1413.53" - process $proc$ls180.v:1413$3685 + attribute \src "ls180.v:1324.5-1324.53" + process $proc$ls180.v:1324$3424 assign { } { } assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 sync always update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] sync init end - attribute \src "ls180.v:1414.5-1414.39" - process $proc$ls180.v:1414$3686 + attribute \src "ls180.v:1325.5-1325.39" + process $proc$ls180.v:1325$3425 assign { } { } assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] end - attribute \src "ls180.v:1415.5-1415.39" - process $proc$ls180.v:1415$3687 + attribute \src "ls180.v:1326.5-1326.39" + process $proc$ls180.v:1326$3426 assign { } { } assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] end - attribute \src "ls180.v:1416.5-1416.38" - process $proc$ls180.v:1416$3688 + attribute \src "ls180.v:1327.5-1327.38" + process $proc$ls180.v:1327$3427 assign { } { } assign $1\main_sdphy_datar_sink_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] end - attribute \src "ls180.v:1417.11-1417.61" - process $proc$ls180.v:1417$3689 + attribute \src "ls180.v:1328.11-1328.61" + process $proc$ls180.v:1328$3428 assign { } { } assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] end - attribute \src "ls180.v:1418.5-1418.41" - process $proc$ls180.v:1418$3690 + attribute \src "ls180.v:1329.5-1329.41" + process $proc$ls180.v:1329$3429 assign { } { } assign $1\main_sdphy_datar_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] end - attribute \src "ls180.v:1419.5-1419.41" - process $proc$ls180.v:1419$3691 + attribute \src "ls180.v:1330.5-1330.41" + process $proc$ls180.v:1330$3430 assign { } { } assign $1\main_sdphy_datar_source_ready[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] end - attribute \src "ls180.v:1420.5-1420.41" - process $proc$ls180.v:1420$3692 + attribute \src "ls180.v:1331.5-1331.41" + process $proc$ls180.v:1331$3431 assign { } { } assign $0\main_sdphy_datar_source_first[0:0] 1'0 sync always update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] sync init end - attribute \src "ls180.v:1421.5-1421.40" - process $proc$ls180.v:1421$3693 + attribute \src "ls180.v:1332.5-1332.40" + process $proc$ls180.v:1332$3432 assign { } { } assign $1\main_sdphy_datar_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] end - attribute \src "ls180.v:1422.11-1422.54" - process $proc$ls180.v:1422$3694 + attribute \src "ls180.v:1333.11-1333.54" + process $proc$ls180.v:1333$3433 assign { } { } assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] end - attribute \src "ls180.v:1423.11-1423.56" - process $proc$ls180.v:1423$3695 + attribute \src "ls180.v:1334.11-1334.56" + process $proc$ls180.v:1334$3434 assign { } { } assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 sync always sync init update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] end - attribute \src "ls180.v:1424.5-1424.33" - process $proc$ls180.v:1424$3696 + attribute \src "ls180.v:1335.5-1335.33" + process $proc$ls180.v:1335$3435 assign { } { } assign $1\main_sdphy_datar_stop[0:0] 1'0 sync always sync init update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] end - attribute \src "ls180.v:1425.12-1425.49" - process $proc$ls180.v:1425$3697 + attribute \src "ls180.v:1336.12-1336.49" + process $proc$ls180.v:1336$3436 assign { } { } assign $1\main_sdphy_datar_timeout[31:0] 500000 sync always sync init update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] end - attribute \src "ls180.v:1426.11-1426.41" - process $proc$ls180.v:1426$3698 + attribute \src "ls180.v:1337.11-1337.41" + process $proc$ls180.v:1337$3437 assign { } { } assign $1\main_sdphy_datar_count[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] end - attribute \src "ls180.v:1428.5-1428.48" - process $proc$ls180.v:1428$3699 + attribute \src "ls180.v:1339.5-1339.48" + process $proc$ls180.v:1339$3438 assign { } { } assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 sync always update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] sync init end - attribute \src "ls180.v:1439.5-1439.55" - process $proc$ls180.v:1439$3700 + attribute \src "ls180.v:135.11-135.79" + process $proc$ls180.v:135$2902 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] 4'0000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] + sync init + end + attribute \src "ls180.v:1350.5-1350.55" + process $proc$ls180.v:1350$3439 assign { } { } assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] end - attribute \src "ls180.v:1444.5-1444.38" - process $proc$ls180.v:1444$3701 + attribute \src "ls180.v:1355.5-1355.38" + process $proc$ls180.v:1355$3440 assign { } { } assign $1\main_sdphy_datar_datar_run[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] end - attribute \src "ls180.v:1447.5-1447.55" - process $proc$ls180.v:1447$3702 + attribute \src "ls180.v:1358.5-1358.55" + process $proc$ls180.v:1358$3441 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 sync always update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] sync init end - attribute \src "ls180.v:1448.5-1448.54" - process $proc$ls180.v:1448$3703 + attribute \src "ls180.v:1359.5-1359.54" + process $proc$ls180.v:1359$3442 assign { } { } assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 sync always update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] sync init end - attribute \src "ls180.v:1452.5-1452.57" - process $proc$ls180.v:1452$3704 + attribute \src "ls180.v:1363.5-1363.57" + process $proc$ls180.v:1363$3443 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] end - attribute \src "ls180.v:1453.5-1453.56" - process $proc$ls180.v:1453$3705 + attribute \src "ls180.v:1364.5-1364.56" + process $proc$ls180.v:1364$3444 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] end - attribute \src "ls180.v:1454.11-1454.70" - process $proc$ls180.v:1454$3706 + attribute \src "ls180.v:1365.11-1365.70" + process $proc$ls180.v:1365$3445 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1455.11-1455.83" - process $proc$ls180.v:1455$3707 + attribute \src "ls180.v:1366.11-1366.83" + process $proc$ls180.v:1366$3446 assign { } { } assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 sync always sync init update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] end - attribute \src "ls180.v:1456.5-1456.50" - process $proc$ls180.v:1456$3708 + attribute \src "ls180.v:1367.5-1367.50" + process $proc$ls180.v:1367$3447 assign { } { } assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] end - attribute \src "ls180.v:1458.5-1458.55" - process $proc$ls180.v:1458$3709 + attribute \src "ls180.v:1369.5-1369.55" + process $proc$ls180.v:1369$3448 assign { } { } assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] end - attribute \src "ls180.v:1469.5-1469.51" - process $proc$ls180.v:1469$3710 + attribute \src "ls180.v:1380.5-1380.51" + process $proc$ls180.v:1380$3449 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] end - attribute \src "ls180.v:1471.5-1471.51" - process $proc$ls180.v:1471$3711 + attribute \src "ls180.v:1382.5-1382.51" + process $proc$ls180.v:1382$3450 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] end - attribute \src "ls180.v:1472.5-1472.50" - process $proc$ls180.v:1472$3712 + attribute \src "ls180.v:1383.5-1383.50" + process $proc$ls180.v:1383$3451 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] end - attribute \src "ls180.v:1473.11-1473.64" - process $proc$ls180.v:1473$3713 + attribute \src "ls180.v:1384.11-1384.64" + process $proc$ls180.v:1384$3452 assign { } { } assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] end - attribute \src "ls180.v:1474.5-1474.40" - process $proc$ls180.v:1474$3714 + attribute \src "ls180.v:1385.5-1385.40" + process $proc$ls180.v:1385$3453 assign { } { } assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] end - attribute \src "ls180.v:1476.5-1476.35" - process $proc$ls180.v:1476$3715 + attribute \src "ls180.v:1387.5-1387.35" + process $proc$ls180.v:1387$3454 assign { } { } assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 sync always sync init update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] end - attribute \src "ls180.v:1479.11-1479.42" - process $proc$ls180.v:1479$3716 + attribute \src "ls180.v:1390.11-1390.42" + process $proc$ls180.v:1390$3455 assign { } { } assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 sync always sync init update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] end - attribute \src "ls180.v:1492.12-1492.52" - process $proc$ls180.v:1492$3717 + attribute \src "ls180.v:1403.12-1403.52" + process $proc$ls180.v:1403$3456 assign { } { } assign $1\main_sdcore_cmd_argument_storage[31:0] 0 sync always sync init update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] end - attribute \src "ls180.v:1493.5-1493.39" - process $proc$ls180.v:1493$3718 + attribute \src "ls180.v:1404.5-1404.39" + process $proc$ls180.v:1404$3457 assign { } { } assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 sync always sync init update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] end - attribute \src "ls180.v:1494.12-1494.51" - process $proc$ls180.v:1494$3719 + attribute \src "ls180.v:1405.12-1405.51" + process $proc$ls180.v:1405$3458 assign { } { } assign $1\main_sdcore_cmd_command_storage[31:0] 0 sync always sync init update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] end - attribute \src "ls180.v:1495.5-1495.38" - process $proc$ls180.v:1495$3720 + attribute \src "ls180.v:1406.5-1406.38" + process $proc$ls180.v:1406$3459 assign { } { } assign $1\main_sdcore_cmd_command_re[0:0] 1'0 sync always sync init update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] end - attribute \src "ls180.v:1499.5-1499.34" - process $proc$ls180.v:1499$3721 + attribute \src "ls180.v:1410.5-1410.34" + process $proc$ls180.v:1410$3460 assign { } { } assign $0\main_sdcore_cmd_send_w[0:0] 1'0 sync always update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] sync init end - attribute \src "ls180.v:1500.13-1500.53" - process $proc$ls180.v:1500$3722 + attribute \src "ls180.v:1411.13-1411.53" + process $proc$ls180.v:1411$3461 assign { } { } assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] end - attribute \src "ls180.v:1506.11-1506.51" - process $proc$ls180.v:1506$3723 + attribute \src "ls180.v:1417.11-1417.51" + process $proc$ls180.v:1417$3462 assign { } { } assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 sync always sync init update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] end - attribute \src "ls180.v:1507.5-1507.39" - process $proc$ls180.v:1507$3724 + attribute \src "ls180.v:1418.5-1418.39" + process $proc$ls180.v:1418$3463 assign { } { } assign $1\main_sdcore_block_length_re[0:0] 1'0 sync always sync init update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] end - attribute \src "ls180.v:1508.12-1508.51" - process $proc$ls180.v:1508$3725 + attribute \src "ls180.v:1419.12-1419.51" + process $proc$ls180.v:1419$3464 assign { } { } assign $1\main_sdcore_block_count_storage[31:0] 0 sync always sync init update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] end - attribute \src "ls180.v:1509.5-1509.38" - process $proc$ls180.v:1509$3726 + attribute \src "ls180.v:1420.5-1420.38" + process $proc$ls180.v:1420$3465 assign { } { } assign $1\main_sdcore_block_count_re[0:0] 1'0 sync always sync init update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] end - attribute \src "ls180.v:1510.11-1510.51" - process $proc$ls180.v:1510$3727 + attribute \src "ls180.v:1421.11-1421.51" + process $proc$ls180.v:1421$3466 assign { } { } assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 sync always sync init update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] end - attribute \src "ls180.v:1552.11-1552.47" - process $proc$ls180.v:1552$3728 + attribute \src "ls180.v:143.12-143.78" + process $proc$ls180.v:143$2903 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] + sync init + end + attribute \src "ls180.v:1463.11-1463.47" + process $proc$ls180.v:1463$3467 assign { } { } assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 sync always sync init update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] end - attribute \src "ls180.v:1556.5-1556.49" - process $proc$ls180.v:1556$3729 + attribute \src "ls180.v:1467.5-1467.49" + process $proc$ls180.v:1467$3468 assign { } { } assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] end - attribute \src "ls180.v:1560.5-1560.51" - process $proc$ls180.v:1560$3730 + attribute \src "ls180.v:1471.5-1471.51" + process $proc$ls180.v:1471$3469 assign { } { } assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] end - attribute \src "ls180.v:1561.5-1561.51" - process $proc$ls180.v:1561$3731 + attribute \src "ls180.v:1472.5-1472.51" + process $proc$ls180.v:1472$3470 assign { } { } assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] end - attribute \src "ls180.v:1562.5-1562.51" - process $proc$ls180.v:1562$3732 + attribute \src "ls180.v:1473.5-1473.51" + process $proc$ls180.v:1473$3471 assign { } { } assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 sync always update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] sync init end - attribute \src "ls180.v:1563.5-1563.50" - process $proc$ls180.v:1563$3733 + attribute \src "ls180.v:1474.5-1474.50" + process $proc$ls180.v:1474$3472 assign { } { } assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] end - attribute \src "ls180.v:1564.11-1564.64" - process $proc$ls180.v:1564$3734 + attribute \src "ls180.v:1475.11-1475.64" + process $proc$ls180.v:1475$3473 assign { } { } assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] end - attribute \src "ls180.v:1565.11-1565.48" - process $proc$ls180.v:1565$3735 + attribute \src "ls180.v:1476.11-1476.48" + process $proc$ls180.v:1476$3474 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 sync always sync init update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] end - attribute \src "ls180.v:1566.12-1566.59" - process $proc$ls180.v:1566$3736 + attribute \src "ls180.v:1477.12-1477.59" + process $proc$ls180.v:1477$3475 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] end - attribute \src "ls180.v:1570.12-1570.55" - process $proc$ls180.v:1570$3737 + attribute \src "ls180.v:1481.12-1481.55" + process $proc$ls180.v:1481$3476 assign { } { } assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] end - attribute \src "ls180.v:1573.12-1573.59" - process $proc$ls180.v:1573$3738 + attribute \src "ls180.v:1484.12-1484.59" + process $proc$ls180.v:1484$3477 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] end - attribute \src "ls180.v:1577.12-1577.55" - process $proc$ls180.v:1577$3739 + attribute \src "ls180.v:1488.12-1488.55" + process $proc$ls180.v:1488$3478 assign { } { } assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] end - attribute \src "ls180.v:1580.12-1580.59" - process $proc$ls180.v:1580$3740 + attribute \src "ls180.v:1491.12-1491.59" + process $proc$ls180.v:1491$3479 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] end - attribute \src "ls180.v:1584.12-1584.55" - process $proc$ls180.v:1584$3741 + attribute \src "ls180.v:1495.12-1495.55" + process $proc$ls180.v:1495$3480 assign { } { } assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] end - attribute \src "ls180.v:1587.12-1587.59" - process $proc$ls180.v:1587$3742 + attribute \src "ls180.v:1498.12-1498.59" + process $proc$ls180.v:1498$3481 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] end - attribute \src "ls180.v:1591.12-1591.55" - process $proc$ls180.v:1591$3743 + attribute \src "ls180.v:1502.12-1502.55" + process $proc$ls180.v:1502$3482 assign { } { } assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] end - attribute \src "ls180.v:1594.12-1594.54" - process $proc$ls180.v:1594$3744 + attribute \src "ls180.v:1505.12-1505.54" + process $proc$ls180.v:1505$3483 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] end - attribute \src "ls180.v:1595.12-1595.54" - process $proc$ls180.v:1595$3745 + attribute \src "ls180.v:1506.12-1506.54" + process $proc$ls180.v:1506$3484 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] end - attribute \src "ls180.v:1596.12-1596.54" - process $proc$ls180.v:1596$3746 + attribute \src "ls180.v:1507.12-1507.54" + process $proc$ls180.v:1507$3485 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] end - attribute \src "ls180.v:1597.12-1597.54" - process $proc$ls180.v:1597$3747 + attribute \src "ls180.v:1508.12-1508.54" + process $proc$ls180.v:1508$3486 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] end - attribute \src "ls180.v:1598.5-1598.48" - process $proc$ls180.v:1598$3748 + attribute \src "ls180.v:1509.5-1509.48" + process $proc$ls180.v:1509$3487 assign { } { } assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] end - attribute \src "ls180.v:1599.5-1599.48" - process $proc$ls180.v:1599$3749 + attribute \src "ls180.v:1510.5-1510.48" + process $proc$ls180.v:1510$3488 assign { } { } assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] end - attribute \src "ls180.v:1600.5-1600.48" - process $proc$ls180.v:1600$3750 + attribute \src "ls180.v:1511.5-1511.48" + process $proc$ls180.v:1511$3489 assign { } { } assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] end - attribute \src "ls180.v:1601.5-1601.47" - process $proc$ls180.v:1601$3751 + attribute \src "ls180.v:1512.5-1512.47" + process $proc$ls180.v:1512$3490 assign { } { } assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] end - attribute \src "ls180.v:1602.11-1602.61" - process $proc$ls180.v:1602$3752 + attribute \src "ls180.v:1513.11-1513.61" + process $proc$ls180.v:1513$3491 assign { } { } assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] end - attribute \src "ls180.v:1603.5-1603.50" - process $proc$ls180.v:1603$3753 + attribute \src "ls180.v:1514.5-1514.50" + process $proc$ls180.v:1514$3492 assign { } { } assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] end - attribute \src "ls180.v:1605.5-1605.50" - process $proc$ls180.v:1605$3754 + attribute \src "ls180.v:1516.5-1516.50" + process $proc$ls180.v:1516$3493 assign { } { } assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 sync always update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] sync init end - attribute \src "ls180.v:1608.11-1608.47" - process $proc$ls180.v:1608$3755 + attribute \src "ls180.v:1519.11-1519.47" + process $proc$ls180.v:1519$3494 assign { } { } assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 sync always sync init update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] end - attribute \src "ls180.v:1609.11-1609.47" - process $proc$ls180.v:1609$3756 + attribute \src "ls180.v:1520.11-1520.47" + process $proc$ls180.v:1520$3495 assign { } { } assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 sync always sync init update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] end - attribute \src "ls180.v:1610.12-1610.58" - process $proc$ls180.v:1610$3757 + attribute \src "ls180.v:1521.12-1521.58" + process $proc$ls180.v:1521$3496 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] end - attribute \src "ls180.v:1614.12-1614.54" - process $proc$ls180.v:1614$3758 + attribute \src "ls180.v:1525.12-1525.54" + process $proc$ls180.v:1525$3497 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] end - attribute \src "ls180.v:1615.5-1615.46" - process $proc$ls180.v:1615$3759 + attribute \src "ls180.v:1526.5-1526.46" + process $proc$ls180.v:1526$3498 assign { } { } assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] end - attribute \src "ls180.v:1617.12-1617.58" - process $proc$ls180.v:1617$3760 + attribute \src "ls180.v:1528.12-1528.58" + process $proc$ls180.v:1528$3499 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] end - attribute \src "ls180.v:1621.12-1621.54" - process $proc$ls180.v:1621$3761 + attribute \src "ls180.v:1532.12-1532.54" + process $proc$ls180.v:1532$3500 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] end - attribute \src "ls180.v:1622.5-1622.46" - process $proc$ls180.v:1622$3762 + attribute \src "ls180.v:1533.5-1533.46" + process $proc$ls180.v:1533$3501 assign { } { } assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] end - attribute \src "ls180.v:1624.12-1624.58" - process $proc$ls180.v:1624$3763 + attribute \src "ls180.v:1535.12-1535.58" + process $proc$ls180.v:1535$3502 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] end - attribute \src "ls180.v:1628.12-1628.54" - process $proc$ls180.v:1628$3764 + attribute \src "ls180.v:1539.12-1539.54" + process $proc$ls180.v:1539$3503 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] end - attribute \src "ls180.v:1629.5-1629.46" - process $proc$ls180.v:1629$3765 + attribute \src "ls180.v:154.12-154.74" + process $proc$ls180.v:154$2904 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + sync init + end + attribute \src "ls180.v:1540.5-1540.46" + process $proc$ls180.v:1540$3504 assign { } { } assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] end - attribute \src "ls180.v:1631.12-1631.58" - process $proc$ls180.v:1631$3766 + attribute \src "ls180.v:1542.12-1542.58" + process $proc$ls180.v:1542$3505 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] end - attribute \src "ls180.v:1635.12-1635.54" - process $proc$ls180.v:1635$3767 + attribute \src "ls180.v:1546.12-1546.54" + process $proc$ls180.v:1546$3506 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] end - attribute \src "ls180.v:1636.5-1636.46" - process $proc$ls180.v:1636$3768 + attribute \src "ls180.v:1547.5-1547.46" + process $proc$ls180.v:1547$3507 assign { } { } assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] end - attribute \src "ls180.v:1638.12-1638.53" - process $proc$ls180.v:1638$3769 + attribute \src "ls180.v:1549.12-1549.53" + process $proc$ls180.v:1549$3508 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] end - attribute \src "ls180.v:1639.12-1639.53" - process $proc$ls180.v:1639$3770 + attribute \src "ls180.v:1550.12-1550.53" + process $proc$ls180.v:1550$3509 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] end - attribute \src "ls180.v:1640.12-1640.53" - process $proc$ls180.v:1640$3771 + attribute \src "ls180.v:1551.12-1551.53" + process $proc$ls180.v:1551$3510 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] end - attribute \src "ls180.v:1641.12-1641.53" - process $proc$ls180.v:1641$3772 + attribute \src "ls180.v:1552.12-1552.53" + process $proc$ls180.v:1552$3511 assign { } { } assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] end - attribute \src "ls180.v:1642.5-1642.43" - process $proc$ls180.v:1642$3773 + attribute \src "ls180.v:1553.5-1553.43" + process $proc$ls180.v:1553$3512 assign { } { } assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 sync always sync init update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] end - attribute \src "ls180.v:1643.12-1643.51" - process $proc$ls180.v:1643$3774 + attribute \src "ls180.v:1554.12-1554.51" + process $proc$ls180.v:1554$3513 assign { } { } assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] end - attribute \src "ls180.v:1644.12-1644.51" - process $proc$ls180.v:1644$3775 + attribute \src "ls180.v:1555.12-1555.51" + process $proc$ls180.v:1555$3514 assign { } { } assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] end - attribute \src "ls180.v:1645.12-1645.51" - process $proc$ls180.v:1645$3776 + attribute \src "ls180.v:1556.12-1556.51" + process $proc$ls180.v:1556$3515 assign { } { } assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] end - attribute \src "ls180.v:1646.12-1646.51" - process $proc$ls180.v:1646$3777 + attribute \src "ls180.v:1557.12-1557.51" + process $proc$ls180.v:1557$3516 assign { } { } assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] end - attribute \src "ls180.v:1648.11-1648.39" - process $proc$ls180.v:1648$3778 + attribute \src "ls180.v:1559.11-1559.39" + process $proc$ls180.v:1559$3517 assign { } { } assign $1\main_sdcore_cmd_count[2:0] 3'000 sync always sync init update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] end - attribute \src "ls180.v:1649.5-1649.32" - process $proc$ls180.v:1649$3779 + attribute \src "ls180.v:1560.5-1560.32" + process $proc$ls180.v:1560$3518 assign { } { } assign $1\main_sdcore_cmd_done[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] end - attribute \src "ls180.v:1650.5-1650.33" - process $proc$ls180.v:1650$3780 + attribute \src "ls180.v:1561.5-1561.33" + process $proc$ls180.v:1561$3519 assign { } { } assign $1\main_sdcore_cmd_error[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] end - attribute \src "ls180.v:1651.5-1651.35" - process $proc$ls180.v:1651$3781 + attribute \src "ls180.v:1562.5-1562.35" + process $proc$ls180.v:1562$3520 assign { } { } assign $1\main_sdcore_cmd_timeout[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] end - attribute \src "ls180.v:1653.12-1653.42" - process $proc$ls180.v:1653$3782 + attribute \src "ls180.v:1564.12-1564.42" + process $proc$ls180.v:1564$3521 assign { } { } assign $1\main_sdcore_data_count[31:0] 0 sync always sync init update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] end - attribute \src "ls180.v:1654.5-1654.33" - process $proc$ls180.v:1654$3783 + attribute \src "ls180.v:1565.5-1565.33" + process $proc$ls180.v:1565$3522 assign { } { } assign $1\main_sdcore_data_done[0:0] 1'0 sync always sync init update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] end - attribute \src "ls180.v:1655.5-1655.34" - process $proc$ls180.v:1655$3784 + attribute \src "ls180.v:1566.5-1566.34" + process $proc$ls180.v:1566$3523 assign { } { } assign $1\main_sdcore_data_error[0:0] 1'0 sync always sync init update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] end - attribute \src "ls180.v:1656.5-1656.36" - process $proc$ls180.v:1656$3785 + attribute \src "ls180.v:1567.5-1567.36" + process $proc$ls180.v:1567$3524 assign { } { } assign $1\main_sdcore_data_timeout[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] end - attribute \src "ls180.v:1665.11-1665.41" - process $proc$ls180.v:1665$3786 + attribute \src "ls180.v:1576.11-1576.41" + process $proc$ls180.v:1576$3525 assign { } { } assign $0\main_interface0_bus_cti[2:0] 3'000 sync always update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] sync init end - attribute \src "ls180.v:1666.11-1666.41" - process $proc$ls180.v:1666$3787 + attribute \src "ls180.v:1577.11-1577.41" + process $proc$ls180.v:1577$3526 assign { } { } assign $0\main_interface0_bus_bte[1:0] 2'00 sync always update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] sync init end - attribute \src "ls180.v:1689.11-1689.45" - process $proc$ls180.v:1689$3788 + attribute \src "ls180.v:1600.11-1600.45" + process $proc$ls180.v:1600$3527 assign { } { } assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 sync always sync init update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] end - attribute \src "ls180.v:1690.5-1690.41" - process $proc$ls180.v:1690$3789 + attribute \src "ls180.v:1601.5-1601.41" + process $proc$ls180.v:1601$3528 assign { } { } assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 sync always update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] sync init end - attribute \src "ls180.v:1691.11-1691.47" - process $proc$ls180.v:1691$3790 + attribute \src "ls180.v:1602.11-1602.47" + process $proc$ls180.v:1602$3529 assign { } { } assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] end - attribute \src "ls180.v:1692.11-1692.47" - process $proc$ls180.v:1692$3791 + attribute \src "ls180.v:1603.11-1603.47" + process $proc$ls180.v:1603$3530 assign { } { } assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] end - attribute \src "ls180.v:1693.11-1693.50" - process $proc$ls180.v:1693$3792 + attribute \src "ls180.v:1604.11-1604.50" + process $proc$ls180.v:1604$3531 assign { } { } assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 sync always sync init update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:171.12-171.74" - process $proc$ls180.v:171$3152 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] - sync init - end - attribute \src "ls180.v:1713.5-1713.51" - process $proc$ls180.v:1713$3793 + attribute \src "ls180.v:1624.5-1624.51" + process $proc$ls180.v:1624$3532 assign { } { } assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] end - attribute \src "ls180.v:1714.5-1714.50" - process $proc$ls180.v:1714$3794 + attribute \src "ls180.v:1625.5-1625.50" + process $proc$ls180.v:1625$3533 assign { } { } assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] end - attribute \src "ls180.v:1715.12-1715.66" - process $proc$ls180.v:1715$3795 + attribute \src "ls180.v:1626.12-1626.66" + process $proc$ls180.v:1626$3534 assign { } { } assign $1\main_sdblock2mem_converter_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[63:0] end - attribute \src "ls180.v:1716.11-1716.77" - process $proc$ls180.v:1716$3796 + attribute \src "ls180.v:1627.11-1627.77" + process $proc$ls180.v:1627$3535 assign { } { } assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] 4'0000 sync always sync init update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] end - attribute \src "ls180.v:1717.11-1717.50" - process $proc$ls180.v:1717$3797 + attribute \src "ls180.v:1628.11-1628.50" + process $proc$ls180.v:1628$3536 assign { } { } assign $1\main_sdblock2mem_converter_demux[2:0] 3'000 sync always sync init update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[2:0] end - attribute \src "ls180.v:1719.5-1719.49" - process $proc$ls180.v:1719$3798 + attribute \src "ls180.v:1630.5-1630.49" + process $proc$ls180.v:1630$3537 assign { } { } assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 sync always sync init update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] end - attribute \src "ls180.v:1725.5-1725.45" - process $proc$ls180.v:1725$3799 + attribute \src "ls180.v:1636.5-1636.45" + process $proc$ls180.v:1636$3538 assign { } { } assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 sync always sync init update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] end - attribute \src "ls180.v:1727.12-1727.62" - process $proc$ls180.v:1727$3800 + attribute \src "ls180.v:1638.12-1638.62" + process $proc$ls180.v:1638$3539 assign { } { } assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 sync always sync init update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] end - attribute \src "ls180.v:1728.12-1728.60" - process $proc$ls180.v:1728$3801 + attribute \src "ls180.v:1639.12-1639.60" + process $proc$ls180.v:1639$3540 assign { } { } assign $1\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] end - attribute \src "ls180.v:1730.5-1730.57" - process $proc$ls180.v:1730$3802 + attribute \src "ls180.v:1641.5-1641.57" + process $proc$ls180.v:1641$3541 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] end - attribute \src "ls180.v:1734.12-1734.67" - process $proc$ls180.v:1734$3803 + attribute \src "ls180.v:1645.12-1645.67" + process $proc$ls180.v:1645$3542 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] end - attribute \src "ls180.v:1735.5-1735.54" - process $proc$ls180.v:1735$3804 + attribute \src "ls180.v:1646.5-1646.54" + process $proc$ls180.v:1646$3543 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] end - attribute \src "ls180.v:1736.12-1736.69" - process $proc$ls180.v:1736$3805 + attribute \src "ls180.v:1647.12-1647.69" + process $proc$ls180.v:1647$3544 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] end - attribute \src "ls180.v:1737.5-1737.56" - process $proc$ls180.v:1737$3806 + attribute \src "ls180.v:1648.5-1648.56" + process $proc$ls180.v:1648$3545 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] end - attribute \src "ls180.v:1738.5-1738.61" - process $proc$ls180.v:1738$3807 + attribute \src "ls180.v:1649.5-1649.61" + process $proc$ls180.v:1649$3546 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] end - attribute \src "ls180.v:1739.5-1739.56" - process $proc$ls180.v:1739$3808 + attribute \src "ls180.v:1650.5-1650.56" + process $proc$ls180.v:1650$3547 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] end - attribute \src "ls180.v:1740.5-1740.53" - process $proc$ls180.v:1740$3809 + attribute \src "ls180.v:1651.5-1651.53" + process $proc$ls180.v:1651$3548 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] end - attribute \src "ls180.v:1742.5-1742.59" - process $proc$ls180.v:1742$3810 + attribute \src "ls180.v:1653.5-1653.59" + process $proc$ls180.v:1653$3549 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] end - attribute \src "ls180.v:1743.5-1743.54" - process $proc$ls180.v:1743$3811 + attribute \src "ls180.v:1654.5-1654.54" + process $proc$ls180.v:1654$3550 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] end - attribute \src "ls180.v:1745.12-1745.61" - process $proc$ls180.v:1745$3812 + attribute \src "ls180.v:1656.12-1656.61" + process $proc$ls180.v:1656$3551 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] end - attribute \src "ls180.v:1748.12-1748.43" - process $proc$ls180.v:1748$3813 + attribute \src "ls180.v:1659.12-1659.43" + process $proc$ls180.v:1659$3552 assign { } { } assign $1\main_interface1_bus_adr[31:0] 0 sync always sync init update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] end - attribute \src "ls180.v:1749.12-1749.45" - process $proc$ls180.v:1749$3814 + attribute \src "ls180.v:1660.12-1660.45" + process $proc$ls180.v:1660$3553 assign { } { } assign $0\main_interface1_bus_dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[63:0] sync init end - attribute \src "ls180.v:175.5-175.69" - process $proc$ls180.v:175$3153 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - sync init - end - attribute \src "ls180.v:1751.11-1751.41" - process $proc$ls180.v:1751$3815 + attribute \src "ls180.v:1662.11-1662.41" + process $proc$ls180.v:1662$3554 assign { } { } assign $1\main_interface1_bus_sel[7:0] 8'00000000 sync always sync init update \main_interface1_bus_sel $1\main_interface1_bus_sel[7:0] end - attribute \src "ls180.v:1752.5-1752.35" - process $proc$ls180.v:1752$3816 + attribute \src "ls180.v:1663.5-1663.35" + process $proc$ls180.v:1663$3555 assign { } { } assign $1\main_interface1_bus_cyc[0:0] 1'0 sync always sync init update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] end - attribute \src "ls180.v:1753.5-1753.35" - process $proc$ls180.v:1753$3817 + attribute \src "ls180.v:1664.5-1664.35" + process $proc$ls180.v:1664$3556 assign { } { } assign $1\main_interface1_bus_stb[0:0] 1'0 sync always sync init update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] end - attribute \src "ls180.v:1755.5-1755.34" - process $proc$ls180.v:1755$3818 + attribute \src "ls180.v:1666.5-1666.34" + process $proc$ls180.v:1666$3557 assign { } { } assign $1\main_interface1_bus_we[0:0] 1'0 sync always sync init update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] end - attribute \src "ls180.v:1756.11-1756.41" - process $proc$ls180.v:1756$3819 + attribute \src "ls180.v:1667.11-1667.41" + process $proc$ls180.v:1667$3558 assign { } { } assign $0\main_interface1_bus_cti[2:0] 3'000 sync always update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] sync init end - attribute \src "ls180.v:1757.11-1757.41" - process $proc$ls180.v:1757$3820 + attribute \src "ls180.v:1668.11-1668.41" + process $proc$ls180.v:1668$3559 assign { } { } assign $0\main_interface1_bus_bte[1:0] 2'00 sync always update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] sync init end - attribute \src "ls180.v:1764.5-1764.43" - process $proc$ls180.v:1764$3821 + attribute \src "ls180.v:1675.5-1675.43" + process $proc$ls180.v:1675$3560 assign { } { } assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] end - attribute \src "ls180.v:1765.5-1765.43" - process $proc$ls180.v:1765$3822 + attribute \src "ls180.v:1676.5-1676.43" + process $proc$ls180.v:1676$3561 assign { } { } assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] end - attribute \src "ls180.v:1766.5-1766.42" - process $proc$ls180.v:1766$3823 + attribute \src "ls180.v:1677.5-1677.42" + process $proc$ls180.v:1677$3562 assign { } { } assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] end - attribute \src "ls180.v:1767.12-1767.61" - process $proc$ls180.v:1767$3824 + attribute \src "ls180.v:1678.12-1678.61" + process $proc$ls180.v:1678$3563 assign { } { } assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 sync always sync init update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] end - attribute \src "ls180.v:1768.5-1768.45" - process $proc$ls180.v:1768$3825 + attribute \src "ls180.v:1679.5-1679.45" + process $proc$ls180.v:1679$3564 assign { } { } assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] end - attribute \src "ls180.v:1770.5-1770.45" - process $proc$ls180.v:1770$3826 + attribute \src "ls180.v:1681.5-1681.45" + process $proc$ls180.v:1681$3565 assign { } { } assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 sync always update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] sync init end - attribute \src "ls180.v:1771.5-1771.44" - process $proc$ls180.v:1771$3827 + attribute \src "ls180.v:1682.5-1682.44" + process $proc$ls180.v:1682$3566 assign { } { } assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] end - attribute \src "ls180.v:1772.12-1772.60" - process $proc$ls180.v:1772$3828 + attribute \src "ls180.v:1683.12-1683.60" + process $proc$ls180.v:1683$3567 assign { } { } assign $1\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[63:0] end - attribute \src "ls180.v:1773.12-1773.45" - process $proc$ls180.v:1773$3829 + attribute \src "ls180.v:1684.12-1684.45" + process $proc$ls180.v:1684$3568 assign { } { } assign $1\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[63:0] end - attribute \src "ls180.v:1774.12-1774.53" - process $proc$ls180.v:1774$3830 + attribute \src "ls180.v:1685.12-1685.53" + process $proc$ls180.v:1685$3569 assign { } { } assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] end - attribute \src "ls180.v:1775.5-1775.40" - process $proc$ls180.v:1775$3831 + attribute \src "ls180.v:1686.5-1686.40" + process $proc$ls180.v:1686$3570 assign { } { } assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] end - attribute \src "ls180.v:1776.12-1776.55" - process $proc$ls180.v:1776$3832 + attribute \src "ls180.v:1687.12-1687.55" + process $proc$ls180.v:1687$3571 assign { } { } assign $1\main_sdmem2block_dma_length_storage[31:0] 0 sync always sync init update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] end - attribute \src "ls180.v:1777.5-1777.42" - process $proc$ls180.v:1777$3833 + attribute \src "ls180.v:1688.5-1688.42" + process $proc$ls180.v:1688$3572 assign { } { } assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] end - attribute \src "ls180.v:1778.5-1778.47" - process $proc$ls180.v:1778$3834 + attribute \src "ls180.v:1689.5-1689.47" + process $proc$ls180.v:1689$3573 assign { } { } assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] end - attribute \src "ls180.v:1779.5-1779.42" - process $proc$ls180.v:1779$3835 + attribute \src "ls180.v:169.5-169.40" + process $proc$ls180.v:169$2905 + assign { } { } + assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] + end + attribute \src "ls180.v:1690.5-1690.42" + process $proc$ls180.v:1690$3574 assign { } { } assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] end - attribute \src "ls180.v:1780.5-1780.44" - process $proc$ls180.v:1780$3836 + attribute \src "ls180.v:1691.5-1691.44" + process $proc$ls180.v:1691$3575 assign { } { } assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] end - attribute \src "ls180.v:1782.5-1782.45" - process $proc$ls180.v:1782$3837 + attribute \src "ls180.v:1693.5-1693.45" + process $proc$ls180.v:1693$3576 assign { } { } assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] end - attribute \src "ls180.v:1783.5-1783.40" - process $proc$ls180.v:1783$3838 + attribute \src "ls180.v:1694.5-1694.40" + process $proc$ls180.v:1694$3577 assign { } { } assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] end - attribute \src "ls180.v:1787.12-1787.47" - process $proc$ls180.v:1787$3839 + attribute \src "ls180.v:1698.12-1698.47" + process $proc$ls180.v:1698$3578 assign { } { } assign $1\main_sdmem2block_dma_offset[31:0] 0 sync always sync init update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] end - attribute \src "ls180.v:1799.11-1799.64" - process $proc$ls180.v:1799$3840 + attribute \src "ls180.v:1710.11-1710.64" + process $proc$ls180.v:1710$3579 assign { } { } assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 sync always sync init update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] end - attribute \src "ls180.v:1801.11-1801.48" - process $proc$ls180.v:1801$3841 + attribute \src "ls180.v:1712.11-1712.48" + process $proc$ls180.v:1712$3580 assign { } { } assign $1\main_sdmem2block_converter_mux[2:0] 3'000 sync always sync init update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[2:0] end - attribute \src "ls180.v:1825.11-1825.45" - process $proc$ls180.v:1825$3842 + attribute \src "ls180.v:173.5-173.40" + process $proc$ls180.v:173$2906 + assign { } { } + assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 + sync always + update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:1736.11-1736.45" + process $proc$ls180.v:1736$3581 assign { } { } assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 sync always sync init update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] end - attribute \src "ls180.v:1826.5-1826.41" - process $proc$ls180.v:1826$3843 + attribute \src "ls180.v:1737.5-1737.41" + process $proc$ls180.v:1737$3582 assign { } { } assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 sync always update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] sync init end - attribute \src "ls180.v:1827.11-1827.47" - process $proc$ls180.v:1827$3844 + attribute \src "ls180.v:1738.11-1738.47" + process $proc$ls180.v:1738$3583 assign { } { } assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] end - attribute \src "ls180.v:1828.11-1828.47" - process $proc$ls180.v:1828$3845 + attribute \src "ls180.v:1739.11-1739.47" + process $proc$ls180.v:1739$3584 assign { } { } assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] end - attribute \src "ls180.v:1829.11-1829.50" - process $proc$ls180.v:1829$3846 + attribute \src "ls180.v:1740.11-1740.50" + process $proc$ls180.v:1740$3585 assign { } { } assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 sync always sync init update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:1842.5-1842.36" - process $proc$ls180.v:1842$3847 + attribute \src "ls180.v:1753.5-1753.36" + process $proc$ls180.v:1753$3586 assign { } { } assign $1\builder_converter0_state[0:0] 1'0 sync always sync init update \builder_converter0_state $1\builder_converter0_state[0:0] end - attribute \src "ls180.v:1843.5-1843.41" - process $proc$ls180.v:1843$3848 + attribute \src "ls180.v:1754.5-1754.41" + process $proc$ls180.v:1754$3587 assign { } { } assign $1\builder_converter0_next_state[0:0] 1'0 sync always sync init update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] end - attribute \src "ls180.v:1844.5-1844.57" - process $proc$ls180.v:1844$3849 + attribute \src "ls180.v:1755.5-1755.57" + process $proc$ls180.v:1755$3588 assign { } { } assign $1\main_converter0_counter_converter0_next_value[0:0] 1'0 sync always sync init update \main_converter0_counter_converter0_next_value $1\main_converter0_counter_converter0_next_value[0:0] end - attribute \src "ls180.v:1845.5-1845.60" - process $proc$ls180.v:1845$3850 + attribute \src "ls180.v:1756.5-1756.60" + process $proc$ls180.v:1756$3589 assign { } { } assign $1\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 sync always sync init update \main_converter0_counter_converter0_next_value_ce $1\main_converter0_counter_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:1846.5-1846.36" - process $proc$ls180.v:1846$3851 + attribute \src "ls180.v:1757.5-1757.36" + process $proc$ls180.v:1757$3590 assign { } { } assign $1\builder_converter1_state[0:0] 1'0 sync always sync init update \builder_converter1_state $1\builder_converter1_state[0:0] end - attribute \src "ls180.v:1847.5-1847.41" - process $proc$ls180.v:1847$3852 + attribute \src "ls180.v:1758.5-1758.41" + process $proc$ls180.v:1758$3591 assign { } { } assign $1\builder_converter1_next_state[0:0] 1'0 sync always sync init update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] end - attribute \src "ls180.v:1848.5-1848.57" - process $proc$ls180.v:1848$3853 + attribute \src "ls180.v:1759.5-1759.57" + process $proc$ls180.v:1759$3592 assign { } { } assign $1\main_converter1_counter_converter1_next_value[0:0] 1'0 sync always sync init update \main_converter1_counter_converter1_next_value $1\main_converter1_counter_converter1_next_value[0:0] end - attribute \src "ls180.v:1849.5-1849.60" - process $proc$ls180.v:1849$3854 + attribute \src "ls180.v:176.11-176.37" + process $proc$ls180.v:176$2907 + assign { } { } + assign $1\main_libresocsim_we[7:0] 8'00000000 + sync always + sync init + update \main_libresocsim_we $1\main_libresocsim_we[7:0] + end + attribute \src "ls180.v:1760.5-1760.60" + process $proc$ls180.v:1760$3593 assign { } { } assign $1\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 sync always sync init update \main_converter1_counter_converter1_next_value_ce $1\main_converter1_counter_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:1850.5-1850.36" - process $proc$ls180.v:1850$3855 + attribute \src "ls180.v:1761.5-1761.36" + process $proc$ls180.v:1761$3594 assign { } { } assign $1\builder_converter2_state[0:0] 1'0 sync always sync init update \builder_converter2_state $1\builder_converter2_state[0:0] end - attribute \src "ls180.v:1851.5-1851.41" - process $proc$ls180.v:1851$3856 + attribute \src "ls180.v:1762.5-1762.41" + process $proc$ls180.v:1762$3595 assign { } { } assign $1\builder_converter2_next_state[0:0] 1'0 sync always sync init update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] end - attribute \src "ls180.v:1852.5-1852.60" - process $proc$ls180.v:1852$3857 + attribute \src "ls180.v:1763.5-1763.60" + process $proc$ls180.v:1763$3596 assign { } { } assign $1\main_socbushandler_counter_converter2_next_value[0:0] 1'0 sync always sync init update \main_socbushandler_counter_converter2_next_value $1\main_socbushandler_counter_converter2_next_value[0:0] end - attribute \src "ls180.v:1853.5-1853.63" - process $proc$ls180.v:1853$3858 + attribute \src "ls180.v:1764.5-1764.63" + process $proc$ls180.v:1764$3597 assign { } { } assign $1\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 sync always sync init update \main_socbushandler_counter_converter2_next_value_ce $1\main_socbushandler_counter_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:1854.11-1854.41" - process $proc$ls180.v:1854$3859 + attribute \src "ls180.v:1765.11-1765.41" + process $proc$ls180.v:1765$3598 assign { } { } assign $1\builder_refresher_state[1:0] 2'00 sync always sync init update \builder_refresher_state $1\builder_refresher_state[1:0] end - attribute \src "ls180.v:1855.11-1855.46" - process $proc$ls180.v:1855$3860 + attribute \src "ls180.v:1766.11-1766.46" + process $proc$ls180.v:1766$3599 assign { } { } assign $1\builder_refresher_next_state[1:0] 2'00 sync always sync init update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] end - attribute \src "ls180.v:1856.11-1856.44" - process $proc$ls180.v:1856$3861 + attribute \src "ls180.v:1767.11-1767.44" + process $proc$ls180.v:1767$3600 assign { } { } assign $1\builder_bankmachine0_state[2:0] 3'000 sync always sync init update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] end - attribute \src "ls180.v:1857.11-1857.49" - process $proc$ls180.v:1857$3862 + attribute \src "ls180.v:1768.11-1768.49" + process $proc$ls180.v:1768$3601 assign { } { } assign $1\builder_bankmachine0_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:1858.11-1858.44" - process $proc$ls180.v:1858$3863 + attribute \src "ls180.v:1769.11-1769.44" + process $proc$ls180.v:1769$3602 assign { } { } assign $1\builder_bankmachine1_state[2:0] 3'000 sync always sync init update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] end - attribute \src "ls180.v:1859.11-1859.49" - process $proc$ls180.v:1859$3864 + attribute \src "ls180.v:1770.11-1770.49" + process $proc$ls180.v:1770$3603 assign { } { } assign $1\builder_bankmachine1_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:1860.11-1860.44" - process $proc$ls180.v:1860$3865 + attribute \src "ls180.v:1771.11-1771.44" + process $proc$ls180.v:1771$3604 assign { } { } assign $1\builder_bankmachine2_state[2:0] 3'000 sync always sync init update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] end - attribute \src "ls180.v:1861.11-1861.49" - process $proc$ls180.v:1861$3866 + attribute \src "ls180.v:1772.11-1772.49" + process $proc$ls180.v:1772$3605 assign { } { } assign $1\builder_bankmachine2_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:1862.11-1862.44" - process $proc$ls180.v:1862$3867 + attribute \src "ls180.v:1773.11-1773.44" + process $proc$ls180.v:1773$3606 assign { } { } assign $1\builder_bankmachine3_state[2:0] 3'000 sync always sync init update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] end - attribute \src "ls180.v:1863.11-1863.49" - process $proc$ls180.v:1863$3868 + attribute \src "ls180.v:1774.11-1774.49" + process $proc$ls180.v:1774$3607 assign { } { } assign $1\builder_bankmachine3_next_state[2:0] 3'000 sync always sync init update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:1864.11-1864.43" - process $proc$ls180.v:1864$3869 + attribute \src "ls180.v:1775.11-1775.43" + process $proc$ls180.v:1775$3608 assign { } { } assign $1\builder_multiplexer_state[2:0] 3'000 sync always sync init update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] end - attribute \src "ls180.v:1865.11-1865.48" - process $proc$ls180.v:1865$3870 + attribute \src "ls180.v:1776.11-1776.48" + process $proc$ls180.v:1776$3609 assign { } { } assign $1\builder_multiplexer_next_state[2:0] 3'000 sync always sync init update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] end - attribute \src "ls180.v:1878.5-1878.27" - process $proc$ls180.v:1878$3871 + attribute \src "ls180.v:178.12-178.49" + process $proc$ls180.v:178$2908 + assign { } { } + assign $1\main_libresocsim_load_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] + end + attribute \src "ls180.v:1789.5-1789.27" + process $proc$ls180.v:1789$3610 assign { } { } assign $0\builder_locked0[0:0] 1'0 sync always update \builder_locked0 $0\builder_locked0[0:0] sync init end - attribute \src "ls180.v:1879.5-1879.27" - process $proc$ls180.v:1879$3872 + attribute \src "ls180.v:179.5-179.36" + process $proc$ls180.v:179$2909 + assign { } { } + assign $1\main_libresocsim_load_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] + end + attribute \src "ls180.v:1790.5-1790.27" + process $proc$ls180.v:1790$3611 assign { } { } assign $0\builder_locked1[0:0] 1'0 sync always update \builder_locked1 $0\builder_locked1[0:0] sync init end - attribute \src "ls180.v:1880.5-1880.27" - process $proc$ls180.v:1880$3873 + attribute \src "ls180.v:1791.5-1791.27" + process $proc$ls180.v:1791$3612 assign { } { } assign $0\builder_locked2[0:0] 1'0 sync always update \builder_locked2 $0\builder_locked2[0:0] sync init end - attribute \src "ls180.v:1881.5-1881.27" - process $proc$ls180.v:1881$3874 + attribute \src "ls180.v:1792.5-1792.27" + process $proc$ls180.v:1792$3613 assign { } { } assign $0\builder_locked3[0:0] 1'0 sync always update \builder_locked3 $0\builder_locked3[0:0] sync init end - attribute \src "ls180.v:1882.5-1882.42" - process $proc$ls180.v:1882$3875 + attribute \src "ls180.v:1793.5-1793.42" + process $proc$ls180.v:1793$3614 assign { } { } assign $1\builder_new_master_wdata_ready[0:0] 1'0 sync always sync init update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] end - attribute \src "ls180.v:1883.5-1883.43" - process $proc$ls180.v:1883$3876 + attribute \src "ls180.v:1794.5-1794.43" + process $proc$ls180.v:1794$3615 assign { } { } assign $1\builder_new_master_rdata_valid0[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] end - attribute \src "ls180.v:1884.5-1884.43" - process $proc$ls180.v:1884$3877 + attribute \src "ls180.v:1795.5-1795.43" + process $proc$ls180.v:1795$3616 assign { } { } assign $1\builder_new_master_rdata_valid1[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] end - attribute \src "ls180.v:1885.5-1885.43" - process $proc$ls180.v:1885$3878 + attribute \src "ls180.v:1796.5-1796.43" + process $proc$ls180.v:1796$3617 assign { } { } assign $1\builder_new_master_rdata_valid2[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] end - attribute \src "ls180.v:1886.5-1886.43" - process $proc$ls180.v:1886$3879 + attribute \src "ls180.v:1797.5-1797.43" + process $proc$ls180.v:1797$3618 assign { } { } assign $1\builder_new_master_rdata_valid3[0:0] 1'0 sync always sync init update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] end - attribute \src "ls180.v:1887.5-1887.35" - process $proc$ls180.v:1887$3880 + attribute \src "ls180.v:1798.5-1798.35" + process $proc$ls180.v:1798$3619 assign { } { } assign $1\builder_converter_state[0:0] 1'0 sync always sync init update \builder_converter_state $1\builder_converter_state[0:0] end - attribute \src "ls180.v:1888.5-1888.40" - process $proc$ls180.v:1888$3881 + attribute \src "ls180.v:1799.5-1799.40" + process $proc$ls180.v:1799$3620 assign { } { } assign $1\builder_converter_next_state[0:0] 1'0 sync always sync init update \builder_converter_next_state $1\builder_converter_next_state[0:0] end - attribute \src "ls180.v:1889.5-1889.55" - process $proc$ls180.v:1889$3882 + attribute \src "ls180.v:180.12-180.51" + process $proc$ls180.v:180$2910 assign { } { } - assign $1\main_converter_counter_converter_next_value[0:0] 1'0 + assign $1\main_libresocsim_reload_storage[31:0] 0 sync always sync init - update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] + update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] end - attribute \src "ls180.v:189.12-189.78" - process $proc$ls180.v:189$3154 + attribute \src "ls180.v:1800.5-1800.55" + process $proc$ls180.v:1800$3621 assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 + assign $1\main_converter_counter_converter_next_value[0:0] 1'0 sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] sync init + update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] end - attribute \src "ls180.v:1890.5-1890.58" - process $proc$ls180.v:1890$3883 + attribute \src "ls180.v:1801.5-1801.58" + process $proc$ls180.v:1801$3622 assign { } { } assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 sync always sync init update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] end - attribute \src "ls180.v:1891.11-1891.42" - process $proc$ls180.v:1891$3884 + attribute \src "ls180.v:1802.11-1802.42" + process $proc$ls180.v:1802$3623 assign { } { } assign $1\builder_spimaster0_state[1:0] 2'00 sync always sync init update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] end - attribute \src "ls180.v:1892.11-1892.47" - process $proc$ls180.v:1892$3885 + attribute \src "ls180.v:1803.11-1803.47" + process $proc$ls180.v:1803$3624 assign { } { } assign $1\builder_spimaster0_next_state[1:0] 2'00 sync always sync init update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] end - attribute \src "ls180.v:1893.11-1893.62" - process $proc$ls180.v:1893$3886 + attribute \src "ls180.v:1804.11-1804.62" + process $proc$ls180.v:1804$3625 assign { } { } assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 sync always sync init update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0] end - attribute \src "ls180.v:1894.5-1894.59" - process $proc$ls180.v:1894$3887 + attribute \src "ls180.v:1805.5-1805.59" + process $proc$ls180.v:1805$3626 assign { } { } assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 sync always sync init update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] end - attribute \src "ls180.v:1895.11-1895.42" - process $proc$ls180.v:1895$3888 + attribute \src "ls180.v:1806.11-1806.42" + process $proc$ls180.v:1806$3627 assign { } { } assign $1\builder_spimaster1_state[1:0] 2'00 sync always sync init update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] end - attribute \src "ls180.v:1896.11-1896.47" - process $proc$ls180.v:1896$3889 + attribute \src "ls180.v:1807.11-1807.47" + process $proc$ls180.v:1807$3628 assign { } { } assign $1\builder_spimaster1_next_state[1:0] 2'00 sync always sync init update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] end - attribute \src "ls180.v:1897.11-1897.60" - process $proc$ls180.v:1897$3890 + attribute \src "ls180.v:1808.11-1808.60" + process $proc$ls180.v:1808$3629 assign { } { } assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 sync always sync init update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0] end - attribute \src "ls180.v:1898.5-1898.57" - process $proc$ls180.v:1898$3891 + attribute \src "ls180.v:1809.5-1809.57" + process $proc$ls180.v:1809$3630 assign { } { } assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 sync always sync init update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] end - attribute \src "ls180.v:1899.5-1899.41" - process $proc$ls180.v:1899$3892 + attribute \src "ls180.v:181.5-181.38" + process $proc$ls180.v:181$2911 + assign { } { } + assign $1\main_libresocsim_reload_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] + end + attribute \src "ls180.v:1810.5-1810.41" + process $proc$ls180.v:1810$3631 assign { } { } assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] end - attribute \src "ls180.v:1900.5-1900.46" - process $proc$ls180.v:1900$3893 + attribute \src "ls180.v:1811.5-1811.46" + process $proc$ls180.v:1811$3632 assign { } { } assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] end - attribute \src "ls180.v:1901.11-1901.66" - process $proc$ls180.v:1901$3894 + attribute \src "ls180.v:1812.11-1812.66" + process $proc$ls180.v:1812$3633 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] end - attribute \src "ls180.v:1902.5-1902.63" - process $proc$ls180.v:1902$3895 + attribute \src "ls180.v:1813.5-1813.63" + process $proc$ls180.v:1813$3634 assign { } { } assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end - attribute \src "ls180.v:1903.11-1903.47" - process $proc$ls180.v:1903$3896 + attribute \src "ls180.v:1814.11-1814.47" + process $proc$ls180.v:1814$3635 assign { } { } assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 sync always sync init update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] end - attribute \src "ls180.v:1904.11-1904.52" - process $proc$ls180.v:1904$3897 + attribute \src "ls180.v:1815.11-1815.52" + process $proc$ls180.v:1815$3636 assign { } { } assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 sync always sync init update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] end - attribute \src "ls180.v:1905.11-1905.66" - process $proc$ls180.v:1905$3898 + attribute \src "ls180.v:1816.11-1816.66" + process $proc$ls180.v:1816$3637 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] end - attribute \src "ls180.v:1906.5-1906.63" - process $proc$ls180.v:1906$3899 + attribute \src "ls180.v:1817.5-1817.63" + process $proc$ls180.v:1817$3638 assign { } { } assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end - attribute \src "ls180.v:1907.11-1907.47" - process $proc$ls180.v:1907$3900 + attribute \src "ls180.v:1818.11-1818.47" + process $proc$ls180.v:1818$3639 assign { } { } assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] end - attribute \src "ls180.v:1908.11-1908.52" - process $proc$ls180.v:1908$3901 + attribute \src "ls180.v:1819.11-1819.52" + process $proc$ls180.v:1819$3640 assign { } { } assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] end - attribute \src "ls180.v:1909.11-1909.67" - process $proc$ls180.v:1909$3902 + attribute \src "ls180.v:182.5-182.39" + process $proc$ls180.v:182$2912 + assign { } { } + assign $1\main_libresocsim_en_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] + end + attribute \src "ls180.v:1820.11-1820.67" + process $proc$ls180.v:1820$3641 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 sync always sync init update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] end - attribute \src "ls180.v:1910.5-1910.64" - process $proc$ls180.v:1910$3903 + attribute \src "ls180.v:1821.5-1821.64" + process $proc$ls180.v:1821$3642 assign { } { } assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] end - attribute \src "ls180.v:1911.12-1911.71" - process $proc$ls180.v:1911$3904 + attribute \src "ls180.v:1822.12-1822.71" + process $proc$ls180.v:1822$3643 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 sync always sync init update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] end - attribute \src "ls180.v:1912.5-1912.66" - process $proc$ls180.v:1912$3905 + attribute \src "ls180.v:1823.5-1823.66" + process $proc$ls180.v:1823$3644 assign { } { } assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] end - attribute \src "ls180.v:1913.5-1913.66" - process $proc$ls180.v:1913$3906 + attribute \src "ls180.v:1824.5-1824.66" + process $proc$ls180.v:1824$3645 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] end - attribute \src "ls180.v:1914.5-1914.69" - process $proc$ls180.v:1914$3907 + attribute \src "ls180.v:1825.5-1825.69" + process $proc$ls180.v:1825$3646 assign { } { } assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end - attribute \src "ls180.v:1915.5-1915.41" - process $proc$ls180.v:1915$3908 + attribute \src "ls180.v:1826.5-1826.41" + process $proc$ls180.v:1826$3647 assign { } { } assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] end - attribute \src "ls180.v:1916.5-1916.46" - process $proc$ls180.v:1916$3909 + attribute \src "ls180.v:1827.5-1827.46" + process $proc$ls180.v:1827$3648 assign { } { } assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 sync always sync init update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] end - attribute \src "ls180.v:1917.5-1917.66" - process $proc$ls180.v:1917$3910 + attribute \src "ls180.v:1828.5-1828.66" + process $proc$ls180.v:1828$3649 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] end - attribute \src "ls180.v:1918.5-1918.69" - process $proc$ls180.v:1918$3911 + attribute \src "ls180.v:1829.5-1829.69" + process $proc$ls180.v:1829$3650 assign { } { } assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] end - attribute \src "ls180.v:1919.11-1919.41" - process $proc$ls180.v:1919$3912 + attribute \src "ls180.v:183.5-183.34" + process $proc$ls180.v:183$2913 + assign { } { } + assign $1\main_libresocsim_en_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] + end + attribute \src "ls180.v:1830.11-1830.41" + process $proc$ls180.v:1830$3651 assign { } { } assign $1\builder_sdphy_fsm_state[2:0] 3'000 sync always sync init update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] end - attribute \src "ls180.v:1920.11-1920.46" - process $proc$ls180.v:1920$3913 + attribute \src "ls180.v:1831.11-1831.46" + process $proc$ls180.v:1831$3652 assign { } { } assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] end - attribute \src "ls180.v:1921.11-1921.61" - process $proc$ls180.v:1921$3914 + attribute \src "ls180.v:1832.11-1832.61" + process $proc$ls180.v:1832$3653 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 sync always sync init update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] end - attribute \src "ls180.v:1922.5-1922.58" - process $proc$ls180.v:1922$3915 + attribute \src "ls180.v:1833.5-1833.58" + process $proc$ls180.v:1833$3654 assign { } { } assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 sync always sync init update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:1923.11-1923.48" - process $proc$ls180.v:1923$3916 + attribute \src "ls180.v:1834.11-1834.48" + process $proc$ls180.v:1834$3655 assign { } { } assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] end - attribute \src "ls180.v:1924.11-1924.53" - process $proc$ls180.v:1924$3917 + attribute \src "ls180.v:1835.11-1835.53" + process $proc$ls180.v:1835$3656 assign { } { } assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 sync always sync init update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] end - attribute \src "ls180.v:1925.11-1925.70" - process $proc$ls180.v:1925$3918 + attribute \src "ls180.v:1836.11-1836.70" + process $proc$ls180.v:1836$3657 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 sync always sync init update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] end - attribute \src "ls180.v:1926.5-1926.66" - process $proc$ls180.v:1926$3919 + attribute \src "ls180.v:1837.5-1837.66" + process $proc$ls180.v:1837$3658 assign { } { } assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] end - attribute \src "ls180.v:1927.12-1927.73" - process $proc$ls180.v:1927$3920 + attribute \src "ls180.v:1838.12-1838.73" + process $proc$ls180.v:1838$3659 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 sync always sync init update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] end - attribute \src "ls180.v:1928.5-1928.68" - process $proc$ls180.v:1928$3921 + attribute \src "ls180.v:1839.5-1839.68" + process $proc$ls180.v:1839$3660 assign { } { } assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] end - attribute \src "ls180.v:1929.5-1929.69" - process $proc$ls180.v:1929$3922 + attribute \src "ls180.v:184.5-184.49" + process $proc$ls180.v:184$2914 + assign { } { } + assign $1\main_libresocsim_update_value_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] + end + attribute \src "ls180.v:1840.5-1840.69" + process $proc$ls180.v:1840$3661 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] end - attribute \src "ls180.v:1930.5-1930.72" - process $proc$ls180.v:1930$3923 + attribute \src "ls180.v:1841.5-1841.72" + process $proc$ls180.v:1841$3662 assign { } { } assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end - attribute \src "ls180.v:1931.5-1931.52" - process $proc$ls180.v:1931$3924 + attribute \src "ls180.v:1842.5-1842.52" + process $proc$ls180.v:1842$3663 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 sync always sync init update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] end - attribute \src "ls180.v:1932.5-1932.57" - process $proc$ls180.v:1932$3925 + attribute \src "ls180.v:1843.5-1843.57" + process $proc$ls180.v:1843$3664 assign { } { } assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 sync always sync init update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] end - attribute \src "ls180.v:1933.12-1933.93" - process $proc$ls180.v:1933$3926 + attribute \src "ls180.v:1844.12-1844.93" + process $proc$ls180.v:1844$3665 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] end - attribute \src "ls180.v:1934.5-1934.88" - process $proc$ls180.v:1934$3927 + attribute \src "ls180.v:1845.5-1845.88" + process $proc$ls180.v:1845$3666 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] end - attribute \src "ls180.v:1935.12-1935.93" - process $proc$ls180.v:1935$3928 + attribute \src "ls180.v:1846.12-1846.93" + process $proc$ls180.v:1846$3667 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] end - attribute \src "ls180.v:1936.5-1936.88" - process $proc$ls180.v:1936$3929 + attribute \src "ls180.v:1847.5-1847.88" + process $proc$ls180.v:1847$3668 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] end - attribute \src "ls180.v:1937.12-1937.93" - process $proc$ls180.v:1937$3930 + attribute \src "ls180.v:1848.12-1848.93" + process $proc$ls180.v:1848$3669 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] end - attribute \src "ls180.v:1938.5-1938.88" - process $proc$ls180.v:1938$3931 + attribute \src "ls180.v:1849.5-1849.88" + process $proc$ls180.v:1849$3670 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] end - attribute \src "ls180.v:1939.12-1939.93" - process $proc$ls180.v:1939$3932 + attribute \src "ls180.v:185.5-185.44" + process $proc$ls180.v:185$2915 + assign { } { } + assign $1\main_libresocsim_update_value_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] + end + attribute \src "ls180.v:1850.12-1850.93" + process $proc$ls180.v:1850$3671 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 sync always sync init update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] end - attribute \src "ls180.v:1940.5-1940.88" - process $proc$ls180.v:1940$3933 + attribute \src "ls180.v:1851.5-1851.88" + process $proc$ls180.v:1851$3672 assign { } { } assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] end - attribute \src "ls180.v:1941.11-1941.87" - process $proc$ls180.v:1941$3934 + attribute \src "ls180.v:1852.11-1852.87" + process $proc$ls180.v:1852$3673 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 sync always sync init update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] end - attribute \src "ls180.v:1942.5-1942.84" - process $proc$ls180.v:1942$3935 + attribute \src "ls180.v:1853.5-1853.84" + process $proc$ls180.v:1853$3674 assign { } { } assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 sync always sync init update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end - attribute \src "ls180.v:1943.11-1943.42" - process $proc$ls180.v:1943$3936 + attribute \src "ls180.v:1854.11-1854.42" + process $proc$ls180.v:1854$3675 assign { } { } assign $1\builder_sdcore_fsm_state[2:0] 3'000 sync always sync init update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] end - attribute \src "ls180.v:1944.11-1944.47" - process $proc$ls180.v:1944$3937 + attribute \src "ls180.v:1855.11-1855.47" + process $proc$ls180.v:1855$3676 assign { } { } assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 sync always sync init update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] end - attribute \src "ls180.v:1945.5-1945.55" - process $proc$ls180.v:1945$3938 + attribute \src "ls180.v:1856.5-1856.55" + process $proc$ls180.v:1856$3677 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] end - attribute \src "ls180.v:1946.5-1946.58" - process $proc$ls180.v:1946$3939 + attribute \src "ls180.v:1857.5-1857.58" + process $proc$ls180.v:1857$3678 assign { } { } assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 sync always sync init update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] end - attribute \src "ls180.v:1947.5-1947.56" - process $proc$ls180.v:1947$3940 + attribute \src "ls180.v:1858.5-1858.56" + process $proc$ls180.v:1858$3679 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 sync always sync init update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] end - attribute \src "ls180.v:1948.5-1948.59" - process $proc$ls180.v:1948$3941 + attribute \src "ls180.v:1859.5-1859.59" + process $proc$ls180.v:1859$3680 assign { } { } assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 sync always sync init update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] end - attribute \src "ls180.v:1949.11-1949.62" - process $proc$ls180.v:1949$3942 + attribute \src "ls180.v:186.12-186.49" + process $proc$ls180.v:186$2916 + assign { } { } + assign $1\main_libresocsim_value_status[31:0] 0 + sync always + sync init + update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] + end + attribute \src "ls180.v:1860.11-1860.62" + process $proc$ls180.v:1860$3681 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 sync always sync init update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] end - attribute \src "ls180.v:1950.5-1950.59" - process $proc$ls180.v:1950$3943 + attribute \src "ls180.v:1861.5-1861.59" + process $proc$ls180.v:1861$3682 assign { } { } assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 sync always sync init update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] end - attribute \src "ls180.v:1951.12-1951.65" - process $proc$ls180.v:1951$3944 + attribute \src "ls180.v:1862.12-1862.65" + process $proc$ls180.v:1862$3683 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 sync always sync init update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] end - attribute \src "ls180.v:1952.5-1952.60" - process $proc$ls180.v:1952$3945 + attribute \src "ls180.v:1863.5-1863.60" + process $proc$ls180.v:1863$3684 assign { } { } assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 sync always sync init update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] end - attribute \src "ls180.v:1953.5-1953.56" - process $proc$ls180.v:1953$3946 + attribute \src "ls180.v:1864.5-1864.56" + process $proc$ls180.v:1864$3685 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] end - attribute \src "ls180.v:1954.5-1954.59" - process $proc$ls180.v:1954$3947 + attribute \src "ls180.v:1865.5-1865.59" + process $proc$ls180.v:1865$3686 assign { } { } assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 sync always sync init update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] end - attribute \src "ls180.v:1955.5-1955.58" - process $proc$ls180.v:1955$3948 + attribute \src "ls180.v:1866.5-1866.58" + process $proc$ls180.v:1866$3687 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] end - attribute \src "ls180.v:1956.5-1956.61" - process $proc$ls180.v:1956$3949 + attribute \src "ls180.v:1867.5-1867.61" + process $proc$ls180.v:1867$3688 assign { } { } assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 sync always sync init update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] end - attribute \src "ls180.v:1957.5-1957.57" - process $proc$ls180.v:1957$3950 + attribute \src "ls180.v:1868.5-1868.57" + process $proc$ls180.v:1868$3689 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 sync always sync init update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] end - attribute \src "ls180.v:1958.5-1958.60" - process $proc$ls180.v:1958$3951 + attribute \src "ls180.v:1869.5-1869.60" + process $proc$ls180.v:1869$3690 assign { } { } assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 sync always sync init update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] end - attribute \src "ls180.v:1959.5-1959.59" - process $proc$ls180.v:1959$3952 + attribute \src "ls180.v:1870.5-1870.59" + process $proc$ls180.v:1870$3691 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] end - attribute \src "ls180.v:1960.5-1960.62" - process $proc$ls180.v:1960$3953 + attribute \src "ls180.v:1871.5-1871.62" + process $proc$ls180.v:1871$3692 assign { } { } assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 sync always sync init update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] end - attribute \src "ls180.v:1961.13-1961.76" - process $proc$ls180.v:1961$3954 + attribute \src "ls180.v:1872.13-1872.76" + process $proc$ls180.v:1872$3693 assign { } { } assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] end - attribute \src "ls180.v:1962.5-1962.69" - process $proc$ls180.v:1962$3955 + attribute \src "ls180.v:1873.5-1873.69" + process $proc$ls180.v:1873$3694 assign { } { } assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 sync always sync init update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end - attribute \src "ls180.v:1963.11-1963.46" - process $proc$ls180.v:1963$3956 + attribute \src "ls180.v:1874.11-1874.46" + process $proc$ls180.v:1874$3695 assign { } { } assign $1\builder_sdblock2memdma_state[1:0] 2'00 sync always sync init update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] end - attribute \src "ls180.v:1964.11-1964.51" - process $proc$ls180.v:1964$3957 + attribute \src "ls180.v:1875.11-1875.51" + process $proc$ls180.v:1875$3696 assign { } { } assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 sync always sync init update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] end - attribute \src "ls180.v:1965.12-1965.87" - process $proc$ls180.v:1965$3958 + attribute \src "ls180.v:1876.12-1876.87" + process $proc$ls180.v:1876$3697 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] end - attribute \src "ls180.v:1966.5-1966.82" - process $proc$ls180.v:1966$3959 + attribute \src "ls180.v:1877.5-1877.82" + process $proc$ls180.v:1877$3698 assign { } { } assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 sync always sync init update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end - attribute \src "ls180.v:1967.5-1967.44" - process $proc$ls180.v:1967$3960 + attribute \src "ls180.v:1878.5-1878.44" + process $proc$ls180.v:1878$3699 assign { } { } assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 sync always sync init update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] end - attribute \src "ls180.v:1968.5-1968.49" - process $proc$ls180.v:1968$3961 + attribute \src "ls180.v:1879.5-1879.49" + process $proc$ls180.v:1879$3700 assign { } { } assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 sync always sync init update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] end - attribute \src "ls180.v:1969.12-1969.75" - process $proc$ls180.v:1969$3962 + attribute \src "ls180.v:1880.12-1880.75" + process $proc$ls180.v:1880$3701 assign { } { } assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] end - attribute \src "ls180.v:1970.5-1970.70" - process $proc$ls180.v:1970$3963 + attribute \src "ls180.v:1881.5-1881.70" + process $proc$ls180.v:1881$3702 assign { } { } assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:1971.11-1971.60" - process $proc$ls180.v:1971$3964 + attribute \src "ls180.v:1882.11-1882.60" + process $proc$ls180.v:1882$3703 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 sync always sync init update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] end - attribute \src "ls180.v:1972.11-1972.65" - process $proc$ls180.v:1972$3965 + attribute \src "ls180.v:1883.11-1883.65" + process $proc$ls180.v:1883$3704 assign { } { } assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 sync always sync init update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] end - attribute \src "ls180.v:1973.12-1973.87" - process $proc$ls180.v:1973$3966 + attribute \src "ls180.v:1884.12-1884.87" + process $proc$ls180.v:1884$3705 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 sync always sync init update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] end - attribute \src "ls180.v:1974.5-1974.82" - process $proc$ls180.v:1974$3967 + attribute \src "ls180.v:1885.5-1885.82" + process $proc$ls180.v:1885$3706 assign { } { } assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 sync always sync init update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end - attribute \src "ls180.v:1975.12-1975.43" - process $proc$ls180.v:1975$3968 + attribute \src "ls180.v:1886.12-1886.43" + process $proc$ls180.v:1886$3707 assign { } { } assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 sync always sync init update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] end - attribute \src "ls180.v:1976.5-1976.34" - process $proc$ls180.v:1976$3969 + attribute \src "ls180.v:1887.5-1887.34" + process $proc$ls180.v:1887$3708 assign { } { } assign $1\builder_libresocsim_we[0:0] 1'0 sync always sync init update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] end - attribute \src "ls180.v:1977.11-1977.43" - process $proc$ls180.v:1977$3970 + attribute \src "ls180.v:1888.11-1888.43" + process $proc$ls180.v:1888$3709 assign { } { } assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 sync always sync init update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] end - attribute \src "ls180.v:1979.12-1979.52" - process $proc$ls180.v:1979$3971 + attribute \src "ls180.v:1890.12-1890.52" + process $proc$ls180.v:1890$3710 assign { } { } assign $0\builder_libresocsim_wishbone_adr[29:0] 30'000000000000000000000000000000 sync always update \builder_libresocsim_wishbone_adr $0\builder_libresocsim_wishbone_adr[29:0] sync init end - attribute \src "ls180.v:1980.12-1980.54" - process $proc$ls180.v:1980$3972 + attribute \src "ls180.v:1891.12-1891.54" + process $proc$ls180.v:1891$3711 assign { } { } assign $0\builder_libresocsim_wishbone_dat_w[31:0] 0 sync always update \builder_libresocsim_wishbone_dat_w $0\builder_libresocsim_wishbone_dat_w[31:0] sync init end - attribute \src "ls180.v:1981.12-1981.54" - process $proc$ls180.v:1981$3973 + attribute \src "ls180.v:1892.12-1892.54" + process $proc$ls180.v:1892$3712 assign { } { } assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 sync always sync init update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] end - attribute \src "ls180.v:1982.11-1982.50" - process $proc$ls180.v:1982$3974 + attribute \src "ls180.v:1893.11-1893.50" + process $proc$ls180.v:1893$3713 assign { } { } assign $0\builder_libresocsim_wishbone_sel[3:0] 4'0000 sync always update \builder_libresocsim_wishbone_sel $0\builder_libresocsim_wishbone_sel[3:0] sync init end - attribute \src "ls180.v:1983.5-1983.44" - process $proc$ls180.v:1983$3975 + attribute \src "ls180.v:1894.5-1894.44" + process $proc$ls180.v:1894$3714 assign { } { } assign $0\builder_libresocsim_wishbone_cyc[0:0] 1'0 sync always update \builder_libresocsim_wishbone_cyc $0\builder_libresocsim_wishbone_cyc[0:0] sync init end - attribute \src "ls180.v:1984.5-1984.44" - process $proc$ls180.v:1984$3976 + attribute \src "ls180.v:1895.5-1895.44" + process $proc$ls180.v:1895$3715 assign { } { } assign $0\builder_libresocsim_wishbone_stb[0:0] 1'0 sync always update \builder_libresocsim_wishbone_stb $0\builder_libresocsim_wishbone_stb[0:0] sync init end - attribute \src "ls180.v:1985.5-1985.44" - process $proc$ls180.v:1985$3977 + attribute \src "ls180.v:1896.5-1896.44" + process $proc$ls180.v:1896$3716 assign { } { } assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 sync always sync init update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] end - attribute \src "ls180.v:1986.5-1986.43" - process $proc$ls180.v:1986$3978 + attribute \src "ls180.v:1897.5-1897.43" + process $proc$ls180.v:1897$3717 assign { } { } assign $0\builder_libresocsim_wishbone_we[0:0] 1'0 sync always update \builder_libresocsim_wishbone_we $0\builder_libresocsim_wishbone_we[0:0] sync init end - attribute \src "ls180.v:1989.12-1989.65" - process $proc$ls180.v:1989$3979 + attribute \src "ls180.v:190.5-190.41" + process $proc$ls180.v:190$2917 + assign { } { } + assign $1\main_libresocsim_zero_pending[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] + end + attribute \src "ls180.v:1900.12-1900.65" + process $proc$ls180.v:1900$3718 assign { } { } assign $0\builder_libresocsim_converted_interface_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always update \builder_libresocsim_converted_interface_dat_r $0\builder_libresocsim_converted_interface_dat_r[63:0] sync init end - attribute \src "ls180.v:1993.5-1993.55" - process $proc$ls180.v:1993$3980 + attribute \src "ls180.v:1904.5-1904.55" + process $proc$ls180.v:1904$3719 assign { } { } assign $0\builder_libresocsim_converted_interface_ack[0:0] 1'0 sync always update \builder_libresocsim_converted_interface_ack $0\builder_libresocsim_converted_interface_ack[0:0] sync init end - attribute \src "ls180.v:1997.5-1997.55" - process $proc$ls180.v:1997$3981 + attribute \src "ls180.v:1908.5-1908.55" + process $proc$ls180.v:1908$3720 assign { } { } assign $0\builder_libresocsim_converted_interface_err[0:0] 1'0 sync always update \builder_libresocsim_converted_interface_err $0\builder_libresocsim_converted_interface_err[0:0] sync init end - attribute \src "ls180.v:2000.12-2000.40" - process $proc$ls180.v:2000$3982 + attribute \src "ls180.v:1911.12-1911.40" + process $proc$ls180.v:1911$3721 assign { } { } assign $1\builder_shared_dat_r[31:0] 0 sync always sync init update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] end - attribute \src "ls180.v:2004.5-2004.30" - process $proc$ls180.v:2004$3983 + attribute \src "ls180.v:1915.5-1915.30" + process $proc$ls180.v:1915$3722 assign { } { } assign $1\builder_shared_ack[0:0] 1'0 sync always sync init update \builder_shared_ack $1\builder_shared_ack[0:0] end - attribute \src "ls180.v:201.5-201.72" - process $proc$ls180.v:201$3155 + attribute \src "ls180.v:192.5-192.39" + process $proc$ls180.v:192$2918 assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 + assign $1\main_libresocsim_zero_clear[0:0] 1'0 sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] sync init + update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:2010.11-2010.31" - process $proc$ls180.v:2010$3984 + attribute \src "ls180.v:1921.11-1921.31" + process $proc$ls180.v:1921$3723 assign { } { } assign $1\builder_grant[2:0] 3'000 sync always sync init update \builder_grant $1\builder_grant[2:0] end - attribute \src "ls180.v:2011.12-2011.37" - process $proc$ls180.v:2011$3985 + attribute \src "ls180.v:1922.11-1922.35" + process $proc$ls180.v:1922$3724 assign { } { } - assign $1\builder_slave_sel[12:0] 13'0000000000000 + assign $1\builder_slave_sel[5:0] 6'000000 sync always sync init - update \builder_slave_sel $1\builder_slave_sel[12:0] + update \builder_slave_sel $1\builder_slave_sel[5:0] end - attribute \src "ls180.v:2012.12-2012.39" - process $proc$ls180.v:2012$3986 + attribute \src "ls180.v:1923.11-1923.37" + process $proc$ls180.v:1923$3725 assign { } { } - assign $1\builder_slave_sel_r[12:0] 13'0000000000000 + assign $1\builder_slave_sel_r[5:0] 6'000000 sync always sync init - update \builder_slave_sel_r $1\builder_slave_sel_r[12:0] + update \builder_slave_sel_r $1\builder_slave_sel_r[5:0] end - attribute \src "ls180.v:2013.5-2013.25" - process $proc$ls180.v:2013$3987 + attribute \src "ls180.v:1924.5-1924.25" + process $proc$ls180.v:1924$3726 assign { } { } assign $1\builder_error[0:0] 1'0 sync always sync init update \builder_error $1\builder_error[0:0] end - attribute \src "ls180.v:2016.12-2016.39" - process $proc$ls180.v:2016$3988 + attribute \src "ls180.v:1927.12-1927.39" + process $proc$ls180.v:1927$3727 assign { } { } assign $1\builder_count[19:0] 20'11110100001001000000 sync always sync init update \builder_count $1\builder_count[19:0] end - attribute \src "ls180.v:2020.11-2020.51" - process $proc$ls180.v:2020$3989 + attribute \src "ls180.v:193.5-193.45" + process $proc$ls180.v:193$2919 assign { } { } - assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 sync always sync init - update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] + update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] end - attribute \src "ls180.v:204.11-204.79" - process $proc$ls180.v:204$3156 + attribute \src "ls180.v:1931.11-1931.51" + process $proc$ls180.v:1931$3728 assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] 4'0000 + assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] sync init + update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2061.11-2061.51" - process $proc$ls180.v:2061$3990 + attribute \src "ls180.v:1972.11-1972.51" + process $proc$ls180.v:1972$3729 assign { } { } assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2090.11-2090.51" - process $proc$ls180.v:2090$3991 + attribute \src "ls180.v:2001.11-2001.51" + process $proc$ls180.v:2001$3730 assign { } { } assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2103.11-2103.51" - process $proc$ls180.v:2103$3992 + attribute \src "ls180.v:2014.11-2014.51" + process $proc$ls180.v:2014$3731 assign { } { } assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:213.5-213.40" - process $proc$ls180.v:213$3157 + attribute \src "ls180.v:202.5-202.49" + process $proc$ls180.v:202$2920 assign { } { } - assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] - end - attribute \src "ls180.v:2144.11-2144.51" - process $proc$ls180.v:2144$3993 - assign { } { } - assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 sync always sync init - update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] + update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] end - attribute \src "ls180.v:217.5-217.40" - process $proc$ls180.v:217$3158 + attribute \src "ls180.v:203.5-203.44" + process $proc$ls180.v:203$2921 assign { } { } - assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 + assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 sync always - update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] sync init + update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] end - attribute \src "ls180.v:2185.11-2185.51" - process $proc$ls180.v:2185$3994 + attribute \src "ls180.v:204.12-204.42" + process $proc$ls180.v:204$2922 assign { } { } - assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_libresocsim_value[31:0] 0 sync always sync init - update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] + update \main_libresocsim_value $1\main_libresocsim_value[31:0] end - attribute \src "ls180.v:220.11-220.37" - process $proc$ls180.v:220$3159 + attribute \src "ls180.v:2055.11-2055.51" + process $proc$ls180.v:2055$3732 assign { } { } - assign $1\main_libresocsim_we[7:0] 8'00000000 + assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_we $1\main_libresocsim_we[7:0] + update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:222.12-222.49" - process $proc$ls180.v:222$3160 + attribute \src "ls180.v:2096.11-2096.51" + process $proc$ls180.v:2096$3733 assign { } { } - assign $1\main_libresocsim_load_storage[31:0] 0 + assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] + update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:223.5-223.36" - process $proc$ls180.v:223$3161 + attribute \src "ls180.v:211.5-211.36" + process $proc$ls180.v:211$2923 assign { } { } - assign $1\main_libresocsim_load_re[0:0] 1'0 + assign $1\main_ram_bus_ram_bus_ack[0:0] 1'0 sync always sync init - update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] + update \main_ram_bus_ram_bus_ack $1\main_ram_bus_ram_bus_ack[0:0] end - attribute \src "ls180.v:224.12-224.51" - process $proc$ls180.v:224$3162 + attribute \src "ls180.v:215.5-215.36" + process $proc$ls180.v:215$2924 assign { } { } - assign $1\main_libresocsim_reload_storage[31:0] 0 + assign $0\main_ram_bus_ram_bus_err[0:0] 1'0 sync always + update \main_ram_bus_ram_bus_err $0\main_ram_bus_ram_bus_err[0:0] sync init - update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] end - attribute \src "ls180.v:225.5-225.38" - process $proc$ls180.v:225$3163 - assign { } { } - assign $1\main_libresocsim_reload_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] - end - attribute \src "ls180.v:2250.11-2250.51" - process $proc$ls180.v:2250$3995 + attribute \src "ls180.v:2161.11-2161.51" + process $proc$ls180.v:2161$3734 assign { } { } assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:226.5-226.39" - process $proc$ls180.v:226$3164 - assign { } { } - assign $1\main_libresocsim_en_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] - end - attribute \src "ls180.v:227.5-227.34" - process $proc$ls180.v:227$3165 - assign { } { } - assign $1\main_libresocsim_en_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] - end - attribute \src "ls180.v:228.5-228.49" - process $proc$ls180.v:228$3166 - assign { } { } - assign $1\main_libresocsim_update_value_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] - end - attribute \src "ls180.v:229.5-229.44" - process $proc$ls180.v:229$3167 + attribute \src "ls180.v:218.11-218.29" + process $proc$ls180.v:218$2925 assign { } { } - assign $1\main_libresocsim_update_value_re[0:0] 1'0 + assign $1\main_ram_we[7:0] 8'00000000 sync always sync init - update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] + update \main_ram_we $1\main_ram_we[7:0] end - attribute \src "ls180.v:230.12-230.49" - process $proc$ls180.v:230$3168 + attribute \src "ls180.v:226.5-226.51" + process $proc$ls180.v:226$2926 assign { } { } - assign $1\main_libresocsim_value_status[31:0] 0 + assign $1\main_interface0_converted_interface_ack[0:0] 1'0 sync always sync init - update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] + update \main_interface0_converted_interface_ack $1\main_interface0_converted_interface_ack[0:0] end - attribute \src "ls180.v:234.5-234.41" - process $proc$ls180.v:234$3169 + attribute \src "ls180.v:2294.11-2294.51" + process $proc$ls180.v:2294$3735 assign { } { } - assign $1\main_libresocsim_zero_pending[0:0] 1'0 + assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] + update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:236.5-236.39" - process $proc$ls180.v:236$3170 + attribute \src "ls180.v:230.5-230.51" + process $proc$ls180.v:230$2927 assign { } { } - assign $1\main_libresocsim_zero_clear[0:0] 1'0 + assign $0\main_interface0_converted_interface_err[0:0] 1'0 sync always + update \main_interface0_converted_interface_err $0\main_interface0_converted_interface_err[0:0] sync init - update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:237.5-237.45" - process $proc$ls180.v:237$3171 + attribute \src "ls180.v:231.5-231.32" + process $proc$ls180.v:231$2928 assign { } { } - assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 + assign $1\main_converter0_skip[0:0] 1'0 sync always sync init - update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] + update \main_converter0_skip $1\main_converter0_skip[0:0] end - attribute \src "ls180.v:2383.11-2383.51" - process $proc$ls180.v:2383$3996 + attribute \src "ls180.v:232.5-232.35" + process $proc$ls180.v:232$2929 assign { } { } - assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + assign $1\main_converter0_counter[0:0] 1'0 sync always sync init - update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] + update \main_converter0_counter $1\main_converter0_counter[0:0] end - attribute \src "ls180.v:246.5-246.49" - process $proc$ls180.v:246$3172 + attribute \src "ls180.v:234.12-234.41" + process $proc$ls180.v:234$2930 assign { } { } - assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 + assign $1\main_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] + update \main_converter0_dat_r $1\main_converter0_dat_r[63:0] end - attribute \src "ls180.v:2464.11-2464.51" - process $proc$ls180.v:2464$3997 + attribute \src "ls180.v:2375.11-2375.51" + process $proc$ls180.v:2375$3736 assign { } { } assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:247.5-247.44" - process $proc$ls180.v:247$3173 + attribute \src "ls180.v:2392.11-2392.51" + process $proc$ls180.v:2392$3737 assign { } { } - assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 + assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] + update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:248.12-248.42" - process $proc$ls180.v:248$3174 + attribute \src "ls180.v:241.5-241.51" + process $proc$ls180.v:241$2931 assign { } { } - assign $1\main_libresocsim_value[31:0] 0 + assign $1\main_interface1_converted_interface_ack[0:0] 1'0 sync always sync init - update \main_libresocsim_value $1\main_libresocsim_value[31:0] + update \main_interface1_converted_interface_ack $1\main_interface1_converted_interface_ack[0:0] end - attribute \src "ls180.v:2481.11-2481.51" - process $proc$ls180.v:2481$3998 + attribute \src "ls180.v:2433.11-2433.52" + process $proc$ls180.v:2433$3738 assign { } { } - assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] + update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2522.11-2522.52" - process $proc$ls180.v:2522$3999 + attribute \src "ls180.v:245.5-245.51" + process $proc$ls180.v:245$2932 assign { } { } - assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_interface1_converted_interface_err[0:0] 1'0 sync always + update \main_interface1_converted_interface_err $0\main_interface1_converted_interface_err[0:0] sync init - update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:255.5-255.39" - process $proc$ls180.v:255$3175 + attribute \src "ls180.v:246.5-246.32" + process $proc$ls180.v:246$2933 assign { } { } - assign $1\main_interface0_ram_bus_ack[0:0] 1'0 + assign $1\main_converter1_skip[0:0] 1'0 sync always sync init - update \main_interface0_ram_bus_ack $1\main_interface0_ram_bus_ack[0:0] + update \main_converter1_skip $1\main_converter1_skip[0:0] end - attribute \src "ls180.v:2555.11-2555.52" - process $proc$ls180.v:2555$4000 + attribute \src "ls180.v:2466.11-2466.52" + process $proc$ls180.v:2466$3739 assign { } { } assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:259.5-259.39" - process $proc$ls180.v:259$3176 + attribute \src "ls180.v:247.5-247.35" + process $proc$ls180.v:247$2934 assign { } { } - assign $0\main_interface0_ram_bus_err[0:0] 1'0 + assign $1\main_converter1_counter[0:0] 1'0 sync always - update \main_interface0_ram_bus_err $0\main_interface0_ram_bus_err[0:0] sync init + update \main_converter1_counter $1\main_converter1_counter[0:0] end - attribute \src "ls180.v:2596.11-2596.52" - process $proc$ls180.v:2596$4001 + attribute \src "ls180.v:249.12-249.41" + process $proc$ls180.v:249$2935 + assign { } { } + assign $1\main_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_converter1_dat_r $1\main_converter1_dat_r[63:0] + end + attribute \src "ls180.v:2507.11-2507.52" + process $proc$ls180.v:2507$3740 assign { } { } assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:262.11-262.31" - process $proc$ls180.v:262$3177 + attribute \src "ls180.v:253.5-253.24" + process $proc$ls180.v:253$2936 assign { } { } - assign $1\main_sram0_we[7:0] 8'00000000 + assign $1\main_int_rst[0:0] 1'1 sync always sync init - update \main_sram0_we $1\main_sram0_we[7:0] + update \main_int_rst $1\main_int_rst[0:0] end - attribute \src "ls180.v:2661.11-2661.52" - process $proc$ls180.v:2661$4002 + attribute \src "ls180.v:2572.11-2572.52" + process $proc$ls180.v:2572$3741 assign { } { } assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2686.11-2686.52" - process $proc$ls180.v:2686$4003 + attribute \src "ls180.v:2597.11-2597.52" + process $proc$ls180.v:2597$3742 assign { } { } assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 sync always sync init update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:270.5-270.39" - process $proc$ls180.v:270$3178 - assign { } { } - assign $1\main_interface1_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_interface1_ram_bus_ack $1\main_interface1_ram_bus_ack[0:0] - end - attribute \src "ls180.v:2708.11-2708.31" - process $proc$ls180.v:2708$4004 + attribute \src "ls180.v:2619.11-2619.31" + process $proc$ls180.v:2619$3743 assign { } { } assign $1\builder_state[1:0] 2'00 sync always sync init update \builder_state $1\builder_state[1:0] end - attribute \src "ls180.v:2709.11-2709.36" - process $proc$ls180.v:2709$4005 + attribute \src "ls180.v:2620.11-2620.36" + process $proc$ls180.v:2620$3744 assign { } { } assign $1\builder_next_state[1:0] 2'00 sync always sync init update \builder_next_state $1\builder_next_state[1:0] end - attribute \src "ls180.v:2710.11-2710.55" - process $proc$ls180.v:2710$4006 + attribute \src "ls180.v:2621.11-2621.55" + process $proc$ls180.v:2621$3745 assign { } { } assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 sync always sync init update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] end - attribute \src "ls180.v:2711.5-2711.52" - process $proc$ls180.v:2711$4007 + attribute \src "ls180.v:2622.5-2622.52" + process $proc$ls180.v:2622$3746 assign { } { } assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 sync always sync init update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] end - attribute \src "ls180.v:2712.12-2712.55" - process $proc$ls180.v:2712$4008 + attribute \src "ls180.v:2623.12-2623.55" + process $proc$ls180.v:2623$3747 assign { } { } assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 sync always sync init update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] end - attribute \src "ls180.v:2713.5-2713.50" - process $proc$ls180.v:2713$4009 + attribute \src "ls180.v:2624.5-2624.50" + process $proc$ls180.v:2624$3748 assign { } { } assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 sync always sync init update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] end - attribute \src "ls180.v:2714.5-2714.46" - process $proc$ls180.v:2714$4010 + attribute \src "ls180.v:2625.5-2625.46" + process $proc$ls180.v:2625$3749 assign { } { } assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 sync always sync init update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] end - attribute \src "ls180.v:2715.5-2715.49" - process $proc$ls180.v:2715$4011 + attribute \src "ls180.v:2626.5-2626.49" + process $proc$ls180.v:2626$3750 assign { } { } assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 sync always sync init update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] end - attribute \src "ls180.v:2716.5-2716.41" - process $proc$ls180.v:2716$4012 + attribute \src "ls180.v:2627.5-2627.41" + process $proc$ls180.v:2627$3751 assign { } { } assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] end - attribute \src "ls180.v:2717.12-2717.49" - process $proc$ls180.v:2717$4013 + attribute \src "ls180.v:2628.12-2628.49" + process $proc$ls180.v:2628$3752 assign { } { } assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:2718.11-2718.47" - process $proc$ls180.v:2718$4014 + attribute \src "ls180.v:2629.11-2629.47" + process $proc$ls180.v:2629$3753 assign { } { } assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] end - attribute \src "ls180.v:2719.5-2719.41" - process $proc$ls180.v:2719$4015 + attribute \src "ls180.v:2630.5-2630.41" + process $proc$ls180.v:2630$3754 assign { } { } assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:2720.5-2720.41" - process $proc$ls180.v:2720$4016 + attribute \src "ls180.v:2631.5-2631.41" + process $proc$ls180.v:2631$3755 assign { } { } assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:2721.5-2721.41" - process $proc$ls180.v:2721$4017 + attribute \src "ls180.v:2632.5-2632.41" + process $proc$ls180.v:2632$3756 assign { } { } assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:2722.5-2722.39" - process $proc$ls180.v:2722$4018 + attribute \src "ls180.v:2633.5-2633.39" + process $proc$ls180.v:2633$3757 assign { } { } assign $1\builder_comb_t_array_muxed0[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] end - attribute \src "ls180.v:2723.5-2723.39" - process $proc$ls180.v:2723$4019 + attribute \src "ls180.v:2634.5-2634.39" + process $proc$ls180.v:2634$3758 assign { } { } assign $1\builder_comb_t_array_muxed1[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] end - attribute \src "ls180.v:2724.5-2724.39" - process $proc$ls180.v:2724$4020 + attribute \src "ls180.v:2635.5-2635.39" + process $proc$ls180.v:2635$3759 assign { } { } assign $1\builder_comb_t_array_muxed2[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] end - attribute \src "ls180.v:2725.5-2725.41" - process $proc$ls180.v:2725$4021 + attribute \src "ls180.v:2636.5-2636.41" + process $proc$ls180.v:2636$3760 assign { } { } assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:2726.12-2726.49" - process $proc$ls180.v:2726$4022 + attribute \src "ls180.v:2637.12-2637.49" + process $proc$ls180.v:2637$3761 assign { } { } assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 sync always sync init update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] end - attribute \src "ls180.v:2727.11-2727.47" - process $proc$ls180.v:2727$4023 + attribute \src "ls180.v:2638.11-2638.47" + process $proc$ls180.v:2638$3762 assign { } { } assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] end - attribute \src "ls180.v:2728.5-2728.41" - process $proc$ls180.v:2728$4024 + attribute \src "ls180.v:2639.5-2639.41" + process $proc$ls180.v:2639$3763 assign { } { } assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] end - attribute \src "ls180.v:2729.5-2729.42" - process $proc$ls180.v:2729$4025 + attribute \src "ls180.v:2640.5-2640.42" + process $proc$ls180.v:2640$3764 assign { } { } assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] end - attribute \src "ls180.v:2730.5-2730.42" - process $proc$ls180.v:2730$4026 + attribute \src "ls180.v:2641.5-2641.42" + process $proc$ls180.v:2641$3765 assign { } { } assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] end - attribute \src "ls180.v:2731.5-2731.39" - process $proc$ls180.v:2731$4027 + attribute \src "ls180.v:2642.5-2642.39" + process $proc$ls180.v:2642$3766 assign { } { } assign $1\builder_comb_t_array_muxed3[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] end - attribute \src "ls180.v:2732.5-2732.39" - process $proc$ls180.v:2732$4028 + attribute \src "ls180.v:2643.5-2643.39" + process $proc$ls180.v:2643$3767 assign { } { } assign $1\builder_comb_t_array_muxed4[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] end - attribute \src "ls180.v:2733.5-2733.39" - process $proc$ls180.v:2733$4029 + attribute \src "ls180.v:2644.5-2644.39" + process $proc$ls180.v:2644$3768 assign { } { } assign $1\builder_comb_t_array_muxed5[0:0] 1'0 sync always sync init update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] end - attribute \src "ls180.v:2734.12-2734.50" - process $proc$ls180.v:2734$4030 + attribute \src "ls180.v:2645.12-2645.50" + process $proc$ls180.v:2645$3769 assign { } { } assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] end - attribute \src "ls180.v:2735.5-2735.42" - process $proc$ls180.v:2735$4031 + attribute \src "ls180.v:2646.5-2646.42" + process $proc$ls180.v:2646$3770 assign { } { } assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] end - attribute \src "ls180.v:2736.5-2736.42" - process $proc$ls180.v:2736$4032 + attribute \src "ls180.v:2647.5-2647.42" + process $proc$ls180.v:2647$3771 assign { } { } assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] end - attribute \src "ls180.v:2737.12-2737.50" - process $proc$ls180.v:2737$4033 + attribute \src "ls180.v:2648.12-2648.50" + process $proc$ls180.v:2648$3772 assign { } { } assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] end - attribute \src "ls180.v:2738.5-2738.42" - process $proc$ls180.v:2738$4034 + attribute \src "ls180.v:2649.5-2649.42" + process $proc$ls180.v:2649$3773 assign { } { } assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] end - attribute \src "ls180.v:2739.5-2739.42" - process $proc$ls180.v:2739$4035 + attribute \src "ls180.v:2650.5-2650.42" + process $proc$ls180.v:2650$3774 assign { } { } assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] end - attribute \src "ls180.v:274.5-274.39" - process $proc$ls180.v:274$3179 - assign { } { } - assign $0\main_interface1_ram_bus_err[0:0] 1'0 - sync always - update \main_interface1_ram_bus_err $0\main_interface1_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:2740.12-2740.50" - process $proc$ls180.v:2740$4036 + attribute \src "ls180.v:2651.12-2651.50" + process $proc$ls180.v:2651$3775 assign { } { } assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] end - attribute \src "ls180.v:2741.5-2741.42" - process $proc$ls180.v:2741$4037 + attribute \src "ls180.v:2652.5-2652.42" + process $proc$ls180.v:2652$3776 assign { } { } assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] end - attribute \src "ls180.v:2742.5-2742.42" - process $proc$ls180.v:2742$4038 + attribute \src "ls180.v:2653.5-2653.42" + process $proc$ls180.v:2653$3777 assign { } { } assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] end - attribute \src "ls180.v:2743.12-2743.50" - process $proc$ls180.v:2743$4039 + attribute \src "ls180.v:2654.12-2654.50" + process $proc$ls180.v:2654$3778 assign { } { } assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] end - attribute \src "ls180.v:2744.5-2744.42" - process $proc$ls180.v:2744$4040 + attribute \src "ls180.v:2655.5-2655.42" + process $proc$ls180.v:2655$3779 assign { } { } assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] end - attribute \src "ls180.v:2745.5-2745.42" - process $proc$ls180.v:2745$4041 + attribute \src "ls180.v:2656.5-2656.42" + process $proc$ls180.v:2656$3780 assign { } { } assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] end - attribute \src "ls180.v:2746.12-2746.50" - process $proc$ls180.v:2746$4042 + attribute \src "ls180.v:2657.12-2657.50" + process $proc$ls180.v:2657$3781 assign { } { } assign $1\builder_comb_rhs_array_muxed24[31:0] 0 sync always sync init update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] end - attribute \src "ls180.v:2747.12-2747.50" - process $proc$ls180.v:2747$4043 + attribute \src "ls180.v:2658.12-2658.50" + process $proc$ls180.v:2658$3782 assign { } { } assign $1\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[63:0] end - attribute \src "ls180.v:2748.11-2748.48" - process $proc$ls180.v:2748$4044 + attribute \src "ls180.v:2659.11-2659.48" + process $proc$ls180.v:2659$3783 assign { } { } assign $1\builder_comb_rhs_array_muxed26[7:0] 8'00000000 sync always sync init update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[7:0] end - attribute \src "ls180.v:2749.5-2749.42" - process $proc$ls180.v:2749$4045 + attribute \src "ls180.v:2660.5-2660.42" + process $proc$ls180.v:2660$3784 assign { } { } assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] end - attribute \src "ls180.v:2750.5-2750.42" - process $proc$ls180.v:2750$4046 + attribute \src "ls180.v:2661.5-2661.42" + process $proc$ls180.v:2661$3785 assign { } { } assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] end - attribute \src "ls180.v:2751.5-2751.42" - process $proc$ls180.v:2751$4047 + attribute \src "ls180.v:2662.5-2662.42" + process $proc$ls180.v:2662$3786 assign { } { } assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 sync always sync init update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] end - attribute \src "ls180.v:2752.11-2752.48" - process $proc$ls180.v:2752$4048 + attribute \src "ls180.v:2663.11-2663.48" + process $proc$ls180.v:2663$3787 assign { } { } assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 sync always sync init update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] end - attribute \src "ls180.v:2753.11-2753.48" - process $proc$ls180.v:2753$4049 + attribute \src "ls180.v:2664.11-2664.48" + process $proc$ls180.v:2664$3788 assign { } { } assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 sync always sync init update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] end - attribute \src "ls180.v:2754.11-2754.47" - process $proc$ls180.v:2754$4050 + attribute \src "ls180.v:2665.11-2665.47" + process $proc$ls180.v:2665$3789 assign { } { } assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 sync always sync init update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] end - attribute \src "ls180.v:2755.12-2755.49" - process $proc$ls180.v:2755$4051 + attribute \src "ls180.v:2666.12-2666.49" + process $proc$ls180.v:2666$3790 assign { } { } assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:2756.5-2756.41" - process $proc$ls180.v:2756$4052 + attribute \src "ls180.v:2667.5-2667.41" + process $proc$ls180.v:2667$3791 assign { } { } assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] end - attribute \src "ls180.v:2757.5-2757.41" - process $proc$ls180.v:2757$4053 + attribute \src "ls180.v:2668.5-2668.41" + process $proc$ls180.v:2668$3792 assign { } { } assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:2758.5-2758.41" - process $proc$ls180.v:2758$4054 + attribute \src "ls180.v:2669.5-2669.41" + process $proc$ls180.v:2669$3793 assign { } { } assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:2759.5-2759.41" - process $proc$ls180.v:2759$4055 + attribute \src "ls180.v:2670.5-2670.41" + process $proc$ls180.v:2670$3794 assign { } { } assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:2760.5-2760.41" - process $proc$ls180.v:2760$4056 + attribute \src "ls180.v:2671.5-2671.41" + process $proc$ls180.v:2671$3795 assign { } { } assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 sync always sync init update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:2761.5-2761.39" - process $proc$ls180.v:2761$4057 + attribute \src "ls180.v:2672.5-2672.39" + process $proc$ls180.v:2672$3796 assign { } { } assign $1\builder_sync_f_array_muxed0[0:0] 1'0 sync always sync init update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] end - attribute \src "ls180.v:2762.5-2762.39" - process $proc$ls180.v:2762$4058 + attribute \src "ls180.v:2673.5-2673.39" + process $proc$ls180.v:2673$3797 assign { } { } assign $1\builder_sync_f_array_muxed1[0:0] 1'0 sync always sync init update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] end - attribute \src "ls180.v:277.11-277.31" - process $proc$ls180.v:277$3180 + attribute \src "ls180.v:268.12-268.38" + process $proc$ls180.v:268$2937 + assign { } { } + assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] + end + attribute \src "ls180.v:269.5-269.36" + process $proc$ls180.v:269$2938 assign { } { } - assign $1\main_sram1_we[7:0] 8'00000000 + assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 sync always sync init - update \main_sram1_we $1\main_sram1_we[7:0] + update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:270.11-270.32" + process $proc$ls180.v:270$2939 + assign { } { } + assign $1\main_rddata_en[2:0] 3'000 + sync always + sync init + update \main_rddata_en $1\main_rddata_en[2:0] + end + attribute \src "ls180.v:273.5-273.36" + process $proc$ls180.v:273$2940 + assign { } { } + assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] end - attribute \src "ls180.v:2819.32-2819.66" - process $proc$ls180.v:2819$4059 + attribute \src "ls180.v:2730.32-2730.66" + process $proc$ls180.v:2730$3798 assign { } { } assign $1\builder_multiregimpl0_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] end - attribute \src "ls180.v:2820.32-2820.66" - process $proc$ls180.v:2820$4060 + attribute \src "ls180.v:2731.32-2731.66" + process $proc$ls180.v:2731$3799 assign { } { } assign $1\builder_multiregimpl0_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] end - attribute \src "ls180.v:2821.32-2821.66" - process $proc$ls180.v:2821$4061 + attribute \src "ls180.v:2732.32-2732.66" + process $proc$ls180.v:2732$3800 assign { } { } assign $1\builder_multiregimpl1_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] end - attribute \src "ls180.v:2822.32-2822.66" - process $proc$ls180.v:2822$4062 + attribute \src "ls180.v:2733.32-2733.66" + process $proc$ls180.v:2733$3801 assign { } { } assign $1\builder_multiregimpl1_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] end - attribute \src "ls180.v:2823.32-2823.66" - process $proc$ls180.v:2823$4063 + attribute \src "ls180.v:2734.32-2734.66" + process $proc$ls180.v:2734$3802 assign { } { } assign $1\builder_multiregimpl2_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] end - attribute \src "ls180.v:2824.32-2824.66" - process $proc$ls180.v:2824$4064 + attribute \src "ls180.v:2735.32-2735.66" + process $proc$ls180.v:2735$3803 assign { } { } assign $1\builder_multiregimpl2_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] end - attribute \src "ls180.v:2825.32-2825.66" - process $proc$ls180.v:2825$4065 + attribute \src "ls180.v:2736.32-2736.66" + process $proc$ls180.v:2736$3804 assign { } { } assign $1\builder_multiregimpl3_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] end - attribute \src "ls180.v:2826.32-2826.66" - process $proc$ls180.v:2826$4066 + attribute \src "ls180.v:2737.32-2737.66" + process $proc$ls180.v:2737$3805 assign { } { } assign $1\builder_multiregimpl3_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] end - attribute \src "ls180.v:2827.32-2827.66" - process $proc$ls180.v:2827$4067 + attribute \src "ls180.v:2738.32-2738.66" + process $proc$ls180.v:2738$3806 assign { } { } assign $1\builder_multiregimpl4_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] end - attribute \src "ls180.v:2828.32-2828.66" - process $proc$ls180.v:2828$4068 + attribute \src "ls180.v:2739.32-2739.66" + process $proc$ls180.v:2739$3807 assign { } { } assign $1\builder_multiregimpl4_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] end - attribute \src "ls180.v:2829.32-2829.66" - process $proc$ls180.v:2829$4069 + attribute \src "ls180.v:274.5-274.35" + process $proc$ls180.v:274$2941 + assign { } { } + assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] + end + attribute \src "ls180.v:2740.32-2740.66" + process $proc$ls180.v:2740$3808 assign { } { } assign $1\builder_multiregimpl5_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] end - attribute \src "ls180.v:2830.32-2830.66" - process $proc$ls180.v:2830$4070 + attribute \src "ls180.v:2741.32-2741.66" + process $proc$ls180.v:2741$3809 assign { } { } assign $1\builder_multiregimpl5_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] end - attribute \src "ls180.v:2831.32-2831.66" - process $proc$ls180.v:2831$4071 + attribute \src "ls180.v:2742.32-2742.66" + process $proc$ls180.v:2742$3810 assign { } { } assign $1\builder_multiregimpl6_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] end - attribute \src "ls180.v:2832.32-2832.66" - process $proc$ls180.v:2832$4072 + attribute \src "ls180.v:2743.32-2743.66" + process $proc$ls180.v:2743$3811 assign { } { } assign $1\builder_multiregimpl6_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] end - attribute \src "ls180.v:2833.32-2833.66" - process $proc$ls180.v:2833$4073 + attribute \src "ls180.v:2744.32-2744.66" + process $proc$ls180.v:2744$3812 assign { } { } assign $1\builder_multiregimpl7_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] end - attribute \src "ls180.v:2834.32-2834.66" - process $proc$ls180.v:2834$4074 + attribute \src "ls180.v:2745.32-2745.66" + process $proc$ls180.v:2745$3813 assign { } { } assign $1\builder_multiregimpl7_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] end - attribute \src "ls180.v:2835.32-2835.66" - process $proc$ls180.v:2835$4075 + attribute \src "ls180.v:2746.32-2746.66" + process $proc$ls180.v:2746$3814 assign { } { } assign $1\builder_multiregimpl8_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] end - attribute \src "ls180.v:2836.32-2836.66" - process $proc$ls180.v:2836$4076 + attribute \src "ls180.v:2747.32-2747.66" + process $proc$ls180.v:2747$3815 assign { } { } assign $1\builder_multiregimpl8_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] end - attribute \src "ls180.v:2837.32-2837.66" - process $proc$ls180.v:2837$4077 + attribute \src "ls180.v:2748.32-2748.66" + process $proc$ls180.v:2748$3816 assign { } { } assign $1\builder_multiregimpl9_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] end - attribute \src "ls180.v:2838.32-2838.66" - process $proc$ls180.v:2838$4078 + attribute \src "ls180.v:2749.32-2749.66" + process $proc$ls180.v:2749$3817 assign { } { } assign $1\builder_multiregimpl9_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] end - attribute \src "ls180.v:2839.32-2839.67" - process $proc$ls180.v:2839$4079 + attribute \src "ls180.v:275.5-275.36" + process $proc$ls180.v:275$2942 + assign { } { } + assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] + end + attribute \src "ls180.v:2750.32-2750.67" + process $proc$ls180.v:2750$3818 assign { } { } assign $1\builder_multiregimpl10_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] end - attribute \src "ls180.v:2840.32-2840.67" - process $proc$ls180.v:2840$4080 + attribute \src "ls180.v:2751.32-2751.67" + process $proc$ls180.v:2751$3819 assign { } { } assign $1\builder_multiregimpl10_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] end - attribute \src "ls180.v:2841.32-2841.67" - process $proc$ls180.v:2841$4081 + attribute \src "ls180.v:2752.32-2752.67" + process $proc$ls180.v:2752$3820 assign { } { } assign $1\builder_multiregimpl11_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] end - attribute \src "ls180.v:2842.32-2842.67" - process $proc$ls180.v:2842$4082 + attribute \src "ls180.v:2753.32-2753.67" + process $proc$ls180.v:2753$3821 assign { } { } assign $1\builder_multiregimpl11_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] end - attribute \src "ls180.v:2843.32-2843.67" - process $proc$ls180.v:2843$4083 + attribute \src "ls180.v:2754.32-2754.67" + process $proc$ls180.v:2754$3822 assign { } { } assign $1\builder_multiregimpl12_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] end - attribute \src "ls180.v:2844.32-2844.67" - process $proc$ls180.v:2844$4084 + attribute \src "ls180.v:2755.32-2755.67" + process $proc$ls180.v:2755$3823 assign { } { } assign $1\builder_multiregimpl12_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] end - attribute \src "ls180.v:2845.32-2845.67" - process $proc$ls180.v:2845$4085 + attribute \src "ls180.v:2756.32-2756.67" + process $proc$ls180.v:2756$3824 assign { } { } assign $1\builder_multiregimpl13_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] end - attribute \src "ls180.v:2846.32-2846.67" - process $proc$ls180.v:2846$4086 + attribute \src "ls180.v:2757.32-2757.67" + process $proc$ls180.v:2757$3825 assign { } { } assign $1\builder_multiregimpl13_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] end - attribute \src "ls180.v:2847.32-2847.67" - process $proc$ls180.v:2847$4087 + attribute \src "ls180.v:2758.32-2758.67" + process $proc$ls180.v:2758$3826 assign { } { } assign $1\builder_multiregimpl14_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] end - attribute \src "ls180.v:2848.32-2848.67" - process $proc$ls180.v:2848$4088 + attribute \src "ls180.v:2759.32-2759.67" + process $proc$ls180.v:2759$3827 assign { } { } assign $1\builder_multiregimpl14_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] end - attribute \src "ls180.v:2849.32-2849.67" - process $proc$ls180.v:2849$4089 + attribute \src "ls180.v:276.5-276.35" + process $proc$ls180.v:276$2943 assign { } { } - assign $1\builder_multiregimpl15_regs0[0:0] 1'0 + assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 sync always sync init - update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] + update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] end - attribute \src "ls180.v:285.5-285.39" - process $proc$ls180.v:285$3181 + attribute \src "ls180.v:2760.32-2760.67" + process $proc$ls180.v:2760$3828 assign { } { } - assign $1\main_interface2_ram_bus_ack[0:0] 1'0 + assign $1\builder_multiregimpl15_regs0[0:0] 1'0 sync always sync init - update \main_interface2_ram_bus_ack $1\main_interface2_ram_bus_ack[0:0] + update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] end - attribute \src "ls180.v:2850.32-2850.67" - process $proc$ls180.v:2850$4090 + attribute \src "ls180.v:2761.32-2761.67" + process $proc$ls180.v:2761$3829 assign { } { } assign $1\builder_multiregimpl15_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] end - attribute \src "ls180.v:2851.32-2851.67" - process $proc$ls180.v:2851$4091 + attribute \src "ls180.v:2762.32-2762.67" + process $proc$ls180.v:2762$3830 assign { } { } assign $1\builder_multiregimpl16_regs0[0:0] 1'0 sync always sync init update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] end - attribute \src "ls180.v:2852.32-2852.67" - process $proc$ls180.v:2852$4092 + attribute \src "ls180.v:2763.32-2763.67" + process $proc$ls180.v:2763$3831 assign { } { } assign $1\builder_multiregimpl16_regs1[0:0] 1'0 sync always sync init update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] end - attribute \src "ls180.v:2887.1-2892.4" - process $proc$ls180.v:2887$49 + attribute \src "ls180.v:2798.1-2803.4" + process $proc$ls180.v:2798$25 assign { } { } assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } @@ -290743,19 +287746,19 @@ module \ls180 sync always update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] end - attribute \src "ls180.v:289.5-289.39" - process $proc$ls180.v:289$3182 + attribute \src "ls180.v:280.5-280.36" + process $proc$ls180.v:280$2944 assign { } { } - assign $0\main_interface2_ram_bus_err[0:0] 1'0 + assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 sync always - update \main_interface2_ram_bus_err $0\main_interface2_ram_bus_err[0:0] + update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] sync init end - attribute \src "ls180.v:2894.1-2904.4" - process $proc$ls180.v:2894$51 + attribute \src "ls180.v:2805.1-2815.4" + process $proc$ls180.v:2805$27 assign { } { } assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 - attribute \src "ls180.v:2896.2-2903.9" + attribute \src "ls180.v:2807.2-2814.9" switch \main_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -290768,8 +287771,8 @@ module \ls180 sync always update \main_libresocsim_libresoc_xics_icp_dat_w $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] end - attribute \src "ls180.v:2906.1-2952.4" - process $proc$ls180.v:2906$52 + attribute \src "ls180.v:2817.1-2863.4" + process $proc$ls180.v:2817$28 assign { } { } assign { } { } assign { } { } @@ -290783,20 +287786,20 @@ module \ls180 assign { } { } assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 assign $0\main_interface0_converted_interface_ack[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 + assign $0\main_converter0_skip[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 - assign $0\main_converter0_skip[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 assign $0\builder_converter0_next_state[0:0] \builder_converter0_state - attribute \src "ls180.v:2918.2-2951.9" + attribute \src "ls180.v:2829.2-2862.9" switch \builder_converter0_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] { \main_interface0_converted_interface_adr [28:0] \main_converter0_counter } - attribute \src "ls180.v:2921.4-2928.11" + attribute \src "ls180.v:2832.4-2839.11" switch \main_converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -290806,23 +287809,23 @@ module \ls180 assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [7:4] case end - attribute \src "ls180.v:2929.4-2942.7" - switch $and$ls180.v:2929$53_Y - attribute \src "ls180.v:2929.8-2929.91" + attribute \src "ls180.v:2840.4-2853.7" + switch $and$ls180.v:2840$29_Y + attribute \src "ls180.v:2840.8-2840.91" case 1'1 - assign $0\main_converter0_skip[0:0] $eq$ls180.v:2930$54_Y + assign $0\main_converter0_skip[0:0] $eq$ls180.v:2841$30_Y assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] \main_interface0_converted_interface_we - assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] $not$ls180.v:2932$55_Y - assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] $not$ls180.v:2933$56_Y - attribute \src "ls180.v:2934.5-2941.8" - switch $or$ls180.v:2934$57_Y - attribute \src "ls180.v:2934.9-2934.72" + assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] $not$ls180.v:2843$31_Y + assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] $not$ls180.v:2844$32_Y + attribute \src "ls180.v:2845.5-2852.8" + switch $or$ls180.v:2845$33_Y + attribute \src "ls180.v:2845.9-2845.72" case 1'1 - assign $0\main_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2935$58_Y + assign $0\main_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2846$34_Y assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2937.6-2940.9" - switch $eq$ls180.v:2937$59_Y - attribute \src "ls180.v:2937.10-2937.43" + attribute \src "ls180.v:2848.6-2851.9" + switch $eq$ls180.v:2848$35_Y + attribute \src "ls180.v:2848.10-2848.43" case 1'1 assign $0\main_interface0_converted_interface_ack[0:0] 1'1 assign $0\builder_converter0_next_state[0:0] 1'0 @@ -290836,9 +287839,9 @@ module \ls180 case assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2947.4-2949.7" - switch $and$ls180.v:2947$60_Y - attribute \src "ls180.v:2947.8-2947.91" + attribute \src "ls180.v:2858.4-2860.7" + switch $and$ls180.v:2858$36_Y + attribute \src "ls180.v:2858.8-2858.91" case 1'1 assign $0\builder_converter0_next_state[0:0] 1'1 case @@ -290856,19 +287859,27 @@ module \ls180 update \main_converter0_counter_converter0_next_value $0\main_converter0_counter_converter0_next_value[0:0] update \main_converter0_counter_converter0_next_value_ce $0\main_converter0_counter_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:292.11-292.31" - process $proc$ls180.v:292$3183 + attribute \src "ls180.v:285.12-285.45" + process $proc$ls180.v:285$2945 + assign { } { } + assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] + end + attribute \src "ls180.v:286.5-286.43" + process $proc$ls180.v:286$2946 assign { } { } - assign $1\main_sram2_we[7:0] 8'00000000 + assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 sync always sync init - update \main_sram2_we $1\main_sram2_we[7:0] + update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] end - attribute \src "ls180.v:2954.1-2964.4" - process $proc$ls180.v:2954$62 + attribute \src "ls180.v:2865.1-2875.4" + process $proc$ls180.v:2865$38 assign { } { } assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 - attribute \src "ls180.v:2956.2-2963.9" + attribute \src "ls180.v:2867.2-2874.9" switch \main_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -290881,9 +287892,8 @@ module \ls180 sync always update \main_libresocsim_libresoc_xics_ics_dat_w $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] end - attribute \src "ls180.v:2966.1-3012.4" - process $proc$ls180.v:2966$63 - assign { } { } + attribute \src "ls180.v:2877.1-2923.4" + process $proc$ls180.v:2877$39 assign { } { } assign { } { } assign { } { } @@ -290894,22 +287904,23 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 assign $0\main_interface1_converted_interface_ack[0:0] 1'0 assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 + assign $0\main_converter1_skip[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 - assign $0\main_converter1_skip[0:0] 1'0 assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 + assign { } { } assign $0\builder_converter1_next_state[0:0] \builder_converter1_state - attribute \src "ls180.v:2978.2-3011.9" + attribute \src "ls180.v:2889.2-2922.9" switch \builder_converter1_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] { \main_interface1_converted_interface_adr [28:0] \main_converter1_counter } - attribute \src "ls180.v:2981.4-2988.11" + attribute \src "ls180.v:2892.4-2899.11" switch \main_converter1_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -290919,23 +287930,23 @@ module \ls180 assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [7:4] case end - attribute \src "ls180.v:2989.4-3002.7" - switch $and$ls180.v:2989$64_Y - attribute \src "ls180.v:2989.8-2989.91" + attribute \src "ls180.v:2900.4-2913.7" + switch $and$ls180.v:2900$40_Y + attribute \src "ls180.v:2900.8-2900.91" case 1'1 - assign $0\main_converter1_skip[0:0] $eq$ls180.v:2990$65_Y + assign $0\main_converter1_skip[0:0] $eq$ls180.v:2901$41_Y assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] \main_interface1_converted_interface_we - assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] $not$ls180.v:2992$66_Y - assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] $not$ls180.v:2993$67_Y - attribute \src "ls180.v:2994.5-3001.8" - switch $or$ls180.v:2994$68_Y - attribute \src "ls180.v:2994.9-2994.72" + assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] $not$ls180.v:2903$42_Y + assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] $not$ls180.v:2904$43_Y + attribute \src "ls180.v:2905.5-2912.8" + switch $or$ls180.v:2905$44_Y + attribute \src "ls180.v:2905.9-2905.72" case 1'1 - assign $0\main_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2995$69_Y + assign $0\main_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2906$45_Y assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2997.6-3000.9" - switch $eq$ls180.v:2997$70_Y - attribute \src "ls180.v:2997.10-2997.43" + attribute \src "ls180.v:2908.6-2911.9" + switch $eq$ls180.v:2908$46_Y + attribute \src "ls180.v:2908.10-2908.43" case 1'1 assign $0\main_interface1_converted_interface_ack[0:0] 1'1 assign $0\builder_converter1_next_state[0:0] 1'0 @@ -290949,9 +287960,9 @@ module \ls180 case assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:3007.4-3009.7" - switch $and$ls180.v:3007$71_Y - attribute \src "ls180.v:3007.8-3007.91" + attribute \src "ls180.v:2918.4-2920.7" + switch $and$ls180.v:2918$47_Y + attribute \src "ls180.v:2918.8-2918.91" case 1'1 assign $0\builder_converter1_next_state[0:0] 1'1 case @@ -290969,19 +287980,11 @@ module \ls180 update \main_converter1_counter_converter1_next_value $0\main_converter1_counter_converter1_next_value[0:0] update \main_converter1_counter_converter1_next_value_ce $0\main_converter1_counter_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:300.5-300.39" - process $proc$ls180.v:300$3184 - assign { } { } - assign $1\main_interface3_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_interface3_ram_bus_ack $1\main_interface3_ram_bus_ack[0:0] - end - attribute \src "ls180.v:3014.1-3024.4" - process $proc$ls180.v:3014$73 + attribute \src "ls180.v:2925.1-2935.4" + process $proc$ls180.v:2925$49 assign { } { } assign $0\main_wb_sdram_dat_w[31:0] 0 - attribute \src "ls180.v:3016.2-3023.9" + attribute \src "ls180.v:2927.2-2934.9" switch \main_socbushandler_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -290994,8 +287997,8 @@ module \ls180 sync always update \main_wb_sdram_dat_w $0\main_wb_sdram_dat_w[31:0] end - attribute \src "ls180.v:3026.1-3072.4" - process $proc$ls180.v:3026$74 + attribute \src "ls180.v:2937.1-2983.4" + process $proc$ls180.v:2937$50 assign { } { } assign { } { } assign { } { } @@ -291006,8 +288009,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 - assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 assign $0\main_wb_sdram_we[0:0] 1'0 assign $0\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 assign $0\main_socbushandler_converted_interface_ack[0:0] 1'0 @@ -291016,13 +288017,15 @@ module \ls180 assign $0\main_wb_sdram_stb[0:0] 1'0 assign $0\main_socbushandler_skip[0:0] 1'0 assign { } { } + assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 assign $0\builder_converter2_next_state[0:0] \builder_converter2_state - attribute \src "ls180.v:3038.2-3071.9" + attribute \src "ls180.v:2949.2-2982.9" switch \builder_converter2_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_wb_sdram_adr[29:0] { \main_socbushandler_converted_interface_adr [28:0] \main_socbushandler_counter } - attribute \src "ls180.v:3041.4-3048.11" + attribute \src "ls180.v:2952.4-2959.11" switch \main_socbushandler_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -291032,23 +288035,23 @@ module \ls180 assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [7:4] case end - attribute \src "ls180.v:3049.4-3062.7" - switch $and$ls180.v:3049$75_Y - attribute \src "ls180.v:3049.8-3049.97" + attribute \src "ls180.v:2960.4-2973.7" + switch $and$ls180.v:2960$51_Y + attribute \src "ls180.v:2960.8-2960.97" case 1'1 - assign $0\main_socbushandler_skip[0:0] $eq$ls180.v:3050$76_Y + assign $0\main_socbushandler_skip[0:0] $eq$ls180.v:2961$52_Y assign $0\main_wb_sdram_we[0:0] \main_socbushandler_converted_interface_we - assign $0\main_wb_sdram_cyc[0:0] $not$ls180.v:3052$77_Y - assign $0\main_wb_sdram_stb[0:0] $not$ls180.v:3053$78_Y - attribute \src "ls180.v:3054.5-3061.8" - switch $or$ls180.v:3054$79_Y - attribute \src "ls180.v:3054.9-3054.54" + assign $0\main_wb_sdram_cyc[0:0] $not$ls180.v:2963$53_Y + assign $0\main_wb_sdram_stb[0:0] $not$ls180.v:2964$54_Y + attribute \src "ls180.v:2965.5-2972.8" + switch $or$ls180.v:2965$55_Y + attribute \src "ls180.v:2965.9-2965.54" case 1'1 - assign $0\main_socbushandler_counter_converter2_next_value[0:0] $add$ls180.v:3055$80_Y + assign $0\main_socbushandler_counter_converter2_next_value[0:0] $add$ls180.v:2966$56_Y assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:3057.6-3060.9" - switch $eq$ls180.v:3057$81_Y - attribute \src "ls180.v:3057.10-3057.46" + attribute \src "ls180.v:2968.6-2971.9" + switch $eq$ls180.v:2968$57_Y + attribute \src "ls180.v:2968.10-2968.46" case 1'1 assign $0\main_socbushandler_converted_interface_ack[0:0] 1'1 assign $0\builder_converter2_next_state[0:0] 1'0 @@ -291062,9 +288065,9 @@ module \ls180 case assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:3067.4-3069.7" - switch $and$ls180.v:3067$82_Y - attribute \src "ls180.v:3067.8-3067.97" + attribute \src "ls180.v:2978.4-2980.7" + switch $and$ls180.v:2978$58_Y + attribute \src "ls180.v:2978.8-2978.97" case 1'1 assign $0\builder_converter2_next_state[0:0] 1'1 case @@ -291082,44 +288085,28 @@ module \ls180 update \main_socbushandler_counter_converter2_next_value $0\main_socbushandler_counter_converter2_next_value[0:0] update \main_socbushandler_counter_converter2_next_value_ce $0\main_socbushandler_counter_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:304.5-304.39" - process $proc$ls180.v:304$3185 + attribute \src "ls180.v:2986.1-2996.4" + process $proc$ls180.v:2986$59 assign { } { } - assign $0\main_interface3_ram_bus_err[0:0] 1'0 - sync always - update \main_interface3_ram_bus_err $0\main_interface3_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:307.11-307.31" - process $proc$ls180.v:307$3186 assign { } { } - assign $1\main_sram3_we[7:0] 8'00000000 - sync always - sync init - update \main_sram3_we $1\main_sram3_we[7:0] - end - attribute \src "ls180.v:3075.1-3085.4" - process $proc$ls180.v:3075$83 - assign { } { } - assign { } { } - assign $0\main_libresocsim_we[7:0] [0] $and$ls180.v:3077$86_Y - assign $0\main_libresocsim_we[7:0] [1] $and$ls180.v:3078$89_Y - assign $0\main_libresocsim_we[7:0] [2] $and$ls180.v:3079$92_Y - assign $0\main_libresocsim_we[7:0] [3] $and$ls180.v:3080$95_Y - assign $0\main_libresocsim_we[7:0] [4] $and$ls180.v:3081$98_Y - assign $0\main_libresocsim_we[7:0] [5] $and$ls180.v:3082$101_Y - assign $0\main_libresocsim_we[7:0] [6] $and$ls180.v:3083$104_Y - assign $0\main_libresocsim_we[7:0] [7] $and$ls180.v:3084$107_Y + assign $0\main_libresocsim_we[7:0] [0] $and$ls180.v:2988$62_Y + assign $0\main_libresocsim_we[7:0] [1] $and$ls180.v:2989$65_Y + assign $0\main_libresocsim_we[7:0] [2] $and$ls180.v:2990$68_Y + assign $0\main_libresocsim_we[7:0] [3] $and$ls180.v:2991$71_Y + assign $0\main_libresocsim_we[7:0] [4] $and$ls180.v:2992$74_Y + assign $0\main_libresocsim_we[7:0] [5] $and$ls180.v:2993$77_Y + assign $0\main_libresocsim_we[7:0] [6] $and$ls180.v:2994$80_Y + assign $0\main_libresocsim_we[7:0] [7] $and$ls180.v:2995$83_Y sync always update \main_libresocsim_we $0\main_libresocsim_we[7:0] end - attribute \src "ls180.v:3091.1-3096.4" - process $proc$ls180.v:3091$109 + attribute \src "ls180.v:3002.1-3007.4" + process $proc$ls180.v:3002$85 assign { } { } assign $0\main_libresocsim_zero_clear[0:0] 1'0 - attribute \src "ls180.v:3093.2-3095.5" - switch $and$ls180.v:3093$110_Y - attribute \src "ls180.v:3093.6-3093.90" + attribute \src "ls180.v:3004.2-3006.5" + switch $and$ls180.v:3004$86_Y + attribute \src "ls180.v:3004.6-3004.90" case 1'1 assign $0\main_libresocsim_zero_clear[0:0] 1'1 case @@ -291127,84 +288114,71 @@ module \ls180 sync always update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:3100.1-3110.4" - process $proc$ls180.v:3100$112 + attribute \src "ls180.v:301.12-301.46" + process $proc$ls180.v:301$2947 assign { } { } - assign { } { } - assign $0\main_sram0_we[7:0] [0] $and$ls180.v:3102$115_Y - assign $0\main_sram0_we[7:0] [1] $and$ls180.v:3103$118_Y - assign $0\main_sram0_we[7:0] [2] $and$ls180.v:3104$121_Y - assign $0\main_sram0_we[7:0] [3] $and$ls180.v:3105$124_Y - assign $0\main_sram0_we[7:0] [4] $and$ls180.v:3106$127_Y - assign $0\main_sram0_we[7:0] [5] $and$ls180.v:3107$130_Y - assign $0\main_sram0_we[7:0] [6] $and$ls180.v:3108$133_Y - assign $0\main_sram0_we[7:0] [7] $and$ls180.v:3109$136_Y + assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 sync always - update \main_sram0_we $0\main_sram0_we[7:0] + sync init + update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] end - attribute \src "ls180.v:3114.1-3124.4" - process $proc$ls180.v:3114$137 + attribute \src "ls180.v:3011.1-3021.4" + process $proc$ls180.v:3011$88 assign { } { } assign { } { } - assign $0\main_sram1_we[7:0] [0] $and$ls180.v:3116$140_Y - assign $0\main_sram1_we[7:0] [1] $and$ls180.v:3117$143_Y - assign $0\main_sram1_we[7:0] [2] $and$ls180.v:3118$146_Y - assign $0\main_sram1_we[7:0] [3] $and$ls180.v:3119$149_Y - assign $0\main_sram1_we[7:0] [4] $and$ls180.v:3120$152_Y - assign $0\main_sram1_we[7:0] [5] $and$ls180.v:3121$155_Y - assign $0\main_sram1_we[7:0] [6] $and$ls180.v:3122$158_Y - assign $0\main_sram1_we[7:0] [7] $and$ls180.v:3123$161_Y + assign $0\main_ram_we[7:0] [0] $and$ls180.v:3013$91_Y + assign $0\main_ram_we[7:0] [1] $and$ls180.v:3014$94_Y + assign $0\main_ram_we[7:0] [2] $and$ls180.v:3015$97_Y + assign $0\main_ram_we[7:0] [3] $and$ls180.v:3016$100_Y + assign $0\main_ram_we[7:0] [4] $and$ls180.v:3017$103_Y + assign $0\main_ram_we[7:0] [5] $and$ls180.v:3018$106_Y + assign $0\main_ram_we[7:0] [6] $and$ls180.v:3019$109_Y + assign $0\main_ram_we[7:0] [7] $and$ls180.v:3020$112_Y sync always - update \main_sram1_we $0\main_sram1_we[7:0] + update \main_ram_we $0\main_ram_we[7:0] end - attribute \src "ls180.v:3128.1-3138.4" - process $proc$ls180.v:3128$162 + attribute \src "ls180.v:302.5-302.44" + process $proc$ls180.v:302$2948 assign { } { } - assign { } { } - assign $0\main_sram2_we[7:0] [0] $and$ls180.v:3130$165_Y - assign $0\main_sram2_we[7:0] [1] $and$ls180.v:3131$168_Y - assign $0\main_sram2_we[7:0] [2] $and$ls180.v:3132$171_Y - assign $0\main_sram2_we[7:0] [3] $and$ls180.v:3133$174_Y - assign $0\main_sram2_we[7:0] [4] $and$ls180.v:3134$177_Y - assign $0\main_sram2_we[7:0] [5] $and$ls180.v:3135$180_Y - assign $0\main_sram2_we[7:0] [6] $and$ls180.v:3136$183_Y - assign $0\main_sram2_we[7:0] [7] $and$ls180.v:3137$186_Y + assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 sync always - update \main_sram2_we $0\main_sram2_we[7:0] + sync init + update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] end - attribute \src "ls180.v:3142.1-3152.4" - process $proc$ls180.v:3142$187 + attribute \src "ls180.v:303.12-303.48" + process $proc$ls180.v:303$2949 assign { } { } + assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] + end + attribute \src "ls180.v:304.11-304.43" + process $proc$ls180.v:304$2950 assign { } { } - assign $0\main_sram3_we[7:0] [0] $and$ls180.v:3144$190_Y - assign $0\main_sram3_we[7:0] [1] $and$ls180.v:3145$193_Y - assign $0\main_sram3_we[7:0] [2] $and$ls180.v:3146$196_Y - assign $0\main_sram3_we[7:0] [3] $and$ls180.v:3147$199_Y - assign $0\main_sram3_we[7:0] [4] $and$ls180.v:3148$202_Y - assign $0\main_sram3_we[7:0] [5] $and$ls180.v:3149$205_Y - assign $0\main_sram3_we[7:0] [6] $and$ls180.v:3150$208_Y - assign $0\main_sram3_we[7:0] [7] $and$ls180.v:3151$211_Y + assign $1\main_sdram_master_p0_bank[1:0] 2'00 sync always - update \main_sram3_we $0\main_sram3_we[7:0] + sync init + update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] end - attribute \src "ls180.v:315.5-315.51" - process $proc$ls180.v:315$3187 + attribute \src "ls180.v:305.5-305.38" + process $proc$ls180.v:305$2951 assign { } { } - assign $1\main_interface0_converted_interface_ack[0:0] 1'0 + assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 sync always sync init - update \main_interface0_converted_interface_ack $1\main_interface0_converted_interface_ack[0:0] + update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] end - attribute \src "ls180.v:319.5-319.51" - process $proc$ls180.v:319$3188 + attribute \src "ls180.v:306.5-306.37" + process $proc$ls180.v:306$2952 assign { } { } - assign $0\main_interface0_converted_interface_err[0:0] 1'0 + assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 sync always - update \main_interface0_converted_interface_err $0\main_interface0_converted_interface_err[0:0] sync init + update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] end - attribute \src "ls180.v:3191.1-3245.4" - process $proc$ls180.v:3191$212 + attribute \src "ls180.v:3060.1-3114.4" + process $proc$ls180.v:3060$113 assign { } { } assign { } { } assign { } { } @@ -291241,9 +288215,9 @@ module \ls180 assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 - attribute \src "ls180.v:3210.2-3244.5" + attribute \src "ls180.v:3079.2-3113.5" switch \main_sdram_sel - attribute \src "ls180.v:3210.6-3210.20" + attribute \src "ls180.v:3079.6-3079.20" case 1'1 assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank @@ -291261,7 +288235,7 @@ module \ls180 assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:3227.6-3227.10" + attribute \src "ls180.v:3096.6-3096.10" case assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank @@ -291300,49 +288274,65 @@ module \ls180 update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] end - attribute \src "ls180.v:320.5-320.32" - process $proc$ls180.v:320$3189 + attribute \src "ls180.v:307.5-307.38" + process $proc$ls180.v:307$2953 assign { } { } - assign $1\main_converter0_skip[0:0] 1'0 + assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 sync always sync init - update \main_converter0_skip $1\main_converter0_skip[0:0] + update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] end - attribute \src "ls180.v:321.5-321.35" - process $proc$ls180.v:321$3190 + attribute \src "ls180.v:308.5-308.37" + process $proc$ls180.v:308$2954 assign { } { } - assign $1\main_converter0_counter[0:0] 1'0 + assign $1\main_sdram_master_p0_we_n[0:0] 1'1 sync always sync init - update \main_converter0_counter $1\main_converter0_counter[0:0] + update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] end - attribute \src "ls180.v:323.12-323.41" - process $proc$ls180.v:323$3191 + attribute \src "ls180.v:309.5-309.36" + process $proc$ls180.v:309$2955 assign { } { } - assign $1\main_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_sdram_master_p0_cke[0:0] 1'0 sync always sync init - update \main_converter0_dat_r $1\main_converter0_dat_r[63:0] + update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] end - attribute \src "ls180.v:3249.1-3265.4" - process $proc$ls180.v:3249$213 + attribute \src "ls180.v:310.5-310.36" + process $proc$ls180.v:310$2956 assign { } { } + assign $1\main_sdram_master_p0_odt[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] + end + attribute \src "ls180.v:311.5-311.40" + process $proc$ls180.v:311$2957 + assign { } { } + assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + end + attribute \src "ls180.v:3118.1-3134.4" + process $proc$ls180.v:3118$114 assign { } { } assign { } { } assign { } { } + assign { } { } + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - attribute \src "ls180.v:3254.2-3264.5" + attribute \src "ls180.v:3123.2-3133.5" switch \main_sdram_command_issue_re - attribute \src "ls180.v:3254.6-3254.33" + attribute \src "ls180.v:3123.6-3123.33" case 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3255$214_Y - assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3256$215_Y - assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3257$216_Y - assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3258$217_Y - attribute \src "ls180.v:3259.6-3259.10" + assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3124$115_Y + assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3125$116_Y + assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3126$117_Y + assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3127$118_Y + attribute \src "ls180.v:3128.6-3128.10" case assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 @@ -291355,33 +288345,65 @@ module \ls180 update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] end - attribute \src "ls180.v:330.5-330.51" - process $proc$ls180.v:330$3192 + attribute \src "ls180.v:312.5-312.38" + process $proc$ls180.v:312$2958 assign { } { } - assign $1\main_interface1_converted_interface_ack[0:0] 1'0 + assign $1\main_sdram_master_p0_act_n[0:0] 1'1 sync always sync init - update \main_interface1_converted_interface_ack $1\main_interface1_converted_interface_ack[0:0] + update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] + end + attribute \src "ls180.v:313.12-313.47" + process $proc$ls180.v:313$2959 + assign { } { } + assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] end - attribute \src "ls180.v:3308.1-3338.4" - process $proc$ls180.v:3308$226 + attribute \src "ls180.v:314.5-314.42" + process $proc$ls180.v:314$2960 assign { } { } + assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:315.11-315.50" + process $proc$ls180.v:315$2961 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + end + attribute \src "ls180.v:316.5-316.42" + process $proc$ls180.v:316$2962 + assign { } { } + assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:3177.1-3207.4" + process $proc$ls180.v:3177$127 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_cmd_valid[0:0] 1'0 assign { } { } assign $0\main_sdram_cmd_last[0:0] 1'0 assign $0\main_sdram_sequencer_start0[0:0] 1'0 + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign { } { } assign $0\builder_refresher_next_state[1:0] \builder_refresher_state - attribute \src "ls180.v:3314.2-3337.9" + attribute \src "ls180.v:3183.2-3206.9" switch \builder_refresher_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3317.4-3320.7" + attribute \src "ls180.v:3186.4-3189.7" switch \main_sdram_cmd_ready - attribute \src "ls180.v:3317.8-3317.28" + attribute \src "ls180.v:3186.8-3186.28" case 1'1 assign $0\main_sdram_sequencer_start0[0:0] 1'1 assign $0\builder_refresher_next_state[1:0] 2'10 @@ -291390,9 +288412,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'10 assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3324.4-3328.7" + attribute \src "ls180.v:3193.4-3197.7" switch \main_sdram_sequencer_done0 - attribute \src "ls180.v:3324.8-3324.34" + attribute \src "ls180.v:3193.8-3193.34" case 1'1 assign $0\main_sdram_cmd_valid[0:0] 1'0 assign $0\main_sdram_cmd_last[0:0] 1'1 @@ -291401,13 +288423,13 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3331.4-3335.7" + attribute \src "ls180.v:3200.4-3204.7" switch 1'1 - attribute \src "ls180.v:3331.8-3331.12" + attribute \src "ls180.v:3200.8-3200.12" case 1'1 - attribute \src "ls180.v:3332.5-3334.8" + attribute \src "ls180.v:3201.5-3203.8" switch \main_sdram_wants_refresh - attribute \src "ls180.v:3332.9-3332.33" + attribute \src "ls180.v:3201.9-3201.33" case 1'1 assign $0\builder_refresher_next_state[1:0] 2'01 case @@ -291421,59 +288443,43 @@ module \ls180 update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] end - attribute \src "ls180.v:334.5-334.51" - process $proc$ls180.v:334$3193 - assign { } { } - assign $0\main_interface1_converted_interface_err[0:0] 1'0 - sync always - update \main_interface1_converted_interface_err $0\main_interface1_converted_interface_err[0:0] - sync init - end - attribute \src "ls180.v:335.5-335.32" - process $proc$ls180.v:335$3194 - assign { } { } - assign $1\main_converter1_skip[0:0] 1'0 - sync always - sync init - update \main_converter1_skip $1\main_converter1_skip[0:0] - end - attribute \src "ls180.v:3353.1-3360.4" - process $proc$ls180.v:3353$230 + attribute \src "ls180.v:3222.1-3229.4" + process $proc$ls180.v:3222$131 assign { } { } assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3355.2-3359.5" + attribute \src "ls180.v:3224.2-3228.5" switch \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:3355.6-3355.48" + attribute \src "ls180.v:3224.6-3224.48" case 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3357.6-3357.10" + attribute \src "ls180.v:3226.6-3226.10" case - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3358$232_Y + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3227$133_Y end sync always update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] end - attribute \src "ls180.v:336.5-336.35" - process $proc$ls180.v:336$3195 + attribute \src "ls180.v:323.11-323.36" + process $proc$ls180.v:323$2963 assign { } { } - assign $1\main_converter1_counter[0:0] 1'0 + assign $1\main_sdram_storage[3:0] 4'0001 sync always sync init - update \main_converter1_counter $1\main_converter1_counter[0:0] + update \main_sdram_storage $1\main_sdram_storage[3:0] end - attribute \src "ls180.v:3364.1-3371.4" - process $proc$ls180.v:3364$239 + attribute \src "ls180.v:3233.1-3240.4" + process $proc$ls180.v:3233$140 assign { } { } assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3366.2-3370.5" - switch $and$ls180.v:3366$240_Y - attribute \src "ls180.v:3366.6-3366.115" + attribute \src "ls180.v:3235.2-3239.5" + switch $and$ls180.v:3235$141_Y + attribute \src "ls180.v:3235.6-3235.115" case 1'1 - attribute \src "ls180.v:3367.3-3369.6" - switch $ne$ls180.v:3367$241_Y - attribute \src "ls180.v:3367.7-3367.143" + attribute \src "ls180.v:3236.3-3238.6" + switch $ne$ls180.v:3236$142_Y + attribute \src "ls180.v:3236.7-3236.143" case 1'1 - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3368$242_Y + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3237$143_Y case end case @@ -291481,32 +288487,48 @@ module \ls180 sync always update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] end - attribute \src "ls180.v:338.12-338.41" - process $proc$ls180.v:338$3196 + attribute \src "ls180.v:324.5-324.25" + process $proc$ls180.v:324$2964 assign { } { } - assign $1\main_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_sdram_re[0:0] 1'0 sync always sync init - update \main_converter1_dat_r $1\main_converter1_dat_r[63:0] + update \main_sdram_re $1\main_sdram_re[0:0] + end + attribute \src "ls180.v:325.11-325.44" + process $proc$ls180.v:325$2965 + assign { } { } + assign $1\main_sdram_command_storage[5:0] 6'000000 + sync always + sync init + update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] end - attribute \src "ls180.v:3386.1-3393.4" - process $proc$ls180.v:3386$243 + attribute \src "ls180.v:3255.1-3262.4" + process $proc$ls180.v:3255$144 assign { } { } assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3388.2-3392.5" + attribute \src "ls180.v:3257.2-3261.5" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3388.6-3388.58" + attribute \src "ls180.v:3257.6-3257.58" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3389$244_Y - attribute \src "ls180.v:3390.6-3390.10" + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3258$145_Y + attribute \src "ls180.v:3259.6-3259.10" case assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:3402.1-3495.4" - process $proc$ls180.v:3402$252 + attribute \src "ls180.v:326.5-326.33" + process $proc$ls180.v:326$2966 + assign { } { } + assign $1\main_sdram_command_re[0:0] 1'0 + sync always + sync init + update \main_sdram_command_re $1\main_sdram_command_re[0:0] + end + attribute \src "ls180.v:3271.1-3364.4" + process $proc$ls180.v:3271$153 assign { } { } assign { } { } assign { } { } @@ -291521,7 +288543,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 @@ -291535,23 +288556,24 @@ module \ls180 assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state - attribute \src "ls180.v:3418.2-3494.9" + attribute \src "ls180.v:3287.2-3363.9" switch \builder_bankmachine0_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3420.4-3428.7" - switch $and$ls180.v:3420$253_Y - attribute \src "ls180.v:3420.8-3420.87" + attribute \src "ls180.v:3289.4-3297.7" + switch $and$ls180.v:3289$154_Y + attribute \src "ls180.v:3289.8-3289.87" case 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3422.5-3424.8" + attribute \src "ls180.v:3291.5-3293.8" switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3422.9-3422.42" + attribute \src "ls180.v:3291.9-3291.42" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'101 case @@ -291561,27 +288583,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3432.4-3434.7" - switch $and$ls180.v:3432$254_Y - attribute \src "ls180.v:3432.8-3432.87" + attribute \src "ls180.v:3301.4-3303.7" + switch $and$ls180.v:3301$155_Y + attribute \src "ls180.v:3301.8-3301.87" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3438.4-3447.7" + attribute \src "ls180.v:3307.4-3316.7" switch \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:3438.8-3438.44" + attribute \src "ls180.v:3307.8-3307.44" case 1'1 assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3443.5-3445.8" + attribute \src "ls180.v:3312.5-3314.8" switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3443.9-3443.42" + attribute \src "ls180.v:3312.9-3312.42" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'110 case @@ -291592,16 +288614,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3450.4-3452.7" + attribute \src "ls180.v:3319.4-3321.7" switch \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:3450.8-3450.45" + attribute \src "ls180.v:3319.8-3319.45" case 1'1 assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3455.4-3457.7" - switch $not$ls180.v:3455$255_Y - attribute \src "ls180.v:3455.8-3455.46" + attribute \src "ls180.v:3324.4-3326.7" + switch $not$ls180.v:3324$156_Y + attribute \src "ls180.v:3324.8-3324.46" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'000 case @@ -291614,51 +288636,51 @@ module \ls180 assign $0\builder_bankmachine0_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3466.4-3492.7" + attribute \src "ls180.v:3335.4-3361.7" switch \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:3466.8-3466.43" + attribute \src "ls180.v:3335.8-3335.43" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'100 - attribute \src "ls180.v:3468.8-3468.12" + attribute \src "ls180.v:3337.8-3337.12" case - attribute \src "ls180.v:3469.5-3491.8" + attribute \src "ls180.v:3338.5-3360.8" switch \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:3469.9-3469.56" + attribute \src "ls180.v:3338.9-3338.56" case 1'1 - attribute \src "ls180.v:3470.6-3490.9" + attribute \src "ls180.v:3339.6-3359.9" switch \main_sdram_bankmachine0_row_opened - attribute \src "ls180.v:3470.10-3470.44" + attribute \src "ls180.v:3339.10-3339.44" case 1'1 - attribute \src "ls180.v:3471.7-3487.10" + attribute \src "ls180.v:3340.7-3356.10" switch \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:3471.11-3471.42" + attribute \src "ls180.v:3340.11-3340.42" case 1'1 assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3473.8-3480.11" + attribute \src "ls180.v:3342.8-3349.11" switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:3473.12-3473.64" + attribute \src "ls180.v:3342.12-3342.64" case 1'1 assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3477.12-3477.16" + attribute \src "ls180.v:3346.12-3346.16" case assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3482.8-3484.11" - switch $and$ls180.v:3482$256_Y - attribute \src "ls180.v:3482.12-3482.88" + attribute \src "ls180.v:3351.8-3353.11" + switch $and$ls180.v:3351$157_Y + attribute \src "ls180.v:3351.12-3351.88" case 1'1 assign $0\builder_bankmachine0_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3485.11-3485.15" + attribute \src "ls180.v:3354.11-3354.15" case assign $0\builder_bankmachine0_next_state[2:0] 3'001 end - attribute \src "ls180.v:3488.10-3488.14" + attribute \src "ls180.v:3357.10-3357.14" case assign $0\builder_bankmachine0_next_state[2:0] 3'011 end @@ -291682,43 +288704,99 @@ module \ls180 update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:342.5-342.24" - process $proc$ls180.v:342$3197 + attribute \src "ls180.v:330.5-330.38" + process $proc$ls180.v:330$2967 assign { } { } - assign $1\main_int_rst[0:0] 1'1 + assign $0\main_sdram_command_issue_w[0:0] 1'0 sync always + update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] sync init - update \main_int_rst $1\main_int_rst[0:0] end - attribute \src "ls180.v:3510.1-3517.4" - process $proc$ls180.v:3510$260 + attribute \src "ls180.v:331.12-331.46" + process $proc$ls180.v:331$2968 + assign { } { } + assign $1\main_sdram_address_storage[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] + end + attribute \src "ls180.v:332.5-332.33" + process $proc$ls180.v:332$2969 + assign { } { } + assign $1\main_sdram_address_re[0:0] 1'0 + sync always + sync init + update \main_sdram_address_re $1\main_sdram_address_re[0:0] + end + attribute \src "ls180.v:333.11-333.45" + process $proc$ls180.v:333$2970 + assign { } { } + assign $1\main_sdram_baddress_storage[1:0] 2'00 + sync always + sync init + update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] + end + attribute \src "ls180.v:334.5-334.34" + process $proc$ls180.v:334$2971 + assign { } { } + assign $1\main_sdram_baddress_re[0:0] 1'0 + sync always + sync init + update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + end + attribute \src "ls180.v:335.12-335.45" + process $proc$ls180.v:335$2972 + assign { } { } + assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + end + attribute \src "ls180.v:336.5-336.32" + process $proc$ls180.v:336$2973 + assign { } { } + assign $1\main_sdram_wrdata_re[0:0] 1'0 + sync always + sync init + update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + end + attribute \src "ls180.v:337.12-337.37" + process $proc$ls180.v:337$2974 + assign { } { } + assign $1\main_sdram_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_status $1\main_sdram_status[15:0] + end + attribute \src "ls180.v:3379.1-3386.4" + process $proc$ls180.v:3379$161 assign { } { } assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3512.2-3516.5" + attribute \src "ls180.v:3381.2-3385.5" switch \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:3512.6-3512.48" + attribute \src "ls180.v:3381.6-3381.48" case 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3514.6-3514.10" + attribute \src "ls180.v:3383.6-3383.10" case - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3515$262_Y + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3384$163_Y end sync always update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:3521.1-3528.4" - process $proc$ls180.v:3521$269 + attribute \src "ls180.v:3390.1-3397.4" + process $proc$ls180.v:3390$170 assign { } { } assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3523.2-3527.5" - switch $and$ls180.v:3523$270_Y - attribute \src "ls180.v:3523.6-3523.115" + attribute \src "ls180.v:3392.2-3396.5" + switch $and$ls180.v:3392$171_Y + attribute \src "ls180.v:3392.6-3392.115" case 1'1 - attribute \src "ls180.v:3524.3-3526.6" - switch $ne$ls180.v:3524$271_Y - attribute \src "ls180.v:3524.7-3524.143" + attribute \src "ls180.v:3393.3-3395.6" + switch $ne$ls180.v:3393$172_Y + attribute \src "ls180.v:3393.7-3393.143" case 1'1 - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3525$272_Y + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3394$173_Y case end case @@ -291726,24 +288804,24 @@ module \ls180 sync always update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] end - attribute \src "ls180.v:3543.1-3550.4" - process $proc$ls180.v:3543$273 + attribute \src "ls180.v:3412.1-3419.4" + process $proc$ls180.v:3412$174 assign { } { } assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3545.2-3549.5" + attribute \src "ls180.v:3414.2-3418.5" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3545.6-3545.58" + attribute \src "ls180.v:3414.6-3414.58" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3546$274_Y - attribute \src "ls180.v:3547.6-3547.10" + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3415$175_Y + attribute \src "ls180.v:3416.6-3416.10" case assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:3559.1-3652.4" - process $proc$ls180.v:3559$282 + attribute \src "ls180.v:3428.1-3521.4" + process $proc$ls180.v:3428$183 assign { } { } assign { } { } assign { } { } @@ -291758,8 +288836,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 assign { } { } assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 @@ -291772,23 +288848,25 @@ module \ls180 assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state - attribute \src "ls180.v:3575.2-3651.9" + attribute \src "ls180.v:3444.2-3520.9" switch \builder_bankmachine1_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3577.4-3585.7" - switch $and$ls180.v:3577$283_Y - attribute \src "ls180.v:3577.8-3577.87" + attribute \src "ls180.v:3446.4-3454.7" + switch $and$ls180.v:3446$184_Y + attribute \src "ls180.v:3446.8-3446.87" case 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3579.5-3581.8" + attribute \src "ls180.v:3448.5-3450.8" switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3579.9-3579.42" + attribute \src "ls180.v:3448.9-3448.42" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'101 case @@ -291798,27 +288876,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3589.4-3591.7" - switch $and$ls180.v:3589$284_Y - attribute \src "ls180.v:3589.8-3589.87" + attribute \src "ls180.v:3458.4-3460.7" + switch $and$ls180.v:3458$185_Y + attribute \src "ls180.v:3458.8-3458.87" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3595.4-3604.7" + attribute \src "ls180.v:3464.4-3473.7" switch \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:3595.8-3595.44" + attribute \src "ls180.v:3464.8-3464.44" case 1'1 assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3600.5-3602.8" + attribute \src "ls180.v:3469.5-3471.8" switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3600.9-3600.42" + attribute \src "ls180.v:3469.9-3469.42" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'110 case @@ -291829,16 +288907,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3607.4-3609.7" + attribute \src "ls180.v:3476.4-3478.7" switch \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:3607.8-3607.45" + attribute \src "ls180.v:3476.8-3476.45" case 1'1 assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3612.4-3614.7" - switch $not$ls180.v:3612$285_Y - attribute \src "ls180.v:3612.8-3612.46" + attribute \src "ls180.v:3481.4-3483.7" + switch $not$ls180.v:3481$186_Y + attribute \src "ls180.v:3481.8-3481.46" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'000 case @@ -291851,51 +288929,51 @@ module \ls180 assign $0\builder_bankmachine1_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3623.4-3649.7" + attribute \src "ls180.v:3492.4-3518.7" switch \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:3623.8-3623.43" + attribute \src "ls180.v:3492.8-3492.43" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'100 - attribute \src "ls180.v:3625.8-3625.12" + attribute \src "ls180.v:3494.8-3494.12" case - attribute \src "ls180.v:3626.5-3648.8" + attribute \src "ls180.v:3495.5-3517.8" switch \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:3626.9-3626.56" + attribute \src "ls180.v:3495.9-3495.56" case 1'1 - attribute \src "ls180.v:3627.6-3647.9" + attribute \src "ls180.v:3496.6-3516.9" switch \main_sdram_bankmachine1_row_opened - attribute \src "ls180.v:3627.10-3627.44" + attribute \src "ls180.v:3496.10-3496.44" case 1'1 - attribute \src "ls180.v:3628.7-3644.10" + attribute \src "ls180.v:3497.7-3513.10" switch \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:3628.11-3628.42" + attribute \src "ls180.v:3497.11-3497.42" case 1'1 assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3630.8-3637.11" + attribute \src "ls180.v:3499.8-3506.11" switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:3630.12-3630.64" + attribute \src "ls180.v:3499.12-3499.64" case 1'1 assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3634.12-3634.16" + attribute \src "ls180.v:3503.12-3503.16" case assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3639.8-3641.11" - switch $and$ls180.v:3639$286_Y - attribute \src "ls180.v:3639.12-3639.88" + attribute \src "ls180.v:3508.8-3510.11" + switch $and$ls180.v:3508$187_Y + attribute \src "ls180.v:3508.12-3508.88" case 1'1 assign $0\builder_bankmachine1_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3642.11-3642.15" + attribute \src "ls180.v:3511.11-3511.15" case assign $0\builder_bankmachine1_next_state[2:0] 3'001 end - attribute \src "ls180.v:3645.10-3645.14" + attribute \src "ls180.v:3514.10-3514.14" case assign $0\builder_bankmachine1_next_state[2:0] 3'011 end @@ -291919,91 +288997,35 @@ module \ls180 update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:357.12-357.38" - process $proc$ls180.v:357$3198 - assign { } { } - assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] - end - attribute \src "ls180.v:358.5-358.36" - process $proc$ls180.v:358$3199 - assign { } { } - assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:359.11-359.32" - process $proc$ls180.v:359$3200 - assign { } { } - assign $1\main_rddata_en[2:0] 3'000 - sync always - sync init - update \main_rddata_en $1\main_rddata_en[2:0] - end - attribute \src "ls180.v:362.5-362.36" - process $proc$ls180.v:362$3201 - assign { } { } - assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] - end - attribute \src "ls180.v:363.5-363.35" - process $proc$ls180.v:363$3202 - assign { } { } - assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] - end - attribute \src "ls180.v:364.5-364.36" - process $proc$ls180.v:364$3203 - assign { } { } - assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] - end - attribute \src "ls180.v:365.5-365.35" - process $proc$ls180.v:365$3204 - assign { } { } - assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] - end - attribute \src "ls180.v:3667.1-3674.4" - process $proc$ls180.v:3667$290 + attribute \src "ls180.v:3536.1-3543.4" + process $proc$ls180.v:3536$191 assign { } { } assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3669.2-3673.5" + attribute \src "ls180.v:3538.2-3542.5" switch \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:3669.6-3669.48" + attribute \src "ls180.v:3538.6-3538.48" case 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3671.6-3671.10" + attribute \src "ls180.v:3540.6-3540.10" case - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3672$292_Y + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3541$193_Y end sync always update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:3678.1-3685.4" - process $proc$ls180.v:3678$299 + attribute \src "ls180.v:3547.1-3554.4" + process $proc$ls180.v:3547$200 assign { } { } assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3680.2-3684.5" - switch $and$ls180.v:3680$300_Y - attribute \src "ls180.v:3680.6-3680.115" + attribute \src "ls180.v:3549.2-3553.5" + switch $and$ls180.v:3549$201_Y + attribute \src "ls180.v:3549.6-3549.115" case 1'1 - attribute \src "ls180.v:3681.3-3683.6" - switch $ne$ls180.v:3681$301_Y - attribute \src "ls180.v:3681.7-3681.143" + attribute \src "ls180.v:3550.3-3552.6" + switch $ne$ls180.v:3550$202_Y + attribute \src "ls180.v:3550.7-3550.143" case 1'1 - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3682$302_Y + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3551$203_Y case end case @@ -292011,32 +289033,24 @@ module \ls180 sync always update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:369.5-369.36" - process $proc$ls180.v:369$3205 - assign { } { } - assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 - sync always - update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] - sync init - end - attribute \src "ls180.v:3700.1-3707.4" - process $proc$ls180.v:3700$303 + attribute \src "ls180.v:3569.1-3576.4" + process $proc$ls180.v:3569$204 assign { } { } assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3702.2-3706.5" + attribute \src "ls180.v:3571.2-3575.5" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3702.6-3702.58" + attribute \src "ls180.v:3571.6-3571.58" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3703$304_Y - attribute \src "ls180.v:3704.6-3704.10" + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3572$205_Y + attribute \src "ls180.v:3573.6-3573.10" case assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:3716.1-3809.4" - process $proc$ls180.v:3716$312 + attribute \src "ls180.v:3585.1-3678.4" + process $proc$ls180.v:3585$213 assign { } { } assign { } { } assign { } { } @@ -292051,37 +289065,37 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 assign { } { } assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state - attribute \src "ls180.v:3732.2-3808.9" + attribute \src "ls180.v:3601.2-3677.9" switch \builder_bankmachine2_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3734.4-3742.7" - switch $and$ls180.v:3734$313_Y - attribute \src "ls180.v:3734.8-3734.87" + attribute \src "ls180.v:3603.4-3611.7" + switch $and$ls180.v:3603$214_Y + attribute \src "ls180.v:3603.8-3603.87" case 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3736.5-3738.8" + attribute \src "ls180.v:3605.5-3607.8" switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3736.9-3736.42" + attribute \src "ls180.v:3605.9-3605.42" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'101 case @@ -292091,27 +289105,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3746.4-3748.7" - switch $and$ls180.v:3746$314_Y - attribute \src "ls180.v:3746.8-3746.87" + attribute \src "ls180.v:3615.4-3617.7" + switch $and$ls180.v:3615$215_Y + attribute \src "ls180.v:3615.8-3615.87" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3752.4-3761.7" + attribute \src "ls180.v:3621.4-3630.7" switch \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:3752.8-3752.44" + attribute \src "ls180.v:3621.8-3621.44" case 1'1 assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3757.5-3759.8" + attribute \src "ls180.v:3626.5-3628.8" switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3757.9-3757.42" + attribute \src "ls180.v:3626.9-3626.42" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'110 case @@ -292122,16 +289136,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3764.4-3766.7" + attribute \src "ls180.v:3633.4-3635.7" switch \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:3764.8-3764.45" + attribute \src "ls180.v:3633.8-3633.45" case 1'1 assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3769.4-3771.7" - switch $not$ls180.v:3769$315_Y - attribute \src "ls180.v:3769.8-3769.46" + attribute \src "ls180.v:3638.4-3640.7" + switch $not$ls180.v:3638$216_Y + attribute \src "ls180.v:3638.8-3638.46" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'000 case @@ -292144,51 +289158,51 @@ module \ls180 assign $0\builder_bankmachine2_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3780.4-3806.7" + attribute \src "ls180.v:3649.4-3675.7" switch \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:3780.8-3780.43" + attribute \src "ls180.v:3649.8-3649.43" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'100 - attribute \src "ls180.v:3782.8-3782.12" + attribute \src "ls180.v:3651.8-3651.12" case - attribute \src "ls180.v:3783.5-3805.8" + attribute \src "ls180.v:3652.5-3674.8" switch \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:3783.9-3783.56" + attribute \src "ls180.v:3652.9-3652.56" case 1'1 - attribute \src "ls180.v:3784.6-3804.9" + attribute \src "ls180.v:3653.6-3673.9" switch \main_sdram_bankmachine2_row_opened - attribute \src "ls180.v:3784.10-3784.44" + attribute \src "ls180.v:3653.10-3653.44" case 1'1 - attribute \src "ls180.v:3785.7-3801.10" + attribute \src "ls180.v:3654.7-3670.10" switch \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:3785.11-3785.42" + attribute \src "ls180.v:3654.11-3654.42" case 1'1 assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3787.8-3794.11" + attribute \src "ls180.v:3656.8-3663.11" switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:3787.12-3787.64" + attribute \src "ls180.v:3656.12-3656.64" case 1'1 assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3791.12-3791.16" + attribute \src "ls180.v:3660.12-3660.16" case assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3796.8-3798.11" - switch $and$ls180.v:3796$316_Y - attribute \src "ls180.v:3796.12-3796.88" + attribute \src "ls180.v:3665.8-3667.11" + switch $and$ls180.v:3665$217_Y + attribute \src "ls180.v:3665.12-3665.88" case 1'1 assign $0\builder_bankmachine2_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3799.11-3799.15" + attribute \src "ls180.v:3668.11-3668.15" case assign $0\builder_bankmachine2_next_state[2:0] 3'001 end - attribute \src "ls180.v:3802.10-3802.14" + attribute \src "ls180.v:3671.10-3671.14" case assign $0\builder_bankmachine2_next_state[2:0] 3'011 end @@ -292212,51 +289226,59 @@ module \ls180 update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:374.12-374.45" - process $proc$ls180.v:374$3206 + attribute \src "ls180.v:367.12-367.46" + process $proc$ls180.v:367$2975 assign { } { } - assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] + update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] end - attribute \src "ls180.v:375.5-375.43" - process $proc$ls180.v:375$3207 + attribute \src "ls180.v:368.11-368.47" + process $proc$ls180.v:368$2976 assign { } { } - assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + assign $1\main_sdram_interface_wdata_we[1:0] 2'00 sync always sync init - update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] + update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:3824.1-3831.4" - process $proc$ls180.v:3824$320 + attribute \src "ls180.v:3693.1-3700.4" + process $proc$ls180.v:3693$221 assign { } { } assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3826.2-3830.5" + attribute \src "ls180.v:3695.2-3699.5" switch \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:3826.6-3826.48" + attribute \src "ls180.v:3695.6-3695.48" case 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3828.6-3828.10" + attribute \src "ls180.v:3697.6-3697.10" case - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3829$322_Y + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3698$223_Y end sync always update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "ls180.v:3835.1-3842.4" - process $proc$ls180.v:3835$329 + attribute \src "ls180.v:370.12-370.45" + process $proc$ls180.v:370$2977 + assign { } { } + assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] + end + attribute \src "ls180.v:3704.1-3711.4" + process $proc$ls180.v:3704$230 assign { } { } assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3837.2-3841.5" - switch $and$ls180.v:3837$330_Y - attribute \src "ls180.v:3837.6-3837.115" + attribute \src "ls180.v:3706.2-3710.5" + switch $and$ls180.v:3706$231_Y + attribute \src "ls180.v:3706.6-3706.115" case 1'1 - attribute \src "ls180.v:3838.3-3840.6" - switch $ne$ls180.v:3838$331_Y - attribute \src "ls180.v:3838.7-3838.143" + attribute \src "ls180.v:3707.3-3709.6" + switch $ne$ls180.v:3707$232_Y + attribute \src "ls180.v:3707.7-3707.143" case 1'1 - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3839$332_Y + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3708$233_Y case end case @@ -292264,25 +289286,56 @@ module \ls180 sync always update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] end - attribute \src "ls180.v:3857.1-3864.4" - process $proc$ls180.v:3857$333 + attribute \src "ls180.v:371.11-371.40" + process $proc$ls180.v:371$2978 + assign { } { } + assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] + end + attribute \src "ls180.v:372.5-372.35" + process $proc$ls180.v:372$2979 + assign { } { } + assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] + end + attribute \src "ls180.v:3726.1-3733.4" + process $proc$ls180.v:3726$234 assign { } { } assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3859.2-3863.5" + attribute \src "ls180.v:3728.2-3732.5" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3859.6-3859.58" + attribute \src "ls180.v:3728.6-3728.58" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3860$334_Y - attribute \src "ls180.v:3861.6-3861.10" + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3729$235_Y + attribute \src "ls180.v:3730.6-3730.10" case assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce end sync always update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:3873.1-3966.4" - process $proc$ls180.v:3873$342 + attribute \src "ls180.v:373.5-373.34" + process $proc$ls180.v:373$2980 assign { } { } + assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] + end + attribute \src "ls180.v:374.5-374.35" + process $proc$ls180.v:374$2981 + assign { } { } + assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] + end + attribute \src "ls180.v:3742.1-3835.4" + process $proc$ls180.v:3742$243 assign { } { } assign { } { } assign { } { } @@ -292296,37 +289349,38 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign { } { } assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state - attribute \src "ls180.v:3889.2-3965.9" + attribute \src "ls180.v:3758.2-3834.9" switch \builder_bankmachine3_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3891.4-3899.7" - switch $and$ls180.v:3891$343_Y - attribute \src "ls180.v:3891.8-3891.87" + attribute \src "ls180.v:3760.4-3768.7" + switch $and$ls180.v:3760$244_Y + attribute \src "ls180.v:3760.8-3760.87" case 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3893.5-3895.8" + attribute \src "ls180.v:3762.5-3764.8" switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3893.9-3893.42" + attribute \src "ls180.v:3762.9-3762.42" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'101 case @@ -292336,27 +289390,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3903.4-3905.7" - switch $and$ls180.v:3903$344_Y - attribute \src "ls180.v:3903.8-3903.87" + attribute \src "ls180.v:3772.4-3774.7" + switch $and$ls180.v:3772$245_Y + attribute \src "ls180.v:3772.8-3772.87" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:3909.4-3918.7" + attribute \src "ls180.v:3778.4-3787.7" switch \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:3909.8-3909.44" + attribute \src "ls180.v:3778.8-3778.44" case 1'1 assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3914.5-3916.8" + attribute \src "ls180.v:3783.5-3785.8" switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3914.9-3914.42" + attribute \src "ls180.v:3783.9-3783.42" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'110 case @@ -292367,16 +289421,16 @@ module \ls180 case 3'100 assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3921.4-3923.7" + attribute \src "ls180.v:3790.4-3792.7" switch \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:3921.8-3921.45" + attribute \src "ls180.v:3790.8-3790.45" case 1'1 assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:3926.4-3928.7" - switch $not$ls180.v:3926$345_Y - attribute \src "ls180.v:3926.8-3926.46" + attribute \src "ls180.v:3795.4-3797.7" + switch $not$ls180.v:3795$246_Y + attribute \src "ls180.v:3795.8-3795.46" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'000 case @@ -292389,51 +289443,51 @@ module \ls180 assign $0\builder_bankmachine3_next_state[2:0] 3'000 attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3937.4-3963.7" + attribute \src "ls180.v:3806.4-3832.7" switch \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:3937.8-3937.43" + attribute \src "ls180.v:3806.8-3806.43" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'100 - attribute \src "ls180.v:3939.8-3939.12" + attribute \src "ls180.v:3808.8-3808.12" case - attribute \src "ls180.v:3940.5-3962.8" + attribute \src "ls180.v:3809.5-3831.8" switch \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:3940.9-3940.56" + attribute \src "ls180.v:3809.9-3809.56" case 1'1 - attribute \src "ls180.v:3941.6-3961.9" + attribute \src "ls180.v:3810.6-3830.9" switch \main_sdram_bankmachine3_row_opened - attribute \src "ls180.v:3941.10-3941.44" + attribute \src "ls180.v:3810.10-3810.44" case 1'1 - attribute \src "ls180.v:3942.7-3958.10" + attribute \src "ls180.v:3811.7-3827.10" switch \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:3942.11-3942.42" + attribute \src "ls180.v:3811.11-3811.42" case 1'1 assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3944.8-3951.11" + attribute \src "ls180.v:3813.8-3820.11" switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:3944.12-3944.64" + attribute \src "ls180.v:3813.12-3813.64" case 1'1 assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3948.12-3948.16" + attribute \src "ls180.v:3817.12-3817.16" case assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 end - attribute \src "ls180.v:3953.8-3955.11" - switch $and$ls180.v:3953$346_Y - attribute \src "ls180.v:3953.12-3953.88" + attribute \src "ls180.v:3822.8-3824.11" + switch $and$ls180.v:3822$247_Y + attribute \src "ls180.v:3822.12-3822.88" case 1'1 assign $0\builder_bankmachine3_next_state[2:0] 3'010 case end - attribute \src "ls180.v:3956.11-3956.15" + attribute \src "ls180.v:3825.11-3825.15" case assign $0\builder_bankmachine3_next_state[2:0] 3'001 end - attribute \src "ls180.v:3959.10-3959.14" + attribute \src "ls180.v:3828.10-3828.14" case assign $0\builder_bankmachine3_next_state[2:0] 3'011 end @@ -292457,112 +289511,64 @@ module \ls180 update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:390.12-390.46" - process $proc$ls180.v:390$3208 + attribute \src "ls180.v:375.5-375.34" + process $proc$ls180.v:375$2982 assign { } { } - assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] - end - attribute \src "ls180.v:391.5-391.44" - process $proc$ls180.v:391$3209 - assign { } { } - assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:392.12-392.48" - process $proc$ls180.v:392$3210 - assign { } { } - assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] - end - attribute \src "ls180.v:393.11-393.43" - process $proc$ls180.v:393$3211 - assign { } { } - assign $1\main_sdram_master_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] - end - attribute \src "ls180.v:394.5-394.38" - process $proc$ls180.v:394$3212 - assign { } { } - assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] - end - attribute \src "ls180.v:395.5-395.37" - process $proc$ls180.v:395$3213 - assign { } { } - assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 + assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 sync always sync init - update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] + update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] end - attribute \src "ls180.v:396.5-396.38" - process $proc$ls180.v:396$3214 + attribute \src "ls180.v:379.5-379.35" + process $proc$ls180.v:379$2983 assign { } { } - assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 sync always + update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] sync init - update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] end - attribute \src "ls180.v:397.5-397.37" - process $proc$ls180.v:397$3215 + attribute \src "ls180.v:381.5-381.39" + process $proc$ls180.v:381$2984 assign { } { } - assign $1\main_sdram_master_p0_we_n[0:0] 1'1 + assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 sync always sync init - update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] + update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] end - attribute \src "ls180.v:398.5-398.36" - process $proc$ls180.v:398$3216 + attribute \src "ls180.v:383.5-383.39" + process $proc$ls180.v:383$2985 assign { } { } - assign $1\main_sdram_master_p0_cke[0:0] 1'0 + assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 sync always sync init - update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] + update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] end - attribute \src "ls180.v:3986.1-3992.4" - process $proc$ls180.v:3986$385 + attribute \src "ls180.v:3855.1-3861.4" + process $proc$ls180.v:3855$286 assign { } { } assign { } { } - assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3988$398_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3989$411_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3990$424_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3991$437_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3857$299_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3858$312_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3859$325_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3860$338_Y sync always update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] end - attribute \src "ls180.v:399.5-399.36" - process $proc$ls180.v:399$3217 + attribute \src "ls180.v:386.5-386.32" + process $proc$ls180.v:386$2986 assign { } { } - assign $1\main_sdram_master_p0_odt[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] - end - attribute \src "ls180.v:400.5-400.40" - process $proc$ls180.v:400$3218 - assign { } { } - assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + assign $1\main_sdram_cmd_valid[0:0] 1'0 sync always sync init - update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] end - attribute \src "ls180.v:4000.1-4005.4" - process $proc$ls180.v:4000$438 + attribute \src "ls180.v:3869.1-3874.4" + process $proc$ls180.v:3869$339 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:4002.2-4004.5" + attribute \src "ls180.v:3871.2-3873.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:4002.6-4002.37" + attribute \src "ls180.v:3871.6-3871.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 case @@ -292570,13 +289576,21 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "ls180.v:4006.1-4011.4" - process $proc$ls180.v:4006$439 + attribute \src "ls180.v:387.5-387.32" + process $proc$ls180.v:387$2987 + assign { } { } + assign $1\main_sdram_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] + end + attribute \src "ls180.v:3875.1-3880.4" + process $proc$ls180.v:3875$340 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:4008.2-4010.5" + attribute \src "ls180.v:3877.2-3879.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:4008.6-4008.37" + attribute \src "ls180.v:3877.6-3877.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 case @@ -292584,21 +289598,21 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "ls180.v:401.5-401.38" - process $proc$ls180.v:401$3219 + attribute \src "ls180.v:388.5-388.31" + process $proc$ls180.v:388$2988 assign { } { } - assign $1\main_sdram_master_p0_act_n[0:0] 1'1 + assign $1\main_sdram_cmd_last[0:0] 1'0 sync always sync init - update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] + update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] end - attribute \src "ls180.v:4012.1-4017.4" - process $proc$ls180.v:4012$440 + attribute \src "ls180.v:3881.1-3886.4" + process $proc$ls180.v:3881$341 assign { } { } assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:4014.2-4016.5" + attribute \src "ls180.v:3883.2-3885.5" switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:4014.6-4014.37" + attribute \src "ls180.v:3883.6-3883.37" case 1'1 assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 case @@ -292606,40 +289620,40 @@ module \ls180 sync always update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "ls180.v:4019.1-4025.4" - process $proc$ls180.v:4019$443 + attribute \src "ls180.v:3888.1-3894.4" + process $proc$ls180.v:3888$344 assign { } { } assign { } { } - assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:4021$456_Y - assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:4022$469_Y - assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:4023$482_Y - assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:4024$495_Y + assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3890$357_Y + assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3891$370_Y + assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3892$383_Y + assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3893$396_Y sync always update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] end - attribute \src "ls180.v:402.12-402.47" - process $proc$ls180.v:402$3220 + attribute \src "ls180.v:389.12-389.44" + process $proc$ls180.v:389$2989 assign { } { } - assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 sync always sync init - update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] + update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] end - attribute \src "ls180.v:403.5-403.42" - process $proc$ls180.v:403$3221 + attribute \src "ls180.v:390.11-390.43" + process $proc$ls180.v:390$2990 assign { } { } - assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 sync always sync init - update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] + update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] end - attribute \src "ls180.v:4033.1-4038.4" - process $proc$ls180.v:4033$496 + attribute \src "ls180.v:3902.1-3907.4" + process $proc$ls180.v:3902$397 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:4035.2-4037.5" + attribute \src "ls180.v:3904.2-3906.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:4035.6-4035.37" + attribute \src "ls180.v:3904.6-3904.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 case @@ -292647,13 +289661,13 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:4039.1-4044.4" - process $proc$ls180.v:4039$497 + attribute \src "ls180.v:3908.1-3913.4" + process $proc$ls180.v:3908$398 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:4041.2-4043.5" + attribute \src "ls180.v:3910.2-3912.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:4041.6-4041.37" + attribute \src "ls180.v:3910.6-3910.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 case @@ -292661,21 +289675,21 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "ls180.v:404.11-404.50" - process $proc$ls180.v:404$3222 + attribute \src "ls180.v:391.5-391.38" + process $proc$ls180.v:391$2991 assign { } { } - assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 sync always sync init - update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] end - attribute \src "ls180.v:4045.1-4050.4" - process $proc$ls180.v:4045$498 + attribute \src "ls180.v:3914.1-3919.4" + process $proc$ls180.v:3914$399 assign { } { } assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:4047.2-4049.5" + attribute \src "ls180.v:3916.2-3918.5" switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:4047.6-4047.37" + attribute \src "ls180.v:3916.6-3916.37" case 1'1 assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 case @@ -292683,28 +289697,28 @@ module \ls180 sync always update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:405.5-405.42" - process $proc$ls180.v:405$3223 + attribute \src "ls180.v:392.5-392.38" + process $proc$ls180.v:392$2992 assign { } { } - assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 sync always sync init - update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] end - attribute \src "ls180.v:4051.1-4059.4" - process $proc$ls180.v:4051$499 + attribute \src "ls180.v:3920.1-3928.4" + process $proc$ls180.v:3920$400 assign { } { } assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:4053.2-4055.5" - switch $and$ls180.v:4053$502_Y - attribute \src "ls180.v:4053.6-4053.115" + attribute \src "ls180.v:3922.2-3924.5" + switch $and$ls180.v:3922$403_Y + attribute \src "ls180.v:3922.6-3922.115" case 1'1 assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:4056.2-4058.5" - switch $and$ls180.v:4056$505_Y - attribute \src "ls180.v:4056.6-4056.115" + attribute \src "ls180.v:3925.2-3927.5" + switch $and$ls180.v:3925$406_Y + attribute \src "ls180.v:3925.6-3925.115" case 1'1 assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 case @@ -292712,20 +289726,20 @@ module \ls180 sync always update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] end - attribute \src "ls180.v:4060.1-4068.4" - process $proc$ls180.v:4060$506 + attribute \src "ls180.v:3929.1-3937.4" + process $proc$ls180.v:3929$407 assign { } { } assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:4062.2-4064.5" - switch $and$ls180.v:4062$509_Y - attribute \src "ls180.v:4062.6-4062.115" + attribute \src "ls180.v:3931.2-3933.5" + switch $and$ls180.v:3931$410_Y + attribute \src "ls180.v:3931.6-3931.115" case 1'1 assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:4065.2-4067.5" - switch $and$ls180.v:4065$512_Y - attribute \src "ls180.v:4065.6-4065.115" + attribute \src "ls180.v:3934.2-3936.5" + switch $and$ls180.v:3934$413_Y + attribute \src "ls180.v:3934.6-3934.115" case 1'1 assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 case @@ -292733,20 +289747,28 @@ module \ls180 sync always update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] end - attribute \src "ls180.v:4069.1-4077.4" - process $proc$ls180.v:4069$513 + attribute \src "ls180.v:393.5-393.37" + process $proc$ls180.v:393$2993 + assign { } { } + assign $1\main_sdram_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] + end + attribute \src "ls180.v:3938.1-3946.4" + process $proc$ls180.v:3938$414 assign { } { } assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:4071.2-4073.5" - switch $and$ls180.v:4071$516_Y - attribute \src "ls180.v:4071.6-4071.115" + attribute \src "ls180.v:3940.2-3942.5" + switch $and$ls180.v:3940$417_Y + attribute \src "ls180.v:3940.6-3940.115" case 1'1 assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:4074.2-4076.5" - switch $and$ls180.v:4074$519_Y - attribute \src "ls180.v:4074.6-4074.115" + attribute \src "ls180.v:3943.2-3945.5" + switch $and$ls180.v:3943$420_Y + attribute \src "ls180.v:3943.6-3943.115" case 1'1 assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 case @@ -292754,20 +289776,28 @@ module \ls180 sync always update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:4078.1-4086.4" - process $proc$ls180.v:4078$520 + attribute \src "ls180.v:394.5-394.42" + process $proc$ls180.v:394$2994 + assign { } { } + assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] + sync init + end + attribute \src "ls180.v:3947.1-3955.4" + process $proc$ls180.v:3947$421 assign { } { } assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:4080.2-4082.5" - switch $and$ls180.v:4080$523_Y - attribute \src "ls180.v:4080.6-4080.115" + attribute \src "ls180.v:3949.2-3951.5" + switch $and$ls180.v:3949$424_Y + attribute \src "ls180.v:3949.6-3949.115" case 1'1 assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 case end - attribute \src "ls180.v:4083.2-4085.5" - switch $and$ls180.v:4083$526_Y - attribute \src "ls180.v:4083.6-4083.115" + attribute \src "ls180.v:3952.2-3954.5" + switch $and$ls180.v:3952$427_Y + attribute \src "ls180.v:3952.6-3952.115" case 1'1 assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 case @@ -292775,9 +289805,16 @@ module \ls180 sync always update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "ls180.v:4091.1-4163.4" - process $proc$ls180.v:4091$529 + attribute \src "ls180.v:395.5-395.43" + process $proc$ls180.v:395$2995 assign { } { } + assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] + sync init + end + attribute \src "ls180.v:3960.1-4032.4" + process $proc$ls180.v:3960$430 assign { } { } assign { } { } assign { } { } @@ -292795,38 +289832,39 @@ module \ls180 assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 assign $0\main_sdram_steerer_sel[1:0] 2'00 assign $0\main_sdram_en0[0:0] 1'0 + assign { } { } assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state - attribute \src "ls180.v:4103.2-4162.9" + attribute \src "ls180.v:3972.2-4031.9" switch \builder_multiplexer_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdram_en1[0:0] 1'1 assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:4107.4-4113.7" + attribute \src "ls180.v:3976.4-3982.7" switch 1'1 - attribute \src "ls180.v:4107.8-4107.12" + attribute \src "ls180.v:3976.8-3976.12" case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4108$536_Y + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3977$437_Y case end - attribute \src "ls180.v:4115.4-4119.7" + attribute \src "ls180.v:3984.4-3988.7" switch \main_sdram_read_available - attribute \src "ls180.v:4115.8-4115.33" + attribute \src "ls180.v:3984.8-3984.33" case 1'1 - attribute \src "ls180.v:4116.5-4118.8" - switch $or$ls180.v:4116$538_Y - attribute \src "ls180.v:4116.9-4116.63" + attribute \src "ls180.v:3985.5-3987.8" + switch $or$ls180.v:3985$439_Y + attribute \src "ls180.v:3985.9-3985.63" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'011 case end case end - attribute \src "ls180.v:4120.4-4122.7" + attribute \src "ls180.v:3989.4-3991.7" switch \main_sdram_go_to_refresh - attribute \src "ls180.v:4120.8-4120.32" + attribute \src "ls180.v:3989.8-3989.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'010 case @@ -292835,18 +289873,18 @@ module \ls180 case 3'010 assign $0\main_sdram_steerer_sel[1:0] 2'11 assign $0\main_sdram_cmd_ready[0:0] 1'1 - attribute \src "ls180.v:4127.4-4129.7" + attribute \src "ls180.v:3996.4-3998.7" switch \main_sdram_cmd_last - attribute \src "ls180.v:4127.8-4127.27" + attribute \src "ls180.v:3996.8-3996.27" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:4132.4-4134.7" + attribute \src "ls180.v:4001.4-4003.7" switch \main_sdram_twtrcon_ready - attribute \src "ls180.v:4132.8-4132.32" + attribute \src "ls180.v:4001.8-4001.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'000 case @@ -292862,29 +289900,29 @@ module \ls180 assign $0\main_sdram_en0[0:0] 1'1 assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:4145.4-4151.7" + attribute \src "ls180.v:4014.4-4020.7" switch 1'1 - attribute \src "ls180.v:4145.8-4145.12" + attribute \src "ls180.v:4014.8-4014.12" case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4146$545_Y + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4015$446_Y case end - attribute \src "ls180.v:4153.4-4157.7" + attribute \src "ls180.v:4022.4-4026.7" switch \main_sdram_write_available - attribute \src "ls180.v:4153.8-4153.34" + attribute \src "ls180.v:4022.8-4022.34" case 1'1 - attribute \src "ls180.v:4154.5-4156.8" - switch $or$ls180.v:4154$547_Y - attribute \src "ls180.v:4154.9-4154.62" + attribute \src "ls180.v:4023.5-4025.8" + switch $or$ls180.v:4023$448_Y + attribute \src "ls180.v:4023.9-4023.62" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'100 case end case end - attribute \src "ls180.v:4158.4-4160.7" + attribute \src "ls180.v:4027.4-4029.7" switch \main_sdram_go_to_refresh - attribute \src "ls180.v:4158.8-4158.32" + attribute \src "ls180.v:4027.8-4027.32" case 1'1 assign $0\builder_multiplexer_next_state[2:0] 3'010 case @@ -292901,45 +289939,45 @@ module \ls180 update \main_sdram_en1 $0\main_sdram_en1[0:0] update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] end - attribute \src "ls180.v:412.11-412.36" - process $proc$ls180.v:412$3224 + attribute \src "ls180.v:401.11-401.44" + process $proc$ls180.v:401$2996 assign { } { } - assign $1\main_sdram_storage[3:0] 4'0001 + assign $1\main_sdram_timer_count1[9:0] 10'1100001101 sync always sync init - update \main_sdram_storage $1\main_sdram_storage[3:0] + update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] end - attribute \src "ls180.v:413.5-413.25" - process $proc$ls180.v:413$3225 + attribute \src "ls180.v:403.5-403.38" + process $proc$ls180.v:403$2997 assign { } { } - assign $1\main_sdram_re[0:0] 1'0 + assign $1\main_sdram_postponer_req_o[0:0] 1'0 sync always sync init - update \main_sdram_re $1\main_sdram_re[0:0] + update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] end - attribute \src "ls180.v:414.11-414.44" - process $proc$ls180.v:414$3226 + attribute \src "ls180.v:404.5-404.38" + process $proc$ls180.v:404$2998 assign { } { } - assign $1\main_sdram_command_storage[5:0] 6'000000 + assign $1\main_sdram_postponer_count[0:0] 1'0 sync always sync init - update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] + update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] end - attribute \src "ls180.v:415.5-415.33" - process $proc$ls180.v:415$3227 + attribute \src "ls180.v:405.5-405.39" + process $proc$ls180.v:405$2999 assign { } { } - assign $1\main_sdram_command_re[0:0] 1'0 + assign $1\main_sdram_sequencer_start0[0:0] 1'0 sync always sync init - update \main_sdram_command_re $1\main_sdram_command_re[0:0] + update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] end - attribute \src "ls180.v:4187.1-4200.4" - process $proc$ls180.v:4187$676 + attribute \src "ls180.v:4056.1-4069.4" + process $proc$ls180.v:4056$577 assign { } { } assign { } { } assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - attribute \src "ls180.v:4190.2-4199.9" + attribute \src "ls180.v:4059.2-4068.9" switch \builder_new_master_wdata_ready attribute \src "ls180.v:0.0-0.0" case 1'1 @@ -292954,27 +289992,11 @@ module \ls180 update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:419.5-419.38" - process $proc$ls180.v:419$3228 - assign { } { } - assign $0\main_sdram_command_issue_w[0:0] 1'0 - sync always - update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] - sync init - end - attribute \src "ls180.v:420.12-420.46" - process $proc$ls180.v:420$3229 - assign { } { } - assign $1\main_sdram_address_storage[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] - end - attribute \src "ls180.v:4207.1-4217.4" - process $proc$ls180.v:4207$678 + attribute \src "ls180.v:4076.1-4086.4" + process $proc$ls180.v:4076$579 assign { } { } assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 - attribute \src "ls180.v:4209.2-4216.9" + attribute \src "ls180.v:4078.2-4085.9" switch \main_converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -292987,16 +290009,16 @@ module \ls180 sync always update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:421.5-421.33" - process $proc$ls180.v:421$3230 + attribute \src "ls180.v:408.5-408.38" + process $proc$ls180.v:408$3000 assign { } { } - assign $1\main_sdram_address_re[0:0] 1'0 + assign $1\main_sdram_sequencer_done1[0:0] 1'0 sync always sync init - update \main_sdram_address_re $1\main_sdram_address_re[0:0] + update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] end - attribute \src "ls180.v:4219.1-4265.4" - process $proc$ls180.v:4219$679 + attribute \src "ls180.v:4088.1-4134.4" + process $proc$ls180.v:4088$580 assign { } { } assign { } { } assign { } { } @@ -293007,7 +290029,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_litedram_wb_sel[1:0] 2'00 assign $0\main_litedram_wb_cyc[0:0] 1'0 assign { } { } assign $0\main_litedram_wb_stb[0:0] 1'0 @@ -293017,13 +290038,14 @@ module \ls180 assign $0\main_converter_skip[0:0] 1'0 assign $0\main_wb_sdram_ack[0:0] 1'0 assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_litedram_wb_sel[1:0] 2'00 assign $0\builder_converter_next_state[0:0] \builder_converter_state - attribute \src "ls180.v:4231.2-4264.9" + attribute \src "ls180.v:4100.2-4133.9" switch \builder_converter_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } - attribute \src "ls180.v:4234.4-4241.11" + attribute \src "ls180.v:4103.4-4110.11" switch \main_converter_counter attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -293033,23 +290055,23 @@ module \ls180 assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] case end - attribute \src "ls180.v:4242.4-4255.7" - switch $and$ls180.v:4242$680_Y - attribute \src "ls180.v:4242.8-4242.47" + attribute \src "ls180.v:4111.4-4124.7" + switch $and$ls180.v:4111$581_Y + attribute \src "ls180.v:4111.8-4111.47" case 1'1 - assign $0\main_converter_skip[0:0] $eq$ls180.v:4243$681_Y + assign $0\main_converter_skip[0:0] $eq$ls180.v:4112$582_Y assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we - assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4245$682_Y - assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4246$683_Y - attribute \src "ls180.v:4247.5-4254.8" - switch $or$ls180.v:4247$684_Y - attribute \src "ls180.v:4247.9-4247.53" + assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4114$583_Y + assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4115$584_Y + attribute \src "ls180.v:4116.5-4123.8" + switch $or$ls180.v:4116$585_Y + attribute \src "ls180.v:4116.9-4116.53" case 1'1 - assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4248$685_Y + assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4117$586_Y assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4250.6-4253.9" - switch $eq$ls180.v:4250$686_Y - attribute \src "ls180.v:4250.10-4250.42" + attribute \src "ls180.v:4119.6-4122.9" + switch $eq$ls180.v:4119$587_Y + attribute \src "ls180.v:4119.10-4119.42" case 1'1 assign $0\main_wb_sdram_ack[0:0] 1'1 assign $0\builder_converter_next_state[0:0] 1'0 @@ -293063,9 +290085,9 @@ module \ls180 case assign $0\main_converter_counter_converter_next_value[0:0] 1'0 assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4260.4-4262.7" - switch $and$ls180.v:4260$687_Y - attribute \src "ls180.v:4260.8-4260.47" + attribute \src "ls180.v:4129.4-4131.7" + switch $and$ls180.v:4129$588_Y + attribute \src "ls180.v:4129.8-4129.47" case 1'1 assign $0\builder_converter_next_state[0:0] 1'1 case @@ -293083,53 +290105,45 @@ module \ls180 update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] end - attribute \src "ls180.v:422.11-422.45" - process $proc$ls180.v:422$3231 + attribute \src "ls180.v:409.11-409.46" + process $proc$ls180.v:409$3001 assign { } { } - assign $1\main_sdram_baddress_storage[1:0] 2'00 - sync always - sync init - update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] - end - attribute \src "ls180.v:423.5-423.34" - process $proc$ls180.v:423$3232 - assign { } { } - assign $1\main_sdram_baddress_re[0:0] 1'0 + assign $1\main_sdram_sequencer_counter[3:0] 4'0000 sync always sync init - update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] end - attribute \src "ls180.v:424.12-424.45" - process $proc$ls180.v:424$3233 + attribute \src "ls180.v:410.5-410.38" + process $proc$ls180.v:410$3002 assign { } { } - assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + assign $1\main_sdram_sequencer_count[0:0] 1'0 sync always sync init - update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] end - attribute \src "ls180.v:425.5-425.32" - process $proc$ls180.v:425$3234 + attribute \src "ls180.v:416.5-416.51" + process $proc$ls180.v:416$3003 assign { } { } - assign $1\main_sdram_wrdata_re[0:0] 1'0 + assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 sync always sync init - update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] end - attribute \src "ls180.v:426.12-426.37" - process $proc$ls180.v:426$3235 + attribute \src "ls180.v:417.5-417.51" + process $proc$ls180.v:417$3004 assign { } { } - assign $1\main_sdram_status[15:0] 16'0000000000000000 + assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 sync always sync init - update \main_sdram_status $1\main_sdram_status[15:0] + update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] end - attribute \src "ls180.v:4310.1-4315.4" - process $proc$ls180.v:4310$719 + attribute \src "ls180.v:4179.1-4184.4" + process $proc$ls180.v:4179$620 assign { } { } assign $0\main_uart_tx_clear[0:0] 1'0 - attribute \src "ls180.v:4312.2-4314.5" - switch $and$ls180.v:4312$720_Y - attribute \src "ls180.v:4312.6-4312.79" + attribute \src "ls180.v:4181.2-4183.5" + switch $and$ls180.v:4181$621_Y + attribute \src "ls180.v:4181.6-4181.79" case 1'1 assign $0\main_uart_tx_clear[0:0] 1'1 case @@ -293137,8 +290151,8 @@ module \ls180 sync always update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] end - attribute \src "ls180.v:4316.1-4320.4" - process $proc$ls180.v:4316$721 + attribute \src "ls180.v:4185.1-4189.4" + process $proc$ls180.v:4185$622 assign { } { } assign { } { } assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status @@ -293146,13 +290160,21 @@ module \ls180 sync always update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] end - attribute \src "ls180.v:4321.1-4326.4" - process $proc$ls180.v:4321$722 + attribute \src "ls180.v:419.5-419.47" + process $proc$ls180.v:419$3005 + assign { } { } + assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] + end + attribute \src "ls180.v:4190.1-4195.4" + process $proc$ls180.v:4190$623 assign { } { } assign $0\main_uart_rx_clear[0:0] 1'0 - attribute \src "ls180.v:4323.2-4325.5" - switch $and$ls180.v:4323$723_Y - attribute \src "ls180.v:4323.6-4323.79" + attribute \src "ls180.v:4192.2-4194.5" + switch $and$ls180.v:4192$624_Y + attribute \src "ls180.v:4192.6-4192.79" case 1'1 assign $0\main_uart_rx_clear[0:0] 1'1 case @@ -293160,8 +290182,8 @@ module \ls180 sync always update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] end - attribute \src "ls180.v:4327.1-4331.4" - process $proc$ls180.v:4327$724 + attribute \src "ls180.v:4196.1-4200.4" + process $proc$ls180.v:4196$625 assign { } { } assign { } { } assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending @@ -293169,40 +290191,88 @@ module \ls180 sync always update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] end - attribute \src "ls180.v:4349.1-4356.4" - process $proc$ls180.v:4349$732 + attribute \src "ls180.v:420.5-420.45" + process $proc$ls180.v:420$3006 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] + end + attribute \src "ls180.v:421.5-421.45" + process $proc$ls180.v:421$3007 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:4218.1-4225.4" + process $proc$ls180.v:4218$633 assign { } { } assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4351.2-4355.5" + attribute \src "ls180.v:4220.2-4224.5" switch \main_uart_tx_fifo_replace - attribute \src "ls180.v:4351.6-4351.31" + attribute \src "ls180.v:4220.6-4220.31" case 1'1 - assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4352$733_Y - attribute \src "ls180.v:4353.6-4353.10" + assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4221$634_Y + attribute \src "ls180.v:4222.6-4222.10" case assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce end sync always update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:4379.1-4386.4" - process $proc$ls180.v:4379$743 + attribute \src "ls180.v:422.12-422.57" + process $proc$ls180.v:422$3008 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:424.5-424.51" + process $proc$ls180.v:424$3009 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:4248.1-4255.4" + process $proc$ls180.v:4248$644 assign { } { } assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4381.2-4385.5" + attribute \src "ls180.v:4250.2-4254.5" switch \main_uart_rx_fifo_replace - attribute \src "ls180.v:4381.6-4381.31" + attribute \src "ls180.v:4250.6-4250.31" case 1'1 - assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4382$744_Y - attribute \src "ls180.v:4383.6-4383.10" + assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4251$645_Y + attribute \src "ls180.v:4252.6-4252.10" case assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce end sync always update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:4399.1-4403.4" - process $proc$ls180.v:4399$750 + attribute \src "ls180.v:425.5-425.51" + process $proc$ls180.v:425$3010 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:426.5-426.50" + process $proc$ls180.v:426$3011 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + end + attribute \src "ls180.v:4268.1-4272.4" + process $proc$ls180.v:4268$651 assign { } { } assign { } { } assign { } { } @@ -293210,8 +290280,16 @@ module \ls180 sync always update \gpio_o $0\gpio_o[15:0] end - attribute \src "ls180.v:4404.1-4408.4" - process $proc$ls180.v:4404$751 + attribute \src "ls180.v:427.5-427.54" + process $proc$ls180.v:427$3012 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:4273.1-4277.4" + process $proc$ls180.v:4273$652 assign { } { } assign { } { } assign { } { } @@ -293219,9 +290297,16 @@ module \ls180 sync always update \gpio_oe $0\gpio_oe[15:0] end - attribute \src "ls180.v:4420.1-4468.4" - process $proc$ls180.v:4420$756 + attribute \src "ls180.v:428.5-428.55" + process $proc$ls180.v:428$3013 assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:4289.1-4337.4" + process $proc$ls180.v:4289$657 assign { } { } assign { } { } assign { } { } @@ -293239,16 +290324,17 @@ module \ls180 assign $0\main_spimaster2_done[0:0] 1'0 assign $0\main_spimaster29_miso_latch[0:0] 1'0 assign $0\main_spimaster3_irq[0:0] 1'0 + assign { } { } assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state - attribute \src "ls180.v:4431.2-4467.9" + attribute \src "ls180.v:4300.2-4336.9" switch \builder_spimaster0_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4435.4-4438.7" + attribute \src "ls180.v:4304.4-4307.7" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4435.8-4435.33" + attribute \src "ls180.v:4304.8-4304.33" case 1'1 assign $0\main_spimaster26_cs_enable[0:0] 1'1 assign $0\builder_spimaster0_next_state[1:0] 2'10 @@ -293258,15 +290344,15 @@ module \ls180 case 2'10 assign $0\main_spimaster25_clk_enable[0:0] 1'1 assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4443.4-4449.7" + attribute \src "ls180.v:4312.4-4318.7" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4443.8-4443.33" + attribute \src "ls180.v:4312.8-4312.33" case 1'1 - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4444$757_Y + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4313$658_Y assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4446.5-4448.8" - switch $eq$ls180.v:4446$759_Y - attribute \src "ls180.v:4446.9-4446.68" + attribute \src "ls180.v:4315.5-4317.8" + switch $eq$ls180.v:4315$660_Y + attribute \src "ls180.v:4315.9-4315.68" case 1'1 assign $0\builder_spimaster0_next_state[1:0] 2'11 case @@ -293276,9 +290362,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'11 assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4453.4-4457.7" + attribute \src "ls180.v:4322.4-4326.7" switch \main_spimaster31_clk_rise - attribute \src "ls180.v:4453.8-4453.33" + attribute \src "ls180.v:4322.8-4322.33" case 1'1 assign $0\main_spimaster29_miso_latch[0:0] 1'1 assign $0\main_spimaster3_irq[0:0] 1'1 @@ -293288,9 +290374,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case assign $0\main_spimaster2_done[0:0] 1'1 - attribute \src "ls180.v:4461.4-4465.7" + attribute \src "ls180.v:4330.4-4334.7" switch \main_spimaster0_start - attribute \src "ls180.v:4461.8-4461.29" + attribute \src "ls180.v:4330.8-4330.29" case 1'1 assign $0\main_spimaster2_done[0:0] 1'0 assign $0\main_spimaster28_mosi_latch[0:0] 1'1 @@ -293309,8 +290395,40 @@ module \ls180 update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0] update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] end - attribute \src "ls180.v:4479.1-4527.4" - process $proc$ls180.v:4479$764 + attribute \src "ls180.v:429.5-429.56" + process $proc$ls180.v:429$3014 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:430.5-430.50" + process $proc$ls180.v:430$3015 + assign { } { } + assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:433.5-433.67" + process $proc$ls180.v:433$3016 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:434.5-434.66" + process $proc$ls180.v:434$3017 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:4348.1-4396.4" + process $proc$ls180.v:4348$665 assign { } { } assign { } { } assign { } { } @@ -293320,7 +290438,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 assign $0\main_spisdcard_clk_enable[0:0] 1'0 assign $0\main_spisdcard_cs_enable[0:0] 1'0 assign $0\main_spisdcard_mosi_latch[0:0] 1'0 @@ -293329,16 +290446,17 @@ module \ls180 assign $0\main_spisdcard_irq[0:0] 1'0 assign { } { } assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state - attribute \src "ls180.v:4490.2-4526.9" + attribute \src "ls180.v:4359.2-4395.9" switch \builder_spimaster1_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4494.4-4497.7" + attribute \src "ls180.v:4363.4-4366.7" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4494.8-4494.31" + attribute \src "ls180.v:4363.8-4363.31" case 1'1 assign $0\main_spisdcard_cs_enable[0:0] 1'1 assign $0\builder_spimaster1_next_state[1:0] 2'10 @@ -293348,15 +290466,15 @@ module \ls180 case 2'10 assign $0\main_spisdcard_clk_enable[0:0] 1'1 assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4502.4-4508.7" + attribute \src "ls180.v:4371.4-4377.7" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4502.8-4502.31" + attribute \src "ls180.v:4371.8-4371.31" case 1'1 - assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4503$765_Y + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4372$666_Y assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4505.5-4507.8" - switch $eq$ls180.v:4505$767_Y - attribute \src "ls180.v:4505.9-4505.66" + attribute \src "ls180.v:4374.5-4376.8" + switch $eq$ls180.v:4374$668_Y + attribute \src "ls180.v:4374.9-4374.66" case 1'1 assign $0\builder_spimaster1_next_state[1:0] 2'11 case @@ -293366,9 +290484,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 2'11 assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4512.4-4516.7" + attribute \src "ls180.v:4381.4-4385.7" switch \main_spisdcard_clk_rise - attribute \src "ls180.v:4512.8-4512.31" + attribute \src "ls180.v:4381.8-4381.31" case 1'1 assign $0\main_spisdcard_miso_latch[0:0] 1'1 assign $0\main_spisdcard_irq[0:0] 1'1 @@ -293378,9 +290496,9 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case assign $0\main_spisdcard_done0[0:0] 1'1 - attribute \src "ls180.v:4520.4-4524.7" + attribute \src "ls180.v:4389.4-4393.7" switch \main_spisdcard_start0 - attribute \src "ls180.v:4520.8-4520.29" + attribute \src "ls180.v:4389.8-4389.29" case 1'1 assign $0\main_spisdcard_done0[0:0] 1'0 assign $0\main_spisdcard_mosi_latch[0:0] 1'1 @@ -293399,11 +290517,11 @@ module \ls180 update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0] update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] end - attribute \src "ls180.v:4559.1-4587.4" - process $proc$ls180.v:4559$789 + attribute \src "ls180.v:4428.1-4456.4" + process $proc$ls180.v:4428$690 assign { } { } assign $0\main_sdphy_clocker_clk1[0:0] 1'0 - attribute \src "ls180.v:4561.2-4586.9" + attribute \src "ls180.v:4430.2-4455.9" switch \main_sdphy_clocker_storage attribute \src "ls180.v:0.0-0.0" case 9'000000100 @@ -293433,24 +290551,9 @@ module \ls180 sync always update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] end - attribute \src "ls180.v:456.12-456.46" - process $proc$ls180.v:456$3236 - assign { } { } - assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] - end - attribute \src "ls180.v:457.11-457.47" - process $proc$ls180.v:457$3237 + attribute \src "ls180.v:4458.1-4491.4" + process $proc$ls180.v:4458$693 assign { } { } - assign $1\main_sdram_interface_wdata_we[1:0] 2'00 - sync always - sync init - update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] - end - attribute \src "ls180.v:4589.1-4622.4" - process $proc$ls180.v:4589$792 assign { } { } assign { } { } assign { } { } @@ -293458,17 +290561,16 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign { } { } - assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 assign { } { } assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:4599.2-4621.9" + attribute \src "ls180.v:4468.2-4490.9" switch \builder_sdphy_sdphyinit_state attribute \src "ls180.v:0.0-0.0" case 1'1 @@ -293477,15 +290579,15 @@ module \ls180 assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4606.4-4612.7" + attribute \src "ls180.v:4475.4-4481.7" switch \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:4606.8-4606.38" + attribute \src "ls180.v:4475.8-4475.38" case 1'1 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4607$793_Y + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4476$694_Y assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4609.5-4611.8" - switch $eq$ls180.v:4609$794_Y - attribute \src "ls180.v:4609.9-4609.41" + attribute \src "ls180.v:4478.5-4480.8" + switch $eq$ls180.v:4478$695_Y + attribute \src "ls180.v:4478.9-4478.41" case 1'1 assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 case @@ -293496,9 +290598,9 @@ module \ls180 case assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4617.4-4619.7" + attribute \src "ls180.v:4486.4-4488.7" switch \main_sdphy_init_initialize_re - attribute \src "ls180.v:4617.8-4617.37" + attribute \src "ls180.v:4486.8-4486.37" case 1'1 assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 case @@ -293514,40 +290616,16 @@ module \ls180 update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] end - attribute \src "ls180.v:459.12-459.45" - process $proc$ls180.v:459$3238 - assign { } { } - assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] - end - attribute \src "ls180.v:460.11-460.40" - process $proc$ls180.v:460$3239 - assign { } { } - assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] - end - attribute \src "ls180.v:461.5-461.35" - process $proc$ls180.v:461$3240 - assign { } { } - assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] - end - attribute \src "ls180.v:462.5-462.34" - process $proc$ls180.v:462$3241 + attribute \src "ls180.v:449.11-449.68" + process $proc$ls180.v:449$3018 assign { } { } - assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init - update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:4623.1-4699.4" - process $proc$ls180.v:4623$795 + attribute \src "ls180.v:4492.1-4568.4" + process $proc$ls180.v:4492$696 assign { } { } assign { } { } assign { } { } @@ -293556,7 +290634,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 assign { } { } assign $0\main_sdphy_cmdw_done[0:0] 1'0 assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 @@ -293564,14 +290641,15 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:4633.2-4698.9" + attribute \src "ls180.v:4502.2-4567.9" switch \builder_sdphy_sdphycmdw_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - attribute \src "ls180.v:4637.4-4662.11" + attribute \src "ls180.v:4506.4-4531.11" switch \main_sdphy_cmdw_count attribute \src "ls180.v:0.0-0.0" case 8'00000000 @@ -293599,22 +290677,22 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] case end - attribute \src "ls180.v:4663.4-4674.7" + attribute \src "ls180.v:4532.4-4543.7" switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4663.8-4663.38" + attribute \src "ls180.v:4532.8-4532.38" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4664$796_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4533$697_Y assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4666.5-4673.8" - switch $eq$ls180.v:4666$797_Y - attribute \src "ls180.v:4666.9-4666.40" + attribute \src "ls180.v:4535.5-4542.8" + switch $eq$ls180.v:4535$698_Y + attribute \src "ls180.v:4535.9-4535.40" case 1'1 - attribute \src "ls180.v:4667.6-4672.9" + attribute \src "ls180.v:4536.6-4541.9" switch \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:4667.10-4667.35" + attribute \src "ls180.v:4536.10-4536.35" case 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 - attribute \src "ls180.v:4669.10-4669.14" + attribute \src "ls180.v:4538.10-4538.14" case assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 @@ -293628,15 +290706,15 @@ module \ls180 assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4680.4-4687.7" + attribute \src "ls180.v:4549.4-4556.7" switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4680.8-4680.38" + attribute \src "ls180.v:4549.8-4549.38" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4681$798_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4550$699_Y assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4683.5-4686.8" - switch $eq$ls180.v:4683$799_Y - attribute \src "ls180.v:4683.9-4683.40" + attribute \src "ls180.v:4552.5-4555.8" + switch $eq$ls180.v:4552$700_Y + attribute \src "ls180.v:4552.9-4552.40" case 1'1 assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 @@ -293648,12 +290726,12 @@ module \ls180 case assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4692.4-4696.7" - switch $and$ls180.v:4692$800_Y - attribute \src "ls180.v:4692.8-4692.69" + attribute \src "ls180.v:4561.4-4565.7" + switch $and$ls180.v:4561$701_Y + attribute \src "ls180.v:4561.8-4561.69" case 1'1 assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 - attribute \src "ls180.v:4694.8-4694.12" + attribute \src "ls180.v:4563.8-4563.12" case assign $0\main_sdphy_cmdw_done[0:0] 1'1 end @@ -293668,48 +290746,40 @@ module \ls180 update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] end - attribute \src "ls180.v:463.5-463.35" - process $proc$ls180.v:463$3242 + attribute \src "ls180.v:450.5-450.64" + process $proc$ls180.v:450$3019 assign { } { } - assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] - end - attribute \src "ls180.v:464.5-464.34" - process $proc$ls180.v:464$3243 - assign { } { } - assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] sync init - update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] end - attribute \src "ls180.v:468.5-468.35" - process $proc$ls180.v:468$3244 + attribute \src "ls180.v:451.11-451.70" + process $proc$ls180.v:451$3020 assign { } { } - assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 sync always - update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:470.5-470.39" - process $proc$ls180.v:470$3245 + attribute \src "ls180.v:452.11-452.70" + process $proc$ls180.v:452$3021 assign { } { } - assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init - update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:472.5-472.39" - process $proc$ls180.v:472$3246 + attribute \src "ls180.v:453.11-453.73" + process $proc$ls180.v:453$3022 assign { } { } - assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init - update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:4733.1-4826.4" - process $proc$ls180.v:4733$809 + attribute \src "ls180.v:4602.1-4695.4" + process $proc$ls180.v:4602$710 assign { } { } assign { } { } assign { } { } @@ -293726,7 +290796,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 @@ -293742,26 +290811,27 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:4751.2-4825.9" + attribute \src "ls180.v:4620.2-4694.9" switch \builder_sdphy_sdphycmdr_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4759$810_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4628$711_Y assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4756.4-4758.7" + attribute \src "ls180.v:4625.4-4627.7" switch \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:4756.8-4756.49" + attribute \src "ls180.v:4625.8-4625.49" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 case end - attribute \src "ls180.v:4761.4-4764.7" - switch $eq$ls180.v:4761$811_Y - attribute \src "ls180.v:4761.8-4761.41" + attribute \src "ls180.v:4630.4-4633.7" + switch $eq$ls180.v:4630$712_Y + attribute \src "ls180.v:4630.8-4630.41" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 @@ -293772,30 +290842,30 @@ module \ls180 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4770$813_Y + assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4639$714_Y assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4787$816_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4656$717_Y assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4772.4-4786.7" - switch $and$ls180.v:4772$814_Y - attribute \src "ls180.v:4772.8-4772.69" + attribute \src "ls180.v:4641.4-4655.7" + switch $and$ls180.v:4641$715_Y + attribute \src "ls180.v:4641.8-4641.69" case 1'1 assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4774$815_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4643$716_Y assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4776.5-4785.8" + attribute \src "ls180.v:4645.5-4654.8" switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:4776.9-4776.36" + attribute \src "ls180.v:4645.9-4645.36" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4778.6-4784.9" + attribute \src "ls180.v:4647.6-4653.9" switch \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:4778.10-4778.35" + attribute \src "ls180.v:4647.10-4647.35" case 1'1 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 - attribute \src "ls180.v:4782.10-4782.14" + attribute \src "ls180.v:4651.10-4651.14" case assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 end @@ -293803,9 +290873,9 @@ module \ls180 end case end - attribute \src "ls180.v:4789.4-4792.7" - switch $eq$ls180.v:4789$817_Y - attribute \src "ls180.v:4789.8-4789.41" + attribute \src "ls180.v:4658.4-4661.7" + switch $eq$ls180.v:4658$718_Y + attribute \src "ls180.v:4658.8-4658.41" case 1'1 assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 @@ -293816,15 +290886,15 @@ module \ls180 assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4798.4-4804.7" + attribute \src "ls180.v:4667.4-4673.7" switch \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:4798.8-4798.38" + attribute \src "ls180.v:4667.8-4667.38" case 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4799$818_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4668$719_Y assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4801.5-4803.8" - switch $eq$ls180.v:4801$819_Y - attribute \src "ls180.v:4801.9-4801.40" + attribute \src "ls180.v:4670.5-4672.8" + switch $eq$ls180.v:4670$720_Y + attribute \src "ls180.v:4670.9-4670.40" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 case @@ -293836,9 +290906,9 @@ module \ls180 assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 - attribute \src "ls180.v:4810.4-4812.7" - switch $and$ls180.v:4810$820_Y - attribute \src "ls180.v:4810.8-4810.69" + attribute \src "ls180.v:4679.4-4681.7" + switch $and$ls180.v:4679$721_Y + attribute \src "ls180.v:4679.8-4679.69" case 1'1 assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 case @@ -293849,9 +290919,9 @@ module \ls180 assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4819.4-4823.7" - switch $and$ls180.v:4819$822_Y - attribute \src "ls180.v:4819.8-4819.94" + attribute \src "ls180.v:4688.4-4692.7" + switch $and$ls180.v:4688$723_Y + attribute \src "ls180.v:4688.8-4688.94" case 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 @@ -293877,122 +290947,42 @@ module \ls180 update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] end - attribute \src "ls180.v:475.5-475.32" - process $proc$ls180.v:475$3247 - assign { } { } - assign $1\main_sdram_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] - end - attribute \src "ls180.v:476.5-476.32" - process $proc$ls180.v:476$3248 - assign { } { } - assign $1\main_sdram_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] - end - attribute \src "ls180.v:477.5-477.31" - process $proc$ls180.v:477$3249 - assign { } { } - assign $1\main_sdram_cmd_last[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] - end - attribute \src "ls180.v:478.12-478.44" - process $proc$ls180.v:478$3250 - assign { } { } - assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] - end - attribute \src "ls180.v:479.11-479.43" - process $proc$ls180.v:479$3251 - assign { } { } - assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 - sync always - sync init - update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] - end - attribute \src "ls180.v:480.5-480.38" - process $proc$ls180.v:480$3252 - assign { } { } - assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:481.5-481.38" - process $proc$ls180.v:481$3253 - assign { } { } - assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:482.5-482.37" - process $proc$ls180.v:482$3254 - assign { } { } - assign $1\main_sdram_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] - end - attribute \src "ls180.v:483.5-483.42" - process $proc$ls180.v:483$3255 - assign { } { } - assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 - sync always - update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] - sync init - end - attribute \src "ls180.v:484.5-484.43" - process $proc$ls180.v:484$3256 - assign { } { } - assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 - sync always - update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] - sync init - end - attribute \src "ls180.v:4860.1-4887.4" - process $proc$ls180.v:4860$830 + attribute \src "ls180.v:4729.1-4756.4" + process $proc$ls180.v:4729$731 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_dataw_valid[0:0] 1'0 assign $0\main_sdphy_dataw_error[0:0] 1'0 assign { } { } + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:4868.2-4886.9" + attribute \src "ls180.v:4737.2-4755.9" switch \builder_sdphy_sdphycrcr_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 - attribute \src "ls180.v:4873.4-4877.7" + attribute \src "ls180.v:4742.4-4746.7" switch \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:4873.8-4873.50" + attribute \src "ls180.v:4742.8-4742.50" case 1'1 - assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4874$831_Y - assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4875$832_Y + assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4743$732_Y + assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4744$733_Y assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 case end attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:4880.4-4884.7" + attribute \src "ls180.v:4749.4-4753.7" switch \main_sdphy_dataw_start - attribute \src "ls180.v:4880.8-4880.30" + attribute \src "ls180.v:4749.8-4749.30" case 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 @@ -294008,8 +290998,16 @@ module \ls180 update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] end - attribute \src "ls180.v:4888.1-4960.4" - process $proc$ls180.v:4888$833 + attribute \src "ls180.v:474.5-474.59" + process $proc$ls180.v:474$3023 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:4757.1-4829.4" + process $proc$ls180.v:4757$734 assign { } { } assign { } { } assign { } { } @@ -294019,7 +291017,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 @@ -294028,27 +291025,28 @@ module \ls180 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 assign $0\main_sdphy_dataw_stop[0:0] 1'0 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state - attribute \src "ls180.v:4899.2-4959.9" + attribute \src "ls180.v:4768.2-4828.9" switch \builder_sdphy_fsm_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - attribute \src "ls180.v:4904.4-4906.7" + attribute \src "ls180.v:4773.4-4775.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4904.8-4904.39" + attribute \src "ls180.v:4773.8-4773.39" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 case end attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4909$834_Y + assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4778$735_Y assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - attribute \src "ls180.v:4912.4-4919.11" + attribute \src "ls180.v:4781.4-4788.11" switch \main_sdphy_dataw_count attribute \src "ls180.v:0.0-0.0" case 8'00000000 @@ -294058,24 +291056,24 @@ module \ls180 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] case end - attribute \src "ls180.v:4920.4-4932.7" + attribute \src "ls180.v:4789.4-4801.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4920.8-4920.39" + attribute \src "ls180.v:4789.8-4789.39" case 1'1 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4921$835_Y + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4790$736_Y assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4923.5-4931.8" - switch $eq$ls180.v:4923$836_Y - attribute \src "ls180.v:4923.9-4923.41" + attribute \src "ls180.v:4792.5-4800.8" + switch $eq$ls180.v:4792$737_Y + attribute \src "ls180.v:4792.9-4792.41" case 1'1 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4926.6-4930.9" + attribute \src "ls180.v:4795.6-4799.9" switch \main_sdphy_dataw_sink_last - attribute \src "ls180.v:4926.10-4926.36" + attribute \src "ls180.v:4795.10-4795.36" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:4928.10-4928.14" + attribute \src "ls180.v:4797.10-4797.14" case assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 end @@ -294088,9 +291086,9 @@ module \ls180 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4938.4-4941.7" + attribute \src "ls180.v:4807.4-4810.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4938.8-4938.39" + attribute \src "ls180.v:4807.8-4807.39" case 1'1 assign $0\main_sdphy_dataw_start[0:0] 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 @@ -294099,13 +291097,13 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'100 assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4945.4-4950.7" + attribute \src "ls180.v:4814.4-4819.7" switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4945.8-4945.39" + attribute \src "ls180.v:4814.8-4814.39" case 1'1 - attribute \src "ls180.v:4946.5-4949.8" + attribute \src "ls180.v:4815.5-4818.8" switch \main_sdphy_dataw_pads_in_payload_data_i [0] - attribute \src "ls180.v:4946.9-4946.51" + attribute \src "ls180.v:4815.9-4815.51" case 1'1 assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 @@ -294117,9 +291115,9 @@ module \ls180 case assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4955.4-4957.7" - switch $and$ls180.v:4955$837_Y - attribute \src "ls180.v:4955.8-4955.71" + attribute \src "ls180.v:4824.4-4826.7" + switch $and$ls180.v:4824$738_Y + attribute \src "ls180.v:4824.8-4824.71" case 1'1 assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 case @@ -294136,64 +291134,80 @@ module \ls180 update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:490.11-490.44" - process $proc$ls180.v:490$3257 + attribute \src "ls180.v:476.5-476.59" + process $proc$ls180.v:476$3024 assign { } { } - assign $1\main_sdram_timer_count1[9:0] 10'1100001101 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 sync always sync init - update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] + update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:492.5-492.38" - process $proc$ls180.v:492$3258 + attribute \src "ls180.v:477.5-477.58" + process $proc$ls180.v:477$3025 assign { } { } - assign $1\main_sdram_postponer_req_o[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 sync always sync init - update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:493.5-493.38" - process $proc$ls180.v:493$3259 + attribute \src "ls180.v:478.5-478.64" + process $proc$ls180.v:478$3026 assign { } { } - assign $1\main_sdram_postponer_count[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:494.5-494.39" - process $proc$ls180.v:494$3260 + attribute \src "ls180.v:479.12-479.74" + process $proc$ls180.v:479$3027 assign { } { } - assign $1\main_sdram_sequencer_start0[0:0] 1'0 + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init - update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:497.5-497.38" - process $proc$ls180.v:497$3261 + attribute \src "ls180.v:480.12-480.47" + process $proc$ls180.v:480$3028 assign { } { } - assign $1\main_sdram_sequencer_done1[0:0] 1'0 + assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 sync always sync init - update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] + update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] end - attribute \src "ls180.v:498.11-498.46" - process $proc$ls180.v:498$3262 + attribute \src "ls180.v:481.5-481.46" + process $proc$ls180.v:481$3029 assign { } { } - assign $1\main_sdram_sequencer_counter[3:0] 4'0000 + assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 sync always sync init - update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] + update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] end - attribute \src "ls180.v:499.5-499.38" - process $proc$ls180.v:499$3263 + attribute \src "ls180.v:483.5-483.44" + process $proc$ls180.v:483$3030 assign { } { } - assign $1\main_sdram_sequencer_count[0:0] 1'0 + assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 sync always sync init - update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] + update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] + end + attribute \src "ls180.v:484.5-484.45" + process $proc$ls180.v:484$3031 + assign { } { } + assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] + end + attribute \src "ls180.v:485.5-485.54" + process $proc$ls180.v:485$3032 + assign { } { } + assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:4994.1-5095.4" - process $proc$ls180.v:4994$845 + attribute \src "ls180.v:4863.1-4964.4" + process $proc$ls180.v:4863$746 assign { } { } assign { } { } assign { } { } @@ -294209,23 +291223,23 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 - assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_datar_stop[0:0] 1'0 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 assign { } { } + assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 assign $0\main_sdphy_datar_source_valid[0:0] 1'0 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 assign $0\main_sdphy_datar_source_last[0:0] 1'0 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:5011.2-5094.9" + attribute \src "ls180.v:4880.2-4963.9" switch \builder_sdphy_sdphydatar_state attribute \src "ls180.v:0.0-0.0" case 3'001 @@ -294234,18 +291248,18 @@ module \ls180 assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 assign { } { } assign { } { } - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:5021$847_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4890$748_Y assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:5018.4-5020.7" + attribute \src "ls180.v:4887.4-4889.7" switch \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:5018.8-5018.51" + attribute \src "ls180.v:4887.8-4887.51" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 case end - attribute \src "ls180.v:5023.4-5026.7" - switch $eq$ls180.v:5023$848_Y - attribute \src "ls180.v:5023.8-5023.42" + attribute \src "ls180.v:4892.4-4895.7" + switch $eq$ls180.v:4892$749_Y + attribute \src "ls180.v:4892.8-4892.42" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 @@ -294256,48 +291270,48 @@ module \ls180 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:5032$851_Y + assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4901$752_Y assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:5053$853_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4922$754_Y assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:5034.4-5052.7" + attribute \src "ls180.v:4903.4-4921.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5034.8-5034.37" + attribute \src "ls180.v:4903.8-4903.37" case 1'1 - attribute \src "ls180.v:5035.5-5051.8" + attribute \src "ls180.v:4904.5-4920.8" switch \main_sdphy_datar_source_ready - attribute \src "ls180.v:5035.9-5035.38" + attribute \src "ls180.v:4904.9-4904.38" case 1'1 assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:5037$852_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4906$753_Y assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5039.6-5048.9" + attribute \src "ls180.v:4908.6-4917.9" switch \main_sdphy_datar_source_last - attribute \src "ls180.v:5039.10-5039.38" + attribute \src "ls180.v:4908.10-4908.38" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - attribute \src "ls180.v:5041.7-5047.10" + attribute \src "ls180.v:4910.7-4916.10" switch \main_sdphy_datar_sink_last - attribute \src "ls180.v:5041.11-5041.37" + attribute \src "ls180.v:4910.11-4910.37" case 1'1 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 - attribute \src "ls180.v:5045.11-5045.15" + attribute \src "ls180.v:4914.11-4914.15" case assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 end case end - attribute \src "ls180.v:5049.9-5049.13" + attribute \src "ls180.v:4918.9-4918.13" case assign $0\main_sdphy_datar_stop[0:0] 1'1 end case end - attribute \src "ls180.v:5055.4-5058.7" - switch $eq$ls180.v:5055$854_Y - attribute \src "ls180.v:5055.8-5055.42" + attribute \src "ls180.v:4924.4-4927.7" + switch $eq$ls180.v:4924$755_Y + attribute \src "ls180.v:4924.8-4924.42" case 1'1 assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 @@ -294306,15 +291320,15 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'011 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:5062.4-5068.7" + attribute \src "ls180.v:4931.4-4937.7" switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:5062.8-5062.39" + attribute \src "ls180.v:4931.8-4931.39" case 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:5063$855_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4932$756_Y assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5065.5-5067.8" - switch $eq$ls180.v:5065$856_Y - attribute \src "ls180.v:5065.9-5065.42" + attribute \src "ls180.v:4934.5-4936.8" + switch $eq$ls180.v:4934$757_Y + attribute \src "ls180.v:4934.9-4934.42" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 case @@ -294326,9 +291340,9 @@ module \ls180 assign $0\main_sdphy_datar_source_valid[0:0] 1'1 assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 assign $0\main_sdphy_datar_source_last[0:0] 1'1 - attribute \src "ls180.v:5074.4-5076.7" - switch $and$ls180.v:5074$857_Y - attribute \src "ls180.v:5074.8-5074.71" + attribute \src "ls180.v:4943.4-4945.7" + switch $and$ls180.v:4943$758_Y + attribute \src "ls180.v:4943.8-4943.71" case 1'1 assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 case @@ -294337,14 +291351,14 @@ module \ls180 case assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5081.4-5092.7" - switch $and$ls180.v:5081$858_Y - attribute \src "ls180.v:5081.8-5081.71" + attribute \src "ls180.v:4950.4-4961.7" + switch $and$ls180.v:4950$759_Y + attribute \src "ls180.v:4950.8-4950.71" case 1'1 assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:5083.5-5091.8" + attribute \src "ls180.v:4952.5-4960.8" switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:5083.9-5083.40" + attribute \src "ls180.v:4952.9-4952.40" case 1'1 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 @@ -294375,192 +291389,192 @@ module \ls180 update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] end - attribute \src "ls180.v:505.5-505.51" - process $proc$ls180.v:505$3264 + attribute \src "ls180.v:487.32-487.76" + process $proc$ls180.v:487$3033 assign { } { } - assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - end - attribute \src "ls180.v:506.5-506.51" - process $proc$ls180.v:506$3265 - assign { } { } - assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] end - attribute \src "ls180.v:508.5-508.47" - process $proc$ls180.v:508$3266 + attribute \src "ls180.v:488.11-488.55" + process $proc$ls180.v:488$3034 assign { } { } - assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] + update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] end - attribute \src "ls180.v:509.5-509.45" - process $proc$ls180.v:509$3267 + attribute \src "ls180.v:490.32-490.75" + process $proc$ls180.v:490$3035 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 sync always + update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] sync init - update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] end - attribute \src "ls180.v:510.5-510.45" - process $proc$ls180.v:510$3268 + attribute \src "ls180.v:492.32-492.76" + process $proc$ls180.v:492$3036 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 sync always + update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] sync init - update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] end - attribute \src "ls180.v:511.12-511.57" - process $proc$ls180.v:511$3269 + attribute \src "ls180.v:498.5-498.51" + process $proc$ls180.v:498$3037 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] end - attribute \src "ls180.v:513.5-513.51" - process $proc$ls180.v:513$3270 + attribute \src "ls180.v:499.5-499.51" + process $proc$ls180.v:499$3038 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] end - attribute \src "ls180.v:514.5-514.51" - process $proc$ls180.v:514$3271 + attribute \src "ls180.v:501.5-501.47" + process $proc$ls180.v:501$3039 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] end - attribute \src "ls180.v:515.5-515.50" - process $proc$ls180.v:515$3272 + attribute \src "ls180.v:502.5-502.45" + process $proc$ls180.v:502$3040 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] end - attribute \src "ls180.v:5153.1-5160.4" - process $proc$ls180.v:5153$980 + attribute \src "ls180.v:5022.1-5029.4" + process $proc$ls180.v:5022$881 assign { } { } assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 - attribute \src "ls180.v:5155.2-5159.5" + attribute \src "ls180.v:5024.2-5028.5" switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:5155.6-5155.38" + attribute \src "ls180.v:5024.6-5024.38" case 1'1 assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:5157.6-5157.10" + attribute \src "ls180.v:5026.6-5026.10" case assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 end sync always update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] end - attribute \src "ls180.v:516.5-516.54" - process $proc$ls180.v:516$3273 + attribute \src "ls180.v:503.5-503.45" + process $proc$ls180.v:503$3041 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] end - attribute \src "ls180.v:517.5-517.55" - process $proc$ls180.v:517$3274 + attribute \src "ls180.v:504.12-504.57" + process $proc$ls180.v:504$3042 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:5175.1-5182.4" - process $proc$ls180.v:5175$1003 + attribute \src "ls180.v:5044.1-5051.4" + process $proc$ls180.v:5044$904 assign { } { } assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5177.2-5181.5" + attribute \src "ls180.v:5046.2-5050.5" switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:5177.6-5177.44" + attribute \src "ls180.v:5046.6-5046.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:5179.6-5179.10" + attribute \src "ls180.v:5048.6-5048.10" case assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] end - attribute \src "ls180.v:518.5-518.56" - process $proc$ls180.v:518$3275 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:5185.1-5192.4" - process $proc$ls180.v:5185$1014 + attribute \src "ls180.v:5054.1-5061.4" + process $proc$ls180.v:5054$915 assign { } { } assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5187.2-5191.5" + attribute \src "ls180.v:5056.2-5060.5" switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:5187.6-5187.44" + attribute \src "ls180.v:5056.6-5056.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:5189.6-5189.10" + attribute \src "ls180.v:5058.6-5058.10" case assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] end - attribute \src "ls180.v:519.5-519.50" - process $proc$ls180.v:519$3276 + attribute \src "ls180.v:506.5-506.51" + process $proc$ls180.v:506$3043 assign { } { } - assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] end - attribute \src "ls180.v:5195.1-5202.4" - process $proc$ls180.v:5195$1025 + attribute \src "ls180.v:5064.1-5071.4" + process $proc$ls180.v:5064$926 assign { } { } assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5197.2-5201.5" + attribute \src "ls180.v:5066.2-5070.5" switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:5197.6-5197.44" + attribute \src "ls180.v:5066.6-5066.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:5199.6-5199.10" + attribute \src "ls180.v:5068.6-5068.10" case assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] end - attribute \src "ls180.v:5205.1-5212.4" - process $proc$ls180.v:5205$1036 + attribute \src "ls180.v:507.5-507.51" + process $proc$ls180.v:507$3044 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:5074.1-5081.4" + process $proc$ls180.v:5074$937 assign { } { } assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5207.2-5211.5" + attribute \src "ls180.v:5076.2-5080.5" switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:5207.6-5207.44" + attribute \src "ls180.v:5076.6-5076.44" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:5209.6-5209.10" + attribute \src "ls180.v:5078.6-5078.10" case assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 end sync always update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] end - attribute \src "ls180.v:5213.1-5292.4" - process $proc$ls180.v:5213$1037 + attribute \src "ls180.v:508.5-508.50" + process $proc$ls180.v:508$3045 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + end + attribute \src "ls180.v:5082.1-5161.4" + process $proc$ls180.v:5082$938 assign { } { } assign { } { } assign { } { } @@ -294576,36 +291590,36 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 assign { } { } assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:5230.2-5291.9" + attribute \src "ls180.v:5099.2-5160.9" switch \builder_sdcore_crcupstreaminserter_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 - attribute \src "ls180.v:5234.4-5236.7" - switch $eq$ls180.v:5234$1038_Y - attribute \src "ls180.v:5234.8-5234.48" + attribute \src "ls180.v:5103.4-5105.7" + switch $eq$ls180.v:5103$939_Y + attribute \src "ls180.v:5103.8-5103.48" case 1'1 assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 case end - attribute \src "ls180.v:5237.4-5262.11" + attribute \src "ls180.v:5106.4-5131.11" switch \main_sdcore_crc16_inserter_cnt attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -294633,18 +291647,18 @@ module \ls180 assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } case end - attribute \src "ls180.v:5263.4-5270.7" + attribute \src "ls180.v:5132.4-5139.7" switch \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:5263.8-5263.47" + attribute \src "ls180.v:5132.8-5132.47" case 1'1 - attribute \src "ls180.v:5264.5-5269.8" - switch $eq$ls180.v:5264$1039_Y - attribute \src "ls180.v:5264.9-5264.49" + attribute \src "ls180.v:5133.5-5138.8" + switch $eq$ls180.v:5133$940_Y + attribute \src "ls180.v:5133.9-5133.49" case 1'1 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - attribute \src "ls180.v:5266.9-5266.13" + attribute \src "ls180.v:5135.9-5135.13" case - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5267$1040_Y + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5136$941_Y assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 end case @@ -294663,9 +291677,9 @@ module \ls180 assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5285.4-5289.7" - switch $and$ls180.v:5285$1042_Y - attribute \src "ls180.v:5285.8-5285.128" + attribute \src "ls180.v:5154.4-5158.7" + switch $and$ls180.v:5154$943_Y + attribute \src "ls180.v:5154.8-5154.128" case 1'1 assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 @@ -294690,29 +291704,61 @@ module \ls180 update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] end - attribute \src "ls180.v:522.5-522.67" - process $proc$ls180.v:522$3277 + attribute \src "ls180.v:509.5-509.54" + process $proc$ls180.v:509$3046 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] sync init + update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:523.5-523.66" - process $proc$ls180.v:523$3278 + attribute \src "ls180.v:510.5-510.55" + process $proc$ls180.v:510$3047 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + sync init + update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:511.5-511.56" + process $proc$ls180.v:511$3048 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:512.5-512.50" + process $proc$ls180.v:512$3049 + assign { } { } + assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:515.5-515.67" + process $proc$ls180.v:515$3050 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:516.5-516.66" + process $proc$ls180.v:516$3051 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] sync init end - attribute \src "ls180.v:5293.1-5298.4" - process $proc$ls180.v:5293$1043 + attribute \src "ls180.v:5162.1-5167.4" + process $proc$ls180.v:5162$944 assign { } { } assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 - attribute \src "ls180.v:5295.2-5297.5" - switch $and$ls180.v:5295$1050_Y - attribute \src "ls180.v:5295.6-5295.301" + attribute \src "ls180.v:5164.2-5166.5" + switch $and$ls180.v:5164$951_Y + attribute \src "ls180.v:5164.6-5164.301" case 1'1 assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 case @@ -294720,77 +291766,77 @@ module \ls180 sync always update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] end - attribute \src "ls180.v:5301.1-5308.4" - process $proc$ls180.v:5301$1052 + attribute \src "ls180.v:5170.1-5177.4" + process $proc$ls180.v:5170$953 assign { } { } assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - attribute \src "ls180.v:5303.2-5307.5" - switch $eq$ls180.v:5303$1053_Y - attribute \src "ls180.v:5303.6-5303.45" + attribute \src "ls180.v:5172.2-5176.5" + switch $eq$ls180.v:5172$954_Y + attribute \src "ls180.v:5172.6-5172.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 - attribute \src "ls180.v:5305.6-5305.10" + attribute \src "ls180.v:5174.6-5174.10" case assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] end - attribute \src "ls180.v:5311.1-5318.4" - process $proc$ls180.v:5311$1055 + attribute \src "ls180.v:5180.1-5187.4" + process $proc$ls180.v:5180$956 assign { } { } assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - attribute \src "ls180.v:5313.2-5317.5" - switch $eq$ls180.v:5313$1056_Y - attribute \src "ls180.v:5313.6-5313.45" + attribute \src "ls180.v:5182.2-5186.5" + switch $eq$ls180.v:5182$957_Y + attribute \src "ls180.v:5182.6-5182.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 - attribute \src "ls180.v:5315.6-5315.10" + attribute \src "ls180.v:5184.6-5184.10" case assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] end - attribute \src "ls180.v:5321.1-5328.4" - process $proc$ls180.v:5321$1058 + attribute \src "ls180.v:5190.1-5197.4" + process $proc$ls180.v:5190$959 assign { } { } assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - attribute \src "ls180.v:5323.2-5327.5" - switch $eq$ls180.v:5323$1059_Y - attribute \src "ls180.v:5323.6-5323.45" + attribute \src "ls180.v:5192.2-5196.5" + switch $eq$ls180.v:5192$960_Y + attribute \src "ls180.v:5192.6-5192.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 - attribute \src "ls180.v:5325.6-5325.10" + attribute \src "ls180.v:5194.6-5194.10" case assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] end - attribute \src "ls180.v:5331.1-5338.4" - process $proc$ls180.v:5331$1061 + attribute \src "ls180.v:5200.1-5207.4" + process $proc$ls180.v:5200$962 assign { } { } assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - attribute \src "ls180.v:5333.2-5337.5" - switch $eq$ls180.v:5333$1062_Y - attribute \src "ls180.v:5333.6-5333.45" + attribute \src "ls180.v:5202.2-5206.5" + switch $eq$ls180.v:5202$963_Y + attribute \src "ls180.v:5202.6-5202.45" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 - attribute \src "ls180.v:5335.6-5335.10" + attribute \src "ls180.v:5204.6-5204.10" case assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 end sync always update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] end - attribute \src "ls180.v:5340.1-5345.4" - process $proc$ls180.v:5340$1063 + attribute \src "ls180.v:5209.1-5214.4" + process $proc$ls180.v:5209$964 assign { } { } assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 - attribute \src "ls180.v:5342.2-5344.5" - switch $and$ls180.v:5342$1065_Y - attribute \src "ls180.v:5342.6-5342.85" + attribute \src "ls180.v:5211.2-5213.5" + switch $and$ls180.v:5211$966_Y + attribute \src "ls180.v:5211.6-5211.85" case 1'1 assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 case @@ -294798,104 +291844,88 @@ module \ls180 sync always update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] end - attribute \src "ls180.v:5346.1-5353.4" - process $proc$ls180.v:5346$1066 + attribute \src "ls180.v:5215.1-5222.4" + process $proc$ls180.v:5215$967 assign { } { } assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 - attribute \src "ls180.v:5348.2-5352.5" - switch $lt$ls180.v:5348$1067_Y - attribute \src "ls180.v:5348.6-5348.44" + attribute \src "ls180.v:5217.2-5221.5" + switch $lt$ls180.v:5217$968_Y + attribute \src "ls180.v:5217.6-5217.44" case 1'1 assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 - attribute \src "ls180.v:5350.6-5350.10" + attribute \src "ls180.v:5219.6-5219.10" case assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready end sync always update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] end - attribute \src "ls180.v:5357.1-5364.4" - process $proc$ls180.v:5357$1078 + attribute \src "ls180.v:5226.1-5233.4" + process $proc$ls180.v:5226$979 assign { } { } assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5359.2-5363.5" + attribute \src "ls180.v:5228.2-5232.5" switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:5359.6-5359.43" + attribute \src "ls180.v:5228.6-5228.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:5361.6-5361.10" + attribute \src "ls180.v:5230.6-5230.10" case assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 end sync always update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] end - attribute \src "ls180.v:5367.1-5374.4" - process $proc$ls180.v:5367$1089 + attribute \src "ls180.v:5236.1-5243.4" + process $proc$ls180.v:5236$990 assign { } { } assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5369.2-5373.5" + attribute \src "ls180.v:5238.2-5242.5" switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:5369.6-5369.43" + attribute \src "ls180.v:5238.6-5238.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:5371.6-5371.10" + attribute \src "ls180.v:5240.6-5240.10" case assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 end sync always update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] end - attribute \src "ls180.v:5377.1-5384.4" - process $proc$ls180.v:5377$1100 + attribute \src "ls180.v:5246.1-5253.4" + process $proc$ls180.v:5246$1001 assign { } { } assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5379.2-5383.5" + attribute \src "ls180.v:5248.2-5252.5" switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:5379.6-5379.43" + attribute \src "ls180.v:5248.6-5248.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:5381.6-5381.10" + attribute \src "ls180.v:5250.6-5250.10" case assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 end sync always update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] end - attribute \src "ls180.v:538.11-538.68" - process $proc$ls180.v:538$3279 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:5387.1-5394.4" - process $proc$ls180.v:5387$1111 + attribute \src "ls180.v:5256.1-5263.4" + process $proc$ls180.v:5256$1012 assign { } { } assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5389.2-5393.5" + attribute \src "ls180.v:5258.2-5262.5" switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:5389.6-5389.43" + attribute \src "ls180.v:5258.6-5258.43" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:5391.6-5391.10" + attribute \src "ls180.v:5260.6-5260.10" case assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 end sync always update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] end - attribute \src "ls180.v:539.5-539.64" - process $proc$ls180.v:539$3280 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:5395.1-5585.4" - process $proc$ls180.v:5395$1112 + attribute \src "ls180.v:5264.1-5454.4" + process $proc$ls180.v:5264$1013 assign { } { } assign { } { } assign { } { } @@ -294935,18 +291965,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 - assign { } { } - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 @@ -294974,13 +291992,25 @@ module \ls180 assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 assign $0\main_sdphy_datar_source_ready[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + assign { } { } + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state - attribute \src "ls180.v:5436.2-5584.9" + attribute \src "ls180.v:5305.2-5453.9" switch \builder_sdcore_fsm_state attribute \src "ls180.v:0.0-0.0" case 3'001 assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 - attribute \src "ls180.v:5439.4-5459.11" + attribute \src "ls180.v:5308.4-5328.11" switch \main_sdcore_cmd_count attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -295000,27 +292030,27 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'101 assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } - assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5457$1113_Y + assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5326$1014_Y case end - attribute \src "ls180.v:5460.4-5472.7" - switch $and$ls180.v:5460$1114_Y - attribute \src "ls180.v:5460.8-5460.65" + attribute \src "ls180.v:5329.4-5341.7" + switch $and$ls180.v:5329$1015_Y + attribute \src "ls180.v:5329.8-5329.65" case 1'1 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5461$1115_Y + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5330$1016_Y assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - attribute \src "ls180.v:5463.5-5471.8" - switch $eq$ls180.v:5463$1116_Y - attribute \src "ls180.v:5463.9-5463.40" + attribute \src "ls180.v:5332.5-5340.8" + switch $eq$ls180.v:5332$1017_Y + attribute \src "ls180.v:5332.9-5332.40" case 1'1 - attribute \src "ls180.v:5464.6-5470.9" - switch $eq$ls180.v:5464$1117_Y - attribute \src "ls180.v:5464.10-5464.40" + attribute \src "ls180.v:5333.6-5339.9" + switch $eq$ls180.v:5333$1018_Y + attribute \src "ls180.v:5333.10-5333.40" case 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5468.10-5468.14" + attribute \src "ls180.v:5337.10-5337.14" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 end @@ -295031,52 +292061,52 @@ module \ls180 attribute \src "ls180.v:0.0-0.0" case 3'010 assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 - assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5476$1118_Y + assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5345$1019_Y assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 - attribute \src "ls180.v:5477.4-5481.7" - switch $eq$ls180.v:5477$1119_Y - attribute \src "ls180.v:5477.8-5477.38" + attribute \src "ls180.v:5346.4-5350.7" + switch $eq$ls180.v:5346$1020_Y + attribute \src "ls180.v:5346.8-5346.38" case 1'1 assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 - attribute \src "ls180.v:5479.8-5479.12" + attribute \src "ls180.v:5348.8-5348.12" case assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 end - attribute \src "ls180.v:5483.4-5504.7" + attribute \src "ls180.v:5352.4-5373.7" switch \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:5483.8-5483.36" + attribute \src "ls180.v:5352.8-5352.36" case 1'1 - attribute \src "ls180.v:5484.5-5503.8" - switch $eq$ls180.v:5484$1120_Y - attribute \src "ls180.v:5484.9-5484.56" + attribute \src "ls180.v:5353.5-5372.8" + switch $eq$ls180.v:5353$1021_Y + attribute \src "ls180.v:5353.9-5353.56" case 1'1 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5488.9-5488.13" + attribute \src "ls180.v:5357.9-5357.13" case - attribute \src "ls180.v:5489.6-5502.9" + attribute \src "ls180.v:5358.6-5371.9" switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:5489.10-5489.37" + attribute \src "ls180.v:5358.10-5358.37" case 1'1 - attribute \src "ls180.v:5490.7-5498.10" - switch $eq$ls180.v:5490$1121_Y - attribute \src "ls180.v:5490.11-5490.42" + attribute \src "ls180.v:5359.7-5367.10" + switch $eq$ls180.v:5359$1022_Y + attribute \src "ls180.v:5359.11-5359.42" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:5492.11-5492.15" + attribute \src "ls180.v:5361.11-5361.15" case - attribute \src "ls180.v:5493.8-5497.11" - switch $eq$ls180.v:5493$1122_Y - attribute \src "ls180.v:5493.12-5493.43" + attribute \src "ls180.v:5362.8-5366.11" + switch $eq$ls180.v:5362$1023_Y + attribute \src "ls180.v:5362.12-5362.43" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - attribute \src "ls180.v:5495.12-5495.16" + attribute \src "ls180.v:5364.12-5364.16" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 end end - attribute \src "ls180.v:5499.10-5499.14" + attribute \src "ls180.v:5368.10-5368.14" case assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 @@ -295092,28 +292122,28 @@ module \ls180 assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data assign $0\main_sdphy_datar_source_ready[0:0] 1'1 - attribute \src "ls180.v:5512.4-5518.7" - switch $and$ls180.v:5512$1124_Y - attribute \src "ls180.v:5512.8-5512.98" + attribute \src "ls180.v:5381.4-5387.7" + switch $and$ls180.v:5381$1025_Y + attribute \src "ls180.v:5381.8-5381.98" case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5513$1125_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5382$1026_Y assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5515.5-5517.8" - switch $eq$ls180.v:5515$1127_Y - attribute \src "ls180.v:5515.9-5515.77" + attribute \src "ls180.v:5384.5-5386.8" + switch $eq$ls180.v:5384$1028_Y + attribute \src "ls180.v:5384.9-5384.77" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 case end case end - attribute \src "ls180.v:5520.4-5525.7" + attribute \src "ls180.v:5389.4-5394.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5520.8-5520.37" + attribute \src "ls180.v:5389.8-5389.37" case 1'1 - attribute \src "ls180.v:5521.5-5524.8" - switch $ne$ls180.v:5521$1128_Y - attribute \src "ls180.v:5521.9-5521.57" + attribute \src "ls180.v:5390.5-5393.8" + switch $ne$ls180.v:5390$1029_Y + attribute \src "ls180.v:5390.9-5390.57" case 1'1 assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 @@ -295125,42 +292155,42 @@ module \ls180 case 3'100 assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage - assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5530$1130_Y - attribute \src "ls180.v:5531.4-5557.7" + assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5399$1031_Y + attribute \src "ls180.v:5400.4-5426.7" switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5531.8-5531.37" + attribute \src "ls180.v:5400.8-5400.37" case 1'1 - attribute \src "ls180.v:5532.5-5556.8" - switch $eq$ls180.v:5532$1131_Y - attribute \src "ls180.v:5532.9-5532.57" + attribute \src "ls180.v:5401.5-5425.8" + switch $eq$ls180.v:5401$1032_Y + attribute \src "ls180.v:5401.9-5401.57" case 1'1 assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:5538.6-5546.9" - switch $and$ls180.v:5538$1132_Y - attribute \src "ls180.v:5538.10-5538.72" + attribute \src "ls180.v:5407.6-5415.9" + switch $and$ls180.v:5407$1033_Y + attribute \src "ls180.v:5407.10-5407.72" case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5539$1133_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5408$1034_Y assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5541.7-5545.10" - switch $eq$ls180.v:5541$1135_Y - attribute \src "ls180.v:5541.11-5541.79" + attribute \src "ls180.v:5410.7-5414.10" + switch $eq$ls180.v:5410$1036_Y + attribute \src "ls180.v:5410.11-5410.79" case 1'1 assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5543.11-5543.15" + attribute \src "ls180.v:5412.11-5412.15" case assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 end case end - attribute \src "ls180.v:5547.9-5547.13" + attribute \src "ls180.v:5416.9-5416.13" case - attribute \src "ls180.v:5548.6-5555.9" - switch $eq$ls180.v:5548$1136_Y - attribute \src "ls180.v:5548.10-5548.58" + attribute \src "ls180.v:5417.6-5424.9" + switch $eq$ls180.v:5417$1037_Y + attribute \src "ls180.v:5417.10-5417.58" case 1'1 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 @@ -295183,9 +292213,9 @@ module \ls180 assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5568.4-5582.7" + attribute \src "ls180.v:5437.4-5451.7" switch \main_sdcore_cmd_send_re - attribute \src "ls180.v:5568.8-5568.31" + attribute \src "ls180.v:5437.8-5437.31" case 1'1 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 @@ -295244,72 +292274,72 @@ module \ls180 update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] end - attribute \src "ls180.v:540.11-540.70" - process $proc$ls180.v:540$3281 + attribute \src "ls180.v:531.11-531.68" + process $proc$ls180.v:531$3052 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:541.11-541.70" - process $proc$ls180.v:541$3282 + attribute \src "ls180.v:532.5-532.64" + process $proc$ls180.v:532$3053 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:542.11-542.73" - process $proc$ls180.v:542$3283 + attribute \src "ls180.v:533.11-533.70" + process $proc$ls180.v:533$3054 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:55.5-55.42" - process $proc$ls180.v:55$3128 + attribute \src "ls180.v:534.11-534.70" + process $proc$ls180.v:534$3055 assign { } { } - assign $1\main_libresocsim_reset_storage[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init - update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:56.5-56.37" - process $proc$ls180.v:56$3129 + attribute \src "ls180.v:535.11-535.73" + process $proc$ls180.v:535$3056 assign { } { } - assign $1\main_libresocsim_reset_re[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init - update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:5613.1-5620.4" - process $proc$ls180.v:5613$1137 + attribute \src "ls180.v:5482.1-5489.4" + process $proc$ls180.v:5482$1038 assign { } { } assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5615.2-5619.5" + attribute \src "ls180.v:5484.2-5488.5" switch \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:5615.6-5615.35" + attribute \src "ls180.v:5484.6-5484.35" case 1'1 - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5616$1138_Y - attribute \src "ls180.v:5617.6-5617.10" + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5485$1039_Y + attribute \src "ls180.v:5486.6-5486.10" case assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce end sync always update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:563.5-563.59" - process $proc$ls180.v:563$3284 + attribute \src "ls180.v:55.5-55.42" + process $proc$ls180.v:55$2876 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + assign $1\main_libresocsim_reset_storage[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] end - attribute \src "ls180.v:5646.1-5685.4" - process $proc$ls180.v:5646$1148 + attribute \src "ls180.v:5515.1-5554.4" + process $proc$ls180.v:5515$1049 assign { } { } assign { } { } assign { } { } @@ -295327,31 +292357,31 @@ module \ls180 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state - attribute \src "ls180.v:5656.2-5684.9" + attribute \src "ls180.v:5525.2-5553.9" switch \builder_sdblock2memdma_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5660$1149_Y + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5529$1050_Y assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:5662.4-5673.7" - switch $and$ls180.v:5662$1150_Y - attribute \src "ls180.v:5662.8-5662.103" + attribute \src "ls180.v:5531.4-5542.7" + switch $and$ls180.v:5531$1051_Y + attribute \src "ls180.v:5531.8-5531.103" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5663$1151_Y + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5532$1052_Y assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5665.5-5672.8" - switch $eq$ls180.v:5665$1153_Y - attribute \src "ls180.v:5665.9-5665.106" + attribute \src "ls180.v:5534.5-5541.8" + switch $eq$ls180.v:5534$1054_Y + attribute \src "ls180.v:5534.9-5534.106" case 1'1 - attribute \src "ls180.v:5666.6-5671.9" + attribute \src "ls180.v:5535.6-5540.9" switch \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:5666.10-5666.57" + attribute \src "ls180.v:5535.10-5535.57" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5669.10-5669.14" + attribute \src "ls180.v:5538.10-5538.14" case assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 end @@ -295379,64 +292409,16 @@ module \ls180 update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] end - attribute \src "ls180.v:565.5-565.59" - process $proc$ls180.v:565$3285 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:566.5-566.58" - process $proc$ls180.v:566$3286 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:567.5-567.64" - process $proc$ls180.v:567$3287 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:568.12-568.74" - process $proc$ls180.v:568$3288 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:569.12-569.47" - process $proc$ls180.v:569$3289 - assign { } { } - assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] - end - attribute \src "ls180.v:57.12-57.60" - process $proc$ls180.v:57$3130 - assign { } { } - assign $1\main_libresocsim_scratch_storage[31:0] 305419896 - sync always - sync init - update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] - end - attribute \src "ls180.v:570.5-570.46" - process $proc$ls180.v:570$3290 + attribute \src "ls180.v:556.5-556.59" + process $proc$ls180.v:556$3057 assign { } { } - assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:5705.1-5742.4" - process $proc$ls180.v:5705$1155 + attribute \src "ls180.v:5574.1-5611.4" + process $proc$ls180.v:5574$1056 assign { } { } assign { } { } assign { } { } @@ -295449,8 +292431,6 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 assign $0\main_interface1_bus_adr[31:0] 0 assign { } { } assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 @@ -295459,19 +292439,21 @@ module \ls180 assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 assign $0\main_interface1_bus_cyc[0:0] 1'0 assign $0\main_interface1_bus_stb[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 assign $0\main_interface1_bus_we[0:0] 1'0 assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:5719.2-5741.9" + attribute \src "ls180.v:5588.2-5610.9" switch \builder_sdmem2blockdma_fsm_state attribute \src "ls180.v:0.0-0.0" case 1'1 assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last assign $0\main_sdmem2block_dma_source_payload_data[63:0] \main_sdmem2block_dma_data - attribute \src "ls180.v:5724.4-5727.7" + attribute \src "ls180.v:5593.4-5596.7" switch \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:5724.8-5724.41" + attribute \src "ls180.v:5593.8-5593.41" case 1'1 assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 @@ -295484,9 +292466,9 @@ module \ls180 assign $0\main_interface1_bus_we[0:0] 1'0 assign $0\main_interface1_bus_sel[7:0] 8'11111111 assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:5735.4-5739.7" - switch $and$ls180.v:5735$1156_Y - attribute \src "ls180.v:5735.8-5735.59" + attribute \src "ls180.v:5604.4-5608.7" + switch $and$ls180.v:5604$1057_Y + attribute \src "ls180.v:5604.8-5604.59" case 1'1 assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] \main_interface1_bus_dat_r [39:32] \main_interface1_bus_dat_r [47:40] \main_interface1_bus_dat_r [55:48] \main_interface1_bus_dat_r [63:56] } assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 @@ -295508,33 +292490,48 @@ module \ls180 update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] end - attribute \src "ls180.v:572.5-572.44" - process $proc$ls180.v:572$3291 + attribute \src "ls180.v:558.5-558.59" + process $proc$ls180.v:558$3058 assign { } { } - assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:573.5-573.45" - process $proc$ls180.v:573$3292 + attribute \src "ls180.v:559.5-559.58" + process $proc$ls180.v:559$3059 assign { } { } - assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 + assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:574.5-574.54" - process $proc$ls180.v:574$3293 + attribute \src "ls180.v:56.5-56.37" + process $proc$ls180.v:56$2877 assign { } { } - assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $1\main_libresocsim_reset_re[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] + end + attribute \src "ls180.v:560.5-560.64" + process $proc$ls180.v:560$3060 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:5743.1-5779.4" - process $proc$ls180.v:5743$1157 + attribute \src "ls180.v:561.12-561.74" + process $proc$ls180.v:561$3061 assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:5612.1-5648.4" + process $proc$ls180.v:5612$1058 assign { } { } assign { } { } assign { } { } @@ -295542,37 +292539,38 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign { } { } assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 - assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:5752.2-5778.9" + attribute \src "ls180.v:5621.2-5647.9" switch \builder_sdmem2blockdma_resetinserter_state attribute \src "ls180.v:0.0-0.0" case 2'01 assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 - assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5755$1159_Y - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5756$1160_Y - attribute \src "ls180.v:5757.4-5768.7" + assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5624$1060_Y + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5625$1061_Y + attribute \src "ls180.v:5626.4-5637.7" switch \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:5757.8-5757.39" + attribute \src "ls180.v:5626.8-5626.39" case 1'1 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5758$1161_Y + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5627$1062_Y assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5760.5-5767.8" + attribute \src "ls180.v:5629.5-5636.8" switch \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:5760.9-5760.39" + attribute \src "ls180.v:5629.9-5629.39" case 1'1 - attribute \src "ls180.v:5761.6-5766.9" + attribute \src "ls180.v:5630.6-5635.9" switch \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:5761.10-5761.43" + attribute \src "ls180.v:5630.10-5630.43" case 1'1 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5764.10-5764.14" + attribute \src "ls180.v:5633.10-5633.14" case assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 end @@ -295598,35 +292596,43 @@ module \ls180 update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] end - attribute \src "ls180.v:576.32-576.76" - process $proc$ls180.v:576$3294 + attribute \src "ls180.v:562.12-562.47" + process $proc$ls180.v:562$3062 assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] end - attribute \src "ls180.v:577.11-577.55" - process $proc$ls180.v:577$3295 + attribute \src "ls180.v:563.5-563.46" + process $proc$ls180.v:563$3063 assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] + update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] end - attribute \src "ls180.v:579.32-579.75" - process $proc$ls180.v:579$3296 + attribute \src "ls180.v:565.5-565.44" + process $proc$ls180.v:565$3064 assign { } { } - assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 sync always - update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] sync init + update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] + end + attribute \src "ls180.v:566.5-566.45" + process $proc$ls180.v:566$3065 + assign { } { } + assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] end - attribute \src "ls180.v:5791.1-5819.4" - process $proc$ls180.v:5791$1167 + attribute \src "ls180.v:5660.1-5688.4" + process $proc$ls180.v:5660$1068 assign { } { } assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - attribute \src "ls180.v:5793.2-5818.9" + attribute \src "ls180.v:5662.2-5687.9" switch \main_sdmem2block_converter_mux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -295656,40 +292662,56 @@ module \ls180 sync always update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] end - attribute \src "ls180.v:58.5-58.39" - process $proc$ls180.v:58$3131 + attribute \src "ls180.v:567.5-567.54" + process $proc$ls180.v:567$3066 assign { } { } - assign $1\main_libresocsim_scratch_re[0:0] 1'0 + assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 sync always sync init - update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] + update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:581.32-581.76" - process $proc$ls180.v:581$3297 + attribute \src "ls180.v:569.32-569.76" + process $proc$ls180.v:569$3067 assign { } { } - assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + end + attribute \src "ls180.v:57.12-57.60" + process $proc$ls180.v:57$2878 + assign { } { } + assign $1\main_libresocsim_scratch_storage[31:0] 305419896 + sync always + sync init + update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] + end + attribute \src "ls180.v:570.11-570.55" + process $proc$ls180.v:570$3068 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 sync always - update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] sync init + update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] end - attribute \src "ls180.v:5833.1-5840.4" - process $proc$ls180.v:5833$1168 + attribute \src "ls180.v:5702.1-5709.4" + process $proc$ls180.v:5702$1069 assign { } { } assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5835.2-5839.5" + attribute \src "ls180.v:5704.2-5708.5" switch \main_sdmem2block_fifo_replace - attribute \src "ls180.v:5835.6-5835.35" + attribute \src "ls180.v:5704.6-5704.35" case 1'1 - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5836$1169_Y - attribute \src "ls180.v:5837.6-5837.10" + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5705$1070_Y + attribute \src "ls180.v:5706.6-5706.10" case assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce end sync always update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] end - attribute \src "ls180.v:5848.1-5884.4" - process $proc$ls180.v:5848$1175 + attribute \src "ls180.v:5717.1-5753.4" + process $proc$ls180.v:5717$1076 assign { } { } assign { } { } assign { } { } @@ -295699,17 +292721,17 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 assign { } { } assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 - assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 assign $0\builder_next_state[1:0] \builder_state - attribute \src "ls180.v:5859.2-5883.9" + attribute \src "ls180.v:5728.2-5752.9" switch \builder_state attribute \src "ls180.v:0.0-0.0" case 2'01 @@ -295727,13 +292749,13 @@ module \ls180 case assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5875.4-5881.7" - switch $and$ls180.v:5875$1176_Y - attribute \src "ls180.v:5875.8-5875.77" + attribute \src "ls180.v:5744.4-5750.7" + switch $and$ls180.v:5744$1077_Y + attribute \src "ls180.v:5744.8-5744.77" case 1'1 assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5878$1178_Y + assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5747$1079_Y assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 assign $0\builder_next_state[1:0] 2'01 case @@ -295750,143 +292772,80 @@ module \ls180 update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] end - attribute \src "ls180.v:587.5-587.51" - process $proc$ls180.v:587$3298 - assign { } { } - assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - end - attribute \src "ls180.v:588.5-588.51" - process $proc$ls180.v:588$3299 + attribute \src "ls180.v:572.32-572.75" + process $proc$ls180.v:572$3069 assign { } { } - assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - end - attribute \src "ls180.v:590.5-590.47" - process $proc$ls180.v:590$3300 - assign { } { } - assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] - end - attribute \src "ls180.v:5909.1-5924.4" - process $proc$ls180.v:5909$1199 - assign { } { } - assign { } { } - assign $0\builder_slave_sel[12:0] [0] $eq$ls180.v:5911$1200_Y - assign $0\builder_slave_sel[12:0] [1] $eq$ls180.v:5912$1201_Y - assign $0\builder_slave_sel[12:0] [2] $eq$ls180.v:5913$1202_Y - assign $0\builder_slave_sel[12:0] [3] $eq$ls180.v:5914$1203_Y - assign $0\builder_slave_sel[12:0] [4] $eq$ls180.v:5915$1204_Y - assign $0\builder_slave_sel[12:0] [5] $eq$ls180.v:5916$1205_Y - assign $0\builder_slave_sel[12:0] [6] $eq$ls180.v:5917$1206_Y - assign $0\builder_slave_sel[12:0] [7] $eq$ls180.v:5918$1207_Y - assign $0\builder_slave_sel[12:0] [8] $eq$ls180.v:5919$1208_Y - assign $0\builder_slave_sel[12:0] [9] $eq$ls180.v:5920$1209_Y - assign $0\builder_slave_sel[12:0] [10] $eq$ls180.v:5921$1210_Y - assign $0\builder_slave_sel[12:0] [11] $eq$ls180.v:5922$1211_Y - assign $0\builder_slave_sel[12:0] [12] $eq$ls180.v:5923$1212_Y - sync always - update \builder_slave_sel $0\builder_slave_sel[12:0] - end - attribute \src "ls180.v:591.5-591.45" - process $proc$ls180.v:591$3301 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] - end - attribute \src "ls180.v:592.5-592.45" - process $proc$ls180.v:592$3302 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] - end - attribute \src "ls180.v:593.12-593.57" - process $proc$ls180.v:593$3303 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 sync always + update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] sync init - update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] end - attribute \src "ls180.v:595.5-595.51" - process $proc$ls180.v:595$3304 + attribute \src "ls180.v:574.32-574.76" + process $proc$ls180.v:574$3070 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 sync always + update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] sync init - update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] end - attribute \src "ls180.v:596.5-596.51" - process $proc$ls180.v:596$3305 + attribute \src "ls180.v:5778.1-5786.4" + process $proc$ls180.v:5778$1100 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:597.5-597.50" - process $proc$ls180.v:597$3306 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + assign $0\builder_slave_sel[5:0] [0] $eq$ls180.v:5780$1101_Y + assign $0\builder_slave_sel[5:0] [1] $eq$ls180.v:5781$1102_Y + assign $0\builder_slave_sel[5:0] [2] $eq$ls180.v:5782$1103_Y + assign $0\builder_slave_sel[5:0] [3] $eq$ls180.v:5783$1104_Y + assign $0\builder_slave_sel[5:0] [4] $eq$ls180.v:5784$1105_Y + assign $0\builder_slave_sel[5:0] [5] $eq$ls180.v:5785$1106_Y sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + update \builder_slave_sel $0\builder_slave_sel[5:0] end - attribute \src "ls180.v:598.5-598.54" - process $proc$ls180.v:598$3307 + attribute \src "ls180.v:58.5-58.39" + process $proc$ls180.v:58$2879 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $1\main_libresocsim_scratch_re[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] end - attribute \src "ls180.v:599.5-599.55" - process $proc$ls180.v:599$3308 + attribute \src "ls180.v:580.5-580.51" + process $proc$ls180.v:580$3071 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] end - attribute \src "ls180.v:600.5-600.56" - process $proc$ls180.v:600$3309 + attribute \src "ls180.v:581.5-581.51" + process $proc$ls180.v:581$3072 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] end - attribute \src "ls180.v:601.5-601.50" - process $proc$ls180.v:601$3310 + attribute \src "ls180.v:583.5-583.47" + process $proc$ls180.v:583$3073 assign { } { } - assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] + update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] end - attribute \src "ls180.v:6031.1-6042.4" - process $proc$ls180.v:6031$1241 - assign { } { } + attribute \src "ls180.v:5837.1-5848.4" + process $proc$ls180.v:5837$1121 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\builder_error[0:0] 1'0 - assign $0\builder_shared_ack[0:0] $or$ls180.v:6035$1253_Y - assign $0\builder_shared_dat_r[31:0] $or$ls180.v:6036$1278_Y [31:0] - attribute \src "ls180.v:6037.2-6041.5" + assign { } { } + assign $0\builder_shared_ack[0:0] $or$ls180.v:5841$1126_Y + assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5842$1137_Y [31:0] + attribute \src "ls180.v:5843.2-5847.5" switch \builder_done - attribute \src "ls180.v:6037.6-6037.18" + attribute \src "ls180.v:5843.6-5843.18" case 1'1 assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 assign $0\builder_shared_ack[0:0] 1'1 @@ -295898,157 +292857,157 @@ module \ls180 update \builder_shared_ack $0\builder_shared_ack[0:0] update \builder_error $0\builder_error[0:0] end - attribute \src "ls180.v:604.5-604.67" - process $proc$ls180.v:604$3311 + attribute \src "ls180.v:584.5-584.45" + process $proc$ls180.v:584$3074 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] sync init + update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] end - attribute \src "ls180.v:605.5-605.66" - process $proc$ls180.v:605$3312 + attribute \src "ls180.v:585.5-585.45" + process $proc$ls180.v:585$3075 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] sync init + update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:620.11-620.68" - process $proc$ls180.v:620$3313 + attribute \src "ls180.v:586.12-586.57" + process $proc$ls180.v:586$3076 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:621.5-621.64" - process $proc$ls180.v:621$3314 + attribute \src "ls180.v:588.5-588.51" + process $proc$ls180.v:588$3077 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] sync init + update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] end - attribute \src "ls180.v:622.11-622.70" - process $proc$ls180.v:622$3315 + attribute \src "ls180.v:589.5-589.51" + process $proc$ls180.v:589$3078 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] end - attribute \src "ls180.v:623.11-623.70" - process $proc$ls180.v:623$3316 + attribute \src "ls180.v:590.5-590.50" + process $proc$ls180.v:590$3079 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] end - attribute \src "ls180.v:624.11-624.73" - process $proc$ls180.v:624$3317 + attribute \src "ls180.v:591.5-591.54" + process $proc$ls180.v:591$3080 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:63.12-63.47" - process $proc$ls180.v:63$3132 + attribute \src "ls180.v:592.5-592.55" + process $proc$ls180.v:592$3081 assign { } { } - assign $1\main_libresocsim_bus_errors[31:0] 0 + assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 sync always sync init - update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] + update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] end - attribute \src "ls180.v:645.5-645.59" - process $proc$ls180.v:645$3318 + attribute \src "ls180.v:593.5-593.56" + process $proc$ls180.v:593$3082 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:647.5-647.59" - process $proc$ls180.v:647$3319 + attribute \src "ls180.v:594.5-594.50" + process $proc$ls180.v:594$3083 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 + assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:648.5-648.58" - process $proc$ls180.v:648$3320 + attribute \src "ls180.v:597.5-597.67" + process $proc$ls180.v:597$3084 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] sync init - update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:649.5-649.64" - process $proc$ls180.v:649$3321 + attribute \src "ls180.v:598.5-598.66" + process $proc$ls180.v:598$3085 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:65.12-65.55" - process $proc$ls180.v:65$3133 + attribute \src "ls180.v:613.11-613.68" + process $proc$ls180.v:613$3086 assign { } { } - assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 sync always sync init - update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] end - attribute \src "ls180.v:650.12-650.74" - process $proc$ls180.v:650$3322 + attribute \src "ls180.v:614.5-614.64" + process $proc$ls180.v:614$3087 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:651.12-651.47" - process $proc$ls180.v:651$3323 + attribute \src "ls180.v:615.11-615.70" + process $proc$ls180.v:615$3088 assign { } { } - assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:652.5-652.46" - process $proc$ls180.v:652$3324 + attribute \src "ls180.v:616.11-616.70" + process $proc$ls180.v:616$3089 assign { } { } - assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] end - attribute \src "ls180.v:654.5-654.44" - process $proc$ls180.v:654$3325 + attribute \src "ls180.v:617.11-617.73" + process $proc$ls180.v:617$3090 assign { } { } - assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:655.5-655.45" - process $proc$ls180.v:655$3326 + attribute \src "ls180.v:63.12-63.47" + process $proc$ls180.v:63$2880 assign { } { } - assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 + assign $1\main_libresocsim_bus_errors[31:0] 0 sync always sync init - update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] + update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] end - attribute \src "ls180.v:6556.1-6561.4" - process $proc$ls180.v:6556$2152 + attribute \src "ls180.v:6362.1-6367.4" + process $proc$ls180.v:6362$2011 assign { } { } assign $0\main_spimaster9_start[0:0] 1'0 - attribute \src "ls180.v:6558.2-6560.5" + attribute \src "ls180.v:6364.2-6366.5" switch \main_spimaster12_re - attribute \src "ls180.v:6558.6-6558.25" + attribute \src "ls180.v:6364.6-6364.25" case 1'1 assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] case @@ -296056,37 +293015,29 @@ module \ls180 sync always update \main_spimaster9_start $0\main_spimaster9_start[0:0] end - attribute \src "ls180.v:656.5-656.54" - process $proc$ls180.v:656$3327 - assign { } { } - assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:658.32-658.76" - process $proc$ls180.v:658$3328 + attribute \src "ls180.v:638.5-638.59" + process $proc$ls180.v:638$3091 assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:659.11-659.55" - process $proc$ls180.v:659$3329 + attribute \src "ls180.v:640.5-640.59" + process $proc$ls180.v:640$3092 assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] + update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:6602.1-6607.4" - process $proc$ls180.v:6602$2217 + attribute \src "ls180.v:6408.1-6413.4" + process $proc$ls180.v:6408$2076 assign { } { } assign $0\main_spisdcard_start1[0:0] 1'0 - attribute \src "ls180.v:6604.2-6606.5" + attribute \src "ls180.v:6410.2-6412.5" switch \main_spisdcard_control_re - attribute \src "ls180.v:6604.6-6604.31" + attribute \src "ls180.v:6410.6-6410.31" case 1'1 assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0] case @@ -296094,99 +293045,115 @@ module \ls180 sync always update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] end - attribute \src "ls180.v:661.32-661.75" - process $proc$ls180.v:661$3330 + attribute \src "ls180.v:641.5-641.58" + process $proc$ls180.v:641$3093 assign { } { } - assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 sync always - update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] sync init + update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:663.32-663.76" - process $proc$ls180.v:663$3331 + attribute \src "ls180.v:642.5-642.64" + process $proc$ls180.v:642$3094 assign { } { } - assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 sync always - update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:669.5-669.51" - process $proc$ls180.v:669$3332 + attribute \src "ls180.v:643.12-643.74" + process $proc$ls180.v:643$3095 assign { } { } - assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 sync always sync init - update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] end - attribute \src "ls180.v:670.5-670.51" - process $proc$ls180.v:670$3333 + attribute \src "ls180.v:644.12-644.47" + process $proc$ls180.v:644$3096 assign { } { } - assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] end - attribute \src "ls180.v:672.5-672.47" - process $proc$ls180.v:672$3334 + attribute \src "ls180.v:645.5-645.46" + process $proc$ls180.v:645$3097 assign { } { } - assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] + update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] end - attribute \src "ls180.v:673.5-673.45" - process $proc$ls180.v:673$3335 + attribute \src "ls180.v:647.5-647.44" + process $proc$ls180.v:647$3098 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] + update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] end - attribute \src "ls180.v:674.5-674.45" - process $proc$ls180.v:674$3336 + attribute \src "ls180.v:648.5-648.45" + process $proc$ls180.v:648$3099 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] + update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] end - attribute \src "ls180.v:675.12-675.57" - process $proc$ls180.v:675$3337 + attribute \src "ls180.v:649.5-649.54" + process $proc$ls180.v:649$3100 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:677.5-677.51" - process $proc$ls180.v:677$3338 + attribute \src "ls180.v:65.12-65.55" + process $proc$ls180.v:65$2881 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] end - attribute \src "ls180.v:678.5-678.51" - process $proc$ls180.v:678$3339 + attribute \src "ls180.v:651.32-651.76" + process $proc$ls180.v:651$3101 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] end - attribute \src "ls180.v:679.5-679.50" - process $proc$ls180.v:679$3340 + attribute \src "ls180.v:652.11-652.55" + process $proc$ls180.v:652$3102 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + end + attribute \src "ls180.v:654.32-654.75" + process $proc$ls180.v:654$3103 + assign { } { } + assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] + sync init end - attribute \src "ls180.v:6791.1-6807.4" - process $proc$ls180.v:6791$2438 + attribute \src "ls180.v:656.32-656.76" + process $proc$ls180.v:656$3104 + assign { } { } + assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:6597.1-6613.4" + process $proc$ls180.v:6597$2297 assign { } { } assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6793.2-6806.9" + attribute \src "ls180.v:6599.2-6612.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296204,19 +293171,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] end - attribute \src "ls180.v:680.5-680.54" - process $proc$ls180.v:680$3341 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:6808.1-6824.4" - process $proc$ls180.v:6808$2439 + attribute \src "ls180.v:6614.1-6630.4" + process $proc$ls180.v:6614$2298 assign { } { } assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:6810.2-6823.9" + attribute \src "ls180.v:6616.2-6629.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296234,27 +293193,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:681.5-681.55" - process $proc$ls180.v:681$3342 + attribute \src "ls180.v:662.5-662.51" + process $proc$ls180.v:662$3105 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] end - attribute \src "ls180.v:682.5-682.56" - process $proc$ls180.v:682$3343 + attribute \src "ls180.v:663.5-663.51" + process $proc$ls180.v:663$3106 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] end - attribute \src "ls180.v:6825.1-6841.4" - process $proc$ls180.v:6825$2440 + attribute \src "ls180.v:6631.1-6647.4" + process $proc$ls180.v:6631$2299 assign { } { } assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 - attribute \src "ls180.v:6827.2-6840.9" + attribute \src "ls180.v:6633.2-6646.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296272,19 +293231,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] end - attribute \src "ls180.v:683.5-683.50" - process $proc$ls180.v:683$3344 - assign { } { } - assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] - end - attribute \src "ls180.v:6842.1-6858.4" - process $proc$ls180.v:6842$2441 + attribute \src "ls180.v:6648.1-6664.4" + process $proc$ls180.v:6648$2300 assign { } { } assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6844.2-6857.9" + attribute \src "ls180.v:6650.2-6663.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296302,11 +293253,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:6859.1-6875.4" - process $proc$ls180.v:6859$2442 + attribute \src "ls180.v:665.5-665.47" + process $proc$ls180.v:665$3107 + assign { } { } + assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] + end + attribute \src "ls180.v:666.5-666.45" + process $proc$ls180.v:666$3108 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] + end + attribute \src "ls180.v:6665.1-6681.4" + process $proc$ls180.v:6665$2301 assign { } { } assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6861.2-6874.9" + attribute \src "ls180.v:6667.2-6680.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296324,27 +293291,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:686.5-686.67" - process $proc$ls180.v:686$3345 + attribute \src "ls180.v:667.5-667.45" + process $proc$ls180.v:667$3109 assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] sync init + update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "ls180.v:687.5-687.66" - process $proc$ls180.v:687$3346 + attribute \src "ls180.v:668.12-668.57" + process $proc$ls180.v:668$3110 assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] sync init + update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "ls180.v:6876.1-6892.4" - process $proc$ls180.v:6876$2443 + attribute \src "ls180.v:6682.1-6698.4" + process $proc$ls180.v:6682$2302 assign { } { } assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6878.2-6891.9" + attribute \src "ls180.v:6684.2-6697.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296362,11 +293329,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:6893.1-6909.4" - process $proc$ls180.v:6893$2444 + attribute \src "ls180.v:6699.1-6715.4" + process $proc$ls180.v:6699$2303 assign { } { } assign $0\builder_comb_t_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6895.2-6908.9" + attribute \src "ls180.v:6701.2-6714.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296384,11 +293351,27 @@ module \ls180 sync always update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] end - attribute \src "ls180.v:6910.1-6926.4" - process $proc$ls180.v:6910$2445 + attribute \src "ls180.v:670.5-670.51" + process $proc$ls180.v:670$3111 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:671.5-671.51" + process $proc$ls180.v:671$3112 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:6716.1-6732.4" + process $proc$ls180.v:6716$2304 assign { } { } assign $0\builder_comb_t_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:6912.2-6925.9" + attribute \src "ls180.v:6718.2-6731.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296406,11 +293389,27 @@ module \ls180 sync always update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] end - attribute \src "ls180.v:6927.1-6943.4" - process $proc$ls180.v:6927$2446 + attribute \src "ls180.v:672.5-672.50" + process $proc$ls180.v:672$3113 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + end + attribute \src "ls180.v:673.5-673.54" + process $proc$ls180.v:673$3114 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:6733.1-6749.4" + process $proc$ls180.v:6733$2305 assign { } { } assign $0\builder_comb_t_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:6929.2-6942.9" + attribute \src "ls180.v:6735.2-6748.9" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296428,11 +293427,27 @@ module \ls180 sync always update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] end - attribute \src "ls180.v:6944.1-6960.4" - process $proc$ls180.v:6944$2447 + attribute \src "ls180.v:674.5-674.55" + process $proc$ls180.v:674$3115 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:675.5-675.56" + process $proc$ls180.v:675$3116 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:6750.1-6766.4" + process $proc$ls180.v:6750$2306 assign { } { } assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:6946.2-6959.9" + attribute \src "ls180.v:6752.2-6765.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296450,11 +293465,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:6961.1-6977.4" - process $proc$ls180.v:6961$2448 + attribute \src "ls180.v:676.5-676.50" + process $proc$ls180.v:676$3117 + assign { } { } + assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:6767.1-6783.4" + process $proc$ls180.v:6767$2307 assign { } { } assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - attribute \src "ls180.v:6963.2-6976.9" + attribute \src "ls180.v:6769.2-6782.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296472,11 +293495,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] end - attribute \src "ls180.v:6978.1-6994.4" - process $proc$ls180.v:6978$2449 + attribute \src "ls180.v:6784.1-6800.4" + process $proc$ls180.v:6784$2308 assign { } { } assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 - attribute \src "ls180.v:6980.2-6993.9" + attribute \src "ls180.v:6786.2-6799.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296494,11 +293517,27 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] end - attribute \src "ls180.v:6995.1-7011.4" - process $proc$ls180.v:6995$2450 + attribute \src "ls180.v:679.5-679.67" + process $proc$ls180.v:679$3118 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:680.5-680.66" + process $proc$ls180.v:680$3119 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:6801.1-6817.4" + process $proc$ls180.v:6801$2309 assign { } { } assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 - attribute \src "ls180.v:6997.2-7010.9" + attribute \src "ls180.v:6803.2-6816.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296516,11 +293555,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] end - attribute \src "ls180.v:7012.1-7028.4" - process $proc$ls180.v:7012$2451 + attribute \src "ls180.v:6818.1-6834.4" + process $proc$ls180.v:6818$2310 assign { } { } assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 - attribute \src "ls180.v:7014.2-7027.9" + attribute \src "ls180.v:6820.2-6833.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296538,19 +293577,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] end - attribute \src "ls180.v:702.11-702.68" - process $proc$ls180.v:702$3347 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:7029.1-7045.4" - process $proc$ls180.v:7029$2452 + attribute \src "ls180.v:6835.1-6851.4" + process $proc$ls180.v:6835$2311 assign { } { } assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 - attribute \src "ls180.v:7031.2-7044.9" + attribute \src "ls180.v:6837.2-6850.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296568,27 +293599,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] end - attribute \src "ls180.v:703.5-703.64" - process $proc$ls180.v:703$3348 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:704.11-704.70" - process $proc$ls180.v:704$3349 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:7046.1-7062.4" - process $proc$ls180.v:7046$2453 + attribute \src "ls180.v:6852.1-6868.4" + process $proc$ls180.v:6852$2312 assign { } { } assign $0\builder_comb_t_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:7048.2-7061.9" + attribute \src "ls180.v:6854.2-6867.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296606,27 +293621,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] end - attribute \src "ls180.v:705.11-705.70" - process $proc$ls180.v:705$3350 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:706.11-706.73" - process $proc$ls180.v:706$3351 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:7063.1-7079.4" - process $proc$ls180.v:7063$2454 + attribute \src "ls180.v:6869.1-6885.4" + process $proc$ls180.v:6869$2313 assign { } { } assign $0\builder_comb_t_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:7065.2-7078.9" + attribute \src "ls180.v:6871.2-6884.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296644,11 +293643,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] end - attribute \src "ls180.v:7080.1-7096.4" - process $proc$ls180.v:7080$2455 + attribute \src "ls180.v:6886.1-6902.4" + process $proc$ls180.v:6886$2314 assign { } { } assign $0\builder_comb_t_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:7082.2-7095.9" + attribute \src "ls180.v:6888.2-6901.9" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -296666,11 +293665,11 @@ module \ls180 sync always update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] end - attribute \src "ls180.v:7097.1-7104.4" - process $proc$ls180.v:7097$2456 + attribute \src "ls180.v:6903.1-6910.4" + process $proc$ls180.v:6903$2315 assign { } { } assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:7099.2-7103.9" + attribute \src "ls180.v:6905.2-6909.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case @@ -296679,11 +293678,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] end - attribute \src "ls180.v:7105.1-7112.4" - process $proc$ls180.v:7105$2457 + attribute \src "ls180.v:6911.1-6918.4" + process $proc$ls180.v:6911$2316 assign { } { } assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 - attribute \src "ls180.v:7107.2-7111.9" + attribute \src "ls180.v:6913.2-6917.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case @@ -296692,24 +293691,24 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] end - attribute \src "ls180.v:7113.1-7120.4" - process $proc$ls180.v:7113$2458 + attribute \src "ls180.v:6919.1-6926.4" + process $proc$ls180.v:6919$2317 assign { } { } assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 - attribute \src "ls180.v:7115.2-7119.9" + attribute \src "ls180.v:6921.2-6925.9" switch \builder_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:7117$2471_Y + assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6923$2330_Y end sync always update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] end - attribute \src "ls180.v:7121.1-7128.4" - process $proc$ls180.v:7121$2472 + attribute \src "ls180.v:6927.1-6934.4" + process $proc$ls180.v:6927$2331 assign { } { } assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:7123.2-7127.9" + attribute \src "ls180.v:6929.2-6933.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case @@ -296718,11 +293717,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] end - attribute \src "ls180.v:7129.1-7136.4" - process $proc$ls180.v:7129$2473 + attribute \src "ls180.v:6935.1-6942.4" + process $proc$ls180.v:6935$2332 assign { } { } assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 - attribute \src "ls180.v:7131.2-7135.9" + attribute \src "ls180.v:6937.2-6941.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case @@ -296731,24 +293730,32 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] end - attribute \src "ls180.v:7137.1-7144.4" - process $proc$ls180.v:7137$2474 + attribute \src "ls180.v:6943.1-6950.4" + process $proc$ls180.v:6943$2333 assign { } { } assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 - attribute \src "ls180.v:7139.2-7143.9" + attribute \src "ls180.v:6945.2-6949.9" switch \builder_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:7141$2487_Y + assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6947$2346_Y end sync always update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] end - attribute \src "ls180.v:7145.1-7152.4" - process $proc$ls180.v:7145$2488 + attribute \src "ls180.v:695.11-695.68" + process $proc$ls180.v:695$3120 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:6951.1-6958.4" + process $proc$ls180.v:6951$2347 assign { } { } assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:7147.2-7151.9" + attribute \src "ls180.v:6953.2-6957.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case @@ -296757,11 +293764,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] end - attribute \src "ls180.v:7153.1-7160.4" - process $proc$ls180.v:7153$2489 + attribute \src "ls180.v:6959.1-6966.4" + process $proc$ls180.v:6959$2348 assign { } { } assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 - attribute \src "ls180.v:7155.2-7159.9" + attribute \src "ls180.v:6961.2-6965.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case @@ -296770,24 +293777,40 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] end - attribute \src "ls180.v:7161.1-7168.4" - process $proc$ls180.v:7161$2490 + attribute \src "ls180.v:696.5-696.64" + process $proc$ls180.v:696$3121 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:6967.1-6974.4" + process $proc$ls180.v:6967$2349 assign { } { } assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 - attribute \src "ls180.v:7163.2-7167.9" + attribute \src "ls180.v:6969.2-6973.9" switch \builder_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:7165$2503_Y + assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6971$2362_Y end sync always update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] end - attribute \src "ls180.v:7169.1-7176.4" - process $proc$ls180.v:7169$2504 + attribute \src "ls180.v:697.11-697.70" + process $proc$ls180.v:697$3122 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:6975.1-6982.4" + process $proc$ls180.v:6975$2363 assign { } { } assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:7171.2-7175.9" + attribute \src "ls180.v:6977.2-6981.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case @@ -296796,11 +293819,19 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] end - attribute \src "ls180.v:7177.1-7184.4" - process $proc$ls180.v:7177$2505 + attribute \src "ls180.v:698.11-698.70" + process $proc$ls180.v:698$3123 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:6983.1-6990.4" + process $proc$ls180.v:6983$2364 assign { } { } assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 - attribute \src "ls180.v:7179.2-7183.9" + attribute \src "ls180.v:6985.2-6989.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case @@ -296809,24 +293840,32 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] end - attribute \src "ls180.v:7185.1-7192.4" - process $proc$ls180.v:7185$2506 + attribute \src "ls180.v:699.11-699.73" + process $proc$ls180.v:699$3124 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:6991.1-6998.4" + process $proc$ls180.v:6991$2365 assign { } { } assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 - attribute \src "ls180.v:7187.2-7191.9" + attribute \src "ls180.v:6993.2-6997.9" switch \builder_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:7189$2519_Y + assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6995$2378_Y end sync always update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] end - attribute \src "ls180.v:7193.1-7212.4" - process $proc$ls180.v:7193$2520 + attribute \src "ls180.v:6999.1-7018.4" + process $proc$ls180.v:6999$2379 assign { } { } assign $0\builder_comb_rhs_array_muxed24[31:0] 0 - attribute \src "ls180.v:7195.2-7211.9" + attribute \src "ls180.v:7001.2-7017.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -296847,11 +293886,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] end - attribute \src "ls180.v:7213.1-7232.4" - process $proc$ls180.v:7213$2521 + attribute \src "ls180.v:7019.1-7038.4" + process $proc$ls180.v:7019$2380 assign { } { } assign $0\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "ls180.v:7215.2-7231.9" + attribute \src "ls180.v:7021.2-7037.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -296872,11 +293911,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[63:0] end - attribute \src "ls180.v:7233.1-7252.4" - process $proc$ls180.v:7233$2522 + attribute \src "ls180.v:7039.1-7058.4" + process $proc$ls180.v:7039$2381 assign { } { } assign $0\builder_comb_rhs_array_muxed26[7:0] 8'00000000 - attribute \src "ls180.v:7235.2-7251.9" + attribute \src "ls180.v:7041.2-7057.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -296897,11 +293936,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[7:0] end - attribute \src "ls180.v:7253.1-7272.4" - process $proc$ls180.v:7253$2523 + attribute \src "ls180.v:7059.1-7078.4" + process $proc$ls180.v:7059$2382 assign { } { } assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 - attribute \src "ls180.v:7255.2-7271.9" + attribute \src "ls180.v:7061.2-7077.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -296922,19 +293961,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] end - attribute \src "ls180.v:727.5-727.59" - process $proc$ls180.v:727$3352 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:7273.1-7292.4" - process $proc$ls180.v:7273$2524 + attribute \src "ls180.v:7079.1-7098.4" + process $proc$ls180.v:7079$2383 assign { } { } assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 - attribute \src "ls180.v:7275.2-7291.9" + attribute \src "ls180.v:7081.2-7097.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -296955,19 +293986,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] end - attribute \src "ls180.v:729.5-729.59" - process $proc$ls180.v:729$3353 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:7293.1-7312.4" - process $proc$ls180.v:7293$2525 + attribute \src "ls180.v:7099.1-7118.4" + process $proc$ls180.v:7099$2384 assign { } { } assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 - attribute \src "ls180.v:7295.2-7311.9" + attribute \src "ls180.v:7101.2-7117.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -296988,27 +294011,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] end - attribute \src "ls180.v:730.5-730.58" - process $proc$ls180.v:730$3354 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:731.5-731.64" - process $proc$ls180.v:731$3355 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:7313.1-7332.4" - process $proc$ls180.v:7313$2526 + attribute \src "ls180.v:7119.1-7138.4" + process $proc$ls180.v:7119$2385 assign { } { } assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 - attribute \src "ls180.v:7315.2-7331.9" + attribute \src "ls180.v:7121.2-7137.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -297029,27 +294036,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] end - attribute \src "ls180.v:732.12-732.74" - process $proc$ls180.v:732$3356 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:733.12-733.47" - process $proc$ls180.v:733$3357 - assign { } { } - assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] - end - attribute \src "ls180.v:7333.1-7352.4" - process $proc$ls180.v:7333$2527 + attribute \src "ls180.v:7139.1-7158.4" + process $proc$ls180.v:7139$2386 assign { } { } assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 - attribute \src "ls180.v:7335.2-7351.9" + attribute \src "ls180.v:7141.2-7157.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -297070,19 +294061,11 @@ module \ls180 sync always update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] end - attribute \src "ls180.v:734.5-734.46" - process $proc$ls180.v:734$3358 - assign { } { } - assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] - end - attribute \src "ls180.v:7353.1-7369.4" - process $proc$ls180.v:7353$2528 + attribute \src "ls180.v:7159.1-7175.4" + process $proc$ls180.v:7159$2387 assign { } { } assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 - attribute \src "ls180.v:7355.2-7368.9" + attribute \src "ls180.v:7161.2-7174.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -297100,27 +294083,11 @@ module \ls180 sync always update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] end - attribute \src "ls180.v:736.5-736.44" - process $proc$ls180.v:736$3359 - assign { } { } - assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] - end - attribute \src "ls180.v:737.5-737.45" - process $proc$ls180.v:737$3360 - assign { } { } - assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] - end - attribute \src "ls180.v:7370.1-7386.4" - process $proc$ls180.v:7370$2529 + attribute \src "ls180.v:7176.1-7192.4" + process $proc$ls180.v:7176$2388 assign { } { } assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:7372.2-7385.9" + attribute \src "ls180.v:7178.2-7191.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -297138,169 +294105,177 @@ module \ls180 sync always update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:738.5-738.54" - process $proc$ls180.v:738$3361 - assign { } { } - assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:7387.1-7403.4" - process $proc$ls180.v:7387$2530 + attribute \src "ls180.v:7193.1-7209.4" + process $proc$ls180.v:7193$2389 assign { } { } assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:7389.2-7402.9" + attribute \src "ls180.v:7195.2-7208.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7394$2532_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7200$2391_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7397$2534_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7203$2393_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7400$2536_Y + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7206$2395_Y end sync always update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] end - attribute \src "ls180.v:74.11-74.52" - process $proc$ls180.v:74$3134 - assign { } { } - assign $0\main_libresocsim_libresoc_dbus_cti[2:0] 3'000 - sync always - update \main_libresocsim_libresoc_dbus_cti $0\main_libresocsim_libresoc_dbus_cti[2:0] - sync init - end - attribute \src "ls180.v:740.32-740.76" - process $proc$ls180.v:740$3362 + attribute \src "ls180.v:720.5-720.59" + process $proc$ls180.v:720$3125 assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] end - attribute \src "ls180.v:7404.1-7420.4" - process $proc$ls180.v:7404$2537 + attribute \src "ls180.v:7210.1-7226.4" + process $proc$ls180.v:7210$2396 assign { } { } assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:7406.2-7419.9" + attribute \src "ls180.v:7212.2-7225.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7411$2539_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7217$2398_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7414$2541_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7220$2400_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7417$2543_Y + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7223$2402_Y end sync always update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] end - attribute \src "ls180.v:741.11-741.55" - process $proc$ls180.v:741$3363 + attribute \src "ls180.v:722.5-722.59" + process $proc$ls180.v:722$3126 assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] end - attribute \src "ls180.v:7421.1-7437.4" - process $proc$ls180.v:7421$2544 + attribute \src "ls180.v:7227.1-7243.4" + process $proc$ls180.v:7227$2403 assign { } { } assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:7423.2-7436.9" + attribute \src "ls180.v:7229.2-7242.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7428$2546_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7234$2405_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7431$2548_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7237$2407_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7434$2550_Y + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7240$2409_Y end sync always update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] end - attribute \src "ls180.v:743.32-743.75" - process $proc$ls180.v:743$3364 + attribute \src "ls180.v:723.5-723.58" + process $proc$ls180.v:723$3127 assign { } { } - assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 sync always - update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] sync init + update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] end - attribute \src "ls180.v:7438.1-7454.4" - process $proc$ls180.v:7438$2551 + attribute \src "ls180.v:724.5-724.64" + process $proc$ls180.v:724$3128 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:7244.1-7260.4" + process $proc$ls180.v:7244$2410 assign { } { } assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:7440.2-7453.9" + attribute \src "ls180.v:7246.2-7259.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7445$2553_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7251$2412_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7448$2555_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7254$2414_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7451$2557_Y + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7257$2416_Y end sync always update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] end - attribute \src "ls180.v:745.32-745.76" - process $proc$ls180.v:745$3365 + attribute \src "ls180.v:725.12-725.74" + process $proc$ls180.v:725$3129 assign { } { } - assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:726.12-726.47" + process $proc$ls180.v:726$3130 + assign { } { } + assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 sync always - update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] sync init + update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] end - attribute \src "ls180.v:7455.1-7471.4" - process $proc$ls180.v:7455$2558 + attribute \src "ls180.v:7261.1-7277.4" + process $proc$ls180.v:7261$2417 assign { } { } assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:7457.2-7470.9" + attribute \src "ls180.v:7263.2-7276.9" switch \main_sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7462$2560_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7268$2419_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7465$2562_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7271$2421_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7468$2564_Y + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7274$2423_Y end sync always update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] end - attribute \src "ls180.v:7472.1-7500.4" - process $proc$ls180.v:7472$2565 + attribute \src "ls180.v:727.5-727.46" + process $proc$ls180.v:727$3131 + assign { } { } + assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] + end + attribute \src "ls180.v:7278.1-7306.4" + process $proc$ls180.v:7278$2424 assign { } { } assign $0\builder_sync_f_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:7474.2-7499.9" + attribute \src "ls180.v:7280.2-7305.9" switch \main_spimaster34_mosi_sel attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -297330,19 +294305,27 @@ module \ls180 sync always update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] end - attribute \src "ls180.v:75.11-75.52" - process $proc$ls180.v:75$3135 + attribute \src "ls180.v:729.5-729.44" + process $proc$ls180.v:729$3132 assign { } { } - assign $0\main_libresocsim_libresoc_dbus_bte[1:0] 2'00 + assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 sync always - update \main_libresocsim_libresoc_dbus_bte $0\main_libresocsim_libresoc_dbus_bte[1:0] sync init + update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] + end + attribute \src "ls180.v:730.5-730.45" + process $proc$ls180.v:730$3133 + assign { } { } + assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] end - attribute \src "ls180.v:7501.1-7529.4" - process $proc$ls180.v:7501$2566 + attribute \src "ls180.v:7307.1-7335.4" + process $proc$ls180.v:7307$2425 assign { } { } assign $0\builder_sync_f_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:7503.2-7528.9" + attribute \src "ls180.v:7309.2-7334.9" switch \main_spisdcard_mosi_sel attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -297372,56 +294355,48 @@ module \ls180 sync always update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] end - attribute \src "ls180.v:751.5-751.51" - process $proc$ls180.v:751$3366 + attribute \src "ls180.v:731.5-731.54" + process $proc$ls180.v:731$3134 assign { } { } - assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - end - attribute \src "ls180.v:752.5-752.51" - process $proc$ls180.v:752$3367 - assign { } { } - assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] end - attribute \src "ls180.v:754.5-754.47" - process $proc$ls180.v:754$3368 + attribute \src "ls180.v:733.32-733.76" + process $proc$ls180.v:733$3135 assign { } { } - assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] + update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] end - attribute \src "ls180.v:755.5-755.45" - process $proc$ls180.v:755$3369 + attribute \src "ls180.v:734.11-734.55" + process $proc$ls180.v:734$3136 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] + update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] end - attribute \src "ls180.v:756.5-756.45" - process $proc$ls180.v:756$3370 + attribute \src "ls180.v:736.32-736.75" + process $proc$ls180.v:736$3137 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 sync always + update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] sync init - update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "ls180.v:757.12-757.57" - process $proc$ls180.v:757$3371 + attribute \src "ls180.v:738.32-738.76" + process $proc$ls180.v:738$3138 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 sync always + update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] sync init - update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "ls180.v:7587.1-7597.4" - process $proc$ls180.v:7587$2567 + attribute \src "ls180.v:7393.1-7403.4" + process $proc$ls180.v:7393$2426 assign { } { } assign $0\main_gpiotristateasic0_status[15:0] [15:8] 8'00000000 assign $0\main_gpiotristateasic0_status[15:0] [0] \builder_multiregimpl1_regs1 @@ -297435,16 +294410,16 @@ module \ls180 sync always update \main_gpiotristateasic0_status $0\main_gpiotristateasic0_status[15:0] end - attribute \src "ls180.v:759.5-759.51" - process $proc$ls180.v:759$3372 + attribute \src "ls180.v:74.11-74.52" + process $proc$ls180.v:74$2882 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign $0\main_libresocsim_libresoc_dbus_cti[2:0] 3'000 sync always + update \main_libresocsim_libresoc_dbus_cti $0\main_libresocsim_libresoc_dbus_cti[2:0] sync init - update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] end - attribute \src "ls180.v:7598.1-7608.4" - process $proc$ls180.v:7598$2568 + attribute \src "ls180.v:7404.1-7414.4" + process $proc$ls180.v:7404$2427 assign { } { } assign $0\main_gpiotristateasic1_status[15:0] [7:0] 8'00000000 assign $0\main_gpiotristateasic1_status[15:0] [8] \builder_multiregimpl9_regs1 @@ -297458,47 +294433,39 @@ module \ls180 sync always update \main_gpiotristateasic1_status $0\main_gpiotristateasic1_status[15:0] end - attribute \src "ls180.v:760.5-760.51" - process $proc$ls180.v:760$3373 + attribute \src "ls180.v:741.5-741.44" + process $proc$ls180.v:741$3139 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 sync always + update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] sync init - update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] end - attribute \src "ls180.v:761.5-761.50" - process $proc$ls180.v:761$3374 + attribute \src "ls180.v:742.5-742.45" + process $proc$ls180.v:742$3140 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 sync always + update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] sync init - update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] end - attribute \src "ls180.v:762.5-762.54" - process $proc$ls180.v:762$3375 + attribute \src "ls180.v:743.5-743.43" + process $proc$ls180.v:743$3141 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 sync always + update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] sync init - update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:7629.1-7631.4" - process $proc$ls180.v:7629$2569 + attribute \src "ls180.v:7435.1-7437.4" + process $proc$ls180.v:7435$2428 assign { } { } assign $0\main_int_rst[0:0] \sys_rst sync posedge \por_clk update \main_int_rst $0\main_int_rst[0:0] end - attribute \src "ls180.v:763.5-763.55" - process $proc$ls180.v:763$3376 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:7633.1-7703.4" - process $proc$ls180.v:7633$2570 + attribute \src "ls180.v:7439.1-7509.4" + process $proc$ls180.v:7439$2429 assign { } { } assign { } { } assign { } { } @@ -297571,10 +294538,10 @@ module \ls180 assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14] assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15] assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15] - assign $0\sdram_dm[1:0] [0] $and$ls180.v:7687$2571_Y - assign $0\sdram_dm[1:0] [1] $and$ls180.v:7688$2572_Y + assign $0\sdram_dm[1:0] [0] $and$ls180.v:7493$2430_Y + assign $0\sdram_dm[1:0] [1] $and$ls180.v:7494$2431_Y assign $0\sdram_clock[0:0] \sys_clk_1 - assign $0\sdcard_clk[0:0] $and$ls180.v:7690$2574_Y + assign $0\sdcard_clk[0:0] $and$ls180.v:7496$2433_Y assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i @@ -297588,6 +294555,11 @@ module \ls180 assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] sync posedge \sdrio_clk + update \sdcard_clk $0\sdcard_clk[0:0] + update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] + update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] + update \sdcard_data_o $0\sdcard_data_o[3:0] + update \sdcard_data_oe $0\sdcard_data_oe[0:0] update \sdram_a $0\sdram_a[12:0] update \sdram_dq_o $0\sdram_dq_o[15:0] update \sdram_dq_oe $0\sdram_dq_oe[0:0] @@ -297599,57 +294571,68 @@ module \ls180 update \sdram_ba $0\sdram_ba[1:0] update \sdram_dm $0\sdram_dm[1:0] update \sdram_clock $0\sdram_clock[0:0] - update \sdcard_clk $0\sdcard_clk[0:0] - update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] - update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] - update \sdcard_data_o $0\sdcard_data_o[3:0] - update \sdcard_data_oe $0\sdcard_data_oe[0:0] update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] end - attribute \src "ls180.v:764.5-764.56" - process $proc$ls180.v:764$3377 + attribute \src "ls180.v:744.5-744.48" + process $proc$ls180.v:744$3142 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 sync always + update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] sync init - update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] end - attribute \src "ls180.v:765.5-765.50" - process $proc$ls180.v:765$3378 + attribute \src "ls180.v:746.5-746.43" + process $proc$ls180.v:746$3143 assign { } { } - assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 sync always + update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] sync init - update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] end - attribute \src "ls180.v:768.5-768.67" - process $proc$ls180.v:768$3379 + attribute \src "ls180.v:749.5-749.49" + process $proc$ls180.v:749$3144 assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] sync init + update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "ls180.v:769.5-769.66" - process $proc$ls180.v:769$3380 + attribute \src "ls180.v:75.11-75.52" + process $proc$ls180.v:75$2883 assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $0\main_libresocsim_libresoc_dbus_bte[1:0] 2'00 + sync always + update \main_libresocsim_libresoc_dbus_bte $0\main_libresocsim_libresoc_dbus_bte[1:0] + sync init + end + attribute \src "ls180.v:750.5-750.49" + process $proc$ls180.v:750$3145 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:751.5-751.48" + process $proc$ls180.v:751$3146 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] sync init + update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "ls180.v:7705.1-10349.4" - process $proc$ls180.v:7705$2575 + attribute \src "ls180.v:7511.1-10140.4" + process $proc$ls180.v:7511$2434 + assign $0\uart_tx[0:0] \uart_tx assign $0\spisdcard_clk[0:0] \spisdcard_clk assign $0\spisdcard_mosi[0:0] \spisdcard_mosi assign { } { } - assign $0\pwm[1:0] \pwm assign $0\spimaster_clk[0:0] \spimaster_clk assign $0\spimaster_mosi[0:0] \spimaster_mosi assign { } { } - assign $0\uart_tx[0:0] \uart_tx + assign $0\pwm[1:0] \pwm assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage assign { } { } assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage @@ -297671,9 +294654,6 @@ module \ls180 assign { } { } assign $0\main_libresocsim_value[31:0] \main_libresocsim_value assign { } { } - assign { } { } - assign { } { } - assign { } { } assign $0\main_converter0_counter[0:0] \main_converter0_counter assign $0\main_converter0_dat_r[63:0] \main_converter0_dat_r assign $0\main_converter1_counter[0:0] \main_converter1_counter @@ -298058,39 +295038,36 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_dummy[23:0] [0] $or$ls180.v:7706$2576_Y - assign $0\main_dummy[23:0] [1] $or$ls180.v:7707$2577_Y - assign $0\main_dummy[23:0] [2] $or$ls180.v:7708$2578_Y - assign $0\main_dummy[23:0] [3] $or$ls180.v:7709$2579_Y - assign $0\main_dummy[23:0] [4] $or$ls180.v:7710$2580_Y - assign $0\main_dummy[23:0] [5] $or$ls180.v:7711$2581_Y - assign $0\main_dummy[23:0] [6] $or$ls180.v:7712$2582_Y - assign $0\main_dummy[23:0] [7] $or$ls180.v:7713$2583_Y - assign $0\main_dummy[23:0] [8] $or$ls180.v:7714$2584_Y - assign $0\main_dummy[23:0] [9] $or$ls180.v:7715$2585_Y - assign $0\main_dummy[23:0] [10] $or$ls180.v:7716$2586_Y - assign $0\main_dummy[23:0] [11] $or$ls180.v:7717$2587_Y - assign $0\main_dummy[23:0] [12] $or$ls180.v:7718$2588_Y - assign $0\main_dummy[23:0] [13] $or$ls180.v:7719$2589_Y - assign $0\main_dummy[23:0] [14] $or$ls180.v:7720$2590_Y - assign $0\main_dummy[23:0] [15] $or$ls180.v:7721$2591_Y - assign $0\main_dummy[23:0] [16] $or$ls180.v:7722$2592_Y - assign $0\main_dummy[23:0] [17] $or$ls180.v:7723$2593_Y - assign $0\main_dummy[23:0] [18] $or$ls180.v:7724$2594_Y - assign $0\main_dummy[23:0] [19] $or$ls180.v:7725$2595_Y - assign $0\main_dummy[23:0] [20] $or$ls180.v:7726$2596_Y - assign $0\main_dummy[23:0] [21] $or$ls180.v:7727$2597_Y - assign $0\main_dummy[23:0] [22] $or$ls180.v:7728$2598_Y - assign $0\main_dummy[23:0] [23] $or$ls180.v:7729$2599_Y + assign $0\main_dummy[23:0] [0] $or$ls180.v:7512$2435_Y + assign $0\main_dummy[23:0] [1] $or$ls180.v:7513$2436_Y + assign $0\main_dummy[23:0] [2] $or$ls180.v:7514$2437_Y + assign $0\main_dummy[23:0] [3] $or$ls180.v:7515$2438_Y + assign $0\main_dummy[23:0] [4] $or$ls180.v:7516$2439_Y + assign $0\main_dummy[23:0] [5] $or$ls180.v:7517$2440_Y + assign $0\main_dummy[23:0] [6] $or$ls180.v:7518$2441_Y + assign $0\main_dummy[23:0] [7] $or$ls180.v:7519$2442_Y + assign $0\main_dummy[23:0] [8] $or$ls180.v:7520$2443_Y + assign $0\main_dummy[23:0] [9] $or$ls180.v:7521$2444_Y + assign $0\main_dummy[23:0] [10] $or$ls180.v:7522$2445_Y + assign $0\main_dummy[23:0] [11] $or$ls180.v:7523$2446_Y + assign $0\main_dummy[23:0] [12] $or$ls180.v:7524$2447_Y + assign $0\main_dummy[23:0] [13] $or$ls180.v:7525$2448_Y + assign $0\main_dummy[23:0] [14] $or$ls180.v:7526$2449_Y + assign $0\main_dummy[23:0] [15] $or$ls180.v:7527$2450_Y + assign $0\main_dummy[23:0] [16] $or$ls180.v:7528$2451_Y + assign $0\main_dummy[23:0] [17] $or$ls180.v:7529$2452_Y + assign $0\main_dummy[23:0] [18] $or$ls180.v:7530$2453_Y + assign $0\main_dummy[23:0] [19] $or$ls180.v:7531$2454_Y + assign $0\main_dummy[23:0] [20] $or$ls180.v:7532$2455_Y + assign $0\main_dummy[23:0] [21] $or$ls180.v:7533$2456_Y + assign $0\main_dummy[23:0] [22] $or$ls180.v:7534$2457_Y + assign $0\main_dummy[23:0] [23] $or$ls180.v:7535$2458_Y assign $0\builder_converter0_state[0:0] \builder_converter0_next_state assign $0\builder_converter1_state[0:0] \builder_converter1_next_state assign $0\builder_converter2_state[0:0] \builder_converter2_next_state assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger - assign $0\main_interface0_ram_bus_ack[0:0] 1'0 - assign $0\main_interface1_ram_bus_ack[0:0] 1'0 - assign $0\main_interface2_ram_bus_ack[0:0] 1'0 - assign $0\main_interface3_ram_bus_ack[0:0] 1'0 + assign $0\main_ram_bus_ram_bus_ack[0:0] 1'0 assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] assign $0\main_sdram_postponer_req_o[0:0] 1'0 @@ -298108,14 +295085,14 @@ module \ls180 assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 - assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8187$2708_Y - assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8188$2709_Y - assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8189$2710_Y + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7981$2558_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7982$2559_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7983$2560_Y assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state - assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8223$2728_Y - assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8224$2740_Y + assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8017$2578_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8018$2590_Y assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 @@ -298125,11 +295102,11 @@ module \ls180 assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger - assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8382$2786_Y - assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8391$2789_Y + assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8176$2636_Y + assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8185$2639_Y assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state - assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8417$2791_Y - assign $0\spimaster_cs_n[0:0] $or$ls180.v:8426$2794_Y + assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8211$2641_Y + assign $0\spimaster_cs_n[0:0] $or$ls180.v:8220$2644_Y assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 @@ -298145,7 +295122,7 @@ module \ls180 assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state assign $0\builder_state[1:0] \builder_next_state - assign $0\builder_slave_sel_r[12:0] \builder_slave_sel + assign $0\builder_slave_sel_r[5:0] \builder_slave_sel assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re @@ -298240,182 +295217,161 @@ module \ls180 assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 assign $0\builder_multiregimpl16_regs0[0:0] \main_gpiotristateasic1_pads_i [15] assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 - attribute \src "ls180.v:7730.2-7732.5" - switch $or$ls180.v:7730$2600_Y - attribute \src "ls180.v:7730.6-7730.69" + attribute \src "ls180.v:7536.2-7538.5" + switch $or$ls180.v:7536$2459_Y + attribute \src "ls180.v:7536.6-7536.69" case 1'1 assign $0\main_converter0_dat_r[63:0] \main_interface0_converted_interface_dat_r case end - attribute \src "ls180.v:7734.2-7736.5" + attribute \src "ls180.v:7540.2-7542.5" switch \main_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:7734.6-7734.54" + attribute \src "ls180.v:7540.6-7540.54" case 1'1 assign $0\main_converter0_counter[0:0] \main_converter0_counter_converter0_next_value case end - attribute \src "ls180.v:7737.2-7740.5" + attribute \src "ls180.v:7543.2-7546.5" switch \main_converter0_reset - attribute \src "ls180.v:7737.6-7737.27" + attribute \src "ls180.v:7543.6-7543.27" case 1'1 assign $0\main_converter0_counter[0:0] 1'0 assign $0\builder_converter0_state[0:0] 1'0 case end - attribute \src "ls180.v:7741.2-7743.5" - switch $or$ls180.v:7741$2601_Y - attribute \src "ls180.v:7741.6-7741.69" + attribute \src "ls180.v:7547.2-7549.5" + switch $or$ls180.v:7547$2460_Y + attribute \src "ls180.v:7547.6-7547.69" case 1'1 assign $0\main_converter1_dat_r[63:0] \main_interface1_converted_interface_dat_r case end - attribute \src "ls180.v:7745.2-7747.5" + attribute \src "ls180.v:7551.2-7553.5" switch \main_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:7745.6-7745.54" + attribute \src "ls180.v:7551.6-7551.54" case 1'1 assign $0\main_converter1_counter[0:0] \main_converter1_counter_converter1_next_value case end - attribute \src "ls180.v:7748.2-7751.5" + attribute \src "ls180.v:7554.2-7557.5" switch \main_converter1_reset - attribute \src "ls180.v:7748.6-7748.27" + attribute \src "ls180.v:7554.6-7554.27" case 1'1 assign $0\main_converter1_counter[0:0] 1'0 assign $0\builder_converter1_state[0:0] 1'0 case end - attribute \src "ls180.v:7752.2-7754.5" - switch $or$ls180.v:7752$2602_Y - attribute \src "ls180.v:7752.6-7752.51" + attribute \src "ls180.v:7558.2-7560.5" + switch $or$ls180.v:7558$2461_Y + attribute \src "ls180.v:7558.6-7558.51" case 1'1 assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_converted_interface_dat_r case end - attribute \src "ls180.v:7756.2-7758.5" + attribute \src "ls180.v:7562.2-7564.5" switch \main_socbushandler_counter_converter2_next_value_ce - attribute \src "ls180.v:7756.6-7756.57" + attribute \src "ls180.v:7562.6-7562.57" case 1'1 assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter_converter2_next_value case end - attribute \src "ls180.v:7759.2-7762.5" + attribute \src "ls180.v:7565.2-7568.5" switch \main_socbushandler_reset - attribute \src "ls180.v:7759.6-7759.30" + attribute \src "ls180.v:7565.6-7565.30" case 1'1 assign $0\main_socbushandler_counter[0:0] 1'0 assign $0\builder_converter2_state[0:0] 1'0 case end - attribute \src "ls180.v:7763.2-7767.5" - switch $ne$ls180.v:7763$2603_Y - attribute \src "ls180.v:7763.6-7763.53" + attribute \src "ls180.v:7569.2-7573.5" + switch $ne$ls180.v:7569$2462_Y + attribute \src "ls180.v:7569.6-7569.53" case 1'1 - attribute \src "ls180.v:7764.3-7766.6" + attribute \src "ls180.v:7570.3-7572.6" switch \main_libresocsim_bus_error - attribute \src "ls180.v:7764.7-7764.33" + attribute \src "ls180.v:7570.7-7570.33" case 1'1 - assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7765$2604_Y + assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7571$2463_Y case end case end - attribute \src "ls180.v:7769.2-7771.5" - switch $and$ls180.v:7769$2607_Y - attribute \src "ls180.v:7769.6-7769.103" + attribute \src "ls180.v:7575.2-7577.5" + switch $and$ls180.v:7575$2466_Y + attribute \src "ls180.v:7575.6-7575.103" case 1'1 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7772.2-7780.5" + attribute \src "ls180.v:7578.2-7586.5" switch \main_libresocsim_en_storage - attribute \src "ls180.v:7772.6-7772.33" + attribute \src "ls180.v:7578.6-7578.33" case 1'1 - attribute \src "ls180.v:7773.3-7777.6" - switch $eq$ls180.v:7773$2608_Y - attribute \src "ls180.v:7773.7-7773.39" + attribute \src "ls180.v:7579.3-7583.6" + switch $eq$ls180.v:7579$2467_Y + attribute \src "ls180.v:7579.7-7579.39" case 1'1 assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage - attribute \src "ls180.v:7775.7-7775.11" + attribute \src "ls180.v:7581.7-7581.11" case - assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7776$2609_Y + assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7582$2468_Y end - attribute \src "ls180.v:7778.6-7778.10" + attribute \src "ls180.v:7584.6-7584.10" case assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage end - attribute \src "ls180.v:7781.2-7783.5" + attribute \src "ls180.v:7587.2-7589.5" switch \main_libresocsim_update_value_re - attribute \src "ls180.v:7781.6-7781.38" + attribute \src "ls180.v:7587.6-7587.38" case 1'1 assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value case end - attribute \src "ls180.v:7784.2-7786.5" + attribute \src "ls180.v:7590.2-7592.5" switch \main_libresocsim_zero_clear - attribute \src "ls180.v:7784.6-7784.33" + attribute \src "ls180.v:7590.6-7590.33" case 1'1 assign $0\main_libresocsim_zero_pending[0:0] 1'0 case end - attribute \src "ls180.v:7788.2-7790.5" - switch $and$ls180.v:7788$2611_Y - attribute \src "ls180.v:7788.6-7788.76" + attribute \src "ls180.v:7594.2-7596.5" + switch $and$ls180.v:7594$2470_Y + attribute \src "ls180.v:7594.6-7594.76" case 1'1 assign $0\main_libresocsim_zero_pending[0:0] 1'1 case end - attribute \src "ls180.v:7792.2-7794.5" - switch $and$ls180.v:7792$2614_Y - attribute \src "ls180.v:7792.6-7792.100" - case 1'1 - assign $0\main_interface0_ram_bus_ack[0:0] 1'1 - case - end - attribute \src "ls180.v:7796.2-7798.5" - switch $and$ls180.v:7796$2617_Y - attribute \src "ls180.v:7796.6-7796.100" + attribute \src "ls180.v:7598.2-7600.5" + switch $and$ls180.v:7598$2473_Y + attribute \src "ls180.v:7598.6-7598.91" case 1'1 - assign $0\main_interface1_ram_bus_ack[0:0] 1'1 + assign $0\main_ram_bus_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7800.2-7802.5" - switch $and$ls180.v:7800$2620_Y - attribute \src "ls180.v:7800.6-7800.100" - case 1'1 - assign $0\main_interface2_ram_bus_ack[0:0] 1'1 - case - end - attribute \src "ls180.v:7804.2-7806.5" - switch $and$ls180.v:7804$2623_Y - attribute \src "ls180.v:7804.6-7804.100" - case 1'1 - assign $0\main_interface3_ram_bus_ack[0:0] 1'1 - case - end - attribute \src "ls180.v:7809.2-7811.5" + attribute \src "ls180.v:7603.2-7605.5" switch \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:7809.6-7809.37" + attribute \src "ls180.v:7603.6-7603.37" case 1'1 assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata case end - attribute \src "ls180.v:7812.2-7816.5" - switch $and$ls180.v:7812$2625_Y - attribute \src "ls180.v:7812.6-7812.57" + attribute \src "ls180.v:7606.2-7610.5" + switch $and$ls180.v:7606$2475_Y + attribute \src "ls180.v:7606.6-7606.57" case 1'1 - assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7813$2626_Y - attribute \src "ls180.v:7814.6-7814.10" + assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7607$2476_Y + attribute \src "ls180.v:7608.6-7608.10" case assign $0\main_sdram_timer_count1[9:0] 10'1100001101 end - attribute \src "ls180.v:7818.2-7824.5" + attribute \src "ls180.v:7612.2-7618.5" switch \main_sdram_postponer_req_i - attribute \src "ls180.v:7818.6-7818.32" + attribute \src "ls180.v:7612.6-7612.32" case 1'1 - assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7819$2627_Y - attribute \src "ls180.v:7820.3-7823.6" - switch $eq$ls180.v:7820$2628_Y - attribute \src "ls180.v:7820.7-7820.43" + assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7613$2477_Y + attribute \src "ls180.v:7614.3-7617.6" + switch $eq$ls180.v:7614$2478_Y + attribute \src "ls180.v:7614.7-7614.43" case 1'1 assign $0\main_sdram_postponer_count[0:0] 1'0 assign $0\main_sdram_postponer_req_o[0:0] 1'1 @@ -298423,30 +295379,30 @@ module \ls180 end case end - attribute \src "ls180.v:7825.2-7833.5" + attribute \src "ls180.v:7619.2-7627.5" switch \main_sdram_sequencer_start0 - attribute \src "ls180.v:7825.6-7825.33" + attribute \src "ls180.v:7619.6-7619.33" case 1'1 assign $0\main_sdram_sequencer_count[0:0] 1'0 - attribute \src "ls180.v:7827.6-7827.10" + attribute \src "ls180.v:7621.6-7621.10" case - attribute \src "ls180.v:7828.3-7832.6" + attribute \src "ls180.v:7622.3-7626.6" switch \main_sdram_sequencer_done1 - attribute \src "ls180.v:7828.7-7828.33" + attribute \src "ls180.v:7622.7-7622.33" case 1'1 - attribute \src "ls180.v:7829.4-7831.7" - switch $ne$ls180.v:7829$2629_Y - attribute \src "ls180.v:7829.8-7829.44" + attribute \src "ls180.v:7623.4-7625.7" + switch $ne$ls180.v:7623$2479_Y + attribute \src "ls180.v:7623.8-7623.44" case 1'1 - assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7830$2630_Y + assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7624$2480_Y case end case end end - attribute \src "ls180.v:7840.2-7846.5" - switch $and$ls180.v:7840$2632_Y - attribute \src "ls180.v:7840.6-7840.76" + attribute \src "ls180.v:7634.2-7640.5" + switch $and$ls180.v:7634$2482_Y + attribute \src "ls180.v:7634.6-7634.76" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -298455,9 +295411,9 @@ module \ls180 assign $0\main_sdram_cmd_payload_we[0:0] 1'1 case end - attribute \src "ls180.v:7847.2-7853.5" - switch $eq$ls180.v:7847$2633_Y - attribute \src "ls180.v:7847.6-7847.44" + attribute \src "ls180.v:7641.2-7647.5" + switch $eq$ls180.v:7641$2483_Y + attribute \src "ls180.v:7641.6-7641.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -298466,9 +295422,9 @@ module \ls180 assign $0\main_sdram_cmd_payload_we[0:0] 1'0 case end - attribute \src "ls180.v:7854.2-7861.5" - switch $eq$ls180.v:7854$2634_Y - attribute \src "ls180.v:7854.6-7854.44" + attribute \src "ls180.v:7648.2-7655.5" + switch $eq$ls180.v:7648$2484_Y + attribute \src "ls180.v:7648.6-7648.44" case 1'1 assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 @@ -298478,83 +295434,83 @@ module \ls180 assign $0\main_sdram_sequencer_done1[0:0] 1'1 case end - attribute \src "ls180.v:7862.2-7872.5" - switch $eq$ls180.v:7862$2635_Y - attribute \src "ls180.v:7862.6-7862.44" + attribute \src "ls180.v:7656.2-7666.5" + switch $eq$ls180.v:7656$2485_Y + attribute \src "ls180.v:7656.6-7656.44" case 1'1 assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - attribute \src "ls180.v:7864.6-7864.10" + attribute \src "ls180.v:7658.6-7658.10" case - attribute \src "ls180.v:7865.3-7871.6" - switch $ne$ls180.v:7865$2636_Y - attribute \src "ls180.v:7865.7-7865.45" + attribute \src "ls180.v:7659.3-7665.6" + switch $ne$ls180.v:7659$2486_Y + attribute \src "ls180.v:7659.7-7659.45" case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7866$2637_Y - attribute \src "ls180.v:7867.7-7867.11" + assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7660$2487_Y + attribute \src "ls180.v:7661.7-7661.11" case - attribute \src "ls180.v:7868.4-7870.7" + attribute \src "ls180.v:7662.4-7664.7" switch \main_sdram_sequencer_start1 - attribute \src "ls180.v:7868.8-7868.35" + attribute \src "ls180.v:7662.8-7662.35" case 1'1 assign $0\main_sdram_sequencer_counter[3:0] 4'0001 case end end end - attribute \src "ls180.v:7874.2-7881.5" + attribute \src "ls180.v:7668.2-7675.5" switch \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:7874.6-7874.39" + attribute \src "ls180.v:7668.6-7668.39" case 1'1 assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - attribute \src "ls180.v:7876.6-7876.10" + attribute \src "ls180.v:7670.6-7670.10" case - attribute \src "ls180.v:7877.3-7880.6" + attribute \src "ls180.v:7671.3-7674.6" switch \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:7877.7-7877.39" + attribute \src "ls180.v:7671.7-7671.39" case 1'1 assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7882.2-7884.5" - switch $and$ls180.v:7882$2640_Y - attribute \src "ls180.v:7882.6-7882.191" + attribute \src "ls180.v:7676.2-7678.5" + switch $and$ls180.v:7676$2490_Y + attribute \src "ls180.v:7676.6-7676.191" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7883$2641_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7677$2491_Y case end - attribute \src "ls180.v:7885.2-7887.5" + attribute \src "ls180.v:7679.2-7681.5" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7885.6-7885.58" + attribute \src "ls180.v:7679.6-7679.58" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7886$2642_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7680$2492_Y case end - attribute \src "ls180.v:7888.2-7896.5" - switch $and$ls180.v:7888$2645_Y - attribute \src "ls180.v:7888.6-7888.191" + attribute \src "ls180.v:7682.2-7690.5" + switch $and$ls180.v:7682$2495_Y + attribute \src "ls180.v:7682.6-7682.191" case 1'1 - attribute \src "ls180.v:7889.3-7891.6" - switch $not$ls180.v:7889$2646_Y - attribute \src "ls180.v:7889.7-7889.62" + attribute \src "ls180.v:7683.3-7685.6" + switch $not$ls180.v:7683$2496_Y + attribute \src "ls180.v:7683.7-7683.62" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7890$2647_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7684$2497_Y case end - attribute \src "ls180.v:7892.6-7892.10" + attribute \src "ls180.v:7686.6-7686.10" case - attribute \src "ls180.v:7893.3-7895.6" + attribute \src "ls180.v:7687.3-7689.6" switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7893.7-7893.59" + attribute \src "ls180.v:7687.7-7687.59" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7894$2648_Y + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7688$2498_Y case end end - attribute \src "ls180.v:7897.2-7903.5" - switch $or$ls180.v:7897$2650_Y - attribute \src "ls180.v:7897.6-7897.108" + attribute \src "ls180.v:7691.2-7697.5" + switch $or$ls180.v:7691$2500_Y + attribute \src "ls180.v:7691.6-7691.108" case 1'1 assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first @@ -298563,27 +295519,27 @@ module \ls180 assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7904.2-7918.5" + attribute \src "ls180.v:7698.2-7712.5" switch \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:7904.6-7904.43" + attribute \src "ls180.v:7698.6-7698.43" case 1'1 assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7906.3-7910.6" + attribute \src "ls180.v:7700.3-7704.6" switch 1'0 - attribute \src "ls180.v:7908.7-7908.11" + attribute \src "ls180.v:7702.7-7702.11" case assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7911.6-7911.10" + attribute \src "ls180.v:7705.6-7705.10" case - attribute \src "ls180.v:7912.3-7917.6" - switch $not$ls180.v:7912$2651_Y - attribute \src "ls180.v:7912.7-7912.47" + attribute \src "ls180.v:7706.3-7711.6" + switch $not$ls180.v:7706$2501_Y + attribute \src "ls180.v:7706.7-7706.47" case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7913$2652_Y - attribute \src "ls180.v:7914.4-7916.7" - switch $eq$ls180.v:7914$2653_Y - attribute \src "ls180.v:7914.8-7914.55" + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7707$2502_Y + attribute \src "ls180.v:7708.4-7710.7" + switch $eq$ls180.v:7708$2503_Y + attribute \src "ls180.v:7708.8-7708.55" case 1'1 assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 case @@ -298591,60 +295547,60 @@ module \ls180 case end end - attribute \src "ls180.v:7920.2-7927.5" + attribute \src "ls180.v:7714.2-7721.5" switch \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:7920.6-7920.39" + attribute \src "ls180.v:7714.6-7714.39" case 1'1 assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - attribute \src "ls180.v:7922.6-7922.10" + attribute \src "ls180.v:7716.6-7716.10" case - attribute \src "ls180.v:7923.3-7926.6" + attribute \src "ls180.v:7717.3-7720.6" switch \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:7923.7-7923.39" + attribute \src "ls180.v:7717.7-7717.39" case 1'1 assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7928.2-7930.5" - switch $and$ls180.v:7928$2656_Y - attribute \src "ls180.v:7928.6-7928.191" + attribute \src "ls180.v:7722.2-7724.5" + switch $and$ls180.v:7722$2506_Y + attribute \src "ls180.v:7722.6-7722.191" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7929$2657_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7723$2507_Y case end - attribute \src "ls180.v:7931.2-7933.5" + attribute \src "ls180.v:7725.2-7727.5" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7931.6-7931.58" + attribute \src "ls180.v:7725.6-7725.58" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7932$2658_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7726$2508_Y case end - attribute \src "ls180.v:7934.2-7942.5" - switch $and$ls180.v:7934$2661_Y - attribute \src "ls180.v:7934.6-7934.191" + attribute \src "ls180.v:7728.2-7736.5" + switch $and$ls180.v:7728$2511_Y + attribute \src "ls180.v:7728.6-7728.191" case 1'1 - attribute \src "ls180.v:7935.3-7937.6" - switch $not$ls180.v:7935$2662_Y - attribute \src "ls180.v:7935.7-7935.62" + attribute \src "ls180.v:7729.3-7731.6" + switch $not$ls180.v:7729$2512_Y + attribute \src "ls180.v:7729.7-7729.62" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7936$2663_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7730$2513_Y case end - attribute \src "ls180.v:7938.6-7938.10" + attribute \src "ls180.v:7732.6-7732.10" case - attribute \src "ls180.v:7939.3-7941.6" + attribute \src "ls180.v:7733.3-7735.6" switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7939.7-7939.59" + attribute \src "ls180.v:7733.7-7733.59" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7940$2664_Y + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7734$2514_Y case end end - attribute \src "ls180.v:7943.2-7949.5" - switch $or$ls180.v:7943$2666_Y - attribute \src "ls180.v:7943.6-7943.108" + attribute \src "ls180.v:7737.2-7743.5" + switch $or$ls180.v:7737$2516_Y + attribute \src "ls180.v:7737.6-7737.108" case 1'1 assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first @@ -298653,27 +295609,27 @@ module \ls180 assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7950.2-7964.5" + attribute \src "ls180.v:7744.2-7758.5" switch \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:7950.6-7950.43" + attribute \src "ls180.v:7744.6-7744.43" case 1'1 assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7952.3-7956.6" + attribute \src "ls180.v:7746.3-7750.6" switch 1'0 - attribute \src "ls180.v:7954.7-7954.11" + attribute \src "ls180.v:7748.7-7748.11" case assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7957.6-7957.10" + attribute \src "ls180.v:7751.6-7751.10" case - attribute \src "ls180.v:7958.3-7963.6" - switch $not$ls180.v:7958$2667_Y - attribute \src "ls180.v:7958.7-7958.47" + attribute \src "ls180.v:7752.3-7757.6" + switch $not$ls180.v:7752$2517_Y + attribute \src "ls180.v:7752.7-7752.47" case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7959$2668_Y - attribute \src "ls180.v:7960.4-7962.7" - switch $eq$ls180.v:7960$2669_Y - attribute \src "ls180.v:7960.8-7960.55" + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7753$2518_Y + attribute \src "ls180.v:7754.4-7756.7" + switch $eq$ls180.v:7754$2519_Y + attribute \src "ls180.v:7754.8-7754.55" case 1'1 assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 case @@ -298681,60 +295637,60 @@ module \ls180 case end end - attribute \src "ls180.v:7966.2-7973.5" + attribute \src "ls180.v:7760.2-7767.5" switch \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:7966.6-7966.39" + attribute \src "ls180.v:7760.6-7760.39" case 1'1 assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - attribute \src "ls180.v:7968.6-7968.10" + attribute \src "ls180.v:7762.6-7762.10" case - attribute \src "ls180.v:7969.3-7972.6" + attribute \src "ls180.v:7763.3-7766.6" switch \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:7969.7-7969.39" + attribute \src "ls180.v:7763.7-7763.39" case 1'1 assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7974.2-7976.5" - switch $and$ls180.v:7974$2672_Y - attribute \src "ls180.v:7974.6-7974.191" + attribute \src "ls180.v:7768.2-7770.5" + switch $and$ls180.v:7768$2522_Y + attribute \src "ls180.v:7768.6-7768.191" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7975$2673_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7769$2523_Y case end - attribute \src "ls180.v:7977.2-7979.5" + attribute \src "ls180.v:7771.2-7773.5" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7977.6-7977.58" + attribute \src "ls180.v:7771.6-7771.58" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7978$2674_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7772$2524_Y case end - attribute \src "ls180.v:7980.2-7988.5" - switch $and$ls180.v:7980$2677_Y - attribute \src "ls180.v:7980.6-7980.191" + attribute \src "ls180.v:7774.2-7782.5" + switch $and$ls180.v:7774$2527_Y + attribute \src "ls180.v:7774.6-7774.191" case 1'1 - attribute \src "ls180.v:7981.3-7983.6" - switch $not$ls180.v:7981$2678_Y - attribute \src "ls180.v:7981.7-7981.62" + attribute \src "ls180.v:7775.3-7777.6" + switch $not$ls180.v:7775$2528_Y + attribute \src "ls180.v:7775.7-7775.62" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7982$2679_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7776$2529_Y case end - attribute \src "ls180.v:7984.6-7984.10" + attribute \src "ls180.v:7778.6-7778.10" case - attribute \src "ls180.v:7985.3-7987.6" + attribute \src "ls180.v:7779.3-7781.6" switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7985.7-7985.59" + attribute \src "ls180.v:7779.7-7779.59" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7986$2680_Y + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7780$2530_Y case end end - attribute \src "ls180.v:7989.2-7995.5" - switch $or$ls180.v:7989$2682_Y - attribute \src "ls180.v:7989.6-7989.108" + attribute \src "ls180.v:7783.2-7789.5" + switch $or$ls180.v:7783$2532_Y + attribute \src "ls180.v:7783.6-7783.108" case 1'1 assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first @@ -298743,27 +295699,27 @@ module \ls180 assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7996.2-8010.5" + attribute \src "ls180.v:7790.2-7804.5" switch \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:7996.6-7996.43" + attribute \src "ls180.v:7790.6-7790.43" case 1'1 assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7998.3-8002.6" + attribute \src "ls180.v:7792.3-7796.6" switch 1'0 - attribute \src "ls180.v:8000.7-8000.11" + attribute \src "ls180.v:7794.7-7794.11" case assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:8003.6-8003.10" + attribute \src "ls180.v:7797.6-7797.10" case - attribute \src "ls180.v:8004.3-8009.6" - switch $not$ls180.v:8004$2683_Y - attribute \src "ls180.v:8004.7-8004.47" + attribute \src "ls180.v:7798.3-7803.6" + switch $not$ls180.v:7798$2533_Y + attribute \src "ls180.v:7798.7-7798.47" case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:8005$2684_Y - attribute \src "ls180.v:8006.4-8008.7" - switch $eq$ls180.v:8006$2685_Y - attribute \src "ls180.v:8006.8-8006.55" + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7799$2534_Y + attribute \src "ls180.v:7800.4-7802.7" + switch $eq$ls180.v:7800$2535_Y + attribute \src "ls180.v:7800.8-7800.55" case 1'1 assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 case @@ -298771,60 +295727,60 @@ module \ls180 case end end - attribute \src "ls180.v:8012.2-8019.5" + attribute \src "ls180.v:7806.2-7813.5" switch \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:8012.6-8012.39" + attribute \src "ls180.v:7806.6-7806.39" case 1'1 assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - attribute \src "ls180.v:8014.6-8014.10" + attribute \src "ls180.v:7808.6-7808.10" case - attribute \src "ls180.v:8015.3-8018.6" + attribute \src "ls180.v:7809.3-7812.6" switch \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:8015.7-8015.39" + attribute \src "ls180.v:7809.7-7809.39" case 1'1 assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:8020.2-8022.5" - switch $and$ls180.v:8020$2688_Y - attribute \src "ls180.v:8020.6-8020.191" + attribute \src "ls180.v:7814.2-7816.5" + switch $and$ls180.v:7814$2538_Y + attribute \src "ls180.v:7814.6-7814.191" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:8021$2689_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7815$2539_Y case end - attribute \src "ls180.v:8023.2-8025.5" + attribute \src "ls180.v:7817.2-7819.5" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:8023.6-8023.58" + attribute \src "ls180.v:7817.6-7817.58" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:8024$2690_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7818$2540_Y case end - attribute \src "ls180.v:8026.2-8034.5" - switch $and$ls180.v:8026$2693_Y - attribute \src "ls180.v:8026.6-8026.191" + attribute \src "ls180.v:7820.2-7828.5" + switch $and$ls180.v:7820$2543_Y + attribute \src "ls180.v:7820.6-7820.191" case 1'1 - attribute \src "ls180.v:8027.3-8029.6" - switch $not$ls180.v:8027$2694_Y - attribute \src "ls180.v:8027.7-8027.62" + attribute \src "ls180.v:7821.3-7823.6" + switch $not$ls180.v:7821$2544_Y + attribute \src "ls180.v:7821.7-7821.62" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:8028$2695_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7822$2545_Y case end - attribute \src "ls180.v:8030.6-8030.10" + attribute \src "ls180.v:7824.6-7824.10" case - attribute \src "ls180.v:8031.3-8033.6" + attribute \src "ls180.v:7825.3-7827.6" switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:8031.7-8031.59" + attribute \src "ls180.v:7825.7-7825.59" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:8032$2696_Y + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7826$2546_Y case end end - attribute \src "ls180.v:8035.2-8041.5" - switch $or$ls180.v:8035$2698_Y - attribute \src "ls180.v:8035.6-8035.108" + attribute \src "ls180.v:7829.2-7835.5" + switch $or$ls180.v:7829$2548_Y + attribute \src "ls180.v:7829.6-7829.108" case 1'1 assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first @@ -298833,27 +295789,27 @@ module \ls180 assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:8042.2-8056.5" + attribute \src "ls180.v:7836.2-7850.5" switch \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:8042.6-8042.43" + attribute \src "ls180.v:7836.6-7836.43" case 1'1 assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:8044.3-8048.6" + attribute \src "ls180.v:7838.3-7842.6" switch 1'0 - attribute \src "ls180.v:8046.7-8046.11" + attribute \src "ls180.v:7840.7-7840.11" case assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:8049.6-8049.10" + attribute \src "ls180.v:7843.6-7843.10" case - attribute \src "ls180.v:8050.3-8055.6" - switch $not$ls180.v:8050$2699_Y - attribute \src "ls180.v:8050.7-8050.47" + attribute \src "ls180.v:7844.3-7849.6" + switch $not$ls180.v:7844$2549_Y + attribute \src "ls180.v:7844.7-7844.47" case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:8051$2700_Y - attribute \src "ls180.v:8052.4-8054.7" - switch $eq$ls180.v:8052$2701_Y - attribute \src "ls180.v:8052.8-8052.55" + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7845$2550_Y + attribute \src "ls180.v:7846.4-7848.7" + switch $eq$ls180.v:7846$2551_Y + attribute \src "ls180.v:7846.8-7846.55" case 1'1 assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 case @@ -298861,61 +295817,61 @@ module \ls180 case end end - attribute \src "ls180.v:8058.2-8064.5" - switch $not$ls180.v:8058$2702_Y - attribute \src "ls180.v:8058.6-8058.23" + attribute \src "ls180.v:7852.2-7858.5" + switch $not$ls180.v:7852$2552_Y + attribute \src "ls180.v:7852.6-7852.23" case 1'1 assign $0\main_sdram_time0[4:0] 5'11111 - attribute \src "ls180.v:8060.6-8060.10" + attribute \src "ls180.v:7854.6-7854.10" case - attribute \src "ls180.v:8061.3-8063.6" - switch $not$ls180.v:8061$2703_Y - attribute \src "ls180.v:8061.7-8061.30" + attribute \src "ls180.v:7855.3-7857.6" + switch $not$ls180.v:7855$2553_Y + attribute \src "ls180.v:7855.7-7855.30" case 1'1 - assign $0\main_sdram_time0[4:0] $sub$ls180.v:8062$2704_Y + assign $0\main_sdram_time0[4:0] $sub$ls180.v:7856$2554_Y case end end - attribute \src "ls180.v:8065.2-8071.5" - switch $not$ls180.v:8065$2705_Y - attribute \src "ls180.v:8065.6-8065.23" + attribute \src "ls180.v:7859.2-7865.5" + switch $not$ls180.v:7859$2555_Y + attribute \src "ls180.v:7859.6-7859.23" case 1'1 assign $0\main_sdram_time1[3:0] 4'1111 - attribute \src "ls180.v:8067.6-8067.10" + attribute \src "ls180.v:7861.6-7861.10" case - attribute \src "ls180.v:8068.3-8070.6" - switch $not$ls180.v:8068$2706_Y - attribute \src "ls180.v:8068.7-8068.30" + attribute \src "ls180.v:7862.3-7864.6" + switch $not$ls180.v:7862$2556_Y + attribute \src "ls180.v:7862.7-7862.30" case 1'1 - assign $0\main_sdram_time1[3:0] $sub$ls180.v:8069$2707_Y + assign $0\main_sdram_time1[3:0] $sub$ls180.v:7863$2557_Y case end end - attribute \src "ls180.v:8072.2-8127.5" + attribute \src "ls180.v:7866.2-7921.5" switch \main_sdram_choose_cmd_ce - attribute \src "ls180.v:8072.6-8072.30" + attribute \src "ls180.v:7866.6-7866.30" case 1'1 - attribute \src "ls180.v:8073.3-8126.10" + attribute \src "ls180.v:7867.3-7920.10" switch \main_sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:8075.5-8085.8" + attribute \src "ls180.v:7869.5-7879.8" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:8075.9-8075.41" + attribute \src "ls180.v:7869.9-7869.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:8077.9-8077.13" + attribute \src "ls180.v:7871.9-7871.13" case - attribute \src "ls180.v:8078.6-8084.9" + attribute \src "ls180.v:7872.6-7878.9" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:8078.10-8078.42" + attribute \src "ls180.v:7872.10-7872.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:8080.10-8080.14" + attribute \src "ls180.v:7874.10-7874.14" case - attribute \src "ls180.v:8081.7-8083.10" + attribute \src "ls180.v:7875.7-7877.10" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:8081.11-8081.43" + attribute \src "ls180.v:7875.11-7875.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 case @@ -298924,23 +295880,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:8088.5-8098.8" + attribute \src "ls180.v:7882.5-7892.8" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:8088.9-8088.41" + attribute \src "ls180.v:7882.9-7882.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:8090.9-8090.13" + attribute \src "ls180.v:7884.9-7884.13" case - attribute \src "ls180.v:8091.6-8097.9" + attribute \src "ls180.v:7885.6-7891.9" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:8091.10-8091.42" + attribute \src "ls180.v:7885.10-7885.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:8093.10-8093.14" + attribute \src "ls180.v:7887.10-7887.14" case - attribute \src "ls180.v:8094.7-8096.10" + attribute \src "ls180.v:7888.7-7890.10" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:8094.11-8094.43" + attribute \src "ls180.v:7888.11-7888.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 case @@ -298949,23 +295905,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:8101.5-8111.8" + attribute \src "ls180.v:7895.5-7905.8" switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:8101.9-8101.41" + attribute \src "ls180.v:7895.9-7895.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:8103.9-8103.13" + attribute \src "ls180.v:7897.9-7897.13" case - attribute \src "ls180.v:8104.6-8110.9" + attribute \src "ls180.v:7898.6-7904.9" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:8104.10-8104.42" + attribute \src "ls180.v:7898.10-7898.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:8106.10-8106.14" + attribute \src "ls180.v:7900.10-7900.14" case - attribute \src "ls180.v:8107.7-8109.10" + attribute \src "ls180.v:7901.7-7903.10" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:8107.11-8107.43" + attribute \src "ls180.v:7901.11-7901.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 case @@ -298974,23 +295930,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:8114.5-8124.8" + attribute \src "ls180.v:7908.5-7918.8" switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:8114.9-8114.41" + attribute \src "ls180.v:7908.9-7908.41" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:8116.9-8116.13" + attribute \src "ls180.v:7910.9-7910.13" case - attribute \src "ls180.v:8117.6-8123.9" + attribute \src "ls180.v:7911.6-7917.9" switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:8117.10-8117.42" + attribute \src "ls180.v:7911.10-7911.42" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:8119.10-8119.14" + attribute \src "ls180.v:7913.10-7913.14" case - attribute \src "ls180.v:8120.7-8122.10" + attribute \src "ls180.v:7914.7-7916.10" switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:8120.11-8120.43" + attribute \src "ls180.v:7914.11-7914.43" case 1'1 assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 case @@ -299001,31 +295957,31 @@ module \ls180 end case end - attribute \src "ls180.v:8128.2-8183.5" + attribute \src "ls180.v:7922.2-7977.5" switch \main_sdram_choose_req_ce - attribute \src "ls180.v:8128.6-8128.30" + attribute \src "ls180.v:7922.6-7922.30" case 1'1 - attribute \src "ls180.v:8129.3-8182.10" + attribute \src "ls180.v:7923.3-7976.10" switch \main_sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:8131.5-8141.8" + attribute \src "ls180.v:7925.5-7935.8" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:8131.9-8131.41" + attribute \src "ls180.v:7925.9-7925.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:8133.9-8133.13" + attribute \src "ls180.v:7927.9-7927.13" case - attribute \src "ls180.v:8134.6-8140.9" + attribute \src "ls180.v:7928.6-7934.9" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:8134.10-8134.42" + attribute \src "ls180.v:7928.10-7928.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:8136.10-8136.14" + attribute \src "ls180.v:7930.10-7930.14" case - attribute \src "ls180.v:8137.7-8139.10" + attribute \src "ls180.v:7931.7-7933.10" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:8137.11-8137.43" + attribute \src "ls180.v:7931.11-7931.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 case @@ -299034,23 +295990,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:8144.5-8154.8" + attribute \src "ls180.v:7938.5-7948.8" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:8144.9-8144.41" + attribute \src "ls180.v:7938.9-7938.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:8146.9-8146.13" + attribute \src "ls180.v:7940.9-7940.13" case - attribute \src "ls180.v:8147.6-8153.9" + attribute \src "ls180.v:7941.6-7947.9" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:8147.10-8147.42" + attribute \src "ls180.v:7941.10-7941.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:8149.10-8149.14" + attribute \src "ls180.v:7943.10-7943.14" case - attribute \src "ls180.v:8150.7-8152.10" + attribute \src "ls180.v:7944.7-7946.10" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:8150.11-8150.43" + attribute \src "ls180.v:7944.11-7944.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 case @@ -299059,23 +296015,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:8157.5-8167.8" + attribute \src "ls180.v:7951.5-7961.8" switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:8157.9-8157.41" + attribute \src "ls180.v:7951.9-7951.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:8159.9-8159.13" + attribute \src "ls180.v:7953.9-7953.13" case - attribute \src "ls180.v:8160.6-8166.9" + attribute \src "ls180.v:7954.6-7960.9" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:8160.10-8160.42" + attribute \src "ls180.v:7954.10-7954.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:8162.10-8162.14" + attribute \src "ls180.v:7956.10-7956.14" case - attribute \src "ls180.v:8163.7-8165.10" + attribute \src "ls180.v:7957.7-7959.10" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:8163.11-8163.43" + attribute \src "ls180.v:7957.11-7957.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 case @@ -299084,23 +296040,23 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:8170.5-8180.8" + attribute \src "ls180.v:7964.5-7974.8" switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:8170.9-8170.41" + attribute \src "ls180.v:7964.9-7964.41" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:8172.9-8172.13" + attribute \src "ls180.v:7966.9-7966.13" case - attribute \src "ls180.v:8173.6-8179.9" + attribute \src "ls180.v:7967.6-7973.9" switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:8173.10-8173.42" + attribute \src "ls180.v:7967.10-7967.42" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:8175.10-8175.14" + attribute \src "ls180.v:7969.10-7969.14" case - attribute \src "ls180.v:8176.7-8178.10" + attribute \src "ls180.v:7970.7-7972.10" switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:8176.11-8176.43" + attribute \src "ls180.v:7970.11-7970.43" case 1'1 assign $0\main_sdram_choose_req_grant[1:0] 2'10 case @@ -299111,28 +296067,28 @@ module \ls180 end case end - attribute \src "ls180.v:8192.2-8206.5" + attribute \src "ls180.v:7986.2-8000.5" switch \main_sdram_tccdcon_valid - attribute \src "ls180.v:8192.6-8192.30" + attribute \src "ls180.v:7986.6-7986.30" case 1'1 assign $0\main_sdram_tccdcon_count[0:0] 1'0 - attribute \src "ls180.v:8194.3-8198.6" + attribute \src "ls180.v:7988.3-7992.6" switch 1'1 - attribute \src "ls180.v:8194.7-8194.11" + attribute \src "ls180.v:7988.7-7988.11" case 1'1 assign $0\main_sdram_tccdcon_ready[0:0] 1'1 case end - attribute \src "ls180.v:8199.6-8199.10" + attribute \src "ls180.v:7993.6-7993.10" case - attribute \src "ls180.v:8200.3-8205.6" - switch $not$ls180.v:8200$2711_Y - attribute \src "ls180.v:8200.7-8200.34" + attribute \src "ls180.v:7994.3-7999.6" + switch $not$ls180.v:7994$2561_Y + attribute \src "ls180.v:7994.7-7994.34" case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8201$2712_Y - attribute \src "ls180.v:8202.4-8204.7" - switch $eq$ls180.v:8202$2713_Y - attribute \src "ls180.v:8202.8-8202.42" + assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7995$2562_Y + attribute \src "ls180.v:7996.4-7998.7" + switch $eq$ls180.v:7996$2563_Y + attribute \src "ls180.v:7996.8-7996.42" case 1'1 assign $0\main_sdram_tccdcon_ready[0:0] 1'1 case @@ -299140,27 +296096,27 @@ module \ls180 case end end - attribute \src "ls180.v:8207.2-8221.5" + attribute \src "ls180.v:8001.2-8015.5" switch \main_sdram_twtrcon_valid - attribute \src "ls180.v:8207.6-8207.30" + attribute \src "ls180.v:8001.6-8001.30" case 1'1 assign $0\main_sdram_twtrcon_count[2:0] 3'100 - attribute \src "ls180.v:8209.3-8213.6" + attribute \src "ls180.v:8003.3-8007.6" switch 1'0 - attribute \src "ls180.v:8211.7-8211.11" + attribute \src "ls180.v:8005.7-8005.11" case assign $0\main_sdram_twtrcon_ready[0:0] 1'0 end - attribute \src "ls180.v:8214.6-8214.10" + attribute \src "ls180.v:8008.6-8008.10" case - attribute \src "ls180.v:8215.3-8220.6" - switch $not$ls180.v:8215$2714_Y - attribute \src "ls180.v:8215.7-8215.34" + attribute \src "ls180.v:8009.3-8014.6" + switch $not$ls180.v:8009$2564_Y + attribute \src "ls180.v:8009.7-8009.34" case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8216$2715_Y - attribute \src "ls180.v:8217.4-8219.7" - switch $eq$ls180.v:8217$2716_Y - attribute \src "ls180.v:8217.8-8217.42" + assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8010$2565_Y + attribute \src "ls180.v:8011.4-8013.7" + switch $eq$ls180.v:8011$2566_Y + attribute \src "ls180.v:8011.8-8011.42" case 1'1 assign $0\main_sdram_twtrcon_ready[0:0] 1'1 case @@ -299168,81 +296124,81 @@ module \ls180 case end end - attribute \src "ls180.v:8228.2-8230.5" - switch $or$ls180.v:8228$2741_Y - attribute \src "ls180.v:8228.6-8228.50" + attribute \src "ls180.v:8022.2-8024.5" + switch $or$ls180.v:8022$2591_Y + attribute \src "ls180.v:8022.6-8022.50" case 1'1 assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r case end - attribute \src "ls180.v:8232.2-8234.5" + attribute \src "ls180.v:8026.2-8028.5" switch \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:8232.6-8232.52" + attribute \src "ls180.v:8026.6-8026.52" case 1'1 assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value case end - attribute \src "ls180.v:8235.2-8238.5" + attribute \src "ls180.v:8029.2-8032.5" switch \main_converter_reset - attribute \src "ls180.v:8235.6-8235.26" + attribute \src "ls180.v:8029.6-8029.26" case 1'1 assign $0\main_converter_counter[0:0] 1'0 assign $0\builder_converter_state[0:0] 1'0 case end - attribute \src "ls180.v:8239.2-8249.5" + attribute \src "ls180.v:8033.2-8043.5" switch \main_litedram_wb_ack - attribute \src "ls180.v:8239.6-8239.26" + attribute \src "ls180.v:8033.6-8033.26" case 1'1 assign $0\main_cmd_consumed[0:0] 1'0 assign $0\main_wdata_consumed[0:0] 1'0 - attribute \src "ls180.v:8242.6-8242.10" + attribute \src "ls180.v:8036.6-8036.10" case - attribute \src "ls180.v:8243.3-8245.6" - switch $and$ls180.v:8243$2742_Y - attribute \src "ls180.v:8243.7-8243.50" + attribute \src "ls180.v:8037.3-8039.6" + switch $and$ls180.v:8037$2592_Y + attribute \src "ls180.v:8037.7-8037.50" case 1'1 assign $0\main_cmd_consumed[0:0] 1'1 case end - attribute \src "ls180.v:8246.3-8248.6" - switch $and$ls180.v:8246$2743_Y - attribute \src "ls180.v:8246.7-8246.54" + attribute \src "ls180.v:8040.3-8042.6" + switch $and$ls180.v:8040$2593_Y + attribute \src "ls180.v:8040.7-8040.54" case 1'1 assign $0\main_wdata_consumed[0:0] 1'1 case end end - attribute \src "ls180.v:8251.2-8272.5" - switch $and$ls180.v:8251$2747_Y - attribute \src "ls180.v:8251.6-8251.91" + attribute \src "ls180.v:8045.2-8066.5" + switch $and$ls180.v:8045$2597_Y + attribute \src "ls180.v:8045.6-8045.91" case 1'1 assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000 assign $0\main_uart_phy_tx_busy[0:0] 1'1 assign $0\uart_tx[0:0] 1'0 - attribute \src "ls180.v:8256.6-8256.10" + attribute \src "ls180.v:8050.6-8050.10" case - attribute \src "ls180.v:8257.3-8271.6" - switch $and$ls180.v:8257$2748_Y - attribute \src "ls180.v:8257.7-8257.60" + attribute \src "ls180.v:8051.3-8065.6" + switch $and$ls180.v:8051$2598_Y + attribute \src "ls180.v:8051.7-8051.60" case 1'1 - assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8258$2749_Y - attribute \src "ls180.v:8259.4-8270.7" - switch $eq$ls180.v:8259$2750_Y - attribute \src "ls180.v:8259.8-8259.43" + assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8052$2599_Y + attribute \src "ls180.v:8053.4-8064.7" + switch $eq$ls180.v:8053$2600_Y + attribute \src "ls180.v:8053.8-8053.43" case 1'1 assign $0\uart_tx[0:0] 1'1 - attribute \src "ls180.v:8261.8-8261.12" + attribute \src "ls180.v:8055.8-8055.12" case - attribute \src "ls180.v:8262.5-8269.8" - switch $eq$ls180.v:8262$2751_Y - attribute \src "ls180.v:8262.9-8262.44" + attribute \src "ls180.v:8056.5-8063.8" + switch $eq$ls180.v:8056$2601_Y + attribute \src "ls180.v:8056.9-8056.44" case 1'1 assign $0\uart_tx[0:0] 1'1 assign $0\main_uart_phy_tx_busy[0:0] 1'0 assign $0\main_uart_phy_sink_ready[0:0] 1'1 - attribute \src "ls180.v:8266.9-8266.13" + attribute \src "ls180.v:8060.9-8060.13" case assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0] assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] } @@ -299251,61 +296207,61 @@ module \ls180 case end end - attribute \src "ls180.v:8273.2-8277.5" + attribute \src "ls180.v:8067.2-8071.5" switch \main_uart_phy_tx_busy - attribute \src "ls180.v:8273.6-8273.27" + attribute \src "ls180.v:8067.6-8067.27" case 1'1 - assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8274$2752_Y - attribute \src "ls180.v:8275.6-8275.10" + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8068$2602_Y + attribute \src "ls180.v:8069.6-8069.10" case assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } end - attribute \src "ls180.v:8280.2-8304.5" - switch $not$ls180.v:8280$2753_Y - attribute \src "ls180.v:8280.6-8280.30" + attribute \src "ls180.v:8074.2-8098.5" + switch $not$ls180.v:8074$2603_Y + attribute \src "ls180.v:8074.6-8074.30" case 1'1 - attribute \src "ls180.v:8281.3-8284.6" - switch $and$ls180.v:8281$2755_Y - attribute \src "ls180.v:8281.7-8281.49" + attribute \src "ls180.v:8075.3-8078.6" + switch $and$ls180.v:8075$2605_Y + attribute \src "ls180.v:8075.7-8075.49" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'1 assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000 case end - attribute \src "ls180.v:8285.6-8285.10" + attribute \src "ls180.v:8079.6-8079.10" case - attribute \src "ls180.v:8286.3-8303.6" + attribute \src "ls180.v:8080.3-8097.6" switch \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:8286.7-8286.34" + attribute \src "ls180.v:8080.7-8080.34" case 1'1 - assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8287$2756_Y - attribute \src "ls180.v:8288.4-8302.7" - switch $eq$ls180.v:8288$2757_Y - attribute \src "ls180.v:8288.8-8288.43" + assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8081$2606_Y + attribute \src "ls180.v:8082.4-8096.7" + switch $eq$ls180.v:8082$2607_Y + attribute \src "ls180.v:8082.8-8082.43" case 1'1 - attribute \src "ls180.v:8289.5-8291.8" + attribute \src "ls180.v:8083.5-8085.8" switch \main_uart_phy_rx - attribute \src "ls180.v:8289.9-8289.25" + attribute \src "ls180.v:8083.9-8083.25" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'0 case end - attribute \src "ls180.v:8292.8-8292.12" + attribute \src "ls180.v:8086.8-8086.12" case - attribute \src "ls180.v:8293.5-8301.8" - switch $eq$ls180.v:8293$2758_Y - attribute \src "ls180.v:8293.9-8293.44" + attribute \src "ls180.v:8087.5-8095.8" + switch $eq$ls180.v:8087$2608_Y + attribute \src "ls180.v:8087.9-8087.44" case 1'1 assign $0\main_uart_phy_rx_busy[0:0] 1'0 - attribute \src "ls180.v:8295.6-8298.9" + attribute \src "ls180.v:8089.6-8092.9" switch \main_uart_phy_rx - attribute \src "ls180.v:8295.10-8295.26" + attribute \src "ls180.v:8089.10-8089.26" case 1'1 assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg assign $0\main_uart_phy_source_valid[0:0] 1'1 case end - attribute \src "ls180.v:8299.9-8299.13" + attribute \src "ls180.v:8093.9-8093.13" case assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] } end @@ -299313,146 +296269,146 @@ module \ls180 case end end - attribute \src "ls180.v:8305.2-8309.5" + attribute \src "ls180.v:8099.2-8103.5" switch \main_uart_phy_rx_busy - attribute \src "ls180.v:8305.6-8305.27" + attribute \src "ls180.v:8099.6-8099.27" case 1'1 - assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8306$2759_Y - attribute \src "ls180.v:8307.6-8307.10" + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8100$2609_Y + attribute \src "ls180.v:8101.6-8101.10" case assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 end - attribute \src "ls180.v:8310.2-8312.5" + attribute \src "ls180.v:8104.2-8106.5" switch \main_uart_tx_clear - attribute \src "ls180.v:8310.6-8310.24" + attribute \src "ls180.v:8104.6-8104.24" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'0 case end - attribute \src "ls180.v:8314.2-8316.5" - switch $and$ls180.v:8314$2761_Y - attribute \src "ls180.v:8314.6-8314.58" + attribute \src "ls180.v:8108.2-8110.5" + switch $and$ls180.v:8108$2611_Y + attribute \src "ls180.v:8108.6-8108.58" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'1 case end - attribute \src "ls180.v:8317.2-8319.5" + attribute \src "ls180.v:8111.2-8113.5" switch \main_uart_rx_clear - attribute \src "ls180.v:8317.6-8317.24" + attribute \src "ls180.v:8111.6-8111.24" case 1'1 assign $0\main_uart_rx_pending[0:0] 1'0 case end - attribute \src "ls180.v:8321.2-8323.5" - switch $and$ls180.v:8321$2763_Y - attribute \src "ls180.v:8321.6-8321.58" + attribute \src "ls180.v:8115.2-8117.5" + switch $and$ls180.v:8115$2613_Y + attribute \src "ls180.v:8115.6-8115.58" case 1'1 assign $0\main_uart_rx_pending[0:0] 1'1 case end - attribute \src "ls180.v:8324.2-8330.5" + attribute \src "ls180.v:8118.2-8124.5" switch \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:8324.6-8324.35" + attribute \src "ls180.v:8118.6-8118.35" case 1'1 assign $0\main_uart_tx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8326.6-8326.10" + attribute \src "ls180.v:8120.6-8120.10" case - attribute \src "ls180.v:8327.3-8329.6" + attribute \src "ls180.v:8121.3-8123.6" switch \main_uart_tx_fifo_re - attribute \src "ls180.v:8327.7-8327.27" + attribute \src "ls180.v:8121.7-8121.27" case 1'1 assign $0\main_uart_tx_fifo_readable[0:0] 1'0 case end end - attribute \src "ls180.v:8331.2-8333.5" - switch $and$ls180.v:8331$2766_Y - attribute \src "ls180.v:8331.6-8331.108" + attribute \src "ls180.v:8125.2-8127.5" + switch $and$ls180.v:8125$2616_Y + attribute \src "ls180.v:8125.6-8125.108" case 1'1 - assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8332$2767_Y + assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8126$2617_Y case end - attribute \src "ls180.v:8334.2-8336.5" + attribute \src "ls180.v:8128.2-8130.5" switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8334.6-8334.31" + attribute \src "ls180.v:8128.6-8128.31" case 1'1 - assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8335$2768_Y + assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8129$2618_Y case end - attribute \src "ls180.v:8337.2-8345.5" - switch $and$ls180.v:8337$2771_Y - attribute \src "ls180.v:8337.6-8337.108" + attribute \src "ls180.v:8131.2-8139.5" + switch $and$ls180.v:8131$2621_Y + attribute \src "ls180.v:8131.6-8131.108" case 1'1 - attribute \src "ls180.v:8338.3-8340.6" - switch $not$ls180.v:8338$2772_Y - attribute \src "ls180.v:8338.7-8338.35" + attribute \src "ls180.v:8132.3-8134.6" + switch $not$ls180.v:8132$2622_Y + attribute \src "ls180.v:8132.7-8132.35" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8339$2773_Y + assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8133$2623_Y case end - attribute \src "ls180.v:8341.6-8341.10" + attribute \src "ls180.v:8135.6-8135.10" case - attribute \src "ls180.v:8342.3-8344.6" + attribute \src "ls180.v:8136.3-8138.6" switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8342.7-8342.32" + attribute \src "ls180.v:8136.7-8136.32" case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8343$2774_Y + assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8137$2624_Y case end end - attribute \src "ls180.v:8346.2-8352.5" + attribute \src "ls180.v:8140.2-8146.5" switch \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:8346.6-8346.35" + attribute \src "ls180.v:8140.6-8140.35" case 1'1 assign $0\main_uart_rx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8348.6-8348.10" + attribute \src "ls180.v:8142.6-8142.10" case - attribute \src "ls180.v:8349.3-8351.6" + attribute \src "ls180.v:8143.3-8145.6" switch \main_uart_rx_fifo_re - attribute \src "ls180.v:8349.7-8349.27" + attribute \src "ls180.v:8143.7-8143.27" case 1'1 assign $0\main_uart_rx_fifo_readable[0:0] 1'0 case end end - attribute \src "ls180.v:8353.2-8355.5" - switch $and$ls180.v:8353$2777_Y - attribute \src "ls180.v:8353.6-8353.108" + attribute \src "ls180.v:8147.2-8149.5" + switch $and$ls180.v:8147$2627_Y + attribute \src "ls180.v:8147.6-8147.108" case 1'1 - assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8354$2778_Y + assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8148$2628_Y case end - attribute \src "ls180.v:8356.2-8358.5" + attribute \src "ls180.v:8150.2-8152.5" switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8356.6-8356.31" + attribute \src "ls180.v:8150.6-8150.31" case 1'1 - assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8357$2779_Y + assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8151$2629_Y case end - attribute \src "ls180.v:8359.2-8367.5" - switch $and$ls180.v:8359$2782_Y - attribute \src "ls180.v:8359.6-8359.108" + attribute \src "ls180.v:8153.2-8161.5" + switch $and$ls180.v:8153$2632_Y + attribute \src "ls180.v:8153.6-8153.108" case 1'1 - attribute \src "ls180.v:8360.3-8362.6" - switch $not$ls180.v:8360$2783_Y - attribute \src "ls180.v:8360.7-8360.35" + attribute \src "ls180.v:8154.3-8156.6" + switch $not$ls180.v:8154$2633_Y + attribute \src "ls180.v:8154.7-8154.35" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8361$2784_Y + assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8155$2634_Y case end - attribute \src "ls180.v:8363.6-8363.10" + attribute \src "ls180.v:8157.6-8157.10" case - attribute \src "ls180.v:8364.3-8366.6" + attribute \src "ls180.v:8158.3-8160.6" switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8364.7-8364.32" + attribute \src "ls180.v:8158.7-8158.32" case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8365$2785_Y + assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8159$2635_Y case end end - attribute \src "ls180.v:8368.2-8381.5" + attribute \src "ls180.v:8162.2-8175.5" switch \main_uart_reset - attribute \src "ls180.v:8368.6-8368.21" + attribute \src "ls180.v:8162.6-8162.21" case 1'1 assign $0\main_uart_tx_pending[0:0] 1'0 assign $0\main_uart_tx_old_trigger[0:0] 1'0 @@ -299468,38 +296424,38 @@ module \ls180 assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 case end - attribute \src "ls180.v:8383.2-8390.5" + attribute \src "ls180.v:8177.2-8184.5" switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8383.6-8383.31" + attribute \src "ls180.v:8177.6-8177.31" case 1'1 assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable - attribute \src "ls180.v:8385.6-8385.10" + attribute \src "ls180.v:8179.6-8179.10" case - attribute \src "ls180.v:8386.3-8389.6" + attribute \src "ls180.v:8180.3-8183.6" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8386.7-8386.32" + attribute \src "ls180.v:8180.7-8180.32" case 1'1 assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 assign $0\spisdcard_clk[0:0] 1'0 case end end - attribute \src "ls180.v:8392.2-8402.5" + attribute \src "ls180.v:8186.2-8196.5" switch \main_spimaster28_mosi_latch - attribute \src "ls180.v:8392.6-8392.33" + attribute \src "ls180.v:8186.6-8186.33" case 1'1 assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi assign $0\main_spimaster34_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8395.6-8395.10" + attribute \src "ls180.v:8189.6-8189.10" case - attribute \src "ls180.v:8396.3-8401.6" + attribute \src "ls180.v:8190.3-8195.6" switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8396.7-8396.32" + attribute \src "ls180.v:8190.7-8190.32" case 1'1 - assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8400$2790_Y - attribute \src "ls180.v:8397.4-8399.7" + assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8194$2640_Y + attribute \src "ls180.v:8191.4-8193.7" switch \main_spimaster26_cs_enable - attribute \src "ls180.v:8397.8-8397.34" + attribute \src "ls180.v:8191.8-8191.34" case 1'1 assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0 case @@ -299507,67 +296463,67 @@ module \ls180 case end end - attribute \src "ls180.v:8403.2-8409.5" + attribute \src "ls180.v:8197.2-8203.5" switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8403.6-8403.31" + attribute \src "ls180.v:8197.6-8197.31" case 1'1 - attribute \src "ls180.v:8404.3-8408.6" + attribute \src "ls180.v:8198.3-8202.6" switch \main_spimaster7_loopback - attribute \src "ls180.v:8404.7-8404.31" + attribute \src "ls180.v:8198.7-8198.31" case 1'1 assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi } - attribute \src "ls180.v:8406.7-8406.11" + attribute \src "ls180.v:8200.7-8200.11" case assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso } end case end - attribute \src "ls180.v:8410.2-8412.5" + attribute \src "ls180.v:8204.2-8206.5" switch \main_spimaster29_miso_latch - attribute \src "ls180.v:8410.6-8410.33" + attribute \src "ls180.v:8204.6-8204.33" case 1'1 assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data case end - attribute \src "ls180.v:8414.2-8416.5" + attribute \src "ls180.v:8208.2-8210.5" switch \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:8414.6-8414.53" + attribute \src "ls180.v:8208.6-8208.53" case 1'1 assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value case end - attribute \src "ls180.v:8418.2-8425.5" + attribute \src "ls180.v:8212.2-8219.5" switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8418.6-8418.29" + attribute \src "ls180.v:8212.6-8212.29" case 1'1 assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable - attribute \src "ls180.v:8420.6-8420.10" + attribute \src "ls180.v:8214.6-8214.10" case - attribute \src "ls180.v:8421.3-8424.6" + attribute \src "ls180.v:8215.3-8218.6" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8421.7-8421.30" + attribute \src "ls180.v:8215.7-8215.30" case 1'1 assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 assign $0\spimaster_clk[0:0] 1'0 case end end - attribute \src "ls180.v:8427.2-8437.5" + attribute \src "ls180.v:8221.2-8231.5" switch \main_spisdcard_mosi_latch - attribute \src "ls180.v:8427.6-8427.31" + attribute \src "ls180.v:8221.6-8221.31" case 1'1 assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi assign $0\main_spisdcard_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8430.6-8430.10" + attribute \src "ls180.v:8224.6-8224.10" case - attribute \src "ls180.v:8431.3-8436.6" + attribute \src "ls180.v:8225.3-8230.6" switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8431.7-8431.30" + attribute \src "ls180.v:8225.7-8225.30" case 1'1 - assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8435$2795_Y - attribute \src "ls180.v:8432.4-8434.7" + assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8229$2645_Y + attribute \src "ls180.v:8226.4-8228.7" switch \main_spisdcard_cs_enable - attribute \src "ls180.v:8432.8-8432.32" + attribute \src "ls180.v:8226.8-8226.32" case 1'1 assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1 case @@ -299575,169 +296531,169 @@ module \ls180 case end end - attribute \src "ls180.v:8438.2-8444.5" + attribute \src "ls180.v:8232.2-8238.5" switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8438.6-8438.29" + attribute \src "ls180.v:8232.6-8232.29" case 1'1 - attribute \src "ls180.v:8439.3-8443.6" + attribute \src "ls180.v:8233.3-8237.6" switch \main_spisdcard_loopback - attribute \src "ls180.v:8439.7-8439.30" + attribute \src "ls180.v:8233.7-8233.30" case 1'1 assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi } - attribute \src "ls180.v:8441.7-8441.11" + attribute \src "ls180.v:8235.7-8235.11" case assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso } end case end - attribute \src "ls180.v:8445.2-8447.5" + attribute \src "ls180.v:8239.2-8241.5" switch \main_spisdcard_miso_latch - attribute \src "ls180.v:8445.6-8445.31" + attribute \src "ls180.v:8239.6-8239.31" case 1'1 assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data case end - attribute \src "ls180.v:8449.2-8451.5" + attribute \src "ls180.v:8243.2-8245.5" switch \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:8449.6-8449.51" + attribute \src "ls180.v:8243.6-8243.51" case 1'1 assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value case end - attribute \src "ls180.v:8452.2-8465.5" + attribute \src "ls180.v:8246.2-8259.5" switch \main_pwm0_enable - attribute \src "ls180.v:8452.6-8452.22" + attribute \src "ls180.v:8246.6-8246.22" case 1'1 - assign $0\main_pwm0_counter[31:0] $add$ls180.v:8453$2796_Y - attribute \src "ls180.v:8454.3-8458.6" - switch $lt$ls180.v:8454$2797_Y - attribute \src "ls180.v:8454.7-8454.44" + assign $0\main_pwm0_counter[31:0] $add$ls180.v:8247$2646_Y + attribute \src "ls180.v:8248.3-8252.6" + switch $lt$ls180.v:8248$2647_Y + attribute \src "ls180.v:8248.7-8248.44" case 1'1 assign $0\pwm[1:0] [0] 1'1 - attribute \src "ls180.v:8456.7-8456.11" + attribute \src "ls180.v:8250.7-8250.11" case assign $0\pwm[1:0] [0] 1'0 end - attribute \src "ls180.v:8459.3-8461.6" - switch $ge$ls180.v:8459$2799_Y - attribute \src "ls180.v:8459.7-8459.55" + attribute \src "ls180.v:8253.3-8255.6" + switch $ge$ls180.v:8253$2649_Y + attribute \src "ls180.v:8253.7-8253.55" case 1'1 assign $0\main_pwm0_counter[31:0] 0 case end - attribute \src "ls180.v:8462.6-8462.10" + attribute \src "ls180.v:8256.6-8256.10" case assign $0\main_pwm0_counter[31:0] 0 assign $0\pwm[1:0] [0] 1'0 end - attribute \src "ls180.v:8466.2-8479.5" + attribute \src "ls180.v:8260.2-8273.5" switch \main_pwm1_enable - attribute \src "ls180.v:8466.6-8466.22" + attribute \src "ls180.v:8260.6-8260.22" case 1'1 - assign $0\main_pwm1_counter[31:0] $add$ls180.v:8467$2800_Y - attribute \src "ls180.v:8468.3-8472.6" - switch $lt$ls180.v:8468$2801_Y - attribute \src "ls180.v:8468.7-8468.44" + assign $0\main_pwm1_counter[31:0] $add$ls180.v:8261$2650_Y + attribute \src "ls180.v:8262.3-8266.6" + switch $lt$ls180.v:8262$2651_Y + attribute \src "ls180.v:8262.7-8262.44" case 1'1 assign $0\pwm[1:0] [1] 1'1 - attribute \src "ls180.v:8470.7-8470.11" + attribute \src "ls180.v:8264.7-8264.11" case assign $0\pwm[1:0] [1] 1'0 end - attribute \src "ls180.v:8473.3-8475.6" - switch $ge$ls180.v:8473$2803_Y - attribute \src "ls180.v:8473.7-8473.55" + attribute \src "ls180.v:8267.3-8269.6" + switch $ge$ls180.v:8267$2653_Y + attribute \src "ls180.v:8267.7-8267.55" case 1'1 assign $0\main_pwm1_counter[31:0] 0 case end - attribute \src "ls180.v:8476.6-8476.10" + attribute \src "ls180.v:8270.6-8270.10" case assign $0\main_pwm1_counter[31:0] 0 assign $0\pwm[1:0] [1] 1'0 end - attribute \src "ls180.v:8480.2-8482.5" - switch $not$ls180.v:8480$2804_Y - attribute \src "ls180.v:8480.6-8480.32" + attribute \src "ls180.v:8274.2-8276.5" + switch $not$ls180.v:8274$2654_Y + attribute \src "ls180.v:8274.6-8274.32" case 1'1 - assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8481$2805_Y + assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8275$2655_Y case end - attribute \src "ls180.v:8486.2-8488.5" + attribute \src "ls180.v:8280.2-8282.5" switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:8486.6-8486.57" + attribute \src "ls180.v:8280.6-8280.57" case 1'1 assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value case end - attribute \src "ls180.v:8490.2-8492.5" + attribute \src "ls180.v:8284.2-8286.5" switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:8490.6-8490.57" + attribute \src "ls180.v:8284.6-8284.57" case 1'1 assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value case end - attribute \src "ls180.v:8493.2-8495.5" + attribute \src "ls180.v:8287.2-8289.5" switch \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:8493.6-8493.40" + attribute \src "ls180.v:8287.6-8287.40" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8494$2806_Y + assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8288$2656_Y case end - attribute \src "ls180.v:8496.2-8498.5" + attribute \src "ls180.v:8290.2-8292.5" switch \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:8496.6-8496.49" + attribute \src "ls180.v:8290.6-8290.49" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8499.2-8506.5" + attribute \src "ls180.v:8293.2-8300.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8499.6-8499.46" + attribute \src "ls180.v:8293.6-8293.46" case 1'1 - attribute \src "ls180.v:8500.3-8505.6" - switch $or$ls180.v:8500$2808_Y - attribute \src "ls180.v:8500.7-8500.98" + attribute \src "ls180.v:8294.3-8299.6" + switch $or$ls180.v:8294$2658_Y + attribute \src "ls180.v:8294.7-8294.98" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8503.7-8503.11" + attribute \src "ls180.v:8297.7-8297.11" case - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8504$2809_Y + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8298$2659_Y end case end - attribute \src "ls180.v:8507.2-8520.5" - switch $and$ls180.v:8507$2810_Y - attribute \src "ls180.v:8507.6-8507.97" + attribute \src "ls180.v:8301.2-8314.5" + switch $and$ls180.v:8301$2660_Y + attribute \src "ls180.v:8301.6-8301.97" case 1'1 - attribute \src "ls180.v:8508.3-8514.6" - switch $and$ls180.v:8508$2811_Y - attribute \src "ls180.v:8508.7-8508.94" + attribute \src "ls180.v:8302.3-8308.6" + switch $and$ls180.v:8302$2661_Y + attribute \src "ls180.v:8302.7-8302.94" case 1'1 assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:8511.7-8511.11" + attribute \src "ls180.v:8305.7-8305.11" case assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8515.6-8515.10" + attribute \src "ls180.v:8309.6-8309.10" case - attribute \src "ls180.v:8516.3-8519.6" - switch $and$ls180.v:8516$2812_Y - attribute \src "ls180.v:8516.7-8516.94" + attribute \src "ls180.v:8310.3-8313.6" + switch $and$ls180.v:8310$2662_Y + attribute \src "ls180.v:8310.7-8310.94" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8517$2813_Y - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8518$2814_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8311$2663_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8312$2664_Y case end end - attribute \src "ls180.v:8521.2-8548.5" + attribute \src "ls180.v:8315.2-8342.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8521.6-8521.46" + attribute \src "ls180.v:8315.6-8315.46" case 1'1 - attribute \src "ls180.v:8522.3-8547.10" + attribute \src "ls180.v:8316.3-8341.10" switch \main_sdphy_cmdr_cmdr_converter_demux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -299767,16 +296723,16 @@ module \ls180 end case end - attribute \src "ls180.v:8549.2-8551.5" + attribute \src "ls180.v:8343.2-8345.5" switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8549.6-8549.46" + attribute \src "ls180.v:8343.6-8343.46" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8550$2815_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8344$2665_Y case end - attribute \src "ls180.v:8552.2-8557.5" - switch $or$ls180.v:8552$2817_Y - attribute \src "ls180.v:8552.6-8552.88" + attribute \src "ls180.v:8346.2-8351.5" + switch $or$ls180.v:8346$2667_Y + attribute \src "ls180.v:8346.6-8346.88" case 1'1 assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first @@ -299784,9 +296740,9 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data case end - attribute \src "ls180.v:8558.2-8563.5" + attribute \src "ls180.v:8352.2-8357.5" switch \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:8558.6-8558.32" + attribute \src "ls180.v:8352.6-8352.32" case 1'1 assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 @@ -299794,88 +296750,88 @@ module \ls180 assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8565.2-8567.5" + attribute \src "ls180.v:8359.2-8361.5" switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:8565.6-8565.58" + attribute \src "ls180.v:8359.6-8359.58" case 1'1 assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 case end - attribute \src "ls180.v:8568.2-8570.5" + attribute \src "ls180.v:8362.2-8364.5" switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:8568.6-8568.60" + attribute \src "ls180.v:8362.6-8362.60" case 1'1 assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 case end - attribute \src "ls180.v:8571.2-8573.5" + attribute \src "ls180.v:8365.2-8367.5" switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:8571.6-8571.63" + attribute \src "ls180.v:8365.6-8365.63" case 1'1 assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 case end - attribute \src "ls180.v:8574.2-8576.5" + attribute \src "ls180.v:8368.2-8370.5" switch \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:8574.6-8574.41" + attribute \src "ls180.v:8368.6-8368.41" case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8575$2818_Y + assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8369$2668_Y case end - attribute \src "ls180.v:8577.2-8579.5" + attribute \src "ls180.v:8371.2-8373.5" switch \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:8577.6-8577.50" + attribute \src "ls180.v:8371.6-8371.50" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8580.2-8587.5" + attribute \src "ls180.v:8374.2-8381.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8580.6-8580.47" + attribute \src "ls180.v:8374.6-8374.47" case 1'1 - attribute \src "ls180.v:8581.3-8586.6" - switch $or$ls180.v:8581$2820_Y - attribute \src "ls180.v:8581.7-8581.100" + attribute \src "ls180.v:8375.3-8380.6" + switch $or$ls180.v:8375$2670_Y + attribute \src "ls180.v:8375.7-8375.100" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8584.7-8584.11" + attribute \src "ls180.v:8378.7-8378.11" case - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8585$2821_Y + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8379$2671_Y end case end - attribute \src "ls180.v:8588.2-8601.5" - switch $and$ls180.v:8588$2822_Y - attribute \src "ls180.v:8588.6-8588.99" + attribute \src "ls180.v:8382.2-8395.5" + switch $and$ls180.v:8382$2672_Y + attribute \src "ls180.v:8382.6-8382.99" case 1'1 - attribute \src "ls180.v:8589.3-8595.6" - switch $and$ls180.v:8589$2823_Y - attribute \src "ls180.v:8589.7-8589.96" + attribute \src "ls180.v:8383.3-8389.6" + switch $and$ls180.v:8383$2673_Y + attribute \src "ls180.v:8383.7-8383.96" case 1'1 assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:8592.7-8592.11" + attribute \src "ls180.v:8386.7-8386.11" case assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8596.6-8596.10" + attribute \src "ls180.v:8390.6-8390.10" case - attribute \src "ls180.v:8597.3-8600.6" - switch $and$ls180.v:8597$2824_Y - attribute \src "ls180.v:8597.7-8597.96" + attribute \src "ls180.v:8391.3-8394.6" + switch $and$ls180.v:8391$2674_Y + attribute \src "ls180.v:8391.7-8391.96" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8598$2825_Y - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8599$2826_Y + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8392$2675_Y + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8393$2676_Y case end end - attribute \src "ls180.v:8602.2-8629.5" + attribute \src "ls180.v:8396.2-8423.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8602.6-8602.47" + attribute \src "ls180.v:8396.6-8396.47" case 1'1 - attribute \src "ls180.v:8603.3-8628.10" + attribute \src "ls180.v:8397.3-8422.10" switch \main_sdphy_dataw_crcr_converter_demux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -299905,16 +296861,16 @@ module \ls180 end case end - attribute \src "ls180.v:8630.2-8632.5" + attribute \src "ls180.v:8424.2-8426.5" switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8630.6-8630.47" + attribute \src "ls180.v:8424.6-8424.47" case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8631$2827_Y + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8425$2677_Y case end - attribute \src "ls180.v:8633.2-8638.5" - switch $or$ls180.v:8633$2829_Y - attribute \src "ls180.v:8633.6-8633.90" + attribute \src "ls180.v:8427.2-8432.5" + switch $or$ls180.v:8427$2679_Y + attribute \src "ls180.v:8427.6-8427.90" case 1'1 assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first @@ -299922,9 +296878,9 @@ module \ls180 assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data case end - attribute \src "ls180.v:8639.2-8644.5" + attribute \src "ls180.v:8433.2-8438.5" switch \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:8639.6-8639.33" + attribute \src "ls180.v:8433.6-8433.33" case 1'1 assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 @@ -299932,81 +296888,81 @@ module \ls180 assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8646.2-8648.5" + attribute \src "ls180.v:8440.2-8442.5" switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:8646.6-8646.63" + attribute \src "ls180.v:8440.6-8440.63" case 1'1 assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value case end - attribute \src "ls180.v:8650.2-8652.5" + attribute \src "ls180.v:8444.2-8446.5" switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:8650.6-8650.52" + attribute \src "ls180.v:8444.6-8444.52" case 1'1 assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value case end - attribute \src "ls180.v:8653.2-8655.5" + attribute \src "ls180.v:8447.2-8449.5" switch \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:8653.6-8653.42" + attribute \src "ls180.v:8447.6-8447.42" case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8654$2830_Y + assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8448$2680_Y case end - attribute \src "ls180.v:8656.2-8658.5" + attribute \src "ls180.v:8450.2-8452.5" switch \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:8656.6-8656.51" + attribute \src "ls180.v:8450.6-8450.51" case 1'1 assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8659.2-8666.5" + attribute \src "ls180.v:8453.2-8460.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8659.6-8659.48" + attribute \src "ls180.v:8453.6-8453.48" case 1'1 - attribute \src "ls180.v:8660.3-8665.6" - switch $or$ls180.v:8660$2832_Y - attribute \src "ls180.v:8660.7-8660.102" + attribute \src "ls180.v:8454.3-8459.6" + switch $or$ls180.v:8454$2682_Y + attribute \src "ls180.v:8454.7-8454.102" case 1'1 assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8663.7-8663.11" + attribute \src "ls180.v:8457.7-8457.11" case - assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8664$2833_Y + assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8458$2683_Y end case end - attribute \src "ls180.v:8667.2-8680.5" - switch $and$ls180.v:8667$2834_Y - attribute \src "ls180.v:8667.6-8667.101" + attribute \src "ls180.v:8461.2-8474.5" + switch $and$ls180.v:8461$2684_Y + attribute \src "ls180.v:8461.6-8461.101" case 1'1 - attribute \src "ls180.v:8668.3-8674.6" - switch $and$ls180.v:8668$2835_Y - attribute \src "ls180.v:8668.7-8668.98" + attribute \src "ls180.v:8462.3-8468.6" + switch $and$ls180.v:8462$2685_Y + attribute \src "ls180.v:8462.7-8462.98" case 1'1 assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:8671.7-8671.11" + attribute \src "ls180.v:8465.7-8465.11" case assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8675.6-8675.10" + attribute \src "ls180.v:8469.6-8469.10" case - attribute \src "ls180.v:8676.3-8679.6" - switch $and$ls180.v:8676$2836_Y - attribute \src "ls180.v:8676.7-8676.98" + attribute \src "ls180.v:8470.3-8473.6" + switch $and$ls180.v:8470$2686_Y + attribute \src "ls180.v:8470.7-8470.98" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8677$2837_Y - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8678$2838_Y + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8471$2687_Y + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8472$2688_Y case end end - attribute \src "ls180.v:8681.2-8690.5" + attribute \src "ls180.v:8475.2-8484.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8681.6-8681.48" + attribute \src "ls180.v:8475.6-8475.48" case 1'1 - attribute \src "ls180.v:8682.3-8689.10" + attribute \src "ls180.v:8476.3-8483.10" switch \main_sdphy_datar_datar_converter_demux attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -300018,16 +296974,16 @@ module \ls180 end case end - attribute \src "ls180.v:8691.2-8693.5" + attribute \src "ls180.v:8485.2-8487.5" switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8691.6-8691.48" + attribute \src "ls180.v:8485.6-8485.48" case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8692$2839_Y + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8486$2689_Y case end - attribute \src "ls180.v:8694.2-8699.5" - switch $or$ls180.v:8694$2841_Y - attribute \src "ls180.v:8694.6-8694.92" + attribute \src "ls180.v:8488.2-8493.5" + switch $or$ls180.v:8488$2691_Y + attribute \src "ls180.v:8488.6-8488.92" case 1'1 assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first @@ -300035,9 +296991,9 @@ module \ls180 assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data case end - attribute \src "ls180.v:8700.2-8705.5" + attribute \src "ls180.v:8494.2-8499.5" switch \main_sdphy_datar_datar_reset - attribute \src "ls180.v:8700.6-8700.34" + attribute \src "ls180.v:8494.6-8494.34" case 1'1 assign $0\main_sdphy_datar_datar_run[0:0] 1'0 assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 @@ -300045,434 +297001,434 @@ module \ls180 assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 case end - attribute \src "ls180.v:8707.2-8709.5" + attribute \src "ls180.v:8501.2-8503.5" switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:8707.6-8707.60" + attribute \src "ls180.v:8501.6-8501.60" case 1'1 assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 case end - attribute \src "ls180.v:8710.2-8712.5" + attribute \src "ls180.v:8504.2-8506.5" switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:8710.6-8710.62" + attribute \src "ls180.v:8504.6-8504.62" case 1'1 assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 case end - attribute \src "ls180.v:8713.2-8715.5" + attribute \src "ls180.v:8507.2-8509.5" switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:8713.6-8713.66" + attribute \src "ls180.v:8507.6-8507.66" case 1'1 assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 case end - attribute \src "ls180.v:8716.2-8722.5" + attribute \src "ls180.v:8510.2-8516.5" switch \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:8716.6-8716.35" + attribute \src "ls180.v:8510.6-8510.35" case 1'1 assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - attribute \src "ls180.v:8718.6-8718.10" + attribute \src "ls180.v:8512.6-8512.10" case - attribute \src "ls180.v:8719.3-8721.6" + attribute \src "ls180.v:8513.3-8515.6" switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:8719.7-8719.39" + attribute \src "ls180.v:8513.7-8513.39" case 1'1 assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 case end end - attribute \src "ls180.v:8723.2-8729.5" + attribute \src "ls180.v:8517.2-8523.5" switch \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:8723.6-8723.41" + attribute \src "ls180.v:8517.6-8517.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8725.6-8725.10" + attribute \src "ls180.v:8519.6-8519.10" case - attribute \src "ls180.v:8726.3-8728.6" + attribute \src "ls180.v:8520.3-8522.6" switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:8726.7-8726.45" + attribute \src "ls180.v:8520.7-8520.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 case end end - attribute \src "ls180.v:8730.2-8736.5" + attribute \src "ls180.v:8524.2-8530.5" switch \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:8730.6-8730.41" + attribute \src "ls180.v:8524.6-8524.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8732.6-8732.10" + attribute \src "ls180.v:8526.6-8526.10" case - attribute \src "ls180.v:8733.3-8735.6" + attribute \src "ls180.v:8527.3-8529.6" switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:8733.7-8733.45" + attribute \src "ls180.v:8527.7-8527.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 case end end - attribute \src "ls180.v:8737.2-8743.5" + attribute \src "ls180.v:8531.2-8537.5" switch \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:8737.6-8737.41" + attribute \src "ls180.v:8531.6-8531.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8739.6-8739.10" + attribute \src "ls180.v:8533.6-8533.10" case - attribute \src "ls180.v:8740.3-8742.6" + attribute \src "ls180.v:8534.3-8536.6" switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:8740.7-8740.45" + attribute \src "ls180.v:8534.7-8534.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 case end end - attribute \src "ls180.v:8744.2-8750.5" + attribute \src "ls180.v:8538.2-8544.5" switch \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:8744.6-8744.41" + attribute \src "ls180.v:8538.6-8538.41" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8746.6-8746.10" + attribute \src "ls180.v:8540.6-8540.10" case - attribute \src "ls180.v:8747.3-8749.6" + attribute \src "ls180.v:8541.3-8543.6" switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:8747.7-8747.45" + attribute \src "ls180.v:8541.7-8541.45" case 1'1 assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 case end end - attribute \src "ls180.v:8752.2-8754.5" + attribute \src "ls180.v:8546.2-8548.5" switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:8752.6-8752.82" + attribute \src "ls180.v:8546.6-8546.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 case end - attribute \src "ls180.v:8755.2-8757.5" + attribute \src "ls180.v:8549.2-8551.5" switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:8755.6-8755.82" + attribute \src "ls180.v:8549.6-8549.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 case end - attribute \src "ls180.v:8758.2-8760.5" + attribute \src "ls180.v:8552.2-8554.5" switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:8758.6-8758.82" + attribute \src "ls180.v:8552.6-8552.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 case end - attribute \src "ls180.v:8761.2-8763.5" + attribute \src "ls180.v:8555.2-8557.5" switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:8761.6-8761.82" + attribute \src "ls180.v:8555.6-8555.82" case 1'1 assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 case end - attribute \src "ls180.v:8764.2-8766.5" + attribute \src "ls180.v:8558.2-8560.5" switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:8764.6-8764.78" + attribute \src "ls180.v:8558.6-8558.78" case 1'1 assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 case end - attribute \src "ls180.v:8767.2-8769.5" - switch $and$ls180.v:8767$2842_Y - attribute \src "ls180.v:8767.6-8767.83" + attribute \src "ls180.v:8561.2-8563.5" + switch $and$ls180.v:8561$2692_Y + attribute \src "ls180.v:8561.6-8561.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc case end - attribute \src "ls180.v:8770.2-8772.5" - switch $and$ls180.v:8770$2843_Y - attribute \src "ls180.v:8770.6-8770.83" + attribute \src "ls180.v:8564.2-8566.5" + switch $and$ls180.v:8564$2693_Y + attribute \src "ls180.v:8564.6-8564.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc case end - attribute \src "ls180.v:8773.2-8775.5" - switch $and$ls180.v:8773$2844_Y - attribute \src "ls180.v:8773.6-8773.83" + attribute \src "ls180.v:8567.2-8569.5" + switch $and$ls180.v:8567$2694_Y + attribute \src "ls180.v:8567.6-8567.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc case end - attribute \src "ls180.v:8776.2-8778.5" - switch $and$ls180.v:8776$2845_Y - attribute \src "ls180.v:8776.6-8776.83" + attribute \src "ls180.v:8570.2-8572.5" + switch $and$ls180.v:8570$2695_Y + attribute \src "ls180.v:8570.6-8570.83" case 1'1 assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc case end - attribute \src "ls180.v:8779.2-8783.5" - switch $and$ls180.v:8779$2846_Y - attribute \src "ls180.v:8779.6-8779.83" + attribute \src "ls180.v:8573.2-8577.5" + switch $and$ls180.v:8573$2696_Y + attribute \src "ls180.v:8573.6-8573.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] case end - attribute \src "ls180.v:8784.2-8788.5" - switch $and$ls180.v:8784$2847_Y - attribute \src "ls180.v:8784.6-8784.83" + attribute \src "ls180.v:8578.2-8582.5" + switch $and$ls180.v:8578$2697_Y + attribute \src "ls180.v:8578.6-8578.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] case end - attribute \src "ls180.v:8789.2-8793.5" - switch $and$ls180.v:8789$2848_Y - attribute \src "ls180.v:8789.6-8789.83" + attribute \src "ls180.v:8583.2-8587.5" + switch $and$ls180.v:8583$2698_Y + attribute \src "ls180.v:8583.6-8583.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] case end - attribute \src "ls180.v:8794.2-8798.5" - switch $and$ls180.v:8794$2849_Y - attribute \src "ls180.v:8794.6-8794.83" + attribute \src "ls180.v:8588.2-8592.5" + switch $and$ls180.v:8588$2699_Y + attribute \src "ls180.v:8588.6-8588.83" case 1'1 assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] case end - attribute \src "ls180.v:8799.2-8807.5" - switch $and$ls180.v:8799$2850_Y - attribute \src "ls180.v:8799.6-8799.83" + attribute \src "ls180.v:8593.2-8601.5" + switch $and$ls180.v:8593$2700_Y + attribute \src "ls180.v:8593.6-8593.83" case 1'1 - attribute \src "ls180.v:8800.3-8806.6" + attribute \src "ls180.v:8594.3-8600.6" switch \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:8800.7-8800.42" + attribute \src "ls180.v:8594.7-8594.42" case 1'1 assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - attribute \src "ls180.v:8802.7-8802.11" + attribute \src "ls180.v:8596.7-8596.11" case - attribute \src "ls180.v:8803.4-8805.7" - switch $ne$ls180.v:8803$2851_Y - attribute \src "ls180.v:8803.8-8803.48" + attribute \src "ls180.v:8597.4-8599.7" + switch $ne$ls180.v:8597$2701_Y + attribute \src "ls180.v:8597.8-8597.48" case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8804$2852_Y + assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8598$2702_Y case end end case end - attribute \src "ls180.v:8808.2-8814.5" + attribute \src "ls180.v:8602.2-8608.5" switch \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:8808.6-8808.40" + attribute \src "ls180.v:8602.6-8602.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8810.6-8810.10" + attribute \src "ls180.v:8604.6-8604.10" case - attribute \src "ls180.v:8811.3-8813.6" + attribute \src "ls180.v:8605.3-8607.6" switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:8811.7-8811.44" + attribute \src "ls180.v:8605.7-8605.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 case end end - attribute \src "ls180.v:8815.2-8821.5" + attribute \src "ls180.v:8609.2-8615.5" switch \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:8815.6-8815.40" + attribute \src "ls180.v:8609.6-8609.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8817.6-8817.10" + attribute \src "ls180.v:8611.6-8611.10" case - attribute \src "ls180.v:8818.3-8820.6" + attribute \src "ls180.v:8612.3-8614.6" switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:8818.7-8818.44" + attribute \src "ls180.v:8612.7-8612.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 case end end - attribute \src "ls180.v:8822.2-8828.5" + attribute \src "ls180.v:8616.2-8622.5" switch \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:8822.6-8822.40" + attribute \src "ls180.v:8616.6-8616.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8824.6-8824.10" + attribute \src "ls180.v:8618.6-8618.10" case - attribute \src "ls180.v:8825.3-8827.6" + attribute \src "ls180.v:8619.3-8621.6" switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:8825.7-8825.44" + attribute \src "ls180.v:8619.7-8619.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 case end end - attribute \src "ls180.v:8829.2-8835.5" + attribute \src "ls180.v:8623.2-8629.5" switch \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:8829.6-8829.40" + attribute \src "ls180.v:8623.6-8623.40" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8831.6-8831.10" + attribute \src "ls180.v:8625.6-8625.10" case - attribute \src "ls180.v:8832.3-8834.6" + attribute \src "ls180.v:8626.3-8628.6" switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:8832.7-8832.44" + attribute \src "ls180.v:8626.7-8626.44" case 1'1 assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 case end end - attribute \src "ls180.v:8837.2-8839.5" + attribute \src "ls180.v:8631.2-8633.5" switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:8837.6-8837.52" + attribute \src "ls180.v:8631.6-8631.52" case 1'1 assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 case end - attribute \src "ls180.v:8840.2-8842.5" + attribute \src "ls180.v:8634.2-8636.5" switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:8840.6-8840.53" + attribute \src "ls180.v:8634.6-8634.53" case 1'1 assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 case end - attribute \src "ls180.v:8843.2-8845.5" + attribute \src "ls180.v:8637.2-8639.5" switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:8843.6-8843.53" + attribute \src "ls180.v:8637.6-8637.53" case 1'1 assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 case end - attribute \src "ls180.v:8846.2-8848.5" + attribute \src "ls180.v:8640.2-8642.5" switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:8846.6-8846.54" + attribute \src "ls180.v:8640.6-8640.54" case 1'1 assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 case end - attribute \src "ls180.v:8849.2-8851.5" + attribute \src "ls180.v:8643.2-8645.5" switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:8849.6-8849.53" + attribute \src "ls180.v:8643.6-8643.53" case 1'1 assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 case end - attribute \src "ls180.v:8852.2-8854.5" + attribute \src "ls180.v:8646.2-8648.5" switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:8852.6-8852.55" + attribute \src "ls180.v:8646.6-8646.55" case 1'1 assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 case end - attribute \src "ls180.v:8855.2-8857.5" + attribute \src "ls180.v:8649.2-8651.5" switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:8855.6-8855.54" + attribute \src "ls180.v:8649.6-8649.54" case 1'1 assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 case end - attribute \src "ls180.v:8858.2-8860.5" + attribute \src "ls180.v:8652.2-8654.5" switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:8858.6-8858.56" + attribute \src "ls180.v:8652.6-8652.56" case 1'1 assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 case end - attribute \src "ls180.v:8861.2-8863.5" + attribute \src "ls180.v:8655.2-8657.5" switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:8861.6-8861.63" + attribute \src "ls180.v:8655.6-8655.63" case 1'1 assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 case end - attribute \src "ls180.v:8864.2-8866.5" - switch $and$ls180.v:8864$2855_Y - attribute \src "ls180.v:8864.6-8864.120" + attribute \src "ls180.v:8658.2-8660.5" + switch $and$ls180.v:8658$2705_Y + attribute \src "ls180.v:8658.6-8658.120" case 1'1 - assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8865$2856_Y + assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8659$2706_Y case end - attribute \src "ls180.v:8867.2-8869.5" + attribute \src "ls180.v:8661.2-8663.5" switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8867.6-8867.35" + attribute \src "ls180.v:8661.6-8661.35" case 1'1 - assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8868$2857_Y + assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8662$2707_Y case end - attribute \src "ls180.v:8870.2-8878.5" - switch $and$ls180.v:8870$2860_Y - attribute \src "ls180.v:8870.6-8870.120" + attribute \src "ls180.v:8664.2-8672.5" + switch $and$ls180.v:8664$2710_Y + attribute \src "ls180.v:8664.6-8664.120" case 1'1 - attribute \src "ls180.v:8871.3-8873.6" - switch $not$ls180.v:8871$2861_Y - attribute \src "ls180.v:8871.7-8871.39" + attribute \src "ls180.v:8665.3-8667.6" + switch $not$ls180.v:8665$2711_Y + attribute \src "ls180.v:8665.7-8665.39" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8872$2862_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8666$2712_Y case end - attribute \src "ls180.v:8874.6-8874.10" + attribute \src "ls180.v:8668.6-8668.10" case - attribute \src "ls180.v:8875.3-8877.6" + attribute \src "ls180.v:8669.3-8671.6" switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8875.7-8875.36" + attribute \src "ls180.v:8669.7-8669.36" case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8876$2863_Y + assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8670$2713_Y case end end - attribute \src "ls180.v:8879.2-8881.5" + attribute \src "ls180.v:8673.2-8675.5" switch \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:8879.6-8879.45" + attribute \src "ls180.v:8673.6-8673.45" case 1'1 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 case end - attribute \src "ls180.v:8882.2-8889.5" + attribute \src "ls180.v:8676.2-8683.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8882.6-8882.42" + attribute \src "ls180.v:8676.6-8676.42" case 1'1 - attribute \src "ls180.v:8883.3-8888.6" - switch $or$ls180.v:8883$2865_Y - attribute \src "ls180.v:8883.7-8883.90" + attribute \src "ls180.v:8677.3-8682.6" + switch $or$ls180.v:8677$2715_Y + attribute \src "ls180.v:8677.7-8677.90" case 1'1 assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8886.7-8886.11" + attribute \src "ls180.v:8680.7-8680.11" case - assign $0\main_sdblock2mem_converter_demux[2:0] $add$ls180.v:8887$2866_Y + assign $0\main_sdblock2mem_converter_demux[2:0] $add$ls180.v:8681$2716_Y end case end - attribute \src "ls180.v:8890.2-8903.5" - switch $and$ls180.v:8890$2867_Y - attribute \src "ls180.v:8890.6-8890.89" + attribute \src "ls180.v:8684.2-8697.5" + switch $and$ls180.v:8684$2717_Y + attribute \src "ls180.v:8684.6-8684.89" case 1'1 - attribute \src "ls180.v:8891.3-8897.6" - switch $and$ls180.v:8891$2868_Y - attribute \src "ls180.v:8891.7-8891.86" + attribute \src "ls180.v:8685.3-8691.6" + switch $and$ls180.v:8685$2718_Y + attribute \src "ls180.v:8685.7-8685.86" case 1'1 assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:8894.7-8894.11" + attribute \src "ls180.v:8688.7-8688.11" case assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 end - attribute \src "ls180.v:8898.6-8898.10" + attribute \src "ls180.v:8692.6-8692.10" case - attribute \src "ls180.v:8899.3-8902.6" - switch $and$ls180.v:8899$2869_Y - attribute \src "ls180.v:8899.7-8899.86" + attribute \src "ls180.v:8693.3-8696.6" + switch $and$ls180.v:8693$2719_Y + attribute \src "ls180.v:8693.7-8693.86" case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8900$2870_Y - assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8901$2871_Y + assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8694$2720_Y + assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8695$2721_Y case end end - attribute \src "ls180.v:8904.2-8931.5" + attribute \src "ls180.v:8698.2-8725.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8904.6-8904.42" + attribute \src "ls180.v:8698.6-8698.42" case 1'1 - attribute \src "ls180.v:8905.3-8930.10" + attribute \src "ls180.v:8699.3-8724.10" switch \main_sdblock2mem_converter_demux attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -300502,153 +297458,153 @@ module \ls180 end case end - attribute \src "ls180.v:8932.2-8934.5" + attribute \src "ls180.v:8726.2-8728.5" switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8932.6-8932.42" + attribute \src "ls180.v:8726.6-8726.42" case 1'1 - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8933$2872_Y + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8727$2722_Y case end - attribute \src "ls180.v:8936.2-8938.5" + attribute \src "ls180.v:8730.2-8732.5" switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:8936.6-8936.76" + attribute \src "ls180.v:8730.6-8730.76" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value case end - attribute \src "ls180.v:8939.2-8942.5" + attribute \src "ls180.v:8733.2-8736.5" switch \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:8939.6-8939.46" + attribute \src "ls180.v:8733.6-8733.46" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 assign $0\builder_sdblock2memdma_state[1:0] 2'00 case end - attribute \src "ls180.v:8944.2-8946.5" + attribute \src "ls180.v:8738.2-8740.5" switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:8944.6-8944.64" + attribute \src "ls180.v:8738.6-8738.64" case 1'1 assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value case end - attribute \src "ls180.v:8948.2-8950.5" + attribute \src "ls180.v:8742.2-8744.5" switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:8948.6-8948.76" + attribute \src "ls180.v:8742.6-8742.76" case 1'1 assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value case end - attribute \src "ls180.v:8951.2-8954.5" + attribute \src "ls180.v:8745.2-8748.5" switch \main_sdmem2block_dma_reset - attribute \src "ls180.v:8951.6-8951.32" + attribute \src "ls180.v:8745.6-8745.32" case 1'1 assign $0\main_sdmem2block_dma_offset[31:0] 0 assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 case end - attribute \src "ls180.v:8955.2-8961.5" - switch $and$ls180.v:8955$2873_Y - attribute \src "ls180.v:8955.6-8955.89" + attribute \src "ls180.v:8749.2-8755.5" + switch $and$ls180.v:8749$2723_Y + attribute \src "ls180.v:8749.6-8749.89" case 1'1 - attribute \src "ls180.v:8956.3-8960.6" + attribute \src "ls180.v:8750.3-8754.6" switch \main_sdmem2block_converter_last - attribute \src "ls180.v:8956.7-8956.38" + attribute \src "ls180.v:8750.7-8750.38" case 1'1 assign $0\main_sdmem2block_converter_mux[2:0] 3'000 - attribute \src "ls180.v:8958.7-8958.11" + attribute \src "ls180.v:8752.7-8752.11" case - assign $0\main_sdmem2block_converter_mux[2:0] $add$ls180.v:8959$2874_Y + assign $0\main_sdmem2block_converter_mux[2:0] $add$ls180.v:8753$2724_Y end case end - attribute \src "ls180.v:8962.2-8964.5" - switch $and$ls180.v:8962$2877_Y - attribute \src "ls180.v:8962.6-8962.120" + attribute \src "ls180.v:8756.2-8758.5" + switch $and$ls180.v:8756$2727_Y + attribute \src "ls180.v:8756.6-8756.120" case 1'1 - assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8963$2878_Y + assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8757$2728_Y case end - attribute \src "ls180.v:8965.2-8967.5" + attribute \src "ls180.v:8759.2-8761.5" switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8965.6-8965.35" + attribute \src "ls180.v:8759.6-8759.35" case 1'1 - assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8966$2879_Y + assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8760$2729_Y case end - attribute \src "ls180.v:8968.2-8976.5" - switch $and$ls180.v:8968$2882_Y - attribute \src "ls180.v:8968.6-8968.120" + attribute \src "ls180.v:8762.2-8770.5" + switch $and$ls180.v:8762$2732_Y + attribute \src "ls180.v:8762.6-8762.120" case 1'1 - attribute \src "ls180.v:8969.3-8971.6" - switch $not$ls180.v:8969$2883_Y - attribute \src "ls180.v:8969.7-8969.39" + attribute \src "ls180.v:8763.3-8765.6" + switch $not$ls180.v:8763$2733_Y + attribute \src "ls180.v:8763.7-8763.39" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8970$2884_Y + assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8764$2734_Y case end - attribute \src "ls180.v:8972.6-8972.10" + attribute \src "ls180.v:8766.6-8766.10" case - attribute \src "ls180.v:8973.3-8975.6" + attribute \src "ls180.v:8767.3-8769.6" switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8973.7-8973.36" + attribute \src "ls180.v:8767.7-8767.36" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8974$2885_Y + assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8768$2735_Y case end end - attribute \src "ls180.v:8978.2-8980.5" + attribute \src "ls180.v:8772.2-8774.5" switch \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:8978.6-8978.46" + attribute \src "ls180.v:8772.6-8772.46" case 1'1 assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 case end - attribute \src "ls180.v:8981.2-8983.5" + attribute \src "ls180.v:8775.2-8777.5" switch \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:8981.6-8981.44" + attribute \src "ls180.v:8775.6-8775.44" case 1'1 assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 case end - attribute \src "ls180.v:8984.2-8986.5" + attribute \src "ls180.v:8778.2-8780.5" switch \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:8984.6-8984.43" + attribute \src "ls180.v:8778.6-8778.43" case 1'1 assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 case end - attribute \src "ls180.v:8987.2-9083.9" + attribute \src "ls180.v:8781.2-8877.9" switch \builder_grant attribute \src "ls180.v:0.0-0.0" case 3'000 - attribute \src "ls180.v:8989.4-9005.7" - switch $not$ls180.v:8989$2886_Y - attribute \src "ls180.v:8989.8-8989.29" + attribute \src "ls180.v:8783.4-8799.7" + switch $not$ls180.v:8783$2736_Y + attribute \src "ls180.v:8783.8-8783.29" case 1'1 - attribute \src "ls180.v:8990.5-9004.8" + attribute \src "ls180.v:8784.5-8798.8" switch \builder_request [1] - attribute \src "ls180.v:8990.9-8990.27" + attribute \src "ls180.v:8784.9-8784.27" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8992.9-8992.13" + attribute \src "ls180.v:8786.9-8786.13" case - attribute \src "ls180.v:8993.6-9003.9" + attribute \src "ls180.v:8787.6-8797.9" switch \builder_request [2] - attribute \src "ls180.v:8993.10-8993.28" + attribute \src "ls180.v:8787.10-8787.28" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8995.10-8995.14" + attribute \src "ls180.v:8789.10-8789.14" case - attribute \src "ls180.v:8996.7-9002.10" + attribute \src "ls180.v:8790.7-8796.10" switch \builder_request [3] - attribute \src "ls180.v:8996.11-8996.29" + attribute \src "ls180.v:8790.11-8790.29" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8998.11-8998.15" + attribute \src "ls180.v:8792.11-8792.15" case - attribute \src "ls180.v:8999.8-9001.11" + attribute \src "ls180.v:8793.8-8795.11" switch \builder_request [4] - attribute \src "ls180.v:8999.12-8999.30" + attribute \src "ls180.v:8793.12-8793.30" case 1'1 assign $0\builder_grant[2:0] 3'100 case @@ -300660,34 +297616,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'001 - attribute \src "ls180.v:9008.4-9024.7" - switch $not$ls180.v:9008$2887_Y - attribute \src "ls180.v:9008.8-9008.29" + attribute \src "ls180.v:8802.4-8818.7" + switch $not$ls180.v:8802$2737_Y + attribute \src "ls180.v:8802.8-8802.29" case 1'1 - attribute \src "ls180.v:9009.5-9023.8" + attribute \src "ls180.v:8803.5-8817.8" switch \builder_request [2] - attribute \src "ls180.v:9009.9-9009.27" + attribute \src "ls180.v:8803.9-8803.27" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:9011.9-9011.13" + attribute \src "ls180.v:8805.9-8805.13" case - attribute \src "ls180.v:9012.6-9022.9" + attribute \src "ls180.v:8806.6-8816.9" switch \builder_request [3] - attribute \src "ls180.v:9012.10-9012.28" + attribute \src "ls180.v:8806.10-8806.28" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:9014.10-9014.14" + attribute \src "ls180.v:8808.10-8808.14" case - attribute \src "ls180.v:9015.7-9021.10" + attribute \src "ls180.v:8809.7-8815.10" switch \builder_request [4] - attribute \src "ls180.v:9015.11-9015.29" + attribute \src "ls180.v:8809.11-8809.29" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:9017.11-9017.15" + attribute \src "ls180.v:8811.11-8811.15" case - attribute \src "ls180.v:9018.8-9020.11" + attribute \src "ls180.v:8812.8-8814.11" switch \builder_request [0] - attribute \src "ls180.v:9018.12-9018.30" + attribute \src "ls180.v:8812.12-8812.30" case 1'1 assign $0\builder_grant[2:0] 3'000 case @@ -300699,34 +297655,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'010 - attribute \src "ls180.v:9027.4-9043.7" - switch $not$ls180.v:9027$2888_Y - attribute \src "ls180.v:9027.8-9027.29" + attribute \src "ls180.v:8821.4-8837.7" + switch $not$ls180.v:8821$2738_Y + attribute \src "ls180.v:8821.8-8821.29" case 1'1 - attribute \src "ls180.v:9028.5-9042.8" + attribute \src "ls180.v:8822.5-8836.8" switch \builder_request [3] - attribute \src "ls180.v:9028.9-9028.27" + attribute \src "ls180.v:8822.9-8822.27" case 1'1 assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:9030.9-9030.13" + attribute \src "ls180.v:8824.9-8824.13" case - attribute \src "ls180.v:9031.6-9041.9" + attribute \src "ls180.v:8825.6-8835.9" switch \builder_request [4] - attribute \src "ls180.v:9031.10-9031.28" + attribute \src "ls180.v:8825.10-8825.28" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:9033.10-9033.14" + attribute \src "ls180.v:8827.10-8827.14" case - attribute \src "ls180.v:9034.7-9040.10" + attribute \src "ls180.v:8828.7-8834.10" switch \builder_request [0] - attribute \src "ls180.v:9034.11-9034.29" + attribute \src "ls180.v:8828.11-8828.29" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:9036.11-9036.15" + attribute \src "ls180.v:8830.11-8830.15" case - attribute \src "ls180.v:9037.8-9039.11" + attribute \src "ls180.v:8831.8-8833.11" switch \builder_request [1] - attribute \src "ls180.v:9037.12-9037.30" + attribute \src "ls180.v:8831.12-8831.30" case 1'1 assign $0\builder_grant[2:0] 3'001 case @@ -300738,34 +297694,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'011 - attribute \src "ls180.v:9046.4-9062.7" - switch $not$ls180.v:9046$2889_Y - attribute \src "ls180.v:9046.8-9046.29" + attribute \src "ls180.v:8840.4-8856.7" + switch $not$ls180.v:8840$2739_Y + attribute \src "ls180.v:8840.8-8840.29" case 1'1 - attribute \src "ls180.v:9047.5-9061.8" + attribute \src "ls180.v:8841.5-8855.8" switch \builder_request [4] - attribute \src "ls180.v:9047.9-9047.27" + attribute \src "ls180.v:8841.9-8841.27" case 1'1 assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:9049.9-9049.13" + attribute \src "ls180.v:8843.9-8843.13" case - attribute \src "ls180.v:9050.6-9060.9" + attribute \src "ls180.v:8844.6-8854.9" switch \builder_request [0] - attribute \src "ls180.v:9050.10-9050.28" + attribute \src "ls180.v:8844.10-8844.28" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:9052.10-9052.14" + attribute \src "ls180.v:8846.10-8846.14" case - attribute \src "ls180.v:9053.7-9059.10" + attribute \src "ls180.v:8847.7-8853.10" switch \builder_request [1] - attribute \src "ls180.v:9053.11-9053.29" + attribute \src "ls180.v:8847.11-8847.29" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:9055.11-9055.15" + attribute \src "ls180.v:8849.11-8849.15" case - attribute \src "ls180.v:9056.8-9058.11" + attribute \src "ls180.v:8850.8-8852.11" switch \builder_request [2] - attribute \src "ls180.v:9056.12-9056.30" + attribute \src "ls180.v:8850.12-8850.30" case 1'1 assign $0\builder_grant[2:0] 3'010 case @@ -300777,34 +297733,34 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case 3'100 - attribute \src "ls180.v:9065.4-9081.7" - switch $not$ls180.v:9065$2890_Y - attribute \src "ls180.v:9065.8-9065.29" + attribute \src "ls180.v:8859.4-8875.7" + switch $not$ls180.v:8859$2740_Y + attribute \src "ls180.v:8859.8-8859.29" case 1'1 - attribute \src "ls180.v:9066.5-9080.8" + attribute \src "ls180.v:8860.5-8874.8" switch \builder_request [0] - attribute \src "ls180.v:9066.9-9066.27" + attribute \src "ls180.v:8860.9-8860.27" case 1'1 assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:9068.9-9068.13" + attribute \src "ls180.v:8862.9-8862.13" case - attribute \src "ls180.v:9069.6-9079.9" + attribute \src "ls180.v:8863.6-8873.9" switch \builder_request [1] - attribute \src "ls180.v:9069.10-9069.28" + attribute \src "ls180.v:8863.10-8863.28" case 1'1 assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:9071.10-9071.14" + attribute \src "ls180.v:8865.10-8865.14" case - attribute \src "ls180.v:9072.7-9078.10" + attribute \src "ls180.v:8866.7-8872.10" switch \builder_request [2] - attribute \src "ls180.v:9072.11-9072.29" + attribute \src "ls180.v:8866.11-8866.29" case 1'1 assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:9074.11-9074.15" + attribute \src "ls180.v:8868.11-8868.15" case - attribute \src "ls180.v:9075.8-9077.11" + attribute \src "ls180.v:8869.8-8871.11" switch \builder_request [3] - attribute \src "ls180.v:9075.12-9075.30" + attribute \src "ls180.v:8869.12-8869.30" case 1'1 assign $0\builder_grant[2:0] 3'011 case @@ -300816,26 +297772,26 @@ module \ls180 end case end - attribute \src "ls180.v:9085.2-9091.5" + attribute \src "ls180.v:8879.2-8885.5" switch \builder_wait - attribute \src "ls180.v:9085.6-9085.18" + attribute \src "ls180.v:8879.6-8879.18" case 1'1 - attribute \src "ls180.v:9086.3-9088.6" - switch $not$ls180.v:9086$2891_Y - attribute \src "ls180.v:9086.7-9086.22" + attribute \src "ls180.v:8880.3-8882.6" + switch $not$ls180.v:8880$2741_Y + attribute \src "ls180.v:8880.7-8880.22" case 1'1 - assign $0\builder_count[19:0] $sub$ls180.v:9087$2892_Y + assign $0\builder_count[19:0] $sub$ls180.v:8881$2742_Y case end - attribute \src "ls180.v:9089.6-9089.10" + attribute \src "ls180.v:8883.6-8883.10" case assign $0\builder_count[19:0] 20'11110100001001000000 end - attribute \src "ls180.v:9093.2-9123.5" + attribute \src "ls180.v:8887.2-8917.5" switch \builder_csrbank0_sel - attribute \src "ls180.v:9093.6-9093.26" + attribute \src "ls180.v:8887.6-8887.26" case 1'1 - attribute \src "ls180.v:9094.3-9122.10" + attribute \src "ls180.v:8888.3-8916.10" switch \builder_interface0_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -300868,46 +297824,46 @@ module \ls180 end case end - attribute \src "ls180.v:9124.2-9126.5" + attribute \src "ls180.v:8918.2-8920.5" switch \builder_csrbank0_reset0_re - attribute \src "ls180.v:9124.6-9124.32" + attribute \src "ls180.v:8918.6-8918.32" case 1'1 assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r case end - attribute \src "ls180.v:9128.2-9130.5" + attribute \src "ls180.v:8922.2-8924.5" switch \builder_csrbank0_scratch3_re - attribute \src "ls180.v:9128.6-9128.34" + attribute \src "ls180.v:8922.6-8922.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r case end - attribute \src "ls180.v:9131.2-9133.5" + attribute \src "ls180.v:8925.2-8927.5" switch \builder_csrbank0_scratch2_re - attribute \src "ls180.v:9131.6-9131.34" + attribute \src "ls180.v:8925.6-8925.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r case end - attribute \src "ls180.v:9134.2-9136.5" + attribute \src "ls180.v:8928.2-8930.5" switch \builder_csrbank0_scratch1_re - attribute \src "ls180.v:9134.6-9134.34" + attribute \src "ls180.v:8928.6-8928.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r case end - attribute \src "ls180.v:9137.2-9139.5" + attribute \src "ls180.v:8931.2-8933.5" switch \builder_csrbank0_scratch0_re - attribute \src "ls180.v:9137.6-9137.34" + attribute \src "ls180.v:8931.6-8931.34" case 1'1 assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r case end - attribute \src "ls180.v:9142.2-9163.5" + attribute \src "ls180.v:8936.2-8957.5" switch \builder_csrbank1_sel - attribute \src "ls180.v:9142.6-9142.26" + attribute \src "ls180.v:8936.6-8936.26" case 1'1 - attribute \src "ls180.v:9143.3-9162.10" + attribute \src "ls180.v:8937.3-8956.10" switch \builder_interface1_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -300931,39 +297887,39 @@ module \ls180 end case end - attribute \src "ls180.v:9164.2-9166.5" + attribute \src "ls180.v:8958.2-8960.5" switch \builder_csrbank1_oe1_re - attribute \src "ls180.v:9164.6-9164.29" + attribute \src "ls180.v:8958.6-8958.29" case 1'1 assign $0\main_gpiotristateasic1_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r case end - attribute \src "ls180.v:9167.2-9169.5" + attribute \src "ls180.v:8961.2-8963.5" switch \builder_csrbank1_oe0_re - attribute \src "ls180.v:9167.6-9167.29" + attribute \src "ls180.v:8961.6-8961.29" case 1'1 assign $0\main_gpiotristateasic1_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r case end - attribute \src "ls180.v:9171.2-9173.5" + attribute \src "ls180.v:8965.2-8967.5" switch \builder_csrbank1_out1_re - attribute \src "ls180.v:9171.6-9171.30" + attribute \src "ls180.v:8965.6-8965.30" case 1'1 assign $0\main_gpiotristateasic1_out_storage[15:0] [15:8] \builder_csrbank1_out1_r case end - attribute \src "ls180.v:9174.2-9176.5" + attribute \src "ls180.v:8968.2-8970.5" switch \builder_csrbank1_out0_re - attribute \src "ls180.v:9174.6-9174.30" + attribute \src "ls180.v:8968.6-8968.30" case 1'1 assign $0\main_gpiotristateasic1_out_storage[15:0] [7:0] \builder_csrbank1_out0_r case end - attribute \src "ls180.v:9179.2-9188.5" + attribute \src "ls180.v:8973.2-8982.5" switch \builder_csrbank2_sel - attribute \src "ls180.v:9179.6-9179.26" + attribute \src "ls180.v:8973.6-8973.26" case 1'1 - attribute \src "ls180.v:9180.3-9187.10" + attribute \src "ls180.v:8974.3-8981.10" switch \builder_interface2_bank_bus_adr [0] attribute \src "ls180.v:0.0-0.0" case 1'0 @@ -300975,18 +297931,18 @@ module \ls180 end case end - attribute \src "ls180.v:9189.2-9191.5" + attribute \src "ls180.v:8983.2-8985.5" switch \builder_csrbank2_w0_re - attribute \src "ls180.v:9189.6-9189.28" + attribute \src "ls180.v:8983.6-8983.28" case 1'1 assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r case end - attribute \src "ls180.v:9194.2-9224.5" + attribute \src "ls180.v:8988.2-9018.5" switch \builder_csrbank3_sel - attribute \src "ls180.v:9194.6-9194.26" + attribute \src "ls180.v:8988.6-8988.26" case 1'1 - attribute \src "ls180.v:9195.3-9223.10" + attribute \src "ls180.v:8989.3-9017.10" switch \builder_interface3_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -301019,74 +297975,74 @@ module \ls180 end case end - attribute \src "ls180.v:9225.2-9227.5" + attribute \src "ls180.v:9019.2-9021.5" switch \builder_csrbank3_enable0_re - attribute \src "ls180.v:9225.6-9225.33" + attribute \src "ls180.v:9019.6-9019.33" case 1'1 assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r case end - attribute \src "ls180.v:9229.2-9231.5" + attribute \src "ls180.v:9023.2-9025.5" switch \builder_csrbank3_width3_re - attribute \src "ls180.v:9229.6-9229.32" + attribute \src "ls180.v:9023.6-9023.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r case end - attribute \src "ls180.v:9232.2-9234.5" + attribute \src "ls180.v:9026.2-9028.5" switch \builder_csrbank3_width2_re - attribute \src "ls180.v:9232.6-9232.32" + attribute \src "ls180.v:9026.6-9026.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r case end - attribute \src "ls180.v:9235.2-9237.5" + attribute \src "ls180.v:9029.2-9031.5" switch \builder_csrbank3_width1_re - attribute \src "ls180.v:9235.6-9235.32" + attribute \src "ls180.v:9029.6-9029.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r case end - attribute \src "ls180.v:9238.2-9240.5" + attribute \src "ls180.v:9032.2-9034.5" switch \builder_csrbank3_width0_re - attribute \src "ls180.v:9238.6-9238.32" + attribute \src "ls180.v:9032.6-9032.32" case 1'1 assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r case end - attribute \src "ls180.v:9242.2-9244.5" + attribute \src "ls180.v:9036.2-9038.5" switch \builder_csrbank3_period3_re - attribute \src "ls180.v:9242.6-9242.33" + attribute \src "ls180.v:9036.6-9036.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r case end - attribute \src "ls180.v:9245.2-9247.5" + attribute \src "ls180.v:9039.2-9041.5" switch \builder_csrbank3_period2_re - attribute \src "ls180.v:9245.6-9245.33" + attribute \src "ls180.v:9039.6-9039.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r case end - attribute \src "ls180.v:9248.2-9250.5" + attribute \src "ls180.v:9042.2-9044.5" switch \builder_csrbank3_period1_re - attribute \src "ls180.v:9248.6-9248.33" + attribute \src "ls180.v:9042.6-9042.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r case end - attribute \src "ls180.v:9251.2-9253.5" + attribute \src "ls180.v:9045.2-9047.5" switch \builder_csrbank3_period0_re - attribute \src "ls180.v:9251.6-9251.33" + attribute \src "ls180.v:9045.6-9045.33" case 1'1 assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r case end - attribute \src "ls180.v:9256.2-9286.5" + attribute \src "ls180.v:9050.2-9080.5" switch \builder_csrbank4_sel - attribute \src "ls180.v:9256.6-9256.26" + attribute \src "ls180.v:9050.6-9050.26" case 1'1 - attribute \src "ls180.v:9257.3-9285.10" + attribute \src "ls180.v:9051.3-9079.10" switch \builder_interface4_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -301119,74 +298075,74 @@ module \ls180 end case end - attribute \src "ls180.v:9287.2-9289.5" + attribute \src "ls180.v:9081.2-9083.5" switch \builder_csrbank4_enable0_re - attribute \src "ls180.v:9287.6-9287.33" + attribute \src "ls180.v:9081.6-9081.33" case 1'1 assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r case end - attribute \src "ls180.v:9291.2-9293.5" + attribute \src "ls180.v:9085.2-9087.5" switch \builder_csrbank4_width3_re - attribute \src "ls180.v:9291.6-9291.32" + attribute \src "ls180.v:9085.6-9085.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r case end - attribute \src "ls180.v:9294.2-9296.5" + attribute \src "ls180.v:9088.2-9090.5" switch \builder_csrbank4_width2_re - attribute \src "ls180.v:9294.6-9294.32" + attribute \src "ls180.v:9088.6-9088.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r case end - attribute \src "ls180.v:9297.2-9299.5" + attribute \src "ls180.v:9091.2-9093.5" switch \builder_csrbank4_width1_re - attribute \src "ls180.v:9297.6-9297.32" + attribute \src "ls180.v:9091.6-9091.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r case end - attribute \src "ls180.v:9300.2-9302.5" + attribute \src "ls180.v:9094.2-9096.5" switch \builder_csrbank4_width0_re - attribute \src "ls180.v:9300.6-9300.32" + attribute \src "ls180.v:9094.6-9094.32" case 1'1 assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r case end - attribute \src "ls180.v:9304.2-9306.5" + attribute \src "ls180.v:9098.2-9100.5" switch \builder_csrbank4_period3_re - attribute \src "ls180.v:9304.6-9304.33" + attribute \src "ls180.v:9098.6-9098.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r case end - attribute \src "ls180.v:9307.2-9309.5" + attribute \src "ls180.v:9101.2-9103.5" switch \builder_csrbank4_period2_re - attribute \src "ls180.v:9307.6-9307.33" + attribute \src "ls180.v:9101.6-9101.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r case end - attribute \src "ls180.v:9310.2-9312.5" + attribute \src "ls180.v:9104.2-9106.5" switch \builder_csrbank4_period1_re - attribute \src "ls180.v:9310.6-9310.33" + attribute \src "ls180.v:9104.6-9104.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r case end - attribute \src "ls180.v:9313.2-9315.5" + attribute \src "ls180.v:9107.2-9109.5" switch \builder_csrbank4_period0_re - attribute \src "ls180.v:9313.6-9313.33" + attribute \src "ls180.v:9107.6-9107.33" case 1'1 assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r case end - attribute \src "ls180.v:9318.2-9366.5" + attribute \src "ls180.v:9112.2-9160.5" switch \builder_csrbank5_sel - attribute \src "ls180.v:9318.6-9318.26" + attribute \src "ls180.v:9112.6-9112.26" case 1'1 - attribute \src "ls180.v:9319.3-9365.10" + attribute \src "ls180.v:9113.3-9159.10" switch \builder_interface5_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -301237,109 +298193,109 @@ module \ls180 end case end - attribute \src "ls180.v:9367.2-9369.5" + attribute \src "ls180.v:9161.2-9163.5" switch \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:9367.6-9367.35" + attribute \src "ls180.v:9161.6-9161.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r case end - attribute \src "ls180.v:9370.2-9372.5" + attribute \src "ls180.v:9164.2-9166.5" switch \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:9370.6-9370.35" + attribute \src "ls180.v:9164.6-9164.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r case end - attribute \src "ls180.v:9373.2-9375.5" + attribute \src "ls180.v:9167.2-9169.5" switch \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:9373.6-9373.35" + attribute \src "ls180.v:9167.6-9167.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r case end - attribute \src "ls180.v:9376.2-9378.5" + attribute \src "ls180.v:9170.2-9172.5" switch \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:9376.6-9376.35" + attribute \src "ls180.v:9170.6-9170.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r case end - attribute \src "ls180.v:9379.2-9381.5" + attribute \src "ls180.v:9173.2-9175.5" switch \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:9379.6-9379.35" + attribute \src "ls180.v:9173.6-9173.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r case end - attribute \src "ls180.v:9382.2-9384.5" + attribute \src "ls180.v:9176.2-9178.5" switch \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:9382.6-9382.35" + attribute \src "ls180.v:9176.6-9176.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r case end - attribute \src "ls180.v:9385.2-9387.5" + attribute \src "ls180.v:9179.2-9181.5" switch \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:9385.6-9385.35" + attribute \src "ls180.v:9179.6-9179.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r case end - attribute \src "ls180.v:9388.2-9390.5" + attribute \src "ls180.v:9182.2-9184.5" switch \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:9388.6-9388.35" + attribute \src "ls180.v:9182.6-9182.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r case end - attribute \src "ls180.v:9392.2-9394.5" + attribute \src "ls180.v:9186.2-9188.5" switch \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:9392.6-9392.37" + attribute \src "ls180.v:9186.6-9186.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r case end - attribute \src "ls180.v:9395.2-9397.5" + attribute \src "ls180.v:9189.2-9191.5" switch \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:9395.6-9395.37" + attribute \src "ls180.v:9189.6-9189.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r case end - attribute \src "ls180.v:9398.2-9400.5" + attribute \src "ls180.v:9192.2-9194.5" switch \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:9398.6-9398.37" + attribute \src "ls180.v:9192.6-9192.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r case end - attribute \src "ls180.v:9401.2-9403.5" + attribute \src "ls180.v:9195.2-9197.5" switch \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:9401.6-9401.37" + attribute \src "ls180.v:9195.6-9195.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r case end - attribute \src "ls180.v:9405.2-9407.5" + attribute \src "ls180.v:9199.2-9201.5" switch \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:9405.6-9405.37" + attribute \src "ls180.v:9199.6-9199.37" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r case end - attribute \src "ls180.v:9409.2-9411.5" + attribute \src "ls180.v:9203.2-9205.5" switch \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:9409.6-9409.35" + attribute \src "ls180.v:9203.6-9203.35" case 1'1 assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r case end - attribute \src "ls180.v:9414.2-9516.5" + attribute \src "ls180.v:9208.2-9310.5" switch \builder_csrbank6_sel - attribute \src "ls180.v:9414.6-9414.26" + attribute \src "ls180.v:9208.6-9208.26" case 1'1 - attribute \src "ls180.v:9415.3-9515.10" + attribute \src "ls180.v:9209.3-9309.10" switch \builder_interface6_bank_bus_adr [5:0] attribute \src "ls180.v:0.0-0.0" case 6'000000 @@ -301444,109 +298400,109 @@ module \ls180 end case end - attribute \src "ls180.v:9517.2-9519.5" + attribute \src "ls180.v:9311.2-9313.5" switch \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:9517.6-9517.39" + attribute \src "ls180.v:9311.6-9311.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r case end - attribute \src "ls180.v:9520.2-9522.5" + attribute \src "ls180.v:9314.2-9316.5" switch \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:9520.6-9520.39" + attribute \src "ls180.v:9314.6-9314.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r case end - attribute \src "ls180.v:9523.2-9525.5" + attribute \src "ls180.v:9317.2-9319.5" switch \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:9523.6-9523.39" + attribute \src "ls180.v:9317.6-9317.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r case end - attribute \src "ls180.v:9526.2-9528.5" + attribute \src "ls180.v:9320.2-9322.5" switch \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:9526.6-9526.39" + attribute \src "ls180.v:9320.6-9320.39" case 1'1 assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r case end - attribute \src "ls180.v:9530.2-9532.5" + attribute \src "ls180.v:9324.2-9326.5" switch \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:9530.6-9530.38" + attribute \src "ls180.v:9324.6-9324.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r case end - attribute \src "ls180.v:9533.2-9535.5" + attribute \src "ls180.v:9327.2-9329.5" switch \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:9533.6-9533.38" + attribute \src "ls180.v:9327.6-9327.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r case end - attribute \src "ls180.v:9536.2-9538.5" + attribute \src "ls180.v:9330.2-9332.5" switch \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:9536.6-9536.38" + attribute \src "ls180.v:9330.6-9330.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r case end - attribute \src "ls180.v:9539.2-9541.5" + attribute \src "ls180.v:9333.2-9335.5" switch \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:9539.6-9539.38" + attribute \src "ls180.v:9333.6-9333.38" case 1'1 assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r case end - attribute \src "ls180.v:9543.2-9545.5" + attribute \src "ls180.v:9337.2-9339.5" switch \builder_csrbank6_block_length1_re - attribute \src "ls180.v:9543.6-9543.39" + attribute \src "ls180.v:9337.6-9337.39" case 1'1 assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r case end - attribute \src "ls180.v:9546.2-9548.5" + attribute \src "ls180.v:9340.2-9342.5" switch \builder_csrbank6_block_length0_re - attribute \src "ls180.v:9546.6-9546.39" + attribute \src "ls180.v:9340.6-9340.39" case 1'1 assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r case end - attribute \src "ls180.v:9550.2-9552.5" + attribute \src "ls180.v:9344.2-9346.5" switch \builder_csrbank6_block_count3_re - attribute \src "ls180.v:9550.6-9550.38" + attribute \src "ls180.v:9344.6-9344.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r case end - attribute \src "ls180.v:9553.2-9555.5" + attribute \src "ls180.v:9347.2-9349.5" switch \builder_csrbank6_block_count2_re - attribute \src "ls180.v:9553.6-9553.38" + attribute \src "ls180.v:9347.6-9347.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r case end - attribute \src "ls180.v:9556.2-9558.5" + attribute \src "ls180.v:9350.2-9352.5" switch \builder_csrbank6_block_count1_re - attribute \src "ls180.v:9556.6-9556.38" + attribute \src "ls180.v:9350.6-9350.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r case end - attribute \src "ls180.v:9559.2-9561.5" + attribute \src "ls180.v:9353.2-9355.5" switch \builder_csrbank6_block_count0_re - attribute \src "ls180.v:9559.6-9559.38" + attribute \src "ls180.v:9353.6-9353.38" case 1'1 assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r case end - attribute \src "ls180.v:9564.2-9624.5" + attribute \src "ls180.v:9358.2-9418.5" switch \builder_csrbank7_sel - attribute \src "ls180.v:9564.6-9564.26" + attribute \src "ls180.v:9358.6-9358.26" case 1'1 - attribute \src "ls180.v:9565.3-9623.10" + attribute \src "ls180.v:9359.3-9417.10" switch \builder_interface7_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 @@ -301609,109 +298565,109 @@ module \ls180 end case end - attribute \src "ls180.v:9625.2-9627.5" + attribute \src "ls180.v:9419.2-9421.5" switch \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:9625.6-9625.35" + attribute \src "ls180.v:9419.6-9419.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r case end - attribute \src "ls180.v:9628.2-9630.5" + attribute \src "ls180.v:9422.2-9424.5" switch \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:9628.6-9628.35" + attribute \src "ls180.v:9422.6-9422.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r case end - attribute \src "ls180.v:9631.2-9633.5" + attribute \src "ls180.v:9425.2-9427.5" switch \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:9631.6-9631.35" + attribute \src "ls180.v:9425.6-9425.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r case end - attribute \src "ls180.v:9634.2-9636.5" + attribute \src "ls180.v:9428.2-9430.5" switch \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:9634.6-9634.35" + attribute \src "ls180.v:9428.6-9428.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r case end - attribute \src "ls180.v:9637.2-9639.5" + attribute \src "ls180.v:9431.2-9433.5" switch \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:9637.6-9637.35" + attribute \src "ls180.v:9431.6-9431.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r case end - attribute \src "ls180.v:9640.2-9642.5" + attribute \src "ls180.v:9434.2-9436.5" switch \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:9640.6-9640.35" + attribute \src "ls180.v:9434.6-9434.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r case end - attribute \src "ls180.v:9643.2-9645.5" + attribute \src "ls180.v:9437.2-9439.5" switch \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:9643.6-9643.35" + attribute \src "ls180.v:9437.6-9437.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r case end - attribute \src "ls180.v:9646.2-9648.5" + attribute \src "ls180.v:9440.2-9442.5" switch \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:9646.6-9646.35" + attribute \src "ls180.v:9440.6-9440.35" case 1'1 assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r case end - attribute \src "ls180.v:9650.2-9652.5" + attribute \src "ls180.v:9444.2-9446.5" switch \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:9650.6-9650.37" + attribute \src "ls180.v:9444.6-9444.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r case end - attribute \src "ls180.v:9653.2-9655.5" + attribute \src "ls180.v:9447.2-9449.5" switch \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:9653.6-9653.37" + attribute \src "ls180.v:9447.6-9447.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r case end - attribute \src "ls180.v:9656.2-9658.5" + attribute \src "ls180.v:9450.2-9452.5" switch \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:9656.6-9656.37" + attribute \src "ls180.v:9450.6-9450.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r case end - attribute \src "ls180.v:9659.2-9661.5" + attribute \src "ls180.v:9453.2-9455.5" switch \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:9659.6-9659.37" + attribute \src "ls180.v:9453.6-9453.37" case 1'1 assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r case end - attribute \src "ls180.v:9663.2-9665.5" + attribute \src "ls180.v:9457.2-9459.5" switch \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:9663.6-9663.37" + attribute \src "ls180.v:9457.6-9457.37" case 1'1 assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r case end - attribute \src "ls180.v:9667.2-9669.5" + attribute \src "ls180.v:9461.2-9463.5" switch \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:9667.6-9667.35" + attribute \src "ls180.v:9461.6-9461.35" case 1'1 assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r case end - attribute \src "ls180.v:9672.2-9687.5" + attribute \src "ls180.v:9466.2-9481.5" switch \builder_csrbank8_sel - attribute \src "ls180.v:9672.6-9672.26" + attribute \src "ls180.v:9466.6-9466.26" case 1'1 - attribute \src "ls180.v:9673.3-9686.10" + attribute \src "ls180.v:9467.3-9480.10" switch \builder_interface8_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -301729,25 +298685,25 @@ module \ls180 end case end - attribute \src "ls180.v:9688.2-9690.5" + attribute \src "ls180.v:9482.2-9484.5" switch \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:9688.6-9688.42" + attribute \src "ls180.v:9482.6-9482.42" case 1'1 assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r case end - attribute \src "ls180.v:9691.2-9693.5" + attribute \src "ls180.v:9485.2-9487.5" switch \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:9691.6-9691.42" + attribute \src "ls180.v:9485.6-9485.42" case 1'1 assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r case end - attribute \src "ls180.v:9696.2-9729.5" + attribute \src "ls180.v:9490.2-9523.5" switch \builder_csrbank9_sel - attribute \src "ls180.v:9696.6-9696.26" + attribute \src "ls180.v:9490.6-9490.26" case 1'1 - attribute \src "ls180.v:9697.3-9728.10" + attribute \src "ls180.v:9491.3-9522.10" switch \builder_interface9_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -301783,60 +298739,60 @@ module \ls180 end case end - attribute \src "ls180.v:9730.2-9732.5" + attribute \src "ls180.v:9524.2-9526.5" switch \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:9730.6-9730.39" + attribute \src "ls180.v:9524.6-9524.39" case 1'1 assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r case end - attribute \src "ls180.v:9734.2-9736.5" + attribute \src "ls180.v:9528.2-9530.5" switch \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:9734.6-9734.43" + attribute \src "ls180.v:9528.6-9528.43" case 1'1 assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r case end - attribute \src "ls180.v:9738.2-9740.5" + attribute \src "ls180.v:9532.2-9534.5" switch \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:9738.6-9738.43" + attribute \src "ls180.v:9532.6-9532.43" case 1'1 assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r case end - attribute \src "ls180.v:9741.2-9743.5" + attribute \src "ls180.v:9535.2-9537.5" switch \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:9741.6-9741.43" + attribute \src "ls180.v:9535.6-9535.43" case 1'1 assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r case end - attribute \src "ls180.v:9745.2-9747.5" + attribute \src "ls180.v:9539.2-9541.5" switch \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:9745.6-9745.44" + attribute \src "ls180.v:9539.6-9539.44" case 1'1 assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r case end - attribute \src "ls180.v:9749.2-9751.5" + attribute \src "ls180.v:9543.2-9545.5" switch \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:9749.6-9749.42" + attribute \src "ls180.v:9543.6-9543.42" case 1'1 assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r case end - attribute \src "ls180.v:9752.2-9754.5" + attribute \src "ls180.v:9546.2-9548.5" switch \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:9752.6-9752.42" + attribute \src "ls180.v:9546.6-9546.42" case 1'1 assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r case end - attribute \src "ls180.v:9757.2-9781.5" + attribute \src "ls180.v:9551.2-9575.5" switch \builder_csrbank10_sel - attribute \src "ls180.v:9757.6-9757.27" + attribute \src "ls180.v:9551.6-9551.27" case 1'1 - attribute \src "ls180.v:9758.3-9780.10" + attribute \src "ls180.v:9552.3-9574.10" switch \builder_interface10_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -301863,46 +298819,46 @@ module \ls180 end case end - attribute \src "ls180.v:9782.2-9784.5" + attribute \src "ls180.v:9576.2-9578.5" switch \builder_csrbank10_control1_re - attribute \src "ls180.v:9782.6-9782.35" + attribute \src "ls180.v:9576.6-9576.35" case 1'1 assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r case end - attribute \src "ls180.v:9785.2-9787.5" + attribute \src "ls180.v:9579.2-9581.5" switch \builder_csrbank10_control0_re - attribute \src "ls180.v:9785.6-9785.35" + attribute \src "ls180.v:9579.6-9579.35" case 1'1 assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r case end - attribute \src "ls180.v:9789.2-9791.5" + attribute \src "ls180.v:9583.2-9585.5" switch \builder_csrbank10_mosi0_re - attribute \src "ls180.v:9789.6-9789.32" + attribute \src "ls180.v:9583.6-9583.32" case 1'1 assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r case end - attribute \src "ls180.v:9793.2-9795.5" + attribute \src "ls180.v:9587.2-9589.5" switch \builder_csrbank10_cs0_re - attribute \src "ls180.v:9793.6-9793.30" + attribute \src "ls180.v:9587.6-9587.30" case 1'1 assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r case end - attribute \src "ls180.v:9797.2-9799.5" + attribute \src "ls180.v:9591.2-9593.5" switch \builder_csrbank10_loopback0_re - attribute \src "ls180.v:9797.6-9797.36" + attribute \src "ls180.v:9591.6-9591.36" case 1'1 assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r case end - attribute \src "ls180.v:9802.2-9832.5" + attribute \src "ls180.v:9596.2-9626.5" switch \builder_csrbank11_sel - attribute \src "ls180.v:9802.6-9802.27" + attribute \src "ls180.v:9596.6-9596.27" case 1'1 - attribute \src "ls180.v:9803.3-9831.10" + attribute \src "ls180.v:9597.3-9625.10" switch \builder_interface11_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 @@ -301935,60 +298891,60 @@ module \ls180 end case end - attribute \src "ls180.v:9833.2-9835.5" + attribute \src "ls180.v:9627.2-9629.5" switch \builder_csrbank11_control1_re - attribute \src "ls180.v:9833.6-9833.35" + attribute \src "ls180.v:9627.6-9627.35" case 1'1 assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r case end - attribute \src "ls180.v:9836.2-9838.5" + attribute \src "ls180.v:9630.2-9632.5" switch \builder_csrbank11_control0_re - attribute \src "ls180.v:9836.6-9836.35" + attribute \src "ls180.v:9630.6-9630.35" case 1'1 assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r case end - attribute \src "ls180.v:9840.2-9842.5" + attribute \src "ls180.v:9634.2-9636.5" switch \builder_csrbank11_mosi0_re - attribute \src "ls180.v:9840.6-9840.32" + attribute \src "ls180.v:9634.6-9634.32" case 1'1 assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r case end - attribute \src "ls180.v:9844.2-9846.5" + attribute \src "ls180.v:9638.2-9640.5" switch \builder_csrbank11_cs0_re - attribute \src "ls180.v:9844.6-9844.30" + attribute \src "ls180.v:9638.6-9638.30" case 1'1 assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r case end - attribute \src "ls180.v:9848.2-9850.5" + attribute \src "ls180.v:9642.2-9644.5" switch \builder_csrbank11_loopback0_re - attribute \src "ls180.v:9848.6-9848.36" + attribute \src "ls180.v:9642.6-9642.36" case 1'1 assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r case end - attribute \src "ls180.v:9852.2-9854.5" + attribute \src "ls180.v:9646.2-9648.5" switch \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:9852.6-9852.39" + attribute \src "ls180.v:9646.6-9646.39" case 1'1 assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r case end - attribute \src "ls180.v:9855.2-9857.5" + attribute \src "ls180.v:9649.2-9651.5" switch \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:9855.6-9855.39" + attribute \src "ls180.v:9649.6-9649.39" case 1'1 assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r case end - attribute \src "ls180.v:9860.2-9914.5" + attribute \src "ls180.v:9654.2-9708.5" switch \builder_csrbank12_sel - attribute \src "ls180.v:9860.6-9860.27" + attribute \src "ls180.v:9654.6-9654.27" case 1'1 - attribute \src "ls180.v:9861.3-9913.10" + attribute \src "ls180.v:9655.3-9707.10" switch \builder_interface12_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 @@ -302045,88 +299001,88 @@ module \ls180 end case end - attribute \src "ls180.v:9915.2-9917.5" + attribute \src "ls180.v:9709.2-9711.5" switch \builder_csrbank12_load3_re - attribute \src "ls180.v:9915.6-9915.32" + attribute \src "ls180.v:9709.6-9709.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r case end - attribute \src "ls180.v:9918.2-9920.5" + attribute \src "ls180.v:9712.2-9714.5" switch \builder_csrbank12_load2_re - attribute \src "ls180.v:9918.6-9918.32" + attribute \src "ls180.v:9712.6-9712.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r case end - attribute \src "ls180.v:9921.2-9923.5" + attribute \src "ls180.v:9715.2-9717.5" switch \builder_csrbank12_load1_re - attribute \src "ls180.v:9921.6-9921.32" + attribute \src "ls180.v:9715.6-9715.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r case end - attribute \src "ls180.v:9924.2-9926.5" + attribute \src "ls180.v:9718.2-9720.5" switch \builder_csrbank12_load0_re - attribute \src "ls180.v:9924.6-9924.32" + attribute \src "ls180.v:9718.6-9718.32" case 1'1 assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r case end - attribute \src "ls180.v:9928.2-9930.5" + attribute \src "ls180.v:9722.2-9724.5" switch \builder_csrbank12_reload3_re - attribute \src "ls180.v:9928.6-9928.34" + attribute \src "ls180.v:9722.6-9722.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r case end - attribute \src "ls180.v:9931.2-9933.5" + attribute \src "ls180.v:9725.2-9727.5" switch \builder_csrbank12_reload2_re - attribute \src "ls180.v:9931.6-9931.34" + attribute \src "ls180.v:9725.6-9725.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r case end - attribute \src "ls180.v:9934.2-9936.5" + attribute \src "ls180.v:9728.2-9730.5" switch \builder_csrbank12_reload1_re - attribute \src "ls180.v:9934.6-9934.34" + attribute \src "ls180.v:9728.6-9728.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r case end - attribute \src "ls180.v:9937.2-9939.5" + attribute \src "ls180.v:9731.2-9733.5" switch \builder_csrbank12_reload0_re - attribute \src "ls180.v:9937.6-9937.34" + attribute \src "ls180.v:9731.6-9731.34" case 1'1 assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r case end - attribute \src "ls180.v:9941.2-9943.5" + attribute \src "ls180.v:9735.2-9737.5" switch \builder_csrbank12_en0_re - attribute \src "ls180.v:9941.6-9941.30" + attribute \src "ls180.v:9735.6-9735.30" case 1'1 assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r case end - attribute \src "ls180.v:9945.2-9947.5" + attribute \src "ls180.v:9739.2-9741.5" switch \builder_csrbank12_update_value0_re - attribute \src "ls180.v:9945.6-9945.40" + attribute \src "ls180.v:9739.6-9739.40" case 1'1 assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r case end - attribute \src "ls180.v:9949.2-9951.5" + attribute \src "ls180.v:9743.2-9745.5" switch \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:9949.6-9949.37" + attribute \src "ls180.v:9743.6-9743.37" case 1'1 assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r case end - attribute \src "ls180.v:9954.2-9981.5" + attribute \src "ls180.v:9748.2-9775.5" switch \builder_csrbank13_sel - attribute \src "ls180.v:9954.6-9954.27" + attribute \src "ls180.v:9748.6-9748.27" case 1'1 - attribute \src "ls180.v:9955.3-9980.10" + attribute \src "ls180.v:9749.3-9774.10" switch \builder_interface13_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 @@ -302156,18 +299112,18 @@ module \ls180 end case end - attribute \src "ls180.v:9982.2-9984.5" + attribute \src "ls180.v:9776.2-9778.5" switch \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:9982.6-9982.37" + attribute \src "ls180.v:9776.6-9776.37" case 1'1 assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r case end - attribute \src "ls180.v:9987.2-10002.5" + attribute \src "ls180.v:9781.2-9796.5" switch \builder_csrbank14_sel - attribute \src "ls180.v:9987.6-9987.27" + attribute \src "ls180.v:9781.6-9781.27" case 1'1 - attribute \src "ls180.v:9988.3-10001.10" + attribute \src "ls180.v:9782.3-9795.10" switch \builder_interface14_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 @@ -302185,51 +299141,51 @@ module \ls180 end case end - attribute \src "ls180.v:10003.2-10005.5" + attribute \src "ls180.v:9797.2-9799.5" switch \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:10003.6-10003.39" + attribute \src "ls180.v:9797.6-9797.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r case end - attribute \src "ls180.v:10006.2-10008.5" + attribute \src "ls180.v:9800.2-9802.5" switch \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:10006.6-10006.39" + attribute \src "ls180.v:9800.6-9800.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r case end - attribute \src "ls180.v:10009.2-10011.5" + attribute \src "ls180.v:9803.2-9805.5" switch \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:10009.6-10009.39" + attribute \src "ls180.v:9803.6-9803.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r case end - attribute \src "ls180.v:10012.2-10014.5" + attribute \src "ls180.v:9806.2-9808.5" switch \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:10012.6-10012.39" + attribute \src "ls180.v:9806.6-9806.39" case 1'1 assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r case end - attribute \src "ls180.v:10016.2-10314.5" + attribute \src "ls180.v:9810.2-10105.5" switch \sys_rst_1 - attribute \src "ls180.v:10016.6-10016.15" + attribute \src "ls180.v:9810.6-9810.15" case 1'1 assign $0\main_libresocsim_reset_storage[0:0] 1'0 assign $0\main_libresocsim_reset_re[0:0] 1'0 assign $0\main_libresocsim_scratch_storage[31:0] 305419896 assign $0\main_libresocsim_scratch_re[0:0] 1'0 assign $0\main_libresocsim_bus_errors[31:0] 0 + assign $0\uart_tx[0:0] 1'1 assign $0\spisdcard_clk[0:0] 1'0 assign $0\spisdcard_mosi[0:0] 1'0 assign $0\spisdcard_cs_n[0:0] 1'0 - assign $0\pwm[1:0] 2'00 assign $0\spimaster_clk[0:0] 1'0 assign $0\spimaster_mosi[0:0] 1'0 assign $0\spimaster_cs_n[0:0] 1'0 - assign $0\uart_tx[0:0] 1'1 + assign $0\pwm[1:0] 2'00 assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 assign $0\main_libresocsim_load_storage[31:0] 0 assign $0\main_libresocsim_load_re[0:0] 1'0 @@ -302245,10 +299201,7 @@ module \ls180 assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0 assign $0\main_libresocsim_eventmanager_re[0:0] 1'0 assign $0\main_libresocsim_value[31:0] 0 - assign $0\main_interface0_ram_bus_ack[0:0] 1'0 - assign $0\main_interface1_ram_bus_ack[0:0] 1'0 - assign $0\main_interface2_ram_bus_ack[0:0] 1'0 - assign $0\main_interface3_ram_bus_ack[0:0] 1'0 + assign $0\main_ram_bus_ram_bus_ack[0:0] 1'0 assign $0\main_converter0_counter[0:0] 1'0 assign $0\main_converter1_counter[0:0] 1'0 assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 @@ -302511,20 +299464,20 @@ module \ls180 assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 assign $0\builder_libresocsim_we[0:0] 1'0 assign $0\builder_grant[2:0] 3'000 - assign $0\builder_slave_sel_r[12:0] 13'0000000000000 + assign $0\builder_slave_sel_r[5:0] 6'000000 assign $0\builder_count[19:0] 20'11110100001001000000 assign $0\builder_state[1:0] 2'00 case end sync posedge \sys_clk_1 + update \uart_tx $0\uart_tx[0:0] update \spisdcard_clk $0\spisdcard_clk[0:0] update \spisdcard_mosi $0\spisdcard_mosi[0:0] update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] - update \pwm $0\pwm[1:0] update \spimaster_clk $0\spimaster_clk[0:0] update \spimaster_mosi $0\spimaster_mosi[0:0] update \spimaster_cs_n $0\spimaster_cs_n[0:0] - update \uart_tx $0\uart_tx[0:0] + update \pwm $0\pwm[1:0] update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] @@ -302545,10 +299498,7 @@ module \ls180 update \main_libresocsim_eventmanager_storage $0\main_libresocsim_eventmanager_storage[0:0] update \main_libresocsim_eventmanager_re $0\main_libresocsim_eventmanager_re[0:0] update \main_libresocsim_value $0\main_libresocsim_value[31:0] - update \main_interface0_ram_bus_ack $0\main_interface0_ram_bus_ack[0:0] - update \main_interface1_ram_bus_ack $0\main_interface1_ram_bus_ack[0:0] - update \main_interface2_ram_bus_ack $0\main_interface2_ram_bus_ack[0:0] - update \main_interface3_ram_bus_ack $0\main_interface3_ram_bus_ack[0:0] + update \main_ram_bus_ram_bus_ack $0\main_ram_bus_ram_bus_ack[0:0] update \main_converter0_counter $0\main_converter0_counter[0:0] update \main_converter0_dat_r $0\main_converter0_dat_r[63:0] update \main_converter1_counter $0\main_converter1_counter[0:0] @@ -302881,7 +299831,7 @@ module \ls180 update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] update \builder_grant $0\builder_grant[2:0] - update \builder_slave_sel_r $0\builder_slave_sel_r[12:0] + update \builder_slave_sel_r $0\builder_slave_sel_r[5:0] update \builder_count $0\builder_count[19:0] update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] @@ -302934,918 +299884,846 @@ module \ls180 update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] end - attribute \src "ls180.v:784.11-784.68" - process $proc$ls180.v:784$3381 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:785.5-785.64" - process $proc$ls180.v:785$3382 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:786.11-786.70" - process $proc$ls180.v:786$3383 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:787.11-787.70" - process $proc$ls180.v:787$3384 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:788.11-788.73" - process $proc$ls180.v:788$3385 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:809.5-809.59" - process $proc$ls180.v:809$3386 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:811.5-811.59" - process $proc$ls180.v:811$3387 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:812.5-812.58" - process $proc$ls180.v:812$3388 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:813.5-813.64" - process $proc$ls180.v:813$3389 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:814.12-814.74" - process $proc$ls180.v:814$3390 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:815.12-815.47" - process $proc$ls180.v:815$3391 - assign { } { } - assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] - end - attribute \src "ls180.v:816.5-816.46" - process $proc$ls180.v:816$3392 - assign { } { } - assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] - end - attribute \src "ls180.v:818.5-818.44" - process $proc$ls180.v:818$3393 - assign { } { } - assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] - end - attribute \src "ls180.v:819.5-819.45" - process $proc$ls180.v:819$3394 - assign { } { } - assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] - end - attribute \src "ls180.v:820.5-820.54" - process $proc$ls180.v:820$3395 - assign { } { } - assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:822.32-822.76" - process $proc$ls180.v:822$3396 - assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - end - attribute \src "ls180.v:823.11-823.55" - process $proc$ls180.v:823$3397 - assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] - end - attribute \src "ls180.v:825.32-825.75" - process $proc$ls180.v:825$3398 - assign { } { } - assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:827.32-827.76" - process $proc$ls180.v:827$3399 - assign { } { } - assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:830.5-830.44" - process $proc$ls180.v:830$3400 - assign { } { } - assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] - sync init - end - attribute \src "ls180.v:831.5-831.45" - process $proc$ls180.v:831$3401 - assign { } { } - assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] - sync init - end - attribute \src "ls180.v:832.5-832.43" - process $proc$ls180.v:832$3402 - assign { } { } - assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] - sync init - end - attribute \src "ls180.v:833.5-833.48" - process $proc$ls180.v:833$3403 - assign { } { } - assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] - sync init - end - attribute \src "ls180.v:835.5-835.43" - process $proc$ls180.v:835$3404 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] - sync init - end - attribute \src "ls180.v:838.5-838.49" - process $proc$ls180.v:838$3405 - assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:839.5-839.49" - process $proc$ls180.v:839$3406 - assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:840.5-840.48" - process $proc$ls180.v:840$3407 - assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - end - attribute \src "ls180.v:844.11-844.46" - process $proc$ls180.v:844$3408 + attribute \src "ls180.v:755.11-755.46" + process $proc$ls180.v:755$3147 assign { } { } assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 sync always sync init update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] end - attribute \src "ls180.v:846.11-846.45" - process $proc$ls180.v:846$3409 + attribute \src "ls180.v:757.11-757.45" + process $proc$ls180.v:757$3148 assign { } { } assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 sync always sync init update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] end - attribute \src "ls180.v:848.5-848.44" - process $proc$ls180.v:848$3410 + attribute \src "ls180.v:759.5-759.44" + process $proc$ls180.v:759$3149 assign { } { } assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 sync always sync init update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] end - attribute \src "ls180.v:849.5-849.45" - process $proc$ls180.v:849$3411 + attribute \src "ls180.v:760.5-760.45" + process $proc$ls180.v:760$3150 assign { } { } assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 sync always sync init update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] end - attribute \src "ls180.v:85.11-85.52" - process $proc$ls180.v:85$3136 - assign { } { } - assign $0\main_libresocsim_libresoc_ibus_cti[2:0] 3'000 - sync always - update \main_libresocsim_libresoc_ibus_cti $0\main_libresocsim_libresoc_ibus_cti[2:0] - sync init - end - attribute \src "ls180.v:851.5-851.48" - process $proc$ls180.v:851$3412 + attribute \src "ls180.v:762.5-762.48" + process $proc$ls180.v:762$3151 assign { } { } assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 sync always sync init update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] end - attribute \src "ls180.v:853.5-853.43" - process $proc$ls180.v:853$3413 + attribute \src "ls180.v:764.5-764.43" + process $proc$ls180.v:764$3152 assign { } { } assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] end - attribute \src "ls180.v:856.5-856.49" - process $proc$ls180.v:856$3414 + attribute \src "ls180.v:767.5-767.49" + process $proc$ls180.v:767$3153 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:857.5-857.49" - process $proc$ls180.v:857$3415 + attribute \src "ls180.v:768.5-768.49" + process $proc$ls180.v:768$3154 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "ls180.v:858.5-858.48" - process $proc$ls180.v:858$3416 + attribute \src "ls180.v:769.5-769.48" + process $proc$ls180.v:769$3155 assign { } { } assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 sync always sync init update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:86.11-86.52" - process $proc$ls180.v:86$3137 - assign { } { } - assign $0\main_libresocsim_libresoc_ibus_bte[1:0] 2'00 - sync always - update \main_libresocsim_libresoc_ibus_bte $0\main_libresocsim_libresoc_ibus_bte[1:0] - sync init - end - attribute \src "ls180.v:862.11-862.46" - process $proc$ls180.v:862$3417 + attribute \src "ls180.v:773.11-773.46" + process $proc$ls180.v:773$3156 assign { } { } assign $1\main_sdram_choose_req_valids[3:0] 4'0000 sync always sync init update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] end - attribute \src "ls180.v:864.11-864.45" - process $proc$ls180.v:864$3418 + attribute \src "ls180.v:775.11-775.45" + process $proc$ls180.v:775$3157 assign { } { } assign $1\main_sdram_choose_req_grant[1:0] 2'00 sync always sync init update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] end - attribute \src "ls180.v:866.12-866.36" - process $proc$ls180.v:866$3419 + attribute \src "ls180.v:777.12-777.36" + process $proc$ls180.v:777$3158 assign { } { } assign $0\main_sdram_nop_a[12:0] 13'0000000000000 sync always update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] sync init end - attribute \src "ls180.v:867.11-867.35" - process $proc$ls180.v:867$3420 + attribute \src "ls180.v:778.11-778.35" + process $proc$ls180.v:778$3159 assign { } { } assign $0\main_sdram_nop_ba[1:0] 2'00 sync always update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] sync init end - attribute \src "ls180.v:868.11-868.40" - process $proc$ls180.v:868$3421 + attribute \src "ls180.v:779.11-779.40" + process $proc$ls180.v:779$3160 assign { } { } assign $1\main_sdram_steerer_sel[1:0] 2'00 sync always sync init update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] end - attribute \src "ls180.v:869.5-869.31" - process $proc$ls180.v:869$3422 + attribute \src "ls180.v:780.5-780.31" + process $proc$ls180.v:780$3161 assign { } { } assign $0\main_sdram_steerer0[0:0] 1'1 sync always update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] sync init end - attribute \src "ls180.v:870.5-870.31" - process $proc$ls180.v:870$3423 + attribute \src "ls180.v:781.5-781.31" + process $proc$ls180.v:781$3162 assign { } { } assign $0\main_sdram_steerer1[0:0] 1'1 sync always update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] sync init end - attribute \src "ls180.v:872.32-872.63" - process $proc$ls180.v:872$3424 + attribute \src "ls180.v:783.32-783.63" + process $proc$ls180.v:783$3163 assign { } { } assign $0\main_sdram_trrdcon_ready[0:0] 1'1 sync always update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] sync init end - attribute \src "ls180.v:874.32-874.63" - process $proc$ls180.v:874$3425 + attribute \src "ls180.v:785.32-785.63" + process $proc$ls180.v:785$3164 assign { } { } assign $0\main_sdram_tfawcon_ready[0:0] 1'1 sync always update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] sync init end - attribute \src "ls180.v:876.32-876.63" - process $proc$ls180.v:876$3426 + attribute \src "ls180.v:787.32-787.63" + process $proc$ls180.v:787$3165 assign { } { } assign $1\main_sdram_tccdcon_ready[0:0] 1'0 sync always sync init update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] end - attribute \src "ls180.v:877.5-877.36" - process $proc$ls180.v:877$3427 + attribute \src "ls180.v:788.5-788.36" + process $proc$ls180.v:788$3166 assign { } { } assign $1\main_sdram_tccdcon_count[0:0] 1'0 sync always sync init update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] end - attribute \src "ls180.v:879.32-879.63" - process $proc$ls180.v:879$3428 + attribute \src "ls180.v:790.32-790.63" + process $proc$ls180.v:790$3167 assign { } { } assign $1\main_sdram_twtrcon_ready[0:0] 1'0 sync always sync init update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] end - attribute \src "ls180.v:88.12-88.58" - process $proc$ls180.v:88$3138 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_libresoc_xics_icp_adr $1\main_libresocsim_libresoc_xics_icp_adr[29:0] - end - attribute \src "ls180.v:880.11-880.42" - process $proc$ls180.v:880$3429 + attribute \src "ls180.v:791.11-791.42" + process $proc$ls180.v:791$3168 assign { } { } assign $1\main_sdram_twtrcon_count[2:0] 3'000 sync always sync init update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] end - attribute \src "ls180.v:883.5-883.26" - process $proc$ls180.v:883$3430 + attribute \src "ls180.v:794.5-794.26" + process $proc$ls180.v:794$3169 assign { } { } assign $1\main_sdram_en0[0:0] 1'0 sync always sync init update \main_sdram_en0 $1\main_sdram_en0[0:0] end - attribute \src "ls180.v:885.11-885.34" - process $proc$ls180.v:885$3431 + attribute \src "ls180.v:796.11-796.34" + process $proc$ls180.v:796$3170 assign { } { } assign $1\main_sdram_time0[4:0] 5'00000 sync always sync init update \main_sdram_time0 $1\main_sdram_time0[4:0] end - attribute \src "ls180.v:886.5-886.26" - process $proc$ls180.v:886$3432 + attribute \src "ls180.v:797.5-797.26" + process $proc$ls180.v:797$3171 assign { } { } assign $1\main_sdram_en1[0:0] 1'0 sync always sync init update \main_sdram_en1 $1\main_sdram_en1[0:0] end - attribute \src "ls180.v:888.11-888.34" - process $proc$ls180.v:888$3433 + attribute \src "ls180.v:799.11-799.34" + process $proc$ls180.v:799$3172 assign { } { } assign $1\main_sdram_time1[3:0] 4'0000 sync always sync init update \main_sdram_time1 $1\main_sdram_time1[3:0] end - attribute \src "ls180.v:89.12-89.60" - process $proc$ls180.v:89$3139 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_libresoc_xics_icp_dat_w $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] - end - attribute \src "ls180.v:903.12-903.37" - process $proc$ls180.v:903$3434 + attribute \src "ls180.v:814.12-814.37" + process $proc$ls180.v:814$3173 assign { } { } assign $1\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 sync always sync init update \main_wb_sdram_adr $1\main_wb_sdram_adr[29:0] end - attribute \src "ls180.v:904.12-904.39" - process $proc$ls180.v:904$3435 + attribute \src "ls180.v:815.12-815.39" + process $proc$ls180.v:815$3174 assign { } { } assign $1\main_wb_sdram_dat_w[31:0] 0 sync always sync init update \main_wb_sdram_dat_w $1\main_wb_sdram_dat_w[31:0] end - attribute \src "ls180.v:906.11-906.35" - process $proc$ls180.v:906$3436 + attribute \src "ls180.v:817.11-817.35" + process $proc$ls180.v:817$3175 assign { } { } assign $1\main_wb_sdram_sel[3:0] 4'0000 sync always sync init update \main_wb_sdram_sel $1\main_wb_sdram_sel[3:0] end - attribute \src "ls180.v:907.5-907.29" - process $proc$ls180.v:907$3437 + attribute \src "ls180.v:818.5-818.29" + process $proc$ls180.v:818$3176 assign { } { } assign $1\main_wb_sdram_cyc[0:0] 1'0 sync always sync init update \main_wb_sdram_cyc $1\main_wb_sdram_cyc[0:0] end - attribute \src "ls180.v:908.5-908.29" - process $proc$ls180.v:908$3438 + attribute \src "ls180.v:819.5-819.29" + process $proc$ls180.v:819$3177 assign { } { } assign $1\main_wb_sdram_stb[0:0] 1'0 sync always sync init update \main_wb_sdram_stb $1\main_wb_sdram_stb[0:0] end - attribute \src "ls180.v:909.5-909.29" - process $proc$ls180.v:909$3439 + attribute \src "ls180.v:820.5-820.29" + process $proc$ls180.v:820$3178 assign { } { } assign $1\main_wb_sdram_ack[0:0] 1'0 sync always sync init update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] end - attribute \src "ls180.v:91.11-91.56" - process $proc$ls180.v:91$3140 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_libresoc_xics_icp_sel $1\main_libresocsim_libresoc_xics_icp_sel[3:0] - end - attribute \src "ls180.v:910.5-910.28" - process $proc$ls180.v:910$3440 + attribute \src "ls180.v:821.5-821.28" + process $proc$ls180.v:821$3179 assign { } { } assign $1\main_wb_sdram_we[0:0] 1'0 sync always sync init update \main_wb_sdram_we $1\main_wb_sdram_we[0:0] end - attribute \src "ls180.v:917.5-917.54" - process $proc$ls180.v:917$3441 + attribute \src "ls180.v:828.5-828.54" + process $proc$ls180.v:828$3180 assign { } { } assign $1\main_socbushandler_converted_interface_ack[0:0] 1'0 sync always sync init update \main_socbushandler_converted_interface_ack $1\main_socbushandler_converted_interface_ack[0:0] end - attribute \src "ls180.v:92.5-92.50" - process $proc$ls180.v:92$3141 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_xics_icp_cyc $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] - end - attribute \src "ls180.v:921.5-921.54" - process $proc$ls180.v:921$3442 + attribute \src "ls180.v:832.5-832.54" + process $proc$ls180.v:832$3181 assign { } { } assign $0\main_socbushandler_converted_interface_err[0:0] 1'0 sync always update \main_socbushandler_converted_interface_err $0\main_socbushandler_converted_interface_err[0:0] sync init end - attribute \src "ls180.v:922.5-922.35" - process $proc$ls180.v:922$3443 + attribute \src "ls180.v:833.5-833.35" + process $proc$ls180.v:833$3182 assign { } { } assign $1\main_socbushandler_skip[0:0] 1'0 sync always sync init update \main_socbushandler_skip $1\main_socbushandler_skip[0:0] end - attribute \src "ls180.v:923.5-923.38" - process $proc$ls180.v:923$3444 + attribute \src "ls180.v:834.5-834.38" + process $proc$ls180.v:834$3183 assign { } { } assign $1\main_socbushandler_counter[0:0] 1'0 sync always sync init update \main_socbushandler_counter $1\main_socbushandler_counter[0:0] end - attribute \src "ls180.v:925.12-925.44" - process $proc$ls180.v:925$3445 + attribute \src "ls180.v:836.12-836.44" + process $proc$ls180.v:836$3184 assign { } { } assign $1\main_socbushandler_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \main_socbushandler_dat_r $1\main_socbushandler_dat_r[63:0] end - attribute \src "ls180.v:926.12-926.40" - process $proc$ls180.v:926$3446 + attribute \src "ls180.v:837.12-837.40" + process $proc$ls180.v:837$3185 assign { } { } assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 sync always sync init update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] end - attribute \src "ls180.v:927.12-927.42" - process $proc$ls180.v:927$3447 + attribute \src "ls180.v:838.12-838.42" + process $proc$ls180.v:838$3186 assign { } { } assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 sync always sync init update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:929.11-929.38" - process $proc$ls180.v:929$3448 + attribute \src "ls180.v:840.11-840.38" + process $proc$ls180.v:840$3187 assign { } { } assign $1\main_litedram_wb_sel[1:0] 2'00 sync always sync init update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] end - attribute \src "ls180.v:93.5-93.50" - process $proc$ls180.v:93$3142 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_xics_icp_stb $1\main_libresocsim_libresoc_xics_icp_stb[0:0] - end - attribute \src "ls180.v:930.5-930.32" - process $proc$ls180.v:930$3449 + attribute \src "ls180.v:841.5-841.32" + process $proc$ls180.v:841$3188 assign { } { } assign $1\main_litedram_wb_cyc[0:0] 1'0 sync always sync init update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] end - attribute \src "ls180.v:931.5-931.32" - process $proc$ls180.v:931$3450 + attribute \src "ls180.v:842.5-842.32" + process $proc$ls180.v:842$3189 assign { } { } assign $1\main_litedram_wb_stb[0:0] 1'0 sync always sync init update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] end - attribute \src "ls180.v:933.5-933.31" - process $proc$ls180.v:933$3451 + attribute \src "ls180.v:844.5-844.31" + process $proc$ls180.v:844$3190 assign { } { } assign $1\main_litedram_wb_we[0:0] 1'0 sync always sync init update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] end - attribute \src "ls180.v:934.5-934.31" - process $proc$ls180.v:934$3452 + attribute \src "ls180.v:845.5-845.31" + process $proc$ls180.v:845$3191 assign { } { } assign $1\main_converter_skip[0:0] 1'0 sync always sync init update \main_converter_skip $1\main_converter_skip[0:0] end - attribute \src "ls180.v:935.5-935.34" - process $proc$ls180.v:935$3453 + attribute \src "ls180.v:846.5-846.34" + process $proc$ls180.v:846$3192 assign { } { } assign $1\main_converter_counter[0:0] 1'0 sync always sync init update \main_converter_counter $1\main_converter_counter[0:0] end - attribute \src "ls180.v:937.12-937.40" - process $proc$ls180.v:937$3454 + attribute \src "ls180.v:848.12-848.40" + process $proc$ls180.v:848$3193 assign { } { } assign $1\main_converter_dat_r[31:0] 0 sync always sync init update \main_converter_dat_r $1\main_converter_dat_r[31:0] end - attribute \src "ls180.v:938.5-938.29" - process $proc$ls180.v:938$3455 + attribute \src "ls180.v:849.5-849.29" + process $proc$ls180.v:849$3194 assign { } { } assign $1\main_cmd_consumed[0:0] 1'0 sync always sync init update \main_cmd_consumed $1\main_cmd_consumed[0:0] end - attribute \src "ls180.v:939.5-939.31" - process $proc$ls180.v:939$3456 + attribute \src "ls180.v:85.11-85.52" + process $proc$ls180.v:85$2884 + assign { } { } + assign $0\main_libresocsim_libresoc_ibus_cti[2:0] 3'000 + sync always + update \main_libresocsim_libresoc_ibus_cti $0\main_libresocsim_libresoc_ibus_cti[2:0] + sync init + end + attribute \src "ls180.v:850.5-850.31" + process $proc$ls180.v:850$3195 assign { } { } assign $1\main_wdata_consumed[0:0] 1'0 sync always sync init update \main_wdata_consumed $1\main_wdata_consumed[0:0] end - attribute \src "ls180.v:943.12-943.47" - process $proc$ls180.v:943$3457 + attribute \src "ls180.v:854.12-854.47" + process $proc$ls180.v:854$3196 assign { } { } assign $1\main_uart_phy_storage[31:0] 9895604 sync always sync init update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] end - attribute \src "ls180.v:944.5-944.28" - process $proc$ls180.v:944$3458 + attribute \src "ls180.v:855.5-855.28" + process $proc$ls180.v:855$3197 assign { } { } assign $1\main_uart_phy_re[0:0] 1'0 sync always sync init update \main_uart_phy_re $1\main_uart_phy_re[0:0] end - attribute \src "ls180.v:946.5-946.36" - process $proc$ls180.v:946$3459 + attribute \src "ls180.v:857.5-857.36" + process $proc$ls180.v:857$3198 assign { } { } assign $1\main_uart_phy_sink_ready[0:0] 1'0 sync always sync init update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] end - attribute \src "ls180.v:95.5-95.49" - process $proc$ls180.v:95$3143 + attribute \src "ls180.v:86.11-86.52" + process $proc$ls180.v:86$2885 assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 + assign $0\main_libresocsim_libresoc_ibus_bte[1:0] 2'00 sync always + update \main_libresocsim_libresoc_ibus_bte $0\main_libresocsim_libresoc_ibus_bte[1:0] sync init - update \main_libresocsim_libresoc_xics_icp_we $1\main_libresocsim_libresoc_xics_icp_we[0:0] end - attribute \src "ls180.v:950.5-950.39" - process $proc$ls180.v:950$3460 + attribute \src "ls180.v:861.5-861.39" + process $proc$ls180.v:861$3199 assign { } { } assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 sync always sync init update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] end - attribute \src "ls180.v:951.12-951.54" - process $proc$ls180.v:951$3461 + attribute \src "ls180.v:862.12-862.54" + process $proc$ls180.v:862$3200 assign { } { } assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 sync always sync init update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] end - attribute \src "ls180.v:952.11-952.38" - process $proc$ls180.v:952$3462 + attribute \src "ls180.v:863.11-863.38" + process $proc$ls180.v:863$3201 assign { } { } assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 sync always sync init update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] end - attribute \src "ls180.v:953.11-953.43" - process $proc$ls180.v:953$3463 + attribute \src "ls180.v:864.11-864.43" + process $proc$ls180.v:864$3202 assign { } { } assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 sync always sync init update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] end - attribute \src "ls180.v:954.5-954.33" - process $proc$ls180.v:954$3464 + attribute \src "ls180.v:865.5-865.33" + process $proc$ls180.v:865$3203 assign { } { } assign $1\main_uart_phy_tx_busy[0:0] 1'0 sync always sync init update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] end - attribute \src "ls180.v:955.5-955.38" - process $proc$ls180.v:955$3465 + attribute \src "ls180.v:866.5-866.38" + process $proc$ls180.v:866$3204 assign { } { } assign $1\main_uart_phy_source_valid[0:0] 1'0 sync always sync init update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] end - attribute \src "ls180.v:957.5-957.38" - process $proc$ls180.v:957$3466 + attribute \src "ls180.v:868.5-868.38" + process $proc$ls180.v:868$3205 assign { } { } assign $0\main_uart_phy_source_first[0:0] 1'0 sync always update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0] sync init end - attribute \src "ls180.v:958.5-958.37" - process $proc$ls180.v:958$3467 + attribute \src "ls180.v:869.5-869.37" + process $proc$ls180.v:869$3206 assign { } { } assign $0\main_uart_phy_source_last[0:0] 1'0 sync always update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0] sync init end - attribute \src "ls180.v:959.11-959.51" - process $proc$ls180.v:959$3468 + attribute \src "ls180.v:870.11-870.51" + process $proc$ls180.v:870$3207 assign { } { } assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 sync always sync init update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] end - attribute \src "ls180.v:960.5-960.39" - process $proc$ls180.v:960$3469 + attribute \src "ls180.v:871.5-871.39" + process $proc$ls180.v:871$3208 assign { } { } assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 sync always sync init update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] end - attribute \src "ls180.v:961.12-961.54" - process $proc$ls180.v:961$3470 + attribute \src "ls180.v:872.12-872.54" + process $proc$ls180.v:872$3209 assign { } { } assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 sync always sync init update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] end - attribute \src "ls180.v:963.5-963.30" - process $proc$ls180.v:963$3471 + attribute \src "ls180.v:874.5-874.30" + process $proc$ls180.v:874$3210 assign { } { } assign $1\main_uart_phy_rx_r[0:0] 1'0 sync always sync init update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] end - attribute \src "ls180.v:964.11-964.38" - process $proc$ls180.v:964$3472 + attribute \src "ls180.v:875.11-875.38" + process $proc$ls180.v:875$3211 assign { } { } assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 sync always sync init update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] end - attribute \src "ls180.v:965.11-965.43" - process $proc$ls180.v:965$3473 + attribute \src "ls180.v:876.11-876.43" + process $proc$ls180.v:876$3212 assign { } { } assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 sync always sync init update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] end - attribute \src "ls180.v:966.5-966.33" - process $proc$ls180.v:966$3474 + attribute \src "ls180.v:877.5-877.33" + process $proc$ls180.v:877$3213 assign { } { } assign $1\main_uart_phy_rx_busy[0:0] 1'0 sync always sync init update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] end - attribute \src "ls180.v:97.12-97.58" - process $proc$ls180.v:97$3144 + attribute \src "ls180.v:88.12-88.58" + process $proc$ls180.v:88$2886 assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 + assign $1\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 sync always sync init - update \main_libresocsim_libresoc_xics_ics_adr $1\main_libresocsim_libresoc_xics_ics_adr[29:0] + update \main_libresocsim_libresoc_xics_icp_adr $1\main_libresocsim_libresoc_xics_icp_adr[29:0] end - attribute \src "ls180.v:977.5-977.32" - process $proc$ls180.v:977$3475 + attribute \src "ls180.v:888.5-888.32" + process $proc$ls180.v:888$3214 assign { } { } assign $1\main_uart_tx_pending[0:0] 1'0 sync always sync init update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] end - attribute \src "ls180.v:979.5-979.30" - process $proc$ls180.v:979$3476 + attribute \src "ls180.v:89.12-89.60" + process $proc$ls180.v:89$2887 assign { } { } - assign $1\main_uart_tx_clear[0:0] 1'0 + assign $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 sync always sync init - update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] + update \main_libresocsim_libresoc_xics_icp_dat_w $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] end - attribute \src "ls180.v:98.12-98.60" - process $proc$ls180.v:98$3145 + attribute \src "ls180.v:890.5-890.30" + process $proc$ls180.v:890$3215 assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 + assign $1\main_uart_tx_clear[0:0] 1'0 sync always sync init - update \main_libresocsim_libresoc_xics_ics_dat_w $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] end - attribute \src "ls180.v:980.5-980.36" - process $proc$ls180.v:980$3477 + attribute \src "ls180.v:891.5-891.36" + process $proc$ls180.v:891$3216 assign { } { } assign $1\main_uart_tx_old_trigger[0:0] 1'0 sync always sync init update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] end - attribute \src "ls180.v:982.5-982.32" - process $proc$ls180.v:982$3478 + attribute \src "ls180.v:893.5-893.32" + process $proc$ls180.v:893$3217 assign { } { } assign $1\main_uart_rx_pending[0:0] 1'0 sync always sync init update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] end - attribute \src "ls180.v:984.5-984.30" - process $proc$ls180.v:984$3479 + attribute \src "ls180.v:895.5-895.30" + process $proc$ls180.v:895$3218 assign { } { } assign $1\main_uart_rx_clear[0:0] 1'0 sync always sync init update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] end - attribute \src "ls180.v:985.5-985.36" - process $proc$ls180.v:985$3480 + attribute \src "ls180.v:896.5-896.36" + process $proc$ls180.v:896$3219 assign { } { } assign $1\main_uart_rx_old_trigger[0:0] 1'0 sync always sync init update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] end - attribute \src "ls180.v:989.11-989.49" - process $proc$ls180.v:989$3481 + attribute \src "ls180.v:900.11-900.49" + process $proc$ls180.v:900$3220 assign { } { } assign $1\main_uart_eventmanager_status_w[1:0] 2'00 sync always sync init update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] end - attribute \src "ls180.v:993.11-993.50" - process $proc$ls180.v:993$3482 + attribute \src "ls180.v:904.11-904.50" + process $proc$ls180.v:904$3221 assign { } { } assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 sync always sync init update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] end - attribute \src "ls180.v:994.11-994.48" - process $proc$ls180.v:994$3483 + attribute \src "ls180.v:905.11-905.48" + process $proc$ls180.v:905$3222 assign { } { } assign $1\main_uart_eventmanager_storage[1:0] 2'00 sync always sync init update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] end - attribute \src "ls180.v:995.5-995.37" - process $proc$ls180.v:995$3484 + attribute \src "ls180.v:906.5-906.37" + process $proc$ls180.v:906$3223 assign { } { } assign $1\main_uart_eventmanager_re[0:0] 1'0 sync always sync init update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] end + attribute \src "ls180.v:91.11-91.56" + process $proc$ls180.v:91$2888 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_sel $1\main_libresocsim_libresoc_xics_icp_sel[3:0] + end + attribute \src "ls180.v:92.5-92.50" + process $proc$ls180.v:92$2889 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_cyc $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] + end + attribute \src "ls180.v:923.5-923.40" + process $proc$ls180.v:923$3224 + assign { } { } + assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 + sync always + update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] + sync init + end + attribute \src "ls180.v:924.5-924.39" + process $proc$ls180.v:924$3225 + assign { } { } + assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 + sync always + update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] + sync init + end + attribute \src "ls180.v:93.5-93.50" + process $proc$ls180.v:93$2890 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_stb $1\main_libresocsim_libresoc_xics_icp_stb[0:0] + end + attribute \src "ls180.v:932.5-932.38" + process $proc$ls180.v:932$3226 + assign { } { } + assign $1\main_uart_tx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] + end + attribute \src "ls180.v:939.11-939.42" + process $proc$ls180.v:939$3227 + assign { } { } + assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] + end + attribute \src "ls180.v:940.5-940.37" + process $proc$ls180.v:940$3228 + assign { } { } + assign $0\main_uart_tx_fifo_replace[0:0] 1'0 + sync always + update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:941.11-941.43" + process $proc$ls180.v:941$3229 + assign { } { } + assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] + end + attribute \src "ls180.v:942.11-942.43" + process $proc$ls180.v:942$3230 + assign { } { } + assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] + end + attribute \src "ls180.v:943.11-943.46" + process $proc$ls180.v:943$3231 + assign { } { } + assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:95.5-95.49" + process $proc$ls180.v:95$2891 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_we $1\main_libresocsim_libresoc_xics_icp_we[0:0] + end + attribute \src "ls180.v:969.5-969.38" + process $proc$ls180.v:969$3232 + assign { } { } + assign $1\main_uart_rx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] + end + attribute \src "ls180.v:97.12-97.58" + process $proc$ls180.v:97$2892 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_adr $1\main_libresocsim_libresoc_xics_ics_adr[29:0] + end + attribute \src "ls180.v:976.11-976.42" + process $proc$ls180.v:976$3233 + assign { } { } + assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] + end + attribute \src "ls180.v:977.5-977.37" + process $proc$ls180.v:977$3234 + assign { } { } + assign $0\main_uart_rx_fifo_replace[0:0] 1'0 + sync always + update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:978.11-978.43" + process $proc$ls180.v:978$3235 + assign { } { } + assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] + end + attribute \src "ls180.v:979.11-979.43" + process $proc$ls180.v:979$3236 + assign { } { } + assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] + end + attribute \src "ls180.v:98.12-98.60" + process $proc$ls180.v:98$2893 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_dat_w $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + end + attribute \src "ls180.v:980.11-980.46" + process $proc$ls180.v:980$3237 + assign { } { } + assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:995.5-995.27" + process $proc$ls180.v:995$3238 + assign { } { } + assign $0\main_uart_reset[0:0] 1'0 + sync always + update \main_uart_reset $0\main_uart_reset[0:0] + sync init + end + attribute \src "ls180.v:996.12-996.53" + process $proc$ls180.v:996$3239 + assign { } { } + assign $0\main_gpiotristateasic0_oe_storage[15:0] 16'0000000000000000 + sync always + update \main_gpiotristateasic0_oe_storage $0\main_gpiotristateasic0_oe_storage[15:0] + sync init + end + attribute \src "ls180.v:997.12-997.49" + process $proc$ls180.v:997$3240 + assign { } { } + assign $1\main_gpiotristateasic0_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic0_status $1\main_gpiotristateasic0_status[15:0] + end + attribute \src "ls180.v:998.12-998.54" + process $proc$ls180.v:998$3241 + assign { } { } + assign $0\main_gpiotristateasic0_out_storage[15:0] 16'0000000000000000 + sync always + update \main_gpiotristateasic0_out_storage $0\main_gpiotristateasic0_out_storage[15:0] + sync init + end connect \main_libresocsim_libresoc_reset \main_libresocsim_reset connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i connect \sys_pll_18_o \main_libresocsim_libresoc_pll_18_o @@ -303866,34 +300744,25 @@ module \ls180 connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 connect \main_libresocsim_bus_error \builder_error - connect \main_converter0_reset $not$ls180.v:2893$50_Y + connect \main_converter0_reset $not$ls180.v:2804$26_Y connect \main_interface0_converted_interface_dat_r { \main_libresocsim_libresoc_xics_icp_dat_r \main_converter0_dat_r [63:32] } - connect \main_converter1_reset $not$ls180.v:2953$61_Y + connect \main_converter1_reset $not$ls180.v:2864$37_Y connect \main_interface1_converted_interface_dat_r { \main_libresocsim_libresoc_xics_ics_dat_r \main_converter1_dat_r [63:32] } - connect \main_socbushandler_reset $not$ls180.v:3013$72_Y + connect \main_socbushandler_reset $not$ls180.v:2924$48_Y connect \main_socbushandler_converted_interface_dat_r { \main_wb_sdram_dat_r \main_socbushandler_dat_r [63:32] } connect \main_libresocsim_reset \main_libresocsim_reset_re connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors - connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [5:0] + connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [3:0] connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w - connect \main_libresocsim_zero_trigger $ne$ls180.v:3089$108_Y + connect \main_libresocsim_zero_trigger $ne$ls180.v:3000$84_Y connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending - connect \main_libresocsim_irq $and$ls180.v:3098$111_Y + connect \main_libresocsim_irq $and$ls180.v:3009$87_Y connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger - connect \main_sram0_adr \main_interface0_ram_bus_adr [5:0] - connect \main_interface0_ram_bus_dat_r \main_sram0_dat_r - connect \main_sram0_dat_w \main_interface0_ram_bus_dat_w - connect \main_sram1_adr \main_interface1_ram_bus_adr [5:0] - connect \main_interface1_ram_bus_dat_r \main_sram1_dat_r - connect \main_sram1_dat_w \main_interface1_ram_bus_dat_w - connect \main_sram2_adr \main_interface2_ram_bus_adr [5:0] - connect \main_interface2_ram_bus_dat_r \main_sram2_dat_r - connect \main_sram2_dat_w \main_interface2_ram_bus_dat_w - connect \main_sram3_adr \main_interface3_ram_bus_adr [5:0] - connect \main_interface3_ram_bus_dat_r \main_sram3_dat_r - connect \main_sram3_dat_w \main_interface3_ram_bus_dat_w + connect \main_ram_adr \main_ram_bus_ram_bus_adr [3:0] + connect \main_ram_bus_ram_bus_dat_r \main_ram_dat_r + connect \main_ram_dat_w \main_ram_bus_ram_bus_dat_w connect \sys_clk_1 \sys_clk connect \por_clk \sys_clk connect \sys_rst_1 \main_int_rst @@ -303934,8 +300803,8 @@ module \ls180 connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n connect \main_sdram_inti_p0_address \main_sdram_address_storage connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage - connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3268$218_Y - connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3269$219_Y + connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3137$119_Y + connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3138$120_Y connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage connect \main_sdram_inti_p0_wrdata_mask 2'00 connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid @@ -303966,14 +300835,14 @@ module \ls180 connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid - connect \main_sdram_timer_wait $not$ls180.v:3300$220_Y + connect \main_sdram_timer_wait $not$ls180.v:3169$121_Y connect \main_sdram_postponer_req_i \main_sdram_timer_done0 connect \main_sdram_wants_refresh \main_sdram_postponer_req_o - connect \main_sdram_timer_done1 $eq$ls180.v:3303$221_Y + connect \main_sdram_timer_done1 $eq$ls180.v:3172$122_Y connect \main_sdram_timer_done0 \main_sdram_timer_done1 connect \main_sdram_timer_count0 \main_sdram_timer_count1 - connect \main_sdram_sequencer_start1 $or$ls180.v:3306$223_Y - connect \main_sdram_sequencer_done0 $and$ls180.v:3307$225_Y + connect \main_sdram_sequencer_start1 $or$ls180.v:3175$124_Y + connect \main_sdram_sequencer_done0 $and$ls180.v:3176$126_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we @@ -303984,13 +300853,13 @@ module \ls180 connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3349$227_Y - connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3350$228_Y - connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3351$229_Y + connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3218$128_Y + connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3219$129_Y + connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3220$130_Y connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 - connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3361$234_Y - connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3362$236_Y - connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3363$238_Y + connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3230$135_Y + connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3231$137_Y + connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3232$139_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable @@ -304006,13 +300875,13 @@ module \ls180 connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3395$246_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3396$247_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3264$147_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3265$148_Y connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3399$248_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3400$249_Y - connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3401$251_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3268$149_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3269$150_Y + connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3270$152_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we @@ -304023,13 +300892,13 @@ module \ls180 connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3506$257_Y - connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3507$258_Y - connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3508$259_Y + connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3375$158_Y + connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3376$159_Y + connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3377$160_Y connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 - connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3518$264_Y - connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3519$266_Y - connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3520$268_Y + connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3387$165_Y + connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3388$167_Y + connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3389$169_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable @@ -304045,13 +300914,13 @@ module \ls180 connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3552$276_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3553$277_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3421$177_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3422$178_Y connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3556$278_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3557$279_Y - connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3558$281_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3425$179_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3426$180_Y + connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3427$182_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we @@ -304062,13 +300931,13 @@ module \ls180 connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3663$287_Y - connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3664$288_Y - connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3665$289_Y + connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3532$188_Y + connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3533$189_Y + connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3534$190_Y connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 - connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3675$294_Y - connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3676$296_Y - connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3677$298_Y + connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3544$195_Y + connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3545$197_Y + connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3546$199_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable @@ -304084,13 +300953,13 @@ module \ls180 connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3709$306_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3710$307_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3578$207_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3579$208_Y connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3713$308_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3714$309_Y - connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3715$311_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3582$209_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3583$210_Y + connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3584$212_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we @@ -304101,13 +300970,13 @@ module \ls180 connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3820$317_Y - connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3821$318_Y - connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3822$319_Y + connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3689$218_Y + connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3690$219_Y + connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3691$220_Y connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 - connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3832$324_Y - connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3833$326_Y - connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3834$328_Y + connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3701$225_Y + connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3702$227_Y + connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3703$229_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable @@ -304123,32 +300992,32 @@ module \ls180 connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3866$336_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3867$337_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3735$237_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3736$238_Y connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3870$338_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3871$339_Y - connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3872$341_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3739$239_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3740$240_Y + connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3741$242_Y connect \main_sdram_choose_req_want_cmds 1'1 - connect \main_sdram_trrdcon_valid $and$ls180.v:3968$352_Y - connect \main_sdram_tfawcon_valid $and$ls180.v:3969$358_Y - connect \main_sdram_ras_allowed $and$ls180.v:3970$359_Y - connect \main_sdram_tccdcon_valid $and$ls180.v:3971$362_Y + connect \main_sdram_trrdcon_valid $and$ls180.v:3837$253_Y + connect \main_sdram_tfawcon_valid $and$ls180.v:3838$259_Y + connect \main_sdram_ras_allowed $and$ls180.v:3839$260_Y + connect \main_sdram_tccdcon_valid $and$ls180.v:3840$263_Y connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready - connect \main_sdram_twtrcon_valid $and$ls180.v:3973$364_Y - connect \main_sdram_read_available $or$ls180.v:3974$371_Y - connect \main_sdram_write_available $or$ls180.v:3975$378_Y - connect \main_sdram_max_time0 $eq$ls180.v:3976$379_Y - connect \main_sdram_max_time1 $eq$ls180.v:3977$380_Y + connect \main_sdram_twtrcon_valid $and$ls180.v:3842$265_Y + connect \main_sdram_read_available $or$ls180.v:3843$272_Y + connect \main_sdram_write_available $or$ls180.v:3844$279_Y + connect \main_sdram_max_time0 $eq$ls180.v:3845$280_Y + connect \main_sdram_max_time1 $eq$ls180.v:3846$281_Y connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid - connect \main_sdram_go_to_refresh $and$ls180.v:3982$383_Y + connect \main_sdram_go_to_refresh $and$ls180.v:3851$284_Y connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata - connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3985$384_Y + connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3854$285_Y connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 @@ -304156,7 +301025,7 @@ module \ls180 connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 - connect \main_sdram_choose_cmd_ce $or$ls180.v:4018$442_Y + connect \main_sdram_choose_cmd_ce $or$ls180.v:3887$343_Y connect \main_sdram_choose_req_request \main_sdram_choose_req_valids connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 @@ -304164,31 +301033,31 @@ module \ls180 connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 - connect \main_sdram_choose_req_ce $or$ls180.v:4087$528_Y + connect \main_sdram_choose_req_ce $or$ls180.v:3956$429_Y connect \main_sdram_dfi_p0_reset_n 1'1 connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 - connect \builder_roundrobin0_request $and$ls180.v:4164$560_Y - connect \builder_roundrobin0_ce $and$ls180.v:4165$563_Y + connect \builder_roundrobin0_request $and$ls180.v:4033$461_Y + connect \builder_roundrobin0_ce $and$ls180.v:4034$464_Y connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 - connect \builder_roundrobin1_request $and$ls180.v:4169$576_Y - connect \builder_roundrobin1_ce $and$ls180.v:4170$579_Y + connect \builder_roundrobin1_request $and$ls180.v:4038$477_Y + connect \builder_roundrobin1_ce $and$ls180.v:4039$480_Y connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 - connect \builder_roundrobin2_request $and$ls180.v:4174$592_Y - connect \builder_roundrobin2_ce $and$ls180.v:4175$595_Y + connect \builder_roundrobin2_request $and$ls180.v:4043$493_Y + connect \builder_roundrobin2_ce $and$ls180.v:4044$496_Y connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 - connect \builder_roundrobin3_request $and$ls180.v:4179$608_Y - connect \builder_roundrobin3_ce $and$ls180.v:4180$611_Y + connect \builder_roundrobin3_request $and$ls180.v:4048$509_Y + connect \builder_roundrobin3_ce $and$ls180.v:4049$512_Y connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 - connect \main_port_cmd_ready $or$ls180.v:4184$675_Y + connect \main_port_cmd_ready $or$ls180.v:4053$576_Y connect \main_port_wdata_ready \builder_new_master_wdata_ready connect \main_port_rdata_valid \builder_new_master_rdata_valid3 connect \main_port_rdata_payload_data \main_sdram_interface_rdata @@ -304196,22 +301065,22 @@ module \ls180 connect \builder_roundrobin1_grant 1'0 connect \builder_roundrobin2_grant 1'0 connect \builder_roundrobin3_grant 1'0 - connect \main_converter_reset $not$ls180.v:4206$677_Y + connect \main_converter_reset $not$ls180.v:4075$578_Y connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } - connect \main_port_cmd_payload_addr $sub$ls180.v:4266$688_Y [23:0] + connect \main_port_cmd_payload_addr $sub$ls180.v:4135$589_Y [23:0] connect \main_port_cmd_payload_we \main_litedram_wb_we connect \main_port_wdata_payload_data \main_litedram_wb_dat_w connect \main_port_wdata_payload_we \main_litedram_wb_sel connect \main_litedram_wb_dat_r \main_port_rdata_payload_data - connect \main_port_flush $not$ls180.v:4271$689_Y - connect \main_port_cmd_last $not$ls180.v:4272$690_Y - connect \main_port_cmd_valid $and$ls180.v:4273$693_Y - connect \main_port_wdata_valid $and$ls180.v:4274$697_Y - connect \main_port_rdata_ready $and$ls180.v:4275$700_Y - connect \main_litedram_wb_ack $and$ls180.v:4276$705_Y - connect \main_ack_cmd $or$ls180.v:4277$707_Y - connect \main_ack_wdata $or$ls180.v:4278$709_Y - connect \main_ack_rdata $and$ls180.v:4279$710_Y + connect \main_port_flush $not$ls180.v:4140$590_Y + connect \main_port_cmd_last $not$ls180.v:4141$591_Y + connect \main_port_cmd_valid $and$ls180.v:4142$594_Y + connect \main_port_wdata_valid $and$ls180.v:4143$598_Y + connect \main_port_rdata_ready $and$ls180.v:4144$601_Y + connect \main_litedram_wb_ack $and$ls180.v:4145$606_Y + connect \main_ack_cmd $or$ls180.v:4146$608_Y + connect \main_ack_wdata $or$ls180.v:4147$610_Y + connect \main_ack_rdata $and$ls180.v:4148$611_Y connect \main_uart_uart_sink_valid \main_uart_phy_source_valid connect \main_uart_phy_source_ready \main_uart_uart_sink_ready connect \main_uart_uart_sink_first \main_uart_phy_source_first @@ -304224,25 +301093,25 @@ module \ls180 connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r - connect \main_uart_txfull_status $not$ls180.v:4292$711_Y - connect \main_uart_txempty_status $not$ls180.v:4293$712_Y + connect \main_uart_txfull_status $not$ls180.v:4161$612_Y + connect \main_uart_txempty_status $not$ls180.v:4162$613_Y connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data - connect \main_uart_tx_trigger $not$ls180.v:4299$713_Y + connect \main_uart_tx_trigger $not$ls180.v:4168$614_Y connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data - connect \main_uart_rxempty_status $not$ls180.v:4305$714_Y - connect \main_uart_rxfull_status $not$ls180.v:4306$715_Y + connect \main_uart_rxempty_status $not$ls180.v:4174$615_Y + connect \main_uart_rxfull_status $not$ls180.v:4175$616_Y connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data - connect \main_uart_rx_fifo_source_ready $or$ls180.v:4308$717_Y - connect \main_uart_rx_trigger $not$ls180.v:4309$718_Y - connect \main_uart_irq $or$ls180.v:4332$727_Y + connect \main_uart_rx_fifo_source_ready $or$ls180.v:4177$618_Y + connect \main_uart_rx_trigger $not$ls180.v:4178$619_Y + connect \main_uart_irq $or$ls180.v:4201$628_Y connect \main_uart_tx_status \main_uart_tx_trigger connect \main_uart_rx_status \main_uart_rx_trigger connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } @@ -304257,16 +301126,16 @@ module \ls180 connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready - connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4347$730_Y - connect \main_uart_tx_fifo_level1 $add$ls180.v:4348$731_Y + connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4216$631_Y + connect \main_uart_tx_fifo_level1 $add$ls180.v:4217$632_Y connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din - connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4358$735_Y - connect \main_uart_tx_fifo_do_read $and$ls180.v:4359$736_Y + connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4227$636_Y + connect \main_uart_tx_fifo_do_read $and$ls180.v:4228$637_Y connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read - connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4363$737_Y - connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4364$738_Y + connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4232$638_Y + connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4233$639_Y connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable @@ -304279,16 +301148,16 @@ module \ls180 connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready - connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4377$741_Y - connect \main_uart_rx_fifo_level1 $add$ls180.v:4378$742_Y + connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4246$642_Y + connect \main_uart_rx_fifo_level1 $add$ls180.v:4247$643_Y connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din - connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4388$746_Y - connect \main_uart_rx_fifo_do_read $and$ls180.v:4389$747_Y + connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4257$647_Y + connect \main_uart_rx_fifo_do_read $and$ls180.v:4258$648_Y connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read - connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4393$748_Y - connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4394$749_Y + connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4262$649_Y + connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4263$650_Y connect \main_gpiotristateasic0_pads_i \gpio_i connect \main_gpiotristateasic0_pads_oe \main_gpiotristateasic0_oe_storage connect \main_gpiotristateasic0_pads_o \main_gpiotristateasic0_out_storage @@ -304302,8 +301171,8 @@ module \ls180 connect \main_spimaster18_status \main_spimaster5_miso connect \main_spimaster6_cs \main_spimaster21_storage connect \main_spimaster7_loopback \main_spimaster23_storage - connect \main_spimaster31_clk_rise $eq$ls180.v:4418$753_Y - connect \main_spimaster32_clk_fall $eq$ls180.v:4419$755_Y + connect \main_spimaster31_clk_rise $eq$ls180.v:4287$654_Y + connect \main_spimaster32_clk_fall $eq$ls180.v:4288$656_Y connect \main_spisdcard_start0 \main_spisdcard_start1 connect \main_spisdcard_length0 \main_spisdcard_length1 connect \main_spisdcard_mosi \main_spisdcard_mosi_storage @@ -304311,19 +301180,19 @@ module \ls180 connect \main_spisdcard_miso_status \main_spisdcard_miso connect \main_spisdcard_cs \main_spisdcard_cs_storage connect \main_spisdcard_loopback \main_spisdcard_loopback_storage - connect \main_spisdcard_clk_rise $eq$ls180.v:4476$761_Y - connect \main_spisdcard_clk_fall $eq$ls180.v:4477$763_Y + connect \main_spisdcard_clk_rise $eq$ls180.v:4345$662_Y + connect \main_spisdcard_clk_fall $eq$ls180.v:4346$664_Y connect \main_spisdcard_clk_divider0 \main_spimaster1_storage connect \i2c_scl \main_i2c_scl connect \i2c_sda_oe \main_i2c_oe connect \i2c_sda_o \main_i2c_sda0 connect \main_i2c_sda1 \i2c_sda_i connect \main_sdphy_status 1'0 - connect \main_sdphy_sdpads_clk $or$ls180.v:4533$771_Y - connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4534$775_Y - connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4535$779_Y - connect \main_sdphy_sdpads_data_oe $or$ls180.v:4536$783_Y - connect \main_sdphy_sdpads_data_o $or$ls180.v:4537$787_Y + connect \main_sdphy_sdpads_clk $or$ls180.v:4402$672_Y + connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4403$676_Y + connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4404$680_Y + connect \main_sdphy_sdpads_data_oe $or$ls180.v:4405$684_Y + connect \main_sdphy_sdpads_data_o $or$ls180.v:4406$688_Y connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce @@ -304344,8 +301213,8 @@ module \ls180 connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_clocker_stop $or$ls180.v:4558$788_Y - connect \main_sdphy_clocker_ce $and$ls180.v:4588$791_Y + connect \main_sdphy_clocker_stop $or$ls180.v:4427$689_Y + connect \main_sdphy_clocker_ce $and$ls180.v:4457$692_Y connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first @@ -304357,8 +301226,8 @@ module \ls180 connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4711$801_Y - connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4712$803_Y + connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4580$702_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4581$704_Y connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready @@ -304375,10 +301244,10 @@ module \ls180 connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data - connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4729$805_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4598$706_Y connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4731$806_Y - connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4732$808_Y + connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4600$707_Y + connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4601$709_Y connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first @@ -304390,8 +301259,8 @@ module \ls180 connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4838$823_Y - connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4839$824_Y + connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4707$724_Y + connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4708$725_Y connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready @@ -304408,10 +301277,10 @@ module \ls180 connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data - connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4856$826_Y + connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4725$727_Y connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all - connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4858$827_Y - connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4859$829_Y + connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4727$728_Y + connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4728$730_Y connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first @@ -304423,8 +301292,8 @@ module \ls180 connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe - connect \main_sdphy_datar_datar_start $eq$ls180.v:4972$838_Y - connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4973$839_Y + connect \main_sdphy_datar_datar_start $eq$ls180.v:4841$739_Y + connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4842$740_Y connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready @@ -304441,10 +301310,10 @@ module \ls180 connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data - connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4990$841_Y + connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4859$742_Y connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all - connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4992$842_Y - connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4993$844_Y + connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4861$743_Y + connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4862$745_Y connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first @@ -304458,88 +301327,88 @@ module \ls180 connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } - connect \main_sdcore_data_event_status { $not$ls180.v:5109$859_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } + connect \main_sdcore_data_event_status { $not$ls180.v:4978$760_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } connect \main_sdcore_crc7_inserter_clr 1'1 connect \main_sdcore_crc7_inserter_enable 1'1 - connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:5113$862_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:5113$860_Y } - connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:5114$865_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:5114$863_Y } - connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:5115$868_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:5115$866_Y } - connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:5116$871_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:5116$869_Y } - connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:5117$874_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:5117$872_Y } - connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:5118$877_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:5118$875_Y } - connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:5119$880_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:5119$878_Y } - connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:5120$883_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:5120$881_Y } - connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:5121$886_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:5121$884_Y } - connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:5122$889_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:5122$887_Y } - connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:5123$892_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:5123$890_Y } - connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:5124$895_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:5124$893_Y } - connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:5125$898_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:5125$896_Y } - connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:5126$901_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:5126$899_Y } - connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:5127$904_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:5127$902_Y } - connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:5128$907_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:5128$905_Y } - connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:5129$910_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:5129$908_Y } - connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:5130$913_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:5130$911_Y } - connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:5131$916_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:5131$914_Y } - connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:5132$919_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:5132$917_Y } - connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:5133$922_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:5133$920_Y } - connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:5134$925_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:5134$923_Y } - connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:5135$928_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:5135$926_Y } - connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:5136$931_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:5136$929_Y } - connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:5137$934_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:5137$932_Y } - connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:5138$937_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:5138$935_Y } - connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:5139$940_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:5139$938_Y } - connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:5140$943_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:5140$941_Y } - connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:5141$946_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:5141$944_Y } - connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:5142$949_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:5142$947_Y } - connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:5143$952_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:5143$950_Y } - connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:5144$955_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:5144$953_Y } - connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:5145$958_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:5145$956_Y } - connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:5146$961_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:5146$959_Y } - connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:5147$964_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:5147$962_Y } - connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:5148$967_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:5148$965_Y } - connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:5149$970_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:5149$968_Y } - connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:5150$973_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:5150$971_Y } - connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:5151$976_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:5151$974_Y } - connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:5152$979_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:5152$977_Y } + connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4982$763_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4982$761_Y } + connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4983$766_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4983$764_Y } + connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4984$769_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4984$767_Y } + connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4985$772_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4985$770_Y } + connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4986$775_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4986$773_Y } + connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4987$778_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4987$776_Y } + connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4988$781_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4988$779_Y } + connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4989$784_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4989$782_Y } + connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4990$787_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4990$785_Y } + connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4991$790_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4991$788_Y } + connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4992$793_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4992$791_Y } + connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4993$796_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4993$794_Y } + connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4994$799_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4994$797_Y } + connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4995$802_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4995$800_Y } + connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4996$805_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4996$803_Y } + connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4997$808_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4997$806_Y } + connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4998$811_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4998$809_Y } + connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4999$814_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4999$812_Y } + connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:5000$817_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:5000$815_Y } + connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:5001$820_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:5001$818_Y } + connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:5002$823_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:5002$821_Y } + connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:5003$826_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:5003$824_Y } + connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:5004$829_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:5004$827_Y } + connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:5005$832_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:5005$830_Y } + connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:5006$835_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:5006$833_Y } + connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:5007$838_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:5007$836_Y } + connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:5008$841_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:5008$839_Y } + connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:5009$844_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:5009$842_Y } + connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:5010$847_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:5010$845_Y } + connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:5011$850_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:5011$848_Y } + connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:5012$853_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:5012$851_Y } + connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:5013$856_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:5013$854_Y } + connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:5014$859_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:5014$857_Y } + connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:5015$862_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:5015$860_Y } + connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:5016$865_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:5016$863_Y } + connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:5017$868_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:5017$866_Y } + connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:5018$871_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:5018$869_Y } + connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:5019$874_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:5019$872_Y } + connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:5020$877_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:5020$875_Y } + connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:5021$880_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:5021$878_Y } connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } - connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:5162$982_Y - connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:5163$983_Y + connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:5031$883_Y + connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:5032$884_Y connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } - connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:5165$985_Y - connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:5166$986_Y + connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:5034$886_Y + connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:5035$887_Y connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } - connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:5168$988_Y - connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:5169$989_Y + connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:5037$889_Y + connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:5038$890_Y connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } - connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:5171$991_Y - connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:5172$992_Y - connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:5173$997_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:5173$995_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:5173$993_Y } - connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:5174$1002_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:5174$1000_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:5174$998_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:5183$1008_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:5183$1006_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:5183$1004_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:5184$1013_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:5184$1011_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:5184$1009_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5193$1019_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5193$1017_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5193$1015_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5194$1024_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5194$1022_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5194$1020_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5203$1030_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5203$1028_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5203$1026_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5204$1035_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5204$1033_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5204$1031_Y } + connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:5040$892_Y + connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:5041$893_Y + connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:5042$898_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:5042$896_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:5042$894_Y } + connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:5043$903_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:5043$901_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:5043$899_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:5052$909_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:5052$907_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:5052$905_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:5053$914_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:5053$912_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:5053$910_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5062$920_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5062$918_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5062$916_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5063$925_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5063$923_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5063$921_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5072$931_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5072$929_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5072$927_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5073$936_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5073$934_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5073$932_Y } connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } - connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5300$1051_Y + connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5169$952_Y connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } - connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5310$1054_Y + connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5179$955_Y connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } - connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5320$1057_Y + connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5189$958_Y connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } - connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5330$1060_Y + connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5199$961_Y connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last - connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5355$1072_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5355$1070_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5355$1068_Y } - connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5356$1077_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5356$1075_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5356$1073_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5365$1083_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5365$1081_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5365$1079_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5366$1088_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5366$1086_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5366$1084_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5375$1094_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5375$1092_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5375$1090_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5376$1099_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5376$1097_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5376$1095_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5385$1105_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5385$1103_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5385$1101_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5386$1110_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5386$1108_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5386$1106_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5224$973_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5224$971_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5224$969_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5225$978_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5225$976_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5225$974_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5234$984_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5234$982_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5234$980_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5235$989_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5235$987_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5235$985_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5244$995_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5244$993_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5244$991_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5245$1000_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5245$998_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5245$996_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5254$1006_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5254$1004_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5254$1002_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5255$1011_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5255$1009_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5255$1007_Y } connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first @@ -304568,20 +301437,20 @@ module \ls180 connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din - connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5622$1140_Y - connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5623$1141_Y + connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5491$1041_Y + connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5492$1042_Y connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r - connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5626$1142_Y - connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5627$1143_Y + connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5495$1043_Y + connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5496$1044_Y connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data - connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5633$1145_Y + connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5502$1046_Y connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all - connect \main_sdblock2mem_converter_load_part $and$ls180.v:5635$1146_Y + connect \main_sdblock2mem_converter_load_part $and$ls180.v:5504$1047_Y connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 connect \main_interface0_bus_we 1'1 @@ -304591,7 +301460,7 @@ module \ls180 connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [34:3] connect \main_sdblock2mem_wishbonedmawriter_length { 3'000 \main_sdblock2mem_wishbonedmawriter_length_storage [31:3] } - connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5645$1147_Y + connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5514$1048_Y connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first @@ -304610,18 +301479,18 @@ module \ls180 connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [34:3] connect \main_sdmem2block_dma_length { 3'000 \main_sdmem2block_dma_length_storage [31:3] } connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset - connect \main_sdmem2block_dma_reset $not$ls180.v:5704$1154_Y + connect \main_sdmem2block_dma_reset $not$ls180.v:5573$1055_Y connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data - connect \main_sdmem2block_converter_first $eq$ls180.v:5785$1162_Y - connect \main_sdmem2block_converter_last $eq$ls180.v:5786$1163_Y + connect \main_sdmem2block_converter_first $eq$ls180.v:5654$1063_Y + connect \main_sdmem2block_converter_last $eq$ls180.v:5655$1064_Y connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid - connect \main_sdmem2block_converter_source_first $and$ls180.v:5788$1164_Y - connect \main_sdmem2block_converter_source_last $and$ls180.v:5789$1165_Y - connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5790$1166_Y + connect \main_sdmem2block_converter_source_first $and$ls180.v:5657$1065_Y + connect \main_sdmem2block_converter_source_last $and$ls180.v:5658$1066_Y + connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5659$1067_Y connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout @@ -304636,12 +301505,12 @@ module \ls180 connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din - connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5842$1171_Y - connect \main_sdmem2block_fifo_do_read $and$ls180.v:5843$1172_Y + connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5711$1072_Y + connect \main_sdmem2block_fifo_do_read $and$ls180.v:5712$1073_Y connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r - connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5846$1173_Y - connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5847$1174_Y + connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5715$1074_Y + connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5716$1075_Y connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 [31:0] connect \builder_shared_sel \builder_comb_rhs_array_muxed26 [3:0] @@ -304655,16 +301524,16 @@ module \ls180 connect \main_libresocsim_libresoc_jtag_wb_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } connect \main_interface0_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } connect \main_interface1_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } - connect \main_libresocsim_libresoc_ibus_ack $and$ls180.v:5898$1180_Y - connect \main_libresocsim_libresoc_dbus_ack $and$ls180.v:5899$1182_Y - connect \main_libresocsim_libresoc_jtag_wb_ack $and$ls180.v:5900$1184_Y - connect \main_interface0_bus_ack $and$ls180.v:5901$1186_Y - connect \main_interface1_bus_ack $and$ls180.v:5902$1188_Y - connect \main_libresocsim_libresoc_ibus_err $and$ls180.v:5903$1190_Y - connect \main_libresocsim_libresoc_dbus_err $and$ls180.v:5904$1192_Y - connect \main_libresocsim_libresoc_jtag_wb_err $and$ls180.v:5905$1194_Y - connect \main_interface0_bus_err $and$ls180.v:5906$1196_Y - connect \main_interface1_bus_err $and$ls180.v:5907$1198_Y + connect \main_libresocsim_libresoc_ibus_ack $and$ls180.v:5767$1081_Y + connect \main_libresocsim_libresoc_dbus_ack $and$ls180.v:5768$1083_Y + connect \main_libresocsim_libresoc_jtag_wb_ack $and$ls180.v:5769$1085_Y + connect \main_interface0_bus_ack $and$ls180.v:5770$1087_Y + connect \main_interface1_bus_ack $and$ls180.v:5771$1089_Y + connect \main_libresocsim_libresoc_ibus_err $and$ls180.v:5772$1091_Y + connect \main_libresocsim_libresoc_dbus_err $and$ls180.v:5773$1093_Y + connect \main_libresocsim_libresoc_jtag_wb_err $and$ls180.v:5774$1095_Y + connect \main_interface0_bus_err $and$ls180.v:5775$1097_Y + connect \main_interface1_bus_err $and$ls180.v:5776$1099_Y connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_libresoc_jtag_wb_cyc \main_libresocsim_libresoc_dbus_cyc \main_libresocsim_libresoc_ibus_cyc } connect \main_libresocsim_ram_bus_adr \builder_shared_adr connect \main_libresocsim_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } @@ -304673,34 +301542,13 @@ module \ls180 connect \main_libresocsim_ram_bus_we \builder_shared_we connect \main_libresocsim_ram_bus_cti \builder_shared_cti connect \main_libresocsim_ram_bus_bte \builder_shared_bte - connect \main_interface0_ram_bus_adr \builder_shared_adr - connect \main_interface0_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface0_ram_bus_sel { 4'0000 \builder_shared_sel } - connect \main_interface0_ram_bus_stb \builder_shared_stb - connect \main_interface0_ram_bus_we \builder_shared_we - connect \main_interface0_ram_bus_cti \builder_shared_cti - connect \main_interface0_ram_bus_bte \builder_shared_bte - connect \main_interface1_ram_bus_adr \builder_shared_adr - connect \main_interface1_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface1_ram_bus_sel { 4'0000 \builder_shared_sel } - connect \main_interface1_ram_bus_stb \builder_shared_stb - connect \main_interface1_ram_bus_we \builder_shared_we - connect \main_interface1_ram_bus_cti \builder_shared_cti - connect \main_interface1_ram_bus_bte \builder_shared_bte - connect \main_interface2_ram_bus_adr \builder_shared_adr - connect \main_interface2_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface2_ram_bus_sel { 4'0000 \builder_shared_sel } - connect \main_interface2_ram_bus_stb \builder_shared_stb - connect \main_interface2_ram_bus_we \builder_shared_we - connect \main_interface2_ram_bus_cti \builder_shared_cti - connect \main_interface2_ram_bus_bte \builder_shared_bte - connect \main_interface3_ram_bus_adr \builder_shared_adr - connect \main_interface3_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface3_ram_bus_sel { 4'0000 \builder_shared_sel } - connect \main_interface3_ram_bus_stb \builder_shared_stb - connect \main_interface3_ram_bus_we \builder_shared_we - connect \main_interface3_ram_bus_cti \builder_shared_cti - connect \main_interface3_ram_bus_bte \builder_shared_bte + connect \main_ram_bus_ram_bus_adr \builder_shared_adr + connect \main_ram_bus_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_ram_bus_ram_bus_sel { 4'0000 \builder_shared_sel } + connect \main_ram_bus_ram_bus_stb \builder_shared_stb + connect \main_ram_bus_ram_bus_we \builder_shared_we + connect \main_ram_bus_ram_bus_cti \builder_shared_cti + connect \main_ram_bus_ram_bus_bte \builder_shared_bte connect \main_interface0_converted_interface_adr \builder_shared_adr connect \main_interface0_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } connect \main_interface0_converted_interface_sel { 4'0000 \builder_shared_sel } @@ -304715,34 +301563,6 @@ module \ls180 connect \main_interface1_converted_interface_we \builder_shared_we connect \main_interface1_converted_interface_cti \builder_shared_cti connect \main_interface1_converted_interface_bte \builder_shared_bte - connect \main_libresocsim_libresoc_interface0_adr \builder_shared_adr [28:0] - connect \main_libresocsim_libresoc_interface0_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_libresocsim_libresoc_interface0_sel { 4'0000 \builder_shared_sel } - connect \main_libresocsim_libresoc_interface0_stb \builder_shared_stb - connect \main_libresocsim_libresoc_interface0_we \builder_shared_we - connect \main_libresocsim_libresoc_interface0_cti \builder_shared_cti - connect \main_libresocsim_libresoc_interface0_bte \builder_shared_bte - connect \main_libresocsim_libresoc_interface1_adr \builder_shared_adr [28:0] - connect \main_libresocsim_libresoc_interface1_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_libresocsim_libresoc_interface1_sel { 4'0000 \builder_shared_sel } - connect \main_libresocsim_libresoc_interface1_stb \builder_shared_stb - connect \main_libresocsim_libresoc_interface1_we \builder_shared_we - connect \main_libresocsim_libresoc_interface1_cti \builder_shared_cti - connect \main_libresocsim_libresoc_interface1_bte \builder_shared_bte - connect \main_libresocsim_libresoc_interface2_adr \builder_shared_adr [28:0] - connect \main_libresocsim_libresoc_interface2_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_libresocsim_libresoc_interface2_sel { 4'0000 \builder_shared_sel } - connect \main_libresocsim_libresoc_interface2_stb \builder_shared_stb - connect \main_libresocsim_libresoc_interface2_we \builder_shared_we - connect \main_libresocsim_libresoc_interface2_cti \builder_shared_cti - connect \main_libresocsim_libresoc_interface2_bte \builder_shared_bte - connect \main_libresocsim_libresoc_interface3_adr \builder_shared_adr [28:0] - connect \main_libresocsim_libresoc_interface3_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_libresocsim_libresoc_interface3_sel { 4'0000 \builder_shared_sel } - connect \main_libresocsim_libresoc_interface3_stb \builder_shared_stb - connect \main_libresocsim_libresoc_interface3_we \builder_shared_we - connect \main_libresocsim_libresoc_interface3_cti \builder_shared_cti - connect \main_libresocsim_libresoc_interface3_bte \builder_shared_bte connect \main_socbushandler_converted_interface_adr \builder_shared_adr connect \main_socbushandler_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } connect \main_socbushandler_converted_interface_sel { 4'0000 \builder_shared_sel } @@ -304757,50 +301577,43 @@ module \ls180 connect \builder_libresocsim_converted_interface_we \builder_shared_we connect \builder_libresocsim_converted_interface_cti \builder_shared_cti connect \builder_libresocsim_converted_interface_bte \builder_shared_bte - connect \main_libresocsim_ram_bus_cyc $and$ls180.v:6016$1213_Y - connect \main_interface0_ram_bus_cyc $and$ls180.v:6017$1214_Y - connect \main_interface1_ram_bus_cyc $and$ls180.v:6018$1215_Y - connect \main_interface2_ram_bus_cyc $and$ls180.v:6019$1216_Y - connect \main_interface3_ram_bus_cyc $and$ls180.v:6020$1217_Y - connect \main_interface0_converted_interface_cyc $and$ls180.v:6021$1218_Y - connect \main_interface1_converted_interface_cyc $and$ls180.v:6022$1219_Y - connect \main_libresocsim_libresoc_interface0_cyc $and$ls180.v:6023$1220_Y - connect \main_libresocsim_libresoc_interface1_cyc $and$ls180.v:6024$1221_Y - connect \main_libresocsim_libresoc_interface2_cyc $and$ls180.v:6025$1222_Y - connect \main_libresocsim_libresoc_interface3_cyc $and$ls180.v:6026$1223_Y - connect \main_socbushandler_converted_interface_cyc $and$ls180.v:6027$1224_Y - connect \builder_libresocsim_converted_interface_cyc $and$ls180.v:6028$1225_Y - connect \builder_shared_err $or$ls180.v:6029$1237_Y - connect \builder_wait $and$ls180.v:6030$1240_Y - connect \builder_done $eq$ls180.v:6043$1279_Y - connect \builder_csrbank0_sel $eq$ls180.v:6044$1280_Y + connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5829$1107_Y + connect \main_ram_bus_ram_bus_cyc $and$ls180.v:5830$1108_Y + connect \main_interface0_converted_interface_cyc $and$ls180.v:5831$1109_Y + connect \main_interface1_converted_interface_cyc $and$ls180.v:5832$1110_Y + connect \main_socbushandler_converted_interface_cyc $and$ls180.v:5833$1111_Y + connect \builder_libresocsim_converted_interface_cyc $and$ls180.v:5834$1112_Y + connect \builder_shared_err $or$ls180.v:5835$1117_Y + connect \builder_wait $and$ls180.v:5836$1120_Y + connect \builder_done $eq$ls180.v:5849$1138_Y + connect \builder_csrbank0_sel $eq$ls180.v:5850$1139_Y connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] - connect \builder_csrbank0_reset0_re $and$ls180.v:6046$1283_Y - connect \builder_csrbank0_reset0_we $and$ls180.v:6047$1287_Y + connect \builder_csrbank0_reset0_re $and$ls180.v:5852$1142_Y + connect \builder_csrbank0_reset0_we $and$ls180.v:5853$1146_Y connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch3_re $and$ls180.v:6049$1290_Y - connect \builder_csrbank0_scratch3_we $and$ls180.v:6050$1294_Y + connect \builder_csrbank0_scratch3_re $and$ls180.v:5855$1149_Y + connect \builder_csrbank0_scratch3_we $and$ls180.v:5856$1153_Y connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch2_re $and$ls180.v:6052$1297_Y - connect \builder_csrbank0_scratch2_we $and$ls180.v:6053$1301_Y + connect \builder_csrbank0_scratch2_re $and$ls180.v:5858$1156_Y + connect \builder_csrbank0_scratch2_we $and$ls180.v:5859$1160_Y connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch1_re $and$ls180.v:6055$1304_Y - connect \builder_csrbank0_scratch1_we $and$ls180.v:6056$1308_Y + connect \builder_csrbank0_scratch1_re $and$ls180.v:5861$1163_Y + connect \builder_csrbank0_scratch1_we $and$ls180.v:5862$1167_Y connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch0_re $and$ls180.v:6058$1311_Y - connect \builder_csrbank0_scratch0_we $and$ls180.v:6059$1315_Y + connect \builder_csrbank0_scratch0_re $and$ls180.v:5864$1170_Y + connect \builder_csrbank0_scratch0_we $and$ls180.v:5865$1174_Y connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors3_re $and$ls180.v:6061$1318_Y - connect \builder_csrbank0_bus_errors3_we $and$ls180.v:6062$1322_Y + connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5867$1177_Y + connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5868$1181_Y connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors2_re $and$ls180.v:6064$1325_Y - connect \builder_csrbank0_bus_errors2_we $and$ls180.v:6065$1329_Y + connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5870$1184_Y + connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5871$1188_Y connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors1_re $and$ls180.v:6067$1332_Y - connect \builder_csrbank0_bus_errors1_we $and$ls180.v:6068$1336_Y + connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5873$1191_Y + connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5874$1195_Y connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors0_re $and$ls180.v:6070$1339_Y - connect \builder_csrbank0_bus_errors0_we $and$ls180.v:6071$1343_Y + connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5876$1198_Y + connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5877$1202_Y connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] @@ -304811,25 +301624,25 @@ module \ls180 connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we - connect \builder_csrbank1_sel $eq$ls180.v:6082$1344_Y + connect \builder_csrbank1_sel $eq$ls180.v:5888$1203_Y connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe1_re $and$ls180.v:6084$1347_Y - connect \builder_csrbank1_oe1_we $and$ls180.v:6085$1351_Y + connect \builder_csrbank1_oe1_re $and$ls180.v:5890$1206_Y + connect \builder_csrbank1_oe1_we $and$ls180.v:5891$1210_Y connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe0_re $and$ls180.v:6087$1354_Y - connect \builder_csrbank1_oe0_we $and$ls180.v:6088$1358_Y + connect \builder_csrbank1_oe0_re $and$ls180.v:5893$1213_Y + connect \builder_csrbank1_oe0_we $and$ls180.v:5894$1217_Y connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in1_re $and$ls180.v:6090$1361_Y - connect \builder_csrbank1_in1_we $and$ls180.v:6091$1365_Y + connect \builder_csrbank1_in1_re $and$ls180.v:5896$1220_Y + connect \builder_csrbank1_in1_we $and$ls180.v:5897$1224_Y connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in0_re $and$ls180.v:6093$1368_Y - connect \builder_csrbank1_in0_we $and$ls180.v:6094$1372_Y + connect \builder_csrbank1_in0_re $and$ls180.v:5899$1227_Y + connect \builder_csrbank1_in0_we $and$ls180.v:5900$1231_Y connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out1_re $and$ls180.v:6096$1375_Y - connect \builder_csrbank1_out1_we $and$ls180.v:6097$1379_Y + connect \builder_csrbank1_out1_re $and$ls180.v:5902$1234_Y + connect \builder_csrbank1_out1_we $and$ls180.v:5903$1238_Y connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out0_re $and$ls180.v:6099$1382_Y - connect \builder_csrbank1_out0_we $and$ls180.v:6100$1386_Y + connect \builder_csrbank1_out0_re $and$ls180.v:5905$1241_Y + connect \builder_csrbank1_out0_we $and$ls180.v:5906$1245_Y connect \builder_csrbank1_oe1_w \main_gpiotristateasic1_oe_storage [15:8] connect \builder_csrbank1_oe0_w \main_gpiotristateasic1_oe_storage [7:0] connect \builder_csrbank1_in1_w \main_gpiotristateasic1_status [15:8] @@ -304837,13 +301650,13 @@ module \ls180 connect \main_gpiotristateasic1_we \builder_csrbank1_in0_we connect \builder_csrbank1_out1_w \main_gpiotristateasic1_out_storage [15:8] connect \builder_csrbank1_out0_w \main_gpiotristateasic1_out_storage [7:0] - connect \builder_csrbank2_sel $eq$ls180.v:6108$1387_Y + connect \builder_csrbank2_sel $eq$ls180.v:5914$1246_Y connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0] - connect \builder_csrbank2_w0_re $and$ls180.v:6110$1390_Y - connect \builder_csrbank2_w0_we $and$ls180.v:6111$1394_Y + connect \builder_csrbank2_w0_re $and$ls180.v:5916$1249_Y + connect \builder_csrbank2_w0_we $and$ls180.v:5917$1253_Y connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0] - connect \builder_csrbank2_r_re $and$ls180.v:6113$1397_Y - connect \builder_csrbank2_r_we $and$ls180.v:6114$1401_Y + connect \builder_csrbank2_r_re $and$ls180.v:5919$1256_Y + connect \builder_csrbank2_r_we $and$ls180.v:5920$1260_Y connect \main_i2c_scl \main_i2c_storage [0] connect \main_i2c_oe \main_i2c_storage [1] connect \main_i2c_sda0 \main_i2c_storage [2] @@ -304851,34 +301664,34 @@ module \ls180 connect \main_i2c_status \main_i2c_sda1 connect \builder_csrbank2_r_w \main_i2c_status connect \main_i2c_we \builder_csrbank2_r_we - connect \builder_csrbank3_sel $eq$ls180.v:6122$1402_Y + connect \builder_csrbank3_sel $eq$ls180.v:5928$1261_Y connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] - connect \builder_csrbank3_enable0_re $and$ls180.v:6124$1405_Y - connect \builder_csrbank3_enable0_we $and$ls180.v:6125$1409_Y + connect \builder_csrbank3_enable0_re $and$ls180.v:5930$1264_Y + connect \builder_csrbank3_enable0_we $and$ls180.v:5931$1268_Y connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width3_re $and$ls180.v:6127$1412_Y - connect \builder_csrbank3_width3_we $and$ls180.v:6128$1416_Y + connect \builder_csrbank3_width3_re $and$ls180.v:5933$1271_Y + connect \builder_csrbank3_width3_we $and$ls180.v:5934$1275_Y connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width2_re $and$ls180.v:6130$1419_Y - connect \builder_csrbank3_width2_we $and$ls180.v:6131$1423_Y + connect \builder_csrbank3_width2_re $and$ls180.v:5936$1278_Y + connect \builder_csrbank3_width2_we $and$ls180.v:5937$1282_Y connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width1_re $and$ls180.v:6133$1426_Y - connect \builder_csrbank3_width1_we $and$ls180.v:6134$1430_Y + connect \builder_csrbank3_width1_re $and$ls180.v:5939$1285_Y + connect \builder_csrbank3_width1_we $and$ls180.v:5940$1289_Y connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width0_re $and$ls180.v:6136$1433_Y - connect \builder_csrbank3_width0_we $and$ls180.v:6137$1437_Y + connect \builder_csrbank3_width0_re $and$ls180.v:5942$1292_Y + connect \builder_csrbank3_width0_we $and$ls180.v:5943$1296_Y connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period3_re $and$ls180.v:6139$1440_Y - connect \builder_csrbank3_period3_we $and$ls180.v:6140$1444_Y + connect \builder_csrbank3_period3_re $and$ls180.v:5945$1299_Y + connect \builder_csrbank3_period3_we $and$ls180.v:5946$1303_Y connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period2_re $and$ls180.v:6142$1447_Y - connect \builder_csrbank3_period2_we $and$ls180.v:6143$1451_Y + connect \builder_csrbank3_period2_re $and$ls180.v:5948$1306_Y + connect \builder_csrbank3_period2_we $and$ls180.v:5949$1310_Y connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period1_re $and$ls180.v:6145$1454_Y - connect \builder_csrbank3_period1_we $and$ls180.v:6146$1458_Y + connect \builder_csrbank3_period1_re $and$ls180.v:5951$1313_Y + connect \builder_csrbank3_period1_we $and$ls180.v:5952$1317_Y connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period0_re $and$ls180.v:6148$1461_Y - connect \builder_csrbank3_period0_we $and$ls180.v:6149$1465_Y + connect \builder_csrbank3_period0_re $and$ls180.v:5954$1320_Y + connect \builder_csrbank3_period0_we $and$ls180.v:5955$1324_Y connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24] connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16] @@ -304888,34 +301701,34 @@ module \ls180 connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16] connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8] connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0] - connect \builder_csrbank4_sel $eq$ls180.v:6159$1466_Y + connect \builder_csrbank4_sel $eq$ls180.v:5965$1325_Y connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0] - connect \builder_csrbank4_enable0_re $and$ls180.v:6161$1469_Y - connect \builder_csrbank4_enable0_we $and$ls180.v:6162$1473_Y + connect \builder_csrbank4_enable0_re $and$ls180.v:5967$1328_Y + connect \builder_csrbank4_enable0_we $and$ls180.v:5968$1332_Y connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width3_re $and$ls180.v:6164$1476_Y - connect \builder_csrbank4_width3_we $and$ls180.v:6165$1480_Y + connect \builder_csrbank4_width3_re $and$ls180.v:5970$1335_Y + connect \builder_csrbank4_width3_we $and$ls180.v:5971$1339_Y connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width2_re $and$ls180.v:6167$1483_Y - connect \builder_csrbank4_width2_we $and$ls180.v:6168$1487_Y + connect \builder_csrbank4_width2_re $and$ls180.v:5973$1342_Y + connect \builder_csrbank4_width2_we $and$ls180.v:5974$1346_Y connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width1_re $and$ls180.v:6170$1490_Y - connect \builder_csrbank4_width1_we $and$ls180.v:6171$1494_Y + connect \builder_csrbank4_width1_re $and$ls180.v:5976$1349_Y + connect \builder_csrbank4_width1_we $and$ls180.v:5977$1353_Y connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width0_re $and$ls180.v:6173$1497_Y - connect \builder_csrbank4_width0_we $and$ls180.v:6174$1501_Y + connect \builder_csrbank4_width0_re $and$ls180.v:5979$1356_Y + connect \builder_csrbank4_width0_we $and$ls180.v:5980$1360_Y connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period3_re $and$ls180.v:6176$1504_Y - connect \builder_csrbank4_period3_we $and$ls180.v:6177$1508_Y + connect \builder_csrbank4_period3_re $and$ls180.v:5982$1363_Y + connect \builder_csrbank4_period3_we $and$ls180.v:5983$1367_Y connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period2_re $and$ls180.v:6179$1511_Y - connect \builder_csrbank4_period2_we $and$ls180.v:6180$1515_Y + connect \builder_csrbank4_period2_re $and$ls180.v:5985$1370_Y + connect \builder_csrbank4_period2_we $and$ls180.v:5986$1374_Y connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period1_re $and$ls180.v:6182$1518_Y - connect \builder_csrbank4_period1_we $and$ls180.v:6183$1522_Y + connect \builder_csrbank4_period1_re $and$ls180.v:5988$1377_Y + connect \builder_csrbank4_period1_we $and$ls180.v:5989$1381_Y connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period0_re $and$ls180.v:6185$1525_Y - connect \builder_csrbank4_period0_we $and$ls180.v:6186$1529_Y + connect \builder_csrbank4_period0_re $and$ls180.v:5991$1384_Y + connect \builder_csrbank4_period0_we $and$ls180.v:5992$1388_Y connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24] connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16] @@ -304925,52 +301738,52 @@ module \ls180 connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16] connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8] connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0] - connect \builder_csrbank5_sel $eq$ls180.v:6196$1530_Y + connect \builder_csrbank5_sel $eq$ls180.v:6002$1389_Y connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base7_re $and$ls180.v:6198$1533_Y - connect \builder_csrbank5_dma_base7_we $and$ls180.v:6199$1537_Y + connect \builder_csrbank5_dma_base7_re $and$ls180.v:6004$1392_Y + connect \builder_csrbank5_dma_base7_we $and$ls180.v:6005$1396_Y connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base6_re $and$ls180.v:6201$1540_Y - connect \builder_csrbank5_dma_base6_we $and$ls180.v:6202$1544_Y + connect \builder_csrbank5_dma_base6_re $and$ls180.v:6007$1399_Y + connect \builder_csrbank5_dma_base6_we $and$ls180.v:6008$1403_Y connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base5_re $and$ls180.v:6204$1547_Y - connect \builder_csrbank5_dma_base5_we $and$ls180.v:6205$1551_Y + connect \builder_csrbank5_dma_base5_re $and$ls180.v:6010$1406_Y + connect \builder_csrbank5_dma_base5_we $and$ls180.v:6011$1410_Y connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base4_re $and$ls180.v:6207$1554_Y - connect \builder_csrbank5_dma_base4_we $and$ls180.v:6208$1558_Y + connect \builder_csrbank5_dma_base4_re $and$ls180.v:6013$1413_Y + connect \builder_csrbank5_dma_base4_we $and$ls180.v:6014$1417_Y connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base3_re $and$ls180.v:6210$1561_Y - connect \builder_csrbank5_dma_base3_we $and$ls180.v:6211$1565_Y + connect \builder_csrbank5_dma_base3_re $and$ls180.v:6016$1420_Y + connect \builder_csrbank5_dma_base3_we $and$ls180.v:6017$1424_Y connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base2_re $and$ls180.v:6213$1568_Y - connect \builder_csrbank5_dma_base2_we $and$ls180.v:6214$1572_Y + connect \builder_csrbank5_dma_base2_re $and$ls180.v:6019$1427_Y + connect \builder_csrbank5_dma_base2_we $and$ls180.v:6020$1431_Y connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base1_re $and$ls180.v:6216$1575_Y - connect \builder_csrbank5_dma_base1_we $and$ls180.v:6217$1579_Y + connect \builder_csrbank5_dma_base1_re $and$ls180.v:6022$1434_Y + connect \builder_csrbank5_dma_base1_we $and$ls180.v:6023$1438_Y connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base0_re $and$ls180.v:6219$1582_Y - connect \builder_csrbank5_dma_base0_we $and$ls180.v:6220$1586_Y + connect \builder_csrbank5_dma_base0_re $and$ls180.v:6025$1441_Y + connect \builder_csrbank5_dma_base0_we $and$ls180.v:6026$1445_Y connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length3_re $and$ls180.v:6222$1589_Y - connect \builder_csrbank5_dma_length3_we $and$ls180.v:6223$1593_Y + connect \builder_csrbank5_dma_length3_re $and$ls180.v:6028$1448_Y + connect \builder_csrbank5_dma_length3_we $and$ls180.v:6029$1452_Y connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length2_re $and$ls180.v:6225$1596_Y - connect \builder_csrbank5_dma_length2_we $and$ls180.v:6226$1600_Y + connect \builder_csrbank5_dma_length2_re $and$ls180.v:6031$1455_Y + connect \builder_csrbank5_dma_length2_we $and$ls180.v:6032$1459_Y connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length1_re $and$ls180.v:6228$1603_Y - connect \builder_csrbank5_dma_length1_we $and$ls180.v:6229$1607_Y + connect \builder_csrbank5_dma_length1_re $and$ls180.v:6034$1462_Y + connect \builder_csrbank5_dma_length1_we $and$ls180.v:6035$1466_Y connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length0_re $and$ls180.v:6231$1610_Y - connect \builder_csrbank5_dma_length0_we $and$ls180.v:6232$1614_Y + connect \builder_csrbank5_dma_length0_re $and$ls180.v:6037$1469_Y + connect \builder_csrbank5_dma_length0_we $and$ls180.v:6038$1473_Y connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_enable0_re $and$ls180.v:6234$1617_Y - connect \builder_csrbank5_dma_enable0_we $and$ls180.v:6235$1621_Y + connect \builder_csrbank5_dma_enable0_re $and$ls180.v:6040$1476_Y + connect \builder_csrbank5_dma_enable0_we $and$ls180.v:6041$1480_Y connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_done_re $and$ls180.v:6237$1624_Y - connect \builder_csrbank5_dma_done_we $and$ls180.v:6238$1628_Y + connect \builder_csrbank5_dma_done_re $and$ls180.v:6043$1483_Y + connect \builder_csrbank5_dma_done_we $and$ls180.v:6044$1487_Y connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_loop0_re $and$ls180.v:6240$1631_Y - connect \builder_csrbank5_dma_loop0_we $and$ls180.v:6241$1635_Y + connect \builder_csrbank5_dma_loop0_re $and$ls180.v:6046$1490_Y + connect \builder_csrbank5_dma_loop0_we $and$ls180.v:6047$1494_Y connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] @@ -304987,106 +301800,106 @@ module \ls180 connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage - connect \builder_csrbank6_sel $eq$ls180.v:6258$1636_Y + connect \builder_csrbank6_sel $eq$ls180.v:6064$1495_Y connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:6260$1639_Y - connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:6261$1643_Y + connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:6066$1498_Y + connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:6067$1502_Y connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:6263$1646_Y - connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:6264$1650_Y + connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:6069$1505_Y + connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:6070$1509_Y connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:6266$1653_Y - connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:6267$1657_Y + connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:6072$1512_Y + connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:6073$1516_Y connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:6269$1660_Y - connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:6270$1664_Y + connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:6075$1519_Y + connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:6076$1523_Y connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6272$1667_Y - connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6273$1671_Y + connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6078$1526_Y + connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6079$1530_Y connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6275$1674_Y - connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6276$1678_Y + connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6081$1533_Y + connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6082$1537_Y connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6278$1681_Y - connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6279$1685_Y + connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6084$1540_Y + connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6085$1544_Y connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6281$1688_Y - connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6282$1692_Y + connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6087$1547_Y + connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6088$1551_Y connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0] - connect \main_sdcore_cmd_send_re $and$ls180.v:6284$1695_Y - connect \main_sdcore_cmd_send_we $and$ls180.v:6285$1699_Y + connect \main_sdcore_cmd_send_re $and$ls180.v:6090$1554_Y + connect \main_sdcore_cmd_send_we $and$ls180.v:6091$1558_Y connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6287$1702_Y - connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6288$1706_Y + connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6093$1561_Y + connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6094$1565_Y connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6290$1709_Y - connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6291$1713_Y + connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6096$1568_Y + connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6097$1572_Y connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6293$1716_Y - connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6294$1720_Y + connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6099$1575_Y + connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6100$1579_Y connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6296$1723_Y - connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6297$1727_Y + connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6102$1582_Y + connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6103$1586_Y connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6299$1730_Y - connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6300$1734_Y + connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6105$1589_Y + connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6106$1593_Y connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6302$1737_Y - connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6303$1741_Y + connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6108$1596_Y + connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6109$1600_Y connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6305$1744_Y - connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6306$1748_Y + connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6111$1603_Y + connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6112$1607_Y connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6308$1751_Y - connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6309$1755_Y + connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6114$1610_Y + connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6115$1614_Y connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6311$1758_Y - connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6312$1762_Y + connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6117$1617_Y + connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6118$1621_Y connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6314$1765_Y - connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6315$1769_Y + connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6120$1624_Y + connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6121$1628_Y connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6317$1772_Y - connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6318$1776_Y + connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6123$1631_Y + connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6124$1635_Y connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6320$1779_Y - connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6321$1783_Y + connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6126$1638_Y + connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6127$1642_Y connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6323$1786_Y - connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6324$1790_Y + connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6129$1645_Y + connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6130$1649_Y connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6326$1793_Y - connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6327$1797_Y + connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6132$1652_Y + connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6133$1656_Y connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6329$1800_Y - connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6330$1804_Y + connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6135$1659_Y + connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6136$1663_Y connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6332$1807_Y - connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6333$1811_Y + connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6138$1666_Y + connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6139$1670_Y connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_cmd_event_re $and$ls180.v:6335$1814_Y - connect \builder_csrbank6_cmd_event_we $and$ls180.v:6336$1818_Y + connect \builder_csrbank6_cmd_event_re $and$ls180.v:6141$1673_Y + connect \builder_csrbank6_cmd_event_we $and$ls180.v:6142$1677_Y connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_data_event_re $and$ls180.v:6338$1821_Y - connect \builder_csrbank6_data_event_we $and$ls180.v:6339$1825_Y + connect \builder_csrbank6_data_event_re $and$ls180.v:6144$1680_Y + connect \builder_csrbank6_data_event_we $and$ls180.v:6145$1684_Y connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0] - connect \builder_csrbank6_block_length1_re $and$ls180.v:6341$1828_Y - connect \builder_csrbank6_block_length1_we $and$ls180.v:6342$1832_Y + connect \builder_csrbank6_block_length1_re $and$ls180.v:6147$1687_Y + connect \builder_csrbank6_block_length1_we $and$ls180.v:6148$1691_Y connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_length0_re $and$ls180.v:6344$1835_Y - connect \builder_csrbank6_block_length0_we $and$ls180.v:6345$1839_Y + connect \builder_csrbank6_block_length0_re $and$ls180.v:6150$1694_Y + connect \builder_csrbank6_block_length0_we $and$ls180.v:6151$1698_Y connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count3_re $and$ls180.v:6347$1842_Y - connect \builder_csrbank6_block_count3_we $and$ls180.v:6348$1846_Y + connect \builder_csrbank6_block_count3_re $and$ls180.v:6153$1701_Y + connect \builder_csrbank6_block_count3_we $and$ls180.v:6154$1705_Y connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count2_re $and$ls180.v:6350$1849_Y - connect \builder_csrbank6_block_count2_we $and$ls180.v:6351$1853_Y + connect \builder_csrbank6_block_count2_re $and$ls180.v:6156$1708_Y + connect \builder_csrbank6_block_count2_we $and$ls180.v:6157$1712_Y connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count1_re $and$ls180.v:6353$1856_Y - connect \builder_csrbank6_block_count1_we $and$ls180.v:6354$1860_Y + connect \builder_csrbank6_block_count1_re $and$ls180.v:6159$1715_Y + connect \builder_csrbank6_block_count1_we $and$ls180.v:6160$1719_Y connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count0_re $and$ls180.v:6356$1863_Y - connect \builder_csrbank6_block_count0_we $and$ls180.v:6357$1867_Y + connect \builder_csrbank6_block_count0_re $and$ls180.v:6162$1722_Y + connect \builder_csrbank6_block_count0_we $and$ls180.v:6163$1726_Y connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] @@ -305122,64 +301935,64 @@ module \ls180 connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16] connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8] connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0] - connect \builder_csrbank7_sel $eq$ls180.v:6393$1868_Y + connect \builder_csrbank7_sel $eq$ls180.v:6199$1727_Y connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base7_re $and$ls180.v:6395$1871_Y - connect \builder_csrbank7_dma_base7_we $and$ls180.v:6396$1875_Y + connect \builder_csrbank7_dma_base7_re $and$ls180.v:6201$1730_Y + connect \builder_csrbank7_dma_base7_we $and$ls180.v:6202$1734_Y connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base6_re $and$ls180.v:6398$1878_Y - connect \builder_csrbank7_dma_base6_we $and$ls180.v:6399$1882_Y + connect \builder_csrbank7_dma_base6_re $and$ls180.v:6204$1737_Y + connect \builder_csrbank7_dma_base6_we $and$ls180.v:6205$1741_Y connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base5_re $and$ls180.v:6401$1885_Y - connect \builder_csrbank7_dma_base5_we $and$ls180.v:6402$1889_Y + connect \builder_csrbank7_dma_base5_re $and$ls180.v:6207$1744_Y + connect \builder_csrbank7_dma_base5_we $and$ls180.v:6208$1748_Y connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base4_re $and$ls180.v:6404$1892_Y - connect \builder_csrbank7_dma_base4_we $and$ls180.v:6405$1896_Y + connect \builder_csrbank7_dma_base4_re $and$ls180.v:6210$1751_Y + connect \builder_csrbank7_dma_base4_we $and$ls180.v:6211$1755_Y connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base3_re $and$ls180.v:6407$1899_Y - connect \builder_csrbank7_dma_base3_we $and$ls180.v:6408$1903_Y + connect \builder_csrbank7_dma_base3_re $and$ls180.v:6213$1758_Y + connect \builder_csrbank7_dma_base3_we $and$ls180.v:6214$1762_Y connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base2_re $and$ls180.v:6410$1906_Y - connect \builder_csrbank7_dma_base2_we $and$ls180.v:6411$1910_Y + connect \builder_csrbank7_dma_base2_re $and$ls180.v:6216$1765_Y + connect \builder_csrbank7_dma_base2_we $and$ls180.v:6217$1769_Y connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base1_re $and$ls180.v:6413$1913_Y - connect \builder_csrbank7_dma_base1_we $and$ls180.v:6414$1917_Y + connect \builder_csrbank7_dma_base1_re $and$ls180.v:6219$1772_Y + connect \builder_csrbank7_dma_base1_we $and$ls180.v:6220$1776_Y connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base0_re $and$ls180.v:6416$1920_Y - connect \builder_csrbank7_dma_base0_we $and$ls180.v:6417$1924_Y + connect \builder_csrbank7_dma_base0_re $and$ls180.v:6222$1779_Y + connect \builder_csrbank7_dma_base0_we $and$ls180.v:6223$1783_Y connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length3_re $and$ls180.v:6419$1927_Y - connect \builder_csrbank7_dma_length3_we $and$ls180.v:6420$1931_Y + connect \builder_csrbank7_dma_length3_re $and$ls180.v:6225$1786_Y + connect \builder_csrbank7_dma_length3_we $and$ls180.v:6226$1790_Y connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length2_re $and$ls180.v:6422$1934_Y - connect \builder_csrbank7_dma_length2_we $and$ls180.v:6423$1938_Y + connect \builder_csrbank7_dma_length2_re $and$ls180.v:6228$1793_Y + connect \builder_csrbank7_dma_length2_we $and$ls180.v:6229$1797_Y connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length1_re $and$ls180.v:6425$1941_Y - connect \builder_csrbank7_dma_length1_we $and$ls180.v:6426$1945_Y + connect \builder_csrbank7_dma_length1_re $and$ls180.v:6231$1800_Y + connect \builder_csrbank7_dma_length1_we $and$ls180.v:6232$1804_Y connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length0_re $and$ls180.v:6428$1948_Y - connect \builder_csrbank7_dma_length0_we $and$ls180.v:6429$1952_Y + connect \builder_csrbank7_dma_length0_re $and$ls180.v:6234$1807_Y + connect \builder_csrbank7_dma_length0_we $and$ls180.v:6235$1811_Y connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6431$1955_Y - connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6432$1959_Y + connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6237$1814_Y + connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6238$1818_Y connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_done_re $and$ls180.v:6434$1962_Y - connect \builder_csrbank7_dma_done_we $and$ls180.v:6435$1966_Y + connect \builder_csrbank7_dma_done_re $and$ls180.v:6240$1821_Y + connect \builder_csrbank7_dma_done_we $and$ls180.v:6241$1825_Y connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6437$1969_Y - connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6438$1973_Y + connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6243$1828_Y + connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6244$1832_Y connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6440$1976_Y - connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6441$1980_Y + connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6246$1835_Y + connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6247$1839_Y connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6443$1983_Y - connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6444$1987_Y + connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6249$1842_Y + connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6250$1846_Y connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6446$1990_Y - connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6447$1994_Y + connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6252$1849_Y + connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6253$1853_Y connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6449$1997_Y - connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6450$2001_Y + connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6255$1856_Y + connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6256$1860_Y connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] @@ -305201,54 +302014,54 @@ module \ls180 connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we - connect \builder_csrbank8_sel $eq$ls180.v:6472$2002_Y + connect \builder_csrbank8_sel $eq$ls180.v:6278$1861_Y connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_card_detect_re $and$ls180.v:6474$2005_Y - connect \builder_csrbank8_card_detect_we $and$ls180.v:6475$2009_Y + connect \builder_csrbank8_card_detect_re $and$ls180.v:6280$1864_Y + connect \builder_csrbank8_card_detect_we $and$ls180.v:6281$1868_Y connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6477$2012_Y - connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6478$2016_Y + connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6283$1871_Y + connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6284$1875_Y connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6480$2019_Y - connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6481$2023_Y + connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6286$1878_Y + connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6287$1882_Y connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0] - connect \main_sdphy_init_initialize_re $and$ls180.v:6483$2026_Y - connect \main_sdphy_init_initialize_we $and$ls180.v:6484$2030_Y + connect \main_sdphy_init_initialize_re $and$ls180.v:6289$1885_Y + connect \main_sdphy_init_initialize_we $and$ls180.v:6290$1889_Y connect \builder_csrbank8_card_detect_w \main_sdphy_status connect \main_sdphy_we \builder_csrbank8_card_detect_we connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8] connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0] - connect \builder_csrbank9_sel $eq$ls180.v:6489$2031_Y + connect \builder_csrbank9_sel $eq$ls180.v:6295$1890_Y connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0] - connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6491$2034_Y - connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6492$2038_Y + connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6297$1893_Y + connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6298$1897_Y connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0] - connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6494$2041_Y - connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6495$2045_Y + connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6300$1900_Y + connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6301$1904_Y connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0] - connect \main_sdram_command_issue_re $and$ls180.v:6497$2048_Y - connect \main_sdram_command_issue_we $and$ls180.v:6498$2052_Y + connect \main_sdram_command_issue_re $and$ls180.v:6303$1907_Y + connect \main_sdram_command_issue_we $and$ls180.v:6304$1911_Y connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0] - connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6500$2055_Y - connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6501$2059_Y + connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6306$1914_Y + connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6307$1918_Y connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6503$2062_Y - connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6504$2066_Y + connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6309$1921_Y + connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6310$1925_Y connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0] - connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6506$2069_Y - connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6507$2073_Y + connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6312$1928_Y + connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6313$1932_Y connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6509$2076_Y - connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6510$2080_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6315$1935_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6316$1939_Y connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6512$2083_Y - connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6513$2087_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6318$1942_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6319$1946_Y connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6515$2090_Y - connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6516$2094_Y + connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6321$1949_Y + connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6322$1953_Y connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6518$2097_Y - connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6519$2101_Y + connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6324$1956_Y + connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6325$1960_Y connect \main_sdram_sel \main_sdram_storage [0] connect \main_sdram_cke \main_sdram_storage [1] connect \main_sdram_odt \main_sdram_storage [2] @@ -305263,28 +302076,28 @@ module \ls180 connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8] connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0] connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we - connect \builder_csrbank10_sel $eq$ls180.v:6534$2102_Y + connect \builder_csrbank10_sel $eq$ls180.v:6340$1961_Y connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control1_re $and$ls180.v:6536$2105_Y - connect \builder_csrbank10_control1_we $and$ls180.v:6537$2109_Y + connect \builder_csrbank10_control1_re $and$ls180.v:6342$1964_Y + connect \builder_csrbank10_control1_we $and$ls180.v:6343$1968_Y connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control0_re $and$ls180.v:6539$2112_Y - connect \builder_csrbank10_control0_we $and$ls180.v:6540$2116_Y + connect \builder_csrbank10_control0_re $and$ls180.v:6345$1971_Y + connect \builder_csrbank10_control0_we $and$ls180.v:6346$1975_Y connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_status_re $and$ls180.v:6542$2119_Y - connect \builder_csrbank10_status_we $and$ls180.v:6543$2123_Y + connect \builder_csrbank10_status_re $and$ls180.v:6348$1978_Y + connect \builder_csrbank10_status_we $and$ls180.v:6349$1982_Y connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_mosi0_re $and$ls180.v:6545$2126_Y - connect \builder_csrbank10_mosi0_we $and$ls180.v:6546$2130_Y + connect \builder_csrbank10_mosi0_re $and$ls180.v:6351$1985_Y + connect \builder_csrbank10_mosi0_we $and$ls180.v:6352$1989_Y connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_miso_re $and$ls180.v:6548$2133_Y - connect \builder_csrbank10_miso_we $and$ls180.v:6549$2137_Y + connect \builder_csrbank10_miso_re $and$ls180.v:6354$1992_Y + connect \builder_csrbank10_miso_we $and$ls180.v:6355$1996_Y connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_cs0_re $and$ls180.v:6551$2140_Y - connect \builder_csrbank10_cs0_we $and$ls180.v:6552$2144_Y + connect \builder_csrbank10_cs0_re $and$ls180.v:6357$1999_Y + connect \builder_csrbank10_cs0_we $and$ls180.v:6358$2003_Y connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_loopback0_re $and$ls180.v:6554$2147_Y - connect \builder_csrbank10_loopback0_we $and$ls180.v:6555$2151_Y + connect \builder_csrbank10_loopback0_re $and$ls180.v:6360$2006_Y + connect \builder_csrbank10_loopback0_we $and$ls180.v:6361$2010_Y connect \main_spimaster10_length \main_spimaster11_storage [15:8] connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8] connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0] @@ -305297,34 +302110,34 @@ module \ls180 connect \main_spimaster20_sel \main_spimaster21_storage connect \builder_csrbank10_cs0_w \main_spimaster21_storage connect \builder_csrbank10_loopback0_w \main_spimaster23_storage - connect \builder_csrbank11_sel $eq$ls180.v:6574$2153_Y + connect \builder_csrbank11_sel $eq$ls180.v:6380$2012_Y connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control1_re $and$ls180.v:6576$2156_Y - connect \builder_csrbank11_control1_we $and$ls180.v:6577$2160_Y + connect \builder_csrbank11_control1_re $and$ls180.v:6382$2015_Y + connect \builder_csrbank11_control1_we $and$ls180.v:6383$2019_Y connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control0_re $and$ls180.v:6579$2163_Y - connect \builder_csrbank11_control0_we $and$ls180.v:6580$2167_Y + connect \builder_csrbank11_control0_re $and$ls180.v:6385$2022_Y + connect \builder_csrbank11_control0_we $and$ls180.v:6386$2026_Y connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_status_re $and$ls180.v:6582$2170_Y - connect \builder_csrbank11_status_we $and$ls180.v:6583$2174_Y + connect \builder_csrbank11_status_re $and$ls180.v:6388$2029_Y + connect \builder_csrbank11_status_we $and$ls180.v:6389$2033_Y connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_mosi0_re $and$ls180.v:6585$2177_Y - connect \builder_csrbank11_mosi0_we $and$ls180.v:6586$2181_Y + connect \builder_csrbank11_mosi0_re $and$ls180.v:6391$2036_Y + connect \builder_csrbank11_mosi0_we $and$ls180.v:6392$2040_Y connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_miso_re $and$ls180.v:6588$2184_Y - connect \builder_csrbank11_miso_we $and$ls180.v:6589$2188_Y + connect \builder_csrbank11_miso_re $and$ls180.v:6394$2043_Y + connect \builder_csrbank11_miso_we $and$ls180.v:6395$2047_Y connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_cs0_re $and$ls180.v:6591$2191_Y - connect \builder_csrbank11_cs0_we $and$ls180.v:6592$2195_Y + connect \builder_csrbank11_cs0_re $and$ls180.v:6397$2050_Y + connect \builder_csrbank11_cs0_we $and$ls180.v:6398$2054_Y connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_loopback0_re $and$ls180.v:6594$2198_Y - connect \builder_csrbank11_loopback0_we $and$ls180.v:6595$2202_Y + connect \builder_csrbank11_loopback0_re $and$ls180.v:6400$2057_Y + connect \builder_csrbank11_loopback0_we $and$ls180.v:6401$2061_Y connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6597$2205_Y - connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6598$2209_Y + connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6403$2064_Y + connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6404$2068_Y connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6600$2212_Y - connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6601$2216_Y + connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6406$2071_Y + connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6407$2075_Y connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8] connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8] connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0] @@ -305339,58 +302152,58 @@ module \ls180 connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8] connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0] - connect \builder_csrbank12_sel $eq$ls180.v:6622$2218_Y + connect \builder_csrbank12_sel $eq$ls180.v:6428$2077_Y connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load3_re $and$ls180.v:6624$2221_Y - connect \builder_csrbank12_load3_we $and$ls180.v:6625$2225_Y + connect \builder_csrbank12_load3_re $and$ls180.v:6430$2080_Y + connect \builder_csrbank12_load3_we $and$ls180.v:6431$2084_Y connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load2_re $and$ls180.v:6627$2228_Y - connect \builder_csrbank12_load2_we $and$ls180.v:6628$2232_Y + connect \builder_csrbank12_load2_re $and$ls180.v:6433$2087_Y + connect \builder_csrbank12_load2_we $and$ls180.v:6434$2091_Y connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load1_re $and$ls180.v:6630$2235_Y - connect \builder_csrbank12_load1_we $and$ls180.v:6631$2239_Y + connect \builder_csrbank12_load1_re $and$ls180.v:6436$2094_Y + connect \builder_csrbank12_load1_we $and$ls180.v:6437$2098_Y connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load0_re $and$ls180.v:6633$2242_Y - connect \builder_csrbank12_load0_we $and$ls180.v:6634$2246_Y + connect \builder_csrbank12_load0_re $and$ls180.v:6439$2101_Y + connect \builder_csrbank12_load0_we $and$ls180.v:6440$2105_Y connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload3_re $and$ls180.v:6636$2249_Y - connect \builder_csrbank12_reload3_we $and$ls180.v:6637$2253_Y + connect \builder_csrbank12_reload3_re $and$ls180.v:6442$2108_Y + connect \builder_csrbank12_reload3_we $and$ls180.v:6443$2112_Y connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload2_re $and$ls180.v:6639$2256_Y - connect \builder_csrbank12_reload2_we $and$ls180.v:6640$2260_Y + connect \builder_csrbank12_reload2_re $and$ls180.v:6445$2115_Y + connect \builder_csrbank12_reload2_we $and$ls180.v:6446$2119_Y connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload1_re $and$ls180.v:6642$2263_Y - connect \builder_csrbank12_reload1_we $and$ls180.v:6643$2267_Y + connect \builder_csrbank12_reload1_re $and$ls180.v:6448$2122_Y + connect \builder_csrbank12_reload1_we $and$ls180.v:6449$2126_Y connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload0_re $and$ls180.v:6645$2270_Y - connect \builder_csrbank12_reload0_we $and$ls180.v:6646$2274_Y + connect \builder_csrbank12_reload0_re $and$ls180.v:6451$2129_Y + connect \builder_csrbank12_reload0_we $and$ls180.v:6452$2133_Y connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_en0_re $and$ls180.v:6648$2277_Y - connect \builder_csrbank12_en0_we $and$ls180.v:6649$2281_Y + connect \builder_csrbank12_en0_re $and$ls180.v:6454$2136_Y + connect \builder_csrbank12_en0_we $and$ls180.v:6455$2140_Y connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_update_value0_re $and$ls180.v:6651$2284_Y - connect \builder_csrbank12_update_value0_we $and$ls180.v:6652$2288_Y + connect \builder_csrbank12_update_value0_re $and$ls180.v:6457$2143_Y + connect \builder_csrbank12_update_value0_we $and$ls180.v:6458$2147_Y connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value3_re $and$ls180.v:6654$2291_Y - connect \builder_csrbank12_value3_we $and$ls180.v:6655$2295_Y + connect \builder_csrbank12_value3_re $and$ls180.v:6460$2150_Y + connect \builder_csrbank12_value3_we $and$ls180.v:6461$2154_Y connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value2_re $and$ls180.v:6657$2298_Y - connect \builder_csrbank12_value2_we $and$ls180.v:6658$2302_Y + connect \builder_csrbank12_value2_re $and$ls180.v:6463$2157_Y + connect \builder_csrbank12_value2_we $and$ls180.v:6464$2161_Y connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value1_re $and$ls180.v:6660$2305_Y - connect \builder_csrbank12_value1_we $and$ls180.v:6661$2309_Y + connect \builder_csrbank12_value1_re $and$ls180.v:6466$2164_Y + connect \builder_csrbank12_value1_we $and$ls180.v:6467$2168_Y connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value0_re $and$ls180.v:6663$2312_Y - connect \builder_csrbank12_value0_we $and$ls180.v:6664$2316_Y + connect \builder_csrbank12_value0_re $and$ls180.v:6469$2171_Y + connect \builder_csrbank12_value0_we $and$ls180.v:6470$2175_Y connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6666$2319_Y - connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6667$2323_Y + connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6472$2178_Y + connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6473$2182_Y connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6669$2326_Y - connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6670$2330_Y + connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6475$2185_Y + connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6476$2189_Y connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6672$2333_Y - connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6673$2337_Y + connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6478$2192_Y + connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6479$2196_Y connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24] connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16] connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8] @@ -305407,31 +302220,31 @@ module \ls180 connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0] connect \main_libresocsim_value_we \builder_csrbank12_value0_we connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage - connect \builder_csrbank13_sel $eq$ls180.v:6690$2338_Y + connect \builder_csrbank13_sel $eq$ls180.v:6496$2197_Y connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w - connect \main_uart_rxtx_re $and$ls180.v:6692$2341_Y - connect \main_uart_rxtx_we $and$ls180.v:6693$2345_Y + connect \main_uart_rxtx_re $and$ls180.v:6498$2200_Y + connect \main_uart_rxtx_we $and$ls180.v:6499$2204_Y connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txfull_re $and$ls180.v:6695$2348_Y - connect \builder_csrbank13_txfull_we $and$ls180.v:6696$2352_Y + connect \builder_csrbank13_txfull_re $and$ls180.v:6501$2207_Y + connect \builder_csrbank13_txfull_we $and$ls180.v:6502$2211_Y connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxempty_re $and$ls180.v:6698$2355_Y - connect \builder_csrbank13_rxempty_we $and$ls180.v:6699$2359_Y + connect \builder_csrbank13_rxempty_re $and$ls180.v:6504$2214_Y + connect \builder_csrbank13_rxempty_we $and$ls180.v:6505$2218_Y connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_status_re $and$ls180.v:6701$2362_Y - connect \main_uart_eventmanager_status_we $and$ls180.v:6702$2366_Y + connect \main_uart_eventmanager_status_re $and$ls180.v:6507$2221_Y + connect \main_uart_eventmanager_status_we $and$ls180.v:6508$2225_Y connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_pending_re $and$ls180.v:6704$2369_Y - connect \main_uart_eventmanager_pending_we $and$ls180.v:6705$2373_Y + connect \main_uart_eventmanager_pending_re $and$ls180.v:6510$2228_Y + connect \main_uart_eventmanager_pending_we $and$ls180.v:6511$2232_Y connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0] - connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6707$2376_Y - connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6708$2380_Y + connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6513$2235_Y + connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6514$2239_Y connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txempty_re $and$ls180.v:6710$2383_Y - connect \builder_csrbank13_txempty_we $and$ls180.v:6711$2387_Y + connect \builder_csrbank13_txempty_re $and$ls180.v:6516$2242_Y + connect \builder_csrbank13_txempty_we $and$ls180.v:6517$2246_Y connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxfull_re $and$ls180.v:6713$2390_Y - connect \builder_csrbank13_rxfull_we $and$ls180.v:6714$2394_Y + connect \builder_csrbank13_rxfull_re $and$ls180.v:6519$2249_Y + connect \builder_csrbank13_rxfull_we $and$ls180.v:6520$2253_Y connect \builder_csrbank13_txfull_w \main_uart_txfull_status connect \main_uart_txfull_we \builder_csrbank13_txfull_we connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status @@ -305441,19 +302254,19 @@ module \ls180 connect \main_uart_txempty_we \builder_csrbank13_txempty_we connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we - connect \builder_csrbank14_sel $eq$ls180.v:6724$2395_Y + connect \builder_csrbank14_sel $eq$ls180.v:6530$2254_Y connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6726$2398_Y - connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6727$2402_Y + connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6532$2257_Y + connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6533$2261_Y connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6729$2405_Y - connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6730$2409_Y + connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6535$2264_Y + connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6536$2268_Y connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6732$2412_Y - connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6733$2416_Y + connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6538$2271_Y + connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6539$2275_Y connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6735$2419_Y - connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6736$2423_Y + connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6541$2278_Y + connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6542$2282_Y connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24] connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16] connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8] @@ -305507,7 +302320,7 @@ module \ls180 connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_csr_interconnect_dat_r $or$ls180.v:6790$2437_Y + connect \builder_csr_interconnect_dat_r $or$ls180.v:6596$2296_Y connect \sdrio_clk \sys_clk_1 connect \sdrio_clk_1 \sys_clk_1 connect \sdrio_clk_2 \sys_clk_1 @@ -305584,59 +302397,56 @@ module \ls180 connect \sdrio_clk_66 \sys_clk_1 connect \sdrio_clk_67 \sys_clk_1 connect \sdrio_clk_68 \sys_clk_1 - connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10373$2918_DATA - connect \main_sram0_dat_r $memrd$\mem_1$ls180.v:10401$2944_DATA - connect \main_sram1_dat_r $memrd$\mem_2$ls180.v:10429$2970_DATA - connect \main_sram2_dat_r $memrd$\mem_3$ls180.v:10457$2996_DATA - connect \main_sram3_dat_r $memrd$\mem_4$ls180.v:10485$3022_DATA + connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10164$2768_DATA + connect \main_ram_dat_r $memrd$\mem_1$ls180.v:10192$2794_DATA connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10503$3029_DATA + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10210$2801_DATA connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10517$3036_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10224$2808_DATA connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10531$3043_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10238$2815_DATA connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10545$3050_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10252$2822_DATA connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 - connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10593$3071_DATA + connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10300$2843_DATA connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 - connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10607$3078_DATA + connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10314$2850_DATA end -attribute \src "libresoc.v:146562.1-146620.10" +attribute \src "libresoc.v:146561.1-146619.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l" attribute \generator "nMigen" module \lsd_l - attribute \src "libresoc.v:146563.7-146563.20" + attribute \src "libresoc.v:146562.7-146562.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146608.3-146616.6" + attribute \src "libresoc.v:146607.3-146615.6" wire $0\q_int$next[0:0]$7149 - attribute \src "libresoc.v:146606.3-146607.27" + attribute \src "libresoc.v:146605.3-146606.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:146608.3-146616.6" + attribute \src "libresoc.v:146607.3-146615.6" wire $1\q_int$next[0:0]$7150 - attribute \src "libresoc.v:146585.7-146585.19" + attribute \src "libresoc.v:146584.7-146584.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:146598.17-146598.96" - wire $and$libresoc.v:146598$7139_Y - attribute \src "libresoc.v:146603.17-146603.96" - wire $and$libresoc.v:146603$7144_Y - attribute \src "libresoc.v:146600.18-146600.93" - wire $not$libresoc.v:146600$7141_Y - attribute \src "libresoc.v:146602.17-146602.92" - wire $not$libresoc.v:146602$7143_Y - attribute \src "libresoc.v:146605.17-146605.92" - wire $not$libresoc.v:146605$7146_Y - attribute \src "libresoc.v:146599.18-146599.98" - wire $or$libresoc.v:146599$7140_Y - attribute \src "libresoc.v:146601.18-146601.99" - wire $or$libresoc.v:146601$7142_Y - attribute \src "libresoc.v:146604.17-146604.97" - wire $or$libresoc.v:146604$7145_Y + attribute \src "libresoc.v:146597.17-146597.96" + wire $and$libresoc.v:146597$7139_Y + attribute \src "libresoc.v:146602.17-146602.96" + wire $and$libresoc.v:146602$7144_Y + attribute \src "libresoc.v:146599.18-146599.93" + wire $not$libresoc.v:146599$7141_Y + attribute \src "libresoc.v:146601.17-146601.92" + wire $not$libresoc.v:146601$7143_Y + attribute \src "libresoc.v:146604.17-146604.92" + wire $not$libresoc.v:146604$7146_Y + attribute \src "libresoc.v:146598.18-146598.98" + wire $or$libresoc.v:146598$7140_Y + attribute \src "libresoc.v:146600.18-146600.99" + wire $or$libresoc.v:146600$7142_Y + attribute \src "libresoc.v:146603.17-146603.97" + wire $or$libresoc.v:146603$7145_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -305657,7 +302467,7 @@ module \lsd_l wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:146563.7-146563.15" + attribute \src "libresoc.v:146562.7-146562.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -305674,7 +302484,7 @@ module \lsd_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lsd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:146598$7139 + cell $and $and$libresoc.v:146597$7139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305682,10 +302492,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:146598$7139_Y + connect \Y $and$libresoc.v:146597$7139_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:146603$7144 + cell $and $and$libresoc.v:146602$7144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305693,34 +302503,34 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:146603$7144_Y + connect \Y $and$libresoc.v:146602$7144_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:146600$7141 + cell $not $not$libresoc.v:146599$7141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lsd - connect \Y $not$libresoc.v:146600$7141_Y + connect \Y $not$libresoc.v:146599$7141_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:146602$7143 + cell $not $not$libresoc.v:146601$7143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:146602$7143_Y + connect \Y $not$libresoc.v:146601$7143_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:146605$7146 + cell $not $not$libresoc.v:146604$7146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:146605$7146_Y + connect \Y $not$libresoc.v:146604$7146_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:146599$7140 + cell $or $or$libresoc.v:146598$7140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305728,10 +302538,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lsd - connect \Y $or$libresoc.v:146599$7140_Y + connect \Y $or$libresoc.v:146598$7140_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:146601$7142 + cell $or $or$libresoc.v:146600$7142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305739,10 +302549,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_lsd connect \B \q_int - connect \Y $or$libresoc.v:146601$7142_Y + connect \Y $or$libresoc.v:146600$7142_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:146604$7145 + cell $or $or$libresoc.v:146603$7145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305750,39 +302560,39 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lsd - connect \Y $or$libresoc.v:146604$7145_Y + connect \Y $or$libresoc.v:146603$7145_Y end - attribute \src "libresoc.v:146563.7-146563.20" - process $proc$libresoc.v:146563$7151 + attribute \src "libresoc.v:146562.7-146562.20" + process $proc$libresoc.v:146562$7151 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146585.7-146585.19" - process $proc$libresoc.v:146585$7152 + attribute \src "libresoc.v:146584.7-146584.19" + process $proc$libresoc.v:146584$7152 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:146606.3-146607.27" - process $proc$libresoc.v:146606$7147 + attribute \src "libresoc.v:146605.3-146606.27" + process $proc$libresoc.v:146605$7147 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:146608.3-146616.6" - process $proc$libresoc.v:146608$7148 + attribute \src "libresoc.v:146607.3-146615.6" + process $proc$libresoc.v:146607$7148 assign { } { } assign { } { } assign $0\q_int$next[0:0]$7149 $1\q_int$next[0:0]$7150 - attribute \src "libresoc.v:146609.5-146609.29" + attribute \src "libresoc.v:146608.5-146608.29" switch \initial - attribute \src "libresoc.v:146609.9-146609.17" + attribute \src "libresoc.v:146608.9-146608.17" case 1'1 case end @@ -305798,259 +302608,259 @@ module \lsd_l sync always update \q_int$next $0\q_int$next[0:0]$7149 end - connect \$9 $and$libresoc.v:146598$7139_Y - connect \$11 $or$libresoc.v:146599$7140_Y - connect \$13 $not$libresoc.v:146600$7141_Y - connect \$15 $or$libresoc.v:146601$7142_Y - connect \$1 $not$libresoc.v:146602$7143_Y - connect \$3 $and$libresoc.v:146603$7144_Y - connect \$5 $or$libresoc.v:146604$7145_Y - connect \$7 $not$libresoc.v:146605$7146_Y + connect \$9 $and$libresoc.v:146597$7139_Y + connect \$11 $or$libresoc.v:146598$7140_Y + connect \$13 $not$libresoc.v:146599$7141_Y + connect \$15 $or$libresoc.v:146600$7142_Y + connect \$1 $not$libresoc.v:146601$7143_Y + connect \$3 $and$libresoc.v:146602$7144_Y + connect \$5 $or$libresoc.v:146603$7145_Y + connect \$7 $not$libresoc.v:146604$7146_Y connect \qlq_lsd \$15 connect \qn_lsd \$13 connect \q_lsd \$11 end -attribute \src "libresoc.v:146624.1-147158.10" +attribute \src "libresoc.v:146623.1-147157.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.lsmem" attribute \generator "nMigen" module \lsmem - attribute \src "libresoc.v:147012.3-147037.6" + attribute \src "libresoc.v:147011.3-147036.6" wire width 45 $0\dbus__adr$next[44:0]$7238 - attribute \src "libresoc.v:146862.3-146863.35" + attribute \src "libresoc.v:146861.3-146862.35" wire width 45 $0\dbus__adr[44:0] - attribute \src "libresoc.v:146872.3-146899.6" + attribute \src "libresoc.v:146871.3-146898.6" wire $0\dbus__cyc$next[0:0]$7212 - attribute \src "libresoc.v:146870.3-146871.35" + attribute \src "libresoc.v:146869.3-146870.35" wire $0\dbus__cyc[0:0] - attribute \src "libresoc.v:147064.3-147089.6" + attribute \src "libresoc.v:147063.3-147088.6" wire width 64 $0\dbus__dat_w$next[63:0]$7248 - attribute \src "libresoc.v:146858.3-146859.39" + attribute \src "libresoc.v:146857.3-146858.39" wire width 64 $0\dbus__dat_w[63:0] - attribute \src "libresoc.v:146956.3-146986.6" + attribute \src "libresoc.v:146955.3-146985.6" wire width 8 $0\dbus__sel$next[7:0]$7226 - attribute \src "libresoc.v:146866.3-146867.35" + attribute \src "libresoc.v:146865.3-146866.35" wire width 8 $0\dbus__sel[7:0] - attribute \src "libresoc.v:146900.3-146927.6" + attribute \src "libresoc.v:146899.3-146926.6" wire $0\dbus__stb$next[0:0]$7218 - attribute \src "libresoc.v:146868.3-146869.35" + attribute \src "libresoc.v:146867.3-146868.35" wire $0\dbus__stb[0:0] - attribute \src "libresoc.v:147038.3-147063.6" + attribute \src "libresoc.v:147037.3-147062.6" wire $0\dbus__we$next[0:0]$7243 - attribute \src "libresoc.v:146860.3-146861.33" + attribute \src "libresoc.v:146859.3-146860.33" wire $0\dbus__we[0:0] - attribute \src "libresoc.v:146625.7-146625.20" + attribute \src "libresoc.v:146624.7-146624.20" wire $0\initial[0:0] - attribute \src "libresoc.v:147136.3-147155.6" + attribute \src "libresoc.v:147135.3-147154.6" wire width 45 $0\m_badaddr_o$next[44:0]$7263 - attribute \src "libresoc.v:146852.3-146853.39" + attribute \src "libresoc.v:146851.3-146852.39" wire width 45 $0\m_badaddr_o[44:0] - attribute \src "libresoc.v:146938.3-146955.6" + attribute \src "libresoc.v:146937.3-146954.6" wire $0\m_busy_o[0:0] - attribute \src "libresoc.v:146987.3-147011.6" + attribute \src "libresoc.v:146986.3-147010.6" wire width 64 $0\m_ld_data_o$next[63:0]$7232 - attribute \src "libresoc.v:146864.3-146865.39" + attribute \src "libresoc.v:146863.3-146864.39" wire width 64 $0\m_ld_data_o[63:0] - attribute \src "libresoc.v:147090.3-147112.6" + attribute \src "libresoc.v:147089.3-147111.6" wire $0\m_load_err_o$next[0:0]$7253 - attribute \src "libresoc.v:146856.3-146857.41" + attribute \src "libresoc.v:146855.3-146856.41" wire $0\m_load_err_o[0:0] - attribute \src "libresoc.v:147113.3-147135.6" + attribute \src "libresoc.v:147112.3-147134.6" wire $0\m_store_err_o$next[0:0]$7258 - attribute \src "libresoc.v:146854.3-146855.43" + attribute \src "libresoc.v:146853.3-146854.43" wire $0\m_store_err_o[0:0] - attribute \src "libresoc.v:146928.3-146937.6" + attribute \src "libresoc.v:146927.3-146936.6" wire $0\x_busy_o[0:0] - attribute \src "libresoc.v:147012.3-147037.6" + attribute \src "libresoc.v:147011.3-147036.6" wire width 45 $1\dbus__adr$next[44:0]$7239 - attribute \src "libresoc.v:146730.14-146730.42" + attribute \src "libresoc.v:146729.14-146729.42" wire width 45 $1\dbus__adr[44:0] - attribute \src "libresoc.v:146872.3-146899.6" + attribute \src "libresoc.v:146871.3-146898.6" wire $1\dbus__cyc$next[0:0]$7213 - attribute \src "libresoc.v:146735.7-146735.23" + attribute \src "libresoc.v:146734.7-146734.23" wire $1\dbus__cyc[0:0] - attribute \src "libresoc.v:147064.3-147089.6" + attribute \src "libresoc.v:147063.3-147088.6" wire width 64 $1\dbus__dat_w$next[63:0]$7249 - attribute \src "libresoc.v:146742.14-146742.48" + attribute \src "libresoc.v:146741.14-146741.48" wire width 64 $1\dbus__dat_w[63:0] - attribute \src "libresoc.v:146956.3-146986.6" + attribute \src "libresoc.v:146955.3-146985.6" wire width 8 $1\dbus__sel$next[7:0]$7227 - attribute \src "libresoc.v:146749.13-146749.30" + attribute \src "libresoc.v:146748.13-146748.30" wire width 8 $1\dbus__sel[7:0] - attribute \src "libresoc.v:146900.3-146927.6" + attribute \src "libresoc.v:146899.3-146926.6" wire $1\dbus__stb$next[0:0]$7219 - attribute \src "libresoc.v:146754.7-146754.23" + attribute \src "libresoc.v:146753.7-146753.23" wire $1\dbus__stb[0:0] - attribute \src "libresoc.v:147038.3-147063.6" + attribute \src "libresoc.v:147037.3-147062.6" wire $1\dbus__we$next[0:0]$7244 - attribute \src "libresoc.v:146759.7-146759.22" + attribute \src "libresoc.v:146758.7-146758.22" wire $1\dbus__we[0:0] - attribute \src "libresoc.v:147136.3-147155.6" + attribute \src "libresoc.v:147135.3-147154.6" wire width 45 $1\m_badaddr_o$next[44:0]$7264 - attribute \src "libresoc.v:146763.14-146763.44" + attribute \src "libresoc.v:146762.14-146762.44" wire width 45 $1\m_badaddr_o[44:0] - attribute \src "libresoc.v:146938.3-146955.6" + attribute \src "libresoc.v:146937.3-146954.6" wire $1\m_busy_o[0:0] - attribute \src "libresoc.v:146987.3-147011.6" + attribute \src "libresoc.v:146986.3-147010.6" wire width 64 $1\m_ld_data_o$next[63:0]$7233 - attribute \src "libresoc.v:146770.14-146770.48" + attribute \src "libresoc.v:146769.14-146769.48" wire width 64 $1\m_ld_data_o[63:0] - attribute \src "libresoc.v:147090.3-147112.6" + attribute \src "libresoc.v:147089.3-147111.6" wire $1\m_load_err_o$next[0:0]$7254 - attribute \src "libresoc.v:146774.7-146774.26" + attribute \src "libresoc.v:146773.7-146773.26" wire $1\m_load_err_o[0:0] - attribute \src "libresoc.v:147113.3-147135.6" + attribute \src "libresoc.v:147112.3-147134.6" wire $1\m_store_err_o$next[0:0]$7259 - attribute \src "libresoc.v:146780.7-146780.27" + attribute \src "libresoc.v:146779.7-146779.27" wire $1\m_store_err_o[0:0] - attribute \src "libresoc.v:146928.3-146937.6" + attribute \src "libresoc.v:146927.3-146936.6" wire $1\x_busy_o[0:0] - attribute \src "libresoc.v:147012.3-147037.6" + attribute \src "libresoc.v:147011.3-147036.6" wire width 45 $2\dbus__adr$next[44:0]$7240 - attribute \src "libresoc.v:146872.3-146899.6" + attribute \src "libresoc.v:146871.3-146898.6" wire $2\dbus__cyc$next[0:0]$7214 - attribute \src "libresoc.v:147064.3-147089.6" + attribute \src "libresoc.v:147063.3-147088.6" wire width 64 $2\dbus__dat_w$next[63:0]$7250 - attribute \src "libresoc.v:146956.3-146986.6" + attribute \src "libresoc.v:146955.3-146985.6" wire width 8 $2\dbus__sel$next[7:0]$7228 - attribute \src "libresoc.v:146900.3-146927.6" + attribute \src "libresoc.v:146899.3-146926.6" wire $2\dbus__stb$next[0:0]$7220 - attribute \src "libresoc.v:147038.3-147063.6" + attribute \src "libresoc.v:147037.3-147062.6" wire $2\dbus__we$next[0:0]$7245 - attribute \src "libresoc.v:147136.3-147155.6" + attribute \src "libresoc.v:147135.3-147154.6" wire width 45 $2\m_badaddr_o$next[44:0]$7265 - attribute \src "libresoc.v:146938.3-146955.6" + attribute \src "libresoc.v:146937.3-146954.6" wire $2\m_busy_o[0:0] - attribute \src "libresoc.v:146987.3-147011.6" + attribute \src "libresoc.v:146986.3-147010.6" wire width 64 $2\m_ld_data_o$next[63:0]$7234 - attribute \src "libresoc.v:147090.3-147112.6" + attribute \src "libresoc.v:147089.3-147111.6" wire $2\m_load_err_o$next[0:0]$7255 - attribute \src "libresoc.v:147113.3-147135.6" + attribute \src "libresoc.v:147112.3-147134.6" wire $2\m_store_err_o$next[0:0]$7260 - attribute \src "libresoc.v:147012.3-147037.6" + attribute \src "libresoc.v:147011.3-147036.6" wire width 45 $3\dbus__adr$next[44:0]$7241 - attribute \src "libresoc.v:146872.3-146899.6" + attribute \src "libresoc.v:146871.3-146898.6" wire $3\dbus__cyc$next[0:0]$7215 - attribute \src "libresoc.v:147064.3-147089.6" + attribute \src "libresoc.v:147063.3-147088.6" wire width 64 $3\dbus__dat_w$next[63:0]$7251 - attribute \src "libresoc.v:146956.3-146986.6" + attribute \src "libresoc.v:146955.3-146985.6" wire width 8 $3\dbus__sel$next[7:0]$7229 - attribute \src "libresoc.v:146900.3-146927.6" + attribute \src "libresoc.v:146899.3-146926.6" wire $3\dbus__stb$next[0:0]$7221 - attribute \src "libresoc.v:147038.3-147063.6" + attribute \src "libresoc.v:147037.3-147062.6" wire $3\dbus__we$next[0:0]$7246 - attribute \src "libresoc.v:147136.3-147155.6" + attribute \src "libresoc.v:147135.3-147154.6" wire width 45 $3\m_badaddr_o$next[44:0]$7266 - attribute \src "libresoc.v:146987.3-147011.6" + attribute \src "libresoc.v:146986.3-147010.6" wire width 64 $3\m_ld_data_o$next[63:0]$7235 - attribute \src "libresoc.v:147090.3-147112.6" + attribute \src "libresoc.v:147089.3-147111.6" wire $3\m_load_err_o$next[0:0]$7256 - attribute \src "libresoc.v:147113.3-147135.6" + attribute \src "libresoc.v:147112.3-147134.6" wire $3\m_store_err_o$next[0:0]$7261 - attribute \src "libresoc.v:146872.3-146899.6" + attribute \src "libresoc.v:146871.3-146898.6" wire $4\dbus__cyc$next[0:0]$7216 - attribute \src "libresoc.v:146956.3-146986.6" + attribute \src "libresoc.v:146955.3-146985.6" wire width 8 $4\dbus__sel$next[7:0]$7230 - attribute \src "libresoc.v:146900.3-146927.6" + attribute \src "libresoc.v:146899.3-146926.6" wire $4\dbus__stb$next[0:0]$7222 - attribute \src "libresoc.v:146987.3-147011.6" + attribute \src "libresoc.v:146986.3-147010.6" wire width 64 $4\m_ld_data_o$next[63:0]$7236 - attribute \src "libresoc.v:146808.18-146808.116" - wire $and$libresoc.v:146808$7157_Y - attribute \src "libresoc.v:146811.18-146811.111" - wire $and$libresoc.v:146811$7160_Y - attribute \src "libresoc.v:146816.18-146816.116" - wire $and$libresoc.v:146816$7165_Y - attribute \src "libresoc.v:146818.18-146818.111" - wire $and$libresoc.v:146818$7167_Y - attribute \src "libresoc.v:146820.17-146820.114" - wire $and$libresoc.v:146820$7169_Y - attribute \src "libresoc.v:146824.18-146824.116" - wire $and$libresoc.v:146824$7173_Y - attribute \src "libresoc.v:146826.18-146826.111" - wire $and$libresoc.v:146826$7175_Y - attribute \src "libresoc.v:146832.18-146832.116" - wire $and$libresoc.v:146832$7181_Y - attribute \src "libresoc.v:146834.18-146834.111" - wire $and$libresoc.v:146834$7183_Y - attribute \src "libresoc.v:146836.18-146836.116" - wire $and$libresoc.v:146836$7185_Y - attribute \src "libresoc.v:146838.18-146838.111" - wire $and$libresoc.v:146838$7187_Y - attribute \src "libresoc.v:146840.18-146840.116" - wire $and$libresoc.v:146840$7189_Y - attribute \src "libresoc.v:146842.17-146842.108" - wire $and$libresoc.v:146842$7191_Y - attribute \src "libresoc.v:146843.18-146843.111" - wire $and$libresoc.v:146843$7192_Y - attribute \src "libresoc.v:146844.18-146844.120" - wire $and$libresoc.v:146844$7193_Y - attribute \src "libresoc.v:146847.18-146847.120" - wire $and$libresoc.v:146847$7196_Y - attribute \src "libresoc.v:146849.18-146849.120" - wire $and$libresoc.v:146849$7198_Y + attribute \src "libresoc.v:146807.18-146807.116" + wire $and$libresoc.v:146807$7157_Y + attribute \src "libresoc.v:146810.18-146810.111" + wire $and$libresoc.v:146810$7160_Y + attribute \src "libresoc.v:146815.18-146815.116" + wire $and$libresoc.v:146815$7165_Y + attribute \src "libresoc.v:146817.18-146817.111" + wire $and$libresoc.v:146817$7167_Y + attribute \src "libresoc.v:146819.17-146819.114" + wire $and$libresoc.v:146819$7169_Y + attribute \src "libresoc.v:146823.18-146823.116" + wire $and$libresoc.v:146823$7173_Y + attribute \src "libresoc.v:146825.18-146825.111" + wire $and$libresoc.v:146825$7175_Y + attribute \src "libresoc.v:146831.18-146831.116" + wire $and$libresoc.v:146831$7181_Y + attribute \src "libresoc.v:146833.18-146833.111" + wire $and$libresoc.v:146833$7183_Y + attribute \src "libresoc.v:146835.18-146835.116" + wire $and$libresoc.v:146835$7185_Y + attribute \src "libresoc.v:146837.18-146837.111" + wire $and$libresoc.v:146837$7187_Y + attribute \src "libresoc.v:146839.18-146839.116" + wire $and$libresoc.v:146839$7189_Y + attribute \src "libresoc.v:146841.17-146841.108" + wire $and$libresoc.v:146841$7191_Y + attribute \src "libresoc.v:146842.18-146842.111" + wire $and$libresoc.v:146842$7192_Y + attribute \src "libresoc.v:146843.18-146843.120" + wire $and$libresoc.v:146843$7193_Y + attribute \src "libresoc.v:146846.18-146846.120" + wire $and$libresoc.v:146846$7196_Y + attribute \src "libresoc.v:146848.18-146848.120" + wire $and$libresoc.v:146848$7198_Y + attribute \src "libresoc.v:146804.18-146804.110" + wire $not$libresoc.v:146804$7154_Y + attribute \src "libresoc.v:146809.18-146809.110" + wire $not$libresoc.v:146809$7159_Y + attribute \src "libresoc.v:146812.18-146812.110" + wire $not$libresoc.v:146812$7162_Y + attribute \src "libresoc.v:146816.18-146816.110" + wire $not$libresoc.v:146816$7166_Y + attribute \src "libresoc.v:146820.18-146820.110" + wire $not$libresoc.v:146820$7170_Y + attribute \src "libresoc.v:146824.18-146824.110" + wire $not$libresoc.v:146824$7174_Y + attribute \src "libresoc.v:146827.18-146827.110" + wire $not$libresoc.v:146827$7177_Y + attribute \src "libresoc.v:146830.17-146830.109" + wire $not$libresoc.v:146830$7180_Y + attribute \src "libresoc.v:146832.18-146832.110" + wire $not$libresoc.v:146832$7182_Y + attribute \src "libresoc.v:146836.18-146836.110" + wire $not$libresoc.v:146836$7186_Y + attribute \src "libresoc.v:146840.18-146840.110" + wire $not$libresoc.v:146840$7190_Y + attribute \src "libresoc.v:146844.18-146844.110" + wire $not$libresoc.v:146844$7194_Y + attribute \src "libresoc.v:146845.18-146845.109" + wire $not$libresoc.v:146845$7195_Y + attribute \src "libresoc.v:146847.18-146847.110" + wire $not$libresoc.v:146847$7197_Y + attribute \src "libresoc.v:146849.18-146849.110" + wire $not$libresoc.v:146849$7199_Y + attribute \src "libresoc.v:146803.17-146803.119" + wire $or$libresoc.v:146803$7153_Y attribute \src "libresoc.v:146805.18-146805.110" - wire $not$libresoc.v:146805$7154_Y - attribute \src "libresoc.v:146810.18-146810.110" - wire $not$libresoc.v:146810$7159_Y - attribute \src "libresoc.v:146813.18-146813.110" - wire $not$libresoc.v:146813$7162_Y - attribute \src "libresoc.v:146817.18-146817.110" - wire $not$libresoc.v:146817$7166_Y - attribute \src "libresoc.v:146821.18-146821.110" - wire $not$libresoc.v:146821$7170_Y - attribute \src "libresoc.v:146825.18-146825.110" - wire $not$libresoc.v:146825$7174_Y - attribute \src "libresoc.v:146828.18-146828.110" - wire $not$libresoc.v:146828$7177_Y - attribute \src "libresoc.v:146831.17-146831.109" - wire $not$libresoc.v:146831$7180_Y - attribute \src "libresoc.v:146833.18-146833.110" - wire $not$libresoc.v:146833$7182_Y - attribute \src "libresoc.v:146837.18-146837.110" - wire $not$libresoc.v:146837$7186_Y - attribute \src "libresoc.v:146841.18-146841.110" - wire $not$libresoc.v:146841$7190_Y - attribute \src "libresoc.v:146845.18-146845.110" - wire $not$libresoc.v:146845$7194_Y - attribute \src "libresoc.v:146846.18-146846.109" - wire $not$libresoc.v:146846$7195_Y - attribute \src "libresoc.v:146848.18-146848.110" - wire $not$libresoc.v:146848$7197_Y - attribute \src "libresoc.v:146850.18-146850.110" - wire $not$libresoc.v:146850$7199_Y - attribute \src "libresoc.v:146804.17-146804.119" - wire $or$libresoc.v:146804$7153_Y - attribute \src "libresoc.v:146806.18-146806.110" - wire $or$libresoc.v:146806$7155_Y - attribute \src "libresoc.v:146807.18-146807.114" - wire $or$libresoc.v:146807$7156_Y - attribute \src "libresoc.v:146809.17-146809.113" - wire $or$libresoc.v:146809$7158_Y - attribute \src "libresoc.v:146812.18-146812.120" - wire $or$libresoc.v:146812$7161_Y - attribute \src "libresoc.v:146814.18-146814.111" - wire $or$libresoc.v:146814$7163_Y - attribute \src "libresoc.v:146815.18-146815.114" - wire $or$libresoc.v:146815$7164_Y - attribute \src "libresoc.v:146819.18-146819.120" - wire $or$libresoc.v:146819$7168_Y - attribute \src "libresoc.v:146822.18-146822.111" - wire $or$libresoc.v:146822$7171_Y - attribute \src "libresoc.v:146823.18-146823.114" - wire $or$libresoc.v:146823$7172_Y - attribute \src "libresoc.v:146827.18-146827.120" - wire $or$libresoc.v:146827$7176_Y - attribute \src "libresoc.v:146829.18-146829.111" - wire $or$libresoc.v:146829$7178_Y - attribute \src "libresoc.v:146830.18-146830.114" - wire $or$libresoc.v:146830$7179_Y - attribute \src "libresoc.v:146835.18-146835.114" - wire $or$libresoc.v:146835$7184_Y - attribute \src "libresoc.v:146839.18-146839.114" - wire $or$libresoc.v:146839$7188_Y - attribute \src "libresoc.v:146851.18-146851.127" - wire $or$libresoc.v:146851$7200_Y + wire $or$libresoc.v:146805$7155_Y + attribute \src "libresoc.v:146806.18-146806.114" + wire $or$libresoc.v:146806$7156_Y + attribute \src "libresoc.v:146808.17-146808.113" + wire $or$libresoc.v:146808$7158_Y + attribute \src "libresoc.v:146811.18-146811.120" + wire $or$libresoc.v:146811$7161_Y + attribute \src "libresoc.v:146813.18-146813.111" + wire $or$libresoc.v:146813$7163_Y + attribute \src "libresoc.v:146814.18-146814.114" + wire $or$libresoc.v:146814$7164_Y + attribute \src "libresoc.v:146818.18-146818.120" + wire $or$libresoc.v:146818$7168_Y + attribute \src "libresoc.v:146821.18-146821.111" + wire $or$libresoc.v:146821$7171_Y + attribute \src "libresoc.v:146822.18-146822.114" + wire $or$libresoc.v:146822$7172_Y + attribute \src "libresoc.v:146826.18-146826.120" + wire $or$libresoc.v:146826$7176_Y + attribute \src "libresoc.v:146828.18-146828.111" + wire $or$libresoc.v:146828$7178_Y + attribute \src "libresoc.v:146829.18-146829.114" + wire $or$libresoc.v:146829$7179_Y + attribute \src "libresoc.v:146834.18-146834.114" + wire $or$libresoc.v:146834$7184_Y + attribute \src "libresoc.v:146838.18-146838.114" + wire $or$libresoc.v:146838$7188_Y + attribute \src "libresoc.v:146850.18-146850.127" + wire $or$libresoc.v:146850$7200_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" @@ -306181,7 +302991,7 @@ module \lsmem wire output 19 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire \dbus__we$next - attribute \src "libresoc.v:146625.7-146625.15" + attribute \src "libresoc.v:146624.7-146624.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" wire width 45 \m_badaddr_o @@ -306224,7 +303034,7 @@ module \lsmem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire input 10 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146808$7157 + cell $and $and$libresoc.v:146807$7157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306232,10 +303042,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$15 connect \B \x_valid_i - connect \Y $and$libresoc.v:146808$7157_Y + connect \Y $and$libresoc.v:146807$7157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146811$7160 + cell $and $and$libresoc.v:146810$7160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306243,10 +303053,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$17 connect \B \$19 - connect \Y $and$libresoc.v:146811$7160_Y + connect \Y $and$libresoc.v:146810$7160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146816$7165 + cell $and $and$libresoc.v:146815$7165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306254,10 +303064,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$29 connect \B \x_valid_i - connect \Y $and$libresoc.v:146816$7165_Y + connect \Y $and$libresoc.v:146815$7165_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146818$7167 + cell $and $and$libresoc.v:146817$7167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306265,10 +303075,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:146818$7167_Y + connect \Y $and$libresoc.v:146817$7167_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146820$7169 + cell $and $and$libresoc.v:146819$7169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306276,10 +303086,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$1 connect \B \x_valid_i - connect \Y $and$libresoc.v:146820$7169_Y + connect \Y $and$libresoc.v:146819$7169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146824$7173 + cell $and $and$libresoc.v:146823$7173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306287,10 +303097,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$43 connect \B \x_valid_i - connect \Y $and$libresoc.v:146824$7173_Y + connect \Y $and$libresoc.v:146823$7173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146826$7175 + cell $and $and$libresoc.v:146825$7175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306298,10 +303108,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$45 connect \B \$47 - connect \Y $and$libresoc.v:146826$7175_Y + connect \Y $and$libresoc.v:146825$7175_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146832$7181 + cell $and $and$libresoc.v:146831$7181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306309,10 +303119,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$57 connect \B \x_valid_i - connect \Y $and$libresoc.v:146832$7181_Y + connect \Y $and$libresoc.v:146831$7181_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146834$7183 + cell $and $and$libresoc.v:146833$7183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306320,10 +303130,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 - connect \Y $and$libresoc.v:146834$7183_Y + connect \Y $and$libresoc.v:146833$7183_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146836$7185 + cell $and $and$libresoc.v:146835$7185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306331,10 +303141,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$65 connect \B \x_valid_i - connect \Y $and$libresoc.v:146836$7185_Y + connect \Y $and$libresoc.v:146835$7185_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146838$7187 + cell $and $and$libresoc.v:146837$7187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306342,10 +303152,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$67 connect \B \$69 - connect \Y $and$libresoc.v:146838$7187_Y + connect \Y $and$libresoc.v:146837$7187_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146840$7189 + cell $and $and$libresoc.v:146839$7189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306353,10 +303163,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$73 connect \B \x_valid_i - connect \Y $and$libresoc.v:146840$7189_Y + connect \Y $and$libresoc.v:146839$7189_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146842$7191 + cell $and $and$libresoc.v:146841$7191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306364,10 +303174,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:146842$7191_Y + connect \Y $and$libresoc.v:146841$7191_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146843$7192 + cell $and $and$libresoc.v:146842$7192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306375,10 +303185,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$75 connect \B \$77 - connect \Y $and$libresoc.v:146843$7192_Y + connect \Y $and$libresoc.v:146842$7192_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:146844$7193 + cell $and $and$libresoc.v:146843$7193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306386,10 +303196,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:146844$7193_Y + connect \Y $and$libresoc.v:146843$7193_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:146847$7196 + cell $and $and$libresoc.v:146846$7196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306397,10 +303207,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:146847$7196_Y + connect \Y $and$libresoc.v:146846$7196_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:146849$7198 + cell $and $and$libresoc.v:146848$7198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306408,130 +303218,130 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:146849$7198_Y + connect \Y $and$libresoc.v:146848$7198_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:146805$7154 + cell $not $not$libresoc.v:146804$7154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:146805$7154_Y + connect \Y $not$libresoc.v:146804$7154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146810$7159 + cell $not $not$libresoc.v:146809$7159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146810$7159_Y + connect \Y $not$libresoc.v:146809$7159_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:146813$7162 + cell $not $not$libresoc.v:146812$7162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:146813$7162_Y + connect \Y $not$libresoc.v:146812$7162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146817$7166 + cell $not $not$libresoc.v:146816$7166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146817$7166_Y + connect \Y $not$libresoc.v:146816$7166_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:146821$7170 + cell $not $not$libresoc.v:146820$7170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:146821$7170_Y + connect \Y $not$libresoc.v:146820$7170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146825$7174 + cell $not $not$libresoc.v:146824$7174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146825$7174_Y + connect \Y $not$libresoc.v:146824$7174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:146828$7177 + cell $not $not$libresoc.v:146827$7177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:146828$7177_Y + connect \Y $not$libresoc.v:146827$7177_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146831$7180 + cell $not $not$libresoc.v:146830$7180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146831$7180_Y + connect \Y $not$libresoc.v:146830$7180_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146833$7182 + cell $not $not$libresoc.v:146832$7182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146833$7182_Y + connect \Y $not$libresoc.v:146832$7182_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146837$7186 + cell $not $not$libresoc.v:146836$7186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146837$7186_Y + connect \Y $not$libresoc.v:146836$7186_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146841$7190 + cell $not $not$libresoc.v:146840$7190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146841$7190_Y + connect \Y $not$libresoc.v:146840$7190_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:146845$7194 + cell $not $not$libresoc.v:146844$7194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:146845$7194_Y + connect \Y $not$libresoc.v:146844$7194_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" - cell $not $not$libresoc.v:146846$7195 + cell $not $not$libresoc.v:146845$7195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbus__we - connect \Y $not$libresoc.v:146846$7195_Y + connect \Y $not$libresoc.v:146845$7195_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:146848$7197 + cell $not $not$libresoc.v:146847$7197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:146848$7197_Y + connect \Y $not$libresoc.v:146847$7197_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:146850$7199 + cell $not $not$libresoc.v:146849$7199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:146850$7199_Y + connect \Y $not$libresoc.v:146849$7199_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146804$7153 + cell $or $or$libresoc.v:146803$7153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306539,10 +303349,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:146804$7153_Y + connect \Y $or$libresoc.v:146803$7153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146806$7155 + cell $or $or$libresoc.v:146805$7155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306550,10 +303360,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:146806$7155_Y + connect \Y $or$libresoc.v:146805$7155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146807$7156 + cell $or $or$libresoc.v:146806$7156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306561,10 +303371,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146807$7156_Y + connect \Y $or$libresoc.v:146806$7156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146809$7158 + cell $or $or$libresoc.v:146808$7158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306572,10 +303382,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146809$7158_Y + connect \Y $or$libresoc.v:146808$7158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146812$7161 + cell $or $or$libresoc.v:146811$7161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306583,10 +303393,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:146812$7161_Y + connect \Y $or$libresoc.v:146811$7161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146814$7163 + cell $or $or$libresoc.v:146813$7163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306594,10 +303404,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $or$libresoc.v:146814$7163_Y + connect \Y $or$libresoc.v:146813$7163_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146815$7164 + cell $or $or$libresoc.v:146814$7164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306605,10 +303415,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146815$7164_Y + connect \Y $or$libresoc.v:146814$7164_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146819$7168 + cell $or $or$libresoc.v:146818$7168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306616,10 +303426,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:146819$7168_Y + connect \Y $or$libresoc.v:146818$7168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146822$7171 + cell $or $or$libresoc.v:146821$7171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306627,10 +303437,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:146822$7171_Y + connect \Y $or$libresoc.v:146821$7171_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146823$7172 + cell $or $or$libresoc.v:146822$7172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306638,10 +303448,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146823$7172_Y + connect \Y $or$libresoc.v:146822$7172_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146827$7176 + cell $or $or$libresoc.v:146826$7176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306649,10 +303459,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:146827$7176_Y + connect \Y $or$libresoc.v:146826$7176_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146829$7178 + cell $or $or$libresoc.v:146828$7178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306660,10 +303470,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$51 connect \B \$53 - connect \Y $or$libresoc.v:146829$7178_Y + connect \Y $or$libresoc.v:146828$7178_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146830$7179 + cell $or $or$libresoc.v:146829$7179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306671,10 +303481,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146830$7179_Y + connect \Y $or$libresoc.v:146829$7179_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146835$7184 + cell $or $or$libresoc.v:146834$7184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306682,10 +303492,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146835$7184_Y + connect \Y $or$libresoc.v:146834$7184_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146839$7188 + cell $or $or$libresoc.v:146838$7188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306693,10 +303503,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146839$7188_Y + connect \Y $or$libresoc.v:146838$7188_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" - cell $or $or$libresoc.v:146851$7200 + cell $or $or$libresoc.v:146850$7200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -306704,175 +303514,175 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \m_load_err_o connect \B \m_store_err_o - connect \Y $or$libresoc.v:146851$7200_Y + connect \Y $or$libresoc.v:146850$7200_Y end - attribute \src "libresoc.v:146625.7-146625.20" - process $proc$libresoc.v:146625$7267 + attribute \src "libresoc.v:146624.7-146624.20" + process $proc$libresoc.v:146624$7267 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146730.14-146730.42" - process $proc$libresoc.v:146730$7268 + attribute \src "libresoc.v:146729.14-146729.42" + process $proc$libresoc.v:146729$7268 assign { } { } assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \dbus__adr $1\dbus__adr[44:0] end - attribute \src "libresoc.v:146735.7-146735.23" - process $proc$libresoc.v:146735$7269 + attribute \src "libresoc.v:146734.7-146734.23" + process $proc$libresoc.v:146734$7269 assign { } { } assign $1\dbus__cyc[0:0] 1'0 sync always sync init update \dbus__cyc $1\dbus__cyc[0:0] end - attribute \src "libresoc.v:146742.14-146742.48" - process $proc$libresoc.v:146742$7270 + attribute \src "libresoc.v:146741.14-146741.48" + process $proc$libresoc.v:146741$7270 assign { } { } assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbus__dat_w $1\dbus__dat_w[63:0] end - attribute \src "libresoc.v:146749.13-146749.30" - process $proc$libresoc.v:146749$7271 + attribute \src "libresoc.v:146748.13-146748.30" + process $proc$libresoc.v:146748$7271 assign { } { } assign $1\dbus__sel[7:0] 8'00000000 sync always sync init update \dbus__sel $1\dbus__sel[7:0] end - attribute \src "libresoc.v:146754.7-146754.23" - process $proc$libresoc.v:146754$7272 + attribute \src "libresoc.v:146753.7-146753.23" + process $proc$libresoc.v:146753$7272 assign { } { } assign $1\dbus__stb[0:0] 1'0 sync always sync init update \dbus__stb $1\dbus__stb[0:0] end - attribute \src "libresoc.v:146759.7-146759.22" - process $proc$libresoc.v:146759$7273 + attribute \src "libresoc.v:146758.7-146758.22" + process $proc$libresoc.v:146758$7273 assign { } { } assign $1\dbus__we[0:0] 1'0 sync always sync init update \dbus__we $1\dbus__we[0:0] end - attribute \src "libresoc.v:146763.14-146763.44" - process $proc$libresoc.v:146763$7274 + attribute \src "libresoc.v:146762.14-146762.44" + process $proc$libresoc.v:146762$7274 assign { } { } assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \m_badaddr_o $1\m_badaddr_o[44:0] end - attribute \src "libresoc.v:146770.14-146770.48" - process $proc$libresoc.v:146770$7275 + attribute \src "libresoc.v:146769.14-146769.48" + process $proc$libresoc.v:146769$7275 assign { } { } assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \m_ld_data_o $1\m_ld_data_o[63:0] end - attribute \src "libresoc.v:146774.7-146774.26" - process $proc$libresoc.v:146774$7276 + attribute \src "libresoc.v:146773.7-146773.26" + process $proc$libresoc.v:146773$7276 assign { } { } assign $1\m_load_err_o[0:0] 1'0 sync always sync init update \m_load_err_o $1\m_load_err_o[0:0] end - attribute \src "libresoc.v:146780.7-146780.27" - process $proc$libresoc.v:146780$7277 + attribute \src "libresoc.v:146779.7-146779.27" + process $proc$libresoc.v:146779$7277 assign { } { } assign $1\m_store_err_o[0:0] 1'0 sync always sync init update \m_store_err_o $1\m_store_err_o[0:0] end - attribute \src "libresoc.v:146852.3-146853.39" - process $proc$libresoc.v:146852$7201 + attribute \src "libresoc.v:146851.3-146852.39" + process $proc$libresoc.v:146851$7201 assign { } { } assign $0\m_badaddr_o[44:0] \m_badaddr_o$next sync posedge \coresync_clk update \m_badaddr_o $0\m_badaddr_o[44:0] end - attribute \src "libresoc.v:146854.3-146855.43" - process $proc$libresoc.v:146854$7202 + attribute \src "libresoc.v:146853.3-146854.43" + process $proc$libresoc.v:146853$7202 assign { } { } assign $0\m_store_err_o[0:0] \m_store_err_o$next sync posedge \coresync_clk update \m_store_err_o $0\m_store_err_o[0:0] end - attribute \src "libresoc.v:146856.3-146857.41" - process $proc$libresoc.v:146856$7203 + attribute \src "libresoc.v:146855.3-146856.41" + process $proc$libresoc.v:146855$7203 assign { } { } assign $0\m_load_err_o[0:0] \m_load_err_o$next sync posedge \coresync_clk update \m_load_err_o $0\m_load_err_o[0:0] end - attribute \src "libresoc.v:146858.3-146859.39" - process $proc$libresoc.v:146858$7204 + attribute \src "libresoc.v:146857.3-146858.39" + process $proc$libresoc.v:146857$7204 assign { } { } assign $0\dbus__dat_w[63:0] \dbus__dat_w$next sync posedge \coresync_clk update \dbus__dat_w $0\dbus__dat_w[63:0] end - attribute \src "libresoc.v:146860.3-146861.33" - process $proc$libresoc.v:146860$7205 + attribute \src "libresoc.v:146859.3-146860.33" + process $proc$libresoc.v:146859$7205 assign { } { } assign $0\dbus__we[0:0] \dbus__we$next sync posedge \coresync_clk update \dbus__we $0\dbus__we[0:0] end - attribute \src "libresoc.v:146862.3-146863.35" - process $proc$libresoc.v:146862$7206 + attribute \src "libresoc.v:146861.3-146862.35" + process $proc$libresoc.v:146861$7206 assign { } { } assign $0\dbus__adr[44:0] \dbus__adr$next sync posedge \coresync_clk update \dbus__adr $0\dbus__adr[44:0] end - attribute \src "libresoc.v:146864.3-146865.39" - process $proc$libresoc.v:146864$7207 + attribute \src "libresoc.v:146863.3-146864.39" + process $proc$libresoc.v:146863$7207 assign { } { } assign $0\m_ld_data_o[63:0] \m_ld_data_o$next sync posedge \coresync_clk update \m_ld_data_o $0\m_ld_data_o[63:0] end - attribute \src "libresoc.v:146866.3-146867.35" - process $proc$libresoc.v:146866$7208 + attribute \src "libresoc.v:146865.3-146866.35" + process $proc$libresoc.v:146865$7208 assign { } { } assign $0\dbus__sel[7:0] \dbus__sel$next sync posedge \coresync_clk update \dbus__sel $0\dbus__sel[7:0] end - attribute \src "libresoc.v:146868.3-146869.35" - process $proc$libresoc.v:146868$7209 + attribute \src "libresoc.v:146867.3-146868.35" + process $proc$libresoc.v:146867$7209 assign { } { } assign $0\dbus__stb[0:0] \dbus__stb$next sync posedge \coresync_clk update \dbus__stb $0\dbus__stb[0:0] end - attribute \src "libresoc.v:146870.3-146871.35" - process $proc$libresoc.v:146870$7210 + attribute \src "libresoc.v:146869.3-146870.35" + process $proc$libresoc.v:146869$7210 assign { } { } assign $0\dbus__cyc[0:0] \dbus__cyc$next sync posedge \coresync_clk update \dbus__cyc $0\dbus__cyc[0:0] end - attribute \src "libresoc.v:146872.3-146899.6" - process $proc$libresoc.v:146872$7211 + attribute \src "libresoc.v:146871.3-146898.6" + process $proc$libresoc.v:146871$7211 assign { } { } assign { } { } assign { } { } assign $0\dbus__cyc$next[0:0]$7212 $4\dbus__cyc$next[0:0]$7216 - attribute \src "libresoc.v:146873.5-146873.29" + attribute \src "libresoc.v:146872.5-146872.29" switch \initial - attribute \src "libresoc.v:146873.9-146873.17" + attribute \src "libresoc.v:146872.9-146872.17" case 1'1 case end @@ -306919,15 +303729,15 @@ module \lsmem sync always update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7212 end - attribute \src "libresoc.v:146900.3-146927.6" - process $proc$libresoc.v:146900$7217 + attribute \src "libresoc.v:146899.3-146926.6" + process $proc$libresoc.v:146899$7217 assign { } { } assign { } { } assign { } { } assign $0\dbus__stb$next[0:0]$7218 $4\dbus__stb$next[0:0]$7222 - attribute \src "libresoc.v:146901.5-146901.29" + attribute \src "libresoc.v:146900.5-146900.29" switch \initial - attribute \src "libresoc.v:146901.9-146901.17" + attribute \src "libresoc.v:146900.9-146900.17" case 1'1 case end @@ -306974,14 +303784,14 @@ module \lsmem sync always update \dbus__stb$next $0\dbus__stb$next[0:0]$7218 end - attribute \src "libresoc.v:146928.3-146937.6" - process $proc$libresoc.v:146928$7223 + attribute \src "libresoc.v:146927.3-146936.6" + process $proc$libresoc.v:146927$7223 assign { } { } assign { } { } assign $0\x_busy_o[0:0] $1\x_busy_o[0:0] - attribute \src "libresoc.v:146929.5-146929.29" + attribute \src "libresoc.v:146928.5-146928.29" switch \initial - attribute \src "libresoc.v:146929.9-146929.17" + attribute \src "libresoc.v:146928.9-146928.17" case 1'1 case end @@ -306997,14 +303807,14 @@ module \lsmem sync always update \x_busy_o $0\x_busy_o[0:0] end - attribute \src "libresoc.v:146938.3-146955.6" - process $proc$libresoc.v:146938$7224 + attribute \src "libresoc.v:146937.3-146954.6" + process $proc$libresoc.v:146937$7224 assign { } { } assign { } { } assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] - attribute \src "libresoc.v:146939.5-146939.29" + attribute \src "libresoc.v:146938.5-146938.29" switch \initial - attribute \src "libresoc.v:146939.9-146939.17" + attribute \src "libresoc.v:146938.9-146938.17" case 1'1 case end @@ -307031,15 +303841,15 @@ module \lsmem sync always update \m_busy_o $0\m_busy_o[0:0] end - attribute \src "libresoc.v:146956.3-146986.6" - process $proc$libresoc.v:146956$7225 + attribute \src "libresoc.v:146955.3-146985.6" + process $proc$libresoc.v:146955$7225 assign { } { } assign { } { } assign { } { } assign $0\dbus__sel$next[7:0]$7226 $4\dbus__sel$next[7:0]$7230 - attribute \src "libresoc.v:146957.5-146957.29" + attribute \src "libresoc.v:146956.5-146956.29" switch \initial - attribute \src "libresoc.v:146957.9-146957.17" + attribute \src "libresoc.v:146956.9-146956.17" case 1'1 case end @@ -307088,15 +303898,15 @@ module \lsmem sync always update \dbus__sel$next $0\dbus__sel$next[7:0]$7226 end - attribute \src "libresoc.v:146987.3-147011.6" - process $proc$libresoc.v:146987$7231 + attribute \src "libresoc.v:146986.3-147010.6" + process $proc$libresoc.v:146986$7231 assign { } { } assign { } { } assign { } { } assign $0\m_ld_data_o$next[63:0]$7232 $4\m_ld_data_o$next[63:0]$7236 - attribute \src "libresoc.v:146988.5-146988.29" + attribute \src "libresoc.v:146987.5-146987.29" switch \initial - attribute \src "libresoc.v:146988.9-146988.17" + attribute \src "libresoc.v:146987.9-146987.17" case 1'1 case end @@ -307139,15 +303949,15 @@ module \lsmem sync always update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7232 end - attribute \src "libresoc.v:147012.3-147037.6" - process $proc$libresoc.v:147012$7237 + attribute \src "libresoc.v:147011.3-147036.6" + process $proc$libresoc.v:147011$7237 assign { } { } assign { } { } assign { } { } assign $0\dbus__adr$next[44:0]$7238 $3\dbus__adr$next[44:0]$7241 - attribute \src "libresoc.v:147013.5-147013.29" + attribute \src "libresoc.v:147012.5-147012.29" switch \initial - attribute \src "libresoc.v:147013.9-147013.17" + attribute \src "libresoc.v:147012.9-147012.17" case 1'1 case end @@ -307186,15 +303996,15 @@ module \lsmem sync always update \dbus__adr$next $0\dbus__adr$next[44:0]$7238 end - attribute \src "libresoc.v:147038.3-147063.6" - process $proc$libresoc.v:147038$7242 + attribute \src "libresoc.v:147037.3-147062.6" + process $proc$libresoc.v:147037$7242 assign { } { } assign { } { } assign { } { } assign $0\dbus__we$next[0:0]$7243 $3\dbus__we$next[0:0]$7246 - attribute \src "libresoc.v:147039.5-147039.29" + attribute \src "libresoc.v:147038.5-147038.29" switch \initial - attribute \src "libresoc.v:147039.9-147039.17" + attribute \src "libresoc.v:147038.9-147038.17" case 1'1 case end @@ -307233,15 +304043,15 @@ module \lsmem sync always update \dbus__we$next $0\dbus__we$next[0:0]$7243 end - attribute \src "libresoc.v:147064.3-147089.6" - process $proc$libresoc.v:147064$7247 + attribute \src "libresoc.v:147063.3-147088.6" + process $proc$libresoc.v:147063$7247 assign { } { } assign { } { } assign { } { } assign $0\dbus__dat_w$next[63:0]$7248 $3\dbus__dat_w$next[63:0]$7251 - attribute \src "libresoc.v:147065.5-147065.29" + attribute \src "libresoc.v:147064.5-147064.29" switch \initial - attribute \src "libresoc.v:147065.9-147065.17" + attribute \src "libresoc.v:147064.9-147064.17" case 1'1 case end @@ -307280,15 +304090,15 @@ module \lsmem sync always update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7248 end - attribute \src "libresoc.v:147090.3-147112.6" - process $proc$libresoc.v:147090$7252 + attribute \src "libresoc.v:147089.3-147111.6" + process $proc$libresoc.v:147089$7252 assign { } { } assign { } { } assign { } { } assign $0\m_load_err_o$next[0:0]$7253 $3\m_load_err_o$next[0:0]$7256 - attribute \src "libresoc.v:147091.5-147091.29" + attribute \src "libresoc.v:147090.5-147090.29" switch \initial - attribute \src "libresoc.v:147091.9-147091.17" + attribute \src "libresoc.v:147090.9-147090.17" case 1'1 case end @@ -307326,15 +304136,15 @@ module \lsmem sync always update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7253 end - attribute \src "libresoc.v:147113.3-147135.6" - process $proc$libresoc.v:147113$7257 + attribute \src "libresoc.v:147112.3-147134.6" + process $proc$libresoc.v:147112$7257 assign { } { } assign { } { } assign { } { } assign $0\m_store_err_o$next[0:0]$7258 $3\m_store_err_o$next[0:0]$7261 - attribute \src "libresoc.v:147114.5-147114.29" + attribute \src "libresoc.v:147113.5-147113.29" switch \initial - attribute \src "libresoc.v:147114.9-147114.17" + attribute \src "libresoc.v:147113.9-147113.17" case 1'1 case end @@ -307372,15 +304182,15 @@ module \lsmem sync always update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7258 end - attribute \src "libresoc.v:147136.3-147155.6" - process $proc$libresoc.v:147136$7262 + attribute \src "libresoc.v:147135.3-147154.6" + process $proc$libresoc.v:147135$7262 assign { } { } assign { } { } assign { } { } assign $0\m_badaddr_o$next[44:0]$7263 $3\m_badaddr_o$next[44:0]$7266 - attribute \src "libresoc.v:147137.5-147137.29" + attribute \src "libresoc.v:147136.5-147136.29" switch \initial - attribute \src "libresoc.v:147137.9-147137.17" + attribute \src "libresoc.v:147136.9-147136.17" case 1'1 case end @@ -307414,318 +304224,318 @@ module \lsmem sync always update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7263 end - connect \$9 $or$libresoc.v:146804$7153_Y - connect \$11 $not$libresoc.v:146805$7154_Y - connect \$13 $or$libresoc.v:146806$7155_Y - connect \$15 $or$libresoc.v:146807$7156_Y - connect \$17 $and$libresoc.v:146808$7157_Y - connect \$1 $or$libresoc.v:146809$7158_Y - connect \$19 $not$libresoc.v:146810$7159_Y - connect \$21 $and$libresoc.v:146811$7160_Y - connect \$23 $or$libresoc.v:146812$7161_Y - connect \$25 $not$libresoc.v:146813$7162_Y - connect \$27 $or$libresoc.v:146814$7163_Y - connect \$29 $or$libresoc.v:146815$7164_Y - connect \$31 $and$libresoc.v:146816$7165_Y - connect \$33 $not$libresoc.v:146817$7166_Y - connect \$35 $and$libresoc.v:146818$7167_Y - connect \$37 $or$libresoc.v:146819$7168_Y - connect \$3 $and$libresoc.v:146820$7169_Y - connect \$39 $not$libresoc.v:146821$7170_Y - connect \$41 $or$libresoc.v:146822$7171_Y - connect \$43 $or$libresoc.v:146823$7172_Y - connect \$45 $and$libresoc.v:146824$7173_Y - connect \$47 $not$libresoc.v:146825$7174_Y - connect \$49 $and$libresoc.v:146826$7175_Y - connect \$51 $or$libresoc.v:146827$7176_Y - connect \$53 $not$libresoc.v:146828$7177_Y - connect \$55 $or$libresoc.v:146829$7178_Y - connect \$57 $or$libresoc.v:146830$7179_Y - connect \$5 $not$libresoc.v:146831$7180_Y - connect \$59 $and$libresoc.v:146832$7181_Y - connect \$61 $not$libresoc.v:146833$7182_Y - connect \$63 $and$libresoc.v:146834$7183_Y - connect \$65 $or$libresoc.v:146835$7184_Y - connect \$67 $and$libresoc.v:146836$7185_Y - connect \$69 $not$libresoc.v:146837$7186_Y - connect \$71 $and$libresoc.v:146838$7187_Y - connect \$73 $or$libresoc.v:146839$7188_Y - connect \$75 $and$libresoc.v:146840$7189_Y - connect \$77 $not$libresoc.v:146841$7190_Y - connect \$7 $and$libresoc.v:146842$7191_Y - connect \$79 $and$libresoc.v:146843$7192_Y - connect \$81 $and$libresoc.v:146844$7193_Y - connect \$83 $not$libresoc.v:146845$7194_Y - connect \$85 $not$libresoc.v:146846$7195_Y - connect \$87 $and$libresoc.v:146847$7196_Y - connect \$89 $not$libresoc.v:146848$7197_Y - connect \$91 $and$libresoc.v:146849$7198_Y - connect \$93 $not$libresoc.v:146850$7199_Y - connect \$95 $or$libresoc.v:146851$7200_Y + connect \$9 $or$libresoc.v:146803$7153_Y + connect \$11 $not$libresoc.v:146804$7154_Y + connect \$13 $or$libresoc.v:146805$7155_Y + connect \$15 $or$libresoc.v:146806$7156_Y + connect \$17 $and$libresoc.v:146807$7157_Y + connect \$1 $or$libresoc.v:146808$7158_Y + connect \$19 $not$libresoc.v:146809$7159_Y + connect \$21 $and$libresoc.v:146810$7160_Y + connect \$23 $or$libresoc.v:146811$7161_Y + connect \$25 $not$libresoc.v:146812$7162_Y + connect \$27 $or$libresoc.v:146813$7163_Y + connect \$29 $or$libresoc.v:146814$7164_Y + connect \$31 $and$libresoc.v:146815$7165_Y + connect \$33 $not$libresoc.v:146816$7166_Y + connect \$35 $and$libresoc.v:146817$7167_Y + connect \$37 $or$libresoc.v:146818$7168_Y + connect \$3 $and$libresoc.v:146819$7169_Y + connect \$39 $not$libresoc.v:146820$7170_Y + connect \$41 $or$libresoc.v:146821$7171_Y + connect \$43 $or$libresoc.v:146822$7172_Y + connect \$45 $and$libresoc.v:146823$7173_Y + connect \$47 $not$libresoc.v:146824$7174_Y + connect \$49 $and$libresoc.v:146825$7175_Y + connect \$51 $or$libresoc.v:146826$7176_Y + connect \$53 $not$libresoc.v:146827$7177_Y + connect \$55 $or$libresoc.v:146828$7178_Y + connect \$57 $or$libresoc.v:146829$7179_Y + connect \$5 $not$libresoc.v:146830$7180_Y + connect \$59 $and$libresoc.v:146831$7181_Y + connect \$61 $not$libresoc.v:146832$7182_Y + connect \$63 $and$libresoc.v:146833$7183_Y + connect \$65 $or$libresoc.v:146834$7184_Y + connect \$67 $and$libresoc.v:146835$7185_Y + connect \$69 $not$libresoc.v:146836$7186_Y + connect \$71 $and$libresoc.v:146837$7187_Y + connect \$73 $or$libresoc.v:146838$7188_Y + connect \$75 $and$libresoc.v:146839$7189_Y + connect \$77 $not$libresoc.v:146840$7190_Y + connect \$7 $and$libresoc.v:146841$7191_Y + connect \$79 $and$libresoc.v:146842$7192_Y + connect \$81 $and$libresoc.v:146843$7193_Y + connect \$83 $not$libresoc.v:146844$7194_Y + connect \$85 $not$libresoc.v:146845$7195_Y + connect \$87 $and$libresoc.v:146846$7196_Y + connect \$89 $not$libresoc.v:146847$7197_Y + connect \$91 $and$libresoc.v:146848$7198_Y + connect \$93 $not$libresoc.v:146849$7199_Y + connect \$95 $or$libresoc.v:146850$7200_Y connect \x_stall_i 1'0 connect \m_stall_i 1'0 end -attribute \src "libresoc.v:147162.1-148123.10" +attribute \src "libresoc.v:147161.1-148122.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" attribute \generator "nMigen" module \main - attribute \src "libresoc.v:147695.3-147717.6" + attribute \src "libresoc.v:147694.3-147716.6" wire width 64 $0\a_i[63:0] - attribute \src "libresoc.v:147794.3-147820.6" + attribute \src "libresoc.v:147793.3-147819.6" wire $0\a_lt[0:0] - attribute \src "libresoc.v:148075.3-148085.6" + attribute \src "libresoc.v:148074.3-148084.6" wire width 64 $0\a_n[63:0] - attribute \src "libresoc.v:148045.3-148054.6" + attribute \src "libresoc.v:148044.3-148053.6" wire width 66 $0\add_a[65:0] - attribute \src "libresoc.v:148055.3-148064.6" + attribute \src "libresoc.v:148054.3-148063.6" wire width 66 $0\add_b[65:0] - attribute \src "libresoc.v:148065.3-148074.6" + attribute \src "libresoc.v:148064.3-148073.6" wire width 66 $0\add_o[65:0] - attribute \src "libresoc.v:147933.3-147955.6" + attribute \src "libresoc.v:147932.3-147954.6" wire width 64 $0\b_i[63:0] - attribute \src "libresoc.v:147919.3-147932.6" + attribute \src "libresoc.v:147918.3-147931.6" wire width 2 $0\ca[1:0] - attribute \src "libresoc.v:148086.3-148096.6" + attribute \src "libresoc.v:148085.3-148095.6" wire $0\carry_32[0:0] - attribute \src "libresoc.v:148097.3-148107.6" + attribute \src "libresoc.v:148096.3-148106.6" wire $0\carry_64[0:0] - attribute \src "libresoc.v:147821.3-147846.6" + attribute \src "libresoc.v:147820.3-147845.6" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:147847.3-147861.6" + attribute \src "libresoc.v:147846.3-147860.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:148025.3-148044.6" + attribute \src "libresoc.v:148024.3-148043.6" wire width 8 $0\eqs[7:0] - attribute \src "libresoc.v:147163.7-147163.20" + attribute \src "libresoc.v:147162.7-147162.20" wire $0\initial[0:0] - attribute \src "libresoc.v:147685.3-147694.6" + attribute \src "libresoc.v:147684.3-147693.6" wire $0\is_32bit[0:0] - attribute \src "libresoc.v:147756.3-147774.6" + attribute \src "libresoc.v:147755.3-147773.6" wire $0\msb_a[0:0] - attribute \src "libresoc.v:147775.3-147793.6" + attribute \src "libresoc.v:147774.3-147792.6" wire $0\msb_b[0:0] - attribute \src "libresoc.v:147862.3-147899.6" + attribute \src "libresoc.v:147861.3-147898.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:147900.3-147918.6" + attribute \src "libresoc.v:147899.3-147917.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:147978.3-147991.6" + attribute \src "libresoc.v:147977.3-147990.6" wire width 2 $0\ov[1:0] - attribute \src "libresoc.v:148014.3-148024.6" + attribute \src "libresoc.v:148013.3-148023.6" wire width 8 $0\src1[7:0] - attribute \src "libresoc.v:147729.3-147755.6" + attribute \src "libresoc.v:147728.3-147754.6" wire width 5 $0\tval[4:0] - attribute \src "libresoc.v:147956.3-147966.6" + attribute \src "libresoc.v:147955.3-147965.6" wire width 2 $0\xer_ca$20[1:0]$7353 - attribute \src "libresoc.v:147967.3-147977.6" + attribute \src "libresoc.v:147966.3-147976.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:147992.3-148002.6" + attribute \src "libresoc.v:147991.3-148001.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:148003.3-148013.6" + attribute \src "libresoc.v:148002.3-148012.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:147718.3-147728.6" + attribute \src "libresoc.v:147717.3-147727.6" wire $0\zerohi[0:0] - attribute \src "libresoc.v:148108.3-148118.6" + attribute \src "libresoc.v:148107.3-148117.6" wire $0\zerolo[0:0] - attribute \src "libresoc.v:147695.3-147717.6" + attribute \src "libresoc.v:147694.3-147716.6" wire width 64 $1\a_i[63:0] - attribute \src "libresoc.v:147794.3-147820.6" + attribute \src "libresoc.v:147793.3-147819.6" wire $1\a_lt[0:0] - attribute \src "libresoc.v:148075.3-148085.6" + attribute \src "libresoc.v:148074.3-148084.6" wire width 64 $1\a_n[63:0] - attribute \src "libresoc.v:148045.3-148054.6" + attribute \src "libresoc.v:148044.3-148053.6" wire width 66 $1\add_a[65:0] - attribute \src "libresoc.v:148055.3-148064.6" + attribute \src "libresoc.v:148054.3-148063.6" wire width 66 $1\add_b[65:0] - attribute \src "libresoc.v:148065.3-148074.6" + attribute \src "libresoc.v:148064.3-148073.6" wire width 66 $1\add_o[65:0] - attribute \src "libresoc.v:147933.3-147955.6" + attribute \src "libresoc.v:147932.3-147954.6" wire width 64 $1\b_i[63:0] - attribute \src "libresoc.v:147919.3-147932.6" + attribute \src "libresoc.v:147918.3-147931.6" wire width 2 $1\ca[1:0] - attribute \src "libresoc.v:148086.3-148096.6" + attribute \src "libresoc.v:148085.3-148095.6" wire $1\carry_32[0:0] - attribute \src "libresoc.v:148097.3-148107.6" + attribute \src "libresoc.v:148096.3-148106.6" wire $1\carry_64[0:0] - attribute \src "libresoc.v:147821.3-147846.6" + attribute \src "libresoc.v:147820.3-147845.6" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:147847.3-147861.6" + attribute \src "libresoc.v:147846.3-147860.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:148025.3-148044.6" + attribute \src "libresoc.v:148024.3-148043.6" wire width 8 $1\eqs[7:0] - attribute \src "libresoc.v:147685.3-147694.6" + attribute \src "libresoc.v:147684.3-147693.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:147756.3-147774.6" + attribute \src "libresoc.v:147755.3-147773.6" wire $1\msb_a[0:0] - attribute \src "libresoc.v:147775.3-147793.6" + attribute \src "libresoc.v:147774.3-147792.6" wire $1\msb_b[0:0] - attribute \src "libresoc.v:147862.3-147899.6" + attribute \src "libresoc.v:147861.3-147898.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:147900.3-147918.6" + attribute \src "libresoc.v:147899.3-147917.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:147978.3-147991.6" + attribute \src "libresoc.v:147977.3-147990.6" wire width 2 $1\ov[1:0] - attribute \src "libresoc.v:148014.3-148024.6" + attribute \src "libresoc.v:148013.3-148023.6" wire width 8 $1\src1[7:0] - attribute \src "libresoc.v:147729.3-147755.6" + attribute \src "libresoc.v:147728.3-147754.6" wire width 5 $1\tval[4:0] - attribute \src "libresoc.v:147956.3-147966.6" + attribute \src "libresoc.v:147955.3-147965.6" wire width 2 $1\xer_ca$20[1:0]$7354 - attribute \src "libresoc.v:147967.3-147977.6" + attribute \src "libresoc.v:147966.3-147976.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:147992.3-148002.6" + attribute \src "libresoc.v:147991.3-148001.6" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:148003.3-148013.6" + attribute \src "libresoc.v:148002.3-148012.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:147718.3-147728.6" + attribute \src "libresoc.v:147717.3-147727.6" wire $1\zerohi[0:0] - attribute \src "libresoc.v:148108.3-148118.6" + attribute \src "libresoc.v:148107.3-148117.6" wire $1\zerolo[0:0] - attribute \src "libresoc.v:147695.3-147717.6" + attribute \src "libresoc.v:147694.3-147716.6" wire width 64 $2\a_i[63:0] - attribute \src "libresoc.v:147794.3-147820.6" + attribute \src "libresoc.v:147793.3-147819.6" wire $2\a_lt[0:0] - attribute \src "libresoc.v:147933.3-147955.6" + attribute \src "libresoc.v:147932.3-147954.6" wire width 64 $2\b_i[63:0] - attribute \src "libresoc.v:147821.3-147846.6" + attribute \src "libresoc.v:147820.3-147845.6" wire width 2 $2\cr_a[3:2] - attribute \src "libresoc.v:147756.3-147774.6" + attribute \src "libresoc.v:147755.3-147773.6" wire $2\msb_a[0:0] - attribute \src "libresoc.v:147775.3-147793.6" + attribute \src "libresoc.v:147774.3-147792.6" wire $2\msb_b[0:0] - attribute \src "libresoc.v:147862.3-147899.6" + attribute \src "libresoc.v:147861.3-147898.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:147729.3-147755.6" + attribute \src "libresoc.v:147728.3-147754.6" wire width 5 $2\tval[4:0] - attribute \src "libresoc.v:147794.3-147820.6" + attribute \src "libresoc.v:147793.3-147819.6" wire $3\a_lt[0:0] - attribute \src "libresoc.v:147862.3-147899.6" + attribute \src "libresoc.v:147861.3-147898.6" wire width 64 $3\o[63:0] - attribute \src "libresoc.v:147729.3-147755.6" + attribute \src "libresoc.v:147728.3-147754.6" wire width 5 $3\tval[4:0] - attribute \src "libresoc.v:147862.3-147899.6" + attribute \src "libresoc.v:147861.3-147898.6" wire width 64 $4\o[63:0] - attribute \src "libresoc.v:147660.18-147660.105" - wire width 67 $add$libresoc.v:147660$7314_Y - attribute \src "libresoc.v:147634.19-147634.107" - wire $and$libresoc.v:147634$7288_Y - attribute \src "libresoc.v:147638.19-147638.107" - wire $and$libresoc.v:147638$7292_Y - attribute \src "libresoc.v:147671.18-147671.106" - wire $and$libresoc.v:147671$7325_Y - attribute \src "libresoc.v:147676.18-147676.106" - wire $and$libresoc.v:147676$7330_Y - attribute \src "libresoc.v:147679.18-147679.106" - wire $and$libresoc.v:147679$7333_Y - attribute \src "libresoc.v:147682.18-147682.106" - wire $and$libresoc.v:147682$7336_Y + attribute \src "libresoc.v:147659.18-147659.105" + wire width 67 $add$libresoc.v:147659$7314_Y + attribute \src "libresoc.v:147633.19-147633.107" + wire $and$libresoc.v:147633$7288_Y + attribute \src "libresoc.v:147637.19-147637.107" + wire $and$libresoc.v:147637$7292_Y + attribute \src "libresoc.v:147670.18-147670.106" + wire $and$libresoc.v:147670$7325_Y + attribute \src "libresoc.v:147675.18-147675.106" + wire $and$libresoc.v:147675$7330_Y + attribute \src "libresoc.v:147678.18-147678.106" + wire $and$libresoc.v:147678$7333_Y + attribute \src "libresoc.v:147681.18-147681.106" + wire $and$libresoc.v:147681$7336_Y + attribute \src "libresoc.v:147624.19-147624.118" + wire $eq$libresoc.v:147624$7279_Y attribute \src "libresoc.v:147625.19-147625.118" - wire $eq$libresoc.v:147625$7279_Y + wire $eq$libresoc.v:147625$7280_Y attribute \src "libresoc.v:147626.19-147626.118" - wire $eq$libresoc.v:147626$7280_Y - attribute \src "libresoc.v:147627.19-147627.118" - wire $eq$libresoc.v:147627$7281_Y - attribute \src "libresoc.v:147639.19-147639.109" - wire $eq$libresoc.v:147639$7293_Y - attribute \src "libresoc.v:147640.19-147640.110" - wire $eq$libresoc.v:147640$7294_Y + wire $eq$libresoc.v:147626$7281_Y + attribute \src "libresoc.v:147638.19-147638.109" + wire $eq$libresoc.v:147638$7293_Y + attribute \src "libresoc.v:147639.19-147639.110" + wire $eq$libresoc.v:147639$7294_Y + attribute \src "libresoc.v:147640.19-147640.111" + wire $eq$libresoc.v:147640$7295_Y attribute \src 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$eq$libresoc.v:147649$7303_Y + wire $eq$libresoc.v:147649$7304_Y attribute \src "libresoc.v:147650.18-147650.118" - wire $eq$libresoc.v:147650$7304_Y + wire $eq$libresoc.v:147650$7305_Y attribute \src "libresoc.v:147651.18-147651.118" - wire $eq$libresoc.v:147651$7305_Y - attribute \src "libresoc.v:147652.18-147652.118" - wire $eq$libresoc.v:147652$7306_Y + wire $eq$libresoc.v:147651$7306_Y + attribute \src "libresoc.v:147653.18-147653.118" + wire $eq$libresoc.v:147653$7308_Y attribute \src "libresoc.v:147654.18-147654.118" - wire $eq$libresoc.v:147654$7308_Y - attribute \src "libresoc.v:147655.18-147655.118" - wire $eq$libresoc.v:147655$7309_Y + wire $eq$libresoc.v:147654$7309_Y + attribute \src "libresoc.v:147656.18-147656.118" + wire $eq$libresoc.v:147656$7311_Y attribute \src "libresoc.v:147657.18-147657.118" - wire $eq$libresoc.v:147657$7311_Y - attribute \src "libresoc.v:147658.18-147658.118" - wire $eq$libresoc.v:147658$7312_Y - attribute \src "libresoc.v:147672.18-147672.107" - wire $ne$libresoc.v:147672$7326_Y - attribute \src "libresoc.v:147683.18-147683.107" - wire $ne$libresoc.v:147683$7337_Y - attribute \src "libresoc.v:147633.19-147633.100" - wire $not$libresoc.v:147633$7287_Y - attribute \src "libresoc.v:147637.19-147637.100" - wire $not$libresoc.v:147637$7291_Y - attribute \src "libresoc.v:147648.18-147648.110" - wire $not$libresoc.v:147648$7302_Y - attribute \src "libresoc.v:147661.18-147661.97" - wire width 64 $not$libresoc.v:147661$7315_Y - attribute \src "libresoc.v:147666.18-147666.99" - wire $not$libresoc.v:147666$7320_Y - attribute \src "libresoc.v:147669.18-147669.99" - wire $not$libresoc.v:147669$7323_Y - attribute \src "libresoc.v:147673.18-147673.99" - wire $not$libresoc.v:147673$7327_Y - attribute \src "libresoc.v:147674.18-147674.99" - wire $not$libresoc.v:147674$7328_Y - attribute \src "libresoc.v:147653.18-147653.104" - wire $or$libresoc.v:147653$7307_Y - attribute \src "libresoc.v:147656.18-147656.104" - wire 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wire $not$libresoc.v:147636$7291_Y + attribute \src "libresoc.v:147647.18-147647.110" + wire $not$libresoc.v:147647$7302_Y + attribute \src "libresoc.v:147660.18-147660.97" + wire width 64 $not$libresoc.v:147660$7315_Y attribute \src "libresoc.v:147665.18-147665.99" - wire $reduce_or$libresoc.v:147665$7319_Y + wire $not$libresoc.v:147665$7320_Y attribute \src "libresoc.v:147668.18-147668.99" - wire $reduce_or$libresoc.v:147668$7322_Y - attribute \src "libresoc.v:147677.18-147677.121" - wire $ternary$libresoc.v:147677$7331_Y - attribute \src "libresoc.v:147680.18-147680.119" - wire $ternary$libresoc.v:147680$7334_Y - attribute \src "libresoc.v:147684.18-147684.123" - wire $ternary$libresoc.v:147684$7338_Y + wire $not$libresoc.v:147668$7323_Y + attribute \src "libresoc.v:147672.18-147672.99" + wire $not$libresoc.v:147672$7327_Y + attribute \src "libresoc.v:147673.18-147673.99" + wire $not$libresoc.v:147673$7328_Y + attribute \src "libresoc.v:147652.18-147652.104" + wire $or$libresoc.v:147652$7307_Y + attribute \src "libresoc.v:147655.18-147655.104" + wire $or$libresoc.v:147655$7310_Y + attribute \src "libresoc.v:147658.18-147658.104" + wire $or$libresoc.v:147658$7313_Y + attribute \src "libresoc.v:147669.18-147669.110" + wire $or$libresoc.v:147669$7324_Y + attribute \src "libresoc.v:147674.18-147674.110" + wire $or$libresoc.v:147674$7329_Y + attribute \src "libresoc.v:147677.18-147677.110" + wire $or$libresoc.v:147677$7332_Y + attribute \src "libresoc.v:147680.18-147680.110" + wire $or$libresoc.v:147680$7335_Y + attribute \src "libresoc.v:147623.18-147623.98" + wire $reduce_or$libresoc.v:147623$7278_Y + attribute \src "libresoc.v:147627.19-147627.99" + wire $reduce_or$libresoc.v:147627$7282_Y + attribute \src "libresoc.v:147664.18-147664.99" + wire $reduce_or$libresoc.v:147664$7319_Y + attribute \src "libresoc.v:147667.18-147667.99" + wire $reduce_or$libresoc.v:147667$7322_Y + attribute \src "libresoc.v:147676.18-147676.121" + wire $ternary$libresoc.v:147676$7331_Y + attribute \src "libresoc.v:147679.18-147679.119" + wire $ternary$libresoc.v:147679$7334_Y + attribute \src "libresoc.v:147683.18-147683.123" + wire $ternary$libresoc.v:147683$7338_Y + attribute \src "libresoc.v:147628.19-147628.111" + wire $xor$libresoc.v:147628$7283_Y attribute \src "libresoc.v:147629.19-147629.111" - wire $xor$libresoc.v:147629$7283_Y - attribute \src "libresoc.v:147630.19-147630.111" - wire $xor$libresoc.v:147630$7284_Y + wire $xor$libresoc.v:147629$7284_Y + attribute \src "libresoc.v:147630.19-147630.110" + wire $xor$libresoc.v:147630$7285_Y attribute \src "libresoc.v:147631.19-147631.110" - wire $xor$libresoc.v:147631$7285_Y - attribute \src "libresoc.v:147632.19-147632.110" - wire $xor$libresoc.v:147632$7286_Y + wire $xor$libresoc.v:147631$7286_Y + attribute \src "libresoc.v:147634.19-147634.110" + wire $xor$libresoc.v:147634$7289_Y attribute \src "libresoc.v:147635.19-147635.110" - wire $xor$libresoc.v:147635$7289_Y - attribute \src "libresoc.v:147636.19-147636.110" - wire $xor$libresoc.v:147636$7290_Y - attribute \src "libresoc.v:147662.18-147662.111" - wire $xor$libresoc.v:147662$7316_Y - attribute \src "libresoc.v:147663.18-147663.107" - wire $xor$libresoc.v:147663$7317_Y - attribute \src "libresoc.v:147664.18-147664.113" - wire width 32 $xor$libresoc.v:147664$7318_Y - attribute \src "libresoc.v:147667.18-147667.115" - wire width 32 $xor$libresoc.v:147667$7321_Y + wire $xor$libresoc.v:147635$7290_Y + attribute \src "libresoc.v:147661.18-147661.111" + wire $xor$libresoc.v:147661$7316_Y + attribute \src "libresoc.v:147662.18-147662.107" + wire $xor$libresoc.v:147662$7317_Y + attribute \src "libresoc.v:147663.18-147663.113" + wire width 32 $xor$libresoc.v:147663$7318_Y + attribute \src "libresoc.v:147666.18-147666.115" + wire width 32 $xor$libresoc.v:147666$7321_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" @@ -308136,7 +304946,7 @@ module \main wire output 45 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" wire width 8 \eqs - attribute \src "libresoc.v:147163.7-147163.15" + attribute \src "libresoc.v:147162.7-147162.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" wire \is_32bit @@ -308181,7 +304991,7 @@ module \main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" wire \zerolo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" - cell $add $add$libresoc.v:147660$7314 + cell $add $add$libresoc.v:147659$7314 parameter \A_SIGNED 0 parameter \A_WIDTH 66 parameter \B_SIGNED 0 @@ -308189,10 +304999,10 @@ module \main parameter \Y_WIDTH 67 connect \A \add_a connect \B \add_b - connect \Y $add$libresoc.v:147660$7314_Y + connect \Y $add$libresoc.v:147659$7314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:147634$7288 + cell $and $and$libresoc.v:147633$7288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308200,10 +305010,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$113 connect \B \$115 - connect \Y $and$libresoc.v:147634$7288_Y + connect \Y $and$libresoc.v:147633$7288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:147638$7292 + cell $and $and$libresoc.v:147637$7292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308211,10 +305021,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$121 connect \B \$123 - connect \Y $and$libresoc.v:147638$7292_Y + connect \Y $and$libresoc.v:147637$7292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:147671$7325 + cell $and $and$libresoc.v:147670$7325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308222,10 +305032,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$69 - connect \Y $and$libresoc.v:147671$7325_Y + connect \Y $and$libresoc.v:147670$7325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:147676$7330 + cell $and $and$libresoc.v:147675$7330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308233,10 +305043,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$79 - connect \Y $and$libresoc.v:147676$7330_Y + connect \Y $and$libresoc.v:147675$7330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:147679$7333 + cell $and $and$libresoc.v:147678$7333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308244,10 +305054,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$85 - connect \Y $and$libresoc.v:147679$7333_Y + connect \Y $and$libresoc.v:147678$7333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:147682$7336 + cell $and $and$libresoc.v:147681$7336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308255,10 +305065,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$91 - connect \Y $and$libresoc.v:147682$7336_Y + connect \Y $and$libresoc.v:147681$7336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - cell $eq $eq$libresoc.v:147625$7279 + cell $eq $eq$libresoc.v:147624$7279 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -308266,10 +305076,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 1'1 - connect \Y $eq$libresoc.v:147625$7279_Y + connect \Y $eq$libresoc.v:147624$7279_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" - cell $eq $eq$libresoc.v:147626$7280 + cell $eq $eq$libresoc.v:147625$7280 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -308277,10 +305087,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:147626$7280_Y + connect \Y $eq$libresoc.v:147625$7280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" - cell $eq $eq$libresoc.v:147627$7281 + cell $eq $eq$libresoc.v:147626$7281 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -308288,10 +305098,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 3'100 - connect \Y $eq$libresoc.v:147627$7281_Y + connect \Y $eq$libresoc.v:147626$7281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147639$7293 + cell $eq $eq$libresoc.v:147638$7293 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308299,10 +305109,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [7:0] - connect \Y $eq$libresoc.v:147639$7293_Y + connect \Y $eq$libresoc.v:147638$7293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147640$7294 + cell $eq $eq$libresoc.v:147639$7294 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308310,10 +305120,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [15:8] - connect \Y $eq$libresoc.v:147640$7294_Y + connect \Y $eq$libresoc.v:147639$7294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147641$7295 + cell $eq $eq$libresoc.v:147640$7295 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308321,10 +305131,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [23:16] - connect \Y $eq$libresoc.v:147641$7295_Y + connect \Y $eq$libresoc.v:147640$7295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147642$7296 + cell $eq $eq$libresoc.v:147641$7296 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308332,10 +305142,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [31:24] - connect \Y $eq$libresoc.v:147642$7296_Y + connect \Y $eq$libresoc.v:147641$7296_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147643$7297 + cell $eq $eq$libresoc.v:147642$7297 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308343,10 +305153,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [39:32] - connect \Y $eq$libresoc.v:147643$7297_Y + connect \Y $eq$libresoc.v:147642$7297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147644$7298 + cell $eq $eq$libresoc.v:147643$7298 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308354,10 +305164,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [47:40] - connect \Y $eq$libresoc.v:147644$7298_Y + connect \Y $eq$libresoc.v:147643$7298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147645$7299 + cell $eq $eq$libresoc.v:147644$7299 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308365,10 +305175,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [55:48] - connect \Y $eq$libresoc.v:147645$7299_Y + connect \Y $eq$libresoc.v:147644$7299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147646$7300 + cell $eq $eq$libresoc.v:147645$7300 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308376,10 +305186,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [63:56] - connect \Y $eq$libresoc.v:147646$7300_Y + connect \Y $eq$libresoc.v:147645$7300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" - cell $eq $eq$libresoc.v:147647$7301 + cell $eq $eq$libresoc.v:147646$7301 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308387,10 +305197,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147647$7301_Y + connect \Y $eq$libresoc.v:147646$7301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:147649$7303 + cell $eq $eq$libresoc.v:147648$7303 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308398,10 +305208,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147649$7303_Y + connect \Y $eq$libresoc.v:147648$7303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:147650$7304 + cell $eq $eq$libresoc.v:147649$7304 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308409,10 +305219,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147650$7304_Y + connect \Y $eq$libresoc.v:147649$7304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:147651$7305 + cell $eq $eq$libresoc.v:147650$7305 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308420,10 +305230,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:147651$7305_Y + connect \Y $eq$libresoc.v:147650$7305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:147652$7306 + cell $eq $eq$libresoc.v:147651$7306 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308431,10 +305241,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147652$7306_Y + connect \Y $eq$libresoc.v:147651$7306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:147654$7308 + cell $eq $eq$libresoc.v:147653$7308 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308442,10 +305252,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:147654$7308_Y + connect \Y $eq$libresoc.v:147653$7308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:147655$7309 + cell $eq $eq$libresoc.v:147654$7309 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308453,10 +305263,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147655$7309_Y + connect \Y $eq$libresoc.v:147654$7309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:147657$7311 + cell $eq $eq$libresoc.v:147656$7311 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308464,10 +305274,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:147657$7311_Y + connect \Y $eq$libresoc.v:147656$7311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:147658$7312 + cell $eq $eq$libresoc.v:147657$7312 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308475,10 +305285,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147658$7312_Y + connect \Y $eq$libresoc.v:147657$7312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:147672$7326 + cell $ne $ne$libresoc.v:147671$7326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308486,10 +305296,10 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:147672$7326_Y + connect \Y $ne$libresoc.v:147671$7326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:147683$7337 + cell $ne $ne$libresoc.v:147682$7337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308497,74 +305307,74 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:147683$7337_Y + connect \Y $ne$libresoc.v:147682$7337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:147633$7287 + cell $not $not$libresoc.v:147632$7287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$116 - connect \Y $not$libresoc.v:147633$7287_Y + connect \Y $not$libresoc.v:147632$7287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:147637$7291 + cell $not $not$libresoc.v:147636$7291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$124 - connect \Y $not$libresoc.v:147637$7291_Y + connect \Y $not$libresoc.v:147636$7291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" - cell $not $not$libresoc.v:147648$7302 + cell $not $not$libresoc.v:147647$7302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_op__insn [21] - connect \Y $not$libresoc.v:147648$7302_Y + connect \Y $not$libresoc.v:147647$7302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $not $not$libresoc.v:147661$7315 + cell $not $not$libresoc.v:147660$7315 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:147661$7315_Y + connect \Y $not$libresoc.v:147660$7315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $not $not$libresoc.v:147666$7320 + cell $not $not$libresoc.v:147665$7320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$58 - connect \Y $not$libresoc.v:147666$7320_Y + connect \Y $not$libresoc.v:147665$7320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $not $not$libresoc.v:147669$7323 + cell $not $not$libresoc.v:147668$7323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $not$libresoc.v:147669$7323_Y + connect \Y $not$libresoc.v:147668$7323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:147673$7327 + cell $not $not$libresoc.v:147672$7327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:147673$7327_Y + connect \Y $not$libresoc.v:147672$7327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:147674$7328 + cell $not $not$libresoc.v:147673$7328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:147674$7328_Y + connect \Y $not$libresoc.v:147673$7328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:147653$7307 + cell $or $or$libresoc.v:147652$7307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308572,10 +305382,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:147653$7307_Y + connect \Y $or$libresoc.v:147652$7307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:147656$7310 + cell $or $or$libresoc.v:147655$7310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308583,10 +305393,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:147656$7310_Y + connect \Y $or$libresoc.v:147655$7310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:147659$7313 + cell $or $or$libresoc.v:147658$7313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308594,10 +305404,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$42 connect \B \$44 - connect \Y $or$libresoc.v:147659$7313_Y + connect \Y $or$libresoc.v:147658$7313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:147670$7324 + cell $or $or$libresoc.v:147669$7324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308605,10 +305415,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:147670$7324_Y + connect \Y $or$libresoc.v:147669$7324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:147675$7329 + cell $or $or$libresoc.v:147674$7329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308616,10 +305426,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:147675$7329_Y + connect \Y $or$libresoc.v:147674$7329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:147678$7332 + cell $or $or$libresoc.v:147677$7332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308627,10 +305437,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:147678$7332_Y + connect \Y $or$libresoc.v:147677$7332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:147681$7335 + cell $or $or$libresoc.v:147680$7335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308638,66 +305448,66 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:147681$7335_Y + connect \Y $or$libresoc.v:147680$7335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" - cell $reduce_or $reduce_or$libresoc.v:147624$7278 + cell $reduce_or $reduce_or$libresoc.v:147623$7278 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:147624$7278_Y + connect \Y $reduce_or$libresoc.v:147623$7278_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" - cell $reduce_or $reduce_or$libresoc.v:147628$7282 + cell $reduce_or $reduce_or$libresoc.v:147627$7282 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:147628$7282_Y + connect \Y $reduce_or$libresoc.v:147627$7282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $reduce_or $reduce_or$libresoc.v:147665$7319 + cell $reduce_or $reduce_or$libresoc.v:147664$7319 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$59 - connect \Y $reduce_or$libresoc.v:147665$7319_Y + connect \Y $reduce_or$libresoc.v:147664$7319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $reduce_or $reduce_or$libresoc.v:147668$7322 + cell $reduce_or $reduce_or$libresoc.v:147667$7322 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$65 - connect \Y $reduce_or$libresoc.v:147668$7322_Y + connect \Y $reduce_or$libresoc.v:147667$7322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" - cell $mux $ternary$libresoc.v:147677$7331 + cell $mux $ternary$libresoc.v:147676$7331 parameter \WIDTH 1 connect \A \a_n [63] connect \B \a_n [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:147677$7331_Y + connect \Y $ternary$libresoc.v:147676$7331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" - cell $mux $ternary$libresoc.v:147680$7334 + cell $mux $ternary$libresoc.v:147679$7334 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:147680$7334_Y + connect \Y $ternary$libresoc.v:147679$7334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" - cell $mux $ternary$libresoc.v:147684$7338 + cell $mux $ternary$libresoc.v:147683$7338 parameter \WIDTH 1 connect \A \carry_64 connect \B \carry_32 connect \S \is_32bit - connect \Y $ternary$libresoc.v:147684$7338_Y + connect \Y $ternary$libresoc.v:147683$7338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:147629$7283 + cell $xor $xor$libresoc.v:147628$7283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308705,10 +305515,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [32] connect \B \b_i [32] - connect \Y $xor$libresoc.v:147629$7283_Y + connect \Y $xor$libresoc.v:147628$7283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:147630$7284 + cell $xor $xor$libresoc.v:147629$7284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308716,10 +305526,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \$109 - connect \Y $xor$libresoc.v:147630$7284_Y + connect \Y $xor$libresoc.v:147629$7284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:147631$7285 + cell $xor $xor$libresoc.v:147630$7285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308727,10 +305537,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [0] connect \B \add_o [64] - connect \Y $xor$libresoc.v:147631$7285_Y + connect \Y $xor$libresoc.v:147630$7285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:147632$7286 + cell $xor $xor$libresoc.v:147631$7286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308738,10 +305548,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [63] connect \B \b_i [63] - connect \Y $xor$libresoc.v:147632$7286_Y + connect \Y $xor$libresoc.v:147631$7286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:147635$7289 + cell $xor $xor$libresoc.v:147634$7289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308749,10 +305559,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [1] connect \B \add_o [32] - connect \Y $xor$libresoc.v:147635$7289_Y + connect \Y $xor$libresoc.v:147634$7289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:147636$7290 + cell $xor $xor$libresoc.v:147635$7290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308760,10 +305570,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [31] connect \B \b_i [31] - connect \Y $xor$libresoc.v:147636$7290_Y + connect \Y $xor$libresoc.v:147635$7290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:147662$7316 + cell $xor $xor$libresoc.v:147661$7316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308771,10 +305581,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \ra [32] - connect \Y $xor$libresoc.v:147662$7316_Y + connect \Y $xor$libresoc.v:147661$7316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:147663$7317 + cell $xor $xor$libresoc.v:147662$7317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308782,10 +305592,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$53 connect \B \rb [32] - connect \Y $xor$libresoc.v:147663$7317_Y + connect \Y $xor$libresoc.v:147662$7317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $xor $xor$libresoc.v:147664$7318 + cell $xor $xor$libresoc.v:147663$7318 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -308793,10 +305603,10 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [31:0] connect \B \rb [31:0] - connect \Y $xor$libresoc.v:147664$7318_Y + connect \Y $xor$libresoc.v:147663$7318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $xor $xor$libresoc.v:147667$7321 + cell $xor $xor$libresoc.v:147666$7321 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -308804,24 +305614,24 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [63:32] connect \B \rb [63:32] - connect \Y $xor$libresoc.v:147667$7321_Y + connect \Y $xor$libresoc.v:147666$7321_Y end - attribute \src "libresoc.v:147163.7-147163.20" - process $proc$libresoc.v:147163$7368 + attribute \src "libresoc.v:147162.7-147162.20" + process $proc$libresoc.v:147162$7368 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:147685.3-147694.6" - process $proc$libresoc.v:147685$7339 + attribute \src "libresoc.v:147684.3-147693.6" + process $proc$libresoc.v:147684$7339 assign { } { } assign { } { } assign $0\is_32bit[0:0] $1\is_32bit[0:0] - attribute \src "libresoc.v:147686.5-147686.29" + attribute \src "libresoc.v:147685.5-147685.29" switch \initial - attribute \src "libresoc.v:147686.9-147686.17" + attribute \src "libresoc.v:147685.9-147685.17" case 1'1 case end @@ -308837,13 +305647,13 @@ module \main sync always update \is_32bit $0\is_32bit[0:0] end - attribute \src "libresoc.v:147695.3-147717.6" - process $proc$libresoc.v:147695$7340 + attribute \src "libresoc.v:147694.3-147716.6" + process $proc$libresoc.v:147694$7340 assign { } { } assign $0\a_i[63:0] $1\a_i[63:0] - attribute \src "libresoc.v:147696.5-147696.29" + attribute \src "libresoc.v:147695.5-147695.29" switch \initial - attribute \src "libresoc.v:147696.9-147696.17" + attribute \src "libresoc.v:147695.9-147695.17" case 1'1 case end @@ -308876,14 +305686,14 @@ module \main sync always update \a_i $0\a_i[63:0] end - attribute \src "libresoc.v:147718.3-147728.6" - process $proc$libresoc.v:147718$7341 + attribute \src "libresoc.v:147717.3-147727.6" + process $proc$libresoc.v:147717$7341 assign { } { } assign { } { } assign $0\zerohi[0:0] $1\zerohi[0:0] - attribute \src "libresoc.v:147719.5-147719.29" + attribute \src "libresoc.v:147718.5-147718.29" switch \initial - attribute \src "libresoc.v:147719.9-147719.17" + attribute \src "libresoc.v:147718.9-147718.17" case 1'1 case end @@ -308899,14 +305709,14 @@ module \main sync always update \zerohi $0\zerohi[0:0] end - attribute \src "libresoc.v:147729.3-147755.6" - process $proc$libresoc.v:147729$7342 + attribute \src "libresoc.v:147728.3-147754.6" + process $proc$libresoc.v:147728$7342 assign { } { } assign { } { } assign $0\tval[4:0] $1\tval[4:0] - attribute \src "libresoc.v:147730.5-147730.29" + attribute \src "libresoc.v:147729.5-147729.29" switch \initial - attribute \src "libresoc.v:147730.9-147730.17" + attribute \src "libresoc.v:147729.9-147729.17" case 1'1 case end @@ -308944,14 +305754,14 @@ module \main sync always update \tval $0\tval[4:0] end - attribute \src "libresoc.v:147756.3-147774.6" - process $proc$libresoc.v:147756$7343 + attribute \src "libresoc.v:147755.3-147773.6" + process $proc$libresoc.v:147755$7343 assign { } { } assign { } { } assign $0\msb_a[0:0] $1\msb_a[0:0] - attribute \src "libresoc.v:147757.5-147757.29" + attribute \src "libresoc.v:147756.5-147756.29" switch \initial - attribute \src "libresoc.v:147757.9-147757.17" + attribute \src "libresoc.v:147756.9-147756.17" case 1'1 case end @@ -308977,14 +305787,14 @@ module \main sync always update \msb_a $0\msb_a[0:0] end - attribute \src "libresoc.v:147775.3-147793.6" - process $proc$libresoc.v:147775$7344 + attribute \src "libresoc.v:147774.3-147792.6" + process $proc$libresoc.v:147774$7344 assign { } { } assign { } { } assign $0\msb_b[0:0] $1\msb_b[0:0] - attribute \src "libresoc.v:147776.5-147776.29" + attribute \src "libresoc.v:147775.5-147775.29" switch \initial - attribute \src "libresoc.v:147776.9-147776.17" + attribute \src "libresoc.v:147775.9-147775.17" case 1'1 case end @@ -309010,14 +305820,14 @@ module \main sync always update \msb_b $0\msb_b[0:0] end - attribute \src "libresoc.v:147794.3-147820.6" - process $proc$libresoc.v:147794$7345 + attribute \src "libresoc.v:147793.3-147819.6" + process $proc$libresoc.v:147793$7345 assign { } { } assign { } { } assign $0\a_lt[0:0] $1\a_lt[0:0] - attribute \src "libresoc.v:147795.5-147795.29" + attribute \src "libresoc.v:147794.5-147794.29" switch \initial - attribute \src "libresoc.v:147795.9-147795.17" + attribute \src "libresoc.v:147794.9-147794.17" case 1'1 case end @@ -309053,14 +305863,14 @@ module \main sync always update \a_lt $0\a_lt[0:0] end - attribute \src "libresoc.v:147821.3-147846.6" - process $proc$libresoc.v:147821$7346 + attribute \src "libresoc.v:147820.3-147845.6" + process $proc$libresoc.v:147820$7346 assign { } { } assign { } { } assign $0\cr_a[3:0] $1\cr_a[3:0] - attribute \src "libresoc.v:147822.5-147822.29" + attribute \src "libresoc.v:147821.5-147821.29" switch \initial - attribute \src "libresoc.v:147822.9-147822.17" + attribute \src "libresoc.v:147821.9-147821.17" case 1'1 case end @@ -309092,14 +305902,14 @@ module \main sync always update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:147847.3-147861.6" - process $proc$libresoc.v:147847$7347 + attribute \src "libresoc.v:147846.3-147860.6" + process $proc$libresoc.v:147846$7347 assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - attribute \src "libresoc.v:147848.5-147848.29" + attribute \src "libresoc.v:147847.5-147847.29" switch \initial - attribute \src "libresoc.v:147848.9-147848.17" + attribute \src "libresoc.v:147847.9-147847.17" case 1'1 case end @@ -309119,14 +305929,14 @@ module \main sync always update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:147862.3-147899.6" - process $proc$libresoc.v:147862$7348 + attribute \src "libresoc.v:147861.3-147898.6" + process $proc$libresoc.v:147861$7348 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:147863.5-147863.29" + attribute \src "libresoc.v:147862.5-147862.29" switch \initial - attribute \src "libresoc.v:147863.9-147863.17" + attribute \src "libresoc.v:147862.9-147862.17" case 1'1 case end @@ -309179,14 +305989,14 @@ module \main sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:147900.3-147918.6" - process $proc$libresoc.v:147900$7349 + attribute \src "libresoc.v:147899.3-147917.6" + process $proc$libresoc.v:147899$7349 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:147901.5-147901.29" + attribute \src "libresoc.v:147900.5-147900.29" switch \initial - attribute \src "libresoc.v:147901.9-147901.17" + attribute \src "libresoc.v:147900.9-147900.17" case 1'1 case end @@ -309210,14 +306020,14 @@ module \main sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:147919.3-147932.6" - process $proc$libresoc.v:147919$7350 + attribute \src "libresoc.v:147918.3-147931.6" + process $proc$libresoc.v:147918$7350 assign { } { } assign { } { } assign $0\ca[1:0] $1\ca[1:0] - attribute \src "libresoc.v:147920.5-147920.29" + attribute \src "libresoc.v:147919.5-147919.29" switch \initial - attribute \src "libresoc.v:147920.9-147920.17" + attribute \src "libresoc.v:147919.9-147919.17" case 1'1 case end @@ -309234,13 +306044,13 @@ module \main sync always update \ca $0\ca[1:0] end - attribute \src "libresoc.v:147933.3-147955.6" - process $proc$libresoc.v:147933$7351 + attribute \src "libresoc.v:147932.3-147954.6" + process $proc$libresoc.v:147932$7351 assign { } { } assign $0\b_i[63:0] $1\b_i[63:0] - attribute \src "libresoc.v:147934.5-147934.29" + attribute \src "libresoc.v:147933.5-147933.29" switch \initial - attribute \src "libresoc.v:147934.9-147934.17" + attribute \src "libresoc.v:147933.9-147933.17" case 1'1 case end @@ -309273,14 +306083,14 @@ module \main sync always update \b_i $0\b_i[63:0] end - attribute \src "libresoc.v:147956.3-147966.6" - process $proc$libresoc.v:147956$7352 + attribute \src "libresoc.v:147955.3-147965.6" + process $proc$libresoc.v:147955$7352 assign { } { } assign { } { } assign $0\xer_ca$20[1:0]$7353 $1\xer_ca$20[1:0]$7354 - attribute \src "libresoc.v:147957.5-147957.29" + attribute \src "libresoc.v:147956.5-147956.29" switch \initial - attribute \src "libresoc.v:147957.9-147957.17" + attribute \src "libresoc.v:147956.9-147956.17" case 1'1 case end @@ -309296,14 +306106,14 @@ module \main sync always update \xer_ca$20 $0\xer_ca$20[1:0]$7353 end - attribute \src "libresoc.v:147967.3-147977.6" - process $proc$libresoc.v:147967$7355 + attribute \src "libresoc.v:147966.3-147976.6" + process $proc$libresoc.v:147966$7355 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:147968.5-147968.29" + attribute \src "libresoc.v:147967.5-147967.29" switch \initial - attribute \src "libresoc.v:147968.9-147968.17" + attribute \src "libresoc.v:147967.9-147967.17" case 1'1 case end @@ -309319,14 +306129,14 @@ module \main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:147978.3-147991.6" - process $proc$libresoc.v:147978$7356 + attribute \src "libresoc.v:147977.3-147990.6" + process $proc$libresoc.v:147977$7356 assign { } { } assign { } { } assign $0\ov[1:0] $1\ov[1:0] - attribute \src "libresoc.v:147979.5-147979.29" + attribute \src "libresoc.v:147978.5-147978.29" switch \initial - attribute \src "libresoc.v:147979.9-147979.17" + attribute \src "libresoc.v:147978.9-147978.17" case 1'1 case end @@ -309343,14 +306153,14 @@ module \main sync always update \ov $0\ov[1:0] end - attribute \src "libresoc.v:147992.3-148002.6" - process $proc$libresoc.v:147992$7357 + attribute \src "libresoc.v:147991.3-148001.6" + process $proc$libresoc.v:147991$7357 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:147993.5-147993.29" + attribute \src "libresoc.v:147992.5-147992.29" switch \initial - attribute \src "libresoc.v:147993.9-147993.17" + attribute \src "libresoc.v:147992.9-147992.17" case 1'1 case end @@ -309366,14 +306176,14 @@ module \main sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:148003.3-148013.6" - process $proc$libresoc.v:148003$7358 + attribute \src "libresoc.v:148002.3-148012.6" + process $proc$libresoc.v:148002$7358 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:148004.5-148004.29" + attribute \src "libresoc.v:148003.5-148003.29" switch \initial - attribute \src "libresoc.v:148004.9-148004.17" + attribute \src "libresoc.v:148003.9-148003.17" case 1'1 case end @@ -309389,14 +306199,14 @@ module \main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:148014.3-148024.6" - process $proc$libresoc.v:148014$7359 + attribute \src "libresoc.v:148013.3-148023.6" + process $proc$libresoc.v:148013$7359 assign { } { } assign { } { } assign $0\src1[7:0] $1\src1[7:0] - attribute \src "libresoc.v:148015.5-148015.29" + attribute \src "libresoc.v:148014.5-148014.29" switch \initial - attribute \src "libresoc.v:148015.9-148015.17" + attribute \src "libresoc.v:148014.9-148014.17" case 1'1 case end @@ -309412,14 +306222,14 @@ module \main sync always update \src1 $0\src1[7:0] end - attribute \src "libresoc.v:148025.3-148044.6" - process $proc$libresoc.v:148025$7360 + attribute \src "libresoc.v:148024.3-148043.6" + process $proc$libresoc.v:148024$7360 assign { } { } assign { } { } assign $0\eqs[7:0] $1\eqs[7:0] - attribute \src "libresoc.v:148026.5-148026.29" + attribute \src "libresoc.v:148025.5-148025.29" switch \initial - attribute \src "libresoc.v:148026.9-148026.17" + attribute \src "libresoc.v:148025.9-148025.17" case 1'1 case end @@ -309442,14 +306252,14 @@ module \main sync always update \eqs $0\eqs[7:0] end - attribute \src "libresoc.v:148045.3-148054.6" - process $proc$libresoc.v:148045$7361 + attribute \src "libresoc.v:148044.3-148053.6" + process $proc$libresoc.v:148044$7361 assign { } { } assign { } { } assign $0\add_a[65:0] $1\add_a[65:0] - attribute \src "libresoc.v:148046.5-148046.29" + attribute \src "libresoc.v:148045.5-148045.29" switch \initial - attribute \src "libresoc.v:148046.9-148046.17" + attribute \src "libresoc.v:148045.9-148045.17" case 1'1 case end @@ -309465,14 +306275,14 @@ module \main sync always update \add_a $0\add_a[65:0] end - attribute \src "libresoc.v:148055.3-148064.6" - process $proc$libresoc.v:148055$7362 + attribute \src "libresoc.v:148054.3-148063.6" + process $proc$libresoc.v:148054$7362 assign { } { } assign { } { } assign $0\add_b[65:0] $1\add_b[65:0] - attribute \src "libresoc.v:148056.5-148056.29" + attribute \src "libresoc.v:148055.5-148055.29" switch \initial - attribute \src "libresoc.v:148056.9-148056.17" + attribute \src "libresoc.v:148055.9-148055.17" case 1'1 case end @@ -309488,14 +306298,14 @@ module \main sync always update \add_b $0\add_b[65:0] end - attribute \src "libresoc.v:148065.3-148074.6" - process $proc$libresoc.v:148065$7363 + attribute \src "libresoc.v:148064.3-148073.6" + process $proc$libresoc.v:148064$7363 assign { } { } assign { } { } assign $0\add_o[65:0] $1\add_o[65:0] - attribute \src "libresoc.v:148066.5-148066.29" + attribute \src "libresoc.v:148065.5-148065.29" switch \initial - attribute \src "libresoc.v:148066.9-148066.17" + attribute \src "libresoc.v:148065.9-148065.17" case 1'1 case end @@ -309511,14 +306321,14 @@ module \main sync always update \add_o $0\add_o[65:0] end - attribute \src "libresoc.v:148075.3-148085.6" - process $proc$libresoc.v:148075$7364 + attribute \src "libresoc.v:148074.3-148084.6" + process $proc$libresoc.v:148074$7364 assign { } { } assign { } { } assign $0\a_n[63:0] $1\a_n[63:0] - attribute \src "libresoc.v:148076.5-148076.29" + attribute \src "libresoc.v:148075.5-148075.29" switch \initial - attribute \src "libresoc.v:148076.9-148076.17" + attribute \src "libresoc.v:148075.9-148075.17" case 1'1 case end @@ -309534,14 +306344,14 @@ module \main sync always update \a_n $0\a_n[63:0] end - attribute \src "libresoc.v:148086.3-148096.6" - process $proc$libresoc.v:148086$7365 + attribute \src "libresoc.v:148085.3-148095.6" + process $proc$libresoc.v:148085$7365 assign { } { } assign { } { } assign $0\carry_32[0:0] $1\carry_32[0:0] - attribute \src "libresoc.v:148087.5-148087.29" + attribute \src "libresoc.v:148086.5-148086.29" switch \initial - attribute \src "libresoc.v:148087.9-148087.17" + attribute \src "libresoc.v:148086.9-148086.17" case 1'1 case end @@ -309557,14 +306367,14 @@ module \main sync always update \carry_32 $0\carry_32[0:0] end - attribute \src "libresoc.v:148097.3-148107.6" - process $proc$libresoc.v:148097$7366 + attribute \src "libresoc.v:148096.3-148106.6" + process $proc$libresoc.v:148096$7366 assign { } { } assign { } { } assign $0\carry_64[0:0] $1\carry_64[0:0] - attribute \src "libresoc.v:148098.5-148098.29" + attribute \src "libresoc.v:148097.5-148097.29" switch \initial - attribute \src "libresoc.v:148098.9-148098.17" + attribute \src "libresoc.v:148097.9-148097.17" case 1'1 case end @@ -309580,14 +306390,14 @@ module \main sync always update \carry_64 $0\carry_64[0:0] end - attribute \src "libresoc.v:148108.3-148118.6" - process $proc$libresoc.v:148108$7367 + attribute \src "libresoc.v:148107.3-148117.6" + process $proc$libresoc.v:148107$7367 assign { } { } assign { } { } assign $0\zerolo[0:0] $1\zerolo[0:0] - attribute \src "libresoc.v:148109.5-148109.29" + attribute \src "libresoc.v:148108.5-148108.29" switch \initial - attribute \src "libresoc.v:148109.9-148109.17" + attribute \src "libresoc.v:148108.9-148108.17" case 1'1 case end @@ -309603,88 +306413,88 @@ module \main sync always update \zerolo $0\zerolo[0:0] end - connect \$99 $reduce_or$libresoc.v:147624$7278_Y - connect \$101 $eq$libresoc.v:147625$7279_Y - connect \$103 $eq$libresoc.v:147626$7280_Y - connect \$105 $eq$libresoc.v:147627$7281_Y - connect \$107 $reduce_or$libresoc.v:147628$7282_Y - connect \$109 $xor$libresoc.v:147629$7283_Y - connect \$111 $xor$libresoc.v:147630$7284_Y - connect \$113 $xor$libresoc.v:147631$7285_Y - connect \$116 $xor$libresoc.v:147632$7286_Y - connect \$115 $not$libresoc.v:147633$7287_Y - connect \$119 $and$libresoc.v:147634$7288_Y - connect \$121 $xor$libresoc.v:147635$7289_Y - connect \$124 $xor$libresoc.v:147636$7290_Y - connect \$123 $not$libresoc.v:147637$7291_Y - connect \$127 $and$libresoc.v:147638$7292_Y - connect \$129 $eq$libresoc.v:147639$7293_Y - connect \$131 $eq$libresoc.v:147640$7294_Y - connect \$133 $eq$libresoc.v:147641$7295_Y - connect \$135 $eq$libresoc.v:147642$7296_Y - connect \$137 $eq$libresoc.v:147643$7297_Y - connect \$139 $eq$libresoc.v:147644$7298_Y - connect \$141 $eq$libresoc.v:147645$7299_Y - connect \$143 $eq$libresoc.v:147646$7300_Y - connect \$22 $eq$libresoc.v:147647$7301_Y - connect \$24 $not$libresoc.v:147648$7302_Y - connect \$26 $eq$libresoc.v:147649$7303_Y - connect \$28 $eq$libresoc.v:147650$7304_Y - connect \$30 $eq$libresoc.v:147651$7305_Y - connect \$32 $eq$libresoc.v:147652$7306_Y - connect \$34 $or$libresoc.v:147653$7307_Y - connect \$36 $eq$libresoc.v:147654$7308_Y - connect \$38 $eq$libresoc.v:147655$7309_Y - connect \$40 $or$libresoc.v:147656$7310_Y - connect \$42 $eq$libresoc.v:147657$7311_Y - connect \$44 $eq$libresoc.v:147658$7312_Y - connect \$46 $or$libresoc.v:147659$7313_Y - connect \$49 $add$libresoc.v:147660$7314_Y - connect \$51 $not$libresoc.v:147661$7315_Y - connect \$53 $xor$libresoc.v:147662$7316_Y - connect \$55 $xor$libresoc.v:147663$7317_Y - connect \$59 $xor$libresoc.v:147664$7318_Y - connect \$58 $reduce_or$libresoc.v:147665$7319_Y - connect \$57 $not$libresoc.v:147666$7320_Y - connect \$65 $xor$libresoc.v:147667$7321_Y - connect \$64 $reduce_or$libresoc.v:147668$7322_Y - connect \$63 $not$libresoc.v:147669$7323_Y - connect \$69 $or$libresoc.v:147670$7324_Y - connect \$71 $and$libresoc.v:147671$7325_Y - connect \$73 $ne$libresoc.v:147672$7326_Y - connect \$75 $not$libresoc.v:147673$7327_Y - connect \$77 $not$libresoc.v:147674$7328_Y - connect \$79 $or$libresoc.v:147675$7329_Y - connect \$81 $and$libresoc.v:147676$7330_Y - connect \$83 $ternary$libresoc.v:147677$7331_Y - connect \$85 $or$libresoc.v:147678$7332_Y - connect \$87 $and$libresoc.v:147679$7333_Y - connect \$89 $ternary$libresoc.v:147680$7334_Y - connect \$91 $or$libresoc.v:147681$7335_Y - connect \$93 $and$libresoc.v:147682$7336_Y - connect \$95 $ne$libresoc.v:147683$7337_Y - connect \$97 $ternary$libresoc.v:147684$7338_Y + connect \$99 $reduce_or$libresoc.v:147623$7278_Y + connect \$101 $eq$libresoc.v:147624$7279_Y + connect \$103 $eq$libresoc.v:147625$7280_Y + connect \$105 $eq$libresoc.v:147626$7281_Y + connect \$107 $reduce_or$libresoc.v:147627$7282_Y + connect \$109 $xor$libresoc.v:147628$7283_Y + connect \$111 $xor$libresoc.v:147629$7284_Y + connect \$113 $xor$libresoc.v:147630$7285_Y + connect \$116 $xor$libresoc.v:147631$7286_Y + connect \$115 $not$libresoc.v:147632$7287_Y + connect \$119 $and$libresoc.v:147633$7288_Y + connect \$121 $xor$libresoc.v:147634$7289_Y + connect \$124 $xor$libresoc.v:147635$7290_Y + connect \$123 $not$libresoc.v:147636$7291_Y + connect \$127 $and$libresoc.v:147637$7292_Y + connect \$129 $eq$libresoc.v:147638$7293_Y + connect \$131 $eq$libresoc.v:147639$7294_Y + connect \$133 $eq$libresoc.v:147640$7295_Y + connect \$135 $eq$libresoc.v:147641$7296_Y + connect \$137 $eq$libresoc.v:147642$7297_Y + connect \$139 $eq$libresoc.v:147643$7298_Y + connect \$141 $eq$libresoc.v:147644$7299_Y + connect \$143 $eq$libresoc.v:147645$7300_Y + connect \$22 $eq$libresoc.v:147646$7301_Y + connect \$24 $not$libresoc.v:147647$7302_Y + connect \$26 $eq$libresoc.v:147648$7303_Y + connect \$28 $eq$libresoc.v:147649$7304_Y + connect \$30 $eq$libresoc.v:147650$7305_Y + connect \$32 $eq$libresoc.v:147651$7306_Y + connect \$34 $or$libresoc.v:147652$7307_Y + connect \$36 $eq$libresoc.v:147653$7308_Y + connect \$38 $eq$libresoc.v:147654$7309_Y + connect \$40 $or$libresoc.v:147655$7310_Y + connect \$42 $eq$libresoc.v:147656$7311_Y + connect \$44 $eq$libresoc.v:147657$7312_Y + connect \$46 $or$libresoc.v:147658$7313_Y + connect \$49 $add$libresoc.v:147659$7314_Y + connect \$51 $not$libresoc.v:147660$7315_Y + connect \$53 $xor$libresoc.v:147661$7316_Y + connect \$55 $xor$libresoc.v:147662$7317_Y + connect \$59 $xor$libresoc.v:147663$7318_Y + connect \$58 $reduce_or$libresoc.v:147664$7319_Y + connect \$57 $not$libresoc.v:147665$7320_Y + connect \$65 $xor$libresoc.v:147666$7321_Y + connect \$64 $reduce_or$libresoc.v:147667$7322_Y + connect \$63 $not$libresoc.v:147668$7323_Y + connect \$69 $or$libresoc.v:147669$7324_Y + connect \$71 $and$libresoc.v:147670$7325_Y + connect \$73 $ne$libresoc.v:147671$7326_Y + connect \$75 $not$libresoc.v:147672$7327_Y + connect \$77 $not$libresoc.v:147673$7328_Y + connect \$79 $or$libresoc.v:147674$7329_Y + connect \$81 $and$libresoc.v:147675$7330_Y + connect \$83 $ternary$libresoc.v:147676$7331_Y + connect \$85 $or$libresoc.v:147677$7332_Y + connect \$87 $and$libresoc.v:147678$7333_Y + connect \$89 $ternary$libresoc.v:147679$7334_Y + connect \$91 $or$libresoc.v:147680$7335_Y + connect \$93 $and$libresoc.v:147681$7336_Y + connect \$95 $ne$libresoc.v:147682$7337_Y + connect \$97 $ternary$libresoc.v:147683$7338_Y connect \$48 \$49 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$21 \xer_so end -attribute \src "libresoc.v:148127.1-148541.10" +attribute \src "libresoc.v:148126.1-148540.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" attribute \generator "nMigen" module \main$114 - attribute \src "libresoc.v:148128.7-148128.20" + attribute \src "libresoc.v:148127.7-148127.20" wire $0\initial[0:0] - attribute \src "libresoc.v:148493.3-148523.6" + attribute \src "libresoc.v:148492.3-148522.6" wire width 4 $0\mode[3:0] - attribute \src "libresoc.v:148458.3-148492.6" + attribute \src "libresoc.v:148457.3-148491.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:148493.3-148523.6" + attribute \src "libresoc.v:148492.3-148522.6" wire width 4 $1\mode[3:0] - attribute \src "libresoc.v:148458.3-148492.6" + attribute \src "libresoc.v:148457.3-148491.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:148128.7-148128.15" + attribute \src "libresoc.v:148127.7-148127.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" wire width 5 \mb @@ -309999,7 +306809,7 @@ module \main$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 42 \xer_so$19 attribute \module_not_derived 1 - attribute \src "libresoc.v:148442.11-148457.4" + attribute \src "libresoc.v:148441.11-148456.4" cell \rotator \rotator connect \arith \rotator_arith connect \carry_out_o \rotator_carry_out_o @@ -310016,22 +306826,22 @@ module \main$114 connect \shift \rotator_shift connect \sign_ext_rs \rotator_sign_ext_rs end - attribute \src "libresoc.v:148128.7-148128.20" - process $proc$libresoc.v:148128$7371 + attribute \src "libresoc.v:148127.7-148127.20" + process $proc$libresoc.v:148127$7371 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:148458.3-148492.6" - process $proc$libresoc.v:148458$7369 + attribute \src "libresoc.v:148457.3-148491.6" + process $proc$libresoc.v:148457$7369 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:148459.5-148459.29" + attribute \src "libresoc.v:148458.5-148458.29" switch \initial - attribute \src "libresoc.v:148459.9-148459.17" + attribute \src "libresoc.v:148458.9-148458.17" case 1'1 case end @@ -310063,14 +306873,14 @@ module \main$114 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:148493.3-148523.6" - process $proc$libresoc.v:148493$7370 + attribute \src "libresoc.v:148492.3-148522.6" + process $proc$libresoc.v:148492$7370 assign { } { } assign { } { } assign $0\mode[3:0] $1\mode[3:0] - attribute \src "libresoc.v:148494.5-148494.29" + attribute \src "libresoc.v:148493.5-148493.29" switch \initial - attribute \src "libresoc.v:148494.9-148494.17" + attribute \src "libresoc.v:148493.9-148493.17" case 1'1 case end @@ -310124,109 +306934,109 @@ module \main$114 connect \me \sr_op__insn [5:1] connect \mb \sr_op__insn [10:6] end -attribute \src "libresoc.v:148545.1-149081.10" +attribute \src "libresoc.v:148544.1-149080.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main" attribute \generator "nMigen" module \main$22 - attribute \src "libresoc.v:148988.3-149011.6" + attribute \src "libresoc.v:148987.3-149010.6" wire $0\bc_taken[0:0] - attribute \src "libresoc.v:148867.3-148878.6" + attribute \src "libresoc.v:148866.3-148877.6" wire width 64 $0\br_addr[63:0] - attribute \src "libresoc.v:148879.3-148905.6" + attribute \src "libresoc.v:148878.3-148904.6" wire width 64 $0\br_imm_addr[63:0] - attribute \src "libresoc.v:148906.3-148924.6" + attribute \src "libresoc.v:148905.3-148923.6" wire $0\br_taken[0:0] - attribute \src "libresoc.v:148960.3-148974.6" + attribute \src "libresoc.v:148959.3-148973.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:149038.3-149058.6" + attribute \src "libresoc.v:149037.3-149057.6" wire width 64 $0\ctr_m[63:0] - attribute \src "libresoc.v:149012.3-149024.6" + attribute \src "libresoc.v:149011.3-149023.6" wire width 64 $0\ctr_n[63:0] - attribute \src "libresoc.v:148975.3-148987.6" + attribute \src "libresoc.v:148974.3-148986.6" wire $0\ctr_write[0:0] - attribute \src "libresoc.v:149059.3-149071.6" + attribute \src "libresoc.v:149058.3-149070.6" wire $0\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:149025.3-149037.6" + attribute \src "libresoc.v:149024.3-149036.6" wire width 64 $0\fast1$10[63:0]$7404 - attribute \src "libresoc.v:148925.3-148939.6" + attribute \src "libresoc.v:148924.3-148938.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:148940.3-148949.6" + attribute \src "libresoc.v:148939.3-148948.6" wire width 64 $0\fast2$11[63:0]$7396 - attribute \src "libresoc.v:148950.3-148959.6" + attribute \src "libresoc.v:148949.3-148958.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:148546.7-148546.20" + attribute \src "libresoc.v:148545.7-148545.20" wire $0\initial[0:0] - attribute \src "libresoc.v:148988.3-149011.6" + attribute \src "libresoc.v:148987.3-149010.6" wire $1\bc_taken[0:0] - attribute \src "libresoc.v:148867.3-148878.6" + attribute \src "libresoc.v:148866.3-148877.6" wire width 64 $1\br_addr[63:0] - attribute \src "libresoc.v:148879.3-148905.6" + attribute \src "libresoc.v:148878.3-148904.6" wire width 64 $1\br_imm_addr[63:0] - attribute \src "libresoc.v:148906.3-148924.6" + attribute \src "libresoc.v:148905.3-148923.6" wire $1\br_taken[0:0] - attribute \src "libresoc.v:148960.3-148974.6" + attribute \src "libresoc.v:148959.3-148973.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:149038.3-149058.6" + attribute \src "libresoc.v:149037.3-149057.6" wire width 64 $1\ctr_m[63:0] - attribute \src "libresoc.v:149012.3-149024.6" + attribute \src "libresoc.v:149011.3-149023.6" wire width 64 $1\ctr_n[63:0] - attribute \src "libresoc.v:148975.3-148987.6" + attribute \src "libresoc.v:148974.3-148986.6" wire $1\ctr_write[0:0] - attribute \src "libresoc.v:149059.3-149071.6" + attribute \src "libresoc.v:149058.3-149070.6" wire $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:149025.3-149037.6" + attribute \src "libresoc.v:149024.3-149036.6" wire width 64 $1\fast1$10[63:0]$7405 - attribute \src "libresoc.v:148925.3-148939.6" + attribute \src "libresoc.v:148924.3-148938.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:148940.3-148949.6" + attribute \src "libresoc.v:148939.3-148948.6" wire width 64 $1\fast2$11[63:0]$7397 - attribute \src "libresoc.v:148950.3-148959.6" + attribute \src "libresoc.v:148949.3-148958.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:148988.3-149011.6" + attribute \src "libresoc.v:148987.3-149010.6" wire $2\bc_taken[0:0] - attribute \src "libresoc.v:148879.3-148905.6" + attribute \src "libresoc.v:148878.3-148904.6" wire width 64 $2\br_imm_addr[63:0] - attribute \src "libresoc.v:149038.3-149058.6" + attribute \src "libresoc.v:149037.3-149057.6" wire width 64 $2\ctr_m[63:0] - attribute \src "libresoc.v:148851.18-148851.119" - wire width 65 $add$libresoc.v:148851$7374_Y - attribute \src "libresoc.v:148866.18-148866.113" - wire width 65 $add$libresoc.v:148866$7390_Y - attribute \src "libresoc.v:148858.18-148858.115" - wire $and$libresoc.v:148858$7381_Y - attribute \src "libresoc.v:148859.18-148859.117" - wire $and$libresoc.v:148859$7382_Y - attribute \src "libresoc.v:148865.18-148865.118" - wire $and$libresoc.v:148865$7389_Y - attribute \src "libresoc.v:148849.18-148849.120" - wire $eq$libresoc.v:148849$7372_Y - attribute \src "libresoc.v:148852.18-148852.111" - wire $eq$libresoc.v:148852$7375_Y + attribute \src "libresoc.v:148850.18-148850.119" + wire width 65 $add$libresoc.v:148850$7374_Y + attribute \src "libresoc.v:148865.18-148865.113" + wire width 65 $add$libresoc.v:148865$7390_Y + attribute \src "libresoc.v:148857.18-148857.115" + wire $and$libresoc.v:148857$7381_Y + attribute \src "libresoc.v:148858.18-148858.117" + wire $and$libresoc.v:148858$7382_Y + attribute \src "libresoc.v:148864.18-148864.118" + wire $and$libresoc.v:148864$7389_Y + attribute \src "libresoc.v:148848.18-148848.120" + wire $eq$libresoc.v:148848$7372_Y + attribute \src "libresoc.v:148851.18-148851.111" + wire $eq$libresoc.v:148851$7375_Y + attribute \src "libresoc.v:148853.18-148853.111" + wire $eq$libresoc.v:148853$7377_Y attribute \src "libresoc.v:148854.18-148854.111" - wire $eq$libresoc.v:148854$7377_Y - attribute \src "libresoc.v:148855.18-148855.111" - wire $eq$libresoc.v:148855$7378_Y - attribute \src "libresoc.v:148856.18-148856.109" - wire $eq$libresoc.v:148856$7379_Y - attribute \src "libresoc.v:148861.18-148861.98" - wire width 64 $extend$libresoc.v:148861$7384_Y - attribute \src "libresoc.v:148857.18-148857.104" - wire $not$libresoc.v:148857$7380_Y - attribute \src "libresoc.v:148864.18-148864.112" - wire $not$libresoc.v:148864$7388_Y - attribute \src "libresoc.v:148850.18-148850.116" - wire $or$libresoc.v:148850$7373_Y - attribute \src "libresoc.v:148853.18-148853.109" - wire $or$libresoc.v:148853$7376_Y - attribute \src "libresoc.v:148861.18-148861.98" - wire width 64 $pos$libresoc.v:148861$7385_Y - attribute \src "libresoc.v:148862.18-148862.103" - wire $reduce_or$libresoc.v:148862$7386_Y - attribute \src "libresoc.v:148860.18-148860.108" - wire width 65 $sub$libresoc.v:148860$7383_Y - attribute \src "libresoc.v:148863.18-148863.108" - wire $xor$libresoc.v:148863$7387_Y + wire $eq$libresoc.v:148854$7378_Y + attribute \src "libresoc.v:148855.18-148855.109" + wire $eq$libresoc.v:148855$7379_Y + attribute \src "libresoc.v:148860.18-148860.98" + wire width 64 $extend$libresoc.v:148860$7384_Y + attribute \src "libresoc.v:148856.18-148856.104" + wire $not$libresoc.v:148856$7380_Y + attribute \src "libresoc.v:148863.18-148863.112" + wire $not$libresoc.v:148863$7388_Y + attribute \src "libresoc.v:148849.18-148849.116" + wire $or$libresoc.v:148849$7373_Y + attribute \src "libresoc.v:148852.18-148852.109" + wire $or$libresoc.v:148852$7376_Y + attribute \src "libresoc.v:148860.18-148860.98" + wire width 64 $pos$libresoc.v:148860$7385_Y + attribute \src "libresoc.v:148861.18-148861.103" + wire $reduce_or$libresoc.v:148861$7386_Y + attribute \src "libresoc.v:148859.18-148859.108" + wire width 65 $sub$libresoc.v:148859$7383_Y + attribute \src "libresoc.v:148862.18-148862.108" + wire $xor$libresoc.v:148862$7387_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" @@ -310517,7 +307327,7 @@ module \main$22 wire width 64 output 23 \fast2$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 24 \fast2_ok - attribute \src "libresoc.v:148546.7-148546.15" + attribute \src "libresoc.v:148545.7-148545.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 27 \muxid @@ -310528,7 +307338,7 @@ module \main$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 26 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" - cell $add $add$libresoc.v:148851$7374 + cell $add $add$libresoc.v:148850$7374 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -310536,10 +307346,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_imm_addr connect \B \br_op__cia - connect \Y $add$libresoc.v:148851$7374_Y + connect \Y $add$libresoc.v:148850$7374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" - cell $add $add$libresoc.v:148866$7390 + cell $add $add$libresoc.v:148865$7390 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -310547,10 +307357,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:148866$7390_Y + connect \Y $add$libresoc.v:148865$7390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $and $and$libresoc.v:148858$7381 + cell $and $and$libresoc.v:148857$7381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310558,10 +307368,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \$29 - connect \Y $and$libresoc.v:148858$7381_Y + connect \Y $and$libresoc.v:148857$7381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" - cell $and $and$libresoc.v:148859$7382 + cell $and $and$libresoc.v:148858$7382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310569,10 +307379,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \cr_bit - connect \Y $and$libresoc.v:148859$7382_Y + connect \Y $and$libresoc.v:148858$7382_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $and $and$libresoc.v:148865$7389 + cell $and $and$libresoc.v:148864$7389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310580,10 +307390,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [10] connect \B \$44 - connect \Y $and$libresoc.v:148865$7389_Y + connect \Y $and$libresoc.v:148864$7389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $eq $eq$libresoc.v:148849$7372 + cell $eq $eq$libresoc.v:148848$7372 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -310591,10 +307401,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn_type connect \B 7'0001000 - connect \Y $eq$libresoc.v:148849$7372_Y + connect \Y $eq$libresoc.v:148848$7372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $eq $eq$libresoc.v:148852$7375 + cell $eq $eq$libresoc.v:148851$7375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310602,10 +307412,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \cr_bit connect \B \bo [3] - connect \Y $eq$libresoc.v:148852$7375_Y + connect \Y $eq$libresoc.v:148851$7375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - cell $eq $eq$libresoc.v:148854$7377 + cell $eq $eq$libresoc.v:148853$7377 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -310613,10 +307423,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'0 - connect \Y $eq$libresoc.v:148854$7377_Y + connect \Y $eq$libresoc.v:148853$7377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - cell $eq $eq$libresoc.v:148855$7378 + cell $eq $eq$libresoc.v:148854$7378 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -310624,10 +307434,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'1 - connect \Y $eq$libresoc.v:148855$7378_Y + connect \Y $eq$libresoc.v:148854$7378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" - cell $eq $eq$libresoc.v:148856$7379 + cell $eq $eq$libresoc.v:148855$7379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310635,34 +307445,34 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4] connect \B 1'1 - connect \Y $eq$libresoc.v:148856$7379_Y + connect \Y $eq$libresoc.v:148855$7379_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:148861$7384 + cell $pos $extend$libresoc.v:148860$7384 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \fast1 [31:0] - connect \Y $extend$libresoc.v:148861$7384_Y + connect \Y $extend$libresoc.v:148860$7384_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $not $not$libresoc.v:148857$7380 + cell $not $not$libresoc.v:148856$7380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_bit - connect \Y $not$libresoc.v:148857$7380_Y + connect \Y $not$libresoc.v:148856$7380_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $not $not$libresoc.v:148864$7388 + cell $not $not$libresoc.v:148863$7388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \br_op__insn [6] - connect \Y $not$libresoc.v:148864$7388_Y + connect \Y $not$libresoc.v:148863$7388_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $or $or$libresoc.v:148850$7373 + cell $or $or$libresoc.v:148849$7373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310670,10 +307480,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [1] connect \B \$12 - connect \Y $or$libresoc.v:148850$7373_Y + connect \Y $or$libresoc.v:148849$7373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $or $or$libresoc.v:148853$7376 + cell $or $or$libresoc.v:148852$7376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310681,26 +307491,26 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \$19 connect \B \bo [4] - connect \Y $or$libresoc.v:148853$7376_Y + connect \Y $or$libresoc.v:148852$7376_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:148861$7385 + cell $pos $pos$libresoc.v:148860$7385 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:148861$7384_Y - connect \Y $pos$libresoc.v:148861$7385_Y + connect \A $extend$libresoc.v:148860$7384_Y + connect \Y $pos$libresoc.v:148860$7385_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $reduce_or $reduce_or$libresoc.v:148862$7386 + cell $reduce_or $reduce_or$libresoc.v:148861$7386 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \ctr_n - connect \Y $reduce_or$libresoc.v:148862$7386_Y + connect \Y $reduce_or$libresoc.v:148861$7386_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" - cell $sub $sub$libresoc.v:148860$7383 + cell $sub $sub$libresoc.v:148859$7383 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -310708,10 +307518,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \fast1 connect \B 1'1 - connect \Y $sub$libresoc.v:148860$7383_Y + connect \Y $sub$libresoc.v:148859$7383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $xor $xor$libresoc.v:148863$7387 + cell $xor $xor$libresoc.v:148862$7387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310719,23 +307529,23 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [1] connect \B \$40 - connect \Y $xor$libresoc.v:148863$7387_Y + connect \Y $xor$libresoc.v:148862$7387_Y end - attribute \src "libresoc.v:148546.7-148546.20" - process $proc$libresoc.v:148546$7408 + attribute \src "libresoc.v:148545.7-148545.20" + process $proc$libresoc.v:148545$7408 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:148867.3-148878.6" - process $proc$libresoc.v:148867$7391 + attribute \src "libresoc.v:148866.3-148877.6" + process $proc$libresoc.v:148866$7391 assign { } { } assign $0\br_addr[63:0] $1\br_addr[63:0] - attribute \src "libresoc.v:148868.5-148868.29" + attribute \src "libresoc.v:148867.5-148867.29" switch \initial - attribute \src "libresoc.v:148868.9-148868.17" + attribute \src "libresoc.v:148867.9-148867.17" case 1'1 case end @@ -310753,14 +307563,14 @@ module \main$22 sync always update \br_addr $0\br_addr[63:0] end - attribute \src "libresoc.v:148879.3-148905.6" - process $proc$libresoc.v:148879$7392 + attribute \src "libresoc.v:148878.3-148904.6" + process $proc$libresoc.v:148878$7392 assign { } { } assign { } { } assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] - attribute \src "libresoc.v:148880.5-148880.29" + attribute \src "libresoc.v:148879.5-148879.29" switch \initial - attribute \src "libresoc.v:148880.9-148880.17" + attribute \src "libresoc.v:148879.9-148879.17" case 1'1 case end @@ -310795,14 +307605,14 @@ module \main$22 sync always update \br_imm_addr $0\br_imm_addr[63:0] end - attribute \src "libresoc.v:148906.3-148924.6" - process $proc$libresoc.v:148906$7393 + attribute \src "libresoc.v:148905.3-148923.6" + process $proc$libresoc.v:148905$7393 assign { } { } assign { } { } assign $0\br_taken[0:0] $1\br_taken[0:0] - attribute \src "libresoc.v:148907.5-148907.29" + attribute \src "libresoc.v:148906.5-148906.29" switch \initial - attribute \src "libresoc.v:148907.9-148907.17" + attribute \src "libresoc.v:148906.9-148906.17" case 1'1 case end @@ -310826,14 +307636,14 @@ module \main$22 sync always update \br_taken $0\br_taken[0:0] end - attribute \src "libresoc.v:148925.3-148939.6" - process $proc$libresoc.v:148925$7394 + attribute \src "libresoc.v:148924.3-148938.6" + process $proc$libresoc.v:148924$7394 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:148926.5-148926.29" + attribute \src "libresoc.v:148925.5-148925.29" switch \initial - attribute \src "libresoc.v:148926.9-148926.17" + attribute \src "libresoc.v:148925.9-148925.17" case 1'1 case end @@ -310853,14 +307663,14 @@ module \main$22 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:148940.3-148949.6" - process $proc$libresoc.v:148940$7395 + attribute \src "libresoc.v:148939.3-148948.6" + process $proc$libresoc.v:148939$7395 assign { } { } assign { } { } assign $0\fast2$11[63:0]$7396 $1\fast2$11[63:0]$7397 - attribute \src "libresoc.v:148941.5-148941.29" + attribute \src "libresoc.v:148940.5-148940.29" switch \initial - attribute \src "libresoc.v:148941.9-148941.17" + attribute \src "libresoc.v:148940.9-148940.17" case 1'1 case end @@ -310876,14 +307686,14 @@ module \main$22 sync always update \fast2$11 $0\fast2$11[63:0]$7396 end - attribute \src "libresoc.v:148950.3-148959.6" - process $proc$libresoc.v:148950$7398 + attribute \src "libresoc.v:148949.3-148958.6" + process $proc$libresoc.v:148949$7398 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:148951.5-148951.29" + attribute \src "libresoc.v:148950.5-148950.29" switch \initial - attribute \src "libresoc.v:148951.9-148951.17" + attribute \src "libresoc.v:148950.9-148950.17" case 1'1 case end @@ -310899,14 +307709,14 @@ module \main$22 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:148960.3-148974.6" - process $proc$libresoc.v:148960$7399 + attribute \src "libresoc.v:148959.3-148973.6" + process $proc$libresoc.v:148959$7399 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:148961.5-148961.29" + attribute \src "libresoc.v:148960.5-148960.29" switch \initial - attribute \src "libresoc.v:148961.9-148961.17" + attribute \src "libresoc.v:148960.9-148960.17" case 1'1 case end @@ -310934,14 +307744,14 @@ module \main$22 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:148975.3-148987.6" - process $proc$libresoc.v:148975$7400 + attribute \src "libresoc.v:148974.3-148986.6" + process $proc$libresoc.v:148974$7400 assign { } { } assign { } { } assign $0\ctr_write[0:0] $1\ctr_write[0:0] - attribute \src "libresoc.v:148976.5-148976.29" + attribute \src "libresoc.v:148975.5-148975.29" switch \initial - attribute \src "libresoc.v:148976.9-148976.17" + attribute \src "libresoc.v:148975.9-148975.17" case 1'1 case end @@ -310958,14 +307768,14 @@ module \main$22 sync always update \ctr_write $0\ctr_write[0:0] end - attribute \src "libresoc.v:148988.3-149011.6" - process $proc$libresoc.v:148988$7401 + attribute \src "libresoc.v:148987.3-149010.6" + process $proc$libresoc.v:148987$7401 assign { } { } assign { } { } assign $0\bc_taken[0:0] $1\bc_taken[0:0] - attribute \src "libresoc.v:148989.5-148989.29" + attribute \src "libresoc.v:148988.5-148988.29" switch \initial - attribute \src "libresoc.v:148989.9-148989.17" + attribute \src "libresoc.v:148988.9-148988.17" case 1'1 case end @@ -311000,14 +307810,14 @@ module \main$22 sync always update \bc_taken $0\bc_taken[0:0] end - attribute \src "libresoc.v:149012.3-149024.6" - process $proc$libresoc.v:149012$7402 + attribute \src "libresoc.v:149011.3-149023.6" + process $proc$libresoc.v:149011$7402 assign { } { } assign { } { } assign $0\ctr_n[63:0] $1\ctr_n[63:0] - attribute \src "libresoc.v:149013.5-149013.29" + attribute \src "libresoc.v:149012.5-149012.29" switch \initial - attribute \src "libresoc.v:149013.9-149013.17" + attribute \src "libresoc.v:149012.9-149012.17" case 1'1 case end @@ -311024,14 +307834,14 @@ module \main$22 sync always update \ctr_n $0\ctr_n[63:0] end - attribute \src "libresoc.v:149025.3-149037.6" - process $proc$libresoc.v:149025$7403 + attribute \src "libresoc.v:149024.3-149036.6" + process $proc$libresoc.v:149024$7403 assign { } { } assign { } { } assign $0\fast1$10[63:0]$7404 $1\fast1$10[63:0]$7405 - attribute \src "libresoc.v:149026.5-149026.29" + attribute \src "libresoc.v:149025.5-149025.29" switch \initial - attribute \src "libresoc.v:149026.9-149026.17" + attribute \src "libresoc.v:149025.9-149025.17" case 1'1 case end @@ -311048,14 +307858,14 @@ module \main$22 sync always update \fast1$10 $0\fast1$10[63:0]$7404 end - attribute \src "libresoc.v:149038.3-149058.6" - process $proc$libresoc.v:149038$7406 + attribute \src "libresoc.v:149037.3-149057.6" + process $proc$libresoc.v:149037$7406 assign { } { } assign { } { } assign $0\ctr_m[63:0] $1\ctr_m[63:0] - attribute \src "libresoc.v:149039.5-149039.29" + attribute \src "libresoc.v:149038.5-149038.29" switch \initial - attribute \src "libresoc.v:149039.9-149039.17" + attribute \src "libresoc.v:149038.9-149038.17" case 1'1 case end @@ -311083,14 +307893,14 @@ module \main$22 sync always update \ctr_m $0\ctr_m[63:0] end - attribute \src "libresoc.v:149059.3-149071.6" - process $proc$libresoc.v:149059$7407 + attribute \src "libresoc.v:149058.3-149070.6" + process $proc$libresoc.v:149058$7407 assign { } { } assign { } { } assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:149060.5-149060.29" + attribute \src "libresoc.v:149059.5-149059.29" switch \initial - attribute \src "libresoc.v:149060.9-149060.17" + attribute \src "libresoc.v:149059.9-149059.17" case 1'1 case end @@ -311107,24 +307917,24 @@ module \main$22 sync always update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] end - connect \$12 $eq$libresoc.v:148849$7372_Y - connect \$14 $or$libresoc.v:148850$7373_Y - connect \$17 $add$libresoc.v:148851$7374_Y - connect \$19 $eq$libresoc.v:148852$7375_Y - connect \$21 $or$libresoc.v:148853$7376_Y - connect \$23 $eq$libresoc.v:148854$7377_Y - connect \$25 $eq$libresoc.v:148855$7378_Y - connect \$27 $eq$libresoc.v:148856$7379_Y - connect \$29 $not$libresoc.v:148857$7380_Y - connect \$31 $and$libresoc.v:148858$7381_Y - connect \$33 $and$libresoc.v:148859$7382_Y - connect \$36 $sub$libresoc.v:148860$7383_Y - connect \$38 $pos$libresoc.v:148861$7385_Y - connect \$40 $reduce_or$libresoc.v:148862$7386_Y - connect \$42 $xor$libresoc.v:148863$7387_Y - connect \$44 $not$libresoc.v:148864$7388_Y - connect \$46 $and$libresoc.v:148865$7389_Y - connect \$49 $add$libresoc.v:148866$7390_Y + connect \$12 $eq$libresoc.v:148848$7372_Y + connect \$14 $or$libresoc.v:148849$7373_Y + connect \$17 $add$libresoc.v:148850$7374_Y + connect \$19 $eq$libresoc.v:148851$7375_Y + connect \$21 $or$libresoc.v:148852$7376_Y + connect \$23 $eq$libresoc.v:148853$7377_Y + connect \$25 $eq$libresoc.v:148854$7378_Y + connect \$27 $eq$libresoc.v:148855$7379_Y + connect \$29 $not$libresoc.v:148856$7380_Y + connect \$31 $and$libresoc.v:148857$7381_Y + connect \$33 $and$libresoc.v:148858$7382_Y + connect \$36 $sub$libresoc.v:148859$7383_Y + connect \$38 $pos$libresoc.v:148860$7385_Y + connect \$40 $reduce_or$libresoc.v:148861$7386_Y + connect \$42 $xor$libresoc.v:148862$7387_Y + connect \$44 $not$libresoc.v:148863$7388_Y + connect \$46 $and$libresoc.v:148864$7389_Y + connect \$49 $add$libresoc.v:148865$7390_Y connect \$16 \$17 connect \$35 \$36 connect \$48 \$49 @@ -311135,279 +307945,279 @@ module \main$22 connect \bi \br_op__insn [17:16] connect \bo \br_op__insn [25:21] end -attribute \src "libresoc.v:149085.1-150035.10" +attribute \src "libresoc.v:149084.1-150034.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" attribute \generator "nMigen" module \main$38 - attribute \src "libresoc.v:150000.3-150011.6" + attribute \src "libresoc.v:149999.3-150010.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:149498.3-149509.6" + attribute \src "libresoc.v:149497.3-149508.6" wire width 64 $0\a_s[63:0] - attribute \src "libresoc.v:150012.3-150023.6" + attribute \src "libresoc.v:150011.3-150022.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:149781.3-149792.6" + attribute \src "libresoc.v:149780.3-149791.6" wire width 64 $0\b_s[63:0] - attribute \src "libresoc.v:149574.3-149605.6" + attribute \src "libresoc.v:149573.3-149604.6" wire width 64 $0\fast1$11[63:0]$7454 - attribute \src "libresoc.v:149606.3-149637.6" + attribute \src "libresoc.v:149605.3-149636.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:149638.3-149720.6" + attribute \src "libresoc.v:149637.3-149719.6" wire width 64 $0\fast2$12[63:0]$7459 - attribute \src "libresoc.v:149721.3-149752.6" + attribute \src "libresoc.v:149720.3-149751.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:149086.7-149086.20" + attribute \src "libresoc.v:149085.7-149085.20" wire $0\initial[0:0] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire $0\msr_ok[0:0] - attribute \src "libresoc.v:149510.3-149541.6" + attribute \src "libresoc.v:149509.3-149540.6" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:149542.3-149573.6" + attribute \src "libresoc.v:149541.3-149572.6" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:149962.3-149980.6" + attribute \src "libresoc.v:149961.3-149979.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:149981.3-149999.6" + attribute \src "libresoc.v:149980.3-149998.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $0\trapexc_$signal$60[0:0]$7473 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $0\trapexc_$signal$61[0:0]$7474 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $0\trapexc_$signal$62[0:0]$7475 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $0\trapexc_$signal$67[0:0]$7476 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $0\trapexc_$signal$68[0:0]$7477 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $0\trapexc_$signal$69[0:0]$7478 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $0\trapexc_$signal$70[0:0]$7479 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $0\trapexc_$signal[0:0]$7472 - attribute \src "libresoc.v:149638.3-149720.6" + attribute \src "libresoc.v:149637.3-149719.6" wire $10\fast2$12[19:19]$7469 - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire width 2 $10\msr[5:4] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire $11\msr[15:15] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire $12\msr[12:12] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire $13\msr[60:60] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire $14\msr[12:12] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire $15\msr[12:12] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire width 2 $16\msr[5:4] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire $17\msr[15:15] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire width 3 $18\msr[34:32] - attribute \src "libresoc.v:150000.3-150011.6" + attribute \src "libresoc.v:149999.3-150010.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:149498.3-149509.6" + attribute \src "libresoc.v:149497.3-149508.6" wire width 64 $1\a_s[63:0] - attribute \src "libresoc.v:150012.3-150023.6" + attribute \src "libresoc.v:150011.3-150022.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:149781.3-149792.6" + attribute \src "libresoc.v:149780.3-149791.6" wire width 64 $1\b_s[63:0] - attribute \src "libresoc.v:149574.3-149605.6" + attribute \src "libresoc.v:149573.3-149604.6" wire width 64 $1\fast1$11[63:0]$7455 - attribute \src "libresoc.v:149606.3-149637.6" + attribute \src "libresoc.v:149605.3-149636.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:149638.3-149720.6" + attribute \src "libresoc.v:149637.3-149719.6" wire width 64 $1\fast2$12[63:0]$7460 - attribute \src "libresoc.v:149721.3-149752.6" + attribute \src "libresoc.v:149720.3-149751.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire $1\msr_ok[0:0] - attribute \src "libresoc.v:149510.3-149541.6" + attribute \src "libresoc.v:149509.3-149540.6" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:149542.3-149573.6" + attribute \src "libresoc.v:149541.3-149572.6" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:149962.3-149980.6" + attribute \src "libresoc.v:149961.3-149979.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:149981.3-149999.6" + attribute \src "libresoc.v:149980.3-149998.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $1\trapexc_$signal$60[0:0]$7481 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $1\trapexc_$signal$61[0:0]$7482 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $1\trapexc_$signal$62[0:0]$7483 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $1\trapexc_$signal$67[0:0]$7484 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $1\trapexc_$signal$68[0:0]$7485 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $1\trapexc_$signal$69[0:0]$7486 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $1\trapexc_$signal$70[0:0]$7487 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $1\trapexc_$signal[0:0]$7480 - attribute \src "libresoc.v:149574.3-149605.6" + attribute \src "libresoc.v:149573.3-149604.6" wire width 64 $2\fast1$11[63:0]$7456 - attribute \src "libresoc.v:149606.3-149637.6" + attribute \src "libresoc.v:149605.3-149636.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:149638.3-149720.6" + attribute \src "libresoc.v:149637.3-149719.6" wire width 64 $2\fast2$12[63:0]$7461 - attribute \src "libresoc.v:149721.3-149752.6" + attribute \src "libresoc.v:149720.3-149751.6" wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire $2\msr_ok[0:0] - attribute \src "libresoc.v:149510.3-149541.6" + attribute \src "libresoc.v:149509.3-149540.6" wire width 64 $2\nia[63:0] - attribute \src "libresoc.v:149542.3-149573.6" + attribute \src "libresoc.v:149541.3-149572.6" wire $2\nia_ok[0:0] - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $2\trapexc_$signal$60[0:0]$7489 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $2\trapexc_$signal$61[0:0]$7490 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $2\trapexc_$signal$62[0:0]$7491 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $2\trapexc_$signal$67[0:0]$7492 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $2\trapexc_$signal$68[0:0]$7493 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $2\trapexc_$signal$69[0:0]$7494 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $2\trapexc_$signal$70[0:0]$7495 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $2\trapexc_$signal[0:0]$7488 - attribute \src "libresoc.v:149638.3-149720.6" + attribute \src "libresoc.v:149637.3-149719.6" wire $3\fast2$12[17:17]$7462 - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire width 11 $3\msr[11:1] - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $3\trapexc_$signal$60[0:0]$7497 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $3\trapexc_$signal$61[0:0]$7498 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $3\trapexc_$signal$62[0:0]$7499 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $3\trapexc_$signal$67[0:0]$7500 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $3\trapexc_$signal$68[0:0]$7501 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $3\trapexc_$signal$69[0:0]$7502 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $3\trapexc_$signal$70[0:0]$7503 - attribute \src "libresoc.v:149753.3-149780.6" + attribute \src "libresoc.v:149752.3-149779.6" wire $3\trapexc_$signal[0:0]$7496 - attribute \src "libresoc.v:149638.3-149720.6" + attribute \src "libresoc.v:149637.3-149719.6" wire $4\fast2$12[18:18]$7463 - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire width 47 $4\msr[59:13] - attribute \src "libresoc.v:149638.3-149720.6" + attribute \src "libresoc.v:149637.3-149719.6" wire $5\fast2$12[20:20]$7464 - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire width 3 $5\msr[63:61] - attribute \src "libresoc.v:149638.3-149720.6" + attribute \src "libresoc.v:149637.3-149719.6" wire $6\fast2$12[16:16]$7465 - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire width 11 $6\msr[11:1] - attribute \src "libresoc.v:149638.3-149720.6" + attribute \src "libresoc.v:149637.3-149719.6" wire width 2 $7\fast2$12[19:18]$7466 - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire width 47 $7\msr[59:13] - attribute \src "libresoc.v:149638.3-149720.6" + attribute \src "libresoc.v:149637.3-149719.6" wire $8\fast2$12[28:28]$7467 - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire width 3 $8\msr[63:61] - attribute \src "libresoc.v:149638.3-149720.6" + attribute \src "libresoc.v:149637.3-149719.6" wire $9\fast2$12[30:30]$7468 - attribute \src "libresoc.v:149793.3-149961.6" + attribute \src "libresoc.v:149792.3-149960.6" wire width 3 $9\msr[34:32] - attribute \src "libresoc.v:149474.18-149474.113" - wire width 65 $add$libresoc.v:149474$7425_Y - attribute \src "libresoc.v:149468.18-149468.108" - wire width 5 $and$libresoc.v:149468$7418_Y - attribute \src "libresoc.v:149476.18-149476.118" - wire width 8 $and$libresoc.v:149476$7427_Y - attribute \src "libresoc.v:149478.18-149478.118" - wire width 8 $and$libresoc.v:149478$7429_Y - attribute \src "libresoc.v:149480.18-149480.118" - wire width 8 $and$libresoc.v:149480$7431_Y - attribute \src "libresoc.v:149482.18-149482.119" - wire width 8 $and$libresoc.v:149482$7433_Y - attribute \src "libresoc.v:149484.18-149484.119" - wire width 8 $and$libresoc.v:149484$7435_Y - attribute \src "libresoc.v:149486.18-149486.119" - wire width 8 $and$libresoc.v:149486$7437_Y - attribute \src "libresoc.v:149492.18-149492.106" - wire $and$libresoc.v:149492$7444_Y - attribute \src "libresoc.v:149497.18-149497.106" - wire $and$libresoc.v:149497$7449_Y - attribute \src "libresoc.v:149467.18-149467.100" - wire $eq$libresoc.v:149467$7417_Y - attribute \src "libresoc.v:149475.18-149475.119" - wire $eq$libresoc.v:149475$7426_Y + attribute \src "libresoc.v:149473.18-149473.113" + wire width 65 $add$libresoc.v:149473$7425_Y + attribute \src "libresoc.v:149467.18-149467.108" + wire width 5 $and$libresoc.v:149467$7418_Y + attribute \src "libresoc.v:149475.18-149475.118" + wire width 8 $and$libresoc.v:149475$7427_Y + attribute \src "libresoc.v:149477.18-149477.118" + wire width 8 $and$libresoc.v:149477$7429_Y + attribute \src "libresoc.v:149479.18-149479.118" + wire width 8 $and$libresoc.v:149479$7431_Y + attribute \src "libresoc.v:149481.18-149481.119" + wire width 8 $and$libresoc.v:149481$7433_Y + attribute \src "libresoc.v:149483.18-149483.119" + wire width 8 $and$libresoc.v:149483$7435_Y + attribute \src "libresoc.v:149485.18-149485.119" + wire width 8 $and$libresoc.v:149485$7437_Y + attribute \src "libresoc.v:149491.18-149491.106" + wire $and$libresoc.v:149491$7444_Y + attribute \src "libresoc.v:149496.18-149496.106" + wire $and$libresoc.v:149496$7449_Y + attribute \src "libresoc.v:149466.18-149466.100" + wire $eq$libresoc.v:149466$7417_Y + attribute \src "libresoc.v:149474.18-149474.119" + wire $eq$libresoc.v:149474$7426_Y + attribute \src "libresoc.v:149488.18-149488.121" + wire $eq$libresoc.v:149488$7441_Y attribute \src "libresoc.v:149489.18-149489.121" - wire $eq$libresoc.v:149489$7441_Y - attribute \src "libresoc.v:149490.18-149490.121" - wire $eq$libresoc.v:149490$7442_Y - attribute \src "libresoc.v:149491.18-149491.111" - wire $eq$libresoc.v:149491$7443_Y - attribute \src "libresoc.v:149495.18-149495.121" - wire $eq$libresoc.v:149495$7447_Y - attribute \src "libresoc.v:149496.18-149496.114" - wire $eq$libresoc.v:149496$7448_Y + wire $eq$libresoc.v:149489$7442_Y + attribute \src "libresoc.v:149490.18-149490.111" + wire $eq$libresoc.v:149490$7443_Y + attribute \src "libresoc.v:149494.18-149494.121" + wire $eq$libresoc.v:149494$7447_Y + attribute \src "libresoc.v:149495.18-149495.114" + wire $eq$libresoc.v:149495$7448_Y + attribute \src "libresoc.v:149460.18-149460.95" + wire width 64 $extend$libresoc.v:149460$7409_Y attribute \src "libresoc.v:149461.18-149461.95" - wire width 64 $extend$libresoc.v:149461$7409_Y - attribute \src "libresoc.v:149462.18-149462.95" - wire width 64 $extend$libresoc.v:149462$7411_Y - attribute \src "libresoc.v:149473.18-149473.100" - wire width 64 $extend$libresoc.v:149473$7423_Y - attribute \src "libresoc.v:149488.18-149488.109" - wire width 65 $extend$libresoc.v:149488$7439_Y - attribute \src "libresoc.v:149464.18-149464.121" - wire $gt$libresoc.v:149464$7414_Y - attribute \src "libresoc.v:149466.18-149466.99" - wire $gt$libresoc.v:149466$7416_Y + wire width 64 $extend$libresoc.v:149461$7411_Y + attribute \src "libresoc.v:149472.18-149472.100" + wire width 64 $extend$libresoc.v:149472$7423_Y + attribute \src "libresoc.v:149487.18-149487.109" + wire width 65 $extend$libresoc.v:149487$7439_Y attribute \src "libresoc.v:149463.18-149463.121" - wire $lt$libresoc.v:149463$7413_Y + wire $gt$libresoc.v:149463$7414_Y attribute \src "libresoc.v:149465.18-149465.99" - wire $lt$libresoc.v:149465$7415_Y + wire $gt$libresoc.v:149465$7416_Y + attribute \src "libresoc.v:149462.18-149462.121" + wire $lt$libresoc.v:149462$7413_Y + attribute \src "libresoc.v:149464.18-149464.99" + wire $lt$libresoc.v:149464$7415_Y + attribute \src "libresoc.v:149492.18-149492.112" + wire $not$libresoc.v:149492$7445_Y attribute \src "libresoc.v:149493.18-149493.112" - wire $not$libresoc.v:149493$7445_Y - attribute \src "libresoc.v:149494.18-149494.112" - wire $not$libresoc.v:149494$7446_Y - attribute \src "libresoc.v:149471.18-149471.106" - wire $or$libresoc.v:149471$7421_Y + wire $not$libresoc.v:149493$7446_Y + attribute \src "libresoc.v:149470.18-149470.106" + wire $or$libresoc.v:149470$7421_Y + attribute \src "libresoc.v:149460.18-149460.95" + wire width 64 $pos$libresoc.v:149460$7410_Y attribute \src "libresoc.v:149461.18-149461.95" - wire width 64 $pos$libresoc.v:149461$7410_Y - attribute \src "libresoc.v:149462.18-149462.95" - wire width 64 $pos$libresoc.v:149462$7412_Y - attribute \src "libresoc.v:149473.18-149473.100" - wire width 64 $pos$libresoc.v:149473$7424_Y - attribute \src "libresoc.v:149488.18-149488.109" - wire width 65 $pos$libresoc.v:149488$7440_Y - attribute \src "libresoc.v:149469.18-149469.100" - wire $reduce_or$libresoc.v:149469$7419_Y - attribute \src "libresoc.v:149470.18-149470.113" - wire $reduce_or$libresoc.v:149470$7420_Y - attribute \src "libresoc.v:149477.18-149477.91" - wire $reduce_or$libresoc.v:149477$7428_Y - attribute \src "libresoc.v:149479.18-149479.91" - wire $reduce_or$libresoc.v:149479$7430_Y - attribute \src "libresoc.v:149481.18-149481.91" - wire $reduce_or$libresoc.v:149481$7432_Y - attribute \src "libresoc.v:149483.18-149483.91" - wire $reduce_or$libresoc.v:149483$7434_Y - attribute \src "libresoc.v:149485.18-149485.91" - wire $reduce_or$libresoc.v:149485$7436_Y - attribute \src "libresoc.v:149487.18-149487.91" - wire $reduce_or$libresoc.v:149487$7438_Y - attribute \src "libresoc.v:149472.18-149472.120" - wire width 20 $sshl$libresoc.v:149472$7422_Y + wire width 64 $pos$libresoc.v:149461$7412_Y + attribute \src "libresoc.v:149472.18-149472.100" + wire width 64 $pos$libresoc.v:149472$7424_Y + attribute \src "libresoc.v:149487.18-149487.109" + wire width 65 $pos$libresoc.v:149487$7440_Y + attribute \src "libresoc.v:149468.18-149468.100" + wire $reduce_or$libresoc.v:149468$7419_Y + attribute \src "libresoc.v:149469.18-149469.113" + wire $reduce_or$libresoc.v:149469$7420_Y + attribute \src "libresoc.v:149476.18-149476.91" + wire $reduce_or$libresoc.v:149476$7428_Y + attribute \src "libresoc.v:149478.18-149478.91" + wire $reduce_or$libresoc.v:149478$7430_Y + attribute \src "libresoc.v:149480.18-149480.91" + wire $reduce_or$libresoc.v:149480$7432_Y + attribute \src "libresoc.v:149482.18-149482.91" + wire $reduce_or$libresoc.v:149482$7434_Y + attribute \src "libresoc.v:149484.18-149484.91" + wire $reduce_or$libresoc.v:149484$7436_Y + attribute \src "libresoc.v:149486.18-149486.91" + wire $reduce_or$libresoc.v:149486$7438_Y + attribute \src "libresoc.v:149471.18-149471.120" + wire width 20 $sshl$libresoc.v:149471$7422_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" wire width 64 \$13 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" @@ -311510,7 +308320,7 @@ module \main$38 wire \gt_s attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" wire \gt_u - attribute \src "libresoc.v:149086.7-149086.15" + attribute \src "libresoc.v:149085.7-149085.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" wire \lt_s @@ -311775,7 +308585,7 @@ module \main$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \trapexc_$signal$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" - cell $add $add$libresoc.v:149474$7425 + cell $add $add$libresoc.v:149473$7425 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -311783,10 +308593,10 @@ module \main$38 parameter \Y_WIDTH 65 connect \A \trap_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:149474$7425_Y + connect \Y $add$libresoc.v:149473$7425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $and $and$libresoc.v:149468$7418 + cell $and $and$libresoc.v:149467$7418 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -311794,10 +308604,10 @@ module \main$38 parameter \Y_WIDTH 5 connect \A \trap_bits connect \B \to - connect \Y $and$libresoc.v:149468$7418_Y + connect \Y $and$libresoc.v:149467$7418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" - cell $and $and$libresoc.v:149476$7427 + cell $and $and$libresoc.v:149475$7427 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311805,10 +308615,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 2'10 - connect \Y $and$libresoc.v:149476$7427_Y + connect \Y $and$libresoc.v:149475$7427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" - cell $and $and$libresoc.v:149478$7429 + cell $and $and$libresoc.v:149477$7429 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311816,10 +308626,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 1'1 - connect \Y $and$libresoc.v:149478$7429_Y + connect \Y $and$libresoc.v:149477$7429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" - cell $and $and$libresoc.v:149480$7431 + cell $and $and$libresoc.v:149479$7431 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311827,10 +308637,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 4'1000 - connect \Y $and$libresoc.v:149480$7431_Y + connect \Y $and$libresoc.v:149479$7431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:149482$7433 + cell $and $and$libresoc.v:149481$7433 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311838,10 +308648,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 - connect \Y $and$libresoc.v:149482$7433_Y + connect \Y $and$libresoc.v:149481$7433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" - cell $and $and$libresoc.v:149484$7435 + cell $and $and$libresoc.v:149483$7435 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311849,10 +308659,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 8'10000000 - connect \Y $and$libresoc.v:149484$7435_Y + connect \Y $and$libresoc.v:149483$7435_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:149486$7437 + cell $and $and$libresoc.v:149485$7437 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311860,10 +308670,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 - connect \Y $and$libresoc.v:149486$7437_Y + connect \Y $and$libresoc.v:149485$7437_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $and $and$libresoc.v:149492$7444 + cell $and $and$libresoc.v:149491$7444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311871,10 +308681,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$79 connect \B \$81 - connect \Y $and$libresoc.v:149492$7444_Y + connect \Y $and$libresoc.v:149491$7444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $and $and$libresoc.v:149497$7449 + cell $and $and$libresoc.v:149496$7449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311882,10 +308692,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$89 connect \B \$91 - connect \Y $and$libresoc.v:149497$7449_Y + connect \Y $and$libresoc.v:149496$7449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" - cell $eq $eq$libresoc.v:149467$7417 + cell $eq $eq$libresoc.v:149466$7417 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -311893,10 +308703,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $eq$libresoc.v:149467$7417_Y + connect \Y $eq$libresoc.v:149466$7417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" - cell $eq $eq$libresoc.v:149475$7426 + cell $eq $eq$libresoc.v:149474$7426 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311904,10 +308714,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__traptype connect \B 1'0 - connect \Y $eq$libresoc.v:149475$7426_Y + connect \Y $eq$libresoc.v:149474$7426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" - cell $eq $eq$libresoc.v:149489$7441 + cell $eq $eq$libresoc.v:149488$7441 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -311915,10 +308725,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__insn_type connect \B 7'1001000 - connect \Y $eq$libresoc.v:149489$7441_Y + connect \Y $eq$libresoc.v:149488$7441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" - cell $eq $eq$libresoc.v:149490$7442 + cell $eq $eq$libresoc.v:149489$7442 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -311926,10 +308736,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:149490$7442_Y + connect \Y $eq$libresoc.v:149489$7442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $eq $eq$libresoc.v:149491$7443 + cell $eq $eq$libresoc.v:149490$7443 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -311937,10 +308747,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \ra [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:149491$7443_Y + connect \Y $eq$libresoc.v:149490$7443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - cell $eq $eq$libresoc.v:149495$7447 + cell $eq $eq$libresoc.v:149494$7447 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -311948,10 +308758,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:149495$7447_Y + connect \Y $eq$libresoc.v:149494$7447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $eq $eq$libresoc.v:149496$7448 + cell $eq $eq$libresoc.v:149495$7448 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -311959,42 +308769,42 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \fast2 [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:149496$7448_Y + connect \Y $eq$libresoc.v:149495$7448_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:149461$7409 + cell $pos $extend$libresoc.v:149460$7409 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \ra [31:0] - connect \Y $extend$libresoc.v:149461$7409_Y + connect \Y $extend$libresoc.v:149460$7409_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:149462$7411 + cell $pos $extend$libresoc.v:149461$7411 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \rb [31:0] - connect \Y $extend$libresoc.v:149462$7411_Y + connect \Y $extend$libresoc.v:149461$7411_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $extend$libresoc.v:149473$7423 + cell $pos $extend$libresoc.v:149472$7423 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \Y_WIDTH 64 connect \A \$36 - connect \Y $extend$libresoc.v:149473$7423_Y + connect \Y $extend$libresoc.v:149472$7423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:149488$7439 + cell $pos $extend$libresoc.v:149487$7439 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \trap_op__msr - connect \Y $extend$libresoc.v:149488$7439_Y + connect \Y $extend$libresoc.v:149487$7439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" - cell $gt $gt$libresoc.v:149464$7414 + cell $gt $gt$libresoc.v:149463$7414 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -312002,10 +308812,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $gt$libresoc.v:149464$7414_Y + connect \Y $gt$libresoc.v:149463$7414_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" - cell $gt $gt$libresoc.v:149466$7416 + cell $gt $gt$libresoc.v:149465$7416 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -312013,10 +308823,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $gt$libresoc.v:149466$7416_Y + connect \Y $gt$libresoc.v:149465$7416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" - cell $lt $lt$libresoc.v:149463$7413 + cell $lt $lt$libresoc.v:149462$7413 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -312024,10 +308834,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $lt$libresoc.v:149463$7413_Y + connect \Y $lt$libresoc.v:149462$7413_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" - cell $lt $lt$libresoc.v:149465$7415 + cell $lt $lt$libresoc.v:149464$7415 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -312035,26 +308845,26 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $lt$libresoc.v:149465$7415_Y + connect \Y $lt$libresoc.v:149464$7415_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - cell $not $not$libresoc.v:149493$7445 + cell $not $not$libresoc.v:149492$7445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__msr [60] - connect \Y $not$libresoc.v:149493$7445_Y + connect \Y $not$libresoc.v:149492$7445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - cell $not $not$libresoc.v:149494$7446 + cell $not $not$libresoc.v:149493$7446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__insn [9] - connect \Y $not$libresoc.v:149494$7446_Y + connect \Y $not$libresoc.v:149493$7446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $or $or$libresoc.v:149471$7421 + cell $or $or$libresoc.v:149470$7421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -312062,106 +308872,106 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$27 connect \B \$31 - connect \Y $or$libresoc.v:149471$7421_Y + connect \Y $or$libresoc.v:149470$7421_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:149461$7410 + cell $pos $pos$libresoc.v:149460$7410 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:149461$7409_Y - connect \Y $pos$libresoc.v:149461$7410_Y + connect \A $extend$libresoc.v:149460$7409_Y + connect \Y $pos$libresoc.v:149460$7410_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:149462$7412 + cell $pos $pos$libresoc.v:149461$7412 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:149462$7411_Y - connect \Y $pos$libresoc.v:149462$7412_Y + connect \A $extend$libresoc.v:149461$7411_Y + connect \Y $pos$libresoc.v:149461$7412_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $pos$libresoc.v:149473$7424 + cell $pos $pos$libresoc.v:149472$7424 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:149473$7423_Y - connect \Y $pos$libresoc.v:149473$7424_Y + connect \A $extend$libresoc.v:149472$7423_Y + connect \Y $pos$libresoc.v:149472$7424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:149488$7440 + cell $pos $pos$libresoc.v:149487$7440 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:149488$7439_Y - connect \Y $pos$libresoc.v:149488$7440_Y + connect \A $extend$libresoc.v:149487$7439_Y + connect \Y $pos$libresoc.v:149487$7440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:149469$7419 + cell $reduce_or $reduce_or$libresoc.v:149468$7419 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $reduce_or$libresoc.v:149469$7419_Y + connect \Y $reduce_or$libresoc.v:149468$7419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:149470$7420 + cell $reduce_or $reduce_or$libresoc.v:149469$7420 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \trap_op__traptype - connect \Y $reduce_or$libresoc.v:149470$7420_Y + connect \Y $reduce_or$libresoc.v:149469$7420_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149477$7428 + cell $reduce_or $reduce_or$libresoc.v:149476$7428 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$45 - connect \Y $reduce_or$libresoc.v:149477$7428_Y + connect \Y $reduce_or$libresoc.v:149476$7428_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149479$7430 + cell $reduce_or $reduce_or$libresoc.v:149478$7430 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$49 - connect \Y $reduce_or$libresoc.v:149479$7430_Y + connect \Y $reduce_or$libresoc.v:149478$7430_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149481$7432 + cell $reduce_or $reduce_or$libresoc.v:149480$7432 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$53 - connect \Y $reduce_or$libresoc.v:149481$7432_Y + connect \Y $reduce_or$libresoc.v:149480$7432_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149483$7434 + cell $reduce_or $reduce_or$libresoc.v:149482$7434 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$57 - connect \Y $reduce_or$libresoc.v:149483$7434_Y + connect \Y $reduce_or$libresoc.v:149482$7434_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149485$7436 + cell $reduce_or $reduce_or$libresoc.v:149484$7436 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $reduce_or$libresoc.v:149485$7436_Y + connect \Y $reduce_or$libresoc.v:149484$7436_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149487$7438 + cell $reduce_or $reduce_or$libresoc.v:149486$7438 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$72 - connect \Y $reduce_or$libresoc.v:149487$7438_Y + connect \Y $reduce_or$libresoc.v:149486$7438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $sshl $sshl$libresoc.v:149472$7422 + cell $sshl $sshl$libresoc.v:149471$7422 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -312169,23 +308979,23 @@ module \main$38 parameter \Y_WIDTH 20 connect \A \trap_op__trapaddr connect \B 3'100 - connect \Y $sshl$libresoc.v:149472$7422_Y + connect \Y $sshl$libresoc.v:149471$7422_Y end - attribute \src "libresoc.v:149086.7-149086.20" - process $proc$libresoc.v:149086$7510 + attribute \src "libresoc.v:149085.7-149085.20" + process $proc$libresoc.v:149085$7510 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:149498.3-149509.6" - process $proc$libresoc.v:149498$7450 + attribute \src "libresoc.v:149497.3-149508.6" + process $proc$libresoc.v:149497$7450 assign { } { } assign $0\a_s[63:0] $1\a_s[63:0] - attribute \src "libresoc.v:149499.5-149499.29" + attribute \src "libresoc.v:149498.5-149498.29" switch \initial - attribute \src "libresoc.v:149499.9-149499.17" + attribute \src "libresoc.v:149498.9-149498.17" case 1'1 case end @@ -312203,14 +309013,14 @@ module \main$38 sync always update \a_s $0\a_s[63:0] end - attribute \src "libresoc.v:149510.3-149541.6" - process $proc$libresoc.v:149510$7451 + attribute \src "libresoc.v:149509.3-149540.6" + process $proc$libresoc.v:149509$7451 assign { } { } assign { } { } assign $0\nia[63:0] $1\nia[63:0] - attribute \src "libresoc.v:149511.5-149511.29" + attribute \src "libresoc.v:149510.5-149510.29" switch \initial - attribute \src "libresoc.v:149511.9-149511.17" + attribute \src "libresoc.v:149510.9-149510.17" case 1'1 case end @@ -312249,14 +309059,14 @@ module \main$38 sync always update \nia $0\nia[63:0] end - attribute \src "libresoc.v:149542.3-149573.6" - process $proc$libresoc.v:149542$7452 + attribute \src "libresoc.v:149541.3-149572.6" + process $proc$libresoc.v:149541$7452 assign { } { } assign { } { } assign $0\nia_ok[0:0] $1\nia_ok[0:0] - attribute \src "libresoc.v:149543.5-149543.29" + attribute \src "libresoc.v:149542.5-149542.29" switch \initial - attribute \src "libresoc.v:149543.9-149543.17" + attribute \src "libresoc.v:149542.9-149542.17" case 1'1 case end @@ -312295,14 +309105,14 @@ module \main$38 sync always update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:149574.3-149605.6" - process $proc$libresoc.v:149574$7453 + attribute \src "libresoc.v:149573.3-149604.6" + process $proc$libresoc.v:149573$7453 assign { } { } assign { } { } assign $0\fast1$11[63:0]$7454 $1\fast1$11[63:0]$7455 - attribute \src "libresoc.v:149575.5-149575.29" + attribute \src "libresoc.v:149574.5-149574.29" switch \initial - attribute \src "libresoc.v:149575.9-149575.17" + attribute \src "libresoc.v:149574.9-149574.17" case 1'1 case end @@ -312340,14 +309150,14 @@ module \main$38 sync always update \fast1$11 $0\fast1$11[63:0]$7454 end - attribute \src "libresoc.v:149606.3-149637.6" - process $proc$libresoc.v:149606$7457 + attribute \src "libresoc.v:149605.3-149636.6" + process $proc$libresoc.v:149605$7457 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:149607.5-149607.29" + attribute \src "libresoc.v:149606.5-149606.29" switch \initial - attribute \src "libresoc.v:149607.9-149607.17" + attribute \src "libresoc.v:149606.9-149606.17" case 1'1 case end @@ -312385,14 +309195,14 @@ module \main$38 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:149638.3-149720.6" - process $proc$libresoc.v:149638$7458 + attribute \src "libresoc.v:149637.3-149719.6" + process $proc$libresoc.v:149637$7458 assign { } { } assign { } { } assign $0\fast2$12[63:0]$7459 $1\fast2$12[63:0]$7460 - attribute \src "libresoc.v:149639.5-149639.29" + attribute \src "libresoc.v:149638.5-149638.29" switch \initial - attribute \src "libresoc.v:149639.9-149639.17" + attribute \src "libresoc.v:149638.9-149638.17" case 1'1 case end @@ -312505,14 +309315,14 @@ module \main$38 sync always update \fast2$12 $0\fast2$12[63:0]$7459 end - attribute \src "libresoc.v:149721.3-149752.6" - process $proc$libresoc.v:149721$7470 + attribute \src "libresoc.v:149720.3-149751.6" + process $proc$libresoc.v:149720$7470 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:149722.5-149722.29" + attribute \src "libresoc.v:149721.5-149721.29" switch \initial - attribute \src "libresoc.v:149722.9-149722.17" + attribute \src "libresoc.v:149721.9-149721.17" case 1'1 case end @@ -312550,8 +309360,8 @@ module \main$38 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:149753.3-149780.6" - process $proc$libresoc.v:149753$7471 + attribute \src "libresoc.v:149752.3-149779.6" + process $proc$libresoc.v:149752$7471 assign { } { } assign { } { } assign { } { } @@ -312576,9 +309386,9 @@ module \main$38 assign $0\trapexc_$signal$68[0:0]$7477 $1\trapexc_$signal$68[0:0]$7485 assign $0\trapexc_$signal$69[0:0]$7478 $1\trapexc_$signal$69[0:0]$7486 assign $0\trapexc_$signal$70[0:0]$7479 $1\trapexc_$signal$70[0:0]$7487 - attribute \src "libresoc.v:149754.5-149754.29" + attribute \src "libresoc.v:149753.5-149753.29" switch \initial - attribute \src "libresoc.v:149754.9-149754.17" + attribute \src "libresoc.v:149753.9-149753.17" case 1'1 case end @@ -312675,13 +309485,13 @@ module \main$38 update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7478 update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7479 end - attribute \src "libresoc.v:149781.3-149792.6" - process $proc$libresoc.v:149781$7504 + attribute \src "libresoc.v:149780.3-149791.6" + process $proc$libresoc.v:149780$7504 assign { } { } assign $0\b_s[63:0] $1\b_s[63:0] - attribute \src "libresoc.v:149782.5-149782.29" + attribute \src "libresoc.v:149781.5-149781.29" switch \initial - attribute \src "libresoc.v:149782.9-149782.17" + attribute \src "libresoc.v:149781.9-149781.17" case 1'1 case end @@ -312699,17 +309509,17 @@ module \main$38 sync always update \b_s $0\b_s[63:0] end - attribute \src "libresoc.v:149793.3-149961.6" - process $proc$libresoc.v:149793$7505 + attribute \src "libresoc.v:149792.3-149960.6" + process $proc$libresoc.v:149792$7505 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\msr[63:0] $1\msr[63:0] assign $0\msr_ok[0:0] $1\msr_ok[0:0] - attribute \src "libresoc.v:149794.5-149794.29" + attribute \src "libresoc.v:149793.5-149793.29" switch \initial - attribute \src "libresoc.v:149794.9-149794.17" + attribute \src "libresoc.v:149793.9-149793.17" case 1'1 case end @@ -312923,14 +309733,14 @@ module \main$38 update \msr $0\msr[63:0] update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:149962.3-149980.6" - process $proc$libresoc.v:149962$7506 + attribute \src "libresoc.v:149961.3-149979.6" + process $proc$libresoc.v:149961$7506 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:149963.5-149963.29" + attribute \src "libresoc.v:149962.5-149962.29" switch \initial - attribute \src "libresoc.v:149963.9-149963.17" + attribute \src "libresoc.v:149962.9-149962.17" case 1'1 case end @@ -312952,14 +309762,14 @@ module \main$38 sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:149981.3-149999.6" - process $proc$libresoc.v:149981$7507 + attribute \src "libresoc.v:149980.3-149998.6" + process $proc$libresoc.v:149980$7507 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:149982.5-149982.29" + attribute \src "libresoc.v:149981.5-149981.29" switch \initial - attribute \src "libresoc.v:149982.9-149982.17" + attribute \src "libresoc.v:149981.9-149981.17" case 1'1 case end @@ -312981,13 +309791,13 @@ module \main$38 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:150000.3-150011.6" - process $proc$libresoc.v:150000$7508 + attribute \src "libresoc.v:149999.3-150010.6" + process $proc$libresoc.v:149999$7508 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:150001.5-150001.29" + attribute \src "libresoc.v:150000.5-150000.29" switch \initial - attribute \src "libresoc.v:150001.9-150001.17" + attribute \src "libresoc.v:150000.9-150000.17" case 1'1 case end @@ -313005,13 +309815,13 @@ module \main$38 sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:150012.3-150023.6" - process $proc$libresoc.v:150012$7509 + attribute \src "libresoc.v:150011.3-150022.6" + process $proc$libresoc.v:150011$7509 assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:150013.5-150013.29" + attribute \src "libresoc.v:150012.5-150012.29" switch \initial - attribute \src "libresoc.v:150013.9-150013.17" + attribute \src "libresoc.v:150012.9-150012.17" case 1'1 case end @@ -313029,43 +309839,43 @@ module \main$38 sync always update \b $0\b[63:0] end - connect \$13 $pos$libresoc.v:149461$7410_Y - connect \$15 $pos$libresoc.v:149462$7412_Y - connect \$17 $lt$libresoc.v:149463$7413_Y - connect \$19 $gt$libresoc.v:149464$7414_Y - connect \$21 $lt$libresoc.v:149465$7415_Y - connect \$23 $gt$libresoc.v:149466$7416_Y - connect \$25 $eq$libresoc.v:149467$7417_Y - connect \$28 $and$libresoc.v:149468$7418_Y - connect \$27 $reduce_or$libresoc.v:149469$7419_Y - connect \$31 $reduce_or$libresoc.v:149470$7420_Y - connect \$33 $or$libresoc.v:149471$7421_Y - connect \$36 $sshl$libresoc.v:149472$7422_Y - connect \$35 $pos$libresoc.v:149473$7424_Y - connect \$40 $add$libresoc.v:149474$7425_Y - connect \$42 $eq$libresoc.v:149475$7426_Y - connect \$45 $and$libresoc.v:149476$7427_Y - connect \$44 $reduce_or$libresoc.v:149477$7428_Y - connect \$49 $and$libresoc.v:149478$7429_Y - connect \$48 $reduce_or$libresoc.v:149479$7430_Y - connect \$53 $and$libresoc.v:149480$7431_Y - connect \$52 $reduce_or$libresoc.v:149481$7432_Y - connect \$57 $and$libresoc.v:149482$7433_Y - connect \$56 $reduce_or$libresoc.v:149483$7434_Y - connect \$64 $and$libresoc.v:149484$7435_Y - connect \$63 $reduce_or$libresoc.v:149485$7436_Y - connect \$72 $and$libresoc.v:149486$7437_Y - connect \$71 $reduce_or$libresoc.v:149487$7438_Y - connect \$75 $pos$libresoc.v:149488$7440_Y - connect \$77 $eq$libresoc.v:149489$7441_Y - connect \$79 $eq$libresoc.v:149490$7442_Y - connect \$81 $eq$libresoc.v:149491$7443_Y - connect \$83 $and$libresoc.v:149492$7444_Y - connect \$85 $not$libresoc.v:149493$7445_Y - connect \$87 $not$libresoc.v:149494$7446_Y - connect \$89 $eq$libresoc.v:149495$7447_Y - connect \$91 $eq$libresoc.v:149496$7448_Y - connect \$93 $and$libresoc.v:149497$7449_Y + connect \$13 $pos$libresoc.v:149460$7410_Y + connect \$15 $pos$libresoc.v:149461$7412_Y + connect \$17 $lt$libresoc.v:149462$7413_Y + connect \$19 $gt$libresoc.v:149463$7414_Y + connect \$21 $lt$libresoc.v:149464$7415_Y + connect \$23 $gt$libresoc.v:149465$7416_Y + connect \$25 $eq$libresoc.v:149466$7417_Y + connect \$28 $and$libresoc.v:149467$7418_Y + connect \$27 $reduce_or$libresoc.v:149468$7419_Y + connect \$31 $reduce_or$libresoc.v:149469$7420_Y + connect \$33 $or$libresoc.v:149470$7421_Y + connect \$36 $sshl$libresoc.v:149471$7422_Y + connect \$35 $pos$libresoc.v:149472$7424_Y + connect \$40 $add$libresoc.v:149473$7425_Y + connect \$42 $eq$libresoc.v:149474$7426_Y + connect \$45 $and$libresoc.v:149475$7427_Y + connect \$44 $reduce_or$libresoc.v:149476$7428_Y + connect \$49 $and$libresoc.v:149477$7429_Y + connect \$48 $reduce_or$libresoc.v:149478$7430_Y + connect \$53 $and$libresoc.v:149479$7431_Y + connect \$52 $reduce_or$libresoc.v:149480$7432_Y + connect \$57 $and$libresoc.v:149481$7433_Y + connect \$56 $reduce_or$libresoc.v:149482$7434_Y + connect \$64 $and$libresoc.v:149483$7435_Y + connect \$63 $reduce_or$libresoc.v:149484$7436_Y + connect \$72 $and$libresoc.v:149485$7437_Y + connect \$71 $reduce_or$libresoc.v:149486$7438_Y + connect \$75 $pos$libresoc.v:149487$7440_Y + connect \$77 $eq$libresoc.v:149488$7441_Y + connect \$79 $eq$libresoc.v:149489$7442_Y + connect \$81 $eq$libresoc.v:149490$7443_Y + connect \$83 $and$libresoc.v:149491$7444_Y + connect \$85 $not$libresoc.v:149492$7445_Y + connect \$87 $not$libresoc.v:149493$7446_Y + connect \$89 $eq$libresoc.v:149494$7447_Y + connect \$91 $eq$libresoc.v:149495$7448_Y + connect \$93 $and$libresoc.v:149496$7449_Y connect \$39 \$40 connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid @@ -313078,239 +309888,239 @@ module \main$38 connect \lt_s \$17 connect \to \trap_op__insn [25:21] end -attribute \src "libresoc.v:150039.1-150788.10" +attribute \src "libresoc.v:150038.1-150787.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" attribute \generator "nMigen" module \main$51 - attribute \src "libresoc.v:150755.3-150765.6" + attribute \src "libresoc.v:150754.3-150764.6" wire width 32 $0\a32[31:0] - attribute \src "libresoc.v:150700.3-150710.6" + attribute \src "libresoc.v:150699.3-150709.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:150678.3-150688.6" + attribute \src "libresoc.v:150677.3-150687.6" wire width 64 $0\bpermd_rb[63:0] - attribute \src "libresoc.v:150667.3-150677.6" + attribute \src "libresoc.v:150666.3-150676.6" wire width 64 $0\bpermd_rs[63:0] - attribute \src "libresoc.v:150656.3-150666.6" + attribute \src "libresoc.v:150655.3-150665.6" wire width 64 $0\clz_sig_in[63:0] - attribute \src "libresoc.v:150766.3-150784.6" + attribute \src "libresoc.v:150765.3-150783.6" wire width 64 $0\cntz_i[63:0] - attribute \src "libresoc.v:150744.3-150754.6" + attribute \src "libresoc.v:150743.3-150753.6" wire $0\count_right[0:0] - attribute \src "libresoc.v:150040.7-150040.20" + attribute \src "libresoc.v:150039.7-150039.20" wire $0\initial[0:0] - attribute \src "libresoc.v:150601.3-150655.6" + attribute \src "libresoc.v:150600.3-150654.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:150601.3-150655.6" + attribute \src "libresoc.v:150600.3-150654.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:150722.3-150732.6" + attribute \src "libresoc.v:150721.3-150731.6" wire $0\par0[0:0] - attribute \src "libresoc.v:150733.3-150743.6" + attribute \src "libresoc.v:150732.3-150742.6" wire $0\par1[0:0] - attribute \src "libresoc.v:150689.3-150699.6" + attribute \src "libresoc.v:150688.3-150698.6" wire width 64 $0\popcount_a[63:0] - attribute \src "libresoc.v:150711.3-150721.6" + attribute \src "libresoc.v:150710.3-150720.6" wire width 64 $0\popcount_data_len[63:0] - attribute \src "libresoc.v:150755.3-150765.6" + attribute \src "libresoc.v:150754.3-150764.6" wire width 32 $1\a32[31:0] - attribute \src "libresoc.v:150700.3-150710.6" + attribute \src "libresoc.v:150699.3-150709.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:150678.3-150688.6" + attribute \src "libresoc.v:150677.3-150687.6" wire width 64 $1\bpermd_rb[63:0] - attribute \src "libresoc.v:150667.3-150677.6" + attribute \src "libresoc.v:150666.3-150676.6" wire width 64 $1\bpermd_rs[63:0] - attribute \src "libresoc.v:150656.3-150666.6" + attribute \src "libresoc.v:150655.3-150665.6" wire width 64 $1\clz_sig_in[63:0] - attribute \src "libresoc.v:150766.3-150784.6" + attribute \src "libresoc.v:150765.3-150783.6" wire width 64 $1\cntz_i[63:0] - attribute \src "libresoc.v:150744.3-150754.6" + attribute \src "libresoc.v:150743.3-150753.6" wire $1\count_right[0:0] - attribute \src "libresoc.v:150601.3-150655.6" + attribute \src "libresoc.v:150600.3-150654.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:150601.3-150655.6" + attribute \src "libresoc.v:150600.3-150654.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:150722.3-150732.6" + attribute \src "libresoc.v:150721.3-150731.6" wire $1\par0[0:0] - attribute \src "libresoc.v:150733.3-150743.6" + attribute \src "libresoc.v:150732.3-150742.6" wire $1\par1[0:0] - attribute \src "libresoc.v:150689.3-150699.6" + attribute \src "libresoc.v:150688.3-150698.6" wire width 64 $1\popcount_a[63:0] - attribute \src "libresoc.v:150711.3-150721.6" + attribute \src "libresoc.v:150710.3-150720.6" wire width 64 $1\popcount_data_len[63:0] - attribute \src "libresoc.v:150766.3-150784.6" + attribute \src "libresoc.v:150765.3-150783.6" wire width 64 $2\cntz_i[63:0] - attribute \src "libresoc.v:150601.3-150655.6" + attribute \src "libresoc.v:150600.3-150654.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:150548.18-150548.103" - wire width 64 $and$libresoc.v:150548$7557_Y - attribute \src "libresoc.v:150507.18-150507.118" - wire $eq$libresoc.v:150507$7511_Y + attribute \src "libresoc.v:150547.18-150547.103" + wire width 64 $and$libresoc.v:150547$7557_Y + attribute \src "libresoc.v:150506.18-150506.118" + wire $eq$libresoc.v:150506$7511_Y + attribute \src "libresoc.v:150507.19-150507.119" + wire $eq$libresoc.v:150507$7512_Y attribute \src "libresoc.v:150508.19-150508.119" - wire $eq$libresoc.v:150508$7512_Y + wire $eq$libresoc.v:150508$7513_Y attribute \src "libresoc.v:150509.19-150509.119" - wire $eq$libresoc.v:150509$7513_Y + wire $eq$libresoc.v:150509$7514_Y attribute \src "libresoc.v:150510.19-150510.119" - wire $eq$libresoc.v:150510$7514_Y + wire $eq$libresoc.v:150510$7515_Y attribute \src "libresoc.v:150511.19-150511.119" - wire $eq$libresoc.v:150511$7515_Y + wire $eq$libresoc.v:150511$7516_Y attribute \src "libresoc.v:150512.19-150512.119" - wire $eq$libresoc.v:150512$7516_Y + wire $eq$libresoc.v:150512$7517_Y attribute \src "libresoc.v:150513.19-150513.119" - wire $eq$libresoc.v:150513$7517_Y + wire $eq$libresoc.v:150513$7518_Y attribute \src "libresoc.v:150514.19-150514.119" - wire $eq$libresoc.v:150514$7518_Y + wire $eq$libresoc.v:150514$7519_Y attribute \src "libresoc.v:150515.19-150515.119" - wire $eq$libresoc.v:150515$7519_Y + wire $eq$libresoc.v:150515$7520_Y attribute \src "libresoc.v:150516.19-150516.119" - wire $eq$libresoc.v:150516$7520_Y + wire $eq$libresoc.v:150516$7521_Y attribute \src "libresoc.v:150517.19-150517.119" - wire $eq$libresoc.v:150517$7521_Y + wire $eq$libresoc.v:150517$7522_Y attribute \src "libresoc.v:150518.19-150518.119" - wire $eq$libresoc.v:150518$7522_Y + wire $eq$libresoc.v:150518$7523_Y attribute \src "libresoc.v:150519.19-150519.119" - wire $eq$libresoc.v:150519$7523_Y + wire $eq$libresoc.v:150519$7524_Y attribute \src "libresoc.v:150520.19-150520.119" - wire $eq$libresoc.v:150520$7524_Y + wire $eq$libresoc.v:150520$7525_Y attribute \src "libresoc.v:150521.19-150521.119" - wire $eq$libresoc.v:150521$7525_Y + wire $eq$libresoc.v:150521$7526_Y attribute \src "libresoc.v:150522.19-150522.119" - wire $eq$libresoc.v:150522$7526_Y + wire $eq$libresoc.v:150522$7527_Y attribute \src "libresoc.v:150523.19-150523.119" - wire $eq$libresoc.v:150523$7527_Y + wire $eq$libresoc.v:150523$7528_Y attribute \src "libresoc.v:150524.19-150524.119" - wire $eq$libresoc.v:150524$7528_Y + wire $eq$libresoc.v:150524$7529_Y attribute \src "libresoc.v:150525.19-150525.119" - wire $eq$libresoc.v:150525$7529_Y + wire $eq$libresoc.v:150525$7530_Y attribute \src "libresoc.v:150526.19-150526.119" - wire $eq$libresoc.v:150526$7530_Y + wire $eq$libresoc.v:150526$7531_Y attribute \src "libresoc.v:150527.19-150527.119" - wire $eq$libresoc.v:150527$7531_Y + wire $eq$libresoc.v:150527$7532_Y attribute \src "libresoc.v:150528.19-150528.119" - wire $eq$libresoc.v:150528$7532_Y + wire $eq$libresoc.v:150528$7533_Y attribute \src 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$eq$libresoc.v:150551$7560_Y + wire $eq$libresoc.v:150551$7561_Y attribute \src "libresoc.v:150552.18-150552.114" - wire $eq$libresoc.v:150552$7561_Y + wire $eq$libresoc.v:150552$7562_Y attribute \src "libresoc.v:150553.18-150553.114" - wire $eq$libresoc.v:150553$7562_Y + wire $eq$libresoc.v:150553$7563_Y attribute \src "libresoc.v:150554.18-150554.114" - wire $eq$libresoc.v:150554$7563_Y + wire $eq$libresoc.v:150554$7564_Y attribute \src "libresoc.v:150555.18-150555.114" - wire $eq$libresoc.v:150555$7564_Y + wire $eq$libresoc.v:150555$7565_Y attribute \src "libresoc.v:150556.18-150556.114" - wire $eq$libresoc.v:150556$7565_Y + wire $eq$libresoc.v:150556$7566_Y attribute \src "libresoc.v:150557.18-150557.114" - wire $eq$libresoc.v:150557$7566_Y - attribute \src "libresoc.v:150558.18-150558.114" - wire $eq$libresoc.v:150558$7567_Y + wire $eq$libresoc.v:150557$7567_Y + attribute \src "libresoc.v:150558.18-150558.116" + wire $eq$libresoc.v:150558$7568_Y attribute \src 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$eq$libresoc.v:150566$7576_Y attribute \src "libresoc.v:150567.18-150567.118" - wire $eq$libresoc.v:150567$7576_Y + wire $eq$libresoc.v:150567$7577_Y attribute \src "libresoc.v:150568.18-150568.118" - wire $eq$libresoc.v:150568$7577_Y + wire $eq$libresoc.v:150568$7578_Y attribute \src "libresoc.v:150569.18-150569.118" - wire $eq$libresoc.v:150569$7578_Y + wire $eq$libresoc.v:150569$7579_Y attribute \src "libresoc.v:150570.18-150570.118" - wire $eq$libresoc.v:150570$7579_Y + wire $eq$libresoc.v:150570$7580_Y attribute \src "libresoc.v:150571.18-150571.118" - wire $eq$libresoc.v:150571$7580_Y + wire $eq$libresoc.v:150571$7581_Y attribute \src "libresoc.v:150572.18-150572.118" - wire $eq$libresoc.v:150572$7581_Y + wire $eq$libresoc.v:150572$7582_Y attribute \src "libresoc.v:150573.18-150573.118" - wire $eq$libresoc.v:150573$7582_Y + wire $eq$libresoc.v:150573$7583_Y attribute \src "libresoc.v:150574.18-150574.118" - wire $eq$libresoc.v:150574$7583_Y + wire $eq$libresoc.v:150574$7584_Y attribute \src "libresoc.v:150575.18-150575.118" - wire $eq$libresoc.v:150575$7584_Y + wire $eq$libresoc.v:150575$7585_Y attribute \src "libresoc.v:150576.18-150576.118" - wire $eq$libresoc.v:150576$7585_Y + wire $eq$libresoc.v:150576$7586_Y attribute \src "libresoc.v:150577.18-150577.118" - wire $eq$libresoc.v:150577$7586_Y + wire $eq$libresoc.v:150577$7587_Y attribute \src "libresoc.v:150578.18-150578.118" - wire $eq$libresoc.v:150578$7587_Y + wire $eq$libresoc.v:150578$7588_Y attribute \src "libresoc.v:150579.18-150579.118" - wire $eq$libresoc.v:150579$7588_Y + wire $eq$libresoc.v:150579$7589_Y attribute \src "libresoc.v:150580.18-150580.118" - wire $eq$libresoc.v:150580$7589_Y + wire $eq$libresoc.v:150580$7590_Y attribute \src "libresoc.v:150581.18-150581.118" - wire $eq$libresoc.v:150581$7590_Y + wire $eq$libresoc.v:150581$7591_Y attribute \src "libresoc.v:150582.18-150582.118" - wire $eq$libresoc.v:150582$7591_Y + wire $eq$libresoc.v:150582$7592_Y attribute \src "libresoc.v:150583.18-150583.118" - wire $eq$libresoc.v:150583$7592_Y + wire $eq$libresoc.v:150583$7593_Y attribute \src "libresoc.v:150584.18-150584.118" - wire $eq$libresoc.v:150584$7593_Y + wire $eq$libresoc.v:150584$7594_Y attribute \src "libresoc.v:150585.18-150585.118" - wire $eq$libresoc.v:150585$7594_Y - attribute \src "libresoc.v:150586.18-150586.118" - wire $eq$libresoc.v:150586$7595_Y - attribute \src "libresoc.v:150537.19-150537.104" - wire width 64 $extend$libresoc.v:150537$7541_Y - attribute \src "libresoc.v:150539.19-150539.93" - wire width 8 $extend$libresoc.v:150539$7544_Y - attribute \src "libresoc.v:150541.19-150541.105" - wire width 64 $extend$libresoc.v:150541$7547_Y - attribute \src "libresoc.v:150542.19-150542.118" - wire width 64 $extend$libresoc.v:150542$7549_Y - attribute \src "libresoc.v:150546.19-150546.105" - wire width 64 $extend$libresoc.v:150546$7554_Y + wire $eq$libresoc.v:150585$7595_Y + attribute \src "libresoc.v:150536.19-150536.104" + wire width 64 $extend$libresoc.v:150536$7541_Y + attribute \src "libresoc.v:150538.19-150538.93" + wire width 8 $extend$libresoc.v:150538$7544_Y + attribute \src "libresoc.v:150540.19-150540.105" + wire width 64 $extend$libresoc.v:150540$7547_Y + attribute \src "libresoc.v:150541.19-150541.118" + wire width 64 $extend$libresoc.v:150541$7549_Y + attribute \src "libresoc.v:150545.19-150545.105" + wire width 64 $extend$libresoc.v:150545$7554_Y + attribute \src "libresoc.v:150548.18-150548.103" + wire width 64 $or$libresoc.v:150548$7558_Y + attribute \src "libresoc.v:150536.19-150536.104" + wire width 64 $pos$libresoc.v:150536$7542_Y + attribute \src "libresoc.v:150538.19-150538.93" + wire width 8 $pos$libresoc.v:150538$7545_Y + attribute \src "libresoc.v:150540.19-150540.105" + wire width 64 $pos$libresoc.v:150540$7548_Y + attribute \src "libresoc.v:150541.19-150541.118" + wire width 64 $pos$libresoc.v:150541$7550_Y + attribute \src "libresoc.v:150545.19-150545.105" + wire width 64 $pos$libresoc.v:150545$7555_Y + attribute \src "libresoc.v:150542.19-150542.131" + wire $reduce_xor$libresoc.v:150542$7551_Y + attribute \src "libresoc.v:150543.19-150543.133" + wire $reduce_xor$libresoc.v:150543$7552_Y + attribute \src "libresoc.v:150537.19-150537.112" + wire width 8 $sub$libresoc.v:150537$7543_Y + attribute \src "libresoc.v:150539.19-150539.135" + wire width 8 $ternary$libresoc.v:150539$7546_Y + attribute \src "libresoc.v:150544.19-150544.398" + wire width 32 $ternary$libresoc.v:150544$7553_Y + attribute \src "libresoc.v:150546.19-150546.621" + wire width 64 $ternary$libresoc.v:150546$7556_Y + attribute \src "libresoc.v:150535.19-150535.108" + wire $xor$libresoc.v:150535$7540_Y attribute \src "libresoc.v:150549.18-150549.103" - wire width 64 $or$libresoc.v:150549$7558_Y - attribute \src "libresoc.v:150537.19-150537.104" - wire width 64 $pos$libresoc.v:150537$7542_Y - attribute \src "libresoc.v:150539.19-150539.93" - wire width 8 $pos$libresoc.v:150539$7545_Y - attribute \src "libresoc.v:150541.19-150541.105" - wire width 64 $pos$libresoc.v:150541$7548_Y - attribute \src "libresoc.v:150542.19-150542.118" - wire width 64 $pos$libresoc.v:150542$7550_Y - attribute \src "libresoc.v:150546.19-150546.105" - wire width 64 $pos$libresoc.v:150546$7555_Y - attribute \src "libresoc.v:150543.19-150543.131" - wire $reduce_xor$libresoc.v:150543$7551_Y - attribute \src "libresoc.v:150544.19-150544.133" - wire $reduce_xor$libresoc.v:150544$7552_Y - attribute \src "libresoc.v:150538.19-150538.112" - wire width 8 $sub$libresoc.v:150538$7543_Y - attribute \src "libresoc.v:150540.19-150540.135" - wire width 8 $ternary$libresoc.v:150540$7546_Y - attribute \src "libresoc.v:150545.19-150545.398" - wire width 32 $ternary$libresoc.v:150545$7553_Y - attribute \src "libresoc.v:150547.19-150547.621" - wire width 64 $ternary$libresoc.v:150547$7556_Y - attribute \src "libresoc.v:150536.19-150536.108" - wire $xor$libresoc.v:150536$7540_Y - attribute \src "libresoc.v:150550.18-150550.103" - wire width 64 $xor$libresoc.v:150550$7559_Y + wire width 64 $xor$libresoc.v:150549$7559_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" @@ -313489,7 +310299,7 @@ module \main$51 wire width 64 \cntz_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" wire \count_right - attribute \src "libresoc.v:150040.7-150040.15" + attribute \src "libresoc.v:150039.7-150039.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -313778,7 +310588,7 @@ module \main$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 43 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - cell $and $and$libresoc.v:150548$7557 + cell $and $and$libresoc.v:150547$7557 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -313786,10 +310596,10 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $and$libresoc.v:150548$7557_Y + connect \Y $and$libresoc.v:150547$7557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150507$7511 + cell $eq $eq$libresoc.v:150506$7511 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313797,10 +310607,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150507$7511_Y + connect \Y $eq$libresoc.v:150506$7511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150508$7512 + cell $eq $eq$libresoc.v:150507$7512 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313808,10 +310618,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150508$7512_Y + connect \Y $eq$libresoc.v:150507$7512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150509$7513 + cell $eq $eq$libresoc.v:150508$7513 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313819,10 +310629,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150509$7513_Y + connect \Y $eq$libresoc.v:150508$7513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150510$7514 + cell $eq $eq$libresoc.v:150509$7514 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313830,10 +310640,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150510$7514_Y + connect \Y $eq$libresoc.v:150509$7514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150511$7515 + cell $eq $eq$libresoc.v:150510$7515 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313841,10 +310651,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150511$7515_Y + connect \Y $eq$libresoc.v:150510$7515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150512$7516 + cell $eq $eq$libresoc.v:150511$7516 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313852,10 +310662,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150512$7516_Y + connect \Y $eq$libresoc.v:150511$7516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150513$7517 + cell $eq $eq$libresoc.v:150512$7517 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313863,10 +310673,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150513$7517_Y + connect \Y $eq$libresoc.v:150512$7517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150514$7518 + cell $eq $eq$libresoc.v:150513$7518 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313874,10 +310684,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150514$7518_Y + connect \Y $eq$libresoc.v:150513$7518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150515$7519 + cell $eq $eq$libresoc.v:150514$7519 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313885,10 +310695,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150515$7519_Y + connect \Y $eq$libresoc.v:150514$7519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150516$7520 + cell $eq $eq$libresoc.v:150515$7520 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313896,10 +310706,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150516$7520_Y + connect \Y $eq$libresoc.v:150515$7520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150517$7521 + cell $eq $eq$libresoc.v:150516$7521 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313907,10 +310717,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150517$7521_Y + connect \Y $eq$libresoc.v:150516$7521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150518$7522 + cell $eq $eq$libresoc.v:150517$7522 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313918,10 +310728,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150518$7522_Y + connect \Y $eq$libresoc.v:150517$7522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150519$7523 + cell $eq $eq$libresoc.v:150518$7523 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313929,10 +310739,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150519$7523_Y + connect \Y $eq$libresoc.v:150518$7523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150520$7524 + cell $eq $eq$libresoc.v:150519$7524 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313940,10 +310750,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150520$7524_Y + connect \Y $eq$libresoc.v:150519$7524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150521$7525 + cell $eq $eq$libresoc.v:150520$7525 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313951,10 +310761,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150521$7525_Y + connect \Y $eq$libresoc.v:150520$7525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150522$7526 + cell $eq $eq$libresoc.v:150521$7526 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313962,10 +310772,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150522$7526_Y + connect \Y $eq$libresoc.v:150521$7526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150523$7527 + cell $eq $eq$libresoc.v:150522$7527 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313973,10 +310783,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150523$7527_Y + connect \Y $eq$libresoc.v:150522$7527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150524$7528 + cell $eq $eq$libresoc.v:150523$7528 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313984,10 +310794,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150524$7528_Y + connect \Y $eq$libresoc.v:150523$7528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150525$7529 + cell $eq $eq$libresoc.v:150524$7529 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -313995,10 +310805,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150525$7529_Y + connect \Y $eq$libresoc.v:150524$7529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150526$7530 + cell $eq $eq$libresoc.v:150525$7530 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314006,10 +310816,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150526$7530_Y + connect \Y $eq$libresoc.v:150525$7530_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150527$7531 + cell $eq $eq$libresoc.v:150526$7531 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314017,10 +310827,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150527$7531_Y + connect \Y $eq$libresoc.v:150526$7531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150528$7532 + cell $eq $eq$libresoc.v:150527$7532 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314028,10 +310838,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150528$7532_Y + connect \Y $eq$libresoc.v:150527$7532_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150529$7533 + cell $eq $eq$libresoc.v:150528$7533 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314039,10 +310849,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150529$7533_Y + connect \Y $eq$libresoc.v:150528$7533_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150530$7534 + cell $eq $eq$libresoc.v:150529$7534 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314050,10 +310860,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150530$7534_Y + connect \Y $eq$libresoc.v:150529$7534_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150531$7535 + cell $eq $eq$libresoc.v:150530$7535 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314061,10 +310871,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150531$7535_Y + connect \Y $eq$libresoc.v:150530$7535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150532$7536 + cell $eq $eq$libresoc.v:150531$7536 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314072,10 +310882,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150532$7536_Y + connect \Y $eq$libresoc.v:150531$7536_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150533$7537 + cell $eq $eq$libresoc.v:150532$7537 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314083,10 +310893,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150533$7537_Y + connect \Y $eq$libresoc.v:150532$7537_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150534$7538 + cell $eq $eq$libresoc.v:150533$7538 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314094,10 +310904,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150534$7538_Y + connect \Y $eq$libresoc.v:150533$7538_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - cell $eq $eq$libresoc.v:150535$7539 + cell $eq $eq$libresoc.v:150534$7539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314105,10 +310915,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \logical_op__data_len [3] connect \B 1'1 - connect \Y $eq$libresoc.v:150535$7539_Y + connect \Y $eq$libresoc.v:150534$7539_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150551$7560 + cell $eq $eq$libresoc.v:150550$7560 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314116,10 +310926,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150551$7560_Y + connect \Y $eq$libresoc.v:150550$7560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150552$7561 + cell $eq $eq$libresoc.v:150551$7561 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314127,10 +310937,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150552$7561_Y + connect \Y $eq$libresoc.v:150551$7561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150553$7562 + cell $eq $eq$libresoc.v:150552$7562 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314138,10 +310948,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150553$7562_Y + connect \Y $eq$libresoc.v:150552$7562_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150554$7563 + cell $eq $eq$libresoc.v:150553$7563 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314149,10 +310959,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150554$7563_Y + connect \Y $eq$libresoc.v:150553$7563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150555$7564 + cell $eq $eq$libresoc.v:150554$7564 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314160,10 +310970,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150555$7564_Y + connect \Y $eq$libresoc.v:150554$7564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150556$7565 + cell $eq $eq$libresoc.v:150555$7565 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314171,10 +310981,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150556$7565_Y + connect \Y $eq$libresoc.v:150555$7565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150557$7566 + cell $eq $eq$libresoc.v:150556$7566 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314182,10 +310992,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150557$7566_Y + connect \Y $eq$libresoc.v:150556$7566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150558$7567 + cell $eq $eq$libresoc.v:150557$7567 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314193,10 +311003,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150558$7567_Y + connect \Y $eq$libresoc.v:150557$7567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150559$7568 + cell $eq $eq$libresoc.v:150558$7568 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314204,10 +311014,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150559$7568_Y + connect \Y $eq$libresoc.v:150558$7568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150560$7569 + cell $eq $eq$libresoc.v:150559$7569 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314215,10 +311025,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150560$7569_Y + connect \Y $eq$libresoc.v:150559$7569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150561$7570 + cell $eq $eq$libresoc.v:150560$7570 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314226,10 +311036,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150561$7570_Y + connect \Y $eq$libresoc.v:150560$7570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150562$7571 + cell $eq $eq$libresoc.v:150561$7571 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314237,10 +311047,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150562$7571_Y + connect \Y $eq$libresoc.v:150561$7571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150563$7572 + cell $eq $eq$libresoc.v:150562$7572 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314248,10 +311058,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150563$7572_Y + connect \Y $eq$libresoc.v:150562$7572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150564$7573 + cell $eq $eq$libresoc.v:150563$7573 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314259,10 +311069,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150564$7573_Y + connect \Y $eq$libresoc.v:150563$7573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150565$7574 + cell $eq $eq$libresoc.v:150564$7574 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314270,10 +311080,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150565$7574_Y + connect \Y $eq$libresoc.v:150564$7574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150566$7575 + cell $eq $eq$libresoc.v:150565$7575 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314281,10 +311091,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150566$7575_Y + connect \Y $eq$libresoc.v:150565$7575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150567$7576 + cell $eq $eq$libresoc.v:150566$7576 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314292,10 +311102,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150567$7576_Y + connect \Y $eq$libresoc.v:150566$7576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150568$7577 + cell $eq $eq$libresoc.v:150567$7577 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314303,10 +311113,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150568$7577_Y + connect \Y $eq$libresoc.v:150567$7577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150569$7578 + cell $eq $eq$libresoc.v:150568$7578 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314314,10 +311124,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150569$7578_Y + connect \Y $eq$libresoc.v:150568$7578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150570$7579 + cell $eq $eq$libresoc.v:150569$7579 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314325,10 +311135,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150570$7579_Y + connect \Y $eq$libresoc.v:150569$7579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150571$7580 + cell $eq $eq$libresoc.v:150570$7580 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314336,10 +311146,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150571$7580_Y + connect \Y $eq$libresoc.v:150570$7580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150572$7581 + cell $eq $eq$libresoc.v:150571$7581 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314347,10 +311157,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150572$7581_Y + connect \Y $eq$libresoc.v:150571$7581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150573$7582 + cell $eq $eq$libresoc.v:150572$7582 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314358,10 +311168,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150573$7582_Y + connect \Y $eq$libresoc.v:150572$7582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150574$7583 + cell $eq $eq$libresoc.v:150573$7583 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314369,10 +311179,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150574$7583_Y + connect \Y $eq$libresoc.v:150573$7583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150575$7584 + cell $eq $eq$libresoc.v:150574$7584 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314380,10 +311190,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150575$7584_Y + connect \Y $eq$libresoc.v:150574$7584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150576$7585 + cell $eq $eq$libresoc.v:150575$7585 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314391,10 +311201,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150576$7585_Y + connect \Y $eq$libresoc.v:150575$7585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150577$7586 + cell $eq $eq$libresoc.v:150576$7586 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314402,10 +311212,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150577$7586_Y + connect \Y $eq$libresoc.v:150576$7586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150578$7587 + cell $eq $eq$libresoc.v:150577$7587 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314413,10 +311223,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150578$7587_Y + connect \Y $eq$libresoc.v:150577$7587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150579$7588 + cell $eq $eq$libresoc.v:150578$7588 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314424,10 +311234,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150579$7588_Y + connect \Y $eq$libresoc.v:150578$7588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150580$7589 + cell $eq $eq$libresoc.v:150579$7589 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314435,10 +311245,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150580$7589_Y + connect \Y $eq$libresoc.v:150579$7589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150581$7590 + cell $eq $eq$libresoc.v:150580$7590 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314446,10 +311256,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150581$7590_Y + connect \Y $eq$libresoc.v:150580$7590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150582$7591 + cell $eq $eq$libresoc.v:150581$7591 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314457,10 +311267,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150582$7591_Y + connect \Y $eq$libresoc.v:150581$7591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150583$7592 + cell $eq $eq$libresoc.v:150582$7592 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314468,10 +311278,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150583$7592_Y + connect \Y $eq$libresoc.v:150582$7592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150584$7593 + cell $eq $eq$libresoc.v:150583$7593 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314479,10 +311289,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150584$7593_Y + connect \Y $eq$libresoc.v:150583$7593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150585$7594 + cell $eq $eq$libresoc.v:150584$7594 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314490,10 +311300,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150585$7594_Y + connect \Y $eq$libresoc.v:150584$7594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150586$7595 + cell $eq $eq$libresoc.v:150585$7595 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -314501,50 +311311,50 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150586$7595_Y + connect \Y $eq$libresoc.v:150585$7595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $extend$libresoc.v:150537$7541 + cell $pos $extend$libresoc.v:150536$7541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 64 connect \A \$158 - connect \Y $extend$libresoc.v:150537$7541_Y + connect \Y $extend$libresoc.v:150536$7541_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" - cell $pos $extend$libresoc.v:150539$7544 + cell $pos $extend$libresoc.v:150538$7544 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 8 connect \A \clz_lz - connect \Y $extend$libresoc.v:150539$7544_Y + connect \Y $extend$libresoc.v:150538$7544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $extend$libresoc.v:150541$7547 + cell $pos $extend$libresoc.v:150540$7547 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \$166 - connect \Y $extend$libresoc.v:150541$7547_Y + connect \Y $extend$libresoc.v:150540$7547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:150542$7549 + cell $pos $extend$libresoc.v:150541$7549 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 64 connect \A \logical_op__data_len - connect \Y $extend$libresoc.v:150542$7549_Y + connect \Y $extend$libresoc.v:150541$7549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $extend$libresoc.v:150546$7554 + cell $pos $extend$libresoc.v:150545$7554 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$176 - connect \Y $extend$libresoc.v:150546$7554_Y + connect \Y $extend$libresoc.v:150545$7554_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - cell $or $or$libresoc.v:150549$7558 + cell $or $or$libresoc.v:150548$7558 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -314552,66 +311362,66 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $or$libresoc.v:150549$7558_Y + connect \Y $or$libresoc.v:150548$7558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $pos$libresoc.v:150537$7542 + cell $pos $pos$libresoc.v:150536$7542 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:150537$7541_Y - connect \Y $pos$libresoc.v:150537$7542_Y + connect \A $extend$libresoc.v:150536$7541_Y + connect \Y $pos$libresoc.v:150536$7542_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" - cell $pos $pos$libresoc.v:150539$7545 + cell $pos $pos$libresoc.v:150538$7545 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:150539$7544_Y - connect \Y $pos$libresoc.v:150539$7545_Y + connect \A $extend$libresoc.v:150538$7544_Y + connect \Y $pos$libresoc.v:150538$7545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $pos$libresoc.v:150541$7548 + cell $pos $pos$libresoc.v:150540$7548 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:150541$7547_Y - connect \Y $pos$libresoc.v:150541$7548_Y + connect \A $extend$libresoc.v:150540$7547_Y + connect \Y $pos$libresoc.v:150540$7548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:150542$7550 + cell $pos $pos$libresoc.v:150541$7550 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:150542$7549_Y - connect \Y $pos$libresoc.v:150542$7550_Y + connect \A $extend$libresoc.v:150541$7549_Y + connect \Y $pos$libresoc.v:150541$7550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $pos$libresoc.v:150546$7555 + cell $pos $pos$libresoc.v:150545$7555 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:150546$7554_Y - connect \Y $pos$libresoc.v:150546$7555_Y + connect \A $extend$libresoc.v:150545$7554_Y + connect \Y $pos$libresoc.v:150545$7555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - cell $reduce_xor $reduce_xor$libresoc.v:150543$7551 + cell $reduce_xor $reduce_xor$libresoc.v:150542$7551 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } - connect \Y $reduce_xor$libresoc.v:150543$7551_Y + connect \Y $reduce_xor$libresoc.v:150542$7551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - cell $reduce_xor $reduce_xor$libresoc.v:150544$7552 + cell $reduce_xor $reduce_xor$libresoc.v:150543$7552 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } - connect \Y $reduce_xor$libresoc.v:150544$7552_Y + connect \Y $reduce_xor$libresoc.v:150543$7552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $sub $sub$libresoc.v:150538$7543 + cell $sub $sub$libresoc.v:150537$7543 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -314619,34 +311429,34 @@ module \main$51 parameter \Y_WIDTH 8 connect \A \clz_lz connect \B 6'100000 - connect \Y $sub$libresoc.v:150538$7543_Y + connect \Y $sub$libresoc.v:150537$7543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $mux $ternary$libresoc.v:150540$7546 + cell $mux $ternary$libresoc.v:150539$7546 parameter \WIDTH 8 connect \A \$164 connect \B \$162 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:150540$7546_Y + connect \Y $ternary$libresoc.v:150539$7546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $mux $ternary$libresoc.v:150545$7553 + cell $mux $ternary$libresoc.v:150544$7553 parameter \WIDTH 32 connect \A \a32 connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } connect \S \count_right - connect \Y $ternary$libresoc.v:150545$7553_Y + connect \Y $ternary$libresoc.v:150544$7553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" - cell $mux $ternary$libresoc.v:150547$7556 + cell $mux $ternary$libresoc.v:150546$7556 parameter \WIDTH 64 connect \A \ra connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } connect \S \count_right - connect \Y $ternary$libresoc.v:150547$7556_Y + connect \Y $ternary$libresoc.v:150546$7556_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $xor $xor$libresoc.v:150536$7540 + cell $xor $xor$libresoc.v:150535$7540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314654,10 +311464,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \par0 connect \B \par1 - connect \Y $xor$libresoc.v:150536$7540_Y + connect \Y $xor$libresoc.v:150535$7540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" - cell $xor $xor$libresoc.v:150550$7559 + cell $xor $xor$libresoc.v:150549$7559 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -314665,47 +311475,47 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $xor$libresoc.v:150550$7559_Y + connect \Y $xor$libresoc.v:150549$7559_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:150587.10-150591.4" + attribute \src "libresoc.v:150586.10-150590.4" cell \bpermd \bpermd connect \ra \bpermd_ra connect \rb \bpermd_rb connect \rs \bpermd_rs end attribute \module_not_derived 1 - attribute \src "libresoc.v:150592.7-150595.4" + attribute \src "libresoc.v:150591.7-150594.4" cell \clz \clz connect \lz \clz_lz connect \sig_in \clz_sig_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:150596.12-150600.4" + attribute \src "libresoc.v:150595.12-150599.4" cell \popcount \popcount connect \a \popcount_a connect \data_len \popcount_data_len connect \o \popcount_o end - attribute \src "libresoc.v:150040.7-150040.20" - process $proc$libresoc.v:150040$7608 + attribute \src "libresoc.v:150039.7-150039.20" + process $proc$libresoc.v:150039$7608 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:150601.3-150655.6" - process $proc$libresoc.v:150601$7596 + attribute \src "libresoc.v:150600.3-150654.6" + process $proc$libresoc.v:150600$7596 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:150602.5-150602.29" + attribute \src "libresoc.v:150601.5-150601.29" switch \initial - attribute \src "libresoc.v:150602.9-150602.17" + attribute \src "libresoc.v:150601.9-150601.17" case 1'1 case end @@ -314773,14 +311583,14 @@ module \main$51 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:150656.3-150666.6" - process $proc$libresoc.v:150656$7597 + attribute \src "libresoc.v:150655.3-150665.6" + process $proc$libresoc.v:150655$7597 assign { } { } assign { } { } assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] - attribute \src "libresoc.v:150657.5-150657.29" + attribute \src "libresoc.v:150656.5-150656.29" switch \initial - attribute \src "libresoc.v:150657.9-150657.17" + attribute \src "libresoc.v:150656.9-150656.17" case 1'1 case end @@ -314796,14 +311606,14 @@ module \main$51 sync always update \clz_sig_in $0\clz_sig_in[63:0] end - attribute \src "libresoc.v:150667.3-150677.6" - process $proc$libresoc.v:150667$7598 + attribute \src "libresoc.v:150666.3-150676.6" + process $proc$libresoc.v:150666$7598 assign { } { } assign { } { } assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] - attribute \src "libresoc.v:150668.5-150668.29" + attribute \src "libresoc.v:150667.5-150667.29" switch \initial - attribute \src "libresoc.v:150668.9-150668.17" + attribute \src "libresoc.v:150667.9-150667.17" case 1'1 case end @@ -314819,14 +311629,14 @@ module \main$51 sync always update \bpermd_rs $0\bpermd_rs[63:0] end - attribute \src "libresoc.v:150678.3-150688.6" - process $proc$libresoc.v:150678$7599 + attribute \src "libresoc.v:150677.3-150687.6" + process $proc$libresoc.v:150677$7599 assign { } { } assign { } { } assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] - attribute \src "libresoc.v:150679.5-150679.29" + attribute \src "libresoc.v:150678.5-150678.29" switch \initial - attribute \src "libresoc.v:150679.9-150679.17" + attribute \src "libresoc.v:150678.9-150678.17" case 1'1 case end @@ -314842,14 +311652,14 @@ module \main$51 sync always update \bpermd_rb $0\bpermd_rb[63:0] end - attribute \src "libresoc.v:150689.3-150699.6" - process $proc$libresoc.v:150689$7600 + attribute \src "libresoc.v:150688.3-150698.6" + process $proc$libresoc.v:150688$7600 assign { } { } assign { } { } assign $0\popcount_a[63:0] $1\popcount_a[63:0] - attribute \src "libresoc.v:150690.5-150690.29" + attribute \src "libresoc.v:150689.5-150689.29" switch \initial - attribute \src "libresoc.v:150690.9-150690.17" + attribute \src "libresoc.v:150689.9-150689.17" case 1'1 case end @@ -314865,14 +311675,14 @@ module \main$51 sync always update \popcount_a $0\popcount_a[63:0] end - attribute \src "libresoc.v:150700.3-150710.6" - process $proc$libresoc.v:150700$7601 + attribute \src "libresoc.v:150699.3-150709.6" + process $proc$libresoc.v:150699$7601 assign { } { } assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:150701.5-150701.29" + attribute \src "libresoc.v:150700.5-150700.29" switch \initial - attribute \src "libresoc.v:150701.9-150701.17" + attribute \src "libresoc.v:150700.9-150700.17" case 1'1 case end @@ -314888,14 +311698,14 @@ module \main$51 sync always update \b $0\b[63:0] end - attribute \src "libresoc.v:150711.3-150721.6" - process $proc$libresoc.v:150711$7602 + attribute \src "libresoc.v:150710.3-150720.6" + process $proc$libresoc.v:150710$7602 assign { } { } assign { } { } assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] - attribute \src "libresoc.v:150712.5-150712.29" + attribute \src "libresoc.v:150711.5-150711.29" switch \initial - attribute \src "libresoc.v:150712.9-150712.17" + attribute \src "libresoc.v:150711.9-150711.17" case 1'1 case end @@ -314911,14 +311721,14 @@ module \main$51 sync always update \popcount_data_len $0\popcount_data_len[63:0] end - attribute \src "libresoc.v:150722.3-150732.6" - process $proc$libresoc.v:150722$7603 + attribute \src "libresoc.v:150721.3-150731.6" + process $proc$libresoc.v:150721$7603 assign { } { } assign { } { } assign $0\par0[0:0] $1\par0[0:0] - attribute \src "libresoc.v:150723.5-150723.29" + attribute \src "libresoc.v:150722.5-150722.29" switch \initial - attribute \src "libresoc.v:150723.9-150723.17" + attribute \src "libresoc.v:150722.9-150722.17" case 1'1 case end @@ -314934,14 +311744,14 @@ module \main$51 sync always update \par0 $0\par0[0:0] end - attribute \src "libresoc.v:150733.3-150743.6" - process $proc$libresoc.v:150733$7604 + attribute \src "libresoc.v:150732.3-150742.6" + process $proc$libresoc.v:150732$7604 assign { } { } assign { } { } assign $0\par1[0:0] $1\par1[0:0] - attribute \src "libresoc.v:150734.5-150734.29" + attribute \src "libresoc.v:150733.5-150733.29" switch \initial - attribute \src "libresoc.v:150734.9-150734.17" + attribute \src "libresoc.v:150733.9-150733.17" case 1'1 case end @@ -314957,14 +311767,14 @@ module \main$51 sync always update \par1 $0\par1[0:0] end - attribute \src "libresoc.v:150744.3-150754.6" - process $proc$libresoc.v:150744$7605 + attribute \src "libresoc.v:150743.3-150753.6" + process $proc$libresoc.v:150743$7605 assign { } { } assign { } { } assign $0\count_right[0:0] $1\count_right[0:0] - attribute \src "libresoc.v:150745.5-150745.29" + attribute \src "libresoc.v:150744.5-150744.29" switch \initial - attribute \src "libresoc.v:150745.9-150745.17" + attribute \src "libresoc.v:150744.9-150744.17" case 1'1 case end @@ -314980,14 +311790,14 @@ module \main$51 sync always update \count_right $0\count_right[0:0] end - attribute \src "libresoc.v:150755.3-150765.6" - process $proc$libresoc.v:150755$7606 + attribute \src "libresoc.v:150754.3-150764.6" + process $proc$libresoc.v:150754$7606 assign { } { } assign { } { } assign $0\a32[31:0] $1\a32[31:0] - attribute \src "libresoc.v:150756.5-150756.29" + attribute \src "libresoc.v:150755.5-150755.29" switch \initial - attribute \src "libresoc.v:150756.9-150756.17" + attribute \src "libresoc.v:150755.9-150755.17" case 1'1 case end @@ -315003,14 +311813,14 @@ module \main$51 sync always update \a32 $0\a32[31:0] end - attribute \src "libresoc.v:150766.3-150784.6" - process $proc$libresoc.v:150766$7607 + attribute \src "libresoc.v:150765.3-150783.6" + process $proc$libresoc.v:150765$7607 assign { } { } assign { } { } assign $0\cntz_i[63:0] $1\cntz_i[63:0] - attribute \src "libresoc.v:150767.5-150767.29" + attribute \src "libresoc.v:150766.5-150766.29" switch \initial - attribute \src "libresoc.v:150767.9-150767.17" + attribute \src "libresoc.v:150766.9-150766.17" case 1'1 case end @@ -315037,193 +311847,193 @@ module \main$51 sync always update \cntz_i $0\cntz_i[63:0] end - connect \$99 $eq$libresoc.v:150507$7511_Y - connect \$101 $eq$libresoc.v:150508$7512_Y - connect \$103 $eq$libresoc.v:150509$7513_Y - connect \$105 $eq$libresoc.v:150510$7514_Y - connect \$107 $eq$libresoc.v:150511$7515_Y - connect \$109 $eq$libresoc.v:150512$7516_Y - connect \$111 $eq$libresoc.v:150513$7517_Y - connect \$113 $eq$libresoc.v:150514$7518_Y - connect \$115 $eq$libresoc.v:150515$7519_Y - connect \$117 $eq$libresoc.v:150516$7520_Y - connect \$119 $eq$libresoc.v:150517$7521_Y - connect \$121 $eq$libresoc.v:150518$7522_Y - connect \$123 $eq$libresoc.v:150519$7523_Y - connect \$125 $eq$libresoc.v:150520$7524_Y - connect \$127 $eq$libresoc.v:150521$7525_Y - connect \$129 $eq$libresoc.v:150522$7526_Y - connect \$131 $eq$libresoc.v:150523$7527_Y - connect \$133 $eq$libresoc.v:150524$7528_Y - connect \$135 $eq$libresoc.v:150525$7529_Y - connect \$137 $eq$libresoc.v:150526$7530_Y - connect \$139 $eq$libresoc.v:150527$7531_Y - connect \$141 $eq$libresoc.v:150528$7532_Y - connect \$143 $eq$libresoc.v:150529$7533_Y - connect \$145 $eq$libresoc.v:150530$7534_Y - connect \$147 $eq$libresoc.v:150531$7535_Y - connect \$149 $eq$libresoc.v:150532$7536_Y - connect \$151 $eq$libresoc.v:150533$7537_Y - connect \$153 $eq$libresoc.v:150534$7538_Y - connect \$155 $eq$libresoc.v:150535$7539_Y - connect \$158 $xor$libresoc.v:150536$7540_Y - connect \$157 $pos$libresoc.v:150537$7542_Y - connect \$162 $sub$libresoc.v:150538$7543_Y - connect \$164 $pos$libresoc.v:150539$7545_Y - connect \$166 $ternary$libresoc.v:150540$7546_Y - connect \$161 $pos$libresoc.v:150541$7548_Y - connect \$169 $pos$libresoc.v:150542$7550_Y - connect \$171 $reduce_xor$libresoc.v:150543$7551_Y - connect \$173 $reduce_xor$libresoc.v:150544$7552_Y - connect \$176 $ternary$libresoc.v:150545$7553_Y - connect \$175 $pos$libresoc.v:150546$7555_Y - connect \$179 $ternary$libresoc.v:150547$7556_Y - connect \$21 $and$libresoc.v:150548$7557_Y - connect \$23 $or$libresoc.v:150549$7558_Y - connect \$25 $xor$libresoc.v:150550$7559_Y - connect \$27 $eq$libresoc.v:150551$7560_Y - connect \$29 $eq$libresoc.v:150552$7561_Y - connect \$31 $eq$libresoc.v:150553$7562_Y - connect \$33 $eq$libresoc.v:150554$7563_Y - connect \$35 $eq$libresoc.v:150555$7564_Y - connect \$37 $eq$libresoc.v:150556$7565_Y - connect \$39 $eq$libresoc.v:150557$7566_Y - connect \$41 $eq$libresoc.v:150558$7567_Y - connect \$43 $eq$libresoc.v:150559$7568_Y - connect \$45 $eq$libresoc.v:150560$7569_Y - connect \$47 $eq$libresoc.v:150561$7570_Y - connect \$49 $eq$libresoc.v:150562$7571_Y - connect \$51 $eq$libresoc.v:150563$7572_Y - connect \$53 $eq$libresoc.v:150564$7573_Y - connect \$55 $eq$libresoc.v:150565$7574_Y - connect \$57 $eq$libresoc.v:150566$7575_Y - connect \$59 $eq$libresoc.v:150567$7576_Y - connect \$61 $eq$libresoc.v:150568$7577_Y - connect \$63 $eq$libresoc.v:150569$7578_Y - connect \$65 $eq$libresoc.v:150570$7579_Y - connect \$67 $eq$libresoc.v:150571$7580_Y - connect \$69 $eq$libresoc.v:150572$7581_Y - connect \$71 $eq$libresoc.v:150573$7582_Y - connect \$73 $eq$libresoc.v:150574$7583_Y - connect \$75 $eq$libresoc.v:150575$7584_Y - connect \$77 $eq$libresoc.v:150576$7585_Y - connect \$79 $eq$libresoc.v:150577$7586_Y - connect \$81 $eq$libresoc.v:150578$7587_Y - connect \$83 $eq$libresoc.v:150579$7588_Y - connect \$85 $eq$libresoc.v:150580$7589_Y - connect \$87 $eq$libresoc.v:150581$7590_Y - connect \$89 $eq$libresoc.v:150582$7591_Y - connect \$91 $eq$libresoc.v:150583$7592_Y - connect \$93 $eq$libresoc.v:150584$7593_Y - connect \$95 $eq$libresoc.v:150585$7594_Y - connect \$97 $eq$libresoc.v:150586$7595_Y + connect \$99 $eq$libresoc.v:150506$7511_Y + connect \$101 $eq$libresoc.v:150507$7512_Y + connect \$103 $eq$libresoc.v:150508$7513_Y + connect \$105 $eq$libresoc.v:150509$7514_Y + connect \$107 $eq$libresoc.v:150510$7515_Y + connect \$109 $eq$libresoc.v:150511$7516_Y + connect \$111 $eq$libresoc.v:150512$7517_Y + connect \$113 $eq$libresoc.v:150513$7518_Y + connect \$115 $eq$libresoc.v:150514$7519_Y + connect \$117 $eq$libresoc.v:150515$7520_Y + connect \$119 $eq$libresoc.v:150516$7521_Y + connect \$121 $eq$libresoc.v:150517$7522_Y + connect \$123 $eq$libresoc.v:150518$7523_Y + connect \$125 $eq$libresoc.v:150519$7524_Y + connect \$127 $eq$libresoc.v:150520$7525_Y + connect \$129 $eq$libresoc.v:150521$7526_Y + connect \$131 $eq$libresoc.v:150522$7527_Y + connect \$133 $eq$libresoc.v:150523$7528_Y + connect \$135 $eq$libresoc.v:150524$7529_Y + connect \$137 $eq$libresoc.v:150525$7530_Y + connect \$139 $eq$libresoc.v:150526$7531_Y + connect \$141 $eq$libresoc.v:150527$7532_Y + connect \$143 $eq$libresoc.v:150528$7533_Y + connect \$145 $eq$libresoc.v:150529$7534_Y + connect \$147 $eq$libresoc.v:150530$7535_Y + connect \$149 $eq$libresoc.v:150531$7536_Y + connect \$151 $eq$libresoc.v:150532$7537_Y + connect \$153 $eq$libresoc.v:150533$7538_Y + connect \$155 $eq$libresoc.v:150534$7539_Y + connect \$158 $xor$libresoc.v:150535$7540_Y + connect \$157 $pos$libresoc.v:150536$7542_Y + connect \$162 $sub$libresoc.v:150537$7543_Y + connect \$164 $pos$libresoc.v:150538$7545_Y + connect \$166 $ternary$libresoc.v:150539$7546_Y + connect \$161 $pos$libresoc.v:150540$7548_Y + connect \$169 $pos$libresoc.v:150541$7550_Y + connect \$171 $reduce_xor$libresoc.v:150542$7551_Y + connect \$173 $reduce_xor$libresoc.v:150543$7552_Y + connect \$176 $ternary$libresoc.v:150544$7553_Y + connect \$175 $pos$libresoc.v:150545$7555_Y + connect \$179 $ternary$libresoc.v:150546$7556_Y + connect \$21 $and$libresoc.v:150547$7557_Y + connect \$23 $or$libresoc.v:150548$7558_Y + connect \$25 $xor$libresoc.v:150549$7559_Y + connect \$27 $eq$libresoc.v:150550$7560_Y + connect \$29 $eq$libresoc.v:150551$7561_Y + connect \$31 $eq$libresoc.v:150552$7562_Y + connect \$33 $eq$libresoc.v:150553$7563_Y + connect \$35 $eq$libresoc.v:150554$7564_Y + connect \$37 $eq$libresoc.v:150555$7565_Y + connect \$39 $eq$libresoc.v:150556$7566_Y + connect \$41 $eq$libresoc.v:150557$7567_Y + connect \$43 $eq$libresoc.v:150558$7568_Y + connect \$45 $eq$libresoc.v:150559$7569_Y + connect \$47 $eq$libresoc.v:150560$7570_Y + connect \$49 $eq$libresoc.v:150561$7571_Y + connect \$51 $eq$libresoc.v:150562$7572_Y + connect \$53 $eq$libresoc.v:150563$7573_Y + connect \$55 $eq$libresoc.v:150564$7574_Y + connect \$57 $eq$libresoc.v:150565$7575_Y + connect \$59 $eq$libresoc.v:150566$7576_Y + connect \$61 $eq$libresoc.v:150567$7577_Y + connect \$63 $eq$libresoc.v:150568$7578_Y + connect \$65 $eq$libresoc.v:150569$7579_Y + connect \$67 $eq$libresoc.v:150570$7580_Y + connect \$69 $eq$libresoc.v:150571$7581_Y + connect \$71 $eq$libresoc.v:150572$7582_Y + connect \$73 $eq$libresoc.v:150573$7583_Y + connect \$75 $eq$libresoc.v:150574$7584_Y + connect \$77 $eq$libresoc.v:150575$7585_Y + connect \$79 $eq$libresoc.v:150576$7586_Y + connect \$81 $eq$libresoc.v:150577$7587_Y + connect \$83 $eq$libresoc.v:150578$7588_Y + connect \$85 $eq$libresoc.v:150579$7589_Y + connect \$87 $eq$libresoc.v:150580$7590_Y + connect \$89 $eq$libresoc.v:150581$7591_Y + connect \$91 $eq$libresoc.v:150582$7592_Y + connect \$93 $eq$libresoc.v:150583$7593_Y + connect \$95 $eq$libresoc.v:150584$7594_Y + connect \$97 $eq$libresoc.v:150585$7595_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$20 \xer_so end -attribute \src "libresoc.v:150792.1-151307.10" +attribute \src "libresoc.v:150791.1-151306.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main" attribute \generator "nMigen" module \main$9 - attribute \src "libresoc.v:151162.3-151172.6" + attribute \src "libresoc.v:151161.3-151171.6" wire width 2 $0\BC[1:0] - attribute \src "libresoc.v:151216.3-151226.6" + attribute \src "libresoc.v:151215.3-151225.6" wire width 2 $0\ba[1:0] - attribute \src "libresoc.v:151227.3-151237.6" + attribute \src "libresoc.v:151226.3-151236.6" wire width 2 $0\bb[1:0] - attribute \src "libresoc.v:151238.3-151258.6" + attribute \src "libresoc.v:151237.3-151257.6" wire $0\bit_a[0:0] - attribute \src "libresoc.v:151259.3-151279.6" + attribute \src "libresoc.v:151258.3-151278.6" wire $0\bit_b[0:0] - attribute \src "libresoc.v:151280.3-151290.6" + attribute \src "libresoc.v:151279.3-151289.6" wire $0\bit_o[0:0] - attribute \src "libresoc.v:151205.3-151215.6" + attribute \src "libresoc.v:151204.3-151214.6" wire width 2 $0\bt[1:0] - attribute \src "libresoc.v:151074.3-151108.6" + attribute \src "libresoc.v:151073.3-151107.6" wire width 4 $0\cr_a$6[3:0]$7623 - attribute \src "libresoc.v:151074.3-151108.6" + attribute \src "libresoc.v:151073.3-151107.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:151173.3-151193.6" + attribute \src "libresoc.v:151172.3-151192.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:151291.3-151301.6" + attribute \src "libresoc.v:151290.3-151300.6" wire width 32 $0\full_cr$5[31:0]$7638 - attribute \src "libresoc.v:151109.3-151119.6" + attribute \src "libresoc.v:151108.3-151118.6" wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:150793.7-150793.20" + attribute \src "libresoc.v:150792.7-150792.20" wire $0\initial[0:0] - attribute \src "libresoc.v:151194.3-151204.6" + attribute \src "libresoc.v:151193.3-151203.6" wire width 4 $0\lut[3:0] - attribute \src "libresoc.v:151120.3-151161.6" + attribute \src "libresoc.v:151119.3-151160.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:151120.3-151161.6" + attribute \src "libresoc.v:151119.3-151160.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:151162.3-151172.6" + attribute \src "libresoc.v:151161.3-151171.6" wire width 2 $1\BC[1:0] - attribute \src "libresoc.v:151216.3-151226.6" + attribute \src "libresoc.v:151215.3-151225.6" wire width 2 $1\ba[1:0] - attribute \src "libresoc.v:151227.3-151237.6" + attribute \src "libresoc.v:151226.3-151236.6" wire width 2 $1\bb[1:0] - attribute \src "libresoc.v:151238.3-151258.6" + attribute \src "libresoc.v:151237.3-151257.6" wire $1\bit_a[0:0] - attribute \src "libresoc.v:151259.3-151279.6" + attribute \src "libresoc.v:151258.3-151278.6" wire $1\bit_b[0:0] - attribute \src "libresoc.v:151280.3-151290.6" + attribute \src "libresoc.v:151279.3-151289.6" wire $1\bit_o[0:0] - attribute \src "libresoc.v:151205.3-151215.6" + attribute \src "libresoc.v:151204.3-151214.6" wire width 2 $1\bt[1:0] - attribute \src "libresoc.v:151074.3-151108.6" + attribute \src "libresoc.v:151073.3-151107.6" wire width 4 $1\cr_a$6[3:0]$7624 - attribute \src "libresoc.v:151074.3-151108.6" + attribute \src "libresoc.v:151073.3-151107.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:151173.3-151193.6" + attribute \src "libresoc.v:151172.3-151192.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:151291.3-151301.6" + attribute \src "libresoc.v:151290.3-151300.6" wire width 32 $1\full_cr$5[31:0]$7639 - attribute \src "libresoc.v:151109.3-151119.6" + attribute \src "libresoc.v:151108.3-151118.6" wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:151194.3-151204.6" + attribute \src "libresoc.v:151193.3-151203.6" wire width 4 $1\lut[3:0] - attribute \src "libresoc.v:151120.3-151161.6" + attribute \src "libresoc.v:151119.3-151160.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:151120.3-151161.6" + attribute \src "libresoc.v:151119.3-151160.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:151238.3-151258.6" + attribute \src "libresoc.v:151237.3-151257.6" wire $2\bit_a[0:0] - attribute \src "libresoc.v:151259.3-151279.6" + attribute \src "libresoc.v:151258.3-151278.6" wire $2\bit_b[0:0] - attribute \src "libresoc.v:151074.3-151108.6" + attribute \src "libresoc.v:151073.3-151107.6" wire width 4 $2\cr_a$6[3:0]$7625 - attribute \src "libresoc.v:151173.3-151193.6" + attribute \src "libresoc.v:151172.3-151192.6" wire $2\cr_bit[0:0] - attribute \src "libresoc.v:151120.3-151161.6" + attribute \src "libresoc.v:151119.3-151160.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:151070.18-151070.96" - wire width 64 $extend$libresoc.v:151070$7615_Y - attribute \src "libresoc.v:151072.18-151072.98" - wire width 65 $extend$libresoc.v:151072$7618_Y - attribute \src "libresoc.v:151073.17-151073.92" - wire width 5 $extend$libresoc.v:151073$7620_Y - attribute \src "libresoc.v:151070.18-151070.96" - wire width 64 $pos$libresoc.v:151070$7616_Y - attribute \src "libresoc.v:151072.18-151072.98" - wire width 65 $pos$libresoc.v:151072$7619_Y - attribute \src "libresoc.v:151073.17-151073.92" - wire width 5 $pos$libresoc.v:151073$7621_Y + attribute \src "libresoc.v:151069.18-151069.96" + wire width 64 $extend$libresoc.v:151069$7615_Y + attribute \src "libresoc.v:151071.18-151071.98" + wire width 65 $extend$libresoc.v:151071$7618_Y + attribute \src "libresoc.v:151072.17-151072.92" + wire width 5 $extend$libresoc.v:151072$7620_Y + attribute \src "libresoc.v:151069.18-151069.96" + wire width 64 $pos$libresoc.v:151069$7616_Y + attribute \src "libresoc.v:151071.18-151071.98" + wire width 65 $pos$libresoc.v:151071$7619_Y + attribute \src "libresoc.v:151072.17-151072.92" + wire width 5 $pos$libresoc.v:151072$7621_Y + attribute \src "libresoc.v:151063.18-151063.116" + wire width 3 $sub$libresoc.v:151063$7609_Y attribute \src "libresoc.v:151064.18-151064.116" - wire width 3 $sub$libresoc.v:151064$7609_Y + wire width 3 $sub$libresoc.v:151064$7610_Y attribute \src "libresoc.v:151065.18-151065.116" - wire width 3 $sub$libresoc.v:151065$7610_Y - attribute \src "libresoc.v:151066.18-151066.116" - wire width 3 $sub$libresoc.v:151066$7611_Y - attribute \src "libresoc.v:151067.18-151067.114" - wire $ternary$libresoc.v:151067$7612_Y - attribute \src "libresoc.v:151068.18-151068.115" - wire $ternary$libresoc.v:151068$7613_Y - attribute \src "libresoc.v:151069.18-151069.112" - wire $ternary$libresoc.v:151069$7614_Y - attribute \src "libresoc.v:151071.18-151071.108" - wire width 64 $ternary$libresoc.v:151071$7617_Y + wire width 3 $sub$libresoc.v:151065$7611_Y + attribute \src "libresoc.v:151066.18-151066.114" + wire $ternary$libresoc.v:151066$7612_Y + attribute \src "libresoc.v:151067.18-151067.115" + wire $ternary$libresoc.v:151067$7613_Y + attribute \src "libresoc.v:151068.18-151068.112" + wire $ternary$libresoc.v:151068$7614_Y + attribute \src "libresoc.v:151070.18-151070.108" + wire width 64 $ternary$libresoc.v:151070$7617_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" wire width 3 \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" @@ -315474,7 +312284,7 @@ module \main$9 wire width 32 output 16 \full_cr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \full_cr_ok - attribute \src "libresoc.v:150793.7-150793.15" + attribute \src "libresoc.v:150792.7-150792.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" wire width 4 \lut @@ -315491,55 +312301,55 @@ module \main$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 5 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:151070$7615 + cell $pos $extend$libresoc.v:151069$7615 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \full_cr - connect \Y $extend$libresoc.v:151070$7615_Y + connect \Y $extend$libresoc.v:151069$7615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $extend$libresoc.v:151072$7618 + cell $pos $extend$libresoc.v:151071$7618 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$27 - connect \Y $extend$libresoc.v:151072$7618_Y + connect \Y $extend$libresoc.v:151071$7618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:151073$7620 + cell $pos $extend$libresoc.v:151072$7620 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 5 connect \A \cr_a - connect \Y $extend$libresoc.v:151073$7620_Y + connect \Y $extend$libresoc.v:151072$7620_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:151070$7616 + cell $pos $pos$libresoc.v:151069$7616 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:151070$7615_Y - connect \Y $pos$libresoc.v:151070$7616_Y + connect \A $extend$libresoc.v:151069$7615_Y + connect \Y $pos$libresoc.v:151069$7616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $pos$libresoc.v:151072$7619 + cell $pos $pos$libresoc.v:151071$7619 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:151072$7618_Y - connect \Y $pos$libresoc.v:151072$7619_Y + connect \A $extend$libresoc.v:151071$7618_Y + connect \Y $pos$libresoc.v:151071$7619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:151073$7621 + cell $pos $pos$libresoc.v:151072$7621 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $extend$libresoc.v:151073$7620_Y - connect \Y $pos$libresoc.v:151073$7621_Y + connect \A $extend$libresoc.v:151072$7620_Y + connect \Y $pos$libresoc.v:151072$7621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" - cell $sub $sub$libresoc.v:151064$7609 + cell $sub $sub$libresoc.v:151063$7609 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -315547,10 +312357,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [22:21] - connect \Y $sub$libresoc.v:151064$7609_Y + connect \Y $sub$libresoc.v:151063$7609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" - cell $sub $sub$libresoc.v:151065$7610 + cell $sub $sub$libresoc.v:151064$7610 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -315558,10 +312368,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [17:16] - connect \Y $sub$libresoc.v:151065$7610_Y + connect \Y $sub$libresoc.v:151064$7610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" - cell $sub $sub$libresoc.v:151066$7611 + cell $sub $sub$libresoc.v:151065$7611 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -315569,59 +312379,59 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [12:11] - connect \Y $sub$libresoc.v:151066$7611_Y + connect \Y $sub$libresoc.v:151065$7611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" - cell $mux $ternary$libresoc.v:151067$7612 + cell $mux $ternary$libresoc.v:151066$7612 parameter \WIDTH 1 connect \A \lut [1] connect \B \lut [3] connect \S \bit_a - connect \Y $ternary$libresoc.v:151067$7612_Y + connect \Y $ternary$libresoc.v:151066$7612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:151068$7613 + cell $mux $ternary$libresoc.v:151067$7613 parameter \WIDTH 1 connect \A \lut [0] connect \B \lut [2] connect \S \bit_a - connect \Y $ternary$libresoc.v:151068$7613_Y + connect \Y $ternary$libresoc.v:151067$7613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:151069$7614 + cell $mux $ternary$libresoc.v:151068$7614 parameter \WIDTH 1 connect \A \$20 connect \B \$18 connect \S \bit_b - connect \Y $ternary$libresoc.v:151069$7614_Y + connect \Y $ternary$libresoc.v:151068$7614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $mux $ternary$libresoc.v:151071$7617 + cell $mux $ternary$libresoc.v:151070$7617 parameter \WIDTH 64 connect \A \rb connect \B \ra connect \S \cr_bit - connect \Y $ternary$libresoc.v:151071$7617_Y + connect \Y $ternary$libresoc.v:151070$7617_Y end - attribute \src "libresoc.v:150793.7-150793.20" - process $proc$libresoc.v:150793$7640 + attribute \src "libresoc.v:150792.7-150792.20" + process $proc$libresoc.v:150792$7640 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:151074.3-151108.6" - process $proc$libresoc.v:151074$7622 + attribute \src "libresoc.v:151073.3-151107.6" + process $proc$libresoc.v:151073$7622 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] assign $0\cr_a$6[3:0]$7623 $1\cr_a$6[3:0]$7624 - attribute \src "libresoc.v:151075.5-151075.29" + attribute \src "libresoc.v:151074.5-151074.29" switch \initial - attribute \src "libresoc.v:151075.9-151075.17" + attribute \src "libresoc.v:151074.9-151074.17" case 1'1 case end @@ -315669,14 +312479,14 @@ module \main$9 update \cr_a_ok $0\cr_a_ok[0:0] update \cr_a$6 $0\cr_a$6[3:0]$7623 end - attribute \src "libresoc.v:151109.3-151119.6" - process $proc$libresoc.v:151109$7626 + attribute \src "libresoc.v:151108.3-151118.6" + process $proc$libresoc.v:151108$7626 assign { } { } assign { } { } assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] - attribute \src "libresoc.v:151110.5-151110.29" + attribute \src "libresoc.v:151109.5-151109.29" switch \initial - attribute \src "libresoc.v:151110.9-151110.17" + attribute \src "libresoc.v:151109.9-151109.17" case 1'1 case end @@ -315692,17 +312502,17 @@ module \main$9 sync always update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:151120.3-151161.6" - process $proc$libresoc.v:151120$7627 + attribute \src "libresoc.v:151119.3-151160.6" + process $proc$libresoc.v:151119$7627 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:151121.5-151121.29" + attribute \src "libresoc.v:151120.5-151120.29" switch \initial - attribute \src "libresoc.v:151121.9-151121.17" + attribute \src "libresoc.v:151120.9-151120.17" case 1'1 case end @@ -315749,14 +312559,14 @@ module \main$9 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:151162.3-151172.6" - process $proc$libresoc.v:151162$7628 + attribute \src "libresoc.v:151161.3-151171.6" + process $proc$libresoc.v:151161$7628 assign { } { } assign { } { } assign $0\BC[1:0] $1\BC[1:0] - attribute \src "libresoc.v:151163.5-151163.29" + attribute \src "libresoc.v:151162.5-151162.29" switch \initial - attribute \src "libresoc.v:151163.9-151163.17" + attribute \src "libresoc.v:151162.9-151162.17" case 1'1 case end @@ -315772,14 +312582,14 @@ module \main$9 sync always update \BC $0\BC[1:0] end - attribute \src "libresoc.v:151173.3-151193.6" - process $proc$libresoc.v:151173$7629 + attribute \src "libresoc.v:151172.3-151192.6" + process $proc$libresoc.v:151172$7629 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:151174.5-151174.29" + attribute \src "libresoc.v:151173.5-151173.29" switch \initial - attribute \src "libresoc.v:151174.9-151174.17" + attribute \src "libresoc.v:151173.9-151173.17" case 1'1 case end @@ -315816,14 +312626,14 @@ module \main$9 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:151194.3-151204.6" - process $proc$libresoc.v:151194$7630 + attribute \src "libresoc.v:151193.3-151203.6" + process $proc$libresoc.v:151193$7630 assign { } { } assign { } { } assign $0\lut[3:0] $1\lut[3:0] - attribute \src "libresoc.v:151195.5-151195.29" + attribute \src "libresoc.v:151194.5-151194.29" switch \initial - attribute \src "libresoc.v:151195.9-151195.17" + attribute \src "libresoc.v:151194.9-151194.17" case 1'1 case end @@ -315839,14 +312649,14 @@ module \main$9 sync always update \lut $0\lut[3:0] end - attribute \src "libresoc.v:151205.3-151215.6" - process $proc$libresoc.v:151205$7631 + attribute \src "libresoc.v:151204.3-151214.6" + process $proc$libresoc.v:151204$7631 assign { } { } assign { } { } assign $0\bt[1:0] $1\bt[1:0] - attribute \src "libresoc.v:151206.5-151206.29" + attribute \src "libresoc.v:151205.5-151205.29" switch \initial - attribute \src "libresoc.v:151206.9-151206.17" + attribute \src "libresoc.v:151205.9-151205.17" case 1'1 case end @@ -315862,14 +312672,14 @@ module \main$9 sync always update \bt $0\bt[1:0] end - attribute \src "libresoc.v:151216.3-151226.6" - process $proc$libresoc.v:151216$7632 + attribute \src "libresoc.v:151215.3-151225.6" + process $proc$libresoc.v:151215$7632 assign { } { } assign { } { } assign $0\ba[1:0] $1\ba[1:0] - attribute \src "libresoc.v:151217.5-151217.29" + attribute \src "libresoc.v:151216.5-151216.29" switch \initial - attribute \src "libresoc.v:151217.9-151217.17" + attribute \src "libresoc.v:151216.9-151216.17" case 1'1 case end @@ -315885,14 +312695,14 @@ module \main$9 sync always update \ba $0\ba[1:0] end - attribute \src "libresoc.v:151227.3-151237.6" - process $proc$libresoc.v:151227$7633 + attribute \src "libresoc.v:151226.3-151236.6" + process $proc$libresoc.v:151226$7633 assign { } { } assign { } { } assign $0\bb[1:0] $1\bb[1:0] - attribute \src "libresoc.v:151228.5-151228.29" + attribute \src "libresoc.v:151227.5-151227.29" switch \initial - attribute \src "libresoc.v:151228.9-151228.17" + attribute \src "libresoc.v:151227.9-151227.17" case 1'1 case end @@ -315908,14 +312718,14 @@ module \main$9 sync always update \bb $0\bb[1:0] end - attribute \src "libresoc.v:151238.3-151258.6" - process $proc$libresoc.v:151238$7634 + attribute \src "libresoc.v:151237.3-151257.6" + process $proc$libresoc.v:151237$7634 assign { } { } assign { } { } assign $0\bit_a[0:0] $1\bit_a[0:0] - attribute \src "libresoc.v:151239.5-151239.29" + attribute \src "libresoc.v:151238.5-151238.29" switch \initial - attribute \src "libresoc.v:151239.9-151239.17" + attribute \src "libresoc.v:151238.9-151238.17" case 1'1 case end @@ -315952,14 +312762,14 @@ module \main$9 sync always update \bit_a $0\bit_a[0:0] end - attribute \src "libresoc.v:151259.3-151279.6" - process $proc$libresoc.v:151259$7635 + attribute \src "libresoc.v:151258.3-151278.6" + process $proc$libresoc.v:151258$7635 assign { } { } assign { } { } assign $0\bit_b[0:0] $1\bit_b[0:0] - attribute \src "libresoc.v:151260.5-151260.29" + attribute \src "libresoc.v:151259.5-151259.29" switch \initial - attribute \src "libresoc.v:151260.9-151260.17" + attribute \src "libresoc.v:151259.9-151259.17" case 1'1 case end @@ -315996,14 +312806,14 @@ module \main$9 sync always update \bit_b $0\bit_b[0:0] end - attribute \src "libresoc.v:151280.3-151290.6" - process $proc$libresoc.v:151280$7636 + attribute \src "libresoc.v:151279.3-151289.6" + process $proc$libresoc.v:151279$7636 assign { } { } assign { } { } assign $0\bit_o[0:0] $1\bit_o[0:0] - attribute \src "libresoc.v:151281.5-151281.29" + attribute \src "libresoc.v:151280.5-151280.29" switch \initial - attribute \src "libresoc.v:151281.9-151281.17" + attribute \src "libresoc.v:151280.9-151280.17" case 1'1 case end @@ -316019,14 +312829,14 @@ module \main$9 sync always update \bit_o $0\bit_o[0:0] end - attribute \src "libresoc.v:151291.3-151301.6" - process $proc$libresoc.v:151291$7637 + attribute \src "libresoc.v:151290.3-151300.6" + process $proc$libresoc.v:151290$7637 assign { } { } assign { } { } assign $0\full_cr$5[31:0]$7638 $1\full_cr$5[31:0]$7639 - attribute \src "libresoc.v:151292.5-151292.29" + attribute \src "libresoc.v:151291.5-151291.29" switch \initial - attribute \src "libresoc.v:151292.9-151292.17" + attribute \src "libresoc.v:151291.9-151291.17" case 1'1 case end @@ -316042,501 +312852,501 @@ module \main$9 sync always update \full_cr$5 $0\full_cr$5[31:0]$7638 end - connect \$10 $sub$libresoc.v:151064$7609_Y - connect \$13 $sub$libresoc.v:151065$7610_Y - connect \$16 $sub$libresoc.v:151066$7611_Y - connect \$18 $ternary$libresoc.v:151067$7612_Y - connect \$20 $ternary$libresoc.v:151068$7613_Y - connect \$22 $ternary$libresoc.v:151069$7614_Y - connect \$24 $pos$libresoc.v:151070$7616_Y - connect \$27 $ternary$libresoc.v:151071$7617_Y - connect \$26 $pos$libresoc.v:151072$7619_Y - connect \$7 $pos$libresoc.v:151073$7621_Y + connect \$10 $sub$libresoc.v:151063$7609_Y + connect \$13 $sub$libresoc.v:151064$7610_Y + connect \$16 $sub$libresoc.v:151065$7611_Y + connect \$18 $ternary$libresoc.v:151066$7612_Y + connect \$20 $ternary$libresoc.v:151067$7613_Y + connect \$22 $ternary$libresoc.v:151068$7614_Y + connect \$24 $pos$libresoc.v:151069$7616_Y + connect \$27 $ternary$libresoc.v:151070$7617_Y + connect \$26 $pos$libresoc.v:151071$7619_Y + connect \$7 $pos$libresoc.v:151072$7621_Y connect \$9 \$10 connect \$12 \$13 connect \$15 \$16 connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \muxid$1 \muxid end -attribute \src "libresoc.v:151311.1-152472.10" +attribute \src "libresoc.v:151310.1-152471.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0" attribute \generator "nMigen" module \mul0 - attribute \src "libresoc.v:152043.3-152044.25" + attribute \src "libresoc.v:152042.3-152043.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:152041.3-152042.40" + attribute \src "libresoc.v:152040.3-152041.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:152384.3-152392.6" + attribute \src "libresoc.v:152383.3-152391.6" wire $0\alu_l_r_alu$next[0:0]$7846 - attribute \src "libresoc.v:151969.3-151970.39" + attribute \src "libresoc.v:151968.3-151969.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire width 14 $0\alu_mul0_mul_op__fn_unit$next[13:0]$7771 - attribute \src "libresoc.v:151997.3-151998.65" + attribute \src "libresoc.v:151996.3-151997.65" wire width 14 $0\alu_mul0_mul_op__fn_unit[13:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7772 - attribute \src "libresoc.v:151999.3-152000.79" + attribute \src "libresoc.v:151998.3-151999.79" wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7773 - attribute \src "libresoc.v:152001.3-152002.75" + attribute \src "libresoc.v:152000.3-152001.75" wire $0\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7774 - attribute \src "libresoc.v:152017.3-152018.59" + attribute \src "libresoc.v:152016.3-152017.59" wire width 32 $0\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7775 - attribute \src "libresoc.v:151995.3-151996.69" + attribute \src "libresoc.v:151994.3-151995.69" wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7776 - attribute \src "libresoc.v:152013.3-152014.67" + attribute \src "libresoc.v:152012.3-152013.67" wire $0\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7777 - attribute \src "libresoc.v:152015.3-152016.69" + attribute \src "libresoc.v:152014.3-152015.69" wire $0\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7778 - attribute \src "libresoc.v:152007.3-152008.63" + attribute \src "libresoc.v:152006.3-152007.63" wire $0\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7779 - attribute \src "libresoc.v:152009.3-152010.63" + attribute \src "libresoc.v:152008.3-152009.63" wire $0\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7780 - attribute \src "libresoc.v:152005.3-152006.63" + attribute \src "libresoc.v:152004.3-152005.63" wire $0\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 - attribute \src "libresoc.v:152003.3-152004.63" + attribute \src "libresoc.v:152002.3-152003.63" wire $0\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7782 - attribute \src "libresoc.v:152011.3-152012.69" + attribute \src "libresoc.v:152010.3-152011.69" wire $0\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:152375.3-152383.6" + attribute \src "libresoc.v:152374.3-152382.6" wire $0\alui_l_r_alui$next[0:0]$7843 - attribute \src "libresoc.v:151971.3-151972.43" + attribute \src "libresoc.v:151970.3-151971.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:152257.3-152278.6" + attribute \src "libresoc.v:152256.3-152277.6" wire width 64 $0\data_r0__o$next[63:0]$7802 - attribute \src "libresoc.v:151991.3-151992.37" + attribute \src "libresoc.v:151990.3-151991.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:152257.3-152278.6" + attribute \src "libresoc.v:152256.3-152277.6" wire $0\data_r0__o_ok$next[0:0]$7803 - attribute \src "libresoc.v:151993.3-151994.43" + attribute \src "libresoc.v:151992.3-151993.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:152279.3-152300.6" + attribute \src "libresoc.v:152278.3-152299.6" wire width 4 $0\data_r1__cr_a$next[3:0]$7810 - attribute \src "libresoc.v:151987.3-151988.43" + attribute \src "libresoc.v:151986.3-151987.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:152279.3-152300.6" + attribute \src "libresoc.v:152278.3-152299.6" wire $0\data_r1__cr_a_ok$next[0:0]$7811 - attribute \src "libresoc.v:151989.3-151990.49" + attribute \src "libresoc.v:151988.3-151989.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:152301.3-152322.6" + attribute \src "libresoc.v:152300.3-152321.6" wire width 2 $0\data_r2__xer_ov$next[1:0]$7818 - attribute \src "libresoc.v:151983.3-151984.47" + attribute \src "libresoc.v:151982.3-151983.47" wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:152301.3-152322.6" + attribute \src "libresoc.v:152300.3-152321.6" wire $0\data_r2__xer_ov_ok$next[0:0]$7819 - attribute \src "libresoc.v:151985.3-151986.53" + attribute \src "libresoc.v:151984.3-151985.53" wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:152323.3-152344.6" + attribute \src "libresoc.v:152322.3-152343.6" wire $0\data_r3__xer_so$next[0:0]$7826 - attribute \src "libresoc.v:151979.3-151980.47" + attribute \src "libresoc.v:151978.3-151979.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:152323.3-152344.6" + attribute \src "libresoc.v:152322.3-152343.6" wire $0\data_r3__xer_so_ok$next[0:0]$7827 - attribute \src "libresoc.v:151981.3-151982.53" + attribute \src "libresoc.v:151980.3-151981.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:152393.3-152402.6" + attribute \src "libresoc.v:152392.3-152401.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:152403.3-152412.6" + attribute \src "libresoc.v:152402.3-152411.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:152413.3-152422.6" + attribute \src "libresoc.v:152412.3-152421.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:152423.3-152432.6" + attribute \src "libresoc.v:152422.3-152431.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:151312.7-151312.20" + attribute \src "libresoc.v:151311.7-151311.20" wire $0\initial[0:0] - attribute \src "libresoc.v:152179.3-152187.6" + attribute \src "libresoc.v:152178.3-152186.6" wire $0\opc_l_r_opc$next[0:0]$7756 - attribute \src "libresoc.v:152027.3-152028.39" + attribute \src "libresoc.v:152026.3-152027.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:152170.3-152178.6" + attribute \src "libresoc.v:152169.3-152177.6" wire $0\opc_l_s_opc$next[0:0]$7753 - attribute \src "libresoc.v:152029.3-152030.39" + attribute \src "libresoc.v:152028.3-152029.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:152433.3-152441.6" + attribute \src "libresoc.v:152432.3-152440.6" wire width 4 $0\prev_wr_go$next[3:0]$7853 - attribute \src "libresoc.v:152039.3-152040.37" + attribute \src "libresoc.v:152038.3-152039.37" wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:152124.3-152133.6" + attribute \src "libresoc.v:152123.3-152132.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:152215.3-152223.6" + attribute \src "libresoc.v:152214.3-152222.6" wire width 4 $0\req_l_r_req$next[3:0]$7768 - attribute \src "libresoc.v:152019.3-152020.39" + attribute \src "libresoc.v:152018.3-152019.39" wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:152206.3-152214.6" + attribute \src "libresoc.v:152205.3-152213.6" wire width 4 $0\req_l_s_req$next[3:0]$7765 - attribute \src "libresoc.v:152021.3-152022.39" + attribute \src "libresoc.v:152020.3-152021.39" wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:152143.3-152151.6" + attribute \src "libresoc.v:152142.3-152150.6" wire $0\rok_l_r_rdok$next[0:0]$7744 - attribute \src "libresoc.v:152035.3-152036.41" + attribute \src "libresoc.v:152034.3-152035.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:152134.3-152142.6" + attribute \src "libresoc.v:152133.3-152141.6" wire $0\rok_l_s_rdok$next[0:0]$7741 - attribute \src "libresoc.v:152037.3-152038.41" + attribute \src "libresoc.v:152036.3-152037.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:152161.3-152169.6" + attribute \src "libresoc.v:152160.3-152168.6" wire $0\rst_l_r_rst$next[0:0]$7750 - attribute \src "libresoc.v:152031.3-152032.39" + attribute \src "libresoc.v:152030.3-152031.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:152152.3-152160.6" + attribute \src "libresoc.v:152151.3-152159.6" wire $0\rst_l_s_rst$next[0:0]$7747 - attribute \src "libresoc.v:152033.3-152034.39" + attribute \src "libresoc.v:152032.3-152033.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:152197.3-152205.6" + attribute \src "libresoc.v:152196.3-152204.6" wire width 3 $0\src_l_r_src$next[2:0]$7762 - attribute \src "libresoc.v:152023.3-152024.39" + attribute \src "libresoc.v:152022.3-152023.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:152188.3-152196.6" + attribute \src "libresoc.v:152187.3-152195.6" wire width 3 $0\src_l_s_src$next[2:0]$7759 - attribute \src "libresoc.v:152025.3-152026.39" + attribute \src "libresoc.v:152024.3-152025.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:152345.3-152354.6" + attribute \src "libresoc.v:152344.3-152353.6" wire width 64 $0\src_r0$next[63:0]$7834 - attribute \src "libresoc.v:151977.3-151978.29" + attribute \src "libresoc.v:151976.3-151977.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:152355.3-152364.6" + attribute \src "libresoc.v:152354.3-152363.6" wire width 64 $0\src_r1$next[63:0]$7837 - attribute \src "libresoc.v:151975.3-151976.29" + attribute \src "libresoc.v:151974.3-151975.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:152365.3-152374.6" + attribute \src "libresoc.v:152364.3-152373.6" wire $0\src_r2$next[0:0]$7840 - attribute \src "libresoc.v:151973.3-151974.29" + attribute \src "libresoc.v:151972.3-151973.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:151436.7-151436.24" + attribute \src "libresoc.v:151435.7-151435.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:151446.7-151446.26" + attribute \src "libresoc.v:151445.7-151445.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:152384.3-152392.6" + attribute \src "libresoc.v:152383.3-152391.6" wire $1\alu_l_r_alu$next[0:0]$7847 - attribute \src "libresoc.v:151454.7-151454.25" + attribute \src "libresoc.v:151453.7-151453.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire width 14 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 - attribute \src "libresoc.v:151477.14-151477.49" + attribute \src "libresoc.v:151476.14-151476.49" wire width 14 $1\alu_mul0_mul_op__fn_unit[13:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 - attribute \src "libresoc.v:151481.14-151481.68" + attribute \src "libresoc.v:151480.14-151480.68" wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 - attribute \src "libresoc.v:151485.7-151485.43" + attribute \src "libresoc.v:151484.7-151484.43" wire $1\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7786 - attribute \src "libresoc.v:151489.14-151489.43" + attribute \src "libresoc.v:151488.14-151488.43" wire width 32 $1\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 - attribute \src "libresoc.v:151568.13-151568.47" + attribute \src "libresoc.v:151567.13-151567.47" wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 - attribute \src "libresoc.v:151572.7-151572.39" + attribute \src "libresoc.v:151571.7-151571.39" wire $1\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 - attribute \src "libresoc.v:151576.7-151576.40" + attribute \src "libresoc.v:151575.7-151575.40" wire $1\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 - attribute \src "libresoc.v:151580.7-151580.37" + attribute \src "libresoc.v:151579.7-151579.37" wire $1\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 - attribute \src "libresoc.v:151584.7-151584.37" + attribute \src "libresoc.v:151583.7-151583.37" wire $1\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 - attribute \src "libresoc.v:151588.7-151588.37" + attribute \src "libresoc.v:151587.7-151587.37" wire $1\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 - attribute \src "libresoc.v:151592.7-151592.37" + attribute \src "libresoc.v:151591.7-151591.37" wire $1\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 - attribute \src "libresoc.v:151596.7-151596.40" + attribute \src "libresoc.v:151595.7-151595.40" wire $1\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:152375.3-152383.6" + attribute \src "libresoc.v:152374.3-152382.6" wire $1\alui_l_r_alui$next[0:0]$7844 - attribute \src "libresoc.v:151626.7-151626.27" + attribute \src "libresoc.v:151625.7-151625.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:152257.3-152278.6" + attribute \src "libresoc.v:152256.3-152277.6" wire width 64 $1\data_r0__o$next[63:0]$7804 - attribute \src "libresoc.v:151660.14-151660.47" + attribute \src "libresoc.v:151659.14-151659.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:152257.3-152278.6" + attribute \src "libresoc.v:152256.3-152277.6" wire $1\data_r0__o_ok$next[0:0]$7805 - attribute \src "libresoc.v:151664.7-151664.27" + attribute \src "libresoc.v:151663.7-151663.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:152279.3-152300.6" + attribute \src "libresoc.v:152278.3-152299.6" wire width 4 $1\data_r1__cr_a$next[3:0]$7812 - attribute \src "libresoc.v:151668.13-151668.33" + attribute \src "libresoc.v:151667.13-151667.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:152279.3-152300.6" + attribute \src "libresoc.v:152278.3-152299.6" wire $1\data_r1__cr_a_ok$next[0:0]$7813 - attribute \src "libresoc.v:151672.7-151672.30" + attribute \src "libresoc.v:151671.7-151671.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:152301.3-152322.6" + attribute \src "libresoc.v:152300.3-152321.6" wire width 2 $1\data_r2__xer_ov$next[1:0]$7820 - attribute \src "libresoc.v:151676.13-151676.35" + attribute \src "libresoc.v:151675.13-151675.35" wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:152301.3-152322.6" + attribute \src "libresoc.v:152300.3-152321.6" wire $1\data_r2__xer_ov_ok$next[0:0]$7821 - attribute \src "libresoc.v:151680.7-151680.32" + attribute \src "libresoc.v:151679.7-151679.32" wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:152323.3-152344.6" + attribute \src "libresoc.v:152322.3-152343.6" wire $1\data_r3__xer_so$next[0:0]$7828 - attribute \src "libresoc.v:151684.7-151684.29" + attribute \src "libresoc.v:151683.7-151683.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:152323.3-152344.6" + attribute \src "libresoc.v:152322.3-152343.6" wire $1\data_r3__xer_so_ok$next[0:0]$7829 - attribute \src "libresoc.v:151688.7-151688.32" + attribute \src "libresoc.v:151687.7-151687.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:152393.3-152402.6" + attribute \src "libresoc.v:152392.3-152401.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:152403.3-152412.6" + attribute \src "libresoc.v:152402.3-152411.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:152413.3-152422.6" + attribute \src "libresoc.v:152412.3-152421.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:152423.3-152432.6" + attribute \src "libresoc.v:152422.3-152431.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:152179.3-152187.6" + attribute \src "libresoc.v:152178.3-152186.6" wire $1\opc_l_r_opc$next[0:0]$7757 - attribute \src "libresoc.v:151708.7-151708.25" + attribute \src "libresoc.v:151707.7-151707.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:152170.3-152178.6" + attribute \src "libresoc.v:152169.3-152177.6" wire $1\opc_l_s_opc$next[0:0]$7754 - attribute \src "libresoc.v:151712.7-151712.25" + attribute \src "libresoc.v:151711.7-151711.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:152433.3-152441.6" + attribute \src "libresoc.v:152432.3-152440.6" wire width 4 $1\prev_wr_go$next[3:0]$7854 - attribute \src "libresoc.v:151830.13-151830.30" + attribute \src "libresoc.v:151829.13-151829.30" wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:152124.3-152133.6" + attribute \src "libresoc.v:152123.3-152132.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:152215.3-152223.6" + attribute \src "libresoc.v:152214.3-152222.6" wire width 4 $1\req_l_r_req$next[3:0]$7769 - attribute \src "libresoc.v:151838.13-151838.31" + attribute \src "libresoc.v:151837.13-151837.31" wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:152206.3-152214.6" + attribute \src "libresoc.v:152205.3-152213.6" wire width 4 $1\req_l_s_req$next[3:0]$7766 - attribute \src "libresoc.v:151842.13-151842.31" + attribute \src "libresoc.v:151841.13-151841.31" wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:152143.3-152151.6" + attribute \src "libresoc.v:152142.3-152150.6" wire $1\rok_l_r_rdok$next[0:0]$7745 - attribute \src "libresoc.v:151854.7-151854.26" + attribute \src "libresoc.v:151853.7-151853.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:152134.3-152142.6" + attribute \src "libresoc.v:152133.3-152141.6" wire $1\rok_l_s_rdok$next[0:0]$7742 - attribute \src "libresoc.v:151858.7-151858.26" + attribute \src "libresoc.v:151857.7-151857.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:152161.3-152169.6" + attribute \src "libresoc.v:152160.3-152168.6" wire $1\rst_l_r_rst$next[0:0]$7751 - attribute \src "libresoc.v:151862.7-151862.25" + attribute \src "libresoc.v:151861.7-151861.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:152152.3-152160.6" + attribute \src "libresoc.v:152151.3-152159.6" wire $1\rst_l_s_rst$next[0:0]$7748 - attribute \src "libresoc.v:151866.7-151866.25" + attribute \src "libresoc.v:151865.7-151865.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:152197.3-152205.6" + attribute \src "libresoc.v:152196.3-152204.6" wire width 3 $1\src_l_r_src$next[2:0]$7763 - attribute \src "libresoc.v:151880.13-151880.31" + attribute \src "libresoc.v:151879.13-151879.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:152188.3-152196.6" + attribute \src "libresoc.v:152187.3-152195.6" wire width 3 $1\src_l_s_src$next[2:0]$7760 - attribute \src "libresoc.v:151884.13-151884.31" + attribute \src "libresoc.v:151883.13-151883.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:152345.3-152354.6" + attribute \src "libresoc.v:152344.3-152353.6" wire width 64 $1\src_r0$next[63:0]$7835 - attribute \src "libresoc.v:151890.14-151890.43" + attribute \src "libresoc.v:151889.14-151889.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:152355.3-152364.6" + attribute \src "libresoc.v:152354.3-152363.6" wire width 64 $1\src_r1$next[63:0]$7838 - attribute \src "libresoc.v:151894.14-151894.43" + attribute \src "libresoc.v:151893.14-151893.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:152365.3-152374.6" + attribute \src "libresoc.v:152364.3-152373.6" wire $1\src_r2$next[0:0]$7841 - attribute \src "libresoc.v:151898.7-151898.20" + attribute \src "libresoc.v:151897.7-151897.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 - attribute \src "libresoc.v:152224.3-152256.6" + attribute \src "libresoc.v:152223.3-152255.6" wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 - attribute \src "libresoc.v:152257.3-152278.6" + attribute \src "libresoc.v:152256.3-152277.6" wire width 64 $2\data_r0__o$next[63:0]$7806 - attribute \src "libresoc.v:152257.3-152278.6" + attribute \src "libresoc.v:152256.3-152277.6" wire $2\data_r0__o_ok$next[0:0]$7807 - attribute \src "libresoc.v:152279.3-152300.6" + attribute \src "libresoc.v:152278.3-152299.6" wire width 4 $2\data_r1__cr_a$next[3:0]$7814 - attribute \src "libresoc.v:152279.3-152300.6" + attribute \src "libresoc.v:152278.3-152299.6" wire $2\data_r1__cr_a_ok$next[0:0]$7815 - attribute \src "libresoc.v:152301.3-152322.6" + attribute \src "libresoc.v:152300.3-152321.6" wire width 2 $2\data_r2__xer_ov$next[1:0]$7822 - attribute \src "libresoc.v:152301.3-152322.6" + attribute \src "libresoc.v:152300.3-152321.6" wire $2\data_r2__xer_ov_ok$next[0:0]$7823 - attribute \src "libresoc.v:152323.3-152344.6" + attribute \src "libresoc.v:152322.3-152343.6" wire $2\data_r3__xer_so$next[0:0]$7830 - attribute \src "libresoc.v:152323.3-152344.6" + attribute \src "libresoc.v:152322.3-152343.6" wire $2\data_r3__xer_so_ok$next[0:0]$7831 - attribute \src "libresoc.v:152257.3-152278.6" + attribute \src "libresoc.v:152256.3-152277.6" wire $3\data_r0__o_ok$next[0:0]$7808 - attribute \src "libresoc.v:152279.3-152300.6" + attribute \src "libresoc.v:152278.3-152299.6" wire $3\data_r1__cr_a_ok$next[0:0]$7816 - attribute \src "libresoc.v:152301.3-152322.6" + attribute \src "libresoc.v:152300.3-152321.6" wire $3\data_r2__xer_ov_ok$next[0:0]$7824 - attribute \src "libresoc.v:152323.3-152344.6" + attribute \src "libresoc.v:152322.3-152343.6" wire $3\data_r3__xer_so_ok$next[0:0]$7832 - attribute \src "libresoc.v:151909.19-151909.113" - wire width 3 $and$libresoc.v:151909$7641_Y + attribute \src "libresoc.v:151908.19-151908.113" + wire width 3 $and$libresoc.v:151908$7641_Y + attribute \src "libresoc.v:151909.19-151909.125" + wire $and$libresoc.v:151909$7642_Y attribute \src "libresoc.v:151910.19-151910.125" - wire $and$libresoc.v:151910$7642_Y + wire $and$libresoc.v:151910$7643_Y attribute \src "libresoc.v:151911.19-151911.125" - wire $and$libresoc.v:151911$7643_Y + wire $and$libresoc.v:151911$7644_Y attribute \src "libresoc.v:151912.19-151912.125" - wire $and$libresoc.v:151912$7644_Y - attribute \src "libresoc.v:151913.19-151913.125" - wire $and$libresoc.v:151913$7645_Y - attribute \src "libresoc.v:151914.18-151914.110" - wire $and$libresoc.v:151914$7646_Y - attribute \src "libresoc.v:151915.19-151915.149" - wire width 4 $and$libresoc.v:151915$7647_Y - attribute \src "libresoc.v:151916.19-151916.121" - wire width 4 $and$libresoc.v:151916$7648_Y + wire $and$libresoc.v:151912$7645_Y + attribute \src "libresoc.v:151913.18-151913.110" + wire $and$libresoc.v:151913$7646_Y + attribute \src "libresoc.v:151914.19-151914.149" + wire width 4 $and$libresoc.v:151914$7647_Y + attribute \src "libresoc.v:151915.19-151915.121" + wire width 4 $and$libresoc.v:151915$7648_Y + attribute \src "libresoc.v:151916.19-151916.127" + wire $and$libresoc.v:151916$7649_Y attribute \src "libresoc.v:151917.19-151917.127" - wire $and$libresoc.v:151917$7649_Y + wire $and$libresoc.v:151917$7650_Y attribute \src "libresoc.v:151918.19-151918.127" - wire $and$libresoc.v:151918$7650_Y + wire $and$libresoc.v:151918$7651_Y attribute \src "libresoc.v:151919.19-151919.127" - wire $and$libresoc.v:151919$7651_Y - attribute \src "libresoc.v:151920.19-151920.127" - wire $and$libresoc.v:151920$7652_Y - attribute \src "libresoc.v:151922.18-151922.98" - wire $and$libresoc.v:151922$7654_Y - attribute \src "libresoc.v:151924.18-151924.100" - wire $and$libresoc.v:151924$7656_Y - attribute \src "libresoc.v:151925.18-151925.160" - wire width 4 $and$libresoc.v:151925$7657_Y - attribute \src "libresoc.v:151927.18-151927.119" - wire width 4 $and$libresoc.v:151927$7659_Y - attribute \src "libresoc.v:151930.17-151930.123" - wire $and$libresoc.v:151930$7662_Y - attribute \src "libresoc.v:151931.18-151931.116" - wire $and$libresoc.v:151931$7663_Y - attribute \src "libresoc.v:151936.18-151936.113" - wire $and$libresoc.v:151936$7668_Y - attribute \src "libresoc.v:151937.18-151937.125" - wire width 4 $and$libresoc.v:151937$7669_Y - attribute \src "libresoc.v:151939.18-151939.112" - wire $and$libresoc.v:151939$7671_Y + wire $and$libresoc.v:151919$7652_Y + attribute \src "libresoc.v:151921.18-151921.98" + wire $and$libresoc.v:151921$7654_Y + attribute \src "libresoc.v:151923.18-151923.100" + wire $and$libresoc.v:151923$7656_Y + attribute \src "libresoc.v:151924.18-151924.160" + wire width 4 $and$libresoc.v:151924$7657_Y + attribute \src "libresoc.v:151926.18-151926.119" + wire width 4 $and$libresoc.v:151926$7659_Y + attribute \src "libresoc.v:151929.17-151929.123" + wire $and$libresoc.v:151929$7662_Y + attribute \src "libresoc.v:151930.18-151930.116" + wire $and$libresoc.v:151930$7663_Y + attribute \src "libresoc.v:151935.18-151935.113" + wire $and$libresoc.v:151935$7668_Y + attribute \src "libresoc.v:151936.18-151936.125" + wire width 4 $and$libresoc.v:151936$7669_Y + attribute \src "libresoc.v:151938.18-151938.112" + wire $and$libresoc.v:151938$7671_Y + attribute \src "libresoc.v:151940.18-151940.126" + wire $and$libresoc.v:151940$7673_Y attribute \src "libresoc.v:151941.18-151941.126" - wire $and$libresoc.v:151941$7673_Y - attribute \src "libresoc.v:151942.18-151942.126" - wire $and$libresoc.v:151942$7674_Y - attribute \src "libresoc.v:151943.18-151943.117" - wire $and$libresoc.v:151943$7675_Y - attribute \src "libresoc.v:151949.18-151949.130" - wire $and$libresoc.v:151949$7681_Y - attribute \src "libresoc.v:151950.18-151950.124" - wire width 4 $and$libresoc.v:151950$7682_Y - attribute \src "libresoc.v:151952.18-151952.116" - wire $and$libresoc.v:151952$7684_Y - attribute \src "libresoc.v:151953.18-151953.119" - wire $and$libresoc.v:151953$7685_Y + wire $and$libresoc.v:151941$7674_Y + attribute \src "libresoc.v:151942.18-151942.117" + wire $and$libresoc.v:151942$7675_Y + attribute \src "libresoc.v:151948.18-151948.130" + wire $and$libresoc.v:151948$7681_Y + attribute \src "libresoc.v:151949.18-151949.124" + wire width 4 $and$libresoc.v:151949$7682_Y + attribute \src "libresoc.v:151951.18-151951.116" + wire $and$libresoc.v:151951$7684_Y + attribute \src "libresoc.v:151952.18-151952.119" + wire $and$libresoc.v:151952$7685_Y + attribute \src "libresoc.v:151953.18-151953.121" + wire $and$libresoc.v:151953$7686_Y attribute \src "libresoc.v:151954.18-151954.121" - wire $and$libresoc.v:151954$7686_Y - attribute \src "libresoc.v:151955.18-151955.121" - wire $and$libresoc.v:151955$7687_Y - attribute \src "libresoc.v:151962.18-151962.134" - wire $and$libresoc.v:151962$7694_Y - attribute \src "libresoc.v:151964.18-151964.132" - wire $and$libresoc.v:151964$7696_Y - attribute \src "libresoc.v:151965.18-151965.149" - wire width 3 $and$libresoc.v:151965$7697_Y - attribute \src "libresoc.v:151967.18-151967.129" - wire width 3 $and$libresoc.v:151967$7699_Y - attribute \src "libresoc.v:151938.18-151938.113" - wire $eq$libresoc.v:151938$7670_Y - attribute \src "libresoc.v:151940.18-151940.119" - wire $eq$libresoc.v:151940$7672_Y - attribute \src "libresoc.v:151921.18-151921.97" - wire $not$libresoc.v:151921$7653_Y - attribute \src "libresoc.v:151923.18-151923.99" - wire $not$libresoc.v:151923$7655_Y - attribute \src "libresoc.v:151926.18-151926.113" - wire width 4 $not$libresoc.v:151926$7658_Y - attribute \src "libresoc.v:151929.18-151929.106" - wire $not$libresoc.v:151929$7661_Y - attribute \src "libresoc.v:151935.18-151935.120" - wire $not$libresoc.v:151935$7667_Y - attribute \src "libresoc.v:151946.17-151946.113" - wire width 3 $not$libresoc.v:151946$7678_Y - attribute \src "libresoc.v:151966.18-151966.131" - wire $not$libresoc.v:151966$7698_Y - attribute \src "libresoc.v:151968.18-151968.114" - wire width 3 $not$libresoc.v:151968$7700_Y - attribute \src "libresoc.v:151934.18-151934.112" - wire $or$libresoc.v:151934$7666_Y - attribute \src "libresoc.v:151944.18-151944.122" - wire $or$libresoc.v:151944$7676_Y - attribute \src "libresoc.v:151945.18-151945.124" - wire $or$libresoc.v:151945$7677_Y - attribute \src "libresoc.v:151947.18-151947.168" - wire width 4 $or$libresoc.v:151947$7679_Y - attribute \src "libresoc.v:151948.18-151948.155" - wire width 3 $or$libresoc.v:151948$7680_Y - attribute \src "libresoc.v:151951.18-151951.120" - wire width 4 $or$libresoc.v:151951$7683_Y - attribute \src "libresoc.v:151957.17-151957.117" - wire width 3 $or$libresoc.v:151957$7689_Y - attribute \src "libresoc.v:151963.17-151963.104" - wire $reduce_and$libresoc.v:151963$7695_Y + wire $and$libresoc.v:151954$7687_Y + attribute \src "libresoc.v:151961.18-151961.134" + wire $and$libresoc.v:151961$7694_Y + attribute \src "libresoc.v:151963.18-151963.132" + wire $and$libresoc.v:151963$7696_Y + attribute \src "libresoc.v:151964.18-151964.149" + wire width 3 $and$libresoc.v:151964$7697_Y + attribute \src "libresoc.v:151966.18-151966.129" + wire width 3 $and$libresoc.v:151966$7699_Y + attribute \src "libresoc.v:151937.18-151937.113" + wire $eq$libresoc.v:151937$7670_Y + attribute \src "libresoc.v:151939.18-151939.119" + wire $eq$libresoc.v:151939$7672_Y + attribute \src "libresoc.v:151920.18-151920.97" + wire $not$libresoc.v:151920$7653_Y + attribute \src "libresoc.v:151922.18-151922.99" + wire $not$libresoc.v:151922$7655_Y + attribute \src "libresoc.v:151925.18-151925.113" + wire width 4 $not$libresoc.v:151925$7658_Y attribute \src "libresoc.v:151928.18-151928.106" - wire $reduce_or$libresoc.v:151928$7660_Y - attribute \src "libresoc.v:151932.18-151932.113" - wire $reduce_or$libresoc.v:151932$7664_Y + wire $not$libresoc.v:151928$7661_Y + attribute \src "libresoc.v:151934.18-151934.120" + wire $not$libresoc.v:151934$7667_Y + attribute \src "libresoc.v:151945.17-151945.113" + wire width 3 $not$libresoc.v:151945$7678_Y + attribute \src "libresoc.v:151965.18-151965.131" + wire $not$libresoc.v:151965$7698_Y + attribute \src "libresoc.v:151967.18-151967.114" + wire width 3 $not$libresoc.v:151967$7700_Y attribute \src "libresoc.v:151933.18-151933.112" - wire $reduce_or$libresoc.v:151933$7665_Y - attribute \src "libresoc.v:151956.18-151956.160" - wire $ternary$libresoc.v:151956$7688_Y - attribute \src "libresoc.v:151958.18-151958.172" - wire width 64 $ternary$libresoc.v:151958$7690_Y - attribute \src "libresoc.v:151959.18-151959.118" - wire width 64 $ternary$libresoc.v:151959$7691_Y - attribute \src "libresoc.v:151960.18-151960.115" - wire width 64 $ternary$libresoc.v:151960$7692_Y - attribute \src "libresoc.v:151961.18-151961.118" - wire $ternary$libresoc.v:151961$7693_Y + wire $or$libresoc.v:151933$7666_Y + attribute \src "libresoc.v:151943.18-151943.122" + wire $or$libresoc.v:151943$7676_Y + attribute \src "libresoc.v:151944.18-151944.124" + wire $or$libresoc.v:151944$7677_Y + attribute \src "libresoc.v:151946.18-151946.168" + wire width 4 $or$libresoc.v:151946$7679_Y + attribute \src "libresoc.v:151947.18-151947.155" + wire width 3 $or$libresoc.v:151947$7680_Y + attribute \src "libresoc.v:151950.18-151950.120" + wire width 4 $or$libresoc.v:151950$7683_Y + attribute \src "libresoc.v:151956.17-151956.117" + wire width 3 $or$libresoc.v:151956$7689_Y + attribute \src "libresoc.v:151962.17-151962.104" + wire $reduce_and$libresoc.v:151962$7695_Y + attribute \src "libresoc.v:151927.18-151927.106" + wire $reduce_or$libresoc.v:151927$7660_Y + attribute \src "libresoc.v:151931.18-151931.113" + wire $reduce_or$libresoc.v:151931$7664_Y + attribute \src "libresoc.v:151932.18-151932.112" + wire $reduce_or$libresoc.v:151932$7665_Y + attribute \src "libresoc.v:151955.18-151955.160" + wire $ternary$libresoc.v:151955$7688_Y + attribute \src "libresoc.v:151957.18-151957.172" + wire width 64 $ternary$libresoc.v:151957$7690_Y + attribute \src "libresoc.v:151958.18-151958.118" + wire width 64 $ternary$libresoc.v:151958$7691_Y + attribute \src "libresoc.v:151959.18-151959.115" + wire width 64 $ternary$libresoc.v:151959$7692_Y + attribute \src "libresoc.v:151960.18-151960.118" + wire $ternary$libresoc.v:151960$7693_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -316923,7 +313733,7 @@ module \mul0 wire width 2 output 29 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 31 \dest4_o - attribute \src "libresoc.v:151312.7-151312.15" + attribute \src "libresoc.v:151311.7-151311.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 22 \o_ok @@ -317132,7 +313942,7 @@ module \mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 30 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:151909$7641 + cell $and $and$libresoc.v:151908$7641 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -317140,10 +313950,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$96 connect \B \$98 - connect \Y $and$libresoc.v:151909$7641_Y + connect \Y $and$libresoc.v:151908$7641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:151910$7642 + cell $and $and$libresoc.v:151909$7642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317151,10 +313961,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:151910$7642_Y + connect \Y $and$libresoc.v:151909$7642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:151911$7643 + cell $and $and$libresoc.v:151910$7643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317162,10 +313972,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:151911$7643_Y + connect \Y $and$libresoc.v:151910$7643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:151912$7644 + cell $and $and$libresoc.v:151911$7644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317173,10 +313983,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:151912$7644_Y + connect \Y $and$libresoc.v:151911$7644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:151913$7645 + cell $and $and$libresoc.v:151912$7645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317184,10 +313994,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:151913$7645_Y + connect \Y $and$libresoc.v:151912$7645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:151914$7646 + cell $and $and$libresoc.v:151913$7646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317195,10 +314005,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:151914$7646_Y + connect \Y $and$libresoc.v:151913$7646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:151915$7647 + cell $and $and$libresoc.v:151914$7647 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317206,10 +314016,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$102 \$104 \$106 \$108 } - connect \Y $and$libresoc.v:151915$7647_Y + connect \Y $and$libresoc.v:151914$7647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:151916$7648 + cell $and $and$libresoc.v:151915$7648 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317217,10 +314027,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:151916$7648_Y + connect \Y $and$libresoc.v:151915$7648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:151917$7649 + cell $and $and$libresoc.v:151916$7649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317228,10 +314038,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:151917$7649_Y + connect \Y $and$libresoc.v:151916$7649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:151918$7650 + cell $and $and$libresoc.v:151917$7650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317239,10 +314049,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:151918$7650_Y + connect \Y $and$libresoc.v:151917$7650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:151919$7651 + cell $and $and$libresoc.v:151918$7651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317250,10 +314060,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:151919$7651_Y + connect \Y $and$libresoc.v:151918$7651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:151920$7652 + cell $and $and$libresoc.v:151919$7652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317261,10 +314071,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:151920$7652_Y + connect \Y $and$libresoc.v:151919$7652_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:151922$7654 + cell $and $and$libresoc.v:151921$7654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317272,10 +314082,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:151922$7654_Y + connect \Y $and$libresoc.v:151921$7654_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:151924$7656 + cell $and $and$libresoc.v:151923$7656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317283,10 +314093,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:151924$7656_Y + connect \Y $and$libresoc.v:151923$7656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:151925$7657 + cell $and $and$libresoc.v:151924$7657 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317294,10 +314104,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:151925$7657_Y + connect \Y $and$libresoc.v:151924$7657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:151927$7659 + cell $and $and$libresoc.v:151926$7659 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317305,10 +314115,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:151927$7659_Y + connect \Y $and$libresoc.v:151926$7659_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:151930$7662 + cell $and $and$libresoc.v:151929$7662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317316,10 +314126,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:151930$7662_Y + connect \Y $and$libresoc.v:151929$7662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:151931$7663 + cell $and $and$libresoc.v:151930$7663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317327,10 +314137,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:151931$7663_Y + connect \Y $and$libresoc.v:151930$7663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:151936$7668 + cell $and $and$libresoc.v:151935$7668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317338,10 +314148,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:151936$7668_Y + connect \Y $and$libresoc.v:151935$7668_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:151937$7669 + cell $and $and$libresoc.v:151936$7669 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317349,10 +314159,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:151937$7669_Y + connect \Y $and$libresoc.v:151936$7669_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:151939$7671 + cell $and $and$libresoc.v:151938$7671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317360,10 +314170,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:151939$7671_Y + connect \Y $and$libresoc.v:151938$7671_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:151941$7673 + cell $and $and$libresoc.v:151940$7673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317371,10 +314181,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_mul0_n_ready_i - connect \Y $and$libresoc.v:151941$7673_Y + connect \Y $and$libresoc.v:151940$7673_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:151942$7674 + cell $and $and$libresoc.v:151941$7674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317382,10 +314192,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_mul0_n_valid_o - connect \Y $and$libresoc.v:151942$7674_Y + connect \Y $and$libresoc.v:151941$7674_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:151943$7675 + cell $and $and$libresoc.v:151942$7675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317393,10 +314203,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:151943$7675_Y + connect \Y $and$libresoc.v:151942$7675_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:151949$7681 + cell $and $and$libresoc.v:151948$7681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317404,10 +314214,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:151949$7681_Y + connect \Y $and$libresoc.v:151948$7681_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:151950$7682 + cell $and $and$libresoc.v:151949$7682 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317415,10 +314225,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:151950$7682_Y + connect \Y $and$libresoc.v:151949$7682_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:151952$7684 + cell $and $and$libresoc.v:151951$7684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317426,10 +314236,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:151952$7684_Y + connect \Y $and$libresoc.v:151951$7684_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:151953$7685 + cell $and $and$libresoc.v:151952$7685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317437,10 +314247,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:151953$7685_Y + connect \Y $and$libresoc.v:151952$7685_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:151954$7686 + cell $and $and$libresoc.v:151953$7686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317448,10 +314258,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:151954$7686_Y + connect \Y $and$libresoc.v:151953$7686_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:151955$7687 + cell $and $and$libresoc.v:151954$7687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317459,10 +314269,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:151955$7687_Y + connect \Y $and$libresoc.v:151954$7687_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:151962$7694 + cell $and $and$libresoc.v:151961$7694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317470,10 +314280,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:151962$7694_Y + connect \Y $and$libresoc.v:151961$7694_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:151964$7696 + cell $and $and$libresoc.v:151963$7696 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317481,10 +314291,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:151964$7696_Y + connect \Y $and$libresoc.v:151963$7696_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:151965$7697 + cell $and $and$libresoc.v:151964$7697 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -317492,10 +314302,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:151965$7697_Y + connect \Y $and$libresoc.v:151964$7697_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:151967$7699 + cell $and $and$libresoc.v:151966$7699 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -317503,10 +314313,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$92 connect \B { 1'1 \$94 1'1 } - connect \Y $and$libresoc.v:151967$7699_Y + connect \Y $and$libresoc.v:151966$7699_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:151938$7670 + cell $eq $eq$libresoc.v:151937$7670 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317514,10 +314324,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:151938$7670_Y + connect \Y $eq$libresoc.v:151937$7670_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:151940$7672 + cell $eq $eq$libresoc.v:151939$7672 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317525,74 +314335,74 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:151940$7672_Y + connect \Y $eq$libresoc.v:151939$7672_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:151921$7653 + cell $not $not$libresoc.v:151920$7653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:151921$7653_Y + connect \Y $not$libresoc.v:151920$7653_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:151923$7655 + cell $not $not$libresoc.v:151922$7655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:151923$7655_Y + connect \Y $not$libresoc.v:151922$7655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:151926$7658 + cell $not $not$libresoc.v:151925$7658 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:151926$7658_Y + connect \Y $not$libresoc.v:151925$7658_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:151929$7661 + cell $not $not$libresoc.v:151928$7661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:151929$7661_Y + connect \Y $not$libresoc.v:151928$7661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:151935$7667 + cell $not $not$libresoc.v:151934$7667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_ready_i - connect \Y $not$libresoc.v:151935$7667_Y + connect \Y $not$libresoc.v:151934$7667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:151946$7678 + cell $not $not$libresoc.v:151945$7678 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:151946$7678_Y + connect \Y $not$libresoc.v:151945$7678_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:151966$7698 + cell $not $not$libresoc.v:151965$7698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_mul_op__imm_data__ok - connect \Y $not$libresoc.v:151966$7698_Y + connect \Y $not$libresoc.v:151965$7698_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:151968$7700 + cell $not $not$libresoc.v:151967$7700 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:151968$7700_Y + connect \Y $not$libresoc.v:151967$7700_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:151934$7666 + cell $or $or$libresoc.v:151933$7666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317600,10 +314410,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:151934$7666_Y + connect \Y $or$libresoc.v:151933$7666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:151944$7676 + cell $or $or$libresoc.v:151943$7676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317611,10 +314421,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:151944$7676_Y + connect \Y $or$libresoc.v:151943$7676_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:151945$7677 + cell $or $or$libresoc.v:151944$7677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317622,10 +314432,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:151945$7677_Y + connect \Y $or$libresoc.v:151944$7677_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:151947$7679 + cell $or $or$libresoc.v:151946$7679 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317633,10 +314443,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:151947$7679_Y + connect \Y $or$libresoc.v:151946$7679_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:151948$7680 + cell $or $or$libresoc.v:151947$7680 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -317644,10 +314454,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:151948$7680_Y + connect \Y $or$libresoc.v:151947$7680_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:151951$7683 + cell $or $or$libresoc.v:151950$7683 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -317655,10 +314465,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:151951$7683_Y + connect \Y $or$libresoc.v:151950$7683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:151957$7689 + cell $or $or$libresoc.v:151956$7689 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -317666,82 +314476,82 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:151957$7689_Y + connect \Y $or$libresoc.v:151956$7689_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:151963$7695 + cell $reduce_and $reduce_and$libresoc.v:151962$7695 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:151963$7695_Y + connect \Y $reduce_and$libresoc.v:151962$7695_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:151928$7660 + cell $reduce_or $reduce_or$libresoc.v:151927$7660 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:151928$7660_Y + connect \Y $reduce_or$libresoc.v:151927$7660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:151932$7664 + cell $reduce_or $reduce_or$libresoc.v:151931$7664 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:151932$7664_Y + connect \Y $reduce_or$libresoc.v:151931$7664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:151933$7665 + cell $reduce_or $reduce_or$libresoc.v:151932$7665 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:151933$7665_Y + connect \Y $reduce_or$libresoc.v:151932$7665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:151956$7688 + cell $mux $ternary$libresoc.v:151955$7688 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:151956$7688_Y + connect \Y $ternary$libresoc.v:151955$7688_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:151958$7690 + cell $mux $ternary$libresoc.v:151957$7690 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_mul0_mul_op__imm_data__data connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:151958$7690_Y + connect \Y $ternary$libresoc.v:151957$7690_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:151959$7691 + cell $mux $ternary$libresoc.v:151958$7691 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:151959$7691_Y + connect \Y $ternary$libresoc.v:151958$7691_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:151960$7692 + cell $mux $ternary$libresoc.v:151959$7692 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:151960$7692_Y + connect \Y $ternary$libresoc.v:151959$7692_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:151961$7693 + cell $mux $ternary$libresoc.v:151960$7693 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:151961$7693_Y + connect \Y $ternary$libresoc.v:151960$7693_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:152045.15-152051.4" + attribute \src "libresoc.v:152044.15-152050.4" cell \alu_l$107 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -317750,7 +314560,7 @@ module \mul0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:152052.12-152082.4" + attribute \src "libresoc.v:152051.12-152081.4" cell \alu_mul0 \alu_mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -317783,7 +314593,7 @@ module \mul0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:152083.16-152089.4" + attribute \src "libresoc.v:152082.16-152088.4" cell \alui_l$106 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -317792,7 +314602,7 @@ module \mul0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:152090.15-152096.4" + attribute \src "libresoc.v:152089.15-152095.4" cell \opc_l$102 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -317801,7 +314611,7 @@ module \mul0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:152097.15-152103.4" + attribute \src "libresoc.v:152096.15-152102.4" cell \req_l$103 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -317810,7 +314620,7 @@ module \mul0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:152104.15-152110.4" + attribute \src "libresoc.v:152103.15-152109.4" cell \rok_l$105 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -317819,7 +314629,7 @@ module \mul0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:152111.15-152116.4" + attribute \src "libresoc.v:152110.15-152115.4" cell \rst_l$104 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -317827,7 +314637,7 @@ module \mul0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:152117.15-152123.4" + attribute \src "libresoc.v:152116.15-152122.4" cell \src_l$101 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -317835,592 +314645,592 @@ module \mul0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:151312.7-151312.20" - process $proc$libresoc.v:151312$7855 + attribute \src "libresoc.v:151311.7-151311.20" + process $proc$libresoc.v:151311$7855 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:151436.7-151436.24" - process $proc$libresoc.v:151436$7856 + attribute \src "libresoc.v:151435.7-151435.24" + process $proc$libresoc.v:151435$7856 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:151446.7-151446.26" - process $proc$libresoc.v:151446$7857 + attribute \src "libresoc.v:151445.7-151445.26" + process $proc$libresoc.v:151445$7857 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:151454.7-151454.25" - process $proc$libresoc.v:151454$7858 + attribute \src "libresoc.v:151453.7-151453.25" + process $proc$libresoc.v:151453$7858 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:151477.14-151477.49" - process $proc$libresoc.v:151477$7859 + attribute \src "libresoc.v:151476.14-151476.49" + process $proc$libresoc.v:151476$7859 assign { } { } assign $1\alu_mul0_mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:151481.14-151481.68" - process $proc$libresoc.v:151481$7860 + attribute \src "libresoc.v:151480.14-151480.68" + process $proc$libresoc.v:151480$7860 assign { } { } assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:151485.7-151485.43" - process $proc$libresoc.v:151485$7861 + attribute \src "libresoc.v:151484.7-151484.43" + process $proc$libresoc.v:151484$7861 assign { } { } assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:151489.14-151489.43" - process $proc$libresoc.v:151489$7862 + attribute \src "libresoc.v:151488.14-151488.43" + process $proc$libresoc.v:151488$7862 assign { } { } assign $1\alu_mul0_mul_op__insn[31:0] 0 sync always sync init update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:151568.13-151568.47" - process $proc$libresoc.v:151568$7863 + attribute \src "libresoc.v:151567.13-151567.47" + process $proc$libresoc.v:151567$7863 assign { } { } assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:151572.7-151572.39" - process $proc$libresoc.v:151572$7864 + attribute \src "libresoc.v:151571.7-151571.39" + process $proc$libresoc.v:151571$7864 assign { } { } assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:151576.7-151576.40" - process $proc$libresoc.v:151576$7865 + attribute \src "libresoc.v:151575.7-151575.40" + process $proc$libresoc.v:151575$7865 assign { } { } assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:151580.7-151580.37" - process $proc$libresoc.v:151580$7866 + attribute \src "libresoc.v:151579.7-151579.37" + process $proc$libresoc.v:151579$7866 assign { } { } assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:151584.7-151584.37" - process $proc$libresoc.v:151584$7867 + attribute \src "libresoc.v:151583.7-151583.37" + process $proc$libresoc.v:151583$7867 assign { } { } assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:151588.7-151588.37" - process $proc$libresoc.v:151588$7868 + attribute \src "libresoc.v:151587.7-151587.37" + process $proc$libresoc.v:151587$7868 assign { } { } assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:151592.7-151592.37" - process $proc$libresoc.v:151592$7869 + attribute \src "libresoc.v:151591.7-151591.37" + process $proc$libresoc.v:151591$7869 assign { } { } assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:151596.7-151596.40" - process $proc$libresoc.v:151596$7870 + attribute \src "libresoc.v:151595.7-151595.40" + process $proc$libresoc.v:151595$7870 assign { } { } assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:151626.7-151626.27" - process $proc$libresoc.v:151626$7871 + attribute \src "libresoc.v:151625.7-151625.27" + process $proc$libresoc.v:151625$7871 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:151660.14-151660.47" - process $proc$libresoc.v:151660$7872 + attribute \src "libresoc.v:151659.14-151659.47" + process $proc$libresoc.v:151659$7872 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:151664.7-151664.27" - process $proc$libresoc.v:151664$7873 + attribute \src "libresoc.v:151663.7-151663.27" + process $proc$libresoc.v:151663$7873 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:151668.13-151668.33" - process $proc$libresoc.v:151668$7874 + attribute \src "libresoc.v:151667.13-151667.33" + process $proc$libresoc.v:151667$7874 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:151672.7-151672.30" - process $proc$libresoc.v:151672$7875 + attribute \src "libresoc.v:151671.7-151671.30" + process $proc$libresoc.v:151671$7875 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:151676.13-151676.35" - process $proc$libresoc.v:151676$7876 + attribute \src "libresoc.v:151675.13-151675.35" + process $proc$libresoc.v:151675$7876 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:151680.7-151680.32" - process $proc$libresoc.v:151680$7877 + attribute \src "libresoc.v:151679.7-151679.32" + process $proc$libresoc.v:151679$7877 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:151684.7-151684.29" - process $proc$libresoc.v:151684$7878 + attribute \src "libresoc.v:151683.7-151683.29" + process $proc$libresoc.v:151683$7878 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:151688.7-151688.32" - process $proc$libresoc.v:151688$7879 + attribute \src "libresoc.v:151687.7-151687.32" + process $proc$libresoc.v:151687$7879 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:151708.7-151708.25" - process $proc$libresoc.v:151708$7880 + attribute \src "libresoc.v:151707.7-151707.25" + process $proc$libresoc.v:151707$7880 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:151712.7-151712.25" - process $proc$libresoc.v:151712$7881 + attribute \src "libresoc.v:151711.7-151711.25" + process $proc$libresoc.v:151711$7881 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:151830.13-151830.30" - process $proc$libresoc.v:151830$7882 + attribute \src "libresoc.v:151829.13-151829.30" + process $proc$libresoc.v:151829$7882 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end - attribute \src "libresoc.v:151838.13-151838.31" - process $proc$libresoc.v:151838$7883 + attribute \src "libresoc.v:151837.13-151837.31" + process $proc$libresoc.v:151837$7883 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:151842.13-151842.31" - process $proc$libresoc.v:151842$7884 + attribute \src "libresoc.v:151841.13-151841.31" + process $proc$libresoc.v:151841$7884 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end - attribute \src "libresoc.v:151854.7-151854.26" - process $proc$libresoc.v:151854$7885 + attribute \src "libresoc.v:151853.7-151853.26" + process $proc$libresoc.v:151853$7885 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:151858.7-151858.26" - process $proc$libresoc.v:151858$7886 + attribute \src "libresoc.v:151857.7-151857.26" + process $proc$libresoc.v:151857$7886 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:151862.7-151862.25" - process $proc$libresoc.v:151862$7887 + attribute \src "libresoc.v:151861.7-151861.25" + process $proc$libresoc.v:151861$7887 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:151866.7-151866.25" - process $proc$libresoc.v:151866$7888 + attribute \src "libresoc.v:151865.7-151865.25" + process $proc$libresoc.v:151865$7888 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:151880.13-151880.31" - process $proc$libresoc.v:151880$7889 + attribute \src "libresoc.v:151879.13-151879.31" + process $proc$libresoc.v:151879$7889 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:151884.13-151884.31" - process $proc$libresoc.v:151884$7890 + attribute \src "libresoc.v:151883.13-151883.31" + process $proc$libresoc.v:151883$7890 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:151890.14-151890.43" - process $proc$libresoc.v:151890$7891 + attribute \src "libresoc.v:151889.14-151889.43" + process $proc$libresoc.v:151889$7891 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:151894.14-151894.43" - process $proc$libresoc.v:151894$7892 + attribute \src "libresoc.v:151893.14-151893.43" + process $proc$libresoc.v:151893$7892 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:151898.7-151898.20" - process $proc$libresoc.v:151898$7893 + attribute \src "libresoc.v:151897.7-151897.20" + process $proc$libresoc.v:151897$7893 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:151969.3-151970.39" - process $proc$libresoc.v:151969$7701 + attribute \src "libresoc.v:151968.3-151969.39" + process $proc$libresoc.v:151968$7701 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:151971.3-151972.43" - process $proc$libresoc.v:151971$7702 + attribute \src "libresoc.v:151970.3-151971.43" + process $proc$libresoc.v:151970$7702 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:151973.3-151974.29" - process $proc$libresoc.v:151973$7703 + attribute \src "libresoc.v:151972.3-151973.29" + process $proc$libresoc.v:151972$7703 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:151975.3-151976.29" - process $proc$libresoc.v:151975$7704 + attribute \src "libresoc.v:151974.3-151975.29" + process $proc$libresoc.v:151974$7704 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:151977.3-151978.29" - process $proc$libresoc.v:151977$7705 + attribute \src "libresoc.v:151976.3-151977.29" + process $proc$libresoc.v:151976$7705 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:151979.3-151980.47" - process $proc$libresoc.v:151979$7706 + attribute \src "libresoc.v:151978.3-151979.47" + process $proc$libresoc.v:151978$7706 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:151981.3-151982.53" - process $proc$libresoc.v:151981$7707 + attribute \src "libresoc.v:151980.3-151981.53" + process $proc$libresoc.v:151980$7707 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:151983.3-151984.47" - process $proc$libresoc.v:151983$7708 + attribute \src "libresoc.v:151982.3-151983.47" + process $proc$libresoc.v:151982$7708 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:151985.3-151986.53" - process $proc$libresoc.v:151985$7709 + attribute \src "libresoc.v:151984.3-151985.53" + process $proc$libresoc.v:151984$7709 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:151987.3-151988.43" - process $proc$libresoc.v:151987$7710 + attribute \src "libresoc.v:151986.3-151987.43" + process $proc$libresoc.v:151986$7710 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:151989.3-151990.49" - process $proc$libresoc.v:151989$7711 + attribute \src "libresoc.v:151988.3-151989.49" + process $proc$libresoc.v:151988$7711 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:151991.3-151992.37" - process $proc$libresoc.v:151991$7712 + attribute \src "libresoc.v:151990.3-151991.37" + process $proc$libresoc.v:151990$7712 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:151993.3-151994.43" - process $proc$libresoc.v:151993$7713 + attribute \src "libresoc.v:151992.3-151993.43" + process $proc$libresoc.v:151992$7713 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:151995.3-151996.69" - process $proc$libresoc.v:151995$7714 + attribute \src "libresoc.v:151994.3-151995.69" + process $proc$libresoc.v:151994$7714 assign { } { } assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:151997.3-151998.65" - process $proc$libresoc.v:151997$7715 + attribute \src "libresoc.v:151996.3-151997.65" + process $proc$libresoc.v:151996$7715 assign { } { } assign $0\alu_mul0_mul_op__fn_unit[13:0] \alu_mul0_mul_op__fn_unit$next sync posedge \coresync_clk update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:151999.3-152000.79" - process $proc$libresoc.v:151999$7716 + attribute \src "libresoc.v:151998.3-151999.79" + process $proc$libresoc.v:151998$7716 assign { } { } assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:152001.3-152002.75" - process $proc$libresoc.v:152001$7717 + attribute \src "libresoc.v:152000.3-152001.75" + process $proc$libresoc.v:152000$7717 assign { } { } assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:152003.3-152004.63" - process $proc$libresoc.v:152003$7718 + attribute \src "libresoc.v:152002.3-152003.63" + process $proc$libresoc.v:152002$7718 assign { } { } assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:152005.3-152006.63" - process $proc$libresoc.v:152005$7719 + attribute \src "libresoc.v:152004.3-152005.63" + process $proc$libresoc.v:152004$7719 assign { } { } assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:152007.3-152008.63" - process $proc$libresoc.v:152007$7720 + attribute \src "libresoc.v:152006.3-152007.63" + process $proc$libresoc.v:152006$7720 assign { } { } assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:152009.3-152010.63" - process $proc$libresoc.v:152009$7721 + attribute \src "libresoc.v:152008.3-152009.63" + process $proc$libresoc.v:152008$7721 assign { } { } assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:152011.3-152012.69" - process $proc$libresoc.v:152011$7722 + attribute \src "libresoc.v:152010.3-152011.69" + process $proc$libresoc.v:152010$7722 assign { } { } assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next sync posedge \coresync_clk update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:152013.3-152014.67" - process $proc$libresoc.v:152013$7723 + attribute \src "libresoc.v:152012.3-152013.67" + process $proc$libresoc.v:152012$7723 assign { } { } assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:152015.3-152016.69" - process $proc$libresoc.v:152015$7724 + attribute \src "libresoc.v:152014.3-152015.69" + process $proc$libresoc.v:152014$7724 assign { } { } assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:152017.3-152018.59" - process $proc$libresoc.v:152017$7725 + attribute \src "libresoc.v:152016.3-152017.59" + process $proc$libresoc.v:152016$7725 assign { } { } assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:152019.3-152020.39" - process $proc$libresoc.v:152019$7726 + attribute \src "libresoc.v:152018.3-152019.39" + process $proc$libresoc.v:152018$7726 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end - attribute \src "libresoc.v:152021.3-152022.39" - process $proc$libresoc.v:152021$7727 + attribute \src "libresoc.v:152020.3-152021.39" + process $proc$libresoc.v:152020$7727 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:152023.3-152024.39" - process $proc$libresoc.v:152023$7728 + attribute \src "libresoc.v:152022.3-152023.39" + process $proc$libresoc.v:152022$7728 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:152025.3-152026.39" - process $proc$libresoc.v:152025$7729 + attribute \src "libresoc.v:152024.3-152025.39" + process $proc$libresoc.v:152024$7729 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:152027.3-152028.39" - process $proc$libresoc.v:152027$7730 + attribute \src "libresoc.v:152026.3-152027.39" + process $proc$libresoc.v:152026$7730 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:152029.3-152030.39" - process $proc$libresoc.v:152029$7731 + attribute \src "libresoc.v:152028.3-152029.39" + process $proc$libresoc.v:152028$7731 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:152031.3-152032.39" - process $proc$libresoc.v:152031$7732 + attribute \src "libresoc.v:152030.3-152031.39" + process $proc$libresoc.v:152030$7732 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:152033.3-152034.39" - process $proc$libresoc.v:152033$7733 + attribute \src "libresoc.v:152032.3-152033.39" + process $proc$libresoc.v:152032$7733 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:152035.3-152036.41" - process $proc$libresoc.v:152035$7734 + attribute \src "libresoc.v:152034.3-152035.41" + process $proc$libresoc.v:152034$7734 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:152037.3-152038.41" - process $proc$libresoc.v:152037$7735 + attribute \src "libresoc.v:152036.3-152037.41" + process $proc$libresoc.v:152036$7735 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:152039.3-152040.37" - process $proc$libresoc.v:152039$7736 + attribute \src "libresoc.v:152038.3-152039.37" + process $proc$libresoc.v:152038$7736 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:152041.3-152042.40" - process $proc$libresoc.v:152041$7737 + attribute \src "libresoc.v:152040.3-152041.40" + process $proc$libresoc.v:152040$7737 assign { } { } assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:152043.3-152044.25" - process $proc$libresoc.v:152043$7738 + attribute \src "libresoc.v:152042.3-152043.25" + process $proc$libresoc.v:152042$7738 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:152124.3-152133.6" - process $proc$libresoc.v:152124$7739 + attribute \src "libresoc.v:152123.3-152132.6" + process $proc$libresoc.v:152123$7739 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:152125.5-152125.29" + attribute \src "libresoc.v:152124.5-152124.29" switch \initial - attribute \src "libresoc.v:152125.9-152125.17" + attribute \src "libresoc.v:152124.9-152124.17" case 1'1 case end @@ -318436,14 +315246,14 @@ module \mul0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:152134.3-152142.6" - process $proc$libresoc.v:152134$7740 + attribute \src "libresoc.v:152133.3-152141.6" + process $proc$libresoc.v:152133$7740 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$7741 $1\rok_l_s_rdok$next[0:0]$7742 - attribute \src "libresoc.v:152135.5-152135.29" + attribute \src "libresoc.v:152134.5-152134.29" switch \initial - attribute \src "libresoc.v:152135.9-152135.17" + attribute \src "libresoc.v:152134.9-152134.17" case 1'1 case end @@ -318459,14 +315269,14 @@ module \mul0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7741 end - attribute \src "libresoc.v:152143.3-152151.6" - process $proc$libresoc.v:152143$7743 + attribute \src "libresoc.v:152142.3-152150.6" + process $proc$libresoc.v:152142$7743 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$7744 $1\rok_l_r_rdok$next[0:0]$7745 - attribute \src "libresoc.v:152144.5-152144.29" + attribute \src "libresoc.v:152143.5-152143.29" switch \initial - attribute \src "libresoc.v:152144.9-152144.17" + attribute \src "libresoc.v:152143.9-152143.17" case 1'1 case end @@ -318482,14 +315292,14 @@ module \mul0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7744 end - attribute \src "libresoc.v:152152.3-152160.6" - process $proc$libresoc.v:152152$7746 + attribute \src "libresoc.v:152151.3-152159.6" + process $proc$libresoc.v:152151$7746 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$7747 $1\rst_l_s_rst$next[0:0]$7748 - attribute \src "libresoc.v:152153.5-152153.29" + attribute \src "libresoc.v:152152.5-152152.29" switch \initial - attribute \src "libresoc.v:152153.9-152153.17" + attribute \src "libresoc.v:152152.9-152152.17" case 1'1 case end @@ -318505,14 +315315,14 @@ module \mul0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7747 end - attribute \src "libresoc.v:152161.3-152169.6" - process $proc$libresoc.v:152161$7749 + attribute \src "libresoc.v:152160.3-152168.6" + process $proc$libresoc.v:152160$7749 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$7750 $1\rst_l_r_rst$next[0:0]$7751 - attribute \src "libresoc.v:152162.5-152162.29" + attribute \src "libresoc.v:152161.5-152161.29" switch \initial - attribute \src "libresoc.v:152162.9-152162.17" + attribute \src "libresoc.v:152161.9-152161.17" case 1'1 case end @@ -318528,14 +315338,14 @@ module \mul0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7750 end - attribute \src "libresoc.v:152170.3-152178.6" - process $proc$libresoc.v:152170$7752 + attribute \src "libresoc.v:152169.3-152177.6" + process $proc$libresoc.v:152169$7752 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$7753 $1\opc_l_s_opc$next[0:0]$7754 - attribute \src "libresoc.v:152171.5-152171.29" + attribute \src "libresoc.v:152170.5-152170.29" switch \initial - attribute \src "libresoc.v:152171.9-152171.17" + attribute \src "libresoc.v:152170.9-152170.17" case 1'1 case end @@ -318551,14 +315361,14 @@ module \mul0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7753 end - attribute \src "libresoc.v:152179.3-152187.6" - process $proc$libresoc.v:152179$7755 + attribute \src "libresoc.v:152178.3-152186.6" + process $proc$libresoc.v:152178$7755 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$7756 $1\opc_l_r_opc$next[0:0]$7757 - attribute \src "libresoc.v:152180.5-152180.29" + attribute \src "libresoc.v:152179.5-152179.29" switch \initial - attribute \src "libresoc.v:152180.9-152180.17" + attribute \src "libresoc.v:152179.9-152179.17" case 1'1 case end @@ -318574,14 +315384,14 @@ module \mul0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7756 end - attribute \src "libresoc.v:152188.3-152196.6" - process $proc$libresoc.v:152188$7758 + attribute \src "libresoc.v:152187.3-152195.6" + process $proc$libresoc.v:152187$7758 assign { } { } assign { } { } assign $0\src_l_s_src$next[2:0]$7759 $1\src_l_s_src$next[2:0]$7760 - attribute \src "libresoc.v:152189.5-152189.29" + attribute \src "libresoc.v:152188.5-152188.29" switch \initial - attribute \src "libresoc.v:152189.9-152189.17" + attribute \src "libresoc.v:152188.9-152188.17" case 1'1 case end @@ -318597,14 +315407,14 @@ module \mul0 sync always update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7759 end - attribute \src "libresoc.v:152197.3-152205.6" - process $proc$libresoc.v:152197$7761 + attribute \src "libresoc.v:152196.3-152204.6" + process $proc$libresoc.v:152196$7761 assign { } { } assign { } { } assign $0\src_l_r_src$next[2:0]$7762 $1\src_l_r_src$next[2:0]$7763 - attribute \src "libresoc.v:152198.5-152198.29" + attribute \src "libresoc.v:152197.5-152197.29" switch \initial - attribute \src "libresoc.v:152198.9-152198.17" + attribute \src "libresoc.v:152197.9-152197.17" case 1'1 case end @@ -318620,14 +315430,14 @@ module \mul0 sync always update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7762 end - attribute \src "libresoc.v:152206.3-152214.6" - process $proc$libresoc.v:152206$7764 + attribute \src "libresoc.v:152205.3-152213.6" + process $proc$libresoc.v:152205$7764 assign { } { } assign { } { } assign $0\req_l_s_req$next[3:0]$7765 $1\req_l_s_req$next[3:0]$7766 - attribute \src "libresoc.v:152207.5-152207.29" + attribute \src "libresoc.v:152206.5-152206.29" switch \initial - attribute \src "libresoc.v:152207.9-152207.17" + attribute \src "libresoc.v:152206.9-152206.17" case 1'1 case end @@ -318643,14 +315453,14 @@ module \mul0 sync always update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7765 end - attribute \src "libresoc.v:152215.3-152223.6" - process $proc$libresoc.v:152215$7767 + attribute \src "libresoc.v:152214.3-152222.6" + process $proc$libresoc.v:152214$7767 assign { } { } assign { } { } assign $0\req_l_r_req$next[3:0]$7768 $1\req_l_r_req$next[3:0]$7769 - attribute \src "libresoc.v:152216.5-152216.29" + attribute \src "libresoc.v:152215.5-152215.29" switch \initial - attribute \src "libresoc.v:152216.9-152216.17" + attribute \src "libresoc.v:152215.9-152215.17" case 1'1 case end @@ -318666,8 +315476,8 @@ module \mul0 sync always update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7768 end - attribute \src "libresoc.v:152224.3-152256.6" - process $proc$libresoc.v:152224$7770 + attribute \src "libresoc.v:152223.3-152255.6" + process $proc$libresoc.v:152223$7770 assign { } { } assign { } { } assign { } { } @@ -318710,9 +315520,9 @@ module \mul0 assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7779 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7780 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 - attribute \src "libresoc.v:152225.5-152225.29" + attribute \src "libresoc.v:152224.5-152224.29" switch \initial - attribute \src "libresoc.v:152225.9-152225.17" + attribute \src "libresoc.v:152224.9-152224.17" case 1'1 case end @@ -318785,8 +315595,8 @@ module \mul0 update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7782 end - attribute \src "libresoc.v:152257.3-152278.6" - process $proc$libresoc.v:152257$7801 + attribute \src "libresoc.v:152256.3-152277.6" + process $proc$libresoc.v:152256$7801 assign { } { } assign { } { } assign { } { } @@ -318796,9 +315606,9 @@ module \mul0 assign $0\data_r0__o$next[63:0]$7802 $2\data_r0__o$next[63:0]$7806 assign { } { } assign $0\data_r0__o_ok$next[0:0]$7803 $3\data_r0__o_ok$next[0:0]$7808 - attribute \src "libresoc.v:152258.5-152258.29" + attribute \src "libresoc.v:152257.5-152257.29" switch \initial - attribute \src "libresoc.v:152258.9-152258.17" + attribute \src "libresoc.v:152257.9-152257.17" case 1'1 case end @@ -318837,8 +315647,8 @@ module \mul0 update \data_r0__o$next $0\data_r0__o$next[63:0]$7802 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7803 end - attribute \src "libresoc.v:152279.3-152300.6" - process $proc$libresoc.v:152279$7809 + attribute \src "libresoc.v:152278.3-152299.6" + process $proc$libresoc.v:152278$7809 assign { } { } assign { } { } assign { } { } @@ -318848,9 +315658,9 @@ module \mul0 assign $0\data_r1__cr_a$next[3:0]$7810 $2\data_r1__cr_a$next[3:0]$7814 assign { } { } assign $0\data_r1__cr_a_ok$next[0:0]$7811 $3\data_r1__cr_a_ok$next[0:0]$7816 - attribute \src "libresoc.v:152280.5-152280.29" + attribute \src "libresoc.v:152279.5-152279.29" switch \initial - attribute \src "libresoc.v:152280.9-152280.17" + attribute \src "libresoc.v:152279.9-152279.17" case 1'1 case end @@ -318889,8 +315699,8 @@ module \mul0 update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7810 update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7811 end - attribute \src "libresoc.v:152301.3-152322.6" - process $proc$libresoc.v:152301$7817 + attribute \src "libresoc.v:152300.3-152321.6" + process $proc$libresoc.v:152300$7817 assign { } { } assign { } { } assign { } { } @@ -318900,9 +315710,9 @@ module \mul0 assign $0\data_r2__xer_ov$next[1:0]$7818 $2\data_r2__xer_ov$next[1:0]$7822 assign { } { } assign $0\data_r2__xer_ov_ok$next[0:0]$7819 $3\data_r2__xer_ov_ok$next[0:0]$7824 - attribute \src "libresoc.v:152302.5-152302.29" + attribute \src "libresoc.v:152301.5-152301.29" switch \initial - attribute \src "libresoc.v:152302.9-152302.17" + attribute \src "libresoc.v:152301.9-152301.17" case 1'1 case end @@ -318941,8 +315751,8 @@ module \mul0 update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7818 update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7819 end - attribute \src "libresoc.v:152323.3-152344.6" - process $proc$libresoc.v:152323$7825 + attribute \src "libresoc.v:152322.3-152343.6" + process $proc$libresoc.v:152322$7825 assign { } { } assign { } { } assign { } { } @@ -318952,9 +315762,9 @@ module \mul0 assign $0\data_r3__xer_so$next[0:0]$7826 $2\data_r3__xer_so$next[0:0]$7830 assign { } { } assign $0\data_r3__xer_so_ok$next[0:0]$7827 $3\data_r3__xer_so_ok$next[0:0]$7832 - attribute \src "libresoc.v:152324.5-152324.29" + attribute \src "libresoc.v:152323.5-152323.29" switch \initial - attribute \src "libresoc.v:152324.9-152324.17" + attribute \src "libresoc.v:152323.9-152323.17" case 1'1 case end @@ -318993,14 +315803,14 @@ module \mul0 update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7826 update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7827 end - attribute \src "libresoc.v:152345.3-152354.6" - process $proc$libresoc.v:152345$7833 + attribute \src "libresoc.v:152344.3-152353.6" + process $proc$libresoc.v:152344$7833 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$7834 $1\src_r0$next[63:0]$7835 - attribute \src "libresoc.v:152346.5-152346.29" + attribute \src "libresoc.v:152345.5-152345.29" switch \initial - attribute \src "libresoc.v:152346.9-152346.17" + attribute \src "libresoc.v:152345.9-152345.17" case 1'1 case end @@ -319016,14 +315826,14 @@ module \mul0 sync always update \src_r0$next $0\src_r0$next[63:0]$7834 end - attribute \src "libresoc.v:152355.3-152364.6" - process $proc$libresoc.v:152355$7836 + attribute \src "libresoc.v:152354.3-152363.6" + process $proc$libresoc.v:152354$7836 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$7837 $1\src_r1$next[63:0]$7838 - attribute \src "libresoc.v:152356.5-152356.29" + attribute \src "libresoc.v:152355.5-152355.29" switch \initial - attribute \src "libresoc.v:152356.9-152356.17" + attribute \src "libresoc.v:152355.9-152355.17" case 1'1 case end @@ -319039,14 +315849,14 @@ module \mul0 sync always update \src_r1$next $0\src_r1$next[63:0]$7837 end - attribute \src "libresoc.v:152365.3-152374.6" - process $proc$libresoc.v:152365$7839 + attribute \src "libresoc.v:152364.3-152373.6" + process $proc$libresoc.v:152364$7839 assign { } { } assign { } { } assign $0\src_r2$next[0:0]$7840 $1\src_r2$next[0:0]$7841 - attribute \src "libresoc.v:152366.5-152366.29" + attribute \src "libresoc.v:152365.5-152365.29" switch \initial - attribute \src "libresoc.v:152366.9-152366.17" + attribute \src "libresoc.v:152365.9-152365.17" case 1'1 case end @@ -319062,14 +315872,14 @@ module \mul0 sync always update \src_r2$next $0\src_r2$next[0:0]$7840 end - attribute \src "libresoc.v:152375.3-152383.6" - process $proc$libresoc.v:152375$7842 + attribute \src "libresoc.v:152374.3-152382.6" + process $proc$libresoc.v:152374$7842 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$7843 $1\alui_l_r_alui$next[0:0]$7844 - attribute \src "libresoc.v:152376.5-152376.29" + attribute \src "libresoc.v:152375.5-152375.29" switch \initial - attribute \src "libresoc.v:152376.9-152376.17" + attribute \src "libresoc.v:152375.9-152375.17" case 1'1 case end @@ -319085,14 +315895,14 @@ module \mul0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7843 end - attribute \src "libresoc.v:152384.3-152392.6" - process $proc$libresoc.v:152384$7845 + attribute \src "libresoc.v:152383.3-152391.6" + process $proc$libresoc.v:152383$7845 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$7846 $1\alu_l_r_alu$next[0:0]$7847 - attribute \src "libresoc.v:152385.5-152385.29" + attribute \src "libresoc.v:152384.5-152384.29" switch \initial - attribute \src "libresoc.v:152385.9-152385.17" + attribute \src "libresoc.v:152384.9-152384.17" case 1'1 case end @@ -319108,14 +315918,14 @@ module \mul0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7846 end - attribute \src "libresoc.v:152393.3-152402.6" - process $proc$libresoc.v:152393$7848 + attribute \src "libresoc.v:152392.3-152401.6" + process $proc$libresoc.v:152392$7848 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:152394.5-152394.29" + attribute \src "libresoc.v:152393.5-152393.29" switch \initial - attribute \src "libresoc.v:152394.9-152394.17" + attribute \src "libresoc.v:152393.9-152393.17" case 1'1 case end @@ -319131,14 +315941,14 @@ module \mul0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:152403.3-152412.6" - process $proc$libresoc.v:152403$7849 + attribute \src "libresoc.v:152402.3-152411.6" + process $proc$libresoc.v:152402$7849 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:152404.5-152404.29" + attribute \src "libresoc.v:152403.5-152403.29" switch \initial - attribute \src "libresoc.v:152404.9-152404.17" + attribute \src "libresoc.v:152403.9-152403.17" case 1'1 case end @@ -319154,14 +315964,14 @@ module \mul0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:152413.3-152422.6" - process $proc$libresoc.v:152413$7850 + attribute \src "libresoc.v:152412.3-152421.6" + process $proc$libresoc.v:152412$7850 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:152414.5-152414.29" + attribute \src "libresoc.v:152413.5-152413.29" switch \initial - attribute \src "libresoc.v:152414.9-152414.17" + attribute \src "libresoc.v:152413.9-152413.17" case 1'1 case end @@ -319177,14 +315987,14 @@ module \mul0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:152423.3-152432.6" - process $proc$libresoc.v:152423$7851 + attribute \src "libresoc.v:152422.3-152431.6" + process $proc$libresoc.v:152422$7851 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:152424.5-152424.29" + attribute \src "libresoc.v:152423.5-152423.29" switch \initial - attribute \src "libresoc.v:152424.9-152424.17" + attribute \src "libresoc.v:152423.9-152423.17" case 1'1 case end @@ -319200,14 +316010,14 @@ module \mul0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:152433.3-152441.6" - process $proc$libresoc.v:152433$7852 + attribute \src "libresoc.v:152432.3-152440.6" + process $proc$libresoc.v:152432$7852 assign { } { } assign { } { } assign $0\prev_wr_go$next[3:0]$7853 $1\prev_wr_go$next[3:0]$7854 - attribute \src "libresoc.v:152434.5-152434.29" + attribute \src "libresoc.v:152433.5-152433.29" switch \initial - attribute \src "libresoc.v:152434.9-152434.17" + attribute \src "libresoc.v:152433.9-152433.17" case 1'1 case end @@ -319223,66 +316033,66 @@ module \mul0 sync always update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7853 end - connect \$100 $and$libresoc.v:151909$7641_Y - connect \$102 $and$libresoc.v:151910$7642_Y - connect \$104 $and$libresoc.v:151911$7643_Y - connect \$106 $and$libresoc.v:151912$7644_Y - connect \$108 $and$libresoc.v:151913$7645_Y - connect \$10 $and$libresoc.v:151914$7646_Y - connect \$110 $and$libresoc.v:151915$7647_Y - connect \$112 $and$libresoc.v:151916$7648_Y - connect \$114 $and$libresoc.v:151917$7649_Y - connect \$116 $and$libresoc.v:151918$7650_Y - connect \$118 $and$libresoc.v:151919$7651_Y - connect \$120 $and$libresoc.v:151920$7652_Y - connect \$12 $not$libresoc.v:151921$7653_Y - connect \$14 $and$libresoc.v:151922$7654_Y - connect \$16 $not$libresoc.v:151923$7655_Y - connect \$18 $and$libresoc.v:151924$7656_Y - connect \$20 $and$libresoc.v:151925$7657_Y - connect \$24 $not$libresoc.v:151926$7658_Y - connect \$26 $and$libresoc.v:151927$7659_Y - connect \$23 $reduce_or$libresoc.v:151928$7660_Y - connect \$22 $not$libresoc.v:151929$7661_Y - connect \$2 $and$libresoc.v:151930$7662_Y - connect \$30 $and$libresoc.v:151931$7663_Y - connect \$32 $reduce_or$libresoc.v:151932$7664_Y - connect \$34 $reduce_or$libresoc.v:151933$7665_Y - connect \$36 $or$libresoc.v:151934$7666_Y - connect \$38 $not$libresoc.v:151935$7667_Y - connect \$40 $and$libresoc.v:151936$7668_Y - connect \$42 $and$libresoc.v:151937$7669_Y - connect \$44 $eq$libresoc.v:151938$7670_Y - connect \$46 $and$libresoc.v:151939$7671_Y - connect \$48 $eq$libresoc.v:151940$7672_Y - connect \$50 $and$libresoc.v:151941$7673_Y - connect \$52 $and$libresoc.v:151942$7674_Y - connect \$54 $and$libresoc.v:151943$7675_Y - connect \$56 $or$libresoc.v:151944$7676_Y - connect \$58 $or$libresoc.v:151945$7677_Y - connect \$5 $not$libresoc.v:151946$7678_Y - connect \$60 $or$libresoc.v:151947$7679_Y - connect \$62 $or$libresoc.v:151948$7680_Y - connect \$64 $and$libresoc.v:151949$7681_Y - connect \$66 $and$libresoc.v:151950$7682_Y - connect \$68 $or$libresoc.v:151951$7683_Y - connect \$70 $and$libresoc.v:151952$7684_Y - connect \$72 $and$libresoc.v:151953$7685_Y - connect \$74 $and$libresoc.v:151954$7686_Y - connect \$76 $and$libresoc.v:151955$7687_Y - connect \$78 $ternary$libresoc.v:151956$7688_Y - connect \$7 $or$libresoc.v:151957$7689_Y - connect \$80 $ternary$libresoc.v:151958$7690_Y - connect \$82 $ternary$libresoc.v:151959$7691_Y - connect \$84 $ternary$libresoc.v:151960$7692_Y - connect \$86 $ternary$libresoc.v:151961$7693_Y - connect \$88 $and$libresoc.v:151962$7694_Y - connect \$4 $reduce_and$libresoc.v:151963$7695_Y - connect \$90 $and$libresoc.v:151964$7696_Y - connect \$92 $and$libresoc.v:151965$7697_Y - connect \$94 $not$libresoc.v:151966$7698_Y - connect \$96 $and$libresoc.v:151967$7699_Y - connect \$98 $not$libresoc.v:151968$7700_Y + connect \$100 $and$libresoc.v:151908$7641_Y + connect \$102 $and$libresoc.v:151909$7642_Y + connect \$104 $and$libresoc.v:151910$7643_Y + connect \$106 $and$libresoc.v:151911$7644_Y + connect \$108 $and$libresoc.v:151912$7645_Y + connect \$10 $and$libresoc.v:151913$7646_Y + connect \$110 $and$libresoc.v:151914$7647_Y + connect \$112 $and$libresoc.v:151915$7648_Y + connect \$114 $and$libresoc.v:151916$7649_Y + connect \$116 $and$libresoc.v:151917$7650_Y + connect \$118 $and$libresoc.v:151918$7651_Y + connect \$120 $and$libresoc.v:151919$7652_Y + connect \$12 $not$libresoc.v:151920$7653_Y + connect \$14 $and$libresoc.v:151921$7654_Y + connect \$16 $not$libresoc.v:151922$7655_Y + connect \$18 $and$libresoc.v:151923$7656_Y + connect \$20 $and$libresoc.v:151924$7657_Y + connect \$24 $not$libresoc.v:151925$7658_Y + connect \$26 $and$libresoc.v:151926$7659_Y + connect \$23 $reduce_or$libresoc.v:151927$7660_Y + connect \$22 $not$libresoc.v:151928$7661_Y + connect \$2 $and$libresoc.v:151929$7662_Y + connect \$30 $and$libresoc.v:151930$7663_Y + connect \$32 $reduce_or$libresoc.v:151931$7664_Y + connect \$34 $reduce_or$libresoc.v:151932$7665_Y + connect \$36 $or$libresoc.v:151933$7666_Y + connect \$38 $not$libresoc.v:151934$7667_Y + connect \$40 $and$libresoc.v:151935$7668_Y + connect \$42 $and$libresoc.v:151936$7669_Y + connect \$44 $eq$libresoc.v:151937$7670_Y + connect \$46 $and$libresoc.v:151938$7671_Y + connect \$48 $eq$libresoc.v:151939$7672_Y + connect \$50 $and$libresoc.v:151940$7673_Y + connect \$52 $and$libresoc.v:151941$7674_Y + connect \$54 $and$libresoc.v:151942$7675_Y + connect \$56 $or$libresoc.v:151943$7676_Y + connect \$58 $or$libresoc.v:151944$7677_Y + connect \$5 $not$libresoc.v:151945$7678_Y + connect \$60 $or$libresoc.v:151946$7679_Y + connect \$62 $or$libresoc.v:151947$7680_Y + connect \$64 $and$libresoc.v:151948$7681_Y + connect \$66 $and$libresoc.v:151949$7682_Y + connect \$68 $or$libresoc.v:151950$7683_Y + connect \$70 $and$libresoc.v:151951$7684_Y + connect \$72 $and$libresoc.v:151952$7685_Y + connect \$74 $and$libresoc.v:151953$7686_Y + connect \$76 $and$libresoc.v:151954$7687_Y + connect \$78 $ternary$libresoc.v:151955$7688_Y + connect \$7 $or$libresoc.v:151956$7689_Y + connect \$80 $ternary$libresoc.v:151957$7690_Y + connect \$82 $ternary$libresoc.v:151958$7691_Y + connect \$84 $ternary$libresoc.v:151959$7692_Y + connect \$86 $ternary$libresoc.v:151960$7693_Y + connect \$88 $and$libresoc.v:151961$7694_Y + connect \$4 $reduce_and$libresoc.v:151962$7695_Y + connect \$90 $and$libresoc.v:151963$7696_Y + connect \$92 $and$libresoc.v:151964$7697_Y + connect \$94 $not$libresoc.v:151965$7698_Y + connect \$96 $and$libresoc.v:151966$7699_Y + connect \$98 $not$libresoc.v:151967$7700_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -319314,51 +316124,51 @@ module \mul0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:152476.1-152809.10" +attribute \src "libresoc.v:152475.1-152808.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1" attribute \generator "nMigen" module \mul1 - attribute \src "libresoc.v:152776.18-152776.116" - wire $and$libresoc.v:152776$7895_Y - attribute \src "libresoc.v:152778.18-152778.116" - wire $and$libresoc.v:152778$7897_Y + attribute \src "libresoc.v:152775.18-152775.116" + wire $and$libresoc.v:152775$7895_Y + attribute \src "libresoc.v:152777.18-152777.116" + wire $and$libresoc.v:152777$7897_Y + attribute \src "libresoc.v:152778.18-152778.117" + wire $and$libresoc.v:152778$7898_Y attribute \src "libresoc.v:152779.18-152779.117" - wire $and$libresoc.v:152779$7898_Y - attribute \src "libresoc.v:152780.18-152780.117" - wire $and$libresoc.v:152780$7899_Y - attribute \src "libresoc.v:152783.18-152783.95" - wire width 65 $extend$libresoc.v:152783$7902_Y - attribute \src "libresoc.v:152784.18-152784.91" - wire width 65 $extend$libresoc.v:152784$7904_Y - attribute \src "libresoc.v:152786.18-152786.95" - wire width 65 $extend$libresoc.v:152786$7907_Y - attribute \src "libresoc.v:152787.18-152787.91" - wire width 65 $extend$libresoc.v:152787$7909_Y - attribute \src "libresoc.v:152783.18-152783.95" - wire width 65 $neg$libresoc.v:152783$7903_Y - attribute \src "libresoc.v:152786.18-152786.95" - wire width 65 $neg$libresoc.v:152786$7908_Y - attribute \src "libresoc.v:152784.18-152784.91" - wire width 65 $pos$libresoc.v:152784$7905_Y - attribute \src "libresoc.v:152787.18-152787.91" - wire width 65 $pos$libresoc.v:152787$7910_Y - attribute \src "libresoc.v:152775.18-152775.125" - wire $ternary$libresoc.v:152775$7894_Y - attribute \src "libresoc.v:152777.18-152777.125" - wire $ternary$libresoc.v:152777$7896_Y - attribute \src "libresoc.v:152785.18-152785.112" - wire width 65 $ternary$libresoc.v:152785$7906_Y - attribute \src "libresoc.v:152788.18-152788.112" - wire width 65 $ternary$libresoc.v:152788$7911_Y + wire $and$libresoc.v:152779$7899_Y + attribute \src "libresoc.v:152782.18-152782.95" + wire width 65 $extend$libresoc.v:152782$7902_Y + attribute \src "libresoc.v:152783.18-152783.91" + wire width 65 $extend$libresoc.v:152783$7904_Y + attribute \src "libresoc.v:152785.18-152785.95" + wire width 65 $extend$libresoc.v:152785$7907_Y + attribute \src "libresoc.v:152786.18-152786.91" + wire width 65 $extend$libresoc.v:152786$7909_Y + attribute \src "libresoc.v:152782.18-152782.95" + wire width 65 $neg$libresoc.v:152782$7903_Y + attribute \src "libresoc.v:152785.18-152785.95" + wire width 65 $neg$libresoc.v:152785$7908_Y + attribute \src "libresoc.v:152783.18-152783.91" + wire width 65 $pos$libresoc.v:152783$7905_Y + attribute \src "libresoc.v:152786.18-152786.91" + wire width 65 $pos$libresoc.v:152786$7910_Y + attribute \src "libresoc.v:152774.18-152774.125" + wire $ternary$libresoc.v:152774$7894_Y + attribute \src "libresoc.v:152776.18-152776.125" + wire $ternary$libresoc.v:152776$7896_Y + attribute \src "libresoc.v:152784.18-152784.112" + wire width 65 $ternary$libresoc.v:152784$7906_Y + attribute \src "libresoc.v:152787.18-152787.112" + wire width 65 $ternary$libresoc.v:152787$7911_Y + attribute \src "libresoc.v:152788.18-152788.116" + wire width 32 $ternary$libresoc.v:152788$7912_Y attribute \src "libresoc.v:152789.18-152789.116" - wire width 32 $ternary$libresoc.v:152789$7912_Y - attribute \src "libresoc.v:152790.18-152790.116" - wire width 32 $ternary$libresoc.v:152790$7913_Y - attribute \src "libresoc.v:152781.18-152781.106" - wire $xor$libresoc.v:152781$7900_Y - attribute \src "libresoc.v:152782.18-152782.110" - wire $xor$libresoc.v:152782$7901_Y + wire width 32 $ternary$libresoc.v:152789$7913_Y + attribute \src "libresoc.v:152780.18-152780.106" + wire $xor$libresoc.v:152780$7900_Y + attribute \src "libresoc.v:152781.18-152781.110" + wire $xor$libresoc.v:152781$7901_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" @@ -319658,7 +316468,7 @@ module \mul1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 31 \xer_so$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $and $and$libresoc.v:152776$7895 + cell $and $and$libresoc.v:152775$7895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -319666,10 +316476,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$17 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:152776$7895_Y + connect \Y $and$libresoc.v:152775$7895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $and $and$libresoc.v:152778$7897 + cell $and $and$libresoc.v:152777$7897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -319677,10 +316487,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$21 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:152778$7897_Y + connect \Y $and$libresoc.v:152777$7897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" - cell $and $and$libresoc.v:152779$7898 + cell $and $and$libresoc.v:152778$7898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -319688,10 +316498,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \ra [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:152779$7898_Y + connect \Y $and$libresoc.v:152778$7898_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" - cell $and $and$libresoc.v:152780$7899 + cell $and $and$libresoc.v:152779$7899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -319699,122 +316509,122 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \rb [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:152780$7899_Y + connect \Y $and$libresoc.v:152779$7899_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $pos $extend$libresoc.v:152783$7902 + cell $pos $extend$libresoc.v:152782$7902 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:152783$7902_Y + connect \Y $extend$libresoc.v:152782$7902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:152784$7904 + cell $pos $extend$libresoc.v:152783$7904 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:152784$7904_Y + connect \Y $extend$libresoc.v:152783$7904_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $pos $extend$libresoc.v:152786$7907 + cell $pos $extend$libresoc.v:152785$7907 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:152786$7907_Y + connect \Y $extend$libresoc.v:152785$7907_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:152787$7909 + cell $pos $extend$libresoc.v:152786$7909 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:152787$7909_Y + connect \Y $extend$libresoc.v:152786$7909_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $neg $neg$libresoc.v:152783$7903 + cell $neg $neg$libresoc.v:152782$7903 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:152783$7902_Y - connect \Y $neg$libresoc.v:152783$7903_Y + connect \A $extend$libresoc.v:152782$7902_Y + connect \Y $neg$libresoc.v:152782$7903_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $neg $neg$libresoc.v:152786$7908 + cell $neg $neg$libresoc.v:152785$7908 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:152786$7907_Y - connect \Y $neg$libresoc.v:152786$7908_Y + connect \A $extend$libresoc.v:152785$7907_Y + connect \Y $neg$libresoc.v:152785$7908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:152784$7905 + cell $pos $pos$libresoc.v:152783$7905 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:152784$7904_Y - connect \Y $pos$libresoc.v:152784$7905_Y + connect \A $extend$libresoc.v:152783$7904_Y + connect \Y $pos$libresoc.v:152783$7905_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:152787$7910 + cell $pos $pos$libresoc.v:152786$7910 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:152787$7909_Y - connect \Y $pos$libresoc.v:152787$7910_Y + connect \A $extend$libresoc.v:152786$7909_Y + connect \Y $pos$libresoc.v:152786$7910_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $mux $ternary$libresoc.v:152775$7894 + cell $mux $ternary$libresoc.v:152774$7894 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:152775$7894_Y + connect \Y $ternary$libresoc.v:152774$7894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $mux $ternary$libresoc.v:152777$7896 + cell $mux $ternary$libresoc.v:152776$7896 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:152777$7896_Y + connect \Y $ternary$libresoc.v:152776$7896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $mux $ternary$libresoc.v:152785$7906 + cell $mux $ternary$libresoc.v:152784$7906 parameter \WIDTH 65 connect \A \$36 connect \B \$34 connect \S \sign_a - connect \Y $ternary$libresoc.v:152785$7906_Y + connect \Y $ternary$libresoc.v:152784$7906_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $mux $ternary$libresoc.v:152788$7911 + cell $mux $ternary$libresoc.v:152787$7911 parameter \WIDTH 65 connect \A \$43 connect \B \$41 connect \S \sign_b - connect \Y $ternary$libresoc.v:152788$7911_Y + connect \Y $ternary$libresoc.v:152787$7911_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:152789$7912 + cell $mux $ternary$libresoc.v:152788$7912 parameter \WIDTH 32 connect \A \abs_a [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:152789$7912_Y + connect \Y $ternary$libresoc.v:152788$7912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:152790$7913 + cell $mux $ternary$libresoc.v:152789$7913 parameter \WIDTH 32 connect \A \abs_b [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:152790$7913_Y + connect \Y $ternary$libresoc.v:152789$7913_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" - cell $xor $xor$libresoc.v:152781$7900 + cell $xor $xor$libresoc.v:152780$7900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -319822,10 +316632,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign_a connect \B \sign_b - connect \Y $xor$libresoc.v:152781$7900_Y + connect \Y $xor$libresoc.v:152780$7900_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" - cell $xor $xor$libresoc.v:152782$7901 + cell $xor $xor$libresoc.v:152781$7901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -319833,24 +316643,24 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign32_a connect \B \sign32_b - connect \Y $xor$libresoc.v:152782$7901_Y - end - connect \$17 $ternary$libresoc.v:152775$7894_Y - connect \$19 $and$libresoc.v:152776$7895_Y - connect \$21 $ternary$libresoc.v:152777$7896_Y - connect \$23 $and$libresoc.v:152778$7897_Y - connect \$25 $and$libresoc.v:152779$7898_Y - connect \$27 $and$libresoc.v:152780$7899_Y - connect \$29 $xor$libresoc.v:152781$7900_Y - connect \$31 $xor$libresoc.v:152782$7901_Y - connect \$34 $neg$libresoc.v:152783$7903_Y - connect \$36 $pos$libresoc.v:152784$7905_Y - connect \$38 $ternary$libresoc.v:152785$7906_Y - connect \$41 $neg$libresoc.v:152786$7908_Y - connect \$43 $pos$libresoc.v:152787$7910_Y - connect \$45 $ternary$libresoc.v:152788$7911_Y - connect \$47 $ternary$libresoc.v:152789$7912_Y - connect \$49 $ternary$libresoc.v:152790$7913_Y + connect \Y $xor$libresoc.v:152781$7901_Y + end + connect \$17 $ternary$libresoc.v:152774$7894_Y + connect \$19 $and$libresoc.v:152775$7895_Y + connect \$21 $ternary$libresoc.v:152776$7896_Y + connect \$23 $and$libresoc.v:152777$7897_Y + connect \$25 $and$libresoc.v:152778$7898_Y + connect \$27 $and$libresoc.v:152779$7899_Y + connect \$29 $xor$libresoc.v:152780$7900_Y + connect \$31 $xor$libresoc.v:152781$7901_Y + connect \$34 $neg$libresoc.v:152782$7903_Y + connect \$36 $pos$libresoc.v:152783$7905_Y + connect \$38 $ternary$libresoc.v:152784$7906_Y + connect \$41 $neg$libresoc.v:152785$7908_Y + connect \$43 $pos$libresoc.v:152786$7910_Y + connect \$45 $ternary$libresoc.v:152787$7911_Y + connect \$47 $ternary$libresoc.v:152788$7912_Y + connect \$49 $ternary$libresoc.v:152789$7913_Y connect \$33 \$38 connect \$40 \$45 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } @@ -319870,17 +316680,17 @@ module \mul1 connect \sign_a \$19 connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:152813.1-153076.10" +attribute \src "libresoc.v:152812.1-153075.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" attribute \generator "nMigen" module \mul2 - attribute \src "libresoc.v:153069.18-153069.98" - wire width 129 $extend$libresoc.v:153069$7915_Y - attribute \src "libresoc.v:153068.18-153068.99" - wire width 128 $mul$libresoc.v:153068$7914_Y - attribute \src "libresoc.v:153069.18-153069.98" - wire width 129 $pos$libresoc.v:153069$7916_Y + attribute \src "libresoc.v:153068.18-153068.98" + wire width 129 $extend$libresoc.v:153068$7915_Y + attribute \src "libresoc.v:153067.18-153067.99" + wire width 128 $mul$libresoc.v:153067$7914_Y + attribute \src "libresoc.v:153068.18-153068.98" + wire width 129 $pos$libresoc.v:153068$7916_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" wire width 129 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" @@ -320136,15 +316946,15 @@ module \mul2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 32 \xer_so$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $extend$libresoc.v:153069$7915 + cell $pos $extend$libresoc.v:153068$7915 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 129 connect \A \$18 - connect \Y $extend$libresoc.v:153069$7915_Y + connect \Y $extend$libresoc.v:153068$7915_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $mul $mul$libresoc.v:153068$7914 + cell $mul $mul$libresoc.v:153067$7914 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -320152,18 +316962,18 @@ module \mul2 parameter \Y_WIDTH 128 connect \A \ra connect \B \rb - connect \Y $mul$libresoc.v:153068$7914_Y + connect \Y $mul$libresoc.v:153067$7914_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $pos$libresoc.v:153069$7916 + cell $pos $pos$libresoc.v:153068$7916 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 129 - connect \A $extend$libresoc.v:153069$7915_Y - connect \Y $pos$libresoc.v:153069$7916_Y + connect \A $extend$libresoc.v:153068$7915_Y + connect \Y $pos$libresoc.v:153068$7916_Y end - connect \$18 $mul$libresoc.v:153068$7914_Y - connect \$17 $pos$libresoc.v:153069$7916_Y + connect \$18 $mul$libresoc.v:153067$7914_Y + connect \$17 $pos$libresoc.v:153068$7916_Y connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid connect \xer_so$14 \xer_so @@ -320171,65 +316981,65 @@ module \mul2 connect \neg_res$15 \neg_res connect \o \$17 end -attribute \src "libresoc.v:153080.1-153465.10" +attribute \src "libresoc.v:153079.1-153464.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3" attribute \generator "nMigen" module \mul3 - attribute \src "libresoc.v:153081.7-153081.20" + attribute \src "libresoc.v:153080.7-153080.20" wire $0\initial[0:0] - attribute \src "libresoc.v:153418.3-153436.6" + attribute \src "libresoc.v:153417.3-153435.6" wire $0\mul_ov[0:0] - attribute \src "libresoc.v:153380.3-153398.6" + attribute \src "libresoc.v:153379.3-153397.6" wire width 64 $0\o$14[63:0]$7933 - attribute \src "libresoc.v:153399.3-153417.6" + attribute \src "libresoc.v:153398.3-153416.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:153437.3-153447.6" + attribute \src "libresoc.v:153436.3-153446.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:153448.3-153458.6" + attribute \src "libresoc.v:153447.3-153457.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:153418.3-153436.6" + attribute \src "libresoc.v:153417.3-153435.6" wire $1\mul_ov[0:0] - attribute \src "libresoc.v:153380.3-153398.6" + attribute \src "libresoc.v:153379.3-153397.6" wire width 64 $1\o$14[63:0]$7934 - attribute \src "libresoc.v:153399.3-153417.6" + attribute \src "libresoc.v:153398.3-153416.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:153437.3-153447.6" + attribute \src "libresoc.v:153436.3-153446.6" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:153448.3-153458.6" + attribute \src "libresoc.v:153447.3-153457.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:153418.3-153436.6" + attribute \src "libresoc.v:153417.3-153435.6" wire $2\mul_ov[0:0] - attribute \src "libresoc.v:153374.18-153374.104" - wire $and$libresoc.v:153374$7925_Y - attribute \src "libresoc.v:153378.18-153378.104" - wire $and$libresoc.v:153378$7929_Y - attribute \src "libresoc.v:153368.18-153368.95" - wire width 130 $extend$libresoc.v:153368$7917_Y - attribute \src "libresoc.v:153369.18-153369.90" - wire width 130 $extend$libresoc.v:153369$7919_Y - attribute \src "libresoc.v:153379.18-153379.95" - wire width 2 $extend$libresoc.v:153379$7930_Y - attribute \src "libresoc.v:153368.18-153368.95" - wire width 130 $neg$libresoc.v:153368$7918_Y - attribute \src "libresoc.v:153373.18-153373.98" - wire $not$libresoc.v:153373$7924_Y - attribute \src "libresoc.v:153377.18-153377.98" - wire $not$libresoc.v:153377$7928_Y - attribute \src "libresoc.v:153369.18-153369.90" - wire width 130 $pos$libresoc.v:153369$7920_Y - attribute \src "libresoc.v:153379.18-153379.95" - wire width 2 $pos$libresoc.v:153379$7931_Y - attribute \src "libresoc.v:153372.18-153372.106" - wire $reduce_and$libresoc.v:153372$7923_Y - attribute \src "libresoc.v:153376.18-153376.107" - wire $reduce_and$libresoc.v:153376$7927_Y + attribute \src "libresoc.v:153373.18-153373.104" + wire $and$libresoc.v:153373$7925_Y + attribute \src "libresoc.v:153377.18-153377.104" + wire $and$libresoc.v:153377$7929_Y + attribute \src "libresoc.v:153367.18-153367.95" + wire width 130 $extend$libresoc.v:153367$7917_Y + attribute \src "libresoc.v:153368.18-153368.90" + wire width 130 $extend$libresoc.v:153368$7919_Y + attribute \src "libresoc.v:153378.18-153378.95" + wire width 2 $extend$libresoc.v:153378$7930_Y + attribute \src "libresoc.v:153367.18-153367.95" + wire width 130 $neg$libresoc.v:153367$7918_Y + attribute \src "libresoc.v:153372.18-153372.98" + wire $not$libresoc.v:153372$7924_Y + attribute \src "libresoc.v:153376.18-153376.98" + wire $not$libresoc.v:153376$7928_Y + attribute \src "libresoc.v:153368.18-153368.90" + wire width 130 $pos$libresoc.v:153368$7920_Y + attribute \src "libresoc.v:153378.18-153378.95" + wire width 2 $pos$libresoc.v:153378$7931_Y attribute \src "libresoc.v:153371.18-153371.106" - wire $reduce_or$libresoc.v:153371$7922_Y + wire $reduce_and$libresoc.v:153371$7923_Y attribute \src "libresoc.v:153375.18-153375.107" - wire $reduce_or$libresoc.v:153375$7926_Y - attribute \src "libresoc.v:153370.18-153370.114" - wire width 130 $ternary$libresoc.v:153370$7921_Y + wire $reduce_and$libresoc.v:153375$7927_Y + attribute \src "libresoc.v:153370.18-153370.106" + wire $reduce_or$libresoc.v:153370$7922_Y + attribute \src "libresoc.v:153374.18-153374.107" + wire $reduce_or$libresoc.v:153374$7926_Y + attribute \src "libresoc.v:153369.18-153369.114" + wire width 130 $ternary$libresoc.v:153369$7921_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" wire width 130 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" @@ -320256,7 +317066,7 @@ module \mul3 wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \$39 - attribute \src "libresoc.v:153081.7-153081.15" + attribute \src "libresoc.v:153080.7-153080.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" wire \is_32bit @@ -320515,7 +317325,7 @@ module \mul3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 34 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $and $and$libresoc.v:153374$7925 + cell $and $and$libresoc.v:153373$7925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -320523,10 +317333,10 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $and$libresoc.v:153374$7925_Y + connect \Y $and$libresoc.v:153373$7925_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $and $and$libresoc.v:153378$7929 + cell $and $and$libresoc.v:153377$7929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -320534,128 +317344,128 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:153378$7929_Y + connect \Y $and$libresoc.v:153377$7929_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $pos $extend$libresoc.v:153368$7917 + cell $pos $extend$libresoc.v:153367$7917 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:153368$7917_Y + connect \Y $extend$libresoc.v:153367$7917_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:153369$7919 + cell $pos $extend$libresoc.v:153368$7919 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:153369$7919_Y + connect \Y $extend$libresoc.v:153368$7919_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:153379$7930 + cell $pos $extend$libresoc.v:153378$7930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 connect \A \xer_so - connect \Y $extend$libresoc.v:153379$7930_Y + connect \Y $extend$libresoc.v:153378$7930_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $neg $neg$libresoc.v:153368$7918 + cell $neg $neg$libresoc.v:153367$7918 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:153368$7917_Y - connect \Y $neg$libresoc.v:153368$7918_Y + connect \A $extend$libresoc.v:153367$7917_Y + connect \Y $neg$libresoc.v:153367$7918_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $not $not$libresoc.v:153373$7924 + cell $not $not$libresoc.v:153372$7924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $not$libresoc.v:153373$7924_Y + connect \Y $not$libresoc.v:153372$7924_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $not $not$libresoc.v:153377$7928 + cell $not $not$libresoc.v:153376$7928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$34 - connect \Y $not$libresoc.v:153377$7928_Y + connect \Y $not$libresoc.v:153376$7928_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:153369$7920 + cell $pos $pos$libresoc.v:153368$7920 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:153369$7919_Y - connect \Y $pos$libresoc.v:153369$7920_Y + connect \A $extend$libresoc.v:153368$7919_Y + connect \Y $pos$libresoc.v:153368$7920_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:153379$7931 + cell $pos $pos$libresoc.v:153378$7931 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:153379$7930_Y - connect \Y $pos$libresoc.v:153379$7931_Y + connect \A $extend$libresoc.v:153378$7930_Y + connect \Y $pos$libresoc.v:153378$7931_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_and $reduce_and$libresoc.v:153372$7923 + cell $reduce_and $reduce_and$libresoc.v:153371$7923 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_and$libresoc.v:153372$7923_Y + connect \Y $reduce_and$libresoc.v:153371$7923_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_and $reduce_and$libresoc.v:153376$7927 + cell $reduce_and $reduce_and$libresoc.v:153375$7927 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_and$libresoc.v:153376$7927_Y + connect \Y $reduce_and$libresoc.v:153375$7927_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_or $reduce_or$libresoc.v:153371$7922 + cell $reduce_or $reduce_or$libresoc.v:153370$7922 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_or$libresoc.v:153371$7922_Y + connect \Y $reduce_or$libresoc.v:153370$7922_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_or $reduce_or$libresoc.v:153375$7926 + cell $reduce_or $reduce_or$libresoc.v:153374$7926 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_or$libresoc.v:153375$7926_Y + connect \Y $reduce_or$libresoc.v:153374$7926_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $mux $ternary$libresoc.v:153370$7921 + cell $mux $ternary$libresoc.v:153369$7921 parameter \WIDTH 130 connect \A \$19 connect \B \$17 connect \S \neg_res - connect \Y $ternary$libresoc.v:153370$7921_Y + connect \Y $ternary$libresoc.v:153369$7921_Y end - attribute \src "libresoc.v:153081.7-153081.20" - process $proc$libresoc.v:153081$7939 + attribute \src "libresoc.v:153080.7-153080.20" + process $proc$libresoc.v:153080$7939 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:153380.3-153398.6" - process $proc$libresoc.v:153380$7932 + attribute \src "libresoc.v:153379.3-153397.6" + process $proc$libresoc.v:153379$7932 assign { } { } assign { } { } assign $0\o$14[63:0]$7933 $1\o$14[63:0]$7934 - attribute \src "libresoc.v:153381.5-153381.29" + attribute \src "libresoc.v:153380.5-153380.29" switch \initial - attribute \src "libresoc.v:153381.9-153381.17" + attribute \src "libresoc.v:153380.9-153380.17" case 1'1 case end @@ -320679,14 +317489,14 @@ module \mul3 sync always update \o$14 $0\o$14[63:0]$7933 end - attribute \src "libresoc.v:153399.3-153417.6" - process $proc$libresoc.v:153399$7935 + attribute \src "libresoc.v:153398.3-153416.6" + process $proc$libresoc.v:153398$7935 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:153400.5-153400.29" + attribute \src "libresoc.v:153399.5-153399.29" switch \initial - attribute \src "libresoc.v:153400.9-153400.17" + attribute \src "libresoc.v:153399.9-153399.17" case 1'1 case end @@ -320710,14 +317520,14 @@ module \mul3 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:153418.3-153436.6" - process $proc$libresoc.v:153418$7936 + attribute \src "libresoc.v:153417.3-153435.6" + process $proc$libresoc.v:153417$7936 assign { } { } assign { } { } assign $0\mul_ov[0:0] $1\mul_ov[0:0] - attribute \src "libresoc.v:153419.5-153419.29" + attribute \src "libresoc.v:153418.5-153418.29" switch \initial - attribute \src "libresoc.v:153419.9-153419.17" + attribute \src "libresoc.v:153418.9-153418.17" case 1'1 case end @@ -320744,14 +317554,14 @@ module \mul3 sync always update \mul_ov $0\mul_ov[0:0] end - attribute \src "libresoc.v:153437.3-153447.6" - process $proc$libresoc.v:153437$7937 + attribute \src "libresoc.v:153436.3-153446.6" + process $proc$libresoc.v:153436$7937 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:153438.5-153438.29" + attribute \src "libresoc.v:153437.5-153437.29" switch \initial - attribute \src "libresoc.v:153438.9-153438.17" + attribute \src "libresoc.v:153437.9-153437.17" case 1'1 case end @@ -320767,14 +317577,14 @@ module \mul3 sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:153448.3-153458.6" - process $proc$libresoc.v:153448$7938 + attribute \src "libresoc.v:153447.3-153457.6" + process $proc$libresoc.v:153447$7938 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:153449.5-153449.29" + attribute \src "libresoc.v:153448.5-153448.29" switch \initial - attribute \src "libresoc.v:153449.9-153449.17" + attribute \src "libresoc.v:153448.9-153448.17" case 1'1 case end @@ -320790,18 +317600,18 @@ module \mul3 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$17 $neg$libresoc.v:153368$7918_Y - connect \$19 $pos$libresoc.v:153369$7920_Y - connect \$21 $ternary$libresoc.v:153370$7921_Y - connect \$23 $reduce_or$libresoc.v:153371$7922_Y - connect \$26 $reduce_and$libresoc.v:153372$7923_Y - connect \$25 $not$libresoc.v:153373$7924_Y - connect \$29 $and$libresoc.v:153374$7925_Y - connect \$31 $reduce_or$libresoc.v:153375$7926_Y - connect \$34 $reduce_and$libresoc.v:153376$7927_Y - connect \$33 $not$libresoc.v:153377$7928_Y - connect \$37 $and$libresoc.v:153378$7929_Y - connect \$39 $pos$libresoc.v:153379$7931_Y + connect \$17 $neg$libresoc.v:153367$7918_Y + connect \$19 $pos$libresoc.v:153368$7920_Y + connect \$21 $ternary$libresoc.v:153369$7921_Y + connect \$23 $reduce_or$libresoc.v:153370$7922_Y + connect \$26 $reduce_and$libresoc.v:153371$7923_Y + connect \$25 $not$libresoc.v:153372$7924_Y + connect \$29 $and$libresoc.v:153373$7925_Y + connect \$31 $reduce_or$libresoc.v:153374$7926_Y + connect \$34 $reduce_and$libresoc.v:153375$7927_Y + connect \$33 $not$libresoc.v:153376$7928_Y + connect \$37 $and$libresoc.v:153377$7929_Y + connect \$39 $pos$libresoc.v:153378$7931_Y connect \$16 \$21 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid @@ -320809,188 +317619,188 @@ module \mul3 connect \mul_o \$21 [128:0] connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:153469.1-154686.10" +attribute \src "libresoc.v:153468.1-154685.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" attribute \generator "nMigen" module \mul_pipe1 - attribute \src "libresoc.v:153470.7-153470.20" + attribute \src "libresoc.v:153469.7-153469.20" wire $0\initial[0:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire width 14 $0\mul_op__fn_unit$next[13:0]$7968 - attribute \src "libresoc.v:154428.3-154429.47" + attribute \src "libresoc.v:154427.3-154428.47" wire width 14 $0\mul_op__fn_unit[13:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire width 64 $0\mul_op__imm_data__data$next[63:0]$7969 - attribute \src "libresoc.v:154430.3-154431.61" + attribute \src "libresoc.v:154429.3-154430.61" wire width 64 $0\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $0\mul_op__imm_data__ok$next[0:0]$7970 - attribute \src "libresoc.v:154432.3-154433.57" + attribute \src "libresoc.v:154431.3-154432.57" wire $0\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire width 32 $0\mul_op__insn$next[31:0]$7971 - attribute \src "libresoc.v:154448.3-154449.41" + attribute \src "libresoc.v:154447.3-154448.41" wire width 32 $0\mul_op__insn[31:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire width 7 $0\mul_op__insn_type$next[6:0]$7972 - attribute \src "libresoc.v:154426.3-154427.51" + attribute \src "libresoc.v:154425.3-154426.51" wire width 7 $0\mul_op__insn_type[6:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $0\mul_op__is_32bit$next[0:0]$7973 - attribute \src "libresoc.v:154444.3-154445.49" + attribute \src "libresoc.v:154443.3-154444.49" wire $0\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $0\mul_op__is_signed$next[0:0]$7974 - attribute \src "libresoc.v:154446.3-154447.51" + attribute \src "libresoc.v:154445.3-154446.51" wire $0\mul_op__is_signed[0:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $0\mul_op__oe__oe$next[0:0]$7975 - attribute \src "libresoc.v:154438.3-154439.45" + attribute \src "libresoc.v:154437.3-154438.45" wire $0\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $0\mul_op__oe__ok$next[0:0]$7976 - attribute \src "libresoc.v:154440.3-154441.45" + attribute \src "libresoc.v:154439.3-154440.45" wire $0\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $0\mul_op__rc__ok$next[0:0]$7977 - attribute \src "libresoc.v:154436.3-154437.45" + attribute \src "libresoc.v:154435.3-154436.45" wire $0\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $0\mul_op__rc__rc$next[0:0]$7978 - attribute \src "libresoc.v:154434.3-154435.45" + attribute \src "libresoc.v:154433.3-154434.45" wire $0\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $0\mul_op__write_cr0$next[0:0]$7979 - attribute \src "libresoc.v:154442.3-154443.51" + attribute \src "libresoc.v:154441.3-154442.51" wire $0\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:154550.3-154562.6" + attribute \src "libresoc.v:154549.3-154561.6" wire width 2 $0\muxid$next[1:0]$7965 - attribute \src "libresoc.v:154450.3-154451.27" + attribute \src "libresoc.v:154449.3-154450.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:154638.3-154650.6" + attribute \src "libresoc.v:154637.3-154649.6" wire $0\neg_res$next[0:0]$8008 - attribute \src "libresoc.v:154651.3-154663.6" + attribute \src "libresoc.v:154650.3-154662.6" wire $0\neg_res32$next[0:0]$8011 - attribute \src "libresoc.v:154416.3-154417.35" + attribute \src "libresoc.v:154415.3-154416.35" wire $0\neg_res32[0:0] - attribute \src "libresoc.v:154418.3-154419.31" + attribute \src "libresoc.v:154417.3-154418.31" wire $0\neg_res[0:0] - attribute \src "libresoc.v:154532.3-154549.6" + attribute \src "libresoc.v:154531.3-154548.6" wire $0\r_busy$next[0:0]$7961 - attribute \src "libresoc.v:154452.3-154453.29" + attribute \src "libresoc.v:154451.3-154452.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:154599.3-154611.6" + attribute \src "libresoc.v:154598.3-154610.6" wire width 64 $0\ra$next[63:0]$7999 - attribute \src "libresoc.v:154424.3-154425.21" + attribute \src "libresoc.v:154423.3-154424.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:154612.3-154624.6" + attribute \src "libresoc.v:154611.3-154623.6" wire width 64 $0\rb$next[63:0]$8002 - attribute \src "libresoc.v:154422.3-154423.21" + attribute \src "libresoc.v:154421.3-154422.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:154625.3-154637.6" + attribute \src "libresoc.v:154624.3-154636.6" wire $0\xer_so$next[0:0]$8005 - attribute \src "libresoc.v:154420.3-154421.29" + attribute \src "libresoc.v:154419.3-154420.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire width 14 $1\mul_op__fn_unit$next[13:0]$7980 - attribute \src "libresoc.v:153986.14-153986.40" + attribute \src "libresoc.v:153985.14-153985.40" wire width 14 $1\mul_op__fn_unit[13:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire width 64 $1\mul_op__imm_data__data$next[63:0]$7981 - attribute \src "libresoc.v:154025.14-154025.59" + attribute \src "libresoc.v:154024.14-154024.59" wire width 64 $1\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $1\mul_op__imm_data__ok$next[0:0]$7982 - attribute \src "libresoc.v:154034.7-154034.34" + attribute \src "libresoc.v:154033.7-154033.34" wire $1\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire width 32 $1\mul_op__insn$next[31:0]$7983 - attribute \src "libresoc.v:154043.14-154043.34" + attribute \src "libresoc.v:154042.14-154042.34" wire width 32 $1\mul_op__insn[31:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire width 7 $1\mul_op__insn_type$next[6:0]$7984 - attribute \src "libresoc.v:154127.13-154127.38" + attribute \src "libresoc.v:154126.13-154126.38" wire width 7 $1\mul_op__insn_type[6:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $1\mul_op__is_32bit$next[0:0]$7985 - attribute \src "libresoc.v:154286.7-154286.30" + attribute \src "libresoc.v:154285.7-154285.30" wire $1\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $1\mul_op__is_signed$next[0:0]$7986 - attribute \src "libresoc.v:154295.7-154295.31" + attribute \src "libresoc.v:154294.7-154294.31" wire $1\mul_op__is_signed[0:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $1\mul_op__oe__oe$next[0:0]$7987 - attribute \src "libresoc.v:154304.7-154304.28" + attribute \src "libresoc.v:154303.7-154303.28" wire $1\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $1\mul_op__oe__ok$next[0:0]$7988 - attribute \src "libresoc.v:154313.7-154313.28" + attribute \src "libresoc.v:154312.7-154312.28" wire $1\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $1\mul_op__rc__ok$next[0:0]$7989 - attribute \src "libresoc.v:154322.7-154322.28" + attribute \src "libresoc.v:154321.7-154321.28" wire $1\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $1\mul_op__rc__rc$next[0:0]$7990 - attribute \src "libresoc.v:154331.7-154331.28" + attribute \src "libresoc.v:154330.7-154330.28" wire $1\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $1\mul_op__write_cr0$next[0:0]$7991 - attribute \src "libresoc.v:154340.7-154340.31" + attribute \src "libresoc.v:154339.7-154339.31" wire $1\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:154550.3-154562.6" + attribute \src "libresoc.v:154549.3-154561.6" wire width 2 $1\muxid$next[1:0]$7966 - attribute \src "libresoc.v:154349.13-154349.25" + attribute \src "libresoc.v:154348.13-154348.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:154638.3-154650.6" + attribute \src "libresoc.v:154637.3-154649.6" wire $1\neg_res$next[0:0]$8009 - attribute \src "libresoc.v:154651.3-154663.6" + attribute \src "libresoc.v:154650.3-154662.6" wire $1\neg_res32$next[0:0]$8012 - attribute \src "libresoc.v:154371.7-154371.23" + attribute \src "libresoc.v:154370.7-154370.23" wire $1\neg_res32[0:0] - attribute \src "libresoc.v:154364.7-154364.21" + attribute \src "libresoc.v:154363.7-154363.21" wire $1\neg_res[0:0] - attribute \src "libresoc.v:154532.3-154549.6" + attribute \src "libresoc.v:154531.3-154548.6" wire $1\r_busy$next[0:0]$7962 - attribute \src "libresoc.v:154385.7-154385.20" + attribute \src "libresoc.v:154384.7-154384.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:154599.3-154611.6" + attribute \src "libresoc.v:154598.3-154610.6" wire width 64 $1\ra$next[63:0]$8000 - attribute \src "libresoc.v:154390.14-154390.39" + attribute \src "libresoc.v:154389.14-154389.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:154612.3-154624.6" + attribute \src "libresoc.v:154611.3-154623.6" wire width 64 $1\rb$next[63:0]$8003 - attribute \src "libresoc.v:154399.14-154399.39" + attribute \src "libresoc.v:154398.14-154398.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:154625.3-154637.6" + attribute \src "libresoc.v:154624.3-154636.6" wire $1\xer_so$next[0:0]$8006 - attribute \src "libresoc.v:154408.7-154408.20" + attribute \src "libresoc.v:154407.7-154407.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire width 64 $2\mul_op__imm_data__data$next[63:0]$7992 - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $2\mul_op__imm_data__ok$next[0:0]$7993 - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $2\mul_op__oe__oe$next[0:0]$7994 - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $2\mul_op__oe__ok$next[0:0]$7995 - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $2\mul_op__rc__ok$next[0:0]$7996 - attribute \src "libresoc.v:154563.3-154598.6" + attribute \src "libresoc.v:154562.3-154597.6" wire $2\mul_op__rc__rc$next[0:0]$7997 - attribute \src "libresoc.v:154532.3-154549.6" + attribute \src "libresoc.v:154531.3-154548.6" wire $2\r_busy$next[0:0]$7963 - attribute \src "libresoc.v:154415.18-154415.118" - wire $and$libresoc.v:154415$7940_Y + attribute \src "libresoc.v:154414.18-154414.118" + wire $and$libresoc.v:154414$7940_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 40 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:153470.7-153470.15" + attribute \src "libresoc.v:153469.7-153469.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -321913,7 +318723,7 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:154415$7940 + cell $and $and$libresoc.v:154414$7940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -321921,10 +318731,10 @@ module \mul_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$49 connect \B \p_ready_o - connect \Y $and$libresoc.v:154415$7940_Y + connect \Y $and$libresoc.v:154414$7940_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:154454.14-154487.4" + attribute \src "libresoc.v:154453.14-154486.4" cell \input$95 \input connect \mul_op__fn_unit \input_mul_op__fn_unit connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 @@ -321960,7 +318770,7 @@ module \mul_pipe1 connect \xer_so$16 \input_xer_so$32 end attribute \module_not_derived 1 - attribute \src "libresoc.v:154488.8-154523.4" + attribute \src "libresoc.v:154487.8-154522.4" cell \mul1 \mul1 connect \mul_op__fn_unit \mul1_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 @@ -321998,319 +318808,319 @@ module \mul_pipe1 connect \xer_so$16 \mul1_xer_so$48 end attribute \module_not_derived 1 - attribute \src "libresoc.v:154524.10-154527.4" + attribute \src "libresoc.v:154523.10-154526.4" cell \n$94 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:154528.10-154531.4" + attribute \src "libresoc.v:154527.10-154530.4" cell \p$93 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:153470.7-153470.20" - process $proc$libresoc.v:153470$8013 + attribute \src "libresoc.v:153469.7-153469.20" + process $proc$libresoc.v:153469$8013 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:153986.14-153986.40" - process $proc$libresoc.v:153986$8014 + attribute \src "libresoc.v:153985.14-153985.40" + process $proc$libresoc.v:153985$8014 assign { } { } assign $1\mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \mul_op__fn_unit $1\mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:154025.14-154025.59" - process $proc$libresoc.v:154025$8015 + attribute \src "libresoc.v:154024.14-154024.59" + process $proc$libresoc.v:154024$8015 assign { } { } assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:154034.7-154034.34" - process $proc$libresoc.v:154034$8016 + attribute \src "libresoc.v:154033.7-154033.34" + process $proc$libresoc.v:154033$8016 assign { } { } assign $1\mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:154043.14-154043.34" - process $proc$libresoc.v:154043$8017 + attribute \src "libresoc.v:154042.14-154042.34" + process $proc$libresoc.v:154042$8017 assign { } { } assign $1\mul_op__insn[31:0] 0 sync always sync init update \mul_op__insn $1\mul_op__insn[31:0] end - attribute \src "libresoc.v:154127.13-154127.38" - process $proc$libresoc.v:154127$8018 + attribute \src "libresoc.v:154126.13-154126.38" + process $proc$libresoc.v:154126$8018 assign { } { } assign $1\mul_op__insn_type[6:0] 7'0000000 sync always sync init update \mul_op__insn_type $1\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:154286.7-154286.30" - process $proc$libresoc.v:154286$8019 + attribute \src "libresoc.v:154285.7-154285.30" + process $proc$libresoc.v:154285$8019 assign { } { } assign $1\mul_op__is_32bit[0:0] 1'0 sync always sync init update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:154295.7-154295.31" - process $proc$libresoc.v:154295$8020 + attribute \src "libresoc.v:154294.7-154294.31" + process $proc$libresoc.v:154294$8020 assign { } { } assign $1\mul_op__is_signed[0:0] 1'0 sync always sync init update \mul_op__is_signed $1\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:154304.7-154304.28" - process $proc$libresoc.v:154304$8021 + attribute \src "libresoc.v:154303.7-154303.28" + process $proc$libresoc.v:154303$8021 assign { } { } assign $1\mul_op__oe__oe[0:0] 1'0 sync always sync init update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:154313.7-154313.28" - process $proc$libresoc.v:154313$8022 + attribute \src "libresoc.v:154312.7-154312.28" + process $proc$libresoc.v:154312$8022 assign { } { } assign $1\mul_op__oe__ok[0:0] 1'0 sync always sync init update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:154322.7-154322.28" - process $proc$libresoc.v:154322$8023 + attribute \src "libresoc.v:154321.7-154321.28" + process $proc$libresoc.v:154321$8023 assign { } { } assign $1\mul_op__rc__ok[0:0] 1'0 sync always sync init update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:154331.7-154331.28" - process $proc$libresoc.v:154331$8024 + attribute \src "libresoc.v:154330.7-154330.28" + process $proc$libresoc.v:154330$8024 assign { } { } assign $1\mul_op__rc__rc[0:0] 1'0 sync always sync init update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:154340.7-154340.31" - process $proc$libresoc.v:154340$8025 + attribute \src "libresoc.v:154339.7-154339.31" + process $proc$libresoc.v:154339$8025 assign { } { } assign $1\mul_op__write_cr0[0:0] 1'0 sync always sync init update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:154349.13-154349.25" - process $proc$libresoc.v:154349$8026 + attribute \src "libresoc.v:154348.13-154348.25" + process $proc$libresoc.v:154348$8026 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:154364.7-154364.21" - process $proc$libresoc.v:154364$8027 + attribute \src "libresoc.v:154363.7-154363.21" + process $proc$libresoc.v:154363$8027 assign { } { } assign $1\neg_res[0:0] 1'0 sync always sync init update \neg_res $1\neg_res[0:0] end - attribute \src "libresoc.v:154371.7-154371.23" - process $proc$libresoc.v:154371$8028 + attribute \src "libresoc.v:154370.7-154370.23" + process $proc$libresoc.v:154370$8028 assign { } { } assign $1\neg_res32[0:0] 1'0 sync always sync init update \neg_res32 $1\neg_res32[0:0] end - attribute \src "libresoc.v:154385.7-154385.20" - process $proc$libresoc.v:154385$8029 + attribute \src "libresoc.v:154384.7-154384.20" + process $proc$libresoc.v:154384$8029 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:154390.14-154390.39" - process $proc$libresoc.v:154390$8030 + attribute \src "libresoc.v:154389.14-154389.39" + process $proc$libresoc.v:154389$8030 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:154399.14-154399.39" - process $proc$libresoc.v:154399$8031 + attribute \src "libresoc.v:154398.14-154398.39" + process $proc$libresoc.v:154398$8031 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:154408.7-154408.20" - process $proc$libresoc.v:154408$8032 + attribute \src "libresoc.v:154407.7-154407.20" + process $proc$libresoc.v:154407$8032 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:154416.3-154417.35" - process $proc$libresoc.v:154416$7941 + attribute \src "libresoc.v:154415.3-154416.35" + process $proc$libresoc.v:154415$7941 assign { } { } assign $0\neg_res32[0:0] \neg_res32$next sync posedge \coresync_clk update \neg_res32 $0\neg_res32[0:0] end - attribute \src "libresoc.v:154418.3-154419.31" - process $proc$libresoc.v:154418$7942 + attribute \src "libresoc.v:154417.3-154418.31" + process $proc$libresoc.v:154417$7942 assign { } { } assign $0\neg_res[0:0] \neg_res$next sync posedge \coresync_clk update \neg_res $0\neg_res[0:0] end - attribute \src "libresoc.v:154420.3-154421.29" - process $proc$libresoc.v:154420$7943 + attribute \src "libresoc.v:154419.3-154420.29" + process $proc$libresoc.v:154419$7943 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:154422.3-154423.21" - process $proc$libresoc.v:154422$7944 + attribute \src "libresoc.v:154421.3-154422.21" + process $proc$libresoc.v:154421$7944 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:154424.3-154425.21" - process $proc$libresoc.v:154424$7945 + attribute \src "libresoc.v:154423.3-154424.21" + process $proc$libresoc.v:154423$7945 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:154426.3-154427.51" - process $proc$libresoc.v:154426$7946 + attribute \src "libresoc.v:154425.3-154426.51" + process $proc$libresoc.v:154425$7946 assign { } { } assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next sync posedge \coresync_clk update \mul_op__insn_type $0\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:154428.3-154429.47" - process $proc$libresoc.v:154428$7947 + attribute \src "libresoc.v:154427.3-154428.47" + process $proc$libresoc.v:154427$7947 assign { } { } assign $0\mul_op__fn_unit[13:0] \mul_op__fn_unit$next sync posedge \coresync_clk update \mul_op__fn_unit $0\mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:154430.3-154431.61" - process $proc$libresoc.v:154430$7948 + attribute \src "libresoc.v:154429.3-154430.61" + process $proc$libresoc.v:154429$7948 assign { } { } assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next sync posedge \coresync_clk update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:154432.3-154433.57" - process $proc$libresoc.v:154432$7949 + attribute \src "libresoc.v:154431.3-154432.57" + process $proc$libresoc.v:154431$7949 assign { } { } assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next sync posedge \coresync_clk update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:154434.3-154435.45" - process $proc$libresoc.v:154434$7950 + attribute \src "libresoc.v:154433.3-154434.45" + process $proc$libresoc.v:154433$7950 assign { } { } assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next sync posedge \coresync_clk update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:154436.3-154437.45" - process $proc$libresoc.v:154436$7951 + attribute \src "libresoc.v:154435.3-154436.45" + process $proc$libresoc.v:154435$7951 assign { } { } assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next sync posedge \coresync_clk update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:154438.3-154439.45" - process $proc$libresoc.v:154438$7952 + attribute \src "libresoc.v:154437.3-154438.45" + process $proc$libresoc.v:154437$7952 assign { } { } assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next sync posedge \coresync_clk update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:154440.3-154441.45" - process $proc$libresoc.v:154440$7953 + attribute \src "libresoc.v:154439.3-154440.45" + process $proc$libresoc.v:154439$7953 assign { } { } assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next sync posedge \coresync_clk update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:154442.3-154443.51" - process $proc$libresoc.v:154442$7954 + attribute \src "libresoc.v:154441.3-154442.51" + process $proc$libresoc.v:154441$7954 assign { } { } assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next sync posedge \coresync_clk update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:154444.3-154445.49" - process $proc$libresoc.v:154444$7955 + attribute \src "libresoc.v:154443.3-154444.49" + process $proc$libresoc.v:154443$7955 assign { } { } assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next sync posedge \coresync_clk update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:154446.3-154447.51" - process $proc$libresoc.v:154446$7956 + attribute \src "libresoc.v:154445.3-154446.51" + process $proc$libresoc.v:154445$7956 assign { } { } assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next sync posedge \coresync_clk update \mul_op__is_signed $0\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:154448.3-154449.41" - process $proc$libresoc.v:154448$7957 + attribute \src "libresoc.v:154447.3-154448.41" + process $proc$libresoc.v:154447$7957 assign { } { } assign $0\mul_op__insn[31:0] \mul_op__insn$next sync posedge \coresync_clk update \mul_op__insn $0\mul_op__insn[31:0] end - attribute \src "libresoc.v:154450.3-154451.27" - process $proc$libresoc.v:154450$7958 + attribute \src "libresoc.v:154449.3-154450.27" + process $proc$libresoc.v:154449$7958 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:154452.3-154453.29" - process $proc$libresoc.v:154452$7959 + attribute \src "libresoc.v:154451.3-154452.29" + process $proc$libresoc.v:154451$7959 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:154532.3-154549.6" - process $proc$libresoc.v:154532$7960 + attribute \src "libresoc.v:154531.3-154548.6" + process $proc$libresoc.v:154531$7960 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$7961 $2\r_busy$next[0:0]$7963 - attribute \src "libresoc.v:154533.5-154533.29" + attribute \src "libresoc.v:154532.5-154532.29" switch \initial - attribute \src "libresoc.v:154533.9-154533.17" + attribute \src "libresoc.v:154532.9-154532.17" case 1'1 case end @@ -322339,14 +319149,14 @@ module \mul_pipe1 sync always update \r_busy$next $0\r_busy$next[0:0]$7961 end - attribute \src "libresoc.v:154550.3-154562.6" - process $proc$libresoc.v:154550$7964 + attribute \src "libresoc.v:154549.3-154561.6" + process $proc$libresoc.v:154549$7964 assign { } { } assign { } { } assign $0\muxid$next[1:0]$7965 $1\muxid$next[1:0]$7966 - attribute \src "libresoc.v:154551.5-154551.29" + attribute \src "libresoc.v:154550.5-154550.29" switch \initial - attribute \src "libresoc.v:154551.9-154551.17" + attribute \src "libresoc.v:154550.9-154550.17" case 1'1 case end @@ -322366,8 +319176,8 @@ module \mul_pipe1 sync always update \muxid$next $0\muxid$next[1:0]$7965 end - attribute \src "libresoc.v:154563.3-154598.6" - process $proc$libresoc.v:154563$7967 + attribute \src "libresoc.v:154562.3-154597.6" + process $proc$libresoc.v:154562$7967 assign { } { } assign { } { } assign { } { } @@ -322410,9 +319220,9 @@ module \mul_pipe1 assign $0\mul_op__oe__ok$next[0:0]$7976 $2\mul_op__oe__ok$next[0:0]$7995 assign $0\mul_op__rc__ok$next[0:0]$7977 $2\mul_op__rc__ok$next[0:0]$7996 assign $0\mul_op__rc__rc$next[0:0]$7978 $2\mul_op__rc__rc$next[0:0]$7997 - attribute \src "libresoc.v:154564.5-154564.29" + attribute \src "libresoc.v:154563.5-154563.29" switch \initial - attribute \src "libresoc.v:154564.9-154564.17" + attribute \src "libresoc.v:154563.9-154563.17" case 1'1 case end @@ -322500,14 +319310,14 @@ module \mul_pipe1 update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7978 update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7979 end - attribute \src "libresoc.v:154599.3-154611.6" - process $proc$libresoc.v:154599$7998 + attribute \src "libresoc.v:154598.3-154610.6" + process $proc$libresoc.v:154598$7998 assign { } { } assign { } { } assign $0\ra$next[63:0]$7999 $1\ra$next[63:0]$8000 - attribute \src "libresoc.v:154600.5-154600.29" + attribute \src "libresoc.v:154599.5-154599.29" switch \initial - attribute \src "libresoc.v:154600.9-154600.17" + attribute \src "libresoc.v:154599.9-154599.17" case 1'1 case end @@ -322527,14 +319337,14 @@ module \mul_pipe1 sync always update \ra$next $0\ra$next[63:0]$7999 end - attribute \src "libresoc.v:154612.3-154624.6" - process $proc$libresoc.v:154612$8001 + attribute \src "libresoc.v:154611.3-154623.6" + process $proc$libresoc.v:154611$8001 assign { } { } assign { } { } assign $0\rb$next[63:0]$8002 $1\rb$next[63:0]$8003 - attribute \src "libresoc.v:154613.5-154613.29" + attribute \src "libresoc.v:154612.5-154612.29" switch \initial - attribute \src "libresoc.v:154613.9-154613.17" + attribute \src "libresoc.v:154612.9-154612.17" case 1'1 case end @@ -322554,14 +319364,14 @@ module \mul_pipe1 sync always update \rb$next $0\rb$next[63:0]$8002 end - attribute \src "libresoc.v:154625.3-154637.6" - process $proc$libresoc.v:154625$8004 + attribute \src "libresoc.v:154624.3-154636.6" + process $proc$libresoc.v:154624$8004 assign { } { } assign { } { } assign $0\xer_so$next[0:0]$8005 $1\xer_so$next[0:0]$8006 - attribute \src "libresoc.v:154626.5-154626.29" + attribute \src "libresoc.v:154625.5-154625.29" switch \initial - attribute \src "libresoc.v:154626.9-154626.17" + attribute \src "libresoc.v:154625.9-154625.17" case 1'1 case end @@ -322581,14 +319391,14 @@ module \mul_pipe1 sync always update \xer_so$next $0\xer_so$next[0:0]$8005 end - attribute \src "libresoc.v:154638.3-154650.6" - process $proc$libresoc.v:154638$8007 + attribute \src "libresoc.v:154637.3-154649.6" + process $proc$libresoc.v:154637$8007 assign { } { } assign { } { } assign $0\neg_res$next[0:0]$8008 $1\neg_res$next[0:0]$8009 - attribute \src "libresoc.v:154639.5-154639.29" + attribute \src "libresoc.v:154638.5-154638.29" switch \initial - attribute \src "libresoc.v:154639.9-154639.17" + attribute \src "libresoc.v:154638.9-154638.17" case 1'1 case end @@ -322608,14 +319418,14 @@ module \mul_pipe1 sync always update \neg_res$next $0\neg_res$next[0:0]$8008 end - attribute \src "libresoc.v:154651.3-154663.6" - process $proc$libresoc.v:154651$8010 + attribute \src "libresoc.v:154650.3-154662.6" + process $proc$libresoc.v:154650$8010 assign { } { } assign { } { } assign $0\neg_res32$next[0:0]$8011 $1\neg_res32$next[0:0]$8012 - attribute \src "libresoc.v:154652.5-154652.29" + attribute \src "libresoc.v:154651.5-154651.29" switch \initial - attribute \src "libresoc.v:154652.9-154652.17" + attribute \src "libresoc.v:154651.9-154651.17" case 1'1 case end @@ -322635,7 +319445,7 @@ module \mul_pipe1 sync always update \neg_res32$next $0\neg_res32$next[0:0]$8011 end - connect \$50 $and$libresoc.v:154415$7940_Y + connect \$50 $and$libresoc.v:154414$7940_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$69 \mul1_neg_res32 @@ -322659,180 +319469,180 @@ module \mul_pipe1 connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:154690.1-155610.10" +attribute \src "libresoc.v:154689.1-155609.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" attribute \generator "nMigen" module \mul_pipe2 - attribute \src "libresoc.v:154691.7-154691.20" + attribute \src "libresoc.v:154690.7-154690.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8076 - attribute \src "libresoc.v:155402.3-155403.53" + attribute \src "libresoc.v:155401.3-155402.53" wire width 14 $0\mul_op__fn_unit$3[13:0]$8044 - attribute \src "libresoc.v:154982.14-154982.44" + attribute \src "libresoc.v:154981.14-154981.44" wire width 14 $0\mul_op__fn_unit$3[13:0]$8120 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8077 - attribute \src "libresoc.v:155404.3-155405.67" + attribute \src "libresoc.v:155403.3-155404.67" wire width 64 $0\mul_op__imm_data__data$4[63:0]$8046 - attribute \src "libresoc.v:155008.14-155008.63" + attribute \src "libresoc.v:155007.14-155007.63" wire width 64 $0\mul_op__imm_data__data$4[63:0]$8122 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $0\mul_op__imm_data__ok$5$next[0:0]$8078 - attribute \src "libresoc.v:155406.3-155407.63" + attribute \src "libresoc.v:155405.3-155406.63" wire $0\mul_op__imm_data__ok$5[0:0]$8048 - attribute \src "libresoc.v:155017.7-155017.38" + attribute \src "libresoc.v:155016.7-155016.38" wire $0\mul_op__imm_data__ok$5[0:0]$8124 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire width 32 $0\mul_op__insn$13$next[31:0]$8079 - attribute \src "libresoc.v:155422.3-155423.49" + attribute \src "libresoc.v:155421.3-155422.49" wire width 32 $0\mul_op__insn$13[31:0]$8064 - attribute \src "libresoc.v:155024.14-155024.39" + attribute \src "libresoc.v:155023.14-155023.39" wire width 32 $0\mul_op__insn$13[31:0]$8126 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire width 7 $0\mul_op__insn_type$2$next[6:0]$8080 - attribute \src "libresoc.v:155400.3-155401.57" + attribute \src "libresoc.v:155399.3-155400.57" wire width 7 $0\mul_op__insn_type$2[6:0]$8042 - attribute \src "libresoc.v:155183.13-155183.42" + attribute \src "libresoc.v:155182.13-155182.42" wire width 7 $0\mul_op__insn_type$2[6:0]$8128 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $0\mul_op__is_32bit$11$next[0:0]$8081 - attribute \src "libresoc.v:155418.3-155419.57" + attribute \src "libresoc.v:155417.3-155418.57" wire $0\mul_op__is_32bit$11[0:0]$8060 - attribute \src "libresoc.v:155267.7-155267.35" + attribute \src "libresoc.v:155266.7-155266.35" wire $0\mul_op__is_32bit$11[0:0]$8130 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $0\mul_op__is_signed$12$next[0:0]$8082 - attribute \src "libresoc.v:155420.3-155421.59" + attribute \src "libresoc.v:155419.3-155420.59" wire $0\mul_op__is_signed$12[0:0]$8062 - attribute \src "libresoc.v:155276.7-155276.36" + attribute \src "libresoc.v:155275.7-155275.36" wire $0\mul_op__is_signed$12[0:0]$8132 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $0\mul_op__oe__oe$8$next[0:0]$8083 - attribute \src "libresoc.v:155412.3-155413.51" + attribute \src "libresoc.v:155411.3-155412.51" wire $0\mul_op__oe__oe$8[0:0]$8054 - attribute \src "libresoc.v:155287.7-155287.32" + attribute \src "libresoc.v:155286.7-155286.32" wire $0\mul_op__oe__oe$8[0:0]$8134 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $0\mul_op__oe__ok$9$next[0:0]$8084 - attribute \src "libresoc.v:155414.3-155415.51" + attribute \src "libresoc.v:155413.3-155414.51" wire $0\mul_op__oe__ok$9[0:0]$8056 - attribute \src "libresoc.v:155296.7-155296.32" + attribute \src "libresoc.v:155295.7-155295.32" wire $0\mul_op__oe__ok$9[0:0]$8136 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $0\mul_op__rc__ok$7$next[0:0]$8085 - attribute \src "libresoc.v:155410.3-155411.51" + attribute \src "libresoc.v:155409.3-155410.51" wire $0\mul_op__rc__ok$7[0:0]$8052 - attribute \src "libresoc.v:155305.7-155305.32" + attribute \src "libresoc.v:155304.7-155304.32" wire $0\mul_op__rc__ok$7[0:0]$8138 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $0\mul_op__rc__rc$6$next[0:0]$8086 - attribute \src "libresoc.v:155408.3-155409.51" + attribute \src "libresoc.v:155407.3-155408.51" wire $0\mul_op__rc__rc$6[0:0]$8050 - attribute \src "libresoc.v:155314.7-155314.32" + attribute \src "libresoc.v:155313.7-155313.32" wire $0\mul_op__rc__rc$6[0:0]$8140 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $0\mul_op__write_cr0$10$next[0:0]$8087 - attribute \src "libresoc.v:155416.3-155417.59" + attribute \src "libresoc.v:155415.3-155416.59" wire $0\mul_op__write_cr0$10[0:0]$8058 - attribute \src "libresoc.v:155321.7-155321.36" + attribute \src "libresoc.v:155320.7-155320.36" wire $0\mul_op__write_cr0$10[0:0]$8142 - attribute \src "libresoc.v:155491.3-155503.6" + attribute \src "libresoc.v:155490.3-155502.6" wire width 2 $0\muxid$1$next[1:0]$8073 - attribute \src "libresoc.v:155424.3-155425.33" + attribute \src "libresoc.v:155423.3-155424.33" wire width 2 $0\muxid$1[1:0]$8066 - attribute \src "libresoc.v:155330.13-155330.29" + attribute \src "libresoc.v:155329.13-155329.29" wire width 2 $0\muxid$1[1:0]$8144 - attribute \src "libresoc.v:155566.3-155578.6" + attribute \src "libresoc.v:155565.3-155577.6" wire $0\neg_res$15$next[0:0]$8113 - attribute \src "libresoc.v:155394.3-155395.39" + attribute \src "libresoc.v:155393.3-155394.39" wire $0\neg_res$15[0:0]$8037 - attribute \src "libresoc.v:155345.7-155345.26" + attribute \src "libresoc.v:155344.7-155344.26" wire $0\neg_res$15[0:0]$8146 - attribute \src "libresoc.v:155579.3-155591.6" + attribute \src "libresoc.v:155578.3-155590.6" wire $0\neg_res32$16$next[0:0]$8116 - attribute \src "libresoc.v:155392.3-155393.43" + attribute \src "libresoc.v:155391.3-155392.43" wire $0\neg_res32$16[0:0]$8035 - attribute \src "libresoc.v:155354.7-155354.28" + attribute \src "libresoc.v:155353.7-155353.28" wire $0\neg_res32$16[0:0]$8148 - attribute \src "libresoc.v:155540.3-155552.6" + attribute \src "libresoc.v:155539.3-155551.6" wire width 129 $0\o$next[128:0]$8107 - attribute \src "libresoc.v:155398.3-155399.19" + attribute \src "libresoc.v:155397.3-155398.19" wire width 129 $0\o[128:0] - attribute \src "libresoc.v:155473.3-155490.6" + attribute \src "libresoc.v:155472.3-155489.6" wire $0\r_busy$next[0:0]$8069 - attribute \src "libresoc.v:155426.3-155427.29" + attribute \src "libresoc.v:155425.3-155426.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:155553.3-155565.6" + attribute \src "libresoc.v:155552.3-155564.6" wire $0\xer_so$14$next[0:0]$8110 - attribute \src "libresoc.v:155396.3-155397.37" + attribute \src "libresoc.v:155395.3-155396.37" wire $0\xer_so$14[0:0]$8039 - attribute \src "libresoc.v:155386.7-155386.25" + attribute \src "libresoc.v:155385.7-155385.25" wire $0\xer_so$14[0:0]$8152 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8088 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8089 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $1\mul_op__imm_data__ok$5$next[0:0]$8090 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire width 32 $1\mul_op__insn$13$next[31:0]$8091 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire width 7 $1\mul_op__insn_type$2$next[6:0]$8092 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $1\mul_op__is_32bit$11$next[0:0]$8093 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $1\mul_op__is_signed$12$next[0:0]$8094 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $1\mul_op__oe__oe$8$next[0:0]$8095 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $1\mul_op__oe__ok$9$next[0:0]$8096 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $1\mul_op__rc__ok$7$next[0:0]$8097 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $1\mul_op__rc__rc$6$next[0:0]$8098 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $1\mul_op__write_cr0$10$next[0:0]$8099 - attribute \src "libresoc.v:155491.3-155503.6" + attribute \src "libresoc.v:155490.3-155502.6" wire width 2 $1\muxid$1$next[1:0]$8074 - attribute \src "libresoc.v:155566.3-155578.6" + attribute \src "libresoc.v:155565.3-155577.6" wire $1\neg_res$15$next[0:0]$8114 - attribute \src "libresoc.v:155579.3-155591.6" + attribute \src "libresoc.v:155578.3-155590.6" wire $1\neg_res32$16$next[0:0]$8117 - attribute \src "libresoc.v:155540.3-155552.6" + attribute \src "libresoc.v:155539.3-155551.6" wire width 129 $1\o$next[128:0]$8108 - attribute \src "libresoc.v:155361.15-155361.57" + attribute \src "libresoc.v:155360.15-155360.57" wire width 129 $1\o[128:0] - attribute \src "libresoc.v:155473.3-155490.6" + attribute \src "libresoc.v:155472.3-155489.6" wire $1\r_busy$next[0:0]$8070 - attribute \src "libresoc.v:155375.7-155375.20" + attribute \src "libresoc.v:155374.7-155374.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:155553.3-155565.6" + attribute \src "libresoc.v:155552.3-155564.6" wire $1\xer_so$14$next[0:0]$8111 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8100 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $2\mul_op__imm_data__ok$5$next[0:0]$8101 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $2\mul_op__oe__oe$8$next[0:0]$8102 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $2\mul_op__oe__ok$9$next[0:0]$8103 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $2\mul_op__rc__ok$7$next[0:0]$8104 - attribute \src "libresoc.v:155504.3-155539.6" + attribute \src "libresoc.v:155503.3-155538.6" wire $2\mul_op__rc__rc$6$next[0:0]$8105 - attribute \src "libresoc.v:155473.3-155490.6" + attribute \src "libresoc.v:155472.3-155489.6" wire $2\r_busy$next[0:0]$8071 - attribute \src "libresoc.v:155391.18-155391.118" - wire $and$libresoc.v:155391$8033_Y + attribute \src "libresoc.v:155390.18-155390.118" + wire $and$libresoc.v:155390$8033_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 41 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:154691.7-154691.15" + attribute \src "libresoc.v:154690.7-154690.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -323511,7 +320321,7 @@ module \mul_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$50 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:155391$8033 + cell $and $and$libresoc.v:155390$8033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323519,10 +320329,10 @@ module \mul_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$33 connect \B \p_ready_o - connect \Y $and$libresoc.v:155391$8033_Y + connect \Y $and$libresoc.v:155390$8033_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:155428.8-155464.4" + attribute \src "libresoc.v:155427.8-155463.4" cell \mul2 \mul2 connect \mul_op__fn_unit \mul2_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 @@ -323561,304 +320371,304 @@ module \mul_pipe2 connect \xer_so$14 \mul2_xer_so$30 end attribute \module_not_derived 1 - attribute \src "libresoc.v:155465.10-155468.4" + attribute \src "libresoc.v:155464.10-155467.4" cell \n$97 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:155469.10-155472.4" + attribute \src "libresoc.v:155468.10-155471.4" cell \p$96 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:154691.7-154691.20" - process $proc$libresoc.v:154691$8118 + attribute \src "libresoc.v:154690.7-154690.20" + process $proc$libresoc.v:154690$8118 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:154982.14-154982.44" - process $proc$libresoc.v:154982$8119 + attribute \src "libresoc.v:154981.14-154981.44" + process $proc$libresoc.v:154981$8119 assign { } { } assign $0\mul_op__fn_unit$3[13:0]$8120 14'00000000000000 sync always sync init update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8120 end - attribute \src "libresoc.v:155008.14-155008.63" - process $proc$libresoc.v:155008$8121 + attribute \src "libresoc.v:155007.14-155007.63" + process $proc$libresoc.v:155007$8121 assign { } { } assign $0\mul_op__imm_data__data$4[63:0]$8122 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8122 end - attribute \src "libresoc.v:155017.7-155017.38" - process $proc$libresoc.v:155017$8123 + attribute \src "libresoc.v:155016.7-155016.38" + process $proc$libresoc.v:155016$8123 assign { } { } assign $0\mul_op__imm_data__ok$5[0:0]$8124 1'0 sync always sync init update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8124 end - attribute \src "libresoc.v:155024.14-155024.39" - process $proc$libresoc.v:155024$8125 + attribute \src "libresoc.v:155023.14-155023.39" + process $proc$libresoc.v:155023$8125 assign { } { } assign $0\mul_op__insn$13[31:0]$8126 0 sync always sync init update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8126 end - attribute \src "libresoc.v:155183.13-155183.42" - process $proc$libresoc.v:155183$8127 + attribute \src "libresoc.v:155182.13-155182.42" + process $proc$libresoc.v:155182$8127 assign { } { } assign $0\mul_op__insn_type$2[6:0]$8128 7'0000000 sync always sync init update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8128 end - attribute \src "libresoc.v:155267.7-155267.35" - process $proc$libresoc.v:155267$8129 + attribute \src "libresoc.v:155266.7-155266.35" + process $proc$libresoc.v:155266$8129 assign { } { } assign $0\mul_op__is_32bit$11[0:0]$8130 1'0 sync always sync init update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8130 end - attribute \src "libresoc.v:155276.7-155276.36" - process $proc$libresoc.v:155276$8131 + attribute \src "libresoc.v:155275.7-155275.36" + process $proc$libresoc.v:155275$8131 assign { } { } assign $0\mul_op__is_signed$12[0:0]$8132 1'0 sync always sync init update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8132 end - attribute \src "libresoc.v:155287.7-155287.32" - process $proc$libresoc.v:155287$8133 + attribute \src "libresoc.v:155286.7-155286.32" + process $proc$libresoc.v:155286$8133 assign { } { } assign $0\mul_op__oe__oe$8[0:0]$8134 1'0 sync always sync init update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8134 end - attribute \src "libresoc.v:155296.7-155296.32" - process $proc$libresoc.v:155296$8135 + attribute \src "libresoc.v:155295.7-155295.32" + process $proc$libresoc.v:155295$8135 assign { } { } assign $0\mul_op__oe__ok$9[0:0]$8136 1'0 sync always sync init update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8136 end - attribute \src "libresoc.v:155305.7-155305.32" - process $proc$libresoc.v:155305$8137 + attribute \src "libresoc.v:155304.7-155304.32" + process $proc$libresoc.v:155304$8137 assign { } { } assign $0\mul_op__rc__ok$7[0:0]$8138 1'0 sync always sync init update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8138 end - attribute \src "libresoc.v:155314.7-155314.32" - process $proc$libresoc.v:155314$8139 + attribute \src "libresoc.v:155313.7-155313.32" + process $proc$libresoc.v:155313$8139 assign { } { } assign $0\mul_op__rc__rc$6[0:0]$8140 1'0 sync always sync init update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8140 end - attribute \src "libresoc.v:155321.7-155321.36" - process $proc$libresoc.v:155321$8141 + attribute \src "libresoc.v:155320.7-155320.36" + process $proc$libresoc.v:155320$8141 assign { } { } assign $0\mul_op__write_cr0$10[0:0]$8142 1'0 sync always sync init update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8142 end - attribute \src "libresoc.v:155330.13-155330.29" - process $proc$libresoc.v:155330$8143 + attribute \src "libresoc.v:155329.13-155329.29" + process $proc$libresoc.v:155329$8143 assign { } { } assign $0\muxid$1[1:0]$8144 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$8144 end - attribute \src "libresoc.v:155345.7-155345.26" - process $proc$libresoc.v:155345$8145 + attribute \src "libresoc.v:155344.7-155344.26" + process $proc$libresoc.v:155344$8145 assign { } { } assign $0\neg_res$15[0:0]$8146 1'0 sync always sync init update \neg_res$15 $0\neg_res$15[0:0]$8146 end - attribute \src "libresoc.v:155354.7-155354.28" - process $proc$libresoc.v:155354$8147 + attribute \src "libresoc.v:155353.7-155353.28" + process $proc$libresoc.v:155353$8147 assign { } { } assign $0\neg_res32$16[0:0]$8148 1'0 sync always sync init update \neg_res32$16 $0\neg_res32$16[0:0]$8148 end - attribute \src "libresoc.v:155361.15-155361.57" - process $proc$libresoc.v:155361$8149 + attribute \src "libresoc.v:155360.15-155360.57" + process $proc$libresoc.v:155360$8149 assign { } { } assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[128:0] end - attribute \src "libresoc.v:155375.7-155375.20" - process $proc$libresoc.v:155375$8150 + attribute \src "libresoc.v:155374.7-155374.20" + process $proc$libresoc.v:155374$8150 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:155386.7-155386.25" - process $proc$libresoc.v:155386$8151 + attribute \src "libresoc.v:155385.7-155385.25" + process $proc$libresoc.v:155385$8151 assign { } { } assign $0\xer_so$14[0:0]$8152 1'0 sync always sync init update \xer_so$14 $0\xer_so$14[0:0]$8152 end - attribute \src "libresoc.v:155392.3-155393.43" - process $proc$libresoc.v:155392$8034 + attribute \src "libresoc.v:155391.3-155392.43" + process $proc$libresoc.v:155391$8034 assign { } { } assign $0\neg_res32$16[0:0]$8035 \neg_res32$16$next sync posedge \coresync_clk update \neg_res32$16 $0\neg_res32$16[0:0]$8035 end - attribute \src "libresoc.v:155394.3-155395.39" - process $proc$libresoc.v:155394$8036 + attribute \src "libresoc.v:155393.3-155394.39" + process $proc$libresoc.v:155393$8036 assign { } { } assign $0\neg_res$15[0:0]$8037 \neg_res$15$next sync posedge \coresync_clk update \neg_res$15 $0\neg_res$15[0:0]$8037 end - attribute \src "libresoc.v:155396.3-155397.37" - process $proc$libresoc.v:155396$8038 + attribute \src "libresoc.v:155395.3-155396.37" + process $proc$libresoc.v:155395$8038 assign { } { } assign $0\xer_so$14[0:0]$8039 \xer_so$14$next sync posedge \coresync_clk update \xer_so$14 $0\xer_so$14[0:0]$8039 end - attribute \src "libresoc.v:155398.3-155399.19" - process $proc$libresoc.v:155398$8040 + attribute \src "libresoc.v:155397.3-155398.19" + process $proc$libresoc.v:155397$8040 assign { } { } assign $0\o[128:0] \o$next sync posedge \coresync_clk update \o $0\o[128:0] end - attribute \src "libresoc.v:155400.3-155401.57" - process $proc$libresoc.v:155400$8041 + attribute \src "libresoc.v:155399.3-155400.57" + process $proc$libresoc.v:155399$8041 assign { } { } assign $0\mul_op__insn_type$2[6:0]$8042 \mul_op__insn_type$2$next sync posedge \coresync_clk update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8042 end - attribute \src "libresoc.v:155402.3-155403.53" - process $proc$libresoc.v:155402$8043 + attribute \src "libresoc.v:155401.3-155402.53" + process $proc$libresoc.v:155401$8043 assign { } { } assign $0\mul_op__fn_unit$3[13:0]$8044 \mul_op__fn_unit$3$next sync posedge \coresync_clk update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8044 end - attribute \src "libresoc.v:155404.3-155405.67" - process $proc$libresoc.v:155404$8045 + attribute \src "libresoc.v:155403.3-155404.67" + process $proc$libresoc.v:155403$8045 assign { } { } assign $0\mul_op__imm_data__data$4[63:0]$8046 \mul_op__imm_data__data$4$next sync posedge \coresync_clk update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8046 end - attribute \src "libresoc.v:155406.3-155407.63" - process $proc$libresoc.v:155406$8047 + attribute \src "libresoc.v:155405.3-155406.63" + process $proc$libresoc.v:155405$8047 assign { } { } assign $0\mul_op__imm_data__ok$5[0:0]$8048 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8048 end - attribute \src "libresoc.v:155408.3-155409.51" - process $proc$libresoc.v:155408$8049 + attribute \src "libresoc.v:155407.3-155408.51" + process $proc$libresoc.v:155407$8049 assign { } { } assign $0\mul_op__rc__rc$6[0:0]$8050 \mul_op__rc__rc$6$next sync posedge \coresync_clk update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8050 end - attribute \src "libresoc.v:155410.3-155411.51" - process $proc$libresoc.v:155410$8051 + attribute \src "libresoc.v:155409.3-155410.51" + process $proc$libresoc.v:155409$8051 assign { } { } assign $0\mul_op__rc__ok$7[0:0]$8052 \mul_op__rc__ok$7$next sync posedge \coresync_clk update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8052 end - attribute \src "libresoc.v:155412.3-155413.51" - process $proc$libresoc.v:155412$8053 + attribute \src "libresoc.v:155411.3-155412.51" + process $proc$libresoc.v:155411$8053 assign { } { } assign $0\mul_op__oe__oe$8[0:0]$8054 \mul_op__oe__oe$8$next sync posedge \coresync_clk update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8054 end - attribute \src "libresoc.v:155414.3-155415.51" - process $proc$libresoc.v:155414$8055 + attribute \src "libresoc.v:155413.3-155414.51" + process $proc$libresoc.v:155413$8055 assign { } { } assign $0\mul_op__oe__ok$9[0:0]$8056 \mul_op__oe__ok$9$next sync posedge \coresync_clk update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8056 end - attribute \src "libresoc.v:155416.3-155417.59" - process $proc$libresoc.v:155416$8057 + attribute \src "libresoc.v:155415.3-155416.59" + process $proc$libresoc.v:155415$8057 assign { } { } assign $0\mul_op__write_cr0$10[0:0]$8058 \mul_op__write_cr0$10$next sync posedge \coresync_clk update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8058 end - attribute \src "libresoc.v:155418.3-155419.57" - process $proc$libresoc.v:155418$8059 + attribute \src "libresoc.v:155417.3-155418.57" + process $proc$libresoc.v:155417$8059 assign { } { } assign $0\mul_op__is_32bit$11[0:0]$8060 \mul_op__is_32bit$11$next sync posedge \coresync_clk update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8060 end - attribute \src "libresoc.v:155420.3-155421.59" - process $proc$libresoc.v:155420$8061 + attribute \src "libresoc.v:155419.3-155420.59" + process $proc$libresoc.v:155419$8061 assign { } { } assign $0\mul_op__is_signed$12[0:0]$8062 \mul_op__is_signed$12$next sync posedge \coresync_clk update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8062 end - attribute \src "libresoc.v:155422.3-155423.49" - process $proc$libresoc.v:155422$8063 + attribute \src "libresoc.v:155421.3-155422.49" + process $proc$libresoc.v:155421$8063 assign { } { } assign $0\mul_op__insn$13[31:0]$8064 \mul_op__insn$13$next sync posedge \coresync_clk update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8064 end - attribute \src "libresoc.v:155424.3-155425.33" - process $proc$libresoc.v:155424$8065 + attribute \src "libresoc.v:155423.3-155424.33" + process $proc$libresoc.v:155423$8065 assign { } { } assign $0\muxid$1[1:0]$8066 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$8066 end - attribute \src "libresoc.v:155426.3-155427.29" - process $proc$libresoc.v:155426$8067 + attribute \src "libresoc.v:155425.3-155426.29" + process $proc$libresoc.v:155425$8067 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:155473.3-155490.6" - process $proc$libresoc.v:155473$8068 + attribute \src "libresoc.v:155472.3-155489.6" + process $proc$libresoc.v:155472$8068 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$8069 $2\r_busy$next[0:0]$8071 - attribute \src "libresoc.v:155474.5-155474.29" + attribute \src "libresoc.v:155473.5-155473.29" switch \initial - attribute \src "libresoc.v:155474.9-155474.17" + attribute \src "libresoc.v:155473.9-155473.17" case 1'1 case end @@ -323887,14 +320697,14 @@ module \mul_pipe2 sync always update \r_busy$next $0\r_busy$next[0:0]$8069 end - attribute \src "libresoc.v:155491.3-155503.6" - process $proc$libresoc.v:155491$8072 + attribute \src "libresoc.v:155490.3-155502.6" + process $proc$libresoc.v:155490$8072 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$8073 $1\muxid$1$next[1:0]$8074 - attribute \src "libresoc.v:155492.5-155492.29" + attribute \src "libresoc.v:155491.5-155491.29" switch \initial - attribute \src "libresoc.v:155492.9-155492.17" + attribute \src "libresoc.v:155491.9-155491.17" case 1'1 case end @@ -323914,8 +320724,8 @@ module \mul_pipe2 sync always update \muxid$1$next $0\muxid$1$next[1:0]$8073 end - attribute \src "libresoc.v:155504.3-155539.6" - process $proc$libresoc.v:155504$8075 + attribute \src "libresoc.v:155503.3-155538.6" + process $proc$libresoc.v:155503$8075 assign { } { } assign { } { } assign { } { } @@ -323958,9 +320768,9 @@ module \mul_pipe2 assign $0\mul_op__oe__ok$9$next[0:0]$8084 $2\mul_op__oe__ok$9$next[0:0]$8103 assign $0\mul_op__rc__ok$7$next[0:0]$8085 $2\mul_op__rc__ok$7$next[0:0]$8104 assign $0\mul_op__rc__rc$6$next[0:0]$8086 $2\mul_op__rc__rc$6$next[0:0]$8105 - attribute \src "libresoc.v:155505.5-155505.29" + attribute \src "libresoc.v:155504.5-155504.29" switch \initial - attribute \src "libresoc.v:155505.9-155505.17" + attribute \src "libresoc.v:155504.9-155504.17" case 1'1 case end @@ -324048,14 +320858,14 @@ module \mul_pipe2 update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8086 update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8087 end - attribute \src "libresoc.v:155540.3-155552.6" - process $proc$libresoc.v:155540$8106 + attribute \src "libresoc.v:155539.3-155551.6" + process $proc$libresoc.v:155539$8106 assign { } { } assign { } { } assign $0\o$next[128:0]$8107 $1\o$next[128:0]$8108 - attribute \src "libresoc.v:155541.5-155541.29" + attribute \src "libresoc.v:155540.5-155540.29" switch \initial - attribute \src "libresoc.v:155541.9-155541.17" + attribute \src "libresoc.v:155540.9-155540.17" case 1'1 case end @@ -324075,14 +320885,14 @@ module \mul_pipe2 sync always update \o$next $0\o$next[128:0]$8107 end - attribute \src "libresoc.v:155553.3-155565.6" - process $proc$libresoc.v:155553$8109 + attribute \src "libresoc.v:155552.3-155564.6" + process $proc$libresoc.v:155552$8109 assign { } { } assign { } { } assign $0\xer_so$14$next[0:0]$8110 $1\xer_so$14$next[0:0]$8111 - attribute \src "libresoc.v:155554.5-155554.29" + attribute \src "libresoc.v:155553.5-155553.29" switch \initial - attribute \src "libresoc.v:155554.9-155554.17" + attribute \src "libresoc.v:155553.9-155553.17" case 1'1 case end @@ -324102,14 +320912,14 @@ module \mul_pipe2 sync always update \xer_so$14$next $0\xer_so$14$next[0:0]$8110 end - attribute \src "libresoc.v:155566.3-155578.6" - process $proc$libresoc.v:155566$8112 + attribute \src "libresoc.v:155565.3-155577.6" + process $proc$libresoc.v:155565$8112 assign { } { } assign { } { } assign $0\neg_res$15$next[0:0]$8113 $1\neg_res$15$next[0:0]$8114 - attribute \src "libresoc.v:155567.5-155567.29" + attribute \src "libresoc.v:155566.5-155566.29" switch \initial - attribute \src "libresoc.v:155567.9-155567.17" + attribute \src "libresoc.v:155566.9-155566.17" case 1'1 case end @@ -324129,14 +320939,14 @@ module \mul_pipe2 sync always update \neg_res$15$next $0\neg_res$15$next[0:0]$8113 end - attribute \src "libresoc.v:155579.3-155591.6" - process $proc$libresoc.v:155579$8115 + attribute \src "libresoc.v:155578.3-155590.6" + process $proc$libresoc.v:155578$8115 assign { } { } assign { } { } assign $0\neg_res32$16$next[0:0]$8116 $1\neg_res32$16$next[0:0]$8117 - attribute \src "libresoc.v:155580.5-155580.29" + attribute \src "libresoc.v:155579.5-155579.29" switch \initial - attribute \src "libresoc.v:155580.9-155580.17" + attribute \src "libresoc.v:155579.9-155579.17" case 1'1 case end @@ -324156,7 +320966,7 @@ module \mul_pipe2 sync always update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8116 end - connect \$34 $and$libresoc.v:155391$8033_Y + connect \$34 $and$libresoc.v:155390$8033_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$52 \mul2_neg_res32$32 @@ -324176,213 +320986,213 @@ module \mul_pipe2 connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul2_muxid \muxid end -attribute \src "libresoc.v:155614.1-156910.10" +attribute \src "libresoc.v:155613.1-156909.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" attribute \generator "nMigen" module \mul_pipe3 - attribute \src "libresoc.v:156828.3-156846.6" + attribute \src "libresoc.v:156827.3-156845.6" wire width 4 $0\cr_a$next[3:0]$8236 - attribute \src "libresoc.v:156620.3-156621.25" + attribute \src "libresoc.v:156619.3-156620.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:156828.3-156846.6" + attribute \src "libresoc.v:156827.3-156845.6" wire $0\cr_a_ok$next[0:0]$8237 - attribute \src "libresoc.v:156622.3-156623.31" + attribute \src "libresoc.v:156621.3-156622.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:155615.7-155615.20" + attribute \src "libresoc.v:155614.7-155614.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8199 - attribute \src "libresoc.v:156630.3-156631.53" + attribute \src "libresoc.v:156629.3-156630.53" wire width 14 $0\mul_op__fn_unit$3[13:0]$8167 - attribute \src "libresoc.v:155926.14-155926.44" + attribute \src "libresoc.v:155925.14-155925.44" wire width 14 $0\mul_op__fn_unit$3[13:0]$8257 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8200 - attribute \src "libresoc.v:156632.3-156633.67" + attribute \src "libresoc.v:156631.3-156632.67" wire width 64 $0\mul_op__imm_data__data$4[63:0]$8169 - attribute \src "libresoc.v:155950.14-155950.63" + attribute \src "libresoc.v:155949.14-155949.63" wire width 64 $0\mul_op__imm_data__data$4[63:0]$8259 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $0\mul_op__imm_data__ok$5$next[0:0]$8201 - attribute \src "libresoc.v:156634.3-156635.63" + attribute \src "libresoc.v:156633.3-156634.63" wire $0\mul_op__imm_data__ok$5[0:0]$8171 - attribute \src "libresoc.v:155959.7-155959.38" + attribute \src "libresoc.v:155958.7-155958.38" wire $0\mul_op__imm_data__ok$5[0:0]$8261 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire width 32 $0\mul_op__insn$13$next[31:0]$8202 - attribute \src "libresoc.v:156650.3-156651.49" + attribute \src "libresoc.v:156649.3-156650.49" wire width 32 $0\mul_op__insn$13[31:0]$8187 - attribute \src "libresoc.v:155968.14-155968.39" + attribute \src "libresoc.v:155967.14-155967.39" wire width 32 $0\mul_op__insn$13[31:0]$8263 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire width 7 $0\mul_op__insn_type$2$next[6:0]$8203 - attribute \src "libresoc.v:156628.3-156629.57" + attribute \src "libresoc.v:156627.3-156628.57" wire width 7 $0\mul_op__insn_type$2[6:0]$8165 - attribute \src "libresoc.v:156127.13-156127.42" + attribute \src "libresoc.v:156126.13-156126.42" wire width 7 $0\mul_op__insn_type$2[6:0]$8265 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $0\mul_op__is_32bit$11$next[0:0]$8204 - attribute \src "libresoc.v:156646.3-156647.57" + attribute \src "libresoc.v:156645.3-156646.57" wire $0\mul_op__is_32bit$11[0:0]$8183 - attribute \src "libresoc.v:156211.7-156211.35" + attribute \src "libresoc.v:156210.7-156210.35" wire $0\mul_op__is_32bit$11[0:0]$8267 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $0\mul_op__is_signed$12$next[0:0]$8205 - attribute \src "libresoc.v:156648.3-156649.59" + attribute \src "libresoc.v:156647.3-156648.59" wire $0\mul_op__is_signed$12[0:0]$8185 - attribute \src "libresoc.v:156220.7-156220.36" + attribute \src "libresoc.v:156219.7-156219.36" wire $0\mul_op__is_signed$12[0:0]$8269 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $0\mul_op__oe__oe$8$next[0:0]$8206 - attribute \src "libresoc.v:156640.3-156641.51" + attribute \src "libresoc.v:156639.3-156640.51" wire $0\mul_op__oe__oe$8[0:0]$8177 - attribute \src "libresoc.v:156231.7-156231.32" + attribute \src "libresoc.v:156230.7-156230.32" wire $0\mul_op__oe__oe$8[0:0]$8271 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $0\mul_op__oe__ok$9$next[0:0]$8207 - attribute \src "libresoc.v:156642.3-156643.51" + attribute \src "libresoc.v:156641.3-156642.51" wire $0\mul_op__oe__ok$9[0:0]$8179 - attribute \src "libresoc.v:156240.7-156240.32" + attribute \src "libresoc.v:156239.7-156239.32" wire $0\mul_op__oe__ok$9[0:0]$8273 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $0\mul_op__rc__ok$7$next[0:0]$8208 - attribute \src "libresoc.v:156638.3-156639.51" + attribute \src "libresoc.v:156637.3-156638.51" wire $0\mul_op__rc__ok$7[0:0]$8175 - attribute \src "libresoc.v:156249.7-156249.32" + attribute \src "libresoc.v:156248.7-156248.32" wire $0\mul_op__rc__ok$7[0:0]$8275 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $0\mul_op__rc__rc$6$next[0:0]$8209 - attribute \src "libresoc.v:156636.3-156637.51" + attribute \src "libresoc.v:156635.3-156636.51" wire $0\mul_op__rc__rc$6[0:0]$8173 - attribute \src "libresoc.v:156256.7-156256.32" + attribute \src "libresoc.v:156255.7-156255.32" wire $0\mul_op__rc__rc$6[0:0]$8277 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $0\mul_op__write_cr0$10$next[0:0]$8210 - attribute \src "libresoc.v:156644.3-156645.59" + attribute \src "libresoc.v:156643.3-156644.59" wire $0\mul_op__write_cr0$10[0:0]$8181 - attribute \src "libresoc.v:156265.7-156265.36" + attribute \src "libresoc.v:156264.7-156264.36" wire $0\mul_op__write_cr0$10[0:0]$8279 - attribute \src "libresoc.v:156760.3-156772.6" + attribute \src "libresoc.v:156759.3-156771.6" wire width 2 $0\muxid$1$next[1:0]$8196 - attribute \src "libresoc.v:156652.3-156653.33" + attribute \src "libresoc.v:156651.3-156652.33" wire width 2 $0\muxid$1[1:0]$8189 - attribute \src "libresoc.v:156274.13-156274.29" + attribute \src "libresoc.v:156273.13-156273.29" wire width 2 $0\muxid$1[1:0]$8281 - attribute \src "libresoc.v:156809.3-156827.6" + attribute \src "libresoc.v:156808.3-156826.6" wire width 64 $0\o$14$next[63:0]$8231 - attribute \src "libresoc.v:156624.3-156625.27" + attribute \src "libresoc.v:156623.3-156624.27" wire width 64 $0\o$14[63:0]$8162 - attribute \src "libresoc.v:156295.14-156295.43" + attribute \src "libresoc.v:156294.14-156294.43" wire width 64 $0\o$14[63:0]$8283 - attribute \src "libresoc.v:156809.3-156827.6" + attribute \src "libresoc.v:156808.3-156826.6" wire $0\o_ok$next[0:0]$8230 - attribute \src "libresoc.v:156626.3-156627.25" + attribute \src "libresoc.v:156625.3-156626.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:156742.3-156759.6" + attribute \src "libresoc.v:156741.3-156758.6" wire $0\r_busy$next[0:0]$8192 - attribute \src "libresoc.v:156654.3-156655.29" + attribute \src "libresoc.v:156653.3-156654.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:156847.3-156865.6" + attribute \src "libresoc.v:156846.3-156864.6" wire width 2 $0\xer_ov$next[1:0]$8242 - attribute \src "libresoc.v:156616.3-156617.29" + attribute \src "libresoc.v:156615.3-156616.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:156847.3-156865.6" + attribute \src "libresoc.v:156846.3-156864.6" wire $0\xer_ov_ok$next[0:0]$8243 - attribute \src "libresoc.v:156618.3-156619.35" + attribute \src "libresoc.v:156617.3-156618.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:156866.3-156884.6" + attribute \src "libresoc.v:156865.3-156883.6" wire $0\xer_so$15$next[0:0]$8249 - attribute \src "libresoc.v:156612.3-156613.37" + attribute \src "libresoc.v:156611.3-156612.37" wire $0\xer_so$15[0:0]$8155 - attribute \src "libresoc.v:156597.7-156597.25" + attribute \src "libresoc.v:156596.7-156596.25" wire $0\xer_so$15[0:0]$8289 - attribute \src "libresoc.v:156866.3-156884.6" + attribute \src "libresoc.v:156865.3-156883.6" wire $0\xer_so_ok$next[0:0]$8248 - attribute \src "libresoc.v:156614.3-156615.35" + attribute \src "libresoc.v:156613.3-156614.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:156828.3-156846.6" + attribute \src "libresoc.v:156827.3-156845.6" wire width 4 $1\cr_a$next[3:0]$8238 - attribute \src "libresoc.v:155624.13-155624.24" + attribute \src "libresoc.v:155623.13-155623.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:156828.3-156846.6" + attribute \src "libresoc.v:156827.3-156845.6" wire $1\cr_a_ok$next[0:0]$8239 - attribute \src "libresoc.v:155633.7-155633.21" + attribute \src "libresoc.v:155632.7-155632.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8211 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8212 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $1\mul_op__imm_data__ok$5$next[0:0]$8213 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire width 32 $1\mul_op__insn$13$next[31:0]$8214 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire width 7 $1\mul_op__insn_type$2$next[6:0]$8215 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $1\mul_op__is_32bit$11$next[0:0]$8216 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $1\mul_op__is_signed$12$next[0:0]$8217 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $1\mul_op__oe__oe$8$next[0:0]$8218 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $1\mul_op__oe__ok$9$next[0:0]$8219 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $1\mul_op__rc__ok$7$next[0:0]$8220 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $1\mul_op__rc__rc$6$next[0:0]$8221 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $1\mul_op__write_cr0$10$next[0:0]$8222 - attribute \src "libresoc.v:156760.3-156772.6" + attribute \src "libresoc.v:156759.3-156771.6" wire width 2 $1\muxid$1$next[1:0]$8197 - attribute \src "libresoc.v:156809.3-156827.6" + attribute \src "libresoc.v:156808.3-156826.6" wire width 64 $1\o$14$next[63:0]$8233 - attribute \src "libresoc.v:156809.3-156827.6" + attribute \src "libresoc.v:156808.3-156826.6" wire $1\o_ok$next[0:0]$8232 - attribute \src "libresoc.v:156302.7-156302.18" + attribute \src "libresoc.v:156301.7-156301.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:156742.3-156759.6" + attribute \src "libresoc.v:156741.3-156758.6" wire $1\r_busy$next[0:0]$8193 - attribute \src "libresoc.v:156574.7-156574.20" + attribute \src "libresoc.v:156573.7-156573.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:156847.3-156865.6" + attribute \src "libresoc.v:156846.3-156864.6" wire width 2 $1\xer_ov$next[1:0]$8244 - attribute \src "libresoc.v:156579.13-156579.26" + attribute \src "libresoc.v:156578.13-156578.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:156847.3-156865.6" + attribute \src "libresoc.v:156846.3-156864.6" wire $1\xer_ov_ok$next[0:0]$8245 - attribute \src "libresoc.v:156586.7-156586.23" + attribute \src "libresoc.v:156585.7-156585.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:156866.3-156884.6" + attribute \src "libresoc.v:156865.3-156883.6" wire $1\xer_so$15$next[0:0]$8251 - attribute \src "libresoc.v:156866.3-156884.6" + attribute \src "libresoc.v:156865.3-156883.6" wire $1\xer_so_ok$next[0:0]$8250 - attribute \src "libresoc.v:156604.7-156604.23" + attribute \src "libresoc.v:156603.7-156603.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:156828.3-156846.6" + attribute \src "libresoc.v:156827.3-156845.6" wire $2\cr_a_ok$next[0:0]$8240 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8223 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $2\mul_op__imm_data__ok$5$next[0:0]$8224 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $2\mul_op__oe__oe$8$next[0:0]$8225 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $2\mul_op__oe__ok$9$next[0:0]$8226 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $2\mul_op__rc__ok$7$next[0:0]$8227 - attribute \src "libresoc.v:156773.3-156808.6" + attribute \src "libresoc.v:156772.3-156807.6" wire $2\mul_op__rc__rc$6$next[0:0]$8228 - attribute \src "libresoc.v:156809.3-156827.6" + attribute \src "libresoc.v:156808.3-156826.6" wire $2\o_ok$next[0:0]$8234 - attribute \src "libresoc.v:156742.3-156759.6" + attribute \src "libresoc.v:156741.3-156758.6" wire $2\r_busy$next[0:0]$8194 - attribute \src "libresoc.v:156847.3-156865.6" + attribute \src "libresoc.v:156846.3-156864.6" wire $2\xer_ov_ok$next[0:0]$8246 - attribute \src "libresoc.v:156866.3-156884.6" + attribute \src "libresoc.v:156865.3-156883.6" wire $2\xer_so_ok$next[0:0]$8252 - attribute \src "libresoc.v:156611.18-156611.118" - wire $and$libresoc.v:156611$8153_Y + attribute \src "libresoc.v:156610.18-156610.118" + wire $and$libresoc.v:156610$8153_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$56 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" @@ -324407,7 +321217,7 @@ module \mul_pipe3 wire \cr_a_ok$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:155615.7-155615.15" + attribute \src "libresoc.v:155614.7-155614.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -325360,7 +322170,7 @@ module \mul_pipe3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:156611$8153 + cell $and $and$libresoc.v:156610$8153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325368,10 +322178,10 @@ module \mul_pipe3 parameter \Y_WIDTH 1 connect \A \p_valid_i$55 connect \B \p_ready_o - connect \Y $and$libresoc.v:156611$8153_Y + connect \Y $and$libresoc.v:156610$8153_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:156656.8-156692.4" + attribute \src "libresoc.v:156655.8-156691.4" cell \mul3 \mul3 connect \mul_op__fn_unit \mul3_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 @@ -325410,13 +322220,13 @@ module \mul_pipe3 connect \xer_so_ok \mul3_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:156693.10-156696.4" + attribute \src "libresoc.v:156692.10-156695.4" cell \n$99 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:156697.16-156737.4" + attribute \src "libresoc.v:156696.16-156736.4" cell \output$100 \output connect \cr_a \output_cr_a connect \cr_a$16 \output_cr_a$46 @@ -325459,358 +322269,358 @@ module \mul_pipe3 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:156738.10-156741.4" + attribute \src "libresoc.v:156737.10-156740.4" cell \p$98 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:155615.7-155615.20" - process $proc$libresoc.v:155615$8253 + attribute \src "libresoc.v:155614.7-155614.20" + process $proc$libresoc.v:155614$8253 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155624.13-155624.24" - process $proc$libresoc.v:155624$8254 + attribute \src "libresoc.v:155623.13-155623.24" + process $proc$libresoc.v:155623$8254 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:155633.7-155633.21" - process $proc$libresoc.v:155633$8255 + attribute \src "libresoc.v:155632.7-155632.21" + process $proc$libresoc.v:155632$8255 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:155926.14-155926.44" - process $proc$libresoc.v:155926$8256 + attribute \src "libresoc.v:155925.14-155925.44" + process $proc$libresoc.v:155925$8256 assign { } { } assign $0\mul_op__fn_unit$3[13:0]$8257 14'00000000000000 sync always sync init update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8257 end - attribute \src "libresoc.v:155950.14-155950.63" - process $proc$libresoc.v:155950$8258 + attribute \src "libresoc.v:155949.14-155949.63" + process $proc$libresoc.v:155949$8258 assign { } { } assign $0\mul_op__imm_data__data$4[63:0]$8259 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8259 end - attribute \src "libresoc.v:155959.7-155959.38" - process $proc$libresoc.v:155959$8260 + attribute \src "libresoc.v:155958.7-155958.38" + process $proc$libresoc.v:155958$8260 assign { } { } assign $0\mul_op__imm_data__ok$5[0:0]$8261 1'0 sync always sync init update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8261 end - attribute \src "libresoc.v:155968.14-155968.39" - process $proc$libresoc.v:155968$8262 + attribute \src "libresoc.v:155967.14-155967.39" + process $proc$libresoc.v:155967$8262 assign { } { } assign $0\mul_op__insn$13[31:0]$8263 0 sync always sync init update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8263 end - attribute \src "libresoc.v:156127.13-156127.42" - process $proc$libresoc.v:156127$8264 + attribute \src "libresoc.v:156126.13-156126.42" + process $proc$libresoc.v:156126$8264 assign { } { } assign $0\mul_op__insn_type$2[6:0]$8265 7'0000000 sync always sync init update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8265 end - attribute \src "libresoc.v:156211.7-156211.35" - process $proc$libresoc.v:156211$8266 + attribute \src "libresoc.v:156210.7-156210.35" + process $proc$libresoc.v:156210$8266 assign { } { } assign $0\mul_op__is_32bit$11[0:0]$8267 1'0 sync always sync init update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8267 end - attribute \src "libresoc.v:156220.7-156220.36" - process $proc$libresoc.v:156220$8268 + attribute \src "libresoc.v:156219.7-156219.36" + process $proc$libresoc.v:156219$8268 assign { } { } assign $0\mul_op__is_signed$12[0:0]$8269 1'0 sync always sync init update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8269 end - attribute \src "libresoc.v:156231.7-156231.32" - process $proc$libresoc.v:156231$8270 + attribute \src "libresoc.v:156230.7-156230.32" + process $proc$libresoc.v:156230$8270 assign { } { } assign $0\mul_op__oe__oe$8[0:0]$8271 1'0 sync always sync init update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8271 end - attribute \src "libresoc.v:156240.7-156240.32" - process $proc$libresoc.v:156240$8272 + attribute \src "libresoc.v:156239.7-156239.32" + process $proc$libresoc.v:156239$8272 assign { } { } assign $0\mul_op__oe__ok$9[0:0]$8273 1'0 sync always sync init update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8273 end - attribute \src "libresoc.v:156249.7-156249.32" - process $proc$libresoc.v:156249$8274 + attribute \src "libresoc.v:156248.7-156248.32" + process $proc$libresoc.v:156248$8274 assign { } { } assign $0\mul_op__rc__ok$7[0:0]$8275 1'0 sync always sync init update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8275 end - attribute \src "libresoc.v:156256.7-156256.32" - process $proc$libresoc.v:156256$8276 + attribute \src "libresoc.v:156255.7-156255.32" + process $proc$libresoc.v:156255$8276 assign { } { } assign $0\mul_op__rc__rc$6[0:0]$8277 1'0 sync always sync init update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8277 end - attribute \src "libresoc.v:156265.7-156265.36" - process $proc$libresoc.v:156265$8278 + attribute \src "libresoc.v:156264.7-156264.36" + process $proc$libresoc.v:156264$8278 assign { } { } assign $0\mul_op__write_cr0$10[0:0]$8279 1'0 sync always sync init update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8279 end - attribute \src "libresoc.v:156274.13-156274.29" - process $proc$libresoc.v:156274$8280 + attribute \src "libresoc.v:156273.13-156273.29" + process $proc$libresoc.v:156273$8280 assign { } { } assign $0\muxid$1[1:0]$8281 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$8281 end - attribute \src "libresoc.v:156295.14-156295.43" - process $proc$libresoc.v:156295$8282 + attribute \src "libresoc.v:156294.14-156294.43" + process $proc$libresoc.v:156294$8282 assign { } { } assign $0\o$14[63:0]$8283 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o$14 $0\o$14[63:0]$8283 end - attribute \src "libresoc.v:156302.7-156302.18" - process $proc$libresoc.v:156302$8284 + attribute \src "libresoc.v:156301.7-156301.18" + process $proc$libresoc.v:156301$8284 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:156574.7-156574.20" - process $proc$libresoc.v:156574$8285 + attribute \src "libresoc.v:156573.7-156573.20" + process $proc$libresoc.v:156573$8285 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:156579.13-156579.26" - process $proc$libresoc.v:156579$8286 + attribute \src "libresoc.v:156578.13-156578.26" + process $proc$libresoc.v:156578$8286 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:156586.7-156586.23" - process $proc$libresoc.v:156586$8287 + attribute \src "libresoc.v:156585.7-156585.23" + process $proc$libresoc.v:156585$8287 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:156597.7-156597.25" - process $proc$libresoc.v:156597$8288 + attribute \src "libresoc.v:156596.7-156596.25" + process $proc$libresoc.v:156596$8288 assign { } { } assign $0\xer_so$15[0:0]$8289 1'0 sync always sync init update \xer_so$15 $0\xer_so$15[0:0]$8289 end - attribute \src "libresoc.v:156604.7-156604.23" - process $proc$libresoc.v:156604$8290 + attribute \src "libresoc.v:156603.7-156603.23" + process $proc$libresoc.v:156603$8290 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:156612.3-156613.37" - process $proc$libresoc.v:156612$8154 + attribute \src "libresoc.v:156611.3-156612.37" + process $proc$libresoc.v:156611$8154 assign { } { } assign $0\xer_so$15[0:0]$8155 \xer_so$15$next sync posedge \coresync_clk update \xer_so$15 $0\xer_so$15[0:0]$8155 end - attribute \src "libresoc.v:156614.3-156615.35" - process $proc$libresoc.v:156614$8156 + attribute \src "libresoc.v:156613.3-156614.35" + process $proc$libresoc.v:156613$8156 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:156616.3-156617.29" - process $proc$libresoc.v:156616$8157 + attribute \src "libresoc.v:156615.3-156616.29" + process $proc$libresoc.v:156615$8157 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:156618.3-156619.35" - process $proc$libresoc.v:156618$8158 + attribute \src "libresoc.v:156617.3-156618.35" + process $proc$libresoc.v:156617$8158 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:156620.3-156621.25" - process $proc$libresoc.v:156620$8159 + attribute \src "libresoc.v:156619.3-156620.25" + process $proc$libresoc.v:156619$8159 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:156622.3-156623.31" - process $proc$libresoc.v:156622$8160 + attribute \src "libresoc.v:156621.3-156622.31" + process $proc$libresoc.v:156621$8160 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:156624.3-156625.27" - process $proc$libresoc.v:156624$8161 + attribute \src "libresoc.v:156623.3-156624.27" + process $proc$libresoc.v:156623$8161 assign { } { } assign $0\o$14[63:0]$8162 \o$14$next sync posedge \coresync_clk update \o$14 $0\o$14[63:0]$8162 end - attribute \src "libresoc.v:156626.3-156627.25" - process $proc$libresoc.v:156626$8163 + attribute \src "libresoc.v:156625.3-156626.25" + process $proc$libresoc.v:156625$8163 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:156628.3-156629.57" - process $proc$libresoc.v:156628$8164 + attribute \src "libresoc.v:156627.3-156628.57" + process $proc$libresoc.v:156627$8164 assign { } { } assign $0\mul_op__insn_type$2[6:0]$8165 \mul_op__insn_type$2$next sync posedge \coresync_clk update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8165 end - attribute \src "libresoc.v:156630.3-156631.53" - process $proc$libresoc.v:156630$8166 + attribute \src "libresoc.v:156629.3-156630.53" + process $proc$libresoc.v:156629$8166 assign { } { } assign $0\mul_op__fn_unit$3[13:0]$8167 \mul_op__fn_unit$3$next sync posedge \coresync_clk update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8167 end - attribute \src "libresoc.v:156632.3-156633.67" - process $proc$libresoc.v:156632$8168 + attribute \src "libresoc.v:156631.3-156632.67" + process $proc$libresoc.v:156631$8168 assign { } { } assign $0\mul_op__imm_data__data$4[63:0]$8169 \mul_op__imm_data__data$4$next sync posedge \coresync_clk update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8169 end - attribute \src "libresoc.v:156634.3-156635.63" - process $proc$libresoc.v:156634$8170 + attribute \src "libresoc.v:156633.3-156634.63" + process $proc$libresoc.v:156633$8170 assign { } { } assign $0\mul_op__imm_data__ok$5[0:0]$8171 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8171 end - attribute \src "libresoc.v:156636.3-156637.51" - process $proc$libresoc.v:156636$8172 + attribute \src "libresoc.v:156635.3-156636.51" + process $proc$libresoc.v:156635$8172 assign { } { } assign $0\mul_op__rc__rc$6[0:0]$8173 \mul_op__rc__rc$6$next sync posedge \coresync_clk update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8173 end - attribute \src "libresoc.v:156638.3-156639.51" - process $proc$libresoc.v:156638$8174 + attribute \src "libresoc.v:156637.3-156638.51" + process $proc$libresoc.v:156637$8174 assign { } { } assign $0\mul_op__rc__ok$7[0:0]$8175 \mul_op__rc__ok$7$next sync posedge \coresync_clk update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8175 end - attribute \src "libresoc.v:156640.3-156641.51" - process $proc$libresoc.v:156640$8176 + attribute \src "libresoc.v:156639.3-156640.51" + process $proc$libresoc.v:156639$8176 assign { } { } assign $0\mul_op__oe__oe$8[0:0]$8177 \mul_op__oe__oe$8$next sync posedge \coresync_clk update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8177 end - attribute \src "libresoc.v:156642.3-156643.51" - process $proc$libresoc.v:156642$8178 + attribute \src "libresoc.v:156641.3-156642.51" + process $proc$libresoc.v:156641$8178 assign { } { } assign $0\mul_op__oe__ok$9[0:0]$8179 \mul_op__oe__ok$9$next sync posedge \coresync_clk update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8179 end - attribute \src "libresoc.v:156644.3-156645.59" - process $proc$libresoc.v:156644$8180 + attribute \src "libresoc.v:156643.3-156644.59" + process $proc$libresoc.v:156643$8180 assign { } { } assign $0\mul_op__write_cr0$10[0:0]$8181 \mul_op__write_cr0$10$next sync posedge \coresync_clk update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8181 end - attribute \src "libresoc.v:156646.3-156647.57" - process $proc$libresoc.v:156646$8182 + attribute \src "libresoc.v:156645.3-156646.57" + process $proc$libresoc.v:156645$8182 assign { } { } assign $0\mul_op__is_32bit$11[0:0]$8183 \mul_op__is_32bit$11$next sync posedge \coresync_clk update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8183 end - attribute \src "libresoc.v:156648.3-156649.59" - process $proc$libresoc.v:156648$8184 + attribute \src "libresoc.v:156647.3-156648.59" + process $proc$libresoc.v:156647$8184 assign { } { } assign $0\mul_op__is_signed$12[0:0]$8185 \mul_op__is_signed$12$next sync posedge \coresync_clk update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8185 end - attribute \src "libresoc.v:156650.3-156651.49" - process $proc$libresoc.v:156650$8186 + attribute \src "libresoc.v:156649.3-156650.49" + process $proc$libresoc.v:156649$8186 assign { } { } assign $0\mul_op__insn$13[31:0]$8187 \mul_op__insn$13$next sync posedge \coresync_clk update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8187 end - attribute \src "libresoc.v:156652.3-156653.33" - process $proc$libresoc.v:156652$8188 + attribute \src "libresoc.v:156651.3-156652.33" + process $proc$libresoc.v:156651$8188 assign { } { } assign $0\muxid$1[1:0]$8189 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$8189 end - attribute \src "libresoc.v:156654.3-156655.29" - process $proc$libresoc.v:156654$8190 + attribute \src "libresoc.v:156653.3-156654.29" + process $proc$libresoc.v:156653$8190 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:156742.3-156759.6" - process $proc$libresoc.v:156742$8191 + attribute \src "libresoc.v:156741.3-156758.6" + process $proc$libresoc.v:156741$8191 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$8192 $2\r_busy$next[0:0]$8194 - attribute \src "libresoc.v:156743.5-156743.29" + attribute \src "libresoc.v:156742.5-156742.29" switch \initial - attribute \src "libresoc.v:156743.9-156743.17" + attribute \src "libresoc.v:156742.9-156742.17" case 1'1 case end @@ -325839,14 +322649,14 @@ module \mul_pipe3 sync always update \r_busy$next $0\r_busy$next[0:0]$8192 end - attribute \src "libresoc.v:156760.3-156772.6" - process $proc$libresoc.v:156760$8195 + attribute \src "libresoc.v:156759.3-156771.6" + process $proc$libresoc.v:156759$8195 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$8196 $1\muxid$1$next[1:0]$8197 - attribute \src "libresoc.v:156761.5-156761.29" + attribute \src "libresoc.v:156760.5-156760.29" switch \initial - attribute \src "libresoc.v:156761.9-156761.17" + attribute \src "libresoc.v:156760.9-156760.17" case 1'1 case end @@ -325866,8 +322676,8 @@ module \mul_pipe3 sync always update \muxid$1$next $0\muxid$1$next[1:0]$8196 end - attribute \src "libresoc.v:156773.3-156808.6" - process $proc$libresoc.v:156773$8198 + attribute \src "libresoc.v:156772.3-156807.6" + process $proc$libresoc.v:156772$8198 assign { } { } assign { } { } assign { } { } @@ -325910,9 +322720,9 @@ module \mul_pipe3 assign $0\mul_op__oe__ok$9$next[0:0]$8207 $2\mul_op__oe__ok$9$next[0:0]$8226 assign $0\mul_op__rc__ok$7$next[0:0]$8208 $2\mul_op__rc__ok$7$next[0:0]$8227 assign $0\mul_op__rc__rc$6$next[0:0]$8209 $2\mul_op__rc__rc$6$next[0:0]$8228 - attribute \src "libresoc.v:156774.5-156774.29" + attribute \src "libresoc.v:156773.5-156773.29" switch \initial - attribute \src "libresoc.v:156774.9-156774.17" + attribute \src "libresoc.v:156773.9-156773.17" case 1'1 case end @@ -326000,8 +322810,8 @@ module \mul_pipe3 update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8209 update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8210 end - attribute \src "libresoc.v:156809.3-156827.6" - process $proc$libresoc.v:156809$8229 + attribute \src "libresoc.v:156808.3-156826.6" + process $proc$libresoc.v:156808$8229 assign { } { } assign { } { } assign { } { } @@ -326009,9 +322819,9 @@ module \mul_pipe3 assign { } { } assign $0\o$14$next[63:0]$8231 $1\o$14$next[63:0]$8233 assign $0\o_ok$next[0:0]$8230 $2\o_ok$next[0:0]$8234 - attribute \src "libresoc.v:156810.5-156810.29" + attribute \src "libresoc.v:156809.5-156809.29" switch \initial - attribute \src "libresoc.v:156810.9-156810.17" + attribute \src "libresoc.v:156809.9-156809.17" case 1'1 case end @@ -326044,8 +322854,8 @@ module \mul_pipe3 update \o_ok$next $0\o_ok$next[0:0]$8230 update \o$14$next $0\o$14$next[63:0]$8231 end - attribute \src "libresoc.v:156828.3-156846.6" - process $proc$libresoc.v:156828$8235 + attribute \src "libresoc.v:156827.3-156845.6" + process $proc$libresoc.v:156827$8235 assign { } { } assign { } { } assign { } { } @@ -326053,9 +322863,9 @@ module \mul_pipe3 assign $0\cr_a$next[3:0]$8236 $1\cr_a$next[3:0]$8238 assign { } { } assign $0\cr_a_ok$next[0:0]$8237 $2\cr_a_ok$next[0:0]$8240 - attribute \src "libresoc.v:156829.5-156829.29" + attribute \src "libresoc.v:156828.5-156828.29" switch \initial - attribute \src "libresoc.v:156829.9-156829.17" + attribute \src "libresoc.v:156828.9-156828.17" case 1'1 case end @@ -326088,8 +322898,8 @@ module \mul_pipe3 update \cr_a$next $0\cr_a$next[3:0]$8236 update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8237 end - attribute \src "libresoc.v:156847.3-156865.6" - process $proc$libresoc.v:156847$8241 + attribute \src "libresoc.v:156846.3-156864.6" + process $proc$libresoc.v:156846$8241 assign { } { } assign { } { } assign { } { } @@ -326097,9 +322907,9 @@ module \mul_pipe3 assign $0\xer_ov$next[1:0]$8242 $1\xer_ov$next[1:0]$8244 assign { } { } assign $0\xer_ov_ok$next[0:0]$8243 $2\xer_ov_ok$next[0:0]$8246 - attribute \src "libresoc.v:156848.5-156848.29" + attribute \src "libresoc.v:156847.5-156847.29" switch \initial - attribute \src "libresoc.v:156848.9-156848.17" + attribute \src "libresoc.v:156847.9-156847.17" case 1'1 case end @@ -326132,8 +322942,8 @@ module \mul_pipe3 update \xer_ov$next $0\xer_ov$next[1:0]$8242 update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8243 end - attribute \src "libresoc.v:156866.3-156884.6" - process $proc$libresoc.v:156866$8247 + attribute \src "libresoc.v:156865.3-156883.6" + process $proc$libresoc.v:156865$8247 assign { } { } assign { } { } assign { } { } @@ -326141,9 +322951,9 @@ module \mul_pipe3 assign { } { } assign $0\xer_so$15$next[0:0]$8249 $1\xer_so$15$next[0:0]$8251 assign $0\xer_so_ok$next[0:0]$8248 $2\xer_so_ok$next[0:0]$8252 - attribute \src "libresoc.v:156867.5-156867.29" + attribute \src "libresoc.v:156866.5-156866.29" switch \initial - attribute \src "libresoc.v:156867.9-156867.17" + attribute \src "libresoc.v:156866.9-156866.17" case 1'1 case end @@ -326176,7 +322986,7 @@ module \mul_pipe3 update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8248 update \xer_so$15$next $0\xer_so$15$next[0:0]$8249 end - connect \$56 $and$libresoc.v:156611$8153_Y + connect \$56 $and$libresoc.v:156610$8153_Y connect \cr_a$51 4'0000 connect \cr_a_ok$52 1'0 connect \p_ready_o \n_i_rdy_data @@ -326203,13 +323013,13 @@ module \mul_pipe3 connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul3_muxid \muxid end -attribute \src "libresoc.v:156914.1-156925.10" +attribute \src "libresoc.v:156913.1-156924.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.n" attribute \generator "nMigen" module \n - attribute \src "libresoc.v:156923.17-156923.111" - wire $and$libresoc.v:156923$8291_Y + attribute \src "libresoc.v:156922.17-156922.111" + wire $and$libresoc.v:156922$8291_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326219,7 +323029,7 @@ module \n attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156923$8291 + cell $and $and$libresoc.v:156922$8291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326227,18 +323037,18 @@ module \n parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156923$8291_Y + connect \Y $and$libresoc.v:156922$8291_Y end - connect \$1 $and$libresoc.v:156923$8291_Y + connect \$1 $and$libresoc.v:156922$8291_Y connect \trigger \$1 end -attribute \src "libresoc.v:156929.1-156940.10" +attribute \src "libresoc.v:156928.1-156939.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" attribute \generator "nMigen" module \n$109 - attribute \src "libresoc.v:156938.17-156938.111" - wire $and$libresoc.v:156938$8292_Y + attribute \src "libresoc.v:156937.17-156937.111" + wire $and$libresoc.v:156937$8292_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326248,7 +323058,7 @@ module \n$109 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156938$8292 + cell $and $and$libresoc.v:156937$8292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326256,18 +323066,18 @@ module \n$109 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156938$8292_Y + connect \Y $and$libresoc.v:156937$8292_Y end - connect \$1 $and$libresoc.v:156938$8292_Y + connect \$1 $and$libresoc.v:156937$8292_Y connect \trigger \$1 end -attribute \src "libresoc.v:156944.1-156955.10" +attribute \src "libresoc.v:156943.1-156954.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" attribute \generator "nMigen" module \n$112 - attribute \src "libresoc.v:156953.17-156953.111" - wire $and$libresoc.v:156953$8293_Y + attribute \src "libresoc.v:156952.17-156952.111" + wire $and$libresoc.v:156952$8293_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326277,7 +323087,7 @@ module \n$112 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156953$8293 + cell $and $and$libresoc.v:156952$8293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326285,18 +323095,18 @@ module \n$112 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156953$8293_Y + connect \Y $and$libresoc.v:156952$8293_Y end - connect \$1 $and$libresoc.v:156953$8293_Y + connect \$1 $and$libresoc.v:156952$8293_Y connect \trigger \$1 end -attribute \src "libresoc.v:156959.1-156970.10" +attribute \src "libresoc.v:156958.1-156969.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" attribute \generator "nMigen" module \n$117 - attribute \src "libresoc.v:156968.17-156968.111" - wire $and$libresoc.v:156968$8294_Y + attribute \src "libresoc.v:156967.17-156967.111" + wire $and$libresoc.v:156967$8294_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326306,7 +323116,7 @@ module \n$117 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156968$8294 + cell $and $and$libresoc.v:156967$8294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326314,18 +323124,18 @@ module \n$117 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156968$8294_Y + connect \Y $and$libresoc.v:156967$8294_Y end - connect \$1 $and$libresoc.v:156968$8294_Y + connect \$1 $and$libresoc.v:156967$8294_Y connect \trigger \$1 end -attribute \src "libresoc.v:156974.1-156985.10" +attribute \src "libresoc.v:156973.1-156984.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.n" attribute \generator "nMigen" module \n$18 - attribute \src "libresoc.v:156983.17-156983.111" - wire $and$libresoc.v:156983$8295_Y + attribute \src "libresoc.v:156982.17-156982.111" + wire $and$libresoc.v:156982$8295_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326335,7 +323145,7 @@ module \n$18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156983$8295 + cell $and $and$libresoc.v:156982$8295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326343,18 +323153,18 @@ module \n$18 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156983$8295_Y + connect \Y $and$libresoc.v:156982$8295_Y end - connect \$1 $and$libresoc.v:156983$8295_Y + connect \$1 $and$libresoc.v:156982$8295_Y connect \trigger \$1 end -attribute \src "libresoc.v:156989.1-157000.10" +attribute \src "libresoc.v:156988.1-156999.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n" attribute \generator "nMigen" module \n$2 - attribute \src "libresoc.v:156998.17-156998.111" - wire $and$libresoc.v:156998$8296_Y + attribute \src "libresoc.v:156997.17-156997.111" + wire $and$libresoc.v:156997$8296_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326364,7 +323174,7 @@ module \n$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156998$8296 + cell $and $and$libresoc.v:156997$8296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326372,18 +323182,18 @@ module \n$2 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156998$8296_Y + connect \Y $and$libresoc.v:156997$8296_Y end - connect \$1 $and$libresoc.v:156998$8296_Y + connect \$1 $and$libresoc.v:156997$8296_Y connect \trigger \$1 end -attribute \src "libresoc.v:157004.1-157015.10" +attribute \src "libresoc.v:157003.1-157014.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n" attribute \generator "nMigen" module \n$21 - attribute \src "libresoc.v:157013.17-157013.111" - wire $and$libresoc.v:157013$8297_Y + attribute \src "libresoc.v:157012.17-157012.111" + wire $and$libresoc.v:157012$8297_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326393,7 +323203,7 @@ module \n$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157013$8297 + cell $and $and$libresoc.v:157012$8297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326401,18 +323211,18 @@ module \n$21 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157013$8297_Y + connect \Y $and$libresoc.v:157012$8297_Y end - connect \$1 $and$libresoc.v:157013$8297_Y + connect \$1 $and$libresoc.v:157012$8297_Y connect \trigger \$1 end -attribute \src "libresoc.v:157019.1-157030.10" +attribute \src "libresoc.v:157018.1-157029.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.n" attribute \generator "nMigen" module \n$31 - attribute \src "libresoc.v:157028.17-157028.111" - wire $and$libresoc.v:157028$8298_Y + attribute \src "libresoc.v:157027.17-157027.111" + wire $and$libresoc.v:157027$8298_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326422,7 +323232,7 @@ module \n$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157028$8298 + cell $and $and$libresoc.v:157027$8298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326430,18 +323240,18 @@ module \n$31 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157028$8298_Y + connect \Y $and$libresoc.v:157027$8298_Y end - connect \$1 $and$libresoc.v:157028$8298_Y + connect \$1 $and$libresoc.v:157027$8298_Y connect \trigger \$1 end -attribute \src "libresoc.v:157034.1-157045.10" +attribute \src "libresoc.v:157033.1-157044.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.n" attribute \generator "nMigen" module \n$34 - attribute \src "libresoc.v:157043.17-157043.111" - wire $and$libresoc.v:157043$8299_Y + attribute \src "libresoc.v:157042.17-157042.111" + wire $and$libresoc.v:157042$8299_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326451,7 +323261,7 @@ module \n$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157043$8299 + cell $and $and$libresoc.v:157042$8299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326459,18 +323269,18 @@ module \n$34 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157043$8299_Y + connect \Y $and$libresoc.v:157042$8299_Y end - connect \$1 $and$libresoc.v:157043$8299_Y + connect \$1 $and$libresoc.v:157042$8299_Y connect \trigger \$1 end -attribute \src "libresoc.v:157049.1-157060.10" +attribute \src "libresoc.v:157048.1-157059.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.n" attribute \generator "nMigen" module \n$37 - attribute \src "libresoc.v:157058.17-157058.111" - wire $and$libresoc.v:157058$8300_Y + attribute \src "libresoc.v:157057.17-157057.111" + wire $and$libresoc.v:157057$8300_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326480,7 +323290,7 @@ module \n$37 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157058$8300 + cell $and $and$libresoc.v:157057$8300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326488,18 +323298,18 @@ module \n$37 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157058$8300_Y + connect \Y $and$libresoc.v:157057$8300_Y end - connect \$1 $and$libresoc.v:157058$8300_Y + connect \$1 $and$libresoc.v:157057$8300_Y connect \trigger \$1 end -attribute \src "libresoc.v:157064.1-157075.10" +attribute \src "libresoc.v:157063.1-157074.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.n" attribute \generator "nMigen" module \n$4 - attribute \src "libresoc.v:157073.17-157073.111" - wire $and$libresoc.v:157073$8301_Y + attribute \src "libresoc.v:157072.17-157072.111" + wire $and$libresoc.v:157072$8301_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326509,7 +323319,7 @@ module \n$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157073$8301 + cell $and $and$libresoc.v:157072$8301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326517,18 +323327,18 @@ module \n$4 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157073$8301_Y + connect \Y $and$libresoc.v:157072$8301_Y end - connect \$1 $and$libresoc.v:157073$8301_Y + connect \$1 $and$libresoc.v:157072$8301_Y connect \trigger \$1 end -attribute \src "libresoc.v:157079.1-157090.10" +attribute \src "libresoc.v:157078.1-157089.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.n" attribute \generator "nMigen" module \n$47 - attribute \src "libresoc.v:157088.17-157088.111" - wire $and$libresoc.v:157088$8302_Y + attribute \src "libresoc.v:157087.17-157087.111" + wire $and$libresoc.v:157087$8302_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326538,7 +323348,7 @@ module \n$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157088$8302 + cell $and $and$libresoc.v:157087$8302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326546,18 +323356,18 @@ module \n$47 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157088$8302_Y + connect \Y $and$libresoc.v:157087$8302_Y end - connect \$1 $and$libresoc.v:157088$8302_Y + connect \$1 $and$libresoc.v:157087$8302_Y connect \trigger \$1 end -attribute \src "libresoc.v:157094.1-157105.10" +attribute \src "libresoc.v:157093.1-157104.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.n" attribute \generator "nMigen" module \n$49 - attribute \src "libresoc.v:157103.17-157103.111" - wire $and$libresoc.v:157103$8303_Y + attribute \src "libresoc.v:157102.17-157102.111" + wire $and$libresoc.v:157102$8303_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326567,7 +323377,7 @@ module \n$49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157103$8303 + cell $and $and$libresoc.v:157102$8303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326575,18 +323385,18 @@ module \n$49 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157103$8303_Y + connect \Y $and$libresoc.v:157102$8303_Y end - connect \$1 $and$libresoc.v:157103$8303_Y + connect \$1 $and$libresoc.v:157102$8303_Y connect \trigger \$1 end -attribute \src "libresoc.v:157109.1-157120.10" +attribute \src "libresoc.v:157108.1-157119.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.n" attribute \generator "nMigen" module \n$53 - attribute \src "libresoc.v:157118.17-157118.111" - wire $and$libresoc.v:157118$8304_Y + attribute \src "libresoc.v:157117.17-157117.111" + wire $and$libresoc.v:157117$8304_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326596,7 +323406,7 @@ module \n$53 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157118$8304 + cell $and $and$libresoc.v:157117$8304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326604,18 +323414,18 @@ module \n$53 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157118$8304_Y + connect \Y $and$libresoc.v:157117$8304_Y end - connect \$1 $and$libresoc.v:157118$8304_Y + connect \$1 $and$libresoc.v:157117$8304_Y connect \trigger \$1 end -attribute \src "libresoc.v:157124.1-157135.10" +attribute \src "libresoc.v:157123.1-157134.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.n" attribute \generator "nMigen" module \n$6 - attribute \src "libresoc.v:157133.17-157133.111" - wire $and$libresoc.v:157133$8305_Y + attribute \src "libresoc.v:157132.17-157132.111" + wire $and$libresoc.v:157132$8305_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326625,7 +323435,7 @@ module \n$6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157133$8305 + cell $and $and$libresoc.v:157132$8305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326633,18 +323443,18 @@ module \n$6 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157133$8305_Y + connect \Y $and$libresoc.v:157132$8305_Y end - connect \$1 $and$libresoc.v:157133$8305_Y + connect \$1 $and$libresoc.v:157132$8305_Y connect \trigger \$1 end -attribute \src "libresoc.v:157139.1-157150.10" +attribute \src "libresoc.v:157138.1-157149.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.n" attribute \generator "nMigen" module \n$63 - attribute \src "libresoc.v:157148.17-157148.111" - wire $and$libresoc.v:157148$8306_Y + attribute \src "libresoc.v:157147.17-157147.111" + wire $and$libresoc.v:157147$8306_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326654,7 +323464,7 @@ module \n$63 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157148$8306 + cell $and $and$libresoc.v:157147$8306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326662,18 +323472,18 @@ module \n$63 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157148$8306_Y + connect \Y $and$libresoc.v:157147$8306_Y end - connect \$1 $and$libresoc.v:157148$8306_Y + connect \$1 $and$libresoc.v:157147$8306_Y connect \trigger \$1 end -attribute \src "libresoc.v:157154.1-157165.10" +attribute \src "libresoc.v:157153.1-157164.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.n" attribute \generator "nMigen" module \n$66 - attribute \src "libresoc.v:157163.17-157163.111" - wire $and$libresoc.v:157163$8307_Y + attribute \src "libresoc.v:157162.17-157162.111" + wire $and$libresoc.v:157162$8307_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326683,7 +323493,7 @@ module \n$66 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157163$8307 + cell $and $and$libresoc.v:157162$8307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326691,18 +323501,18 @@ module \n$66 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157163$8307_Y + connect \Y $and$libresoc.v:157162$8307_Y end - connect \$1 $and$libresoc.v:157163$8307_Y + connect \$1 $and$libresoc.v:157162$8307_Y connect \trigger \$1 end -attribute \src "libresoc.v:157169.1-157180.10" +attribute \src "libresoc.v:157168.1-157179.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.n" attribute \generator "nMigen" module \n$75 - attribute \src "libresoc.v:157178.17-157178.111" - wire $and$libresoc.v:157178$8308_Y + attribute \src "libresoc.v:157177.17-157177.111" + wire $and$libresoc.v:157177$8308_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326712,7 +323522,7 @@ module \n$75 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157178$8308 + cell $and $and$libresoc.v:157177$8308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326720,18 +323530,18 @@ module \n$75 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157178$8308_Y + connect \Y $and$libresoc.v:157177$8308_Y end - connect \$1 $and$libresoc.v:157178$8308_Y + connect \$1 $and$libresoc.v:157177$8308_Y connect \trigger \$1 end -attribute \src "libresoc.v:157184.1-157195.10" +attribute \src "libresoc.v:157183.1-157194.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.n" attribute \generator "nMigen" module \n$77 - attribute \src "libresoc.v:157193.17-157193.111" - wire $and$libresoc.v:157193$8309_Y + attribute \src "libresoc.v:157192.17-157192.111" + wire $and$libresoc.v:157192$8309_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326741,7 +323551,7 @@ module \n$77 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157193$8309 + cell $and $and$libresoc.v:157192$8309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326749,18 +323559,18 @@ module \n$77 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157193$8309_Y + connect \Y $and$libresoc.v:157192$8309_Y end - connect \$1 $and$libresoc.v:157193$8309_Y + connect \$1 $and$libresoc.v:157192$8309_Y connect \trigger \$1 end -attribute \src "libresoc.v:157199.1-157210.10" +attribute \src "libresoc.v:157198.1-157209.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.n" attribute \generator "nMigen" module \n$8 - attribute \src "libresoc.v:157208.17-157208.111" - wire $and$libresoc.v:157208$8310_Y + attribute \src "libresoc.v:157207.17-157207.111" + wire $and$libresoc.v:157207$8310_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326770,7 +323580,7 @@ module \n$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157208$8310 + cell $and $and$libresoc.v:157207$8310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326778,18 +323588,18 @@ module \n$8 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157208$8310_Y + connect \Y $and$libresoc.v:157207$8310_Y end - connect \$1 $and$libresoc.v:157208$8310_Y + connect \$1 $and$libresoc.v:157207$8310_Y connect \trigger \$1 end -attribute \src "libresoc.v:157214.1-157225.10" +attribute \src "libresoc.v:157213.1-157224.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.n" attribute \generator "nMigen" module \n$80 - attribute \src "libresoc.v:157223.17-157223.111" - wire $and$libresoc.v:157223$8311_Y + attribute \src "libresoc.v:157222.17-157222.111" + wire $and$libresoc.v:157222$8311_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326799,7 +323609,7 @@ module \n$80 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157223$8311 + cell $and $and$libresoc.v:157222$8311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326807,18 +323617,18 @@ module \n$80 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157223$8311_Y + connect \Y $and$libresoc.v:157222$8311_Y end - connect \$1 $and$libresoc.v:157223$8311_Y + connect \$1 $and$libresoc.v:157222$8311_Y connect \trigger \$1 end -attribute \src "libresoc.v:157229.1-157240.10" +attribute \src "libresoc.v:157228.1-157239.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.n" attribute \generator "nMigen" module \n$82 - attribute \src "libresoc.v:157238.17-157238.111" - wire $and$libresoc.v:157238$8312_Y + attribute \src "libresoc.v:157237.17-157237.111" + wire $and$libresoc.v:157237$8312_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326828,7 +323638,7 @@ module \n$82 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157238$8312 + cell $and $and$libresoc.v:157237$8312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326836,18 +323646,18 @@ module \n$82 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157238$8312_Y + connect \Y $and$libresoc.v:157237$8312_Y end - connect \$1 $and$libresoc.v:157238$8312_Y + connect \$1 $and$libresoc.v:157237$8312_Y connect \trigger \$1 end -attribute \src "libresoc.v:157244.1-157255.10" +attribute \src "libresoc.v:157243.1-157254.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.n" attribute \generator "nMigen" module \n$92 - attribute \src "libresoc.v:157253.17-157253.111" - wire $and$libresoc.v:157253$8313_Y + attribute \src "libresoc.v:157252.17-157252.111" + wire $and$libresoc.v:157252$8313_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326857,7 +323667,7 @@ module \n$92 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157253$8313 + cell $and $and$libresoc.v:157252$8313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326865,18 +323675,18 @@ module \n$92 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157253$8313_Y + connect \Y $and$libresoc.v:157252$8313_Y end - connect \$1 $and$libresoc.v:157253$8313_Y + connect \$1 $and$libresoc.v:157252$8313_Y connect \trigger \$1 end -attribute \src "libresoc.v:157259.1-157270.10" +attribute \src "libresoc.v:157258.1-157269.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.n" attribute \generator "nMigen" module \n$94 - attribute \src "libresoc.v:157268.17-157268.111" - wire $and$libresoc.v:157268$8314_Y + attribute \src "libresoc.v:157267.17-157267.111" + wire $and$libresoc.v:157267$8314_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326886,7 +323696,7 @@ module \n$94 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157268$8314 + cell $and $and$libresoc.v:157267$8314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326894,18 +323704,18 @@ module \n$94 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157268$8314_Y + connect \Y $and$libresoc.v:157267$8314_Y end - connect \$1 $and$libresoc.v:157268$8314_Y + connect \$1 $and$libresoc.v:157267$8314_Y connect \trigger \$1 end -attribute \src "libresoc.v:157274.1-157285.10" +attribute \src "libresoc.v:157273.1-157284.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.n" attribute \generator "nMigen" module \n$97 - attribute \src "libresoc.v:157283.17-157283.111" - wire $and$libresoc.v:157283$8315_Y + attribute \src "libresoc.v:157282.17-157282.111" + wire $and$libresoc.v:157282$8315_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326915,7 +323725,7 @@ module \n$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157283$8315 + cell $and $and$libresoc.v:157282$8315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326923,18 +323733,18 @@ module \n$97 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157283$8315_Y + connect \Y $and$libresoc.v:157282$8315_Y end - connect \$1 $and$libresoc.v:157283$8315_Y + connect \$1 $and$libresoc.v:157282$8315_Y connect \trigger \$1 end -attribute \src "libresoc.v:157289.1-157300.10" +attribute \src "libresoc.v:157288.1-157299.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.n" attribute \generator "nMigen" module \n$99 - attribute \src "libresoc.v:157298.17-157298.111" - wire $and$libresoc.v:157298$8316_Y + attribute \src "libresoc.v:157297.17-157297.111" + wire $and$libresoc.v:157297$8316_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -326944,7 +323754,7 @@ module \n$99 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157298$8316 + cell $and $and$libresoc.v:157297$8316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326952,42 +323762,42 @@ module \n$99 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157298$8316_Y + connect \Y $and$libresoc.v:157297$8316_Y end - connect \$1 $and$libresoc.v:157298$8316_Y + connect \$1 $and$libresoc.v:157297$8316_Y connect \trigger \$1 end -attribute \src "libresoc.v:157304.1-157362.10" +attribute \src "libresoc.v:157303.1-157361.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.opc_l" attribute \generator "nMigen" module \opc_l - attribute \src "libresoc.v:157305.7-157305.20" + attribute \src "libresoc.v:157304.7-157304.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157350.3-157358.6" + attribute \src "libresoc.v:157349.3-157357.6" wire $0\q_int$next[0:0]$8327 - attribute \src "libresoc.v:157348.3-157349.27" + attribute \src "libresoc.v:157347.3-157348.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157350.3-157358.6" + attribute \src "libresoc.v:157349.3-157357.6" wire $1\q_int$next[0:0]$8328 - attribute \src "libresoc.v:157327.7-157327.19" + attribute \src "libresoc.v:157326.7-157326.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157340.17-157340.96" - wire $and$libresoc.v:157340$8317_Y - attribute \src "libresoc.v:157345.17-157345.96" - wire $and$libresoc.v:157345$8322_Y - attribute \src "libresoc.v:157342.18-157342.93" - wire $not$libresoc.v:157342$8319_Y - attribute \src "libresoc.v:157344.17-157344.92" - wire $not$libresoc.v:157344$8321_Y - attribute \src "libresoc.v:157347.17-157347.92" - wire $not$libresoc.v:157347$8324_Y - attribute \src "libresoc.v:157341.18-157341.98" - wire $or$libresoc.v:157341$8318_Y - attribute \src "libresoc.v:157343.18-157343.99" - wire $or$libresoc.v:157343$8320_Y - attribute \src "libresoc.v:157346.17-157346.97" - wire $or$libresoc.v:157346$8323_Y + attribute \src "libresoc.v:157339.17-157339.96" + wire $and$libresoc.v:157339$8317_Y + attribute \src "libresoc.v:157344.17-157344.96" + wire $and$libresoc.v:157344$8322_Y + attribute \src "libresoc.v:157341.18-157341.93" + wire $not$libresoc.v:157341$8319_Y + attribute \src "libresoc.v:157343.17-157343.92" + wire $not$libresoc.v:157343$8321_Y + attribute \src "libresoc.v:157346.17-157346.92" + wire $not$libresoc.v:157346$8324_Y + attribute \src "libresoc.v:157340.18-157340.98" + wire $or$libresoc.v:157340$8318_Y + attribute \src "libresoc.v:157342.18-157342.99" + wire $or$libresoc.v:157342$8320_Y + attribute \src "libresoc.v:157345.17-157345.97" + wire $or$libresoc.v:157345$8323_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -327008,7 +323818,7 @@ module \opc_l wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:157305.7-157305.15" + attribute \src "libresoc.v:157304.7-157304.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -327025,7 +323835,7 @@ module \opc_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157340$8317 + cell $and $and$libresoc.v:157339$8317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327033,10 +323843,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157340$8317_Y + connect \Y $and$libresoc.v:157339$8317_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157345$8322 + cell $and $and$libresoc.v:157344$8322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327044,34 +323854,34 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157345$8322_Y + connect \Y $and$libresoc.v:157344$8322_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157342$8319 + cell $not $not$libresoc.v:157341$8319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157342$8319_Y + connect \Y $not$libresoc.v:157341$8319_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157344$8321 + cell $not $not$libresoc.v:157343$8321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157344$8321_Y + connect \Y $not$libresoc.v:157343$8321_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157347$8324 + cell $not $not$libresoc.v:157346$8324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157347$8324_Y + connect \Y $not$libresoc.v:157346$8324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157341$8318 + cell $or $or$libresoc.v:157340$8318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327079,10 +323889,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157341$8318_Y + connect \Y $or$libresoc.v:157340$8318_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157343$8320 + cell $or $or$libresoc.v:157342$8320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327090,10 +323900,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157343$8320_Y + connect \Y $or$libresoc.v:157342$8320_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157346$8323 + cell $or $or$libresoc.v:157345$8323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327101,39 +323911,39 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157346$8323_Y + connect \Y $or$libresoc.v:157345$8323_Y end - attribute \src "libresoc.v:157305.7-157305.20" - process $proc$libresoc.v:157305$8329 + attribute \src "libresoc.v:157304.7-157304.20" + process $proc$libresoc.v:157304$8329 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157327.7-157327.19" - process $proc$libresoc.v:157327$8330 + attribute \src "libresoc.v:157326.7-157326.19" + process $proc$libresoc.v:157326$8330 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157348.3-157349.27" - process $proc$libresoc.v:157348$8325 + attribute \src "libresoc.v:157347.3-157348.27" + process $proc$libresoc.v:157347$8325 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157350.3-157358.6" - process $proc$libresoc.v:157350$8326 + attribute \src "libresoc.v:157349.3-157357.6" + process $proc$libresoc.v:157349$8326 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8327 $1\q_int$next[0:0]$8328 - attribute \src "libresoc.v:157351.5-157351.29" + attribute \src "libresoc.v:157350.5-157350.29" switch \initial - attribute \src "libresoc.v:157351.9-157351.17" + attribute \src "libresoc.v:157350.9-157350.17" case 1'1 case end @@ -327149,49 +323959,49 @@ module \opc_l sync always update \q_int$next $0\q_int$next[0:0]$8327 end - connect \$9 $and$libresoc.v:157340$8317_Y - connect \$11 $or$libresoc.v:157341$8318_Y - connect \$13 $not$libresoc.v:157342$8319_Y - connect \$15 $or$libresoc.v:157343$8320_Y - connect \$1 $not$libresoc.v:157344$8321_Y - connect \$3 $and$libresoc.v:157345$8322_Y - connect \$5 $or$libresoc.v:157346$8323_Y - connect \$7 $not$libresoc.v:157347$8324_Y + connect \$9 $and$libresoc.v:157339$8317_Y + connect \$11 $or$libresoc.v:157340$8318_Y + connect \$13 $not$libresoc.v:157341$8319_Y + connect \$15 $or$libresoc.v:157342$8320_Y + connect \$1 $not$libresoc.v:157343$8321_Y + connect \$3 $and$libresoc.v:157344$8322_Y + connect \$5 $or$libresoc.v:157345$8323_Y + connect \$7 $not$libresoc.v:157346$8324_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157366.1-157424.10" +attribute \src "libresoc.v:157365.1-157423.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.opc_l" attribute \generator "nMigen" module \opc_l$102 - attribute \src "libresoc.v:157367.7-157367.20" + attribute \src "libresoc.v:157366.7-157366.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157412.3-157420.6" + attribute \src "libresoc.v:157411.3-157419.6" wire $0\q_int$next[0:0]$8341 - attribute \src "libresoc.v:157410.3-157411.27" + attribute \src "libresoc.v:157409.3-157410.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157412.3-157420.6" + attribute \src "libresoc.v:157411.3-157419.6" wire $1\q_int$next[0:0]$8342 - attribute \src "libresoc.v:157389.7-157389.19" + attribute \src "libresoc.v:157388.7-157388.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157402.17-157402.96" - wire $and$libresoc.v:157402$8331_Y - attribute \src "libresoc.v:157407.17-157407.96" - wire $and$libresoc.v:157407$8336_Y - attribute \src "libresoc.v:157404.18-157404.93" - wire $not$libresoc.v:157404$8333_Y - attribute \src "libresoc.v:157406.17-157406.92" - wire $not$libresoc.v:157406$8335_Y - attribute \src "libresoc.v:157409.17-157409.92" - wire $not$libresoc.v:157409$8338_Y - attribute \src "libresoc.v:157403.18-157403.98" - wire $or$libresoc.v:157403$8332_Y - attribute \src "libresoc.v:157405.18-157405.99" - wire $or$libresoc.v:157405$8334_Y - attribute \src "libresoc.v:157408.17-157408.97" - wire $or$libresoc.v:157408$8337_Y + attribute \src "libresoc.v:157401.17-157401.96" + wire $and$libresoc.v:157401$8331_Y + attribute \src "libresoc.v:157406.17-157406.96" + wire $and$libresoc.v:157406$8336_Y + attribute \src "libresoc.v:157403.18-157403.93" + wire $not$libresoc.v:157403$8333_Y + attribute \src "libresoc.v:157405.17-157405.92" + wire $not$libresoc.v:157405$8335_Y + attribute \src "libresoc.v:157408.17-157408.92" + wire $not$libresoc.v:157408$8338_Y + attribute \src "libresoc.v:157402.18-157402.98" + wire $or$libresoc.v:157402$8332_Y + attribute \src "libresoc.v:157404.18-157404.99" + wire $or$libresoc.v:157404$8334_Y + attribute \src "libresoc.v:157407.17-157407.97" + wire $or$libresoc.v:157407$8337_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -327212,7 +324022,7 @@ module \opc_l$102 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:157367.7-157367.15" + attribute \src "libresoc.v:157366.7-157366.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -327229,7 +324039,7 @@ module \opc_l$102 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157402$8331 + cell $and $and$libresoc.v:157401$8331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327237,10 +324047,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157402$8331_Y + connect \Y $and$libresoc.v:157401$8331_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157407$8336 + cell $and $and$libresoc.v:157406$8336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327248,34 +324058,34 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157407$8336_Y + connect \Y $and$libresoc.v:157406$8336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157404$8333 + cell $not $not$libresoc.v:157403$8333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157404$8333_Y + connect \Y $not$libresoc.v:157403$8333_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157406$8335 + cell $not $not$libresoc.v:157405$8335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157406$8335_Y + connect \Y $not$libresoc.v:157405$8335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157409$8338 + cell $not $not$libresoc.v:157408$8338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157409$8338_Y + connect \Y $not$libresoc.v:157408$8338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157403$8332 + cell $or $or$libresoc.v:157402$8332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327283,10 +324093,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157403$8332_Y + connect \Y $or$libresoc.v:157402$8332_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157405$8334 + cell $or $or$libresoc.v:157404$8334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327294,10 +324104,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157405$8334_Y + connect \Y $or$libresoc.v:157404$8334_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157408$8337 + cell $or $or$libresoc.v:157407$8337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327305,39 +324115,39 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157408$8337_Y + connect \Y $or$libresoc.v:157407$8337_Y end - attribute \src "libresoc.v:157367.7-157367.20" - process $proc$libresoc.v:157367$8343 + attribute \src "libresoc.v:157366.7-157366.20" + process $proc$libresoc.v:157366$8343 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157389.7-157389.19" - process $proc$libresoc.v:157389$8344 + attribute \src "libresoc.v:157388.7-157388.19" + process $proc$libresoc.v:157388$8344 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157410.3-157411.27" - process $proc$libresoc.v:157410$8339 + attribute \src "libresoc.v:157409.3-157410.27" + process $proc$libresoc.v:157409$8339 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157412.3-157420.6" - process $proc$libresoc.v:157412$8340 + attribute \src "libresoc.v:157411.3-157419.6" + process $proc$libresoc.v:157411$8340 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8341 $1\q_int$next[0:0]$8342 - attribute \src "libresoc.v:157413.5-157413.29" + attribute \src "libresoc.v:157412.5-157412.29" switch \initial - attribute \src "libresoc.v:157413.9-157413.17" + attribute \src "libresoc.v:157412.9-157412.17" case 1'1 case end @@ -327353,49 +324163,49 @@ module \opc_l$102 sync always update \q_int$next $0\q_int$next[0:0]$8341 end - connect \$9 $and$libresoc.v:157402$8331_Y - connect \$11 $or$libresoc.v:157403$8332_Y - connect \$13 $not$libresoc.v:157404$8333_Y - connect \$15 $or$libresoc.v:157405$8334_Y - connect \$1 $not$libresoc.v:157406$8335_Y - connect \$3 $and$libresoc.v:157407$8336_Y - connect \$5 $or$libresoc.v:157408$8337_Y - connect \$7 $not$libresoc.v:157409$8338_Y + connect \$9 $and$libresoc.v:157401$8331_Y + connect \$11 $or$libresoc.v:157402$8332_Y + connect \$13 $not$libresoc.v:157403$8333_Y + connect \$15 $or$libresoc.v:157404$8334_Y + connect \$1 $not$libresoc.v:157405$8335_Y + connect \$3 $and$libresoc.v:157406$8336_Y + connect \$5 $or$libresoc.v:157407$8337_Y + connect \$7 $not$libresoc.v:157408$8338_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157428.1-157486.10" +attribute \src "libresoc.v:157427.1-157485.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.opc_l" attribute \generator "nMigen" module \opc_l$11 - attribute \src "libresoc.v:157429.7-157429.20" + attribute \src "libresoc.v:157428.7-157428.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157474.3-157482.6" + attribute \src "libresoc.v:157473.3-157481.6" wire $0\q_int$next[0:0]$8355 - attribute \src "libresoc.v:157472.3-157473.27" + attribute \src "libresoc.v:157471.3-157472.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157474.3-157482.6" + attribute \src "libresoc.v:157473.3-157481.6" wire $1\q_int$next[0:0]$8356 - attribute \src "libresoc.v:157451.7-157451.19" + attribute \src "libresoc.v:157450.7-157450.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157464.17-157464.96" - wire $and$libresoc.v:157464$8345_Y - attribute \src "libresoc.v:157469.17-157469.96" - wire $and$libresoc.v:157469$8350_Y - attribute \src "libresoc.v:157466.18-157466.93" - wire $not$libresoc.v:157466$8347_Y - attribute \src "libresoc.v:157468.17-157468.92" - wire $not$libresoc.v:157468$8349_Y - attribute \src "libresoc.v:157471.17-157471.92" - wire $not$libresoc.v:157471$8352_Y - attribute \src "libresoc.v:157465.18-157465.98" - wire $or$libresoc.v:157465$8346_Y - attribute \src "libresoc.v:157467.18-157467.99" - wire $or$libresoc.v:157467$8348_Y - attribute \src "libresoc.v:157470.17-157470.97" - wire $or$libresoc.v:157470$8351_Y + attribute \src "libresoc.v:157463.17-157463.96" + wire $and$libresoc.v:157463$8345_Y + attribute \src "libresoc.v:157468.17-157468.96" + wire $and$libresoc.v:157468$8350_Y + attribute \src "libresoc.v:157465.18-157465.93" + wire $not$libresoc.v:157465$8347_Y + attribute \src "libresoc.v:157467.17-157467.92" + wire $not$libresoc.v:157467$8349_Y + attribute \src "libresoc.v:157470.17-157470.92" + wire $not$libresoc.v:157470$8352_Y + attribute \src "libresoc.v:157464.18-157464.98" + wire $or$libresoc.v:157464$8346_Y + attribute \src "libresoc.v:157466.18-157466.99" + wire $or$libresoc.v:157466$8348_Y + attribute \src "libresoc.v:157469.17-157469.97" + wire $or$libresoc.v:157469$8351_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -327416,7 +324226,7 @@ module \opc_l$11 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:157429.7-157429.15" + attribute \src "libresoc.v:157428.7-157428.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -327433,7 +324243,7 @@ module \opc_l$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157464$8345 + cell $and $and$libresoc.v:157463$8345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327441,10 +324251,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157464$8345_Y + connect \Y $and$libresoc.v:157463$8345_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157469$8350 + cell $and $and$libresoc.v:157468$8350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327452,34 +324262,34 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157469$8350_Y + connect \Y $and$libresoc.v:157468$8350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157466$8347 + cell $not $not$libresoc.v:157465$8347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157466$8347_Y + connect \Y $not$libresoc.v:157465$8347_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157468$8349 + cell $not $not$libresoc.v:157467$8349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157468$8349_Y + connect \Y $not$libresoc.v:157467$8349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157471$8352 + cell $not $not$libresoc.v:157470$8352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157471$8352_Y + connect \Y $not$libresoc.v:157470$8352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157465$8346 + cell $or $or$libresoc.v:157464$8346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327487,10 +324297,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157465$8346_Y + connect \Y $or$libresoc.v:157464$8346_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157467$8348 + cell $or $or$libresoc.v:157466$8348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327498,10 +324308,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157467$8348_Y + connect \Y $or$libresoc.v:157466$8348_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157470$8351 + cell $or $or$libresoc.v:157469$8351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327509,39 +324319,39 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157470$8351_Y + connect \Y $or$libresoc.v:157469$8351_Y end - attribute \src "libresoc.v:157429.7-157429.20" - process $proc$libresoc.v:157429$8357 + attribute \src "libresoc.v:157428.7-157428.20" + process $proc$libresoc.v:157428$8357 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157451.7-157451.19" - process $proc$libresoc.v:157451$8358 + attribute \src "libresoc.v:157450.7-157450.19" + process $proc$libresoc.v:157450$8358 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157472.3-157473.27" - process $proc$libresoc.v:157472$8353 + attribute \src "libresoc.v:157471.3-157472.27" + process $proc$libresoc.v:157471$8353 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157474.3-157482.6" - process $proc$libresoc.v:157474$8354 + attribute \src "libresoc.v:157473.3-157481.6" + process $proc$libresoc.v:157473$8354 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8355 $1\q_int$next[0:0]$8356 - attribute \src "libresoc.v:157475.5-157475.29" + attribute \src "libresoc.v:157474.5-157474.29" switch \initial - attribute \src "libresoc.v:157475.9-157475.17" + attribute \src "libresoc.v:157474.9-157474.17" case 1'1 case end @@ -327557,49 +324367,49 @@ module \opc_l$11 sync always update \q_int$next $0\q_int$next[0:0]$8355 end - connect \$9 $and$libresoc.v:157464$8345_Y - connect \$11 $or$libresoc.v:157465$8346_Y - connect \$13 $not$libresoc.v:157466$8347_Y - connect \$15 $or$libresoc.v:157467$8348_Y - connect \$1 $not$libresoc.v:157468$8349_Y - connect \$3 $and$libresoc.v:157469$8350_Y - connect \$5 $or$libresoc.v:157470$8351_Y - connect \$7 $not$libresoc.v:157471$8352_Y + connect \$9 $and$libresoc.v:157463$8345_Y + connect \$11 $or$libresoc.v:157464$8346_Y + connect \$13 $not$libresoc.v:157465$8347_Y + connect \$15 $or$libresoc.v:157466$8348_Y + connect \$1 $not$libresoc.v:157467$8349_Y + connect \$3 $and$libresoc.v:157468$8350_Y + connect \$5 $or$libresoc.v:157469$8351_Y + connect \$7 $not$libresoc.v:157470$8352_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157490.1-157548.10" +attribute \src "libresoc.v:157489.1-157547.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l" attribute \generator "nMigen" module \opc_l$120 - attribute \src "libresoc.v:157491.7-157491.20" + attribute \src "libresoc.v:157490.7-157490.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157536.3-157544.6" + attribute \src "libresoc.v:157535.3-157543.6" wire $0\q_int$next[0:0]$8369 - attribute \src "libresoc.v:157534.3-157535.27" + attribute \src "libresoc.v:157533.3-157534.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157536.3-157544.6" + attribute \src "libresoc.v:157535.3-157543.6" wire $1\q_int$next[0:0]$8370 - attribute \src "libresoc.v:157513.7-157513.19" + attribute \src "libresoc.v:157512.7-157512.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157526.17-157526.96" - wire $and$libresoc.v:157526$8359_Y - attribute \src "libresoc.v:157531.17-157531.96" - wire $and$libresoc.v:157531$8364_Y - attribute \src "libresoc.v:157528.18-157528.93" - wire $not$libresoc.v:157528$8361_Y - attribute \src "libresoc.v:157530.17-157530.92" - wire $not$libresoc.v:157530$8363_Y - attribute \src "libresoc.v:157533.17-157533.92" - wire $not$libresoc.v:157533$8366_Y - attribute \src "libresoc.v:157527.18-157527.98" - wire $or$libresoc.v:157527$8360_Y - attribute \src "libresoc.v:157529.18-157529.99" - wire $or$libresoc.v:157529$8362_Y - attribute \src "libresoc.v:157532.17-157532.97" - wire $or$libresoc.v:157532$8365_Y + attribute \src "libresoc.v:157525.17-157525.96" + wire $and$libresoc.v:157525$8359_Y + attribute \src "libresoc.v:157530.17-157530.96" + wire $and$libresoc.v:157530$8364_Y + attribute \src "libresoc.v:157527.18-157527.93" + wire $not$libresoc.v:157527$8361_Y + attribute \src "libresoc.v:157529.17-157529.92" + wire $not$libresoc.v:157529$8363_Y + attribute \src "libresoc.v:157532.17-157532.92" + wire $not$libresoc.v:157532$8366_Y + attribute \src "libresoc.v:157526.18-157526.98" + wire $or$libresoc.v:157526$8360_Y + attribute \src "libresoc.v:157528.18-157528.99" + wire $or$libresoc.v:157528$8362_Y + attribute \src "libresoc.v:157531.17-157531.97" + wire $or$libresoc.v:157531$8365_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -327620,7 +324430,7 @@ module \opc_l$120 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:157491.7-157491.15" + attribute \src "libresoc.v:157490.7-157490.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -327637,7 +324447,7 @@ module \opc_l$120 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157526$8359 + cell $and $and$libresoc.v:157525$8359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327645,10 +324455,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157526$8359_Y + connect \Y $and$libresoc.v:157525$8359_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157531$8364 + cell $and $and$libresoc.v:157530$8364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327656,34 +324466,34 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157531$8364_Y + connect \Y $and$libresoc.v:157530$8364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157528$8361 + cell $not $not$libresoc.v:157527$8361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157528$8361_Y + connect \Y $not$libresoc.v:157527$8361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157530$8363 + cell $not $not$libresoc.v:157529$8363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157530$8363_Y + connect \Y $not$libresoc.v:157529$8363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157533$8366 + cell $not $not$libresoc.v:157532$8366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157533$8366_Y + connect \Y $not$libresoc.v:157532$8366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157527$8360 + cell $or $or$libresoc.v:157526$8360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327691,10 +324501,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157527$8360_Y + connect \Y $or$libresoc.v:157526$8360_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157529$8362 + cell $or $or$libresoc.v:157528$8362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327702,10 +324512,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157529$8362_Y + connect \Y $or$libresoc.v:157528$8362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157532$8365 + cell $or $or$libresoc.v:157531$8365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327713,39 +324523,39 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157532$8365_Y + connect \Y $or$libresoc.v:157531$8365_Y end - attribute \src "libresoc.v:157491.7-157491.20" - process $proc$libresoc.v:157491$8371 + attribute \src "libresoc.v:157490.7-157490.20" + process $proc$libresoc.v:157490$8371 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157513.7-157513.19" - process $proc$libresoc.v:157513$8372 + attribute \src "libresoc.v:157512.7-157512.19" + process $proc$libresoc.v:157512$8372 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157534.3-157535.27" - process $proc$libresoc.v:157534$8367 + attribute \src "libresoc.v:157533.3-157534.27" + process $proc$libresoc.v:157533$8367 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157536.3-157544.6" - process $proc$libresoc.v:157536$8368 + attribute \src "libresoc.v:157535.3-157543.6" + process $proc$libresoc.v:157535$8368 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8369 $1\q_int$next[0:0]$8370 - attribute \src "libresoc.v:157537.5-157537.29" + attribute \src "libresoc.v:157536.5-157536.29" switch \initial - attribute \src "libresoc.v:157537.9-157537.17" + attribute \src "libresoc.v:157536.9-157536.17" case 1'1 case end @@ -327761,49 +324571,49 @@ module \opc_l$120 sync always update \q_int$next $0\q_int$next[0:0]$8369 end - connect \$9 $and$libresoc.v:157526$8359_Y - connect \$11 $or$libresoc.v:157527$8360_Y - connect \$13 $not$libresoc.v:157528$8361_Y - connect \$15 $or$libresoc.v:157529$8362_Y - connect \$1 $not$libresoc.v:157530$8363_Y - connect \$3 $and$libresoc.v:157531$8364_Y - connect \$5 $or$libresoc.v:157532$8365_Y - connect \$7 $not$libresoc.v:157533$8366_Y + connect \$9 $and$libresoc.v:157525$8359_Y + connect \$11 $or$libresoc.v:157526$8360_Y + connect \$13 $not$libresoc.v:157527$8361_Y + connect \$15 $or$libresoc.v:157528$8362_Y + connect \$1 $not$libresoc.v:157529$8363_Y + connect \$3 $and$libresoc.v:157530$8364_Y + connect \$5 $or$libresoc.v:157531$8365_Y + connect \$7 $not$libresoc.v:157532$8366_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157552.1-157610.10" +attribute \src "libresoc.v:157551.1-157609.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.opc_l" attribute \generator "nMigen" module \opc_l$126 - attribute \src "libresoc.v:157553.7-157553.20" + attribute \src "libresoc.v:157552.7-157552.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157598.3-157606.6" + attribute \src "libresoc.v:157597.3-157605.6" wire $0\q_int$next[0:0]$8383 - attribute \src "libresoc.v:157596.3-157597.27" + attribute \src "libresoc.v:157595.3-157596.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157598.3-157606.6" + attribute \src "libresoc.v:157597.3-157605.6" wire $1\q_int$next[0:0]$8384 - attribute \src "libresoc.v:157575.7-157575.19" + attribute \src "libresoc.v:157574.7-157574.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157588.17-157588.96" - wire $and$libresoc.v:157588$8373_Y - attribute \src "libresoc.v:157593.17-157593.96" - wire $and$libresoc.v:157593$8378_Y - attribute \src "libresoc.v:157590.18-157590.93" - wire $not$libresoc.v:157590$8375_Y - attribute \src "libresoc.v:157592.17-157592.92" - wire $not$libresoc.v:157592$8377_Y - attribute \src "libresoc.v:157595.17-157595.92" - wire $not$libresoc.v:157595$8380_Y - attribute \src "libresoc.v:157589.18-157589.98" - wire $or$libresoc.v:157589$8374_Y - attribute \src "libresoc.v:157591.18-157591.99" - wire $or$libresoc.v:157591$8376_Y - attribute \src "libresoc.v:157594.17-157594.97" - wire $or$libresoc.v:157594$8379_Y + attribute \src "libresoc.v:157587.17-157587.96" + wire $and$libresoc.v:157587$8373_Y + attribute \src "libresoc.v:157592.17-157592.96" + wire $and$libresoc.v:157592$8378_Y + attribute \src "libresoc.v:157589.18-157589.93" + wire $not$libresoc.v:157589$8375_Y + attribute \src "libresoc.v:157591.17-157591.92" + wire $not$libresoc.v:157591$8377_Y + attribute \src "libresoc.v:157594.17-157594.92" + wire $not$libresoc.v:157594$8380_Y + attribute \src "libresoc.v:157588.18-157588.98" + wire $or$libresoc.v:157588$8374_Y + attribute \src "libresoc.v:157590.18-157590.99" + wire $or$libresoc.v:157590$8376_Y + attribute \src "libresoc.v:157593.17-157593.97" + wire $or$libresoc.v:157593$8379_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -327824,7 +324634,7 @@ module \opc_l$126 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:157553.7-157553.15" + attribute \src "libresoc.v:157552.7-157552.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -327841,7 +324651,7 @@ module \opc_l$126 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157588$8373 + cell $and $and$libresoc.v:157587$8373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327849,10 +324659,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157588$8373_Y + connect \Y $and$libresoc.v:157587$8373_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157593$8378 + cell $and $and$libresoc.v:157592$8378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327860,34 +324670,34 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157593$8378_Y + connect \Y $and$libresoc.v:157592$8378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157590$8375 + cell $not $not$libresoc.v:157589$8375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157590$8375_Y + connect \Y $not$libresoc.v:157589$8375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157592$8377 + cell $not $not$libresoc.v:157591$8377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157592$8377_Y + connect \Y $not$libresoc.v:157591$8377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157595$8380 + cell $not $not$libresoc.v:157594$8380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157595$8380_Y + connect \Y $not$libresoc.v:157594$8380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157589$8374 + cell $or $or$libresoc.v:157588$8374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327895,10 +324705,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157589$8374_Y + connect \Y $or$libresoc.v:157588$8374_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157591$8376 + cell $or $or$libresoc.v:157590$8376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327906,10 +324716,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157591$8376_Y + connect \Y $or$libresoc.v:157590$8376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157594$8379 + cell $or $or$libresoc.v:157593$8379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327917,39 +324727,39 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157594$8379_Y + connect \Y $or$libresoc.v:157593$8379_Y end - attribute \src "libresoc.v:157553.7-157553.20" - process $proc$libresoc.v:157553$8385 + attribute \src "libresoc.v:157552.7-157552.20" + process $proc$libresoc.v:157552$8385 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157575.7-157575.19" - process $proc$libresoc.v:157575$8386 + attribute \src "libresoc.v:157574.7-157574.19" + process $proc$libresoc.v:157574$8386 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157596.3-157597.27" - process $proc$libresoc.v:157596$8381 + attribute \src "libresoc.v:157595.3-157596.27" + process $proc$libresoc.v:157595$8381 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157598.3-157606.6" - process $proc$libresoc.v:157598$8382 + attribute \src "libresoc.v:157597.3-157605.6" + process $proc$libresoc.v:157597$8382 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8383 $1\q_int$next[0:0]$8384 - attribute \src "libresoc.v:157599.5-157599.29" + attribute \src "libresoc.v:157598.5-157598.29" switch \initial - attribute \src "libresoc.v:157599.9-157599.17" + attribute \src "libresoc.v:157598.9-157598.17" case 1'1 case end @@ -327965,49 +324775,49 @@ module \opc_l$126 sync always update \q_int$next $0\q_int$next[0:0]$8383 end - connect \$9 $and$libresoc.v:157588$8373_Y - connect \$11 $or$libresoc.v:157589$8374_Y - connect \$13 $not$libresoc.v:157590$8375_Y - connect \$15 $or$libresoc.v:157591$8376_Y - connect \$1 $not$libresoc.v:157592$8377_Y - connect \$3 $and$libresoc.v:157593$8378_Y - connect \$5 $or$libresoc.v:157594$8379_Y - connect \$7 $not$libresoc.v:157595$8380_Y + connect \$9 $and$libresoc.v:157587$8373_Y + connect \$11 $or$libresoc.v:157588$8374_Y + connect \$13 $not$libresoc.v:157589$8375_Y + connect \$15 $or$libresoc.v:157590$8376_Y + connect \$1 $not$libresoc.v:157591$8377_Y + connect \$3 $and$libresoc.v:157592$8378_Y + connect \$5 $or$libresoc.v:157593$8379_Y + connect \$7 $not$libresoc.v:157594$8380_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157614.1-157672.10" +attribute \src "libresoc.v:157613.1-157671.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.opc_l" attribute \generator "nMigen" module \opc_l$24 - attribute \src "libresoc.v:157615.7-157615.20" + attribute \src "libresoc.v:157614.7-157614.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157660.3-157668.6" + attribute \src "libresoc.v:157659.3-157667.6" wire $0\q_int$next[0:0]$8397 - attribute \src "libresoc.v:157658.3-157659.27" + attribute \src "libresoc.v:157657.3-157658.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157660.3-157668.6" + attribute \src "libresoc.v:157659.3-157667.6" wire $1\q_int$next[0:0]$8398 - attribute \src "libresoc.v:157637.7-157637.19" + attribute \src "libresoc.v:157636.7-157636.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157650.17-157650.96" - wire $and$libresoc.v:157650$8387_Y - attribute \src "libresoc.v:157655.17-157655.96" - wire $and$libresoc.v:157655$8392_Y - attribute \src "libresoc.v:157652.18-157652.93" - wire $not$libresoc.v:157652$8389_Y - attribute \src "libresoc.v:157654.17-157654.92" - wire $not$libresoc.v:157654$8391_Y - attribute \src "libresoc.v:157657.17-157657.92" - wire $not$libresoc.v:157657$8394_Y - attribute \src "libresoc.v:157651.18-157651.98" - wire $or$libresoc.v:157651$8388_Y - attribute \src "libresoc.v:157653.18-157653.99" - wire $or$libresoc.v:157653$8390_Y - attribute \src "libresoc.v:157656.17-157656.97" - wire $or$libresoc.v:157656$8393_Y + attribute \src "libresoc.v:157649.17-157649.96" + wire $and$libresoc.v:157649$8387_Y + attribute \src "libresoc.v:157654.17-157654.96" + wire $and$libresoc.v:157654$8392_Y + attribute \src "libresoc.v:157651.18-157651.93" + wire $not$libresoc.v:157651$8389_Y + attribute \src "libresoc.v:157653.17-157653.92" + wire $not$libresoc.v:157653$8391_Y + attribute \src "libresoc.v:157656.17-157656.92" + wire $not$libresoc.v:157656$8394_Y + attribute \src "libresoc.v:157650.18-157650.98" + wire $or$libresoc.v:157650$8388_Y + attribute \src "libresoc.v:157652.18-157652.99" + wire $or$libresoc.v:157652$8390_Y + attribute \src "libresoc.v:157655.17-157655.97" + wire $or$libresoc.v:157655$8393_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -328028,7 +324838,7 @@ module \opc_l$24 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:157615.7-157615.15" + attribute \src "libresoc.v:157614.7-157614.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -328045,7 +324855,7 @@ module \opc_l$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157650$8387 + cell $and $and$libresoc.v:157649$8387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328053,10 +324863,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157650$8387_Y + connect \Y $and$libresoc.v:157649$8387_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157655$8392 + cell $and $and$libresoc.v:157654$8392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328064,34 +324874,34 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157655$8392_Y + connect \Y $and$libresoc.v:157654$8392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157652$8389 + cell $not $not$libresoc.v:157651$8389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157652$8389_Y + connect \Y $not$libresoc.v:157651$8389_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157654$8391 + cell $not $not$libresoc.v:157653$8391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157654$8391_Y + connect \Y $not$libresoc.v:157653$8391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157657$8394 + cell $not $not$libresoc.v:157656$8394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157657$8394_Y + connect \Y $not$libresoc.v:157656$8394_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157651$8388 + cell $or $or$libresoc.v:157650$8388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328099,10 +324909,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157651$8388_Y + connect \Y $or$libresoc.v:157650$8388_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157653$8390 + cell $or $or$libresoc.v:157652$8390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328110,10 +324920,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157653$8390_Y + connect \Y $or$libresoc.v:157652$8390_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157656$8393 + cell $or $or$libresoc.v:157655$8393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328121,39 +324931,39 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157656$8393_Y + connect \Y $or$libresoc.v:157655$8393_Y end - attribute \src "libresoc.v:157615.7-157615.20" - process $proc$libresoc.v:157615$8399 + attribute \src "libresoc.v:157614.7-157614.20" + process $proc$libresoc.v:157614$8399 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157637.7-157637.19" - process $proc$libresoc.v:157637$8400 + attribute \src "libresoc.v:157636.7-157636.19" + process $proc$libresoc.v:157636$8400 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157658.3-157659.27" - process $proc$libresoc.v:157658$8395 + attribute \src "libresoc.v:157657.3-157658.27" + process $proc$libresoc.v:157657$8395 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157660.3-157668.6" - process $proc$libresoc.v:157660$8396 + attribute \src "libresoc.v:157659.3-157667.6" + process $proc$libresoc.v:157659$8396 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8397 $1\q_int$next[0:0]$8398 - attribute \src "libresoc.v:157661.5-157661.29" + attribute \src "libresoc.v:157660.5-157660.29" switch \initial - attribute \src "libresoc.v:157661.9-157661.17" + attribute \src "libresoc.v:157660.9-157660.17" case 1'1 case end @@ -328169,49 +324979,49 @@ module \opc_l$24 sync always update \q_int$next $0\q_int$next[0:0]$8397 end - connect \$9 $and$libresoc.v:157650$8387_Y - connect \$11 $or$libresoc.v:157651$8388_Y - connect \$13 $not$libresoc.v:157652$8389_Y - connect \$15 $or$libresoc.v:157653$8390_Y - connect \$1 $not$libresoc.v:157654$8391_Y - connect \$3 $and$libresoc.v:157655$8392_Y - connect \$5 $or$libresoc.v:157656$8393_Y - connect \$7 $not$libresoc.v:157657$8394_Y + connect \$9 $and$libresoc.v:157649$8387_Y + connect \$11 $or$libresoc.v:157650$8388_Y + connect \$13 $not$libresoc.v:157651$8389_Y + connect \$15 $or$libresoc.v:157652$8390_Y + connect \$1 $not$libresoc.v:157653$8391_Y + connect \$3 $and$libresoc.v:157654$8392_Y + connect \$5 $or$libresoc.v:157655$8393_Y + connect \$7 $not$libresoc.v:157656$8394_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157676.1-157734.10" +attribute \src "libresoc.v:157675.1-157733.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.opc_l" attribute \generator "nMigen" module \opc_l$40 - attribute \src "libresoc.v:157677.7-157677.20" + attribute \src "libresoc.v:157676.7-157676.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157722.3-157730.6" + attribute \src "libresoc.v:157721.3-157729.6" wire $0\q_int$next[0:0]$8411 - attribute \src "libresoc.v:157720.3-157721.27" + attribute \src "libresoc.v:157719.3-157720.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157722.3-157730.6" + attribute \src "libresoc.v:157721.3-157729.6" wire $1\q_int$next[0:0]$8412 - attribute \src "libresoc.v:157699.7-157699.19" + attribute \src "libresoc.v:157698.7-157698.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157712.17-157712.96" - wire $and$libresoc.v:157712$8401_Y - attribute \src "libresoc.v:157717.17-157717.96" - wire $and$libresoc.v:157717$8406_Y - attribute \src "libresoc.v:157714.18-157714.93" - wire $not$libresoc.v:157714$8403_Y - attribute \src "libresoc.v:157716.17-157716.92" - wire $not$libresoc.v:157716$8405_Y - attribute \src "libresoc.v:157719.17-157719.92" - wire $not$libresoc.v:157719$8408_Y - attribute \src "libresoc.v:157713.18-157713.98" - wire $or$libresoc.v:157713$8402_Y - attribute \src "libresoc.v:157715.18-157715.99" - wire $or$libresoc.v:157715$8404_Y - attribute \src "libresoc.v:157718.17-157718.97" - wire $or$libresoc.v:157718$8407_Y + attribute \src "libresoc.v:157711.17-157711.96" + wire $and$libresoc.v:157711$8401_Y + attribute \src "libresoc.v:157716.17-157716.96" + wire $and$libresoc.v:157716$8406_Y + attribute \src "libresoc.v:157713.18-157713.93" + wire $not$libresoc.v:157713$8403_Y + attribute \src "libresoc.v:157715.17-157715.92" + wire $not$libresoc.v:157715$8405_Y + attribute \src "libresoc.v:157718.17-157718.92" + wire $not$libresoc.v:157718$8408_Y + attribute \src "libresoc.v:157712.18-157712.98" + wire $or$libresoc.v:157712$8402_Y + attribute \src "libresoc.v:157714.18-157714.99" + wire $or$libresoc.v:157714$8404_Y + attribute \src "libresoc.v:157717.17-157717.97" + wire $or$libresoc.v:157717$8407_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -328232,7 +325042,7 @@ module \opc_l$40 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:157677.7-157677.15" + attribute \src "libresoc.v:157676.7-157676.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -328249,7 +325059,7 @@ module \opc_l$40 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157712$8401 + cell $and $and$libresoc.v:157711$8401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328257,10 +325067,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157712$8401_Y + connect \Y $and$libresoc.v:157711$8401_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157717$8406 + cell $and $and$libresoc.v:157716$8406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328268,34 +325078,34 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157717$8406_Y + connect \Y $and$libresoc.v:157716$8406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157714$8403 + cell $not $not$libresoc.v:157713$8403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157714$8403_Y + connect \Y $not$libresoc.v:157713$8403_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157716$8405 + cell $not $not$libresoc.v:157715$8405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157716$8405_Y + connect \Y $not$libresoc.v:157715$8405_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157719$8408 + cell $not $not$libresoc.v:157718$8408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157719$8408_Y + connect \Y $not$libresoc.v:157718$8408_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157713$8402 + cell $or $or$libresoc.v:157712$8402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328303,10 +325113,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157713$8402_Y + connect \Y $or$libresoc.v:157712$8402_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157715$8404 + cell $or $or$libresoc.v:157714$8404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328314,10 +325124,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157715$8404_Y + connect \Y $or$libresoc.v:157714$8404_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157718$8407 + cell $or $or$libresoc.v:157717$8407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328325,39 +325135,39 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157718$8407_Y + connect \Y $or$libresoc.v:157717$8407_Y end - attribute \src "libresoc.v:157677.7-157677.20" - process $proc$libresoc.v:157677$8413 + attribute \src "libresoc.v:157676.7-157676.20" + process $proc$libresoc.v:157676$8413 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157699.7-157699.19" - process $proc$libresoc.v:157699$8414 + attribute \src "libresoc.v:157698.7-157698.19" + process $proc$libresoc.v:157698$8414 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157720.3-157721.27" - process $proc$libresoc.v:157720$8409 + attribute \src "libresoc.v:157719.3-157720.27" + process $proc$libresoc.v:157719$8409 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157722.3-157730.6" - process $proc$libresoc.v:157722$8410 + attribute \src "libresoc.v:157721.3-157729.6" + process $proc$libresoc.v:157721$8410 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8411 $1\q_int$next[0:0]$8412 - attribute \src "libresoc.v:157723.5-157723.29" + attribute \src "libresoc.v:157722.5-157722.29" switch \initial - attribute \src "libresoc.v:157723.9-157723.17" + attribute \src "libresoc.v:157722.9-157722.17" case 1'1 case end @@ -328373,49 +325183,49 @@ module \opc_l$40 sync always update \q_int$next $0\q_int$next[0:0]$8411 end - connect \$9 $and$libresoc.v:157712$8401_Y - connect \$11 $or$libresoc.v:157713$8402_Y - connect \$13 $not$libresoc.v:157714$8403_Y - connect \$15 $or$libresoc.v:157715$8404_Y - connect \$1 $not$libresoc.v:157716$8405_Y - connect \$3 $and$libresoc.v:157717$8406_Y - connect \$5 $or$libresoc.v:157718$8407_Y - connect \$7 $not$libresoc.v:157719$8408_Y + connect \$9 $and$libresoc.v:157711$8401_Y + connect \$11 $or$libresoc.v:157712$8402_Y + connect \$13 $not$libresoc.v:157713$8403_Y + connect \$15 $or$libresoc.v:157714$8404_Y + connect \$1 $not$libresoc.v:157715$8405_Y + connect \$3 $and$libresoc.v:157716$8406_Y + connect \$5 $or$libresoc.v:157717$8407_Y + connect \$7 $not$libresoc.v:157718$8408_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157738.1-157796.10" +attribute \src "libresoc.v:157737.1-157795.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l" attribute \generator "nMigen" module \opc_l$56 - attribute \src "libresoc.v:157739.7-157739.20" + attribute \src "libresoc.v:157738.7-157738.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157784.3-157792.6" + attribute \src "libresoc.v:157783.3-157791.6" wire $0\q_int$next[0:0]$8425 - attribute \src "libresoc.v:157782.3-157783.27" + attribute \src "libresoc.v:157781.3-157782.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157784.3-157792.6" + attribute \src "libresoc.v:157783.3-157791.6" wire $1\q_int$next[0:0]$8426 - attribute \src "libresoc.v:157761.7-157761.19" + attribute \src "libresoc.v:157760.7-157760.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157774.17-157774.96" - wire $and$libresoc.v:157774$8415_Y - attribute \src "libresoc.v:157779.17-157779.96" - wire $and$libresoc.v:157779$8420_Y - attribute \src "libresoc.v:157776.18-157776.93" - wire $not$libresoc.v:157776$8417_Y - attribute \src "libresoc.v:157778.17-157778.92" - wire $not$libresoc.v:157778$8419_Y - attribute \src "libresoc.v:157781.17-157781.92" - wire $not$libresoc.v:157781$8422_Y - attribute \src "libresoc.v:157775.18-157775.98" - wire $or$libresoc.v:157775$8416_Y - attribute \src "libresoc.v:157777.18-157777.99" - wire $or$libresoc.v:157777$8418_Y - attribute \src "libresoc.v:157780.17-157780.97" - wire $or$libresoc.v:157780$8421_Y + attribute \src "libresoc.v:157773.17-157773.96" + wire $and$libresoc.v:157773$8415_Y + attribute \src "libresoc.v:157778.17-157778.96" + wire $and$libresoc.v:157778$8420_Y + attribute \src "libresoc.v:157775.18-157775.93" + wire $not$libresoc.v:157775$8417_Y + attribute \src "libresoc.v:157777.17-157777.92" + wire $not$libresoc.v:157777$8419_Y + attribute \src "libresoc.v:157780.17-157780.92" + wire $not$libresoc.v:157780$8422_Y + attribute \src "libresoc.v:157774.18-157774.98" + wire $or$libresoc.v:157774$8416_Y + attribute \src "libresoc.v:157776.18-157776.99" + wire $or$libresoc.v:157776$8418_Y + attribute \src "libresoc.v:157779.17-157779.97" + wire $or$libresoc.v:157779$8421_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -328436,7 +325246,7 @@ module \opc_l$56 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:157739.7-157739.15" + attribute \src "libresoc.v:157738.7-157738.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -328453,7 +325263,7 @@ module \opc_l$56 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157774$8415 + cell $and $and$libresoc.v:157773$8415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328461,10 +325271,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157774$8415_Y + connect \Y $and$libresoc.v:157773$8415_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157779$8420 + cell $and $and$libresoc.v:157778$8420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328472,34 +325282,34 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157779$8420_Y + connect \Y $and$libresoc.v:157778$8420_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157776$8417 + cell $not $not$libresoc.v:157775$8417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157776$8417_Y + connect \Y $not$libresoc.v:157775$8417_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157778$8419 + cell $not $not$libresoc.v:157777$8419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157778$8419_Y + connect \Y $not$libresoc.v:157777$8419_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157781$8422 + cell $not $not$libresoc.v:157780$8422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157781$8422_Y + connect \Y $not$libresoc.v:157780$8422_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157775$8416 + cell $or $or$libresoc.v:157774$8416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328507,10 +325317,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157775$8416_Y + connect \Y $or$libresoc.v:157774$8416_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157777$8418 + cell $or $or$libresoc.v:157776$8418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328518,10 +325328,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157777$8418_Y + connect \Y $or$libresoc.v:157776$8418_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157780$8421 + cell $or $or$libresoc.v:157779$8421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328529,39 +325339,39 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157780$8421_Y + connect \Y $or$libresoc.v:157779$8421_Y end - attribute \src "libresoc.v:157739.7-157739.20" - process $proc$libresoc.v:157739$8427 + attribute \src "libresoc.v:157738.7-157738.20" + process $proc$libresoc.v:157738$8427 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157761.7-157761.19" - process $proc$libresoc.v:157761$8428 + attribute \src "libresoc.v:157760.7-157760.19" + process $proc$libresoc.v:157760$8428 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157782.3-157783.27" - process $proc$libresoc.v:157782$8423 + attribute \src "libresoc.v:157781.3-157782.27" + process $proc$libresoc.v:157781$8423 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157784.3-157792.6" - process $proc$libresoc.v:157784$8424 + attribute \src "libresoc.v:157783.3-157791.6" + process $proc$libresoc.v:157783$8424 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8425 $1\q_int$next[0:0]$8426 - attribute \src "libresoc.v:157785.5-157785.29" + attribute \src "libresoc.v:157784.5-157784.29" switch \initial - attribute \src "libresoc.v:157785.9-157785.17" + attribute \src "libresoc.v:157784.9-157784.17" case 1'1 case end @@ -328577,49 +325387,49 @@ module \opc_l$56 sync always update \q_int$next $0\q_int$next[0:0]$8425 end - connect \$9 $and$libresoc.v:157774$8415_Y - connect \$11 $or$libresoc.v:157775$8416_Y - connect \$13 $not$libresoc.v:157776$8417_Y - connect \$15 $or$libresoc.v:157777$8418_Y - connect \$1 $not$libresoc.v:157778$8419_Y - connect \$3 $and$libresoc.v:157779$8420_Y - connect \$5 $or$libresoc.v:157780$8421_Y - connect \$7 $not$libresoc.v:157781$8422_Y + connect \$9 $and$libresoc.v:157773$8415_Y + connect \$11 $or$libresoc.v:157774$8416_Y + connect \$13 $not$libresoc.v:157775$8417_Y + connect \$15 $or$libresoc.v:157776$8418_Y + connect \$1 $not$libresoc.v:157777$8419_Y + connect \$3 $and$libresoc.v:157778$8420_Y + connect \$5 $or$libresoc.v:157779$8421_Y + connect \$7 $not$libresoc.v:157780$8422_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157800.1-157858.10" +attribute \src "libresoc.v:157799.1-157857.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.opc_l" attribute \generator "nMigen" module \opc_l$68 - attribute \src "libresoc.v:157801.7-157801.20" + attribute \src "libresoc.v:157800.7-157800.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157846.3-157854.6" + attribute \src "libresoc.v:157845.3-157853.6" wire $0\q_int$next[0:0]$8439 - attribute \src "libresoc.v:157844.3-157845.27" + attribute \src "libresoc.v:157843.3-157844.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157846.3-157854.6" + attribute \src "libresoc.v:157845.3-157853.6" wire $1\q_int$next[0:0]$8440 - attribute \src "libresoc.v:157823.7-157823.19" + attribute \src "libresoc.v:157822.7-157822.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157836.17-157836.96" - wire $and$libresoc.v:157836$8429_Y - attribute \src "libresoc.v:157841.17-157841.96" - wire $and$libresoc.v:157841$8434_Y - attribute \src "libresoc.v:157838.18-157838.93" - wire $not$libresoc.v:157838$8431_Y - attribute \src "libresoc.v:157840.17-157840.92" - wire $not$libresoc.v:157840$8433_Y - attribute \src "libresoc.v:157843.17-157843.92" - wire $not$libresoc.v:157843$8436_Y - attribute \src "libresoc.v:157837.18-157837.98" - wire $or$libresoc.v:157837$8430_Y - attribute \src "libresoc.v:157839.18-157839.99" - wire $or$libresoc.v:157839$8432_Y - attribute \src "libresoc.v:157842.17-157842.97" - wire $or$libresoc.v:157842$8435_Y + attribute \src "libresoc.v:157835.17-157835.96" + wire $and$libresoc.v:157835$8429_Y + attribute \src "libresoc.v:157840.17-157840.96" + wire $and$libresoc.v:157840$8434_Y + attribute \src "libresoc.v:157837.18-157837.93" + wire $not$libresoc.v:157837$8431_Y + attribute \src "libresoc.v:157839.17-157839.92" + wire $not$libresoc.v:157839$8433_Y + attribute \src "libresoc.v:157842.17-157842.92" + wire $not$libresoc.v:157842$8436_Y + attribute \src "libresoc.v:157836.18-157836.98" + wire $or$libresoc.v:157836$8430_Y + attribute \src "libresoc.v:157838.18-157838.99" + wire $or$libresoc.v:157838$8432_Y + attribute \src "libresoc.v:157841.17-157841.97" + wire $or$libresoc.v:157841$8435_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -328640,7 +325450,7 @@ module \opc_l$68 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:157801.7-157801.15" + attribute \src "libresoc.v:157800.7-157800.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -328657,7 +325467,7 @@ module \opc_l$68 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157836$8429 + cell $and $and$libresoc.v:157835$8429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328665,10 +325475,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157836$8429_Y + connect \Y $and$libresoc.v:157835$8429_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157841$8434 + cell $and $and$libresoc.v:157840$8434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328676,34 +325486,34 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157841$8434_Y + connect \Y $and$libresoc.v:157840$8434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157838$8431 + cell $not $not$libresoc.v:157837$8431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157838$8431_Y + connect \Y $not$libresoc.v:157837$8431_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157840$8433 + cell $not $not$libresoc.v:157839$8433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157840$8433_Y + connect \Y $not$libresoc.v:157839$8433_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157843$8436 + cell $not $not$libresoc.v:157842$8436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157843$8436_Y + connect \Y $not$libresoc.v:157842$8436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157837$8430 + cell $or $or$libresoc.v:157836$8430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328711,10 +325521,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157837$8430_Y + connect \Y $or$libresoc.v:157836$8430_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157839$8432 + cell $or $or$libresoc.v:157838$8432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328722,10 +325532,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157839$8432_Y + connect \Y $or$libresoc.v:157838$8432_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157842$8435 + cell $or $or$libresoc.v:157841$8435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328733,39 +325543,39 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157842$8435_Y + connect \Y $or$libresoc.v:157841$8435_Y end - attribute \src "libresoc.v:157801.7-157801.20" - process $proc$libresoc.v:157801$8441 + attribute \src "libresoc.v:157800.7-157800.20" + process $proc$libresoc.v:157800$8441 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157823.7-157823.19" - process $proc$libresoc.v:157823$8442 + attribute \src "libresoc.v:157822.7-157822.19" + process $proc$libresoc.v:157822$8442 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157844.3-157845.27" - process $proc$libresoc.v:157844$8437 + attribute \src "libresoc.v:157843.3-157844.27" + process $proc$libresoc.v:157843$8437 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157846.3-157854.6" - process $proc$libresoc.v:157846$8438 + attribute \src "libresoc.v:157845.3-157853.6" + process $proc$libresoc.v:157845$8438 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8439 $1\q_int$next[0:0]$8440 - attribute \src "libresoc.v:157847.5-157847.29" + attribute \src "libresoc.v:157846.5-157846.29" switch \initial - attribute \src "libresoc.v:157847.9-157847.17" + attribute \src "libresoc.v:157846.9-157846.17" case 1'1 case end @@ -328781,49 +325591,49 @@ module \opc_l$68 sync always update \q_int$next $0\q_int$next[0:0]$8439 end - connect \$9 $and$libresoc.v:157836$8429_Y - connect \$11 $or$libresoc.v:157837$8430_Y - connect \$13 $not$libresoc.v:157838$8431_Y - connect \$15 $or$libresoc.v:157839$8432_Y - connect \$1 $not$libresoc.v:157840$8433_Y - connect \$3 $and$libresoc.v:157841$8434_Y - connect \$5 $or$libresoc.v:157842$8435_Y - connect \$7 $not$libresoc.v:157843$8436_Y + connect \$9 $and$libresoc.v:157835$8429_Y + connect \$11 $or$libresoc.v:157836$8430_Y + connect \$13 $not$libresoc.v:157837$8431_Y + connect \$15 $or$libresoc.v:157838$8432_Y + connect \$1 $not$libresoc.v:157839$8433_Y + connect \$3 $and$libresoc.v:157840$8434_Y + connect \$5 $or$libresoc.v:157841$8435_Y + connect \$7 $not$libresoc.v:157842$8436_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157862.1-157920.10" +attribute \src "libresoc.v:157861.1-157919.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.opc_l" attribute \generator "nMigen" module \opc_l$85 - attribute \src "libresoc.v:157863.7-157863.20" + attribute \src "libresoc.v:157862.7-157862.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157908.3-157916.6" + attribute \src "libresoc.v:157907.3-157915.6" wire $0\q_int$next[0:0]$8453 - attribute \src "libresoc.v:157906.3-157907.27" + attribute \src "libresoc.v:157905.3-157906.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157908.3-157916.6" + attribute \src "libresoc.v:157907.3-157915.6" wire $1\q_int$next[0:0]$8454 - attribute \src "libresoc.v:157885.7-157885.19" + attribute \src "libresoc.v:157884.7-157884.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157898.17-157898.96" - wire $and$libresoc.v:157898$8443_Y - attribute \src "libresoc.v:157903.17-157903.96" - wire $and$libresoc.v:157903$8448_Y - attribute \src "libresoc.v:157900.18-157900.93" - wire $not$libresoc.v:157900$8445_Y - attribute \src "libresoc.v:157902.17-157902.92" - wire $not$libresoc.v:157902$8447_Y - attribute \src "libresoc.v:157905.17-157905.92" - wire $not$libresoc.v:157905$8450_Y - attribute \src "libresoc.v:157899.18-157899.98" - wire $or$libresoc.v:157899$8444_Y - attribute \src "libresoc.v:157901.18-157901.99" - wire $or$libresoc.v:157901$8446_Y - attribute \src "libresoc.v:157904.17-157904.97" - wire $or$libresoc.v:157904$8449_Y + attribute \src "libresoc.v:157897.17-157897.96" + wire $and$libresoc.v:157897$8443_Y + attribute \src "libresoc.v:157902.17-157902.96" + wire $and$libresoc.v:157902$8448_Y + attribute \src "libresoc.v:157899.18-157899.93" + wire $not$libresoc.v:157899$8445_Y + attribute \src "libresoc.v:157901.17-157901.92" + wire $not$libresoc.v:157901$8447_Y + attribute \src "libresoc.v:157904.17-157904.92" + wire $not$libresoc.v:157904$8450_Y + attribute \src "libresoc.v:157898.18-157898.98" + wire $or$libresoc.v:157898$8444_Y + attribute \src "libresoc.v:157900.18-157900.99" + wire $or$libresoc.v:157900$8446_Y + attribute \src "libresoc.v:157903.17-157903.97" + wire $or$libresoc.v:157903$8449_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -328844,7 +325654,7 @@ module \opc_l$85 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:157863.7-157863.15" + attribute \src "libresoc.v:157862.7-157862.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -328861,7 +325671,7 @@ module \opc_l$85 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157898$8443 + cell $and $and$libresoc.v:157897$8443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328869,10 +325679,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157898$8443_Y + connect \Y $and$libresoc.v:157897$8443_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157903$8448 + cell $and $and$libresoc.v:157902$8448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328880,34 +325690,34 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157903$8448_Y + connect \Y $and$libresoc.v:157902$8448_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157900$8445 + cell $not $not$libresoc.v:157899$8445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157900$8445_Y + connect \Y $not$libresoc.v:157899$8445_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157902$8447 + cell $not $not$libresoc.v:157901$8447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157902$8447_Y + connect \Y $not$libresoc.v:157901$8447_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157905$8450 + cell $not $not$libresoc.v:157904$8450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157905$8450_Y + connect \Y $not$libresoc.v:157904$8450_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157899$8444 + cell $or $or$libresoc.v:157898$8444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328915,10 +325725,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157899$8444_Y + connect \Y $or$libresoc.v:157898$8444_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157901$8446 + cell $or $or$libresoc.v:157900$8446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328926,10 +325736,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157901$8446_Y + connect \Y $or$libresoc.v:157900$8446_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157904$8449 + cell $or $or$libresoc.v:157903$8449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328937,39 +325747,39 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157904$8449_Y + connect \Y $or$libresoc.v:157903$8449_Y end - attribute \src "libresoc.v:157863.7-157863.20" - process $proc$libresoc.v:157863$8455 + attribute \src "libresoc.v:157862.7-157862.20" + process $proc$libresoc.v:157862$8455 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157885.7-157885.19" - process $proc$libresoc.v:157885$8456 + attribute \src "libresoc.v:157884.7-157884.19" + process $proc$libresoc.v:157884$8456 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157906.3-157907.27" - process $proc$libresoc.v:157906$8451 + attribute \src "libresoc.v:157905.3-157906.27" + process $proc$libresoc.v:157905$8451 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157908.3-157916.6" - process $proc$libresoc.v:157908$8452 + attribute \src "libresoc.v:157907.3-157915.6" + process $proc$libresoc.v:157907$8452 assign { } { } assign { } { } assign $0\q_int$next[0:0]$8453 $1\q_int$next[0:0]$8454 - attribute \src "libresoc.v:157909.5-157909.29" + attribute \src "libresoc.v:157908.5-157908.29" switch \initial - attribute \src "libresoc.v:157909.9-157909.17" + attribute \src "libresoc.v:157908.9-157908.17" case 1'1 case end @@ -328985,83 +325795,83 @@ module \opc_l$85 sync always update \q_int$next $0\q_int$next[0:0]$8453 end - connect \$9 $and$libresoc.v:157898$8443_Y - connect \$11 $or$libresoc.v:157899$8444_Y - connect \$13 $not$libresoc.v:157900$8445_Y - connect \$15 $or$libresoc.v:157901$8446_Y - connect \$1 $not$libresoc.v:157902$8447_Y - connect \$3 $and$libresoc.v:157903$8448_Y - connect \$5 $or$libresoc.v:157904$8449_Y - connect \$7 $not$libresoc.v:157905$8450_Y + connect \$9 $and$libresoc.v:157897$8443_Y + connect \$11 $or$libresoc.v:157898$8444_Y + connect \$13 $not$libresoc.v:157899$8445_Y + connect \$15 $or$libresoc.v:157900$8446_Y + connect \$1 $not$libresoc.v:157901$8447_Y + connect \$3 $and$libresoc.v:157902$8448_Y + connect \$5 $or$libresoc.v:157903$8449_Y + connect \$7 $not$libresoc.v:157904$8450_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157924.1-158382.10" +attribute \src "libresoc.v:157923.1-158381.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.output" attribute \generator "nMigen" module \output - attribute \src "libresoc.v:158301.3-158312.6" + attribute \src "libresoc.v:158300.3-158311.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:157925.7-157925.20" + attribute \src "libresoc.v:157924.7-157924.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158313.3-158324.6" + attribute \src "libresoc.v:158312.3-158323.6" wire width 65 $0\o$28[64:0]$8475 - attribute \src "libresoc.v:158289.3-158300.6" + attribute \src "libresoc.v:158288.3-158299.6" wire $0\so[0:0] - attribute \src "libresoc.v:158345.3-158354.6" + attribute \src "libresoc.v:158344.3-158353.6" wire width 2 $0\xer_ov$24[1:0]$8482 - attribute \src "libresoc.v:158355.3-158364.6" + attribute \src "libresoc.v:158354.3-158363.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:158325.3-158334.6" + attribute \src "libresoc.v:158324.3-158333.6" wire $0\xer_so$25[0:0]$8478 - attribute \src "libresoc.v:158335.3-158344.6" + attribute \src "libresoc.v:158334.3-158343.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:158301.3-158312.6" + attribute \src "libresoc.v:158300.3-158311.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:158313.3-158324.6" + attribute \src "libresoc.v:158312.3-158323.6" wire width 65 $1\o$28[64:0]$8476 - attribute \src "libresoc.v:158289.3-158300.6" + attribute \src "libresoc.v:158288.3-158299.6" wire $1\so[0:0] - attribute \src "libresoc.v:158345.3-158354.6" + attribute \src "libresoc.v:158344.3-158353.6" wire width 2 $1\xer_ov$24[1:0]$8483 - attribute \src "libresoc.v:158355.3-158364.6" + attribute \src "libresoc.v:158354.3-158363.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:158325.3-158334.6" + attribute \src "libresoc.v:158324.3-158333.6" wire $1\xer_so$25[0:0]$8479 - attribute \src "libresoc.v:158335.3-158344.6" + attribute \src "libresoc.v:158334.3-158343.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:158276.18-158276.128" - wire $and$libresoc.v:158276$8457_Y - attribute \src "libresoc.v:158284.18-158284.112" - wire $and$libresoc.v:158284$8467_Y - attribute \src "libresoc.v:158287.18-158287.125" - wire $and$libresoc.v:158287$8470_Y + attribute \src "libresoc.v:158275.18-158275.128" + wire $and$libresoc.v:158275$8457_Y + attribute \src "libresoc.v:158283.18-158283.112" + wire $and$libresoc.v:158283$8467_Y + attribute \src "libresoc.v:158286.18-158286.125" + wire $and$libresoc.v:158286$8470_Y + attribute \src "libresoc.v:158279.18-158279.123" + wire $eq$libresoc.v:158279$8463_Y attribute \src "libresoc.v:158280.18-158280.123" - wire $eq$libresoc.v:158280$8463_Y - attribute \src "libresoc.v:158281.18-158281.123" - wire $eq$libresoc.v:158281$8464_Y - attribute \src "libresoc.v:158278.18-158278.103" - wire width 65 $extend$libresoc.v:158278$8459_Y - attribute \src "libresoc.v:158279.18-158279.101" - wire width 65 $extend$libresoc.v:158279$8461_Y - attribute \src "libresoc.v:158277.18-158277.100" - wire width 64 $not$libresoc.v:158277$8458_Y - attribute \src "libresoc.v:158283.18-158283.107" - wire $not$libresoc.v:158283$8466_Y - attribute \src "libresoc.v:158286.18-158286.107" - wire $not$libresoc.v:158286$8469_Y - attribute \src "libresoc.v:158285.18-158285.115" - wire $or$libresoc.v:158285$8468_Y - attribute \src "libresoc.v:158288.18-158288.112" - wire $or$libresoc.v:158288$8471_Y - attribute \src "libresoc.v:158278.18-158278.103" - wire width 65 $pos$libresoc.v:158278$8460_Y - attribute \src "libresoc.v:158279.18-158279.101" - wire width 65 $pos$libresoc.v:158279$8462_Y - attribute \src "libresoc.v:158282.18-158282.105" - wire $reduce_or$libresoc.v:158282$8465_Y + wire $eq$libresoc.v:158280$8464_Y + attribute \src "libresoc.v:158277.18-158277.103" + wire width 65 $extend$libresoc.v:158277$8459_Y + attribute \src "libresoc.v:158278.18-158278.101" + wire width 65 $extend$libresoc.v:158278$8461_Y + attribute \src "libresoc.v:158276.18-158276.100" + wire width 64 $not$libresoc.v:158276$8458_Y + attribute \src "libresoc.v:158282.18-158282.107" + wire $not$libresoc.v:158282$8466_Y + attribute \src "libresoc.v:158285.18-158285.107" + wire $not$libresoc.v:158285$8469_Y + attribute \src "libresoc.v:158284.18-158284.115" + wire $or$libresoc.v:158284$8468_Y + attribute \src "libresoc.v:158287.18-158287.112" + wire $or$libresoc.v:158287$8471_Y + attribute \src "libresoc.v:158277.18-158277.103" + wire width 65 $pos$libresoc.v:158277$8460_Y + attribute \src "libresoc.v:158278.18-158278.101" + wire width 65 $pos$libresoc.v:158278$8462_Y + attribute \src "libresoc.v:158281.18-158281.105" + wire $reduce_or$libresoc.v:158281$8465_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -329356,7 +326166,7 @@ module \output wire width 4 output 46 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 47 \cr_a_ok - attribute \src "libresoc.v:157925.7-157925.15" + attribute \src "libresoc.v:157924.7-157924.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -329411,7 +326221,7 @@ module \output attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 53 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:158276$8457 + cell $and $and$libresoc.v:158275$8457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329419,10 +326229,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:158276$8457_Y + connect \Y $and$libresoc.v:158275$8457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:158284$8467 + cell $and $and$libresoc.v:158283$8467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329430,10 +326240,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$41 - connect \Y $and$libresoc.v:158284$8467_Y + connect \Y $and$libresoc.v:158283$8467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:158287$8470 + cell $and $and$libresoc.v:158286$8470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329441,10 +326251,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:158287$8470_Y + connect \Y $and$libresoc.v:158286$8470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:158280$8463 + cell $eq $eq$libresoc.v:158279$8463 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -329452,10 +326262,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:158280$8463_Y + connect \Y $eq$libresoc.v:158279$8463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:158281$8464 + cell $eq $eq$libresoc.v:158280$8464 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -329463,50 +326273,50 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:158281$8464_Y + connect \Y $eq$libresoc.v:158280$8464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:158278$8459 + cell $pos $extend$libresoc.v:158277$8459 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$30 - connect \Y $extend$libresoc.v:158278$8459_Y + connect \Y $extend$libresoc.v:158277$8459_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:158279$8461 + cell $pos $extend$libresoc.v:158278$8461 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:158279$8461_Y + connect \Y $extend$libresoc.v:158278$8461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:158277$8458 + cell $not $not$libresoc.v:158276$8458 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:158277$8458_Y + connect \Y $not$libresoc.v:158276$8458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:158283$8466 + cell $not $not$libresoc.v:158282$8466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:158283$8466_Y + connect \Y $not$libresoc.v:158282$8466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:158286$8469 + cell $not $not$libresoc.v:158285$8469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:158286$8469_Y + connect \Y $not$libresoc.v:158285$8469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:158285$8468 + cell $or $or$libresoc.v:158284$8468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329514,10 +326324,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:158285$8468_Y + connect \Y $or$libresoc.v:158284$8468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:158288$8471 + cell $or $or$libresoc.v:158287$8471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329525,47 +326335,47 @@ module \output parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:158288$8471_Y + connect \Y $or$libresoc.v:158287$8471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:158278$8460 + cell $pos $pos$libresoc.v:158277$8460 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158278$8459_Y - connect \Y $pos$libresoc.v:158278$8460_Y + connect \A $extend$libresoc.v:158277$8459_Y + connect \Y $pos$libresoc.v:158277$8460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:158279$8462 + cell $pos $pos$libresoc.v:158278$8462 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158279$8461_Y - connect \Y $pos$libresoc.v:158279$8462_Y + connect \A $extend$libresoc.v:158278$8461_Y + connect \Y $pos$libresoc.v:158278$8462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:158282$8465 + cell $reduce_or $reduce_or$libresoc.v:158281$8465 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:158282$8465_Y + connect \Y $reduce_or$libresoc.v:158281$8465_Y end - attribute \src "libresoc.v:157925.7-157925.20" - process $proc$libresoc.v:157925$8485 + attribute \src "libresoc.v:157924.7-157924.20" + process $proc$libresoc.v:157924$8485 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158289.3-158300.6" - process $proc$libresoc.v:158289$8472 + attribute \src "libresoc.v:158288.3-158299.6" + process $proc$libresoc.v:158288$8472 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:158290.5-158290.29" + attribute \src "libresoc.v:158289.5-158289.29" switch \initial - attribute \src "libresoc.v:158290.9-158290.17" + attribute \src "libresoc.v:158289.9-158289.17" case 1'1 case end @@ -329583,13 +326393,13 @@ module \output sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:158301.3-158312.6" - process $proc$libresoc.v:158301$8473 + attribute \src "libresoc.v:158300.3-158311.6" + process $proc$libresoc.v:158300$8473 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:158302.5-158302.29" + attribute \src "libresoc.v:158301.5-158301.29" switch \initial - attribute \src "libresoc.v:158302.9-158302.17" + attribute \src "libresoc.v:158301.9-158301.17" case 1'1 case end @@ -329607,13 +326417,13 @@ module \output sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:158313.3-158324.6" - process $proc$libresoc.v:158313$8474 + attribute \src "libresoc.v:158312.3-158323.6" + process $proc$libresoc.v:158312$8474 assign { } { } assign $0\o$28[64:0]$8475 $1\o$28[64:0]$8476 - attribute \src "libresoc.v:158314.5-158314.29" + attribute \src "libresoc.v:158313.5-158313.29" switch \initial - attribute \src "libresoc.v:158314.9-158314.17" + attribute \src "libresoc.v:158313.9-158313.17" case 1'1 case end @@ -329631,14 +326441,14 @@ module \output sync always update \o$28 $0\o$28[64:0]$8475 end - attribute \src "libresoc.v:158325.3-158334.6" - process $proc$libresoc.v:158325$8477 + attribute \src "libresoc.v:158324.3-158333.6" + process $proc$libresoc.v:158324$8477 assign { } { } assign { } { } assign $0\xer_so$25[0:0]$8478 $1\xer_so$25[0:0]$8479 - attribute \src "libresoc.v:158326.5-158326.29" + attribute \src "libresoc.v:158325.5-158325.29" switch \initial - attribute \src "libresoc.v:158326.9-158326.17" + attribute \src "libresoc.v:158325.9-158325.17" case 1'1 case end @@ -329654,14 +326464,14 @@ module \output sync always update \xer_so$25 $0\xer_so$25[0:0]$8478 end - attribute \src "libresoc.v:158335.3-158344.6" - process $proc$libresoc.v:158335$8480 + attribute \src "libresoc.v:158334.3-158343.6" + process $proc$libresoc.v:158334$8480 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:158336.5-158336.29" + attribute \src "libresoc.v:158335.5-158335.29" switch \initial - attribute \src "libresoc.v:158336.9-158336.17" + attribute \src "libresoc.v:158335.9-158335.17" case 1'1 case end @@ -329677,14 +326487,14 @@ module \output sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:158345.3-158354.6" - process $proc$libresoc.v:158345$8481 + attribute \src "libresoc.v:158344.3-158353.6" + process $proc$libresoc.v:158344$8481 assign { } { } assign { } { } assign $0\xer_ov$24[1:0]$8482 $1\xer_ov$24[1:0]$8483 - attribute \src "libresoc.v:158346.5-158346.29" + attribute \src "libresoc.v:158345.5-158345.29" switch \initial - attribute \src "libresoc.v:158346.9-158346.17" + attribute \src "libresoc.v:158345.9-158345.17" case 1'1 case end @@ -329700,14 +326510,14 @@ module \output sync always update \xer_ov$24 $0\xer_ov$24[1:0]$8482 end - attribute \src "libresoc.v:158355.3-158364.6" - process $proc$libresoc.v:158355$8484 + attribute \src "libresoc.v:158354.3-158363.6" + process $proc$libresoc.v:158354$8484 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:158356.5-158356.29" + attribute \src "libresoc.v:158355.5-158355.29" switch \initial - attribute \src "libresoc.v:158356.9-158356.17" + attribute \src "libresoc.v:158355.9-158355.17" case 1'1 case end @@ -329723,19 +326533,19 @@ module \output sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$26 $and$libresoc.v:158276$8457_Y - connect \$30 $not$libresoc.v:158277$8458_Y - connect \$29 $pos$libresoc.v:158278$8460_Y - connect \$33 $pos$libresoc.v:158279$8462_Y - connect \$35 $eq$libresoc.v:158280$8463_Y - connect \$37 $eq$libresoc.v:158281$8464_Y - connect \$39 $reduce_or$libresoc.v:158282$8465_Y - connect \$41 $not$libresoc.v:158283$8466_Y - connect \$43 $and$libresoc.v:158284$8467_Y - connect \$45 $or$libresoc.v:158285$8468_Y - connect \$47 $not$libresoc.v:158286$8469_Y - connect \$50 $and$libresoc.v:158287$8470_Y - connect \$52 $or$libresoc.v:158288$8471_Y + connect \$26 $and$libresoc.v:158275$8457_Y + connect \$30 $not$libresoc.v:158276$8458_Y + connect \$29 $pos$libresoc.v:158277$8460_Y + connect \$33 $pos$libresoc.v:158278$8462_Y + connect \$35 $eq$libresoc.v:158279$8463_Y + connect \$37 $eq$libresoc.v:158280$8464_Y + connect \$39 $reduce_or$libresoc.v:158281$8465_Y + connect \$41 $not$libresoc.v:158282$8466_Y + connect \$43 $and$libresoc.v:158283$8467_Y + connect \$45 $or$libresoc.v:158284$8468_Y + connect \$47 $not$libresoc.v:158285$8469_Y + connect \$50 $and$libresoc.v:158286$8470_Y + connect \$52 $or$libresoc.v:158287$8471_Y connect \oe$49 \$50 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid @@ -329754,61 +326564,61 @@ module \output connect \target \o$28 [63:0] connect \oe \$26 end -attribute \src "libresoc.v:158386.1-158787.10" +attribute \src "libresoc.v:158385.1-158786.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output" attribute \generator "nMigen" module \output$100 - attribute \src "libresoc.v:158719.3-158730.6" + attribute \src "libresoc.v:158718.3-158729.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:158387.7-158387.20" + attribute \src "libresoc.v:158386.7-158386.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158707.3-158718.6" + attribute \src "libresoc.v:158706.3-158717.6" wire $0\so[0:0] - attribute \src "libresoc.v:158751.3-158760.6" + attribute \src "libresoc.v:158750.3-158759.6" wire width 2 $0\xer_ov$17[1:0]$8505 - attribute \src "libresoc.v:158761.3-158770.6" + attribute \src "libresoc.v:158760.3-158769.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:158731.3-158740.6" + attribute \src "libresoc.v:158730.3-158739.6" wire $0\xer_so$18[0:0]$8501 - attribute \src "libresoc.v:158741.3-158750.6" + attribute \src "libresoc.v:158740.3-158749.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:158719.3-158730.6" + attribute \src "libresoc.v:158718.3-158729.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:158707.3-158718.6" + attribute \src "libresoc.v:158706.3-158717.6" wire $1\so[0:0] - attribute \src "libresoc.v:158751.3-158760.6" + attribute \src "libresoc.v:158750.3-158759.6" wire width 2 $1\xer_ov$17[1:0]$8506 - attribute \src "libresoc.v:158761.3-158770.6" + attribute \src "libresoc.v:158760.3-158769.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:158731.3-158740.6" + attribute \src "libresoc.v:158730.3-158739.6" wire $1\xer_so$18[0:0]$8502 - attribute \src "libresoc.v:158741.3-158750.6" + attribute \src "libresoc.v:158740.3-158749.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:158696.18-158696.128" - wire $and$libresoc.v:158696$8486_Y - attribute \src "libresoc.v:158702.18-158702.112" - wire $and$libresoc.v:158702$8493_Y - attribute \src "libresoc.v:158705.18-158705.125" - wire $and$libresoc.v:158705$8496_Y + attribute \src "libresoc.v:158695.18-158695.128" + wire $and$libresoc.v:158695$8486_Y + attribute \src "libresoc.v:158701.18-158701.112" + wire $and$libresoc.v:158701$8493_Y + attribute \src "libresoc.v:158704.18-158704.125" + wire $and$libresoc.v:158704$8496_Y + attribute \src "libresoc.v:158697.18-158697.123" + wire $eq$libresoc.v:158697$8489_Y attribute \src "libresoc.v:158698.18-158698.123" - wire $eq$libresoc.v:158698$8489_Y - attribute \src "libresoc.v:158699.18-158699.123" - wire $eq$libresoc.v:158699$8490_Y - attribute \src "libresoc.v:158697.18-158697.101" - wire width 65 $extend$libresoc.v:158697$8487_Y - attribute \src "libresoc.v:158701.18-158701.107" - wire $not$libresoc.v:158701$8492_Y - attribute \src "libresoc.v:158704.18-158704.107" - wire $not$libresoc.v:158704$8495_Y - attribute \src "libresoc.v:158703.18-158703.115" - wire $or$libresoc.v:158703$8494_Y - attribute \src "libresoc.v:158706.18-158706.112" - wire $or$libresoc.v:158706$8497_Y - attribute \src "libresoc.v:158697.18-158697.101" - wire width 65 $pos$libresoc.v:158697$8488_Y - attribute \src "libresoc.v:158700.18-158700.105" - wire $reduce_or$libresoc.v:158700$8491_Y + wire $eq$libresoc.v:158698$8490_Y + attribute \src "libresoc.v:158696.18-158696.101" + wire width 65 $extend$libresoc.v:158696$8487_Y + attribute \src "libresoc.v:158700.18-158700.107" + wire $not$libresoc.v:158700$8492_Y + attribute \src "libresoc.v:158703.18-158703.107" + wire $not$libresoc.v:158703$8495_Y + attribute \src "libresoc.v:158702.18-158702.115" + wire $or$libresoc.v:158702$8494_Y + attribute \src "libresoc.v:158705.18-158705.112" + wire $or$libresoc.v:158705$8497_Y + attribute \src "libresoc.v:158696.18-158696.101" + wire width 65 $pos$libresoc.v:158696$8488_Y + attribute \src "libresoc.v:158699.18-158699.105" + wire $reduce_or$libresoc.v:158699$8491_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -329839,7 +326649,7 @@ module \output$100 wire width 4 output 33 \cr_a$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 34 \cr_a_ok - attribute \src "libresoc.v:158387.7-158387.15" + attribute \src "libresoc.v:158386.7-158386.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -330116,7 +326926,7 @@ module \output$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 38 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:158696$8486 + cell $and $and$libresoc.v:158695$8486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330124,10 +326934,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:158696$8486_Y + connect \Y $and$libresoc.v:158695$8486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:158702$8493 + cell $and $and$libresoc.v:158701$8493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330135,10 +326945,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$30 - connect \Y $and$libresoc.v:158702$8493_Y + connect \Y $and$libresoc.v:158701$8493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:158705$8496 + cell $and $and$libresoc.v:158704$8496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330146,10 +326956,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:158705$8496_Y + connect \Y $and$libresoc.v:158704$8496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:158698$8489 + cell $eq $eq$libresoc.v:158697$8489 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -330157,10 +326967,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:158698$8489_Y + connect \Y $eq$libresoc.v:158697$8489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:158699$8490 + cell $eq $eq$libresoc.v:158698$8490 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -330168,34 +326978,34 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:158699$8490_Y + connect \Y $eq$libresoc.v:158698$8490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:158697$8487 + cell $pos $extend$libresoc.v:158696$8487 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:158697$8487_Y + connect \Y $extend$libresoc.v:158696$8487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:158701$8492 + cell $not $not$libresoc.v:158700$8492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:158701$8492_Y + connect \Y $not$libresoc.v:158700$8492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:158704$8495 + cell $not $not$libresoc.v:158703$8495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:158704$8495_Y + connect \Y $not$libresoc.v:158703$8495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:158703$8494 + cell $or $or$libresoc.v:158702$8494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330203,10 +327013,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:158703$8494_Y + connect \Y $or$libresoc.v:158702$8494_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:158706$8497 + cell $or $or$libresoc.v:158705$8497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330214,39 +327024,39 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:158706$8497_Y + connect \Y $or$libresoc.v:158705$8497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:158697$8488 + cell $pos $pos$libresoc.v:158696$8488 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158697$8487_Y - connect \Y $pos$libresoc.v:158697$8488_Y + connect \A $extend$libresoc.v:158696$8487_Y + connect \Y $pos$libresoc.v:158696$8488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:158700$8491 + cell $reduce_or $reduce_or$libresoc.v:158699$8491 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:158700$8491_Y + connect \Y $reduce_or$libresoc.v:158699$8491_Y end - attribute \src "libresoc.v:158387.7-158387.20" - process $proc$libresoc.v:158387$8508 + attribute \src "libresoc.v:158386.7-158386.20" + process $proc$libresoc.v:158386$8508 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158707.3-158718.6" - process $proc$libresoc.v:158707$8498 + attribute \src "libresoc.v:158706.3-158717.6" + process $proc$libresoc.v:158706$8498 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:158708.5-158708.29" + attribute \src "libresoc.v:158707.5-158707.29" switch \initial - attribute \src "libresoc.v:158708.9-158708.17" + attribute \src "libresoc.v:158707.9-158707.17" case 1'1 case end @@ -330264,13 +327074,13 @@ module \output$100 sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:158719.3-158730.6" - process $proc$libresoc.v:158719$8499 + attribute \src "libresoc.v:158718.3-158729.6" + process $proc$libresoc.v:158718$8499 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:158720.5-158720.29" + attribute \src "libresoc.v:158719.5-158719.29" switch \initial - attribute \src "libresoc.v:158720.9-158720.17" + attribute \src "libresoc.v:158719.9-158719.17" case 1'1 case end @@ -330288,14 +327098,14 @@ module \output$100 sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:158731.3-158740.6" - process $proc$libresoc.v:158731$8500 + attribute \src "libresoc.v:158730.3-158739.6" + process $proc$libresoc.v:158730$8500 assign { } { } assign { } { } assign $0\xer_so$18[0:0]$8501 $1\xer_so$18[0:0]$8502 - attribute \src "libresoc.v:158732.5-158732.29" + attribute \src "libresoc.v:158731.5-158731.29" switch \initial - attribute \src "libresoc.v:158732.9-158732.17" + attribute \src "libresoc.v:158731.9-158731.17" case 1'1 case end @@ -330311,14 +327121,14 @@ module \output$100 sync always update \xer_so$18 $0\xer_so$18[0:0]$8501 end - attribute \src "libresoc.v:158741.3-158750.6" - process $proc$libresoc.v:158741$8503 + attribute \src "libresoc.v:158740.3-158749.6" + process $proc$libresoc.v:158740$8503 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:158742.5-158742.29" + attribute \src "libresoc.v:158741.5-158741.29" switch \initial - attribute \src "libresoc.v:158742.9-158742.17" + attribute \src "libresoc.v:158741.9-158741.17" case 1'1 case end @@ -330334,14 +327144,14 @@ module \output$100 sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:158751.3-158760.6" - process $proc$libresoc.v:158751$8504 + attribute \src "libresoc.v:158750.3-158759.6" + process $proc$libresoc.v:158750$8504 assign { } { } assign { } { } assign $0\xer_ov$17[1:0]$8505 $1\xer_ov$17[1:0]$8506 - attribute \src "libresoc.v:158752.5-158752.29" + attribute \src "libresoc.v:158751.5-158751.29" switch \initial - attribute \src "libresoc.v:158752.9-158752.17" + attribute \src "libresoc.v:158751.9-158751.17" case 1'1 case end @@ -330357,14 +327167,14 @@ module \output$100 sync always update \xer_ov$17 $0\xer_ov$17[1:0]$8505 end - attribute \src "libresoc.v:158761.3-158770.6" - process $proc$libresoc.v:158761$8507 + attribute \src "libresoc.v:158760.3-158769.6" + process $proc$libresoc.v:158760$8507 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:158762.5-158762.29" + attribute \src "libresoc.v:158761.5-158761.29" switch \initial - attribute \src "libresoc.v:158762.9-158762.17" + attribute \src "libresoc.v:158761.9-158761.17" case 1'1 case end @@ -330380,17 +327190,17 @@ module \output$100 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$19 $and$libresoc.v:158696$8486_Y - connect \$22 $pos$libresoc.v:158697$8488_Y - connect \$24 $eq$libresoc.v:158698$8489_Y - connect \$26 $eq$libresoc.v:158699$8490_Y - connect \$28 $reduce_or$libresoc.v:158700$8491_Y - connect \$30 $not$libresoc.v:158701$8492_Y - connect \$32 $and$libresoc.v:158702$8493_Y - connect \$34 $or$libresoc.v:158703$8494_Y - connect \$36 $not$libresoc.v:158704$8495_Y - connect \$39 $and$libresoc.v:158705$8496_Y - connect \$41 $or$libresoc.v:158706$8497_Y + connect \$19 $and$libresoc.v:158695$8486_Y + connect \$22 $pos$libresoc.v:158696$8488_Y + connect \$24 $eq$libresoc.v:158697$8489_Y + connect \$26 $eq$libresoc.v:158698$8490_Y + connect \$28 $reduce_or$libresoc.v:158699$8491_Y + connect \$30 $not$libresoc.v:158700$8492_Y + connect \$32 $and$libresoc.v:158701$8493_Y + connect \$34 $or$libresoc.v:158702$8494_Y + connect \$36 $not$libresoc.v:158703$8495_Y + connect \$39 $and$libresoc.v:158704$8496_Y + connect \$41 $or$libresoc.v:158705$8497_Y connect \oe$38 \$39 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid @@ -330408,35 +327218,35 @@ module \output$100 connect \o$21 \$22 connect \oe \$19 end -attribute \src "libresoc.v:158791.1-159145.10" +attribute \src "libresoc.v:158790.1-159144.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" attribute \generator "nMigen" module \output$118 - attribute \src "libresoc.v:159117.3-159128.6" + attribute \src "libresoc.v:159116.3-159127.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:158792.7-158792.20" + attribute \src "libresoc.v:158791.7-158791.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159117.3-159128.6" + attribute \src "libresoc.v:159116.3-159127.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:159114.18-159114.112" - wire $and$libresoc.v:159114$8515_Y + attribute \src "libresoc.v:159113.18-159113.112" + wire $and$libresoc.v:159113$8515_Y + attribute \src "libresoc.v:159109.18-159109.122" + wire $eq$libresoc.v:159109$8511_Y attribute \src "libresoc.v:159110.18-159110.122" - wire $eq$libresoc.v:159110$8511_Y - attribute \src "libresoc.v:159111.18-159111.122" - wire $eq$libresoc.v:159111$8512_Y - attribute \src "libresoc.v:159109.18-159109.101" - wire width 65 $extend$libresoc.v:159109$8509_Y - attribute \src "libresoc.v:159113.18-159113.107" - wire $not$libresoc.v:159113$8514_Y - attribute \src "libresoc.v:159116.18-159116.107" - wire $not$libresoc.v:159116$8517_Y - attribute \src "libresoc.v:159115.18-159115.115" - wire $or$libresoc.v:159115$8516_Y - attribute \src "libresoc.v:159109.18-159109.101" - wire width 65 $pos$libresoc.v:159109$8510_Y - attribute \src "libresoc.v:159112.18-159112.105" - wire $reduce_or$libresoc.v:159112$8513_Y + wire $eq$libresoc.v:159110$8512_Y + attribute \src "libresoc.v:159108.18-159108.101" + wire width 65 $extend$libresoc.v:159108$8509_Y + attribute \src "libresoc.v:159112.18-159112.107" + wire $not$libresoc.v:159112$8514_Y + attribute \src "libresoc.v:159115.18-159115.107" + wire $not$libresoc.v:159115$8517_Y + attribute \src "libresoc.v:159114.18-159114.115" + wire $or$libresoc.v:159114$8516_Y + attribute \src "libresoc.v:159108.18-159108.101" + wire width 65 $pos$libresoc.v:159108$8510_Y + attribute \src "libresoc.v:159111.18-159111.105" + wire $reduce_or$libresoc.v:159111$8513_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" @@ -330461,7 +327271,7 @@ module \output$118 wire width 4 output 43 \cr_a$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 44 \cr_a_ok - attribute \src "libresoc.v:158792.7-158792.15" + attribute \src "libresoc.v:158791.7-158791.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -330756,7 +327566,7 @@ module \output$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:159114$8515 + cell $and $and$libresoc.v:159113$8515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330764,10 +327574,10 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$32 - connect \Y $and$libresoc.v:159114$8515_Y + connect \Y $and$libresoc.v:159113$8515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:159110$8511 + cell $eq $eq$libresoc.v:159109$8511 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -330775,10 +327585,10 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:159110$8511_Y + connect \Y $eq$libresoc.v:159109$8511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:159111$8512 + cell $eq $eq$libresoc.v:159110$8512 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -330786,34 +327596,34 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:159111$8512_Y + connect \Y $eq$libresoc.v:159110$8512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:159109$8509 + cell $pos $extend$libresoc.v:159108$8509 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:159109$8509_Y + connect \Y $extend$libresoc.v:159108$8509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:159113$8514 + cell $not $not$libresoc.v:159112$8514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:159113$8514_Y + connect \Y $not$libresoc.v:159112$8514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:159116$8517 + cell $not $not$libresoc.v:159115$8517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:159116$8517_Y + connect \Y $not$libresoc.v:159115$8517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:159115$8516 + cell $or $or$libresoc.v:159114$8516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330821,39 +327631,39 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:159115$8516_Y + connect \Y $or$libresoc.v:159114$8516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:159109$8510 + cell $pos $pos$libresoc.v:159108$8510 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159109$8509_Y - connect \Y $pos$libresoc.v:159109$8510_Y + connect \A $extend$libresoc.v:159108$8509_Y + connect \Y $pos$libresoc.v:159108$8510_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:159112$8513 + cell $reduce_or $reduce_or$libresoc.v:159111$8513 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:159112$8513_Y + connect \Y $reduce_or$libresoc.v:159111$8513_Y end - attribute \src "libresoc.v:158792.7-158792.20" - process $proc$libresoc.v:158792$8519 + attribute \src "libresoc.v:158791.7-158791.20" + process $proc$libresoc.v:158791$8519 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:159117.3-159128.6" - process $proc$libresoc.v:159117$8518 + attribute \src "libresoc.v:159116.3-159127.6" + process $proc$libresoc.v:159116$8518 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:159118.5-159118.29" + attribute \src "libresoc.v:159117.5-159117.29" switch \initial - attribute \src "libresoc.v:159118.9-159118.17" + attribute \src "libresoc.v:159117.9-159117.17" case 1'1 case end @@ -330871,14 +327681,14 @@ module \output$118 sync always update \cr0 $0\cr0[3:0] end - connect \$24 $pos$libresoc.v:159109$8510_Y - connect \$26 $eq$libresoc.v:159110$8511_Y - connect \$28 $eq$libresoc.v:159111$8512_Y - connect \$30 $reduce_or$libresoc.v:159112$8513_Y - connect \$32 $not$libresoc.v:159113$8514_Y - connect \$34 $and$libresoc.v:159114$8515_Y - connect \$36 $or$libresoc.v:159115$8516_Y - connect \$38 $not$libresoc.v:159116$8517_Y + connect \$24 $pos$libresoc.v:159108$8510_Y + connect \$26 $eq$libresoc.v:159109$8511_Y + connect \$28 $eq$libresoc.v:159110$8512_Y + connect \$30 $reduce_or$libresoc.v:159111$8513_Y + connect \$32 $not$libresoc.v:159112$8514_Y + connect \$34 $and$libresoc.v:159113$8515_Y + connect \$36 $or$libresoc.v:159114$8516_Y + connect \$38 $not$libresoc.v:159115$8517_Y connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \sr_op__write_cr0 @@ -330896,45 +327706,45 @@ module \output$118 connect \target \o$23 [63:0] connect \o$23 \$24 end -attribute \src "libresoc.v:159149.1-159516.10" +attribute \src "libresoc.v:159148.1-159515.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output" attribute \generator "nMigen" module \output$54 - attribute \src "libresoc.v:159491.3-159502.6" + attribute \src "libresoc.v:159490.3-159501.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:159150.7-159150.20" + attribute \src "libresoc.v:159149.7-159149.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159479.3-159490.6" + attribute \src "libresoc.v:159478.3-159489.6" wire width 65 $0\o$23[64:0]$8533 - attribute \src "libresoc.v:159491.3-159502.6" + attribute \src "libresoc.v:159490.3-159501.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:159479.3-159490.6" + attribute \src "libresoc.v:159478.3-159489.6" wire width 65 $1\o$23[64:0]$8534 - attribute \src "libresoc.v:159476.18-159476.112" - wire $and$libresoc.v:159476$8529_Y + attribute \src "libresoc.v:159475.18-159475.112" + wire $and$libresoc.v:159475$8529_Y + attribute \src "libresoc.v:159471.18-159471.127" + wire $eq$libresoc.v:159471$8525_Y attribute \src "libresoc.v:159472.18-159472.127" - wire $eq$libresoc.v:159472$8525_Y - attribute \src "libresoc.v:159473.18-159473.127" - wire $eq$libresoc.v:159473$8526_Y - attribute \src "libresoc.v:159470.18-159470.103" - wire width 65 $extend$libresoc.v:159470$8521_Y - attribute \src "libresoc.v:159471.18-159471.101" - wire width 65 $extend$libresoc.v:159471$8523_Y - attribute \src "libresoc.v:159469.18-159469.100" - wire width 64 $not$libresoc.v:159469$8520_Y - attribute \src "libresoc.v:159475.18-159475.107" - wire $not$libresoc.v:159475$8528_Y - attribute \src "libresoc.v:159478.18-159478.107" - wire $not$libresoc.v:159478$8531_Y - attribute \src "libresoc.v:159477.18-159477.115" - wire $or$libresoc.v:159477$8530_Y - attribute \src "libresoc.v:159470.18-159470.103" - wire width 65 $pos$libresoc.v:159470$8522_Y - attribute \src "libresoc.v:159471.18-159471.101" - wire width 65 $pos$libresoc.v:159471$8524_Y - attribute \src "libresoc.v:159474.18-159474.105" - wire $reduce_or$libresoc.v:159474$8527_Y + wire $eq$libresoc.v:159472$8526_Y + attribute \src "libresoc.v:159469.18-159469.103" + wire width 65 $extend$libresoc.v:159469$8521_Y + attribute \src "libresoc.v:159470.18-159470.101" + wire width 65 $extend$libresoc.v:159470$8523_Y + attribute \src "libresoc.v:159468.18-159468.100" + wire width 64 $not$libresoc.v:159468$8520_Y + attribute \src "libresoc.v:159474.18-159474.107" + wire $not$libresoc.v:159474$8528_Y + attribute \src "libresoc.v:159477.18-159477.107" + wire $not$libresoc.v:159477$8531_Y + attribute \src "libresoc.v:159476.18-159476.115" + wire $or$libresoc.v:159476$8530_Y + attribute \src "libresoc.v:159469.18-159469.103" + wire width 65 $pos$libresoc.v:159469$8522_Y + attribute \src "libresoc.v:159470.18-159470.101" + wire width 65 $pos$libresoc.v:159470$8524_Y + attribute \src "libresoc.v:159473.18-159473.105" + wire $reduce_or$libresoc.v:159473$8527_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -330963,7 +327773,7 @@ module \output$54 wire width 4 output 44 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 45 \cr_a_ok - attribute \src "libresoc.v:159150.7-159150.15" + attribute \src "libresoc.v:159149.7-159149.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -331256,7 +328066,7 @@ module \output$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 22 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:159476$8529 + cell $and $and$libresoc.v:159475$8529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331264,10 +328074,10 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$36 - connect \Y $and$libresoc.v:159476$8529_Y + connect \Y $and$libresoc.v:159475$8529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:159472$8525 + cell $eq $eq$libresoc.v:159471$8525 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -331275,10 +328085,10 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:159472$8525_Y + connect \Y $eq$libresoc.v:159471$8525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:159473$8526 + cell $eq $eq$libresoc.v:159472$8526 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -331286,50 +328096,50 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:159473$8526_Y + connect \Y $eq$libresoc.v:159472$8526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:159470$8521 + cell $pos $extend$libresoc.v:159469$8521 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$25 - connect \Y $extend$libresoc.v:159470$8521_Y + connect \Y $extend$libresoc.v:159469$8521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:159471$8523 + cell $pos $extend$libresoc.v:159470$8523 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:159471$8523_Y + connect \Y $extend$libresoc.v:159470$8523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:159469$8520 + cell $not $not$libresoc.v:159468$8520 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:159469$8520_Y + connect \Y $not$libresoc.v:159468$8520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:159475$8528 + cell $not $not$libresoc.v:159474$8528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:159475$8528_Y + connect \Y $not$libresoc.v:159474$8528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:159478$8531 + cell $not $not$libresoc.v:159477$8531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:159478$8531_Y + connect \Y $not$libresoc.v:159477$8531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:159477$8530 + cell $or $or$libresoc.v:159476$8530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331337,47 +328147,47 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:159477$8530_Y + connect \Y $or$libresoc.v:159476$8530_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:159470$8522 + cell $pos $pos$libresoc.v:159469$8522 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159470$8521_Y - connect \Y $pos$libresoc.v:159470$8522_Y + connect \A $extend$libresoc.v:159469$8521_Y + connect \Y $pos$libresoc.v:159469$8522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:159471$8524 + cell $pos $pos$libresoc.v:159470$8524 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159471$8523_Y - connect \Y $pos$libresoc.v:159471$8524_Y + connect \A $extend$libresoc.v:159470$8523_Y + connect \Y $pos$libresoc.v:159470$8524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:159474$8527 + cell $reduce_or $reduce_or$libresoc.v:159473$8527 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:159474$8527_Y + connect \Y $reduce_or$libresoc.v:159473$8527_Y end - attribute \src "libresoc.v:159150.7-159150.20" - process $proc$libresoc.v:159150$8536 + attribute \src "libresoc.v:159149.7-159149.20" + process $proc$libresoc.v:159149$8536 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:159479.3-159490.6" - process $proc$libresoc.v:159479$8532 + attribute \src "libresoc.v:159478.3-159489.6" + process $proc$libresoc.v:159478$8532 assign { } { } assign $0\o$23[64:0]$8533 $1\o$23[64:0]$8534 - attribute \src "libresoc.v:159480.5-159480.29" + attribute \src "libresoc.v:159479.5-159479.29" switch \initial - attribute \src "libresoc.v:159480.9-159480.17" + attribute \src "libresoc.v:159479.9-159479.17" case 1'1 case end @@ -331395,13 +328205,13 @@ module \output$54 sync always update \o$23 $0\o$23[64:0]$8533 end - attribute \src "libresoc.v:159491.3-159502.6" - process $proc$libresoc.v:159491$8535 + attribute \src "libresoc.v:159490.3-159501.6" + process $proc$libresoc.v:159490$8535 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:159492.5-159492.29" + attribute \src "libresoc.v:159491.5-159491.29" switch \initial - attribute \src "libresoc.v:159492.9-159492.17" + attribute \src "libresoc.v:159491.9-159491.17" case 1'1 case end @@ -331419,16 +328229,16 @@ module \output$54 sync always update \cr0 $0\cr0[3:0] end - connect \$25 $not$libresoc.v:159469$8520_Y - connect \$24 $pos$libresoc.v:159470$8522_Y - connect \$28 $pos$libresoc.v:159471$8524_Y - connect \$30 $eq$libresoc.v:159472$8525_Y - connect \$32 $eq$libresoc.v:159473$8526_Y - connect \$34 $reduce_or$libresoc.v:159474$8527_Y - connect \$36 $not$libresoc.v:159475$8528_Y - connect \$38 $and$libresoc.v:159476$8529_Y - connect \$40 $or$libresoc.v:159477$8530_Y - connect \$42 $not$libresoc.v:159478$8531_Y + connect \$25 $not$libresoc.v:159468$8520_Y + connect \$24 $pos$libresoc.v:159469$8522_Y + connect \$28 $pos$libresoc.v:159470$8524_Y + connect \$30 $eq$libresoc.v:159471$8525_Y + connect \$32 $eq$libresoc.v:159472$8526_Y + connect \$34 $reduce_or$libresoc.v:159473$8527_Y + connect \$36 $not$libresoc.v:159474$8528_Y + connect \$38 $and$libresoc.v:159475$8529_Y + connect \$40 $or$libresoc.v:159476$8530_Y + connect \$42 $not$libresoc.v:159477$8531_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \logical_op__write_cr0 @@ -331443,71 +328253,71 @@ module \output$54 connect \is_cmp \$30 connect \target \o$23 [63:0] end -attribute \src "libresoc.v:159520.1-159970.10" +attribute \src "libresoc.v:159519.1-159969.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output" attribute \generator "nMigen" module \output$83 - attribute \src "libresoc.v:159891.3-159902.6" + attribute \src "libresoc.v:159890.3-159901.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:159521.7-159521.20" + attribute \src "libresoc.v:159520.7-159520.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159903.3-159914.6" + attribute \src "libresoc.v:159902.3-159913.6" wire width 65 $0\o$27[64:0]$8555 - attribute \src "libresoc.v:159879.3-159890.6" + attribute \src "libresoc.v:159878.3-159889.6" wire $0\so[0:0] - attribute \src "libresoc.v:159935.3-159944.6" + attribute \src "libresoc.v:159934.3-159943.6" wire width 2 $0\xer_ov$23[1:0]$8562 - attribute \src "libresoc.v:159945.3-159954.6" + attribute \src "libresoc.v:159944.3-159953.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:159915.3-159924.6" + attribute \src "libresoc.v:159914.3-159923.6" wire $0\xer_so$24[0:0]$8558 - attribute \src "libresoc.v:159925.3-159934.6" + attribute \src "libresoc.v:159924.3-159933.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:159891.3-159902.6" + attribute \src "libresoc.v:159890.3-159901.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:159903.3-159914.6" + attribute \src "libresoc.v:159902.3-159913.6" wire width 65 $1\o$27[64:0]$8556 - attribute \src "libresoc.v:159879.3-159890.6" + attribute \src "libresoc.v:159878.3-159889.6" wire $1\so[0:0] - attribute \src "libresoc.v:159935.3-159944.6" + attribute \src "libresoc.v:159934.3-159943.6" wire width 2 $1\xer_ov$23[1:0]$8563 - attribute \src "libresoc.v:159945.3-159954.6" + attribute \src "libresoc.v:159944.3-159953.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:159915.3-159924.6" + attribute \src "libresoc.v:159914.3-159923.6" wire $1\xer_so$24[0:0]$8559 - attribute \src "libresoc.v:159925.3-159934.6" + attribute \src "libresoc.v:159924.3-159933.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:159866.18-159866.136" - wire $and$libresoc.v:159866$8537_Y - attribute \src "libresoc.v:159874.18-159874.112" - wire $and$libresoc.v:159874$8547_Y - attribute \src "libresoc.v:159877.18-159877.133" - wire $and$libresoc.v:159877$8550_Y + attribute \src "libresoc.v:159865.18-159865.136" + wire $and$libresoc.v:159865$8537_Y + attribute \src "libresoc.v:159873.18-159873.112" + wire $and$libresoc.v:159873$8547_Y + attribute \src "libresoc.v:159876.18-159876.133" + wire $and$libresoc.v:159876$8550_Y + attribute \src "libresoc.v:159869.18-159869.127" + wire $eq$libresoc.v:159869$8543_Y attribute \src "libresoc.v:159870.18-159870.127" - wire $eq$libresoc.v:159870$8543_Y - attribute \src "libresoc.v:159871.18-159871.127" - wire $eq$libresoc.v:159871$8544_Y - attribute \src "libresoc.v:159868.18-159868.103" - wire width 65 $extend$libresoc.v:159868$8539_Y - attribute \src "libresoc.v:159869.18-159869.101" - wire width 65 $extend$libresoc.v:159869$8541_Y - attribute \src "libresoc.v:159867.18-159867.100" - wire width 64 $not$libresoc.v:159867$8538_Y - attribute \src "libresoc.v:159873.18-159873.107" - wire $not$libresoc.v:159873$8546_Y - attribute \src "libresoc.v:159876.18-159876.107" - wire $not$libresoc.v:159876$8549_Y - attribute \src "libresoc.v:159875.18-159875.115" - wire $or$libresoc.v:159875$8548_Y - attribute \src "libresoc.v:159878.18-159878.112" - wire $or$libresoc.v:159878$8551_Y - attribute \src "libresoc.v:159868.18-159868.103" - wire width 65 $pos$libresoc.v:159868$8540_Y - attribute \src "libresoc.v:159869.18-159869.101" - wire width 65 $pos$libresoc.v:159869$8542_Y - attribute \src "libresoc.v:159872.18-159872.105" - wire $reduce_or$libresoc.v:159872$8545_Y + wire $eq$libresoc.v:159870$8544_Y + attribute \src "libresoc.v:159867.18-159867.103" + wire width 65 $extend$libresoc.v:159867$8539_Y + attribute \src "libresoc.v:159868.18-159868.101" + wire width 65 $extend$libresoc.v:159868$8541_Y + attribute \src "libresoc.v:159866.18-159866.100" + wire width 64 $not$libresoc.v:159866$8538_Y + attribute \src "libresoc.v:159872.18-159872.107" + wire $not$libresoc.v:159872$8546_Y + attribute \src "libresoc.v:159875.18-159875.107" + wire $not$libresoc.v:159875$8549_Y + attribute \src "libresoc.v:159874.18-159874.115" + wire $or$libresoc.v:159874$8548_Y + attribute \src "libresoc.v:159877.18-159877.112" + wire $or$libresoc.v:159877$8551_Y + attribute \src "libresoc.v:159867.18-159867.103" + wire width 65 $pos$libresoc.v:159867$8540_Y + attribute \src "libresoc.v:159868.18-159868.101" + wire width 65 $pos$libresoc.v:159868$8542_Y + attribute \src "libresoc.v:159871.18-159871.105" + wire $reduce_or$libresoc.v:159871$8545_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -331542,7 +328352,7 @@ module \output$83 wire width 4 output 45 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 46 \cr_a_ok - attribute \src "libresoc.v:159521.7-159521.15" + attribute \src "libresoc.v:159520.7-159520.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -331851,7 +328661,7 @@ module \output$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 50 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:159866$8537 + cell $and $and$libresoc.v:159865$8537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331859,10 +328669,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:159866$8537_Y + connect \Y $and$libresoc.v:159865$8537_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:159874$8547 + cell $and $and$libresoc.v:159873$8547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331870,10 +328680,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$40 - connect \Y $and$libresoc.v:159874$8547_Y + connect \Y $and$libresoc.v:159873$8547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:159877$8550 + cell $and $and$libresoc.v:159876$8550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331881,10 +328691,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:159877$8550_Y + connect \Y $and$libresoc.v:159876$8550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:159870$8543 + cell $eq $eq$libresoc.v:159869$8543 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -331892,10 +328702,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:159870$8543_Y + connect \Y $eq$libresoc.v:159869$8543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:159871$8544 + cell $eq $eq$libresoc.v:159870$8544 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -331903,50 +328713,50 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:159871$8544_Y + connect \Y $eq$libresoc.v:159870$8544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:159868$8539 + cell $pos $extend$libresoc.v:159867$8539 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$29 - connect \Y $extend$libresoc.v:159868$8539_Y + connect \Y $extend$libresoc.v:159867$8539_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:159869$8541 + cell $pos $extend$libresoc.v:159868$8541 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:159869$8541_Y + connect \Y $extend$libresoc.v:159868$8541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:159867$8538 + cell $not $not$libresoc.v:159866$8538 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:159867$8538_Y + connect \Y $not$libresoc.v:159866$8538_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:159873$8546 + cell $not $not$libresoc.v:159872$8546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:159873$8546_Y + connect \Y $not$libresoc.v:159872$8546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:159876$8549 + cell $not $not$libresoc.v:159875$8549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:159876$8549_Y + connect \Y $not$libresoc.v:159875$8549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:159875$8548 + cell $or $or$libresoc.v:159874$8548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331954,10 +328764,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:159875$8548_Y + connect \Y $or$libresoc.v:159874$8548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:159878$8551 + cell $or $or$libresoc.v:159877$8551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331965,47 +328775,47 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:159878$8551_Y + connect \Y $or$libresoc.v:159877$8551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:159868$8540 + cell $pos $pos$libresoc.v:159867$8540 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159868$8539_Y - connect \Y $pos$libresoc.v:159868$8540_Y + connect \A $extend$libresoc.v:159867$8539_Y + connect \Y $pos$libresoc.v:159867$8540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:159869$8542 + cell $pos $pos$libresoc.v:159868$8542 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159869$8541_Y - connect \Y $pos$libresoc.v:159869$8542_Y + connect \A $extend$libresoc.v:159868$8541_Y + connect \Y $pos$libresoc.v:159868$8542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:159872$8545 + cell $reduce_or $reduce_or$libresoc.v:159871$8545 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:159872$8545_Y + connect \Y $reduce_or$libresoc.v:159871$8545_Y end - attribute \src "libresoc.v:159521.7-159521.20" - process $proc$libresoc.v:159521$8565 + attribute \src "libresoc.v:159520.7-159520.20" + process $proc$libresoc.v:159520$8565 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:159879.3-159890.6" - process $proc$libresoc.v:159879$8552 + attribute \src "libresoc.v:159878.3-159889.6" + process $proc$libresoc.v:159878$8552 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:159880.5-159880.29" + attribute \src "libresoc.v:159879.5-159879.29" switch \initial - attribute \src "libresoc.v:159880.9-159880.17" + attribute \src "libresoc.v:159879.9-159879.17" case 1'1 case end @@ -332023,13 +328833,13 @@ module \output$83 sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:159891.3-159902.6" - process $proc$libresoc.v:159891$8553 + attribute \src "libresoc.v:159890.3-159901.6" + process $proc$libresoc.v:159890$8553 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:159892.5-159892.29" + attribute \src "libresoc.v:159891.5-159891.29" switch \initial - attribute \src "libresoc.v:159892.9-159892.17" + attribute \src "libresoc.v:159891.9-159891.17" case 1'1 case end @@ -332047,13 +328857,13 @@ module \output$83 sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:159903.3-159914.6" - process $proc$libresoc.v:159903$8554 + attribute \src "libresoc.v:159902.3-159913.6" + process $proc$libresoc.v:159902$8554 assign { } { } assign $0\o$27[64:0]$8555 $1\o$27[64:0]$8556 - attribute \src "libresoc.v:159904.5-159904.29" + attribute \src "libresoc.v:159903.5-159903.29" switch \initial - attribute \src "libresoc.v:159904.9-159904.17" + attribute \src "libresoc.v:159903.9-159903.17" case 1'1 case end @@ -332071,14 +328881,14 @@ module \output$83 sync always update \o$27 $0\o$27[64:0]$8555 end - attribute \src "libresoc.v:159915.3-159924.6" - process $proc$libresoc.v:159915$8557 + attribute \src "libresoc.v:159914.3-159923.6" + process $proc$libresoc.v:159914$8557 assign { } { } assign { } { } assign $0\xer_so$24[0:0]$8558 $1\xer_so$24[0:0]$8559 - attribute \src "libresoc.v:159916.5-159916.29" + attribute \src "libresoc.v:159915.5-159915.29" switch \initial - attribute \src "libresoc.v:159916.9-159916.17" + attribute \src "libresoc.v:159915.9-159915.17" case 1'1 case end @@ -332094,14 +328904,14 @@ module \output$83 sync always update \xer_so$24 $0\xer_so$24[0:0]$8558 end - attribute \src "libresoc.v:159925.3-159934.6" - process $proc$libresoc.v:159925$8560 + attribute \src "libresoc.v:159924.3-159933.6" + process $proc$libresoc.v:159924$8560 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:159926.5-159926.29" + attribute \src "libresoc.v:159925.5-159925.29" switch \initial - attribute \src "libresoc.v:159926.9-159926.17" + attribute \src "libresoc.v:159925.9-159925.17" case 1'1 case end @@ -332117,14 +328927,14 @@ module \output$83 sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:159935.3-159944.6" - process $proc$libresoc.v:159935$8561 + attribute \src "libresoc.v:159934.3-159943.6" + process $proc$libresoc.v:159934$8561 assign { } { } assign { } { } assign $0\xer_ov$23[1:0]$8562 $1\xer_ov$23[1:0]$8563 - attribute \src "libresoc.v:159936.5-159936.29" + attribute \src "libresoc.v:159935.5-159935.29" switch \initial - attribute \src "libresoc.v:159936.9-159936.17" + attribute \src "libresoc.v:159935.9-159935.17" case 1'1 case end @@ -332140,14 +328950,14 @@ module \output$83 sync always update \xer_ov$23 $0\xer_ov$23[1:0]$8562 end - attribute \src "libresoc.v:159945.3-159954.6" - process $proc$libresoc.v:159945$8564 + attribute \src "libresoc.v:159944.3-159953.6" + process $proc$libresoc.v:159944$8564 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:159946.5-159946.29" + attribute \src "libresoc.v:159945.5-159945.29" switch \initial - attribute \src "libresoc.v:159946.9-159946.17" + attribute \src "libresoc.v:159945.9-159945.17" case 1'1 case end @@ -332163,19 +328973,19 @@ module \output$83 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$25 $and$libresoc.v:159866$8537_Y - connect \$29 $not$libresoc.v:159867$8538_Y - connect \$28 $pos$libresoc.v:159868$8540_Y - connect \$32 $pos$libresoc.v:159869$8542_Y - connect \$34 $eq$libresoc.v:159870$8543_Y - connect \$36 $eq$libresoc.v:159871$8544_Y - connect \$38 $reduce_or$libresoc.v:159872$8545_Y - connect \$40 $not$libresoc.v:159873$8546_Y - connect \$42 $and$libresoc.v:159874$8547_Y - connect \$44 $or$libresoc.v:159875$8548_Y - connect \$46 $not$libresoc.v:159876$8549_Y - connect \$49 $and$libresoc.v:159877$8550_Y - connect \$51 $or$libresoc.v:159878$8551_Y + connect \$25 $and$libresoc.v:159865$8537_Y + connect \$29 $not$libresoc.v:159866$8538_Y + connect \$28 $pos$libresoc.v:159867$8540_Y + connect \$32 $pos$libresoc.v:159868$8542_Y + connect \$34 $eq$libresoc.v:159869$8543_Y + connect \$36 $eq$libresoc.v:159870$8544_Y + connect \$38 $reduce_or$libresoc.v:159871$8545_Y + connect \$40 $not$libresoc.v:159872$8546_Y + connect \$42 $and$libresoc.v:159873$8547_Y + connect \$44 $or$libresoc.v:159874$8548_Y + connect \$46 $not$libresoc.v:159875$8549_Y + connect \$49 $and$libresoc.v:159876$8550_Y + connect \$51 $or$libresoc.v:159877$8551_Y connect \oe$48 \$49 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid @@ -332192,93 +329002,93 @@ module \output$83 connect \target \o$27 [63:0] connect \oe \$25 end -attribute \src "libresoc.v:159974.1-160456.10" +attribute \src "libresoc.v:159973.1-160455.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output_stage" attribute \generator "nMigen" module \output_stage - attribute \src "libresoc.v:159975.7-159975.20" + attribute \src "libresoc.v:159974.7-159974.20" wire $0\initial[0:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:160336.3-160407.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:160409.3-160442.6" + attribute \src "libresoc.v:160408.3-160441.6" wire $0\ov[0:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:160336.3-160407.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:160409.3-160442.6" + attribute \src "libresoc.v:160408.3-160441.6" wire $1\ov[0:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:160336.3-160407.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:160409.3-160442.6" + attribute \src "libresoc.v:160408.3-160441.6" wire $2\ov[0:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:160336.3-160407.6" wire width 64 $3\o[63:0] - attribute \src "libresoc.v:160409.3-160442.6" + attribute \src "libresoc.v:160408.3-160441.6" wire $3\ov[0:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:160336.3-160407.6" wire width 64 $4\o[63:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:160336.3-160407.6" wire width 64 $5\o[63:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:160336.3-160407.6" wire width 64 $6\o[63:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:160336.3-160407.6" wire width 64 $7\o[63:0] - attribute \src "libresoc.v:160337.3-160408.6" + attribute \src "libresoc.v:160336.3-160407.6" wire width 64 $8\o[63:0] - attribute \src "libresoc.v:160328.18-160328.122" - wire $and$libresoc.v:160328$8579_Y - attribute \src "libresoc.v:160320.18-160320.109" - wire width 65 $extend$libresoc.v:160320$8567_Y - attribute \src "libresoc.v:160321.18-160321.100" - wire width 65 $extend$libresoc.v:160321$8569_Y - attribute \src "libresoc.v:160323.18-160323.113" - wire width 65 $extend$libresoc.v:160323$8572_Y - attribute \src "libresoc.v:160324.18-160324.104" - wire width 65 $extend$libresoc.v:160324$8574_Y + attribute \src "libresoc.v:160327.18-160327.122" + wire $and$libresoc.v:160327$8579_Y + attribute \src "libresoc.v:160319.18-160319.109" + wire width 65 $extend$libresoc.v:160319$8567_Y + attribute \src "libresoc.v:160320.18-160320.100" + wire width 65 $extend$libresoc.v:160320$8569_Y + attribute \src "libresoc.v:160322.18-160322.113" + wire width 65 $extend$libresoc.v:160322$8572_Y + attribute \src "libresoc.v:160323.18-160323.104" + wire width 65 $extend$libresoc.v:160323$8574_Y + attribute \src "libresoc.v:160331.18-160331.114" + wire width 64 $extend$libresoc.v:160331$8583_Y attribute \src "libresoc.v:160332.18-160332.114" - wire width 64 $extend$libresoc.v:160332$8583_Y + wire width 64 $extend$libresoc.v:160332$8585_Y attribute \src "libresoc.v:160333.18-160333.114" - wire width 64 $extend$libresoc.v:160333$8585_Y + wire width 64 $extend$libresoc.v:160333$8587_Y attribute \src "libresoc.v:160334.18-160334.114" - wire width 64 $extend$libresoc.v:160334$8587_Y - attribute \src "libresoc.v:160335.18-160335.114" - wire width 64 $extend$libresoc.v:160335$8589_Y - attribute \src "libresoc.v:160336.18-160336.115" - wire width 64 $extend$libresoc.v:160336$8591_Y - attribute \src "libresoc.v:160329.18-160329.128" - wire $ne$libresoc.v:160329$8580_Y - attribute \src "libresoc.v:160320.18-160320.109" - wire width 65 $neg$libresoc.v:160320$8568_Y - attribute \src "libresoc.v:160323.18-160323.113" - wire width 65 $neg$libresoc.v:160323$8573_Y - attribute \src "libresoc.v:160326.18-160326.116" - wire $not$libresoc.v:160326$8577_Y - attribute \src "libresoc.v:160331.18-160331.99" - wire $not$libresoc.v:160331$8582_Y - attribute \src "libresoc.v:160321.18-160321.100" - wire width 65 $pos$libresoc.v:160321$8570_Y - attribute \src "libresoc.v:160324.18-160324.104" - wire width 65 $pos$libresoc.v:160324$8575_Y - attribute \src "libresoc.v:160330.18-160330.118" - wire width 64 $pos$libresoc.v:160330$8581_Y + wire width 64 $extend$libresoc.v:160334$8589_Y + attribute \src "libresoc.v:160335.18-160335.115" + wire width 64 $extend$libresoc.v:160335$8591_Y + attribute \src "libresoc.v:160328.18-160328.128" + wire $ne$libresoc.v:160328$8580_Y + attribute \src "libresoc.v:160319.18-160319.109" + wire width 65 $neg$libresoc.v:160319$8568_Y + attribute \src "libresoc.v:160322.18-160322.113" + wire width 65 $neg$libresoc.v:160322$8573_Y + attribute \src "libresoc.v:160325.18-160325.116" + wire $not$libresoc.v:160325$8577_Y + attribute \src "libresoc.v:160330.18-160330.99" + wire $not$libresoc.v:160330$8582_Y + attribute \src "libresoc.v:160320.18-160320.100" + wire width 65 $pos$libresoc.v:160320$8570_Y + attribute \src "libresoc.v:160323.18-160323.104" + wire width 65 $pos$libresoc.v:160323$8575_Y + attribute \src "libresoc.v:160329.18-160329.118" + wire width 64 $pos$libresoc.v:160329$8581_Y + attribute \src "libresoc.v:160331.18-160331.114" + wire width 64 $pos$libresoc.v:160331$8584_Y attribute \src "libresoc.v:160332.18-160332.114" - wire width 64 $pos$libresoc.v:160332$8584_Y + wire width 64 $pos$libresoc.v:160332$8586_Y attribute \src "libresoc.v:160333.18-160333.114" - wire width 64 $pos$libresoc.v:160333$8586_Y + wire width 64 $pos$libresoc.v:160333$8588_Y attribute \src "libresoc.v:160334.18-160334.114" - wire width 64 $pos$libresoc.v:160334$8588_Y - attribute \src "libresoc.v:160335.18-160335.114" - wire width 64 $pos$libresoc.v:160335$8590_Y - attribute \src "libresoc.v:160336.18-160336.115" - wire width 64 $pos$libresoc.v:160336$8592_Y - attribute \src "libresoc.v:160322.18-160322.121" - wire width 65 $ternary$libresoc.v:160322$8571_Y - attribute \src "libresoc.v:160325.18-160325.122" - wire width 65 $ternary$libresoc.v:160325$8576_Y - attribute \src "libresoc.v:160319.18-160319.120" - wire $xor$libresoc.v:160319$8566_Y - attribute \src "libresoc.v:160327.18-160327.127" - wire $xor$libresoc.v:160327$8578_Y + wire width 64 $pos$libresoc.v:160334$8590_Y + attribute \src "libresoc.v:160335.18-160335.115" + wire width 64 $pos$libresoc.v:160335$8592_Y + attribute \src "libresoc.v:160321.18-160321.121" + wire width 65 $ternary$libresoc.v:160321$8571_Y + attribute \src "libresoc.v:160324.18-160324.122" + wire width 65 $ternary$libresoc.v:160324$8576_Y + attribute \src "libresoc.v:160318.18-160318.120" + wire $xor$libresoc.v:160318$8566_Y + attribute \src "libresoc.v:160326.18-160326.127" + wire $xor$libresoc.v:160326$8578_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" @@ -332327,7 +329137,7 @@ module \output_stage wire input 21 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 20 \divisor_neg - attribute \src "libresoc.v:159975.7-159975.15" + attribute \src "libresoc.v:159974.7-159974.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -332624,7 +329434,7 @@ module \output_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 50 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $and $and$libresoc.v:160328$8579 + cell $and $and$libresoc.v:160327$8579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332632,82 +329442,82 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \logical_op__is_signed connect \B \$38 - connect \Y $and$libresoc.v:160328$8579_Y + connect \Y $and$libresoc.v:160327$8579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $pos $extend$libresoc.v:160320$8567 + cell $pos $extend$libresoc.v:160319$8567 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:160320$8567_Y + connect \Y $extend$libresoc.v:160319$8567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $extend$libresoc.v:160321$8569 + cell $pos $extend$libresoc.v:160320$8569 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:160321$8569_Y + connect \Y $extend$libresoc.v:160320$8569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $pos $extend$libresoc.v:160323$8572 + cell $pos $extend$libresoc.v:160322$8572 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:160323$8572_Y + connect \Y $extend$libresoc.v:160322$8572_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:160324$8574 + cell $pos $extend$libresoc.v:160323$8574 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:160324$8574_Y + connect \Y $extend$libresoc.v:160323$8574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $extend$libresoc.v:160332$8583 + cell $pos $extend$libresoc.v:160331$8583 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:160332$8583_Y + connect \Y $extend$libresoc.v:160331$8583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $extend$libresoc.v:160333$8585 + cell $pos $extend$libresoc.v:160332$8585 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:160333$8585_Y + connect \Y $extend$libresoc.v:160332$8585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $extend$libresoc.v:160334$8587 + cell $pos $extend$libresoc.v:160333$8587 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:160334$8587_Y + connect \Y $extend$libresoc.v:160333$8587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $extend$libresoc.v:160335$8589 + cell $pos $extend$libresoc.v:160334$8589 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:160335$8589_Y + connect \Y $extend$libresoc.v:160334$8589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $extend$libresoc.v:160336$8591 + cell $pos $extend$libresoc.v:160335$8591 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \remainder_64 [31:0] - connect \Y $extend$libresoc.v:160336$8591_Y + connect \Y $extend$libresoc.v:160335$8591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - cell $ne $ne$libresoc.v:160329$8580 + cell $ne $ne$libresoc.v:160328$8580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332715,122 +329525,122 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [32] connect \B \quotient_65 [31] - connect \Y $ne$libresoc.v:160329$8580_Y + connect \Y $ne$libresoc.v:160328$8580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $neg $neg$libresoc.v:160320$8568 + cell $neg $neg$libresoc.v:160319$8568 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:160320$8567_Y - connect \Y $neg$libresoc.v:160320$8568_Y + connect \A $extend$libresoc.v:160319$8567_Y + connect \Y $neg$libresoc.v:160319$8568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $neg $neg$libresoc.v:160323$8573 + cell $neg $neg$libresoc.v:160322$8573 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:160323$8572_Y - connect \Y $neg$libresoc.v:160323$8573_Y + connect \A $extend$libresoc.v:160322$8572_Y + connect \Y $neg$libresoc.v:160322$8573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - cell $not $not$libresoc.v:160326$8577 + cell $not $not$libresoc.v:160325$8577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \logical_op__is_32bit - connect \Y $not$libresoc.v:160326$8577_Y + connect \Y $not$libresoc.v:160325$8577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - cell $not $not$libresoc.v:160331$8582 + cell $not $not$libresoc.v:160330$8582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ov - connect \Y $not$libresoc.v:160331$8582_Y + connect \Y $not$libresoc.v:160330$8582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $pos$libresoc.v:160321$8570 + cell $pos $pos$libresoc.v:160320$8570 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:160321$8569_Y - connect \Y $pos$libresoc.v:160321$8570_Y + connect \A $extend$libresoc.v:160320$8569_Y + connect \Y $pos$libresoc.v:160320$8570_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:160324$8575 + cell $pos $pos$libresoc.v:160323$8575 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:160324$8574_Y - connect \Y $pos$libresoc.v:160324$8575_Y + connect \A $extend$libresoc.v:160323$8574_Y + connect \Y $pos$libresoc.v:160323$8575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" - cell $pos $pos$libresoc.v:160330$8581 + cell $pos $pos$libresoc.v:160329$8581 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 } - connect \Y $pos$libresoc.v:160330$8581_Y + connect \Y $pos$libresoc.v:160329$8581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $pos$libresoc.v:160332$8584 + cell $pos $pos$libresoc.v:160331$8584 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:160332$8583_Y - connect \Y $pos$libresoc.v:160332$8584_Y + connect \A $extend$libresoc.v:160331$8583_Y + connect \Y $pos$libresoc.v:160331$8584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $pos$libresoc.v:160333$8586 + cell $pos $pos$libresoc.v:160332$8586 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:160333$8585_Y - connect \Y $pos$libresoc.v:160333$8586_Y + connect \A $extend$libresoc.v:160332$8585_Y + connect \Y $pos$libresoc.v:160332$8586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $pos$libresoc.v:160334$8588 + cell $pos $pos$libresoc.v:160333$8588 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:160334$8587_Y - connect \Y $pos$libresoc.v:160334$8588_Y + connect \A $extend$libresoc.v:160333$8587_Y + connect \Y $pos$libresoc.v:160333$8588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $pos$libresoc.v:160335$8590 + cell $pos $pos$libresoc.v:160334$8590 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:160335$8589_Y - connect \Y $pos$libresoc.v:160335$8590_Y + connect \A $extend$libresoc.v:160334$8589_Y + connect \Y $pos$libresoc.v:160334$8590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $pos$libresoc.v:160336$8592 + cell $pos $pos$libresoc.v:160335$8592 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:160336$8591_Y - connect \Y $pos$libresoc.v:160336$8592_Y + connect \A $extend$libresoc.v:160335$8591_Y + connect \Y $pos$libresoc.v:160335$8592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $mux $ternary$libresoc.v:160322$8571 + cell $mux $ternary$libresoc.v:160321$8571 parameter \WIDTH 65 connect \A \$25 connect \B \$23 connect \S \quotient_neg - connect \Y $ternary$libresoc.v:160322$8571_Y + connect \Y $ternary$libresoc.v:160321$8571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $mux $ternary$libresoc.v:160325$8576 + cell $mux $ternary$libresoc.v:160324$8576 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \remainder_neg - connect \Y $ternary$libresoc.v:160325$8576_Y + connect \Y $ternary$libresoc.v:160324$8576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" - cell $xor $xor$libresoc.v:160319$8566 + cell $xor $xor$libresoc.v:160318$8566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332838,10 +329648,10 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \dividend_neg connect \B \divisor_neg - connect \Y $xor$libresoc.v:160319$8566_Y + connect \Y $xor$libresoc.v:160318$8566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $xor $xor$libresoc.v:160327$8578 + cell $xor $xor$libresoc.v:160326$8578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -332849,24 +329659,24 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [64] connect \B \quotient_65 [63] - connect \Y $xor$libresoc.v:160327$8578_Y + connect \Y $xor$libresoc.v:160326$8578_Y end - attribute \src "libresoc.v:159975.7-159975.20" - process $proc$libresoc.v:159975$8595 + attribute \src "libresoc.v:159974.7-159974.20" + process $proc$libresoc.v:159974$8595 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160337.3-160408.6" - process $proc$libresoc.v:160337$8593 + attribute \src "libresoc.v:160336.3-160407.6" + process $proc$libresoc.v:160336$8593 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:160338.5-160338.29" + attribute \src "libresoc.v:160337.5-160337.29" switch \initial - attribute \src "libresoc.v:160338.9-160338.17" + attribute \src "libresoc.v:160337.9-160337.17" case 1'1 case end @@ -332965,13 +329775,13 @@ module \output_stage sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:160409.3-160442.6" - process $proc$libresoc.v:160409$8594 + attribute \src "libresoc.v:160408.3-160441.6" + process $proc$libresoc.v:160408$8594 assign { } { } assign $0\ov[0:0] $1\ov[0:0] - attribute \src "libresoc.v:160410.5-160410.29" + attribute \src "libresoc.v:160409.5-160409.29" switch \initial - attribute \src "libresoc.v:160410.9-160410.17" + attribute \src "libresoc.v:160409.9-160409.17" case 1'1 case end @@ -333017,24 +329827,24 @@ module \output_stage sync always update \ov $0\ov[0:0] end - connect \$21 $xor$libresoc.v:160319$8566_Y - connect \$23 $neg$libresoc.v:160320$8568_Y - connect \$25 $pos$libresoc.v:160321$8570_Y - connect \$27 $ternary$libresoc.v:160322$8571_Y - connect \$30 $neg$libresoc.v:160323$8573_Y - connect \$32 $pos$libresoc.v:160324$8575_Y - connect \$34 $ternary$libresoc.v:160325$8576_Y - connect \$36 $not$libresoc.v:160326$8577_Y - connect \$38 $xor$libresoc.v:160327$8578_Y - connect \$40 $and$libresoc.v:160328$8579_Y - connect \$42 $ne$libresoc.v:160329$8580_Y - connect \$44 $pos$libresoc.v:160330$8581_Y - connect \$46 $not$libresoc.v:160331$8582_Y - connect \$48 $pos$libresoc.v:160332$8584_Y - connect \$50 $pos$libresoc.v:160333$8586_Y - connect \$52 $pos$libresoc.v:160334$8588_Y - connect \$54 $pos$libresoc.v:160335$8590_Y - connect \$56 $pos$libresoc.v:160336$8592_Y + connect \$21 $xor$libresoc.v:160318$8566_Y + connect \$23 $neg$libresoc.v:160319$8568_Y + connect \$25 $pos$libresoc.v:160320$8570_Y + connect \$27 $ternary$libresoc.v:160321$8571_Y + connect \$30 $neg$libresoc.v:160322$8573_Y + connect \$32 $pos$libresoc.v:160323$8575_Y + connect \$34 $ternary$libresoc.v:160324$8576_Y + connect \$36 $not$libresoc.v:160325$8577_Y + connect \$38 $xor$libresoc.v:160326$8578_Y + connect \$40 $and$libresoc.v:160327$8579_Y + connect \$42 $ne$libresoc.v:160328$8580_Y + connect \$44 $pos$libresoc.v:160329$8581_Y + connect \$46 $not$libresoc.v:160330$8582_Y + connect \$48 $pos$libresoc.v:160331$8584_Y + connect \$50 $pos$libresoc.v:160332$8586_Y + connect \$52 $pos$libresoc.v:160333$8588_Y + connect \$54 $pos$libresoc.v:160334$8590_Y + connect \$56 $pos$libresoc.v:160335$8592_Y connect \$29 \$34 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid @@ -333049,13 +329859,13 @@ module \output_stage connect \remainder_neg \dividend_neg connect \quotient_neg \$21 end -attribute \src "libresoc.v:160460.1-160471.10" +attribute \src "libresoc.v:160459.1-160470.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p" attribute \generator "nMigen" module \p - attribute \src "libresoc.v:160469.17-160469.111" - wire $and$libresoc.v:160469$8596_Y + attribute \src "libresoc.v:160468.17-160468.111" + wire $and$libresoc.v:160468$8596_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333065,7 +329875,7 @@ module \p attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160469$8596 + cell $and $and$libresoc.v:160468$8596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333073,18 +329883,18 @@ module \p parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160469$8596_Y + connect \Y $and$libresoc.v:160468$8596_Y end - connect \$1 $and$libresoc.v:160469$8596_Y + connect \$1 $and$libresoc.v:160468$8596_Y connect \trigger \$1 end -attribute \src "libresoc.v:160475.1-160486.10" +attribute \src "libresoc.v:160474.1-160485.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" attribute \generator "nMigen" module \p$1 - attribute \src "libresoc.v:160484.17-160484.111" - wire $and$libresoc.v:160484$8597_Y + attribute \src "libresoc.v:160483.17-160483.111" + wire $and$libresoc.v:160483$8597_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333094,7 +329904,7 @@ module \p$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160484$8597 + cell $and $and$libresoc.v:160483$8597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333102,18 +329912,18 @@ module \p$1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160484$8597_Y + connect \Y $and$libresoc.v:160483$8597_Y end - connect \$1 $and$libresoc.v:160484$8597_Y + connect \$1 $and$libresoc.v:160483$8597_Y connect \trigger \$1 end -attribute \src "libresoc.v:160490.1-160501.10" +attribute \src "libresoc.v:160489.1-160500.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p" attribute \generator "nMigen" module \p$108 - attribute \src "libresoc.v:160499.17-160499.111" - wire $and$libresoc.v:160499$8598_Y + attribute \src "libresoc.v:160498.17-160498.111" + wire $and$libresoc.v:160498$8598_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333123,7 +329933,7 @@ module \p$108 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160499$8598 + cell $and $and$libresoc.v:160498$8598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333131,18 +329941,18 @@ module \p$108 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160499$8598_Y + connect \Y $and$libresoc.v:160498$8598_Y end - connect \$1 $and$libresoc.v:160499$8598_Y + connect \$1 $and$libresoc.v:160498$8598_Y connect \trigger \$1 end -attribute \src "libresoc.v:160505.1-160516.10" +attribute \src "libresoc.v:160504.1-160515.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" attribute \generator "nMigen" module \p$111 - attribute \src "libresoc.v:160514.17-160514.111" - wire $and$libresoc.v:160514$8599_Y + attribute \src "libresoc.v:160513.17-160513.111" + wire $and$libresoc.v:160513$8599_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333152,7 +329962,7 @@ module \p$111 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160514$8599 + cell $and $and$libresoc.v:160513$8599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333160,18 +329970,18 @@ module \p$111 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160514$8599_Y + connect \Y $and$libresoc.v:160513$8599_Y end - connect \$1 $and$libresoc.v:160514$8599_Y + connect \$1 $and$libresoc.v:160513$8599_Y connect \trigger \$1 end -attribute \src "libresoc.v:160520.1-160531.10" +attribute \src "libresoc.v:160519.1-160530.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" attribute \generator "nMigen" module \p$116 - attribute \src "libresoc.v:160529.17-160529.111" - wire $and$libresoc.v:160529$8600_Y + attribute \src "libresoc.v:160528.17-160528.111" + wire $and$libresoc.v:160528$8600_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333181,7 +329991,7 @@ module \p$116 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160529$8600 + cell $and $and$libresoc.v:160528$8600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333189,18 +329999,18 @@ module \p$116 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160529$8600_Y + connect \Y $and$libresoc.v:160528$8600_Y end - connect \$1 $and$libresoc.v:160529$8600_Y + connect \$1 $and$libresoc.v:160528$8600_Y connect \trigger \$1 end -attribute \src "libresoc.v:160535.1-160546.10" +attribute \src "libresoc.v:160534.1-160545.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.p" attribute \generator "nMigen" module \p$17 - attribute \src "libresoc.v:160544.17-160544.111" - wire $and$libresoc.v:160544$8601_Y + attribute \src "libresoc.v:160543.17-160543.111" + wire $and$libresoc.v:160543$8601_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333210,7 +330020,7 @@ module \p$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160544$8601 + cell $and $and$libresoc.v:160543$8601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333218,18 +330028,18 @@ module \p$17 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160544$8601_Y + connect \Y $and$libresoc.v:160543$8601_Y end - connect \$1 $and$libresoc.v:160544$8601_Y + connect \$1 $and$libresoc.v:160543$8601_Y connect \trigger \$1 end -attribute \src "libresoc.v:160550.1-160561.10" +attribute \src "libresoc.v:160549.1-160560.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.p" attribute \generator "nMigen" module \p$20 - attribute \src "libresoc.v:160559.17-160559.111" - wire $and$libresoc.v:160559$8602_Y + attribute \src "libresoc.v:160558.17-160558.111" + wire $and$libresoc.v:160558$8602_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333239,7 +330049,7 @@ module \p$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160559$8602 + cell $and $and$libresoc.v:160558$8602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333247,18 +330057,18 @@ module \p$20 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160559$8602_Y + connect \Y $and$libresoc.v:160558$8602_Y end - connect \$1 $and$libresoc.v:160559$8602_Y + connect \$1 $and$libresoc.v:160558$8602_Y connect \trigger \$1 end -attribute \src "libresoc.v:160565.1-160576.10" +attribute \src "libresoc.v:160564.1-160575.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.p" attribute \generator "nMigen" module \p$3 - attribute \src "libresoc.v:160574.17-160574.111" - wire $and$libresoc.v:160574$8603_Y + attribute \src "libresoc.v:160573.17-160573.111" + wire $and$libresoc.v:160573$8603_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333268,7 +330078,7 @@ module \p$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160574$8603 + cell $and $and$libresoc.v:160573$8603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333276,18 +330086,18 @@ module \p$3 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160574$8603_Y + connect \Y $and$libresoc.v:160573$8603_Y end - connect \$1 $and$libresoc.v:160574$8603_Y + connect \$1 $and$libresoc.v:160573$8603_Y connect \trigger \$1 end -attribute \src "libresoc.v:160580.1-160591.10" +attribute \src "libresoc.v:160579.1-160590.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.p" attribute \generator "nMigen" module \p$30 - attribute \src "libresoc.v:160589.17-160589.111" - wire $and$libresoc.v:160589$8604_Y + attribute \src "libresoc.v:160588.17-160588.111" + wire $and$libresoc.v:160588$8604_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333297,7 +330107,7 @@ module \p$30 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160589$8604 + cell $and $and$libresoc.v:160588$8604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333305,18 +330115,18 @@ module \p$30 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160589$8604_Y + connect \Y $and$libresoc.v:160588$8604_Y end - connect \$1 $and$libresoc.v:160589$8604_Y + connect \$1 $and$libresoc.v:160588$8604_Y connect \trigger \$1 end -attribute \src "libresoc.v:160595.1-160606.10" +attribute \src "libresoc.v:160594.1-160605.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.p" attribute \generator "nMigen" module \p$33 - attribute \src "libresoc.v:160604.17-160604.111" - wire $and$libresoc.v:160604$8605_Y + attribute \src "libresoc.v:160603.17-160603.111" + wire $and$libresoc.v:160603$8605_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333326,7 +330136,7 @@ module \p$33 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160604$8605 + cell $and $and$libresoc.v:160603$8605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333334,18 +330144,18 @@ module \p$33 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160604$8605_Y + connect \Y $and$libresoc.v:160603$8605_Y end - connect \$1 $and$libresoc.v:160604$8605_Y + connect \$1 $and$libresoc.v:160603$8605_Y connect \trigger \$1 end -attribute \src "libresoc.v:160610.1-160621.10" +attribute \src "libresoc.v:160609.1-160620.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.p" attribute \generator "nMigen" module \p$36 - attribute \src "libresoc.v:160619.17-160619.111" - wire $and$libresoc.v:160619$8606_Y + attribute \src "libresoc.v:160618.17-160618.111" + wire $and$libresoc.v:160618$8606_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333355,7 +330165,7 @@ module \p$36 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160619$8606 + cell $and $and$libresoc.v:160618$8606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333363,18 +330173,18 @@ module \p$36 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160619$8606_Y + connect \Y $and$libresoc.v:160618$8606_Y end - connect \$1 $and$libresoc.v:160619$8606_Y + connect \$1 $and$libresoc.v:160618$8606_Y connect \trigger \$1 end -attribute \src "libresoc.v:160625.1-160636.10" +attribute \src "libresoc.v:160624.1-160635.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.p" attribute \generator "nMigen" module \p$46 - attribute \src "libresoc.v:160634.17-160634.111" - wire $and$libresoc.v:160634$8607_Y + attribute \src "libresoc.v:160633.17-160633.111" + wire $and$libresoc.v:160633$8607_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333384,7 +330194,7 @@ module \p$46 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160634$8607 + cell $and $and$libresoc.v:160633$8607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333392,18 +330202,18 @@ module \p$46 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160634$8607_Y + connect \Y $and$libresoc.v:160633$8607_Y end - connect \$1 $and$libresoc.v:160634$8607_Y + connect \$1 $and$libresoc.v:160633$8607_Y connect \trigger \$1 end -attribute \src "libresoc.v:160640.1-160651.10" +attribute \src "libresoc.v:160639.1-160650.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.p" attribute \generator "nMigen" module \p$48 - attribute \src "libresoc.v:160649.17-160649.111" - wire $and$libresoc.v:160649$8608_Y + attribute \src "libresoc.v:160648.17-160648.111" + wire $and$libresoc.v:160648$8608_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333413,7 +330223,7 @@ module \p$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160649$8608 + cell $and $and$libresoc.v:160648$8608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333421,18 +330231,18 @@ module \p$48 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160649$8608_Y + connect \Y $and$libresoc.v:160648$8608_Y end - connect \$1 $and$libresoc.v:160649$8608_Y + connect \$1 $and$libresoc.v:160648$8608_Y connect \trigger \$1 end -attribute \src "libresoc.v:160655.1-160666.10" +attribute \src "libresoc.v:160654.1-160665.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.p" attribute \generator "nMigen" module \p$5 - attribute \src "libresoc.v:160664.17-160664.111" - wire $and$libresoc.v:160664$8609_Y + attribute \src "libresoc.v:160663.17-160663.111" + wire $and$libresoc.v:160663$8609_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333442,7 +330252,7 @@ module \p$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160664$8609 + cell $and $and$libresoc.v:160663$8609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333450,18 +330260,18 @@ module \p$5 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160664$8609_Y + connect \Y $and$libresoc.v:160663$8609_Y end - connect \$1 $and$libresoc.v:160664$8609_Y + connect \$1 $and$libresoc.v:160663$8609_Y connect \trigger \$1 end -attribute \src "libresoc.v:160670.1-160681.10" +attribute \src "libresoc.v:160669.1-160680.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.p" attribute \generator "nMigen" module \p$52 - attribute \src "libresoc.v:160679.17-160679.111" - wire $and$libresoc.v:160679$8610_Y + attribute \src "libresoc.v:160678.17-160678.111" + wire $and$libresoc.v:160678$8610_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333471,7 +330281,7 @@ module \p$52 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160679$8610 + cell $and $and$libresoc.v:160678$8610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333479,18 +330289,18 @@ module \p$52 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160679$8610_Y + connect \Y $and$libresoc.v:160678$8610_Y end - connect \$1 $and$libresoc.v:160679$8610_Y + connect \$1 $and$libresoc.v:160678$8610_Y connect \trigger \$1 end -attribute \src "libresoc.v:160685.1-160696.10" +attribute \src "libresoc.v:160684.1-160695.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.p" attribute \generator "nMigen" module \p$62 - attribute \src "libresoc.v:160694.17-160694.111" - wire $and$libresoc.v:160694$8611_Y + attribute \src "libresoc.v:160693.17-160693.111" + wire $and$libresoc.v:160693$8611_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333500,7 +330310,7 @@ module \p$62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160694$8611 + cell $and $and$libresoc.v:160693$8611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333508,18 +330318,18 @@ module \p$62 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160694$8611_Y + connect \Y $and$libresoc.v:160693$8611_Y end - connect \$1 $and$libresoc.v:160694$8611_Y + connect \$1 $and$libresoc.v:160693$8611_Y connect \trigger \$1 end -attribute \src "libresoc.v:160700.1-160711.10" +attribute \src "libresoc.v:160699.1-160710.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.p" attribute \generator "nMigen" module \p$65 - attribute \src "libresoc.v:160709.17-160709.111" - wire $and$libresoc.v:160709$8612_Y + attribute \src "libresoc.v:160708.17-160708.111" + wire $and$libresoc.v:160708$8612_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333529,7 +330339,7 @@ module \p$65 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160709$8612 + cell $and $and$libresoc.v:160708$8612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333537,18 +330347,18 @@ module \p$65 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160709$8612_Y + connect \Y $and$libresoc.v:160708$8612_Y end - connect \$1 $and$libresoc.v:160709$8612_Y + connect \$1 $and$libresoc.v:160708$8612_Y connect \trigger \$1 end -attribute \src "libresoc.v:160715.1-160726.10" +attribute \src "libresoc.v:160714.1-160725.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.p" attribute \generator "nMigen" module \p$7 - attribute \src "libresoc.v:160724.17-160724.111" - wire $and$libresoc.v:160724$8613_Y + attribute \src "libresoc.v:160723.17-160723.111" + wire $and$libresoc.v:160723$8613_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333558,7 +330368,7 @@ module \p$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160724$8613 + cell $and $and$libresoc.v:160723$8613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333566,18 +330376,18 @@ module \p$7 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160724$8613_Y + connect \Y $and$libresoc.v:160723$8613_Y end - connect \$1 $and$libresoc.v:160724$8613_Y + connect \$1 $and$libresoc.v:160723$8613_Y connect \trigger \$1 end -attribute \src "libresoc.v:160730.1-160741.10" +attribute \src "libresoc.v:160729.1-160740.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.p" attribute \generator "nMigen" module \p$74 - attribute \src "libresoc.v:160739.17-160739.111" - wire $and$libresoc.v:160739$8614_Y + attribute \src "libresoc.v:160738.17-160738.111" + wire $and$libresoc.v:160738$8614_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333587,7 +330397,7 @@ module \p$74 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160739$8614 + cell $and $and$libresoc.v:160738$8614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333595,18 +330405,18 @@ module \p$74 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160739$8614_Y + connect \Y $and$libresoc.v:160738$8614_Y end - connect \$1 $and$libresoc.v:160739$8614_Y + connect \$1 $and$libresoc.v:160738$8614_Y connect \trigger \$1 end -attribute \src "libresoc.v:160745.1-160756.10" +attribute \src "libresoc.v:160744.1-160755.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.p" attribute \generator "nMigen" module \p$76 - attribute \src "libresoc.v:160754.17-160754.111" - wire $and$libresoc.v:160754$8615_Y + attribute \src "libresoc.v:160753.17-160753.111" + wire $and$libresoc.v:160753$8615_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333616,7 +330426,7 @@ module \p$76 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160754$8615 + cell $and $and$libresoc.v:160753$8615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333624,18 +330434,18 @@ module \p$76 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160754$8615_Y + connect \Y $and$libresoc.v:160753$8615_Y end - connect \$1 $and$libresoc.v:160754$8615_Y + connect \$1 $and$libresoc.v:160753$8615_Y connect \trigger \$1 end -attribute \src "libresoc.v:160760.1-160771.10" +attribute \src "libresoc.v:160759.1-160770.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.p" attribute \generator "nMigen" module \p$79 - attribute \src "libresoc.v:160769.17-160769.111" - wire $and$libresoc.v:160769$8616_Y + attribute \src "libresoc.v:160768.17-160768.111" + wire $and$libresoc.v:160768$8616_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333645,7 +330455,7 @@ module \p$79 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160769$8616 + cell $and $and$libresoc.v:160768$8616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333653,18 +330463,18 @@ module \p$79 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160769$8616_Y + connect \Y $and$libresoc.v:160768$8616_Y end - connect \$1 $and$libresoc.v:160769$8616_Y + connect \$1 $and$libresoc.v:160768$8616_Y connect \trigger \$1 end -attribute \src "libresoc.v:160775.1-160786.10" +attribute \src "libresoc.v:160774.1-160785.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.p" attribute \generator "nMigen" module \p$81 - attribute \src "libresoc.v:160784.17-160784.111" - wire $and$libresoc.v:160784$8617_Y + attribute \src "libresoc.v:160783.17-160783.111" + wire $and$libresoc.v:160783$8617_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333674,7 +330484,7 @@ module \p$81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160784$8617 + cell $and $and$libresoc.v:160783$8617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333682,18 +330492,18 @@ module \p$81 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160784$8617_Y + connect \Y $and$libresoc.v:160783$8617_Y end - connect \$1 $and$libresoc.v:160784$8617_Y + connect \$1 $and$libresoc.v:160783$8617_Y connect \trigger \$1 end -attribute \src "libresoc.v:160790.1-160801.10" +attribute \src "libresoc.v:160789.1-160800.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.p" attribute \generator "nMigen" module \p$91 - attribute \src "libresoc.v:160799.17-160799.111" - wire $and$libresoc.v:160799$8618_Y + attribute \src "libresoc.v:160798.17-160798.111" + wire $and$libresoc.v:160798$8618_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333703,7 +330513,7 @@ module \p$91 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160799$8618 + cell $and $and$libresoc.v:160798$8618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333711,18 +330521,18 @@ module \p$91 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160799$8618_Y + connect \Y $and$libresoc.v:160798$8618_Y end - connect \$1 $and$libresoc.v:160799$8618_Y + connect \$1 $and$libresoc.v:160798$8618_Y connect \trigger \$1 end -attribute \src "libresoc.v:160805.1-160816.10" +attribute \src "libresoc.v:160804.1-160815.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.p" attribute \generator "nMigen" module \p$93 - attribute \src "libresoc.v:160814.17-160814.111" - wire $and$libresoc.v:160814$8619_Y + attribute \src "libresoc.v:160813.17-160813.111" + wire $and$libresoc.v:160813$8619_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333732,7 +330542,7 @@ module \p$93 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160814$8619 + cell $and $and$libresoc.v:160813$8619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333740,18 +330550,18 @@ module \p$93 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160814$8619_Y + connect \Y $and$libresoc.v:160813$8619_Y end - connect \$1 $and$libresoc.v:160814$8619_Y + connect \$1 $and$libresoc.v:160813$8619_Y connect \trigger \$1 end -attribute \src "libresoc.v:160820.1-160831.10" +attribute \src "libresoc.v:160819.1-160830.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.p" attribute \generator "nMigen" module \p$96 - attribute \src "libresoc.v:160829.17-160829.111" - wire $and$libresoc.v:160829$8620_Y + attribute \src "libresoc.v:160828.17-160828.111" + wire $and$libresoc.v:160828$8620_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333761,7 +330571,7 @@ module \p$96 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160829$8620 + cell $and $and$libresoc.v:160828$8620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333769,18 +330579,18 @@ module \p$96 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160829$8620_Y + connect \Y $and$libresoc.v:160828$8620_Y end - connect \$1 $and$libresoc.v:160829$8620_Y + connect \$1 $and$libresoc.v:160828$8620_Y connect \trigger \$1 end -attribute \src "libresoc.v:160835.1-160846.10" +attribute \src "libresoc.v:160834.1-160845.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.p" attribute \generator "nMigen" module \p$98 - attribute \src "libresoc.v:160844.17-160844.111" - wire $and$libresoc.v:160844$8621_Y + attribute \src "libresoc.v:160843.17-160843.111" + wire $and$libresoc.v:160843$8621_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -333790,7 +330600,7 @@ module \p$98 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160844$8621 + cell $and $and$libresoc.v:160843$8621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333798,36 +330608,36 @@ module \p$98 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160844$8621_Y + connect \Y $and$libresoc.v:160843$8621_Y end - connect \$1 $and$libresoc.v:160844$8621_Y + connect \$1 $and$libresoc.v:160843$8621_Y connect \trigger \$1 end -attribute \src "libresoc.v:160850.1-160873.10" +attribute \src "libresoc.v:160849.1-160872.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.pick" attribute \generator "nMigen" module \pick - attribute \src "libresoc.v:160851.7-160851.20" + attribute \src "libresoc.v:160850.7-160850.20" wire $0\initial[0:0] - attribute \src "libresoc.v:160862.3-160871.6" + attribute \src "libresoc.v:160861.3-160870.6" wire $0\o[0:0] - attribute \src "libresoc.v:160862.3-160871.6" + attribute \src "libresoc.v:160861.3-160870.6" wire $1\o[0:0] - attribute \src "libresoc.v:160861.17-160861.95" - wire $eq$libresoc.v:160861$8622_Y + attribute \src "libresoc.v:160860.17-160860.95" + wire $eq$libresoc.v:160860$8622_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" wire input 3 \i - attribute \src "libresoc.v:160851.7-160851.15" + attribute \src "libresoc.v:160850.7-160850.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" wire output 2 \n attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $eq$libresoc.v:160861$8622 + cell $eq $eq$libresoc.v:160860$8622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333835,24 +330645,24 @@ module \pick parameter \Y_WIDTH 1 connect \A \i connect \B 1'0 - connect \Y $eq$libresoc.v:160861$8622_Y + connect \Y $eq$libresoc.v:160860$8622_Y end - attribute \src "libresoc.v:160851.7-160851.20" - process $proc$libresoc.v:160851$8624 + attribute \src "libresoc.v:160850.7-160850.20" + process $proc$libresoc.v:160850$8624 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160862.3-160871.6" - process $proc$libresoc.v:160862$8623 + attribute \src "libresoc.v:160861.3-160870.6" + process $proc$libresoc.v:160861$8623 assign { } { } assign { } { } assign $0\o[0:0] $1\o[0:0] - attribute \src "libresoc.v:160863.5-160863.29" + attribute \src "libresoc.v:160862.5-160862.29" switch \initial - attribute \src "libresoc.v:160863.9-160863.17" + attribute \src "libresoc.v:160862.9-160862.17" case 1'1 case end @@ -333868,296 +330678,296 @@ module \pick sync always update \o $0\o[0:0] end - connect \$1 $eq$libresoc.v:160861$8622_Y + connect \$1 $eq$libresoc.v:160860$8622_Y connect \n \$1 end -attribute \src "libresoc.v:160877.1-161691.10" +attribute \src "libresoc.v:160876.1-161690.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem" attribute \generator "nMigen" module \pimem - attribute \src "libresoc.v:161654.3-161669.6" + attribute \src "libresoc.v:161653.3-161668.6" wire $0\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:161618.3-161653.6" + attribute \src "libresoc.v:161617.3-161652.6" wire $0\adrok_l_s_addr_acked$next[0:0]$8714 - attribute \src "libresoc.v:161176.3-161177.57" + attribute \src "libresoc.v:161175.3-161176.57" wire $0\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:161268.3-161276.6" + attribute \src "libresoc.v:161267.3-161275.6" wire $0\busy_delay$next[0:0]$8682 - attribute \src "libresoc.v:161174.3-161175.37" + attribute \src "libresoc.v:161173.3-161174.37" wire $0\busy_delay[0:0] - attribute \src "libresoc.v:161602.3-161617.6" + attribute \src "libresoc.v:161601.3-161616.6" wire $0\busy_l_r_busy[0:0] - attribute \src "libresoc.v:161592.3-161601.6" + attribute \src "libresoc.v:161591.3-161600.6" wire $0\busy_l_s_busy[0:0] - attribute \src "libresoc.v:161582.3-161591.6" + attribute \src "libresoc.v:161581.3-161590.6" wire $0\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:161563.3-161572.6" + attribute \src "libresoc.v:161562.3-161571.6" wire $0\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:161524.3-161562.6" + attribute \src "libresoc.v:161523.3-161561.6" wire width 2 $0\fsm_state$next[1:0]$8700 - attribute \src "libresoc.v:161166.3-161167.35" + attribute \src "libresoc.v:161165.3-161166.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:160878.7-160878.20" + attribute \src "libresoc.v:160877.7-160877.20" wire $0\initial[0:0] - attribute \src "libresoc.v:161464.3-161473.6" + attribute \src "libresoc.v:161463.3-161472.6" wire $0\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:161172.3-161173.35" + attribute \src "libresoc.v:161171.3-161172.35" wire $0\lds_dly[0:0] - attribute \src "libresoc.v:161397.3-161427.6" + attribute \src "libresoc.v:161396.3-161426.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161454.3-161463.6" + attribute \src "libresoc.v:161453.3-161462.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:161474.3-161483.6" + attribute \src "libresoc.v:161473.3-161482.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:161303.3-161318.6" + attribute \src "libresoc.v:161302.3-161317.6" wire width 4 $0\lenexp_addr_i[3:0] - attribute \src "libresoc.v:161287.3-161302.6" + attribute \src "libresoc.v:161286.3-161301.6" wire width 4 $0\lenexp_len_i[3:0] - attribute \src "libresoc.v:161573.3-161581.6" + attribute \src "libresoc.v:161572.3-161580.6" wire $0\lsui_active_dly$next[0:0]$8708 - attribute \src "libresoc.v:161164.3-161165.47" + attribute \src "libresoc.v:161163.3-161164.47" wire $0\lsui_active_dly[0:0] - attribute \src "libresoc.v:161504.3-161523.6" + attribute \src "libresoc.v:161503.3-161522.6" wire $0\lsui_busy[0:0] - attribute \src "libresoc.v:161168.3-161169.36" + attribute \src "libresoc.v:161167.3-161168.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:161444.3-161453.6" + attribute \src "libresoc.v:161443.3-161452.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:161428.3-161443.6" + attribute \src "libresoc.v:161427.3-161442.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:161277.3-161286.6" + attribute \src "libresoc.v:161276.3-161285.6" wire $0\st_active_r_st_active[0:0] - attribute \src "libresoc.v:161258.3-161267.6" + attribute \src "libresoc.v:161257.3-161266.6" wire $0\st_done_r_st_done[0:0] - attribute \src "libresoc.v:161243.3-161257.6" + attribute \src "libresoc.v:161242.3-161256.6" wire $0\st_done_s_st_done$next[0:0]$8677 - attribute \src "libresoc.v:161178.3-161179.51" + attribute \src "libresoc.v:161177.3-161178.51" wire $0\st_done_s_st_done[0:0] - attribute \src "libresoc.v:161484.3-161493.6" + attribute \src "libresoc.v:161483.3-161492.6" wire width 64 $0\stdata[63:0] - attribute \src "libresoc.v:161170.3-161171.35" + attribute \src "libresoc.v:161169.3-161170.35" wire $0\sts_dly[0:0] - attribute \src "libresoc.v:161319.3-161344.6" + attribute \src "libresoc.v:161318.3-161343.6" wire $0\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161371.3-161396.6" + attribute \src "libresoc.v:161370.3-161395.6" wire width 48 $0\x_addr_i[47:0] - attribute \src "libresoc.v:161345.3-161370.6" + attribute \src "libresoc.v:161344.3-161369.6" wire width 8 $0\x_mask_i[7:0] - attribute \src "libresoc.v:161494.3-161503.6" + attribute \src "libresoc.v:161493.3-161502.6" wire width 64 $0\x_st_data_i[63:0] - attribute \src "libresoc.v:161654.3-161669.6" + attribute \src "libresoc.v:161653.3-161668.6" wire $1\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:161618.3-161653.6" + attribute \src "libresoc.v:161617.3-161652.6" wire $1\adrok_l_s_addr_acked$next[0:0]$8715 - attribute \src "libresoc.v:160972.7-160972.34" + attribute \src "libresoc.v:160971.7-160971.34" wire $1\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:161268.3-161276.6" + attribute \src "libresoc.v:161267.3-161275.6" wire $1\busy_delay$next[0:0]$8683 - attribute \src "libresoc.v:160976.7-160976.24" + attribute \src "libresoc.v:160975.7-160975.24" wire $1\busy_delay[0:0] - attribute \src "libresoc.v:161602.3-161617.6" + attribute \src "libresoc.v:161601.3-161616.6" wire $1\busy_l_r_busy[0:0] - attribute \src "libresoc.v:161592.3-161601.6" + attribute \src "libresoc.v:161591.3-161600.6" wire $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:161582.3-161591.6" + attribute \src "libresoc.v:161581.3-161590.6" wire $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:161563.3-161572.6" + attribute \src "libresoc.v:161562.3-161571.6" wire $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:161524.3-161562.6" + attribute \src "libresoc.v:161523.3-161561.6" wire width 2 $1\fsm_state$next[1:0]$8701 - attribute \src "libresoc.v:160998.13-160998.29" + attribute \src "libresoc.v:160997.13-160997.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:161464.3-161473.6" + attribute \src "libresoc.v:161463.3-161472.6" wire $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:161012.7-161012.21" + attribute \src "libresoc.v:161011.7-161011.21" wire $1\lds_dly[0:0] - attribute \src "libresoc.v:161397.3-161427.6" + attribute \src "libresoc.v:161396.3-161426.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161454.3-161463.6" + attribute \src "libresoc.v:161453.3-161462.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:161474.3-161483.6" + attribute \src "libresoc.v:161473.3-161482.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:161303.3-161318.6" + attribute \src "libresoc.v:161302.3-161317.6" wire width 4 $1\lenexp_addr_i[3:0] - attribute \src "libresoc.v:161287.3-161302.6" + attribute \src "libresoc.v:161286.3-161301.6" wire width 4 $1\lenexp_len_i[3:0] - attribute \src "libresoc.v:161573.3-161581.6" + attribute \src "libresoc.v:161572.3-161580.6" wire $1\lsui_active_dly$next[0:0]$8709 - attribute \src "libresoc.v:161055.7-161055.29" + attribute \src "libresoc.v:161054.7-161054.29" wire $1\lsui_active_dly[0:0] - attribute \src "libresoc.v:161504.3-161523.6" + attribute \src "libresoc.v:161503.3-161522.6" wire $1\lsui_busy[0:0] - attribute \src "libresoc.v:161067.7-161067.25" + attribute \src "libresoc.v:161066.7-161066.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:161444.3-161453.6" + attribute \src "libresoc.v:161443.3-161452.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:161428.3-161443.6" + attribute \src "libresoc.v:161427.3-161442.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:161277.3-161286.6" + attribute \src "libresoc.v:161276.3-161285.6" wire $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:161258.3-161267.6" + attribute \src "libresoc.v:161257.3-161266.6" wire $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:161243.3-161257.6" + attribute \src "libresoc.v:161242.3-161256.6" wire $1\st_done_s_st_done$next[0:0]$8678 - attribute \src "libresoc.v:161087.7-161087.31" + attribute \src "libresoc.v:161086.7-161086.31" wire $1\st_done_s_st_done[0:0] - attribute \src "libresoc.v:161484.3-161493.6" + attribute \src "libresoc.v:161483.3-161492.6" wire width 64 $1\stdata[63:0] - attribute \src "libresoc.v:161095.7-161095.21" + attribute \src "libresoc.v:161094.7-161094.21" wire $1\sts_dly[0:0] - attribute \src "libresoc.v:161319.3-161344.6" + attribute \src "libresoc.v:161318.3-161343.6" wire $1\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161371.3-161396.6" + attribute \src "libresoc.v:161370.3-161395.6" wire width 48 $1\x_addr_i[47:0] - attribute \src "libresoc.v:161345.3-161370.6" + attribute \src "libresoc.v:161344.3-161369.6" wire width 8 $1\x_mask_i[7:0] - attribute \src "libresoc.v:161494.3-161503.6" + attribute \src "libresoc.v:161493.3-161502.6" wire width 64 $1\x_st_data_i[63:0] - attribute \src "libresoc.v:161654.3-161669.6" + attribute \src "libresoc.v:161653.3-161668.6" wire $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:161618.3-161653.6" + attribute \src "libresoc.v:161617.3-161652.6" wire $2\adrok_l_s_addr_acked$next[0:0]$8716 - attribute \src "libresoc.v:161602.3-161617.6" + attribute \src "libresoc.v:161601.3-161616.6" wire $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:161524.3-161562.6" + attribute \src "libresoc.v:161523.3-161561.6" wire width 2 $2\fsm_state$next[1:0]$8702 - attribute \src "libresoc.v:161397.3-161427.6" + attribute \src "libresoc.v:161396.3-161426.6" wire $2\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161303.3-161318.6" + attribute \src "libresoc.v:161302.3-161317.6" wire width 4 $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:161287.3-161302.6" + attribute \src "libresoc.v:161286.3-161301.6" wire width 4 $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:161504.3-161523.6" + attribute \src "libresoc.v:161503.3-161522.6" wire $2\lsui_busy[0:0] - attribute \src "libresoc.v:161428.3-161443.6" + attribute \src "libresoc.v:161427.3-161442.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:161243.3-161257.6" + attribute \src "libresoc.v:161242.3-161256.6" wire $2\st_done_s_st_done$next[0:0]$8679 - attribute \src "libresoc.v:161319.3-161344.6" + attribute \src "libresoc.v:161318.3-161343.6" wire $2\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161371.3-161396.6" + attribute \src "libresoc.v:161370.3-161395.6" wire width 48 $2\x_addr_i[47:0] - attribute \src "libresoc.v:161345.3-161370.6" + attribute \src "libresoc.v:161344.3-161369.6" wire width 8 $2\x_mask_i[7:0] - attribute \src "libresoc.v:161618.3-161653.6" + attribute \src "libresoc.v:161617.3-161652.6" wire $3\adrok_l_s_addr_acked$next[0:0]$8717 - attribute \src "libresoc.v:161524.3-161562.6" + attribute \src "libresoc.v:161523.3-161561.6" wire width 2 $3\fsm_state$next[1:0]$8703 - attribute \src "libresoc.v:161397.3-161427.6" + attribute \src "libresoc.v:161396.3-161426.6" wire $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161319.3-161344.6" + attribute \src "libresoc.v:161318.3-161343.6" wire $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161371.3-161396.6" + attribute \src "libresoc.v:161370.3-161395.6" wire width 48 $3\x_addr_i[47:0] - attribute \src "libresoc.v:161345.3-161370.6" + attribute \src "libresoc.v:161344.3-161369.6" wire width 8 $3\x_mask_i[7:0] - attribute \src "libresoc.v:161618.3-161653.6" + attribute \src "libresoc.v:161617.3-161652.6" wire $4\adrok_l_s_addr_acked$next[0:0]$8718 - attribute \src "libresoc.v:161524.3-161562.6" + attribute \src "libresoc.v:161523.3-161561.6" wire width 2 $4\fsm_state$next[1:0]$8704 - attribute \src "libresoc.v:161397.3-161427.6" + attribute \src "libresoc.v:161396.3-161426.6" wire $4\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161319.3-161344.6" + attribute \src "libresoc.v:161318.3-161343.6" wire $4\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161371.3-161396.6" + attribute \src "libresoc.v:161370.3-161395.6" wire width 48 $4\x_addr_i[47:0] - attribute \src "libresoc.v:161345.3-161370.6" + attribute \src "libresoc.v:161344.3-161369.6" wire width 8 $4\x_mask_i[7:0] - attribute \src "libresoc.v:161618.3-161653.6" + attribute \src "libresoc.v:161617.3-161652.6" wire $5\adrok_l_s_addr_acked$next[0:0]$8719 - attribute \src "libresoc.v:161524.3-161562.6" + attribute \src "libresoc.v:161523.3-161561.6" wire width 2 $5\fsm_state$next[1:0]$8705 - attribute \src "libresoc.v:161397.3-161427.6" + attribute \src "libresoc.v:161396.3-161426.6" wire $5\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161618.3-161653.6" + attribute \src "libresoc.v:161617.3-161652.6" wire $6\adrok_l_s_addr_acked$next[0:0]$8720 - attribute \src "libresoc.v:161124.18-161124.115" - wire $and$libresoc.v:161124$8626_Y - attribute \src "libresoc.v:161126.18-161126.95" - wire $and$libresoc.v:161126$8628_Y - attribute \src "libresoc.v:161128.17-161128.138" - wire $and$libresoc.v:161128$8630_Y - attribute \src "libresoc.v:161129.18-161129.95" - wire $and$libresoc.v:161129$8631_Y + attribute \src "libresoc.v:161123.18-161123.115" + wire $and$libresoc.v:161123$8626_Y + attribute \src "libresoc.v:161125.18-161125.95" + wire $and$libresoc.v:161125$8628_Y + attribute \src "libresoc.v:161127.17-161127.138" + wire $and$libresoc.v:161127$8630_Y + attribute \src "libresoc.v:161128.18-161128.95" + wire $and$libresoc.v:161128$8631_Y + attribute \src "libresoc.v:161131.18-161131.136" + wire $and$libresoc.v:161131$8636_Y attribute \src "libresoc.v:161132.18-161132.136" - wire $and$libresoc.v:161132$8636_Y + wire $and$libresoc.v:161132$8637_Y attribute \src "libresoc.v:161133.18-161133.136" - wire $and$libresoc.v:161133$8637_Y + wire $and$libresoc.v:161133$8638_Y attribute \src "libresoc.v:161134.18-161134.136" - wire $and$libresoc.v:161134$8638_Y + wire $and$libresoc.v:161134$8639_Y attribute \src "libresoc.v:161135.18-161135.136" - wire $and$libresoc.v:161135$8639_Y - attribute \src "libresoc.v:161136.18-161136.136" - wire $and$libresoc.v:161136$8640_Y - attribute \src "libresoc.v:161141.18-161141.119" - wire width 176 $and$libresoc.v:161141$8645_Y + wire $and$libresoc.v:161135$8640_Y + attribute \src "libresoc.v:161140.18-161140.119" + wire width 176 $and$libresoc.v:161140$8645_Y + attribute \src "libresoc.v:161143.18-161143.136" + wire $and$libresoc.v:161143$8648_Y attribute \src "libresoc.v:161144.18-161144.136" - wire $and$libresoc.v:161144$8648_Y - attribute \src "libresoc.v:161145.18-161145.136" - wire $and$libresoc.v:161145$8649_Y - attribute \src "libresoc.v:161147.18-161147.139" - wire $and$libresoc.v:161147$8651_Y - attribute \src "libresoc.v:161151.18-161151.139" - wire $and$libresoc.v:161151$8655_Y - attribute \src "libresoc.v:161153.18-161153.114" - wire $and$libresoc.v:161153$8657_Y - attribute \src "libresoc.v:161155.18-161155.114" - wire $and$libresoc.v:161155$8659_Y - attribute \src "libresoc.v:161159.18-161159.103" - wire $and$libresoc.v:161159$8663_Y - attribute \src "libresoc.v:161160.17-161160.135" - wire $and$libresoc.v:161160$8664_Y - attribute \src "libresoc.v:161163.18-161163.103" - wire $and$libresoc.v:161163$8667_Y + wire $and$libresoc.v:161144$8649_Y + attribute \src "libresoc.v:161146.18-161146.139" + wire $and$libresoc.v:161146$8651_Y + attribute \src "libresoc.v:161150.18-161150.139" + wire $and$libresoc.v:161150$8655_Y + attribute \src "libresoc.v:161152.18-161152.114" + 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$mul$libresoc.v:161147$8652_Y + attribute \src "libresoc.v:161122.17-161122.103" + wire $not$libresoc.v:161122$8625_Y + attribute \src "libresoc.v:161124.18-161124.94" + wire $not$libresoc.v:161124$8627_Y + attribute \src "libresoc.v:161126.18-161126.94" + wire $not$libresoc.v:161126$8629_Y + attribute \src "libresoc.v:161136.18-161136.102" + wire $not$libresoc.v:161136$8641_Y + attribute \src "libresoc.v:161139.18-161139.97" + wire $not$libresoc.v:161139$8644_Y + attribute \src "libresoc.v:161145.18-161145.102" + wire $not$libresoc.v:161145$8650_Y + attribute \src "libresoc.v:161148.17-161148.103" + wire $not$libresoc.v:161148$8653_Y + attribute \src "libresoc.v:161155.18-161155.101" + wire $not$libresoc.v:161155$8660_Y + attribute \src "libresoc.v:161156.18-161156.111" + wire $not$libresoc.v:161156$8661_Y + attribute \src "libresoc.v:161157.18-161157.110" + wire $not$libresoc.v:161157$8662_Y + attribute \src "libresoc.v:161160.18-161160.102" + wire $not$libresoc.v:161160$8665_Y attribute \src "libresoc.v:161161.18-161161.102" - wire $not$libresoc.v:161161$8665_Y - attribute \src "libresoc.v:161162.18-161162.102" - wire $not$libresoc.v:161162$8666_Y - attribute \src "libresoc.v:161138.18-161138.111" - wire $or$libresoc.v:161138$8642_Y - attribute \src "libresoc.v:161139.17-161139.130" - wire $or$libresoc.v:161139$8643_Y - attribute \src "libresoc.v:161152.18-161152.130" - wire $or$libresoc.v:161152$8656_Y - attribute \src "libresoc.v:161154.18-161154.130" - wire $or$libresoc.v:161154$8658_Y + wire $not$libresoc.v:161161$8666_Y + attribute \src "libresoc.v:161137.18-161137.111" + wire $or$libresoc.v:161137$8642_Y + attribute \src "libresoc.v:161138.17-161138.130" + wire $or$libresoc.v:161138$8643_Y + attribute \src "libresoc.v:161151.18-161151.130" + wire $or$libresoc.v:161151$8656_Y + attribute \src "libresoc.v:161153.18-161153.130" + wire $or$libresoc.v:161153$8658_Y + attribute \src "libresoc.v:161129.18-161129.109" + wire width 4 $pos$libresoc.v:161129$8633_Y attribute \src "libresoc.v:161130.18-161130.109" - wire width 4 $pos$libresoc.v:161130$8633_Y - attribute \src "libresoc.v:161131.18-161131.109" - wire width 4 $pos$libresoc.v:161131$8635_Y - attribute \src "libresoc.v:161150.18-161150.121" - wire width 319 $sshl$libresoc.v:161150$8654_Y - attribute \src "libresoc.v:161143.18-161143.106" - wire width 176 $sshr$libresoc.v:161143$8647_Y + wire width 4 $pos$libresoc.v:161130$8635_Y + attribute \src "libresoc.v:161149.18-161149.121" + wire width 319 $sshl$libresoc.v:161149$8654_Y + attribute \src "libresoc.v:161142.18-161142.106" + wire width 176 $sshr$libresoc.v:161142$8647_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" @@ -334280,7 +331090,7 @@ module \pimem wire width 2 \fsm_state attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" wire width 2 \fsm_state$next - attribute \src "libresoc.v:160878.7-160878.15" + attribute \src "libresoc.v:160877.7-160877.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \ld_active_q_ld_active @@ -334399,7 +331209,7 @@ module \pimem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire output 22 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $and $and$libresoc.v:161124$8626 + cell $and $and$libresoc.v:161123$8626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334407,10 +331217,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o connect \B \$9 - connect \Y $and$libresoc.v:161124$8626_Y + connect \Y $and$libresoc.v:161123$8626_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:161126$8628 + cell $and $and$libresoc.v:161125$8628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334418,10 +331228,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lds connect \B \$13 - connect \Y $and$libresoc.v:161126$8628_Y + connect \Y $and$libresoc.v:161125$8628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:161128$8630 + cell $and $and$libresoc.v:161127$8630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334429,10 +331239,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:161128$8630_Y + connect \Y $and$libresoc.v:161127$8630_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:161129$8631 + cell $and $and$libresoc.v:161128$8631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334440,10 +331250,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \sts connect \B \$17 - connect \Y $and$libresoc.v:161129$8631_Y + connect \Y $and$libresoc.v:161128$8631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:161132$8636 + cell $and $and$libresoc.v:161131$8636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334451,10 +331261,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:161132$8636_Y + connect \Y $and$libresoc.v:161131$8636_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:161133$8637 + cell $and $and$libresoc.v:161132$8637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334462,10 +331272,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:161133$8637_Y + connect \Y $and$libresoc.v:161132$8637_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:161134$8638 + cell $and $and$libresoc.v:161133$8638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334473,10 +331283,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:161134$8638_Y + connect \Y $and$libresoc.v:161133$8638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:161135$8639 + cell $and $and$libresoc.v:161134$8639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334484,10 +331294,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:161135$8639_Y + connect \Y $and$libresoc.v:161134$8639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:161136$8640 + cell $and $and$libresoc.v:161135$8640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334495,10 +331305,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:161136$8640_Y + connect \Y $and$libresoc.v:161135$8640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" - cell $and $and$libresoc.v:161141$8645 + cell $and $and$libresoc.v:161140$8645 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -334506,10 +331316,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \m_ld_data_o connect \B \lenexp_rexp_o - connect \Y $and$libresoc.v:161141$8645_Y + connect \Y $and$libresoc.v:161140$8645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:161144$8648 + cell $and $and$libresoc.v:161143$8648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334517,10 +331327,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:161144$8648_Y + connect \Y $and$libresoc.v:161143$8648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:161145$8649 + cell $and $and$libresoc.v:161144$8649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334528,10 +331338,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:161145$8649_Y + connect \Y $and$libresoc.v:161144$8649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:161147$8651 + cell $and $and$libresoc.v:161146$8651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334539,10 +331349,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:161147$8651_Y + connect \Y $and$libresoc.v:161146$8651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:161151$8655 + cell $and $and$libresoc.v:161150$8655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334550,10 +331360,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:161151$8655_Y + connect \Y $and$libresoc.v:161150$8655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:161153$8657 + cell $and $and$libresoc.v:161152$8657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334561,10 +331371,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$63 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:161153$8657_Y + connect \Y $and$libresoc.v:161152$8657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:161155$8659 + cell $and $and$libresoc.v:161154$8659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334572,10 +331382,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$67 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:161155$8659_Y + connect \Y $and$libresoc.v:161154$8659_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $and $and$libresoc.v:161159$8663 + cell $and $and$libresoc.v:161158$8663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334583,10 +331393,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$73 connect \B \$75 - connect \Y $and$libresoc.v:161159$8663_Y + connect \Y $and$libresoc.v:161158$8663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:161160$8664 + cell $and $and$libresoc.v:161159$8664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334594,10 +331404,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:161160$8664_Y + connect \Y $and$libresoc.v:161159$8664_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:161163$8667 + cell $and $and$libresoc.v:161162$8667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334605,26 +331415,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lsui_active connect \B \$81 - connect \Y $and$libresoc.v:161163$8667_Y + connect \Y $and$libresoc.v:161162$8667_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:161130$8632 + cell $pos $extend$libresoc.v:161129$8632 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:161130$8632_Y + connect \Y $extend$libresoc.v:161129$8632_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:161131$8634 + cell $pos $extend$libresoc.v:161130$8634 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:161131$8634_Y + connect \Y $extend$libresoc.v:161130$8634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $mul $mul$libresoc.v:161142$8646 + cell $mul $mul$libresoc.v:161141$8646 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -334632,10 +331442,10 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:161142$8646_Y + connect \Y $mul$libresoc.v:161141$8646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $mul $mul$libresoc.v:161148$8652 + cell $mul $mul$libresoc.v:161147$8652 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -334643,106 +331453,106 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:161148$8652_Y + connect \Y $mul$libresoc.v:161147$8652_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $not $not$libresoc.v:161123$8625 + cell $not $not$libresoc.v:161122$8625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:161123$8625_Y + connect \Y $not$libresoc.v:161122$8625_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:161125$8627 + cell $not $not$libresoc.v:161124$8627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lds_dly - connect \Y $not$libresoc.v:161125$8627_Y + connect \Y $not$libresoc.v:161124$8627_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:161127$8629 + cell $not $not$libresoc.v:161126$8629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sts_dly - connect \Y $not$libresoc.v:161127$8629_Y + connect \Y $not$libresoc.v:161126$8629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:161137$8641 + cell $not $not$libresoc.v:161136$8641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:161137$8641_Y + connect \Y $not$libresoc.v:161136$8641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $not $not$libresoc.v:161140$8644 + cell $not $not$libresoc.v:161139$8644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 - connect \Y $not$libresoc.v:161140$8644_Y + connect \Y $not$libresoc.v:161139$8644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:161146$8650 + cell $not $not$libresoc.v:161145$8650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:161146$8650_Y + connect \Y $not$libresoc.v:161145$8650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" - cell $not $not$libresoc.v:161149$8653 + cell $not $not$libresoc.v:161148$8653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:161149$8653_Y + connect \Y $not$libresoc.v:161148$8653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - cell $not $not$libresoc.v:161156$8660 + cell $not $not$libresoc.v:161155$8660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:161156$8660_Y + connect \Y $not$libresoc.v:161155$8660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:161157$8661 + cell $not $not$libresoc.v:161156$8661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_st_i - connect \Y $not$libresoc.v:161157$8661_Y + connect \Y $not$libresoc.v:161156$8661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:161158$8662 + cell $not $not$libresoc.v:161157$8662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:161158$8662_Y + connect \Y $not$libresoc.v:161157$8662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" - cell $not $not$libresoc.v:161161$8665 + cell $not $not$libresoc.v:161160$8665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:161161$8665_Y + connect \Y $not$libresoc.v:161160$8665_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:161162$8666 + cell $not $not$libresoc.v:161161$8666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_active_dly - connect \Y $not$libresoc.v:161162$8666_Y + connect \Y $not$libresoc.v:161161$8666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $or $or$libresoc.v:161138$8642 + cell $or $or$libresoc.v:161137$8642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334750,10 +331560,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \x_busy_o connect \B \lsui_busy - connect \Y $or$libresoc.v:161138$8642_Y + connect \Y $or$libresoc.v:161137$8642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - cell $or $or$libresoc.v:161139$8643 + cell $or $or$libresoc.v:161138$8643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334761,10 +331571,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:161139$8643_Y + connect \Y $or$libresoc.v:161138$8643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:161152$8656 + cell $or $or$libresoc.v:161151$8656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334772,10 +331582,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:161152$8656_Y + connect \Y $or$libresoc.v:161151$8656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:161154$8658 + cell $or $or$libresoc.v:161153$8658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334783,26 +331593,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:161154$8658_Y + connect \Y $or$libresoc.v:161153$8658_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:161130$8633 + cell $pos $pos$libresoc.v:161129$8633 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:161130$8632_Y - connect \Y $pos$libresoc.v:161130$8633_Y + connect \A $extend$libresoc.v:161129$8632_Y + connect \Y $pos$libresoc.v:161129$8633_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:161131$8635 + cell $pos $pos$libresoc.v:161130$8635 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:161131$8634_Y - connect \Y $pos$libresoc.v:161131$8635_Y + connect \A $extend$libresoc.v:161130$8634_Y + connect \Y $pos$libresoc.v:161130$8635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $sshl $sshl$libresoc.v:161150$8654 + cell $sshl $sshl$libresoc.v:161149$8654 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -334810,10 +331620,10 @@ module \pimem parameter \Y_WIDTH 319 connect \A \ldst_port0_st_data_i connect \B \$57 - connect \Y $sshl$libresoc.v:161150$8654_Y + connect \Y $sshl$libresoc.v:161149$8654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $sshr $sshr$libresoc.v:161143$8647 + cell $sshr $sshr$libresoc.v:161142$8647 parameter \A_SIGNED 0 parameter \A_WIDTH 176 parameter \B_SIGNED 0 @@ -334821,10 +331631,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \$42 connect \B \$44 - connect \Y $sshr$libresoc.v:161143$8647_Y + connect \Y $sshr$libresoc.v:161142$8647_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:161180.11-161187.4" + attribute \src "libresoc.v:161179.11-161186.4" cell \adrok_l \adrok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -334834,7 +331644,7 @@ module \pimem connect \s_addr_acked \adrok_l_s_addr_acked end attribute \module_not_derived 1 - attribute \src "libresoc.v:161188.10-161194.4" + attribute \src "libresoc.v:161187.10-161193.4" cell \busy_l \busy_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -334843,7 +331653,7 @@ module \pimem connect \s_busy \busy_l_s_busy end attribute \module_not_derived 1 - attribute \src "libresoc.v:161195.9-161201.4" + attribute \src "libresoc.v:161194.9-161200.4" cell \cyc_l \cyc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -334852,7 +331662,7 @@ module \pimem connect \s_cyc \cyc_l_s_cyc end attribute \module_not_derived 1 - attribute \src "libresoc.v:161202.13-161208.4" + attribute \src "libresoc.v:161201.13-161207.4" cell \ld_active \ld_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -334861,7 +331671,7 @@ module \pimem connect \s_ld_active \ld_active_s_ld_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:161209.10-161214.4" + attribute \src "libresoc.v:161208.10-161213.4" cell \lenexp \lenexp connect \addr_i \lenexp_addr_i connect \len_i \lenexp_len_i @@ -334869,7 +331679,7 @@ module \pimem connect \rexp_o \lenexp_rexp_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:161215.11-161221.4" + attribute \src "libresoc.v:161214.11-161220.4" cell \reset_l \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -334878,7 +331688,7 @@ module \pimem connect \s_reset \reset_l_s_reset end attribute \module_not_derived 1 - attribute \src "libresoc.v:161222.13-161228.4" + attribute \src "libresoc.v:161221.13-161227.4" cell \st_active \st_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -334887,7 +331697,7 @@ module \pimem connect \s_st_active \st_active_s_st_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:161229.11-161235.4" + attribute \src "libresoc.v:161228.11-161234.4" cell \st_done \st_done connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -334896,7 +331706,7 @@ module \pimem connect \s_st_done \st_done_s_st_done end attribute \module_not_derived 1 - attribute \src "libresoc.v:161236.11-161242.4" + attribute \src "libresoc.v:161235.11-161241.4" cell \valid_l \valid_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -334904,143 +331714,143 @@ module \pimem connect \r_valid \valid_l_r_valid connect \s_valid \valid_l_s_valid end - attribute \src "libresoc.v:160878.7-160878.20" - process $proc$libresoc.v:160878$8722 + attribute \src "libresoc.v:160877.7-160877.20" + process $proc$libresoc.v:160877$8722 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160972.7-160972.34" - process $proc$libresoc.v:160972$8723 + attribute \src "libresoc.v:160971.7-160971.34" + process $proc$libresoc.v:160971$8723 assign { } { } assign $1\adrok_l_s_addr_acked[0:0] 1'0 sync always sync init update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:160976.7-160976.24" - process $proc$libresoc.v:160976$8724 + attribute \src "libresoc.v:160975.7-160975.24" + process $proc$libresoc.v:160975$8724 assign { } { } assign $1\busy_delay[0:0] 1'0 sync always sync init update \busy_delay $1\busy_delay[0:0] end - attribute \src "libresoc.v:160998.13-160998.29" - process $proc$libresoc.v:160998$8725 + attribute \src "libresoc.v:160997.13-160997.29" + process $proc$libresoc.v:160997$8725 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:161012.7-161012.21" - process $proc$libresoc.v:161012$8726 + attribute \src "libresoc.v:161011.7-161011.21" + process $proc$libresoc.v:161011$8726 assign { } { } assign $1\lds_dly[0:0] 1'0 sync always sync init update \lds_dly $1\lds_dly[0:0] end - attribute \src "libresoc.v:161055.7-161055.29" - process $proc$libresoc.v:161055$8727 + attribute \src "libresoc.v:161054.7-161054.29" + process $proc$libresoc.v:161054$8727 assign { } { } assign $1\lsui_active_dly[0:0] 1'0 sync always sync init update \lsui_active_dly $1\lsui_active_dly[0:0] end - attribute \src "libresoc.v:161067.7-161067.25" - process $proc$libresoc.v:161067$8728 + attribute \src "libresoc.v:161066.7-161066.25" + process $proc$libresoc.v:161066$8728 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:161087.7-161087.31" - process $proc$libresoc.v:161087$8729 + attribute \src "libresoc.v:161086.7-161086.31" + process $proc$libresoc.v:161086$8729 assign { } { } assign $1\st_done_s_st_done[0:0] 1'0 sync always sync init update \st_done_s_st_done $1\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:161095.7-161095.21" - process $proc$libresoc.v:161095$8730 + attribute \src "libresoc.v:161094.7-161094.21" + process $proc$libresoc.v:161094$8730 assign { } { } assign $1\sts_dly[0:0] 1'0 sync always sync init update \sts_dly $1\sts_dly[0:0] end - attribute \src "libresoc.v:161164.3-161165.47" - process $proc$libresoc.v:161164$8668 + attribute \src "libresoc.v:161163.3-161164.47" + process $proc$libresoc.v:161163$8668 assign { } { } assign $0\lsui_active_dly[0:0] \lsui_active_dly$next sync posedge \coresync_clk update \lsui_active_dly $0\lsui_active_dly[0:0] end - attribute \src "libresoc.v:161166.3-161167.35" - process $proc$libresoc.v:161166$8669 + attribute \src "libresoc.v:161165.3-161166.35" + process $proc$libresoc.v:161165$8669 assign { } { } assign $0\fsm_state[1:0] \fsm_state$next sync posedge \coresync_clk update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:161168.3-161169.36" - process $proc$libresoc.v:161168$8670 + attribute \src "libresoc.v:161167.3-161168.36" + process $proc$libresoc.v:161167$8670 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end - attribute \src "libresoc.v:161170.3-161171.35" - process $proc$libresoc.v:161170$8671 + attribute \src "libresoc.v:161169.3-161170.35" + process $proc$libresoc.v:161169$8671 assign { } { } assign $0\sts_dly[0:0] \ldst_port0_is_st_i sync posedge \coresync_clk update \sts_dly $0\sts_dly[0:0] end - attribute \src "libresoc.v:161172.3-161173.35" - process $proc$libresoc.v:161172$8672 + attribute \src "libresoc.v:161171.3-161172.35" + process $proc$libresoc.v:161171$8672 assign { } { } assign $0\lds_dly[0:0] \ldst_port0_is_ld_i sync posedge \coresync_clk update \lds_dly $0\lds_dly[0:0] end - attribute \src "libresoc.v:161174.3-161175.37" - process $proc$libresoc.v:161174$8673 + attribute \src "libresoc.v:161173.3-161174.37" + process $proc$libresoc.v:161173$8673 assign { } { } assign $0\busy_delay[0:0] \busy_delay$next sync posedge \coresync_clk update \busy_delay $0\busy_delay[0:0] end - attribute \src "libresoc.v:161176.3-161177.57" - process $proc$libresoc.v:161176$8674 + attribute \src "libresoc.v:161175.3-161176.57" + process $proc$libresoc.v:161175$8674 assign { } { } assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next sync posedge \coresync_clk update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:161178.3-161179.51" - process $proc$libresoc.v:161178$8675 + attribute \src "libresoc.v:161177.3-161178.51" + process $proc$libresoc.v:161177$8675 assign { } { } assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next sync posedge \coresync_clk update \st_done_s_st_done $0\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:161243.3-161257.6" - process $proc$libresoc.v:161243$8676 + attribute \src "libresoc.v:161242.3-161256.6" + process $proc$libresoc.v:161242$8676 assign { } { } assign { } { } assign { } { } assign $0\st_done_s_st_done$next[0:0]$8677 $2\st_done_s_st_done$next[0:0]$8679 - attribute \src "libresoc.v:161244.5-161244.29" + attribute \src "libresoc.v:161243.5-161243.29" switch \initial - attribute \src "libresoc.v:161244.9-161244.17" + attribute \src "libresoc.v:161243.9-161243.17" case 1'1 case end @@ -335065,14 +331875,14 @@ module \pimem sync always update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8677 end - attribute \src "libresoc.v:161258.3-161267.6" - process $proc$libresoc.v:161258$8680 + attribute \src "libresoc.v:161257.3-161266.6" + process $proc$libresoc.v:161257$8680 assign { } { } assign { } { } assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:161259.5-161259.29" + attribute \src "libresoc.v:161258.5-161258.29" switch \initial - attribute \src "libresoc.v:161259.9-161259.17" + attribute \src "libresoc.v:161258.9-161258.17" case 1'1 case end @@ -335088,14 +331898,14 @@ module \pimem sync always update \st_done_r_st_done $0\st_done_r_st_done[0:0] end - attribute \src "libresoc.v:161268.3-161276.6" - process $proc$libresoc.v:161268$8681 + attribute \src "libresoc.v:161267.3-161275.6" + process $proc$libresoc.v:161267$8681 assign { } { } assign { } { } assign $0\busy_delay$next[0:0]$8682 $1\busy_delay$next[0:0]$8683 - attribute \src "libresoc.v:161269.5-161269.29" + attribute \src "libresoc.v:161268.5-161268.29" switch \initial - attribute \src "libresoc.v:161269.9-161269.17" + attribute \src "libresoc.v:161268.9-161268.17" case 1'1 case end @@ -335111,14 +331921,14 @@ module \pimem sync always update \busy_delay$next $0\busy_delay$next[0:0]$8682 end - attribute \src "libresoc.v:161277.3-161286.6" - process $proc$libresoc.v:161277$8684 + attribute \src "libresoc.v:161276.3-161285.6" + process $proc$libresoc.v:161276$8684 assign { } { } assign { } { } assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:161278.5-161278.29" + attribute \src "libresoc.v:161277.5-161277.29" switch \initial - attribute \src "libresoc.v:161278.9-161278.17" + attribute \src "libresoc.v:161277.9-161277.17" case 1'1 case end @@ -335134,15 +331944,15 @@ module \pimem sync always update \st_active_r_st_active $0\st_active_r_st_active[0:0] end - attribute \src "libresoc.v:161287.3-161302.6" - process $proc$libresoc.v:161287$8685 + attribute \src "libresoc.v:161286.3-161301.6" + process $proc$libresoc.v:161286$8685 assign { } { } assign { } { } assign { } { } assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:161288.5-161288.29" + attribute \src "libresoc.v:161287.5-161287.29" switch \initial - attribute \src "libresoc.v:161288.9-161288.17" + attribute \src "libresoc.v:161287.9-161287.17" case 1'1 case end @@ -335167,15 +331977,15 @@ module \pimem sync always update \lenexp_len_i $0\lenexp_len_i[3:0] end - attribute \src "libresoc.v:161303.3-161318.6" - process $proc$libresoc.v:161303$8686 + attribute \src "libresoc.v:161302.3-161317.6" + process $proc$libresoc.v:161302$8686 assign { } { } assign { } { } assign { } { } assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:161304.5-161304.29" + attribute \src "libresoc.v:161303.5-161303.29" switch \initial - attribute \src "libresoc.v:161304.9-161304.17" + attribute \src "libresoc.v:161303.9-161303.17" case 1'1 case end @@ -335200,15 +332010,15 @@ module \pimem sync always update \lenexp_addr_i $0\lenexp_addr_i[3:0] end - attribute \src "libresoc.v:161319.3-161344.6" - process $proc$libresoc.v:161319$8687 + attribute \src "libresoc.v:161318.3-161343.6" + process $proc$libresoc.v:161318$8687 assign { } { } assign { } { } assign { } { } assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161320.5-161320.29" + attribute \src "libresoc.v:161319.5-161319.29" switch \initial - attribute \src "libresoc.v:161320.9-161320.17" + attribute \src "libresoc.v:161319.9-161319.17" case 1'1 case end @@ -335251,15 +332061,15 @@ module \pimem sync always update \valid_l_s_valid $0\valid_l_s_valid[0:0] end - attribute \src "libresoc.v:161345.3-161370.6" - process $proc$libresoc.v:161345$8688 + attribute \src "libresoc.v:161344.3-161369.6" + process $proc$libresoc.v:161344$8688 assign { } { } assign { } { } assign { } { } assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] - attribute \src "libresoc.v:161346.5-161346.29" + attribute \src "libresoc.v:161345.5-161345.29" switch \initial - attribute \src "libresoc.v:161346.9-161346.17" + attribute \src "libresoc.v:161345.9-161345.17" case 1'1 case end @@ -335302,15 +332112,15 @@ module \pimem sync always update \x_mask_i $0\x_mask_i[7:0] end - attribute \src "libresoc.v:161371.3-161396.6" - process $proc$libresoc.v:161371$8689 + attribute \src "libresoc.v:161370.3-161395.6" + process $proc$libresoc.v:161370$8689 assign { } { } assign { } { } assign { } { } assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] - attribute \src "libresoc.v:161372.5-161372.29" + attribute \src "libresoc.v:161371.5-161371.29" switch \initial - attribute \src "libresoc.v:161372.9-161372.17" + attribute \src "libresoc.v:161371.9-161371.17" case 1'1 case end @@ -335353,15 +332163,15 @@ module \pimem sync always update \x_addr_i $0\x_addr_i[47:0] end - attribute \src "libresoc.v:161397.3-161427.6" - process $proc$libresoc.v:161397$8690 + attribute \src "libresoc.v:161396.3-161426.6" + process $proc$libresoc.v:161396$8690 assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161398.5-161398.29" + attribute \src "libresoc.v:161397.5-161397.29" switch \initial - attribute \src "libresoc.v:161398.9-161398.17" + attribute \src "libresoc.v:161397.9-161397.17" case 1'1 case end @@ -335413,15 +332223,15 @@ module \pimem sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:161428.3-161443.6" - process $proc$libresoc.v:161428$8691 + attribute \src "libresoc.v:161427.3-161442.6" + process $proc$libresoc.v:161427$8691 assign { } { } assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:161429.5-161429.29" + attribute \src "libresoc.v:161428.5-161428.29" switch \initial - attribute \src "libresoc.v:161429.9-161429.17" + attribute \src "libresoc.v:161428.9-161428.17" case 1'1 case end @@ -335446,14 +332256,14 @@ module \pimem sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:161444.3-161453.6" - process $proc$libresoc.v:161444$8692 + attribute \src "libresoc.v:161443.3-161452.6" + process $proc$libresoc.v:161443$8692 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:161445.5-161445.29" + attribute \src "libresoc.v:161444.5-161444.29" switch \initial - attribute \src "libresoc.v:161445.9-161445.17" + attribute \src "libresoc.v:161444.9-161444.17" case 1'1 case end @@ -335469,14 +332279,14 @@ module \pimem sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:161454.3-161463.6" - process $proc$libresoc.v:161454$8693 + attribute \src "libresoc.v:161453.3-161462.6" + process $proc$libresoc.v:161453$8693 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:161455.5-161455.29" + attribute \src "libresoc.v:161454.5-161454.29" switch \initial - attribute \src "libresoc.v:161455.9-161455.17" + attribute \src "libresoc.v:161454.9-161454.17" case 1'1 case end @@ -335492,14 +332302,14 @@ module \pimem sync always update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] end - attribute \src "libresoc.v:161464.3-161473.6" - process $proc$libresoc.v:161464$8694 + attribute \src "libresoc.v:161463.3-161472.6" + process $proc$libresoc.v:161463$8694 assign { } { } assign { } { } assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:161465.5-161465.29" + attribute \src "libresoc.v:161464.5-161464.29" switch \initial - attribute \src "libresoc.v:161465.9-161465.17" + attribute \src "libresoc.v:161464.9-161464.17" case 1'1 case end @@ -335515,14 +332325,14 @@ module \pimem sync always update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] end - attribute \src "libresoc.v:161474.3-161483.6" - process $proc$libresoc.v:161474$8695 + attribute \src "libresoc.v:161473.3-161482.6" + process $proc$libresoc.v:161473$8695 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:161475.5-161475.29" + attribute \src "libresoc.v:161474.5-161474.29" switch \initial - attribute \src "libresoc.v:161475.9-161475.17" + attribute \src "libresoc.v:161474.9-161474.17" case 1'1 case end @@ -335538,14 +332348,14 @@ module \pimem sync always update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:161484.3-161493.6" - process $proc$libresoc.v:161484$8696 + attribute \src "libresoc.v:161483.3-161492.6" + process $proc$libresoc.v:161483$8696 assign { } { } assign { } { } assign $0\stdata[63:0] $1\stdata[63:0] - attribute \src "libresoc.v:161485.5-161485.29" + attribute \src "libresoc.v:161484.5-161484.29" switch \initial - attribute \src "libresoc.v:161485.9-161485.17" + attribute \src "libresoc.v:161484.9-161484.17" case 1'1 case end @@ -335561,14 +332371,14 @@ module \pimem sync always update \stdata $0\stdata[63:0] end - attribute \src "libresoc.v:161494.3-161503.6" - process $proc$libresoc.v:161494$8697 + attribute \src "libresoc.v:161493.3-161502.6" + process $proc$libresoc.v:161493$8697 assign { } { } assign { } { } assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] - attribute \src "libresoc.v:161495.5-161495.29" + attribute \src "libresoc.v:161494.5-161494.29" switch \initial - attribute \src "libresoc.v:161495.9-161495.17" + attribute \src "libresoc.v:161494.9-161494.17" case 1'1 case end @@ -335584,14 +332394,14 @@ module \pimem sync always update \x_st_data_i $0\x_st_data_i[63:0] end - attribute \src "libresoc.v:161504.3-161523.6" - process $proc$libresoc.v:161504$8698 + attribute \src "libresoc.v:161503.3-161522.6" + process $proc$libresoc.v:161503$8698 assign { } { } assign { } { } assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] - attribute \src "libresoc.v:161505.5-161505.29" + attribute \src "libresoc.v:161504.5-161504.29" switch \initial - attribute \src "libresoc.v:161505.9-161505.17" + attribute \src "libresoc.v:161504.9-161504.17" case 1'1 case end @@ -335620,15 +332430,15 @@ module \pimem sync always update \lsui_busy $0\lsui_busy[0:0] end - attribute \src "libresoc.v:161524.3-161562.6" - process $proc$libresoc.v:161524$8699 + attribute \src "libresoc.v:161523.3-161561.6" + process $proc$libresoc.v:161523$8699 assign { } { } assign { } { } assign { } { } assign $0\fsm_state$next[1:0]$8700 $5\fsm_state$next[1:0]$8705 - attribute \src "libresoc.v:161525.5-161525.29" + attribute \src "libresoc.v:161524.5-161524.29" switch \initial - attribute \src "libresoc.v:161525.9-161525.17" + attribute \src "libresoc.v:161524.9-161524.17" case 1'1 case end @@ -335688,14 +332498,14 @@ module \pimem sync always update \fsm_state$next $0\fsm_state$next[1:0]$8700 end - attribute \src "libresoc.v:161563.3-161572.6" - process $proc$libresoc.v:161563$8706 + attribute \src "libresoc.v:161562.3-161571.6" + process $proc$libresoc.v:161562$8706 assign { } { } assign { } { } assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:161564.5-161564.29" + attribute \src "libresoc.v:161563.5-161563.29" switch \initial - attribute \src "libresoc.v:161564.9-161564.17" + attribute \src "libresoc.v:161563.9-161563.17" case 1'1 case end @@ -335711,14 +332521,14 @@ module \pimem sync always update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] end - attribute \src "libresoc.v:161573.3-161581.6" - process $proc$libresoc.v:161573$8707 + attribute \src "libresoc.v:161572.3-161580.6" + process $proc$libresoc.v:161572$8707 assign { } { } assign { } { } assign $0\lsui_active_dly$next[0:0]$8708 $1\lsui_active_dly$next[0:0]$8709 - attribute \src "libresoc.v:161574.5-161574.29" + attribute \src "libresoc.v:161573.5-161573.29" switch \initial - attribute \src "libresoc.v:161574.9-161574.17" + attribute \src "libresoc.v:161573.9-161573.17" case 1'1 case end @@ -335734,14 +332544,14 @@ module \pimem sync always update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8708 end - attribute \src "libresoc.v:161582.3-161591.6" - process $proc$libresoc.v:161582$8710 + attribute \src "libresoc.v:161581.3-161590.6" + process $proc$libresoc.v:161581$8710 assign { } { } assign { } { } assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:161583.5-161583.29" + attribute \src "libresoc.v:161582.5-161582.29" switch \initial - attribute \src "libresoc.v:161583.9-161583.17" + attribute \src "libresoc.v:161582.9-161582.17" case 1'1 case end @@ -335757,14 +332567,14 @@ module \pimem sync always update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] end - attribute \src "libresoc.v:161592.3-161601.6" - process $proc$libresoc.v:161592$8711 + attribute \src "libresoc.v:161591.3-161600.6" + process $proc$libresoc.v:161591$8711 assign { } { } assign { } { } assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:161593.5-161593.29" + attribute \src "libresoc.v:161592.5-161592.29" switch \initial - attribute \src "libresoc.v:161593.9-161593.17" + attribute \src "libresoc.v:161592.9-161592.17" case 1'1 case end @@ -335780,15 +332590,15 @@ module \pimem sync always update \busy_l_s_busy $0\busy_l_s_busy[0:0] end - attribute \src "libresoc.v:161602.3-161617.6" - process $proc$libresoc.v:161602$8712 + attribute \src "libresoc.v:161601.3-161616.6" + process $proc$libresoc.v:161601$8712 assign { } { } assign { } { } assign { } { } assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:161603.5-161603.29" + attribute \src "libresoc.v:161602.5-161602.29" switch \initial - attribute \src "libresoc.v:161603.9-161603.17" + attribute \src "libresoc.v:161602.9-161602.17" case 1'1 case end @@ -335813,16 +332623,16 @@ module \pimem sync always update \busy_l_r_busy $0\busy_l_r_busy[0:0] end - attribute \src "libresoc.v:161618.3-161653.6" - process $proc$libresoc.v:161618$8713 + attribute \src "libresoc.v:161617.3-161652.6" + process $proc$libresoc.v:161617$8713 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\adrok_l_s_addr_acked$next[0:0]$8714 $6\adrok_l_s_addr_acked$next[0:0]$8720 - attribute \src "libresoc.v:161619.5-161619.29" + attribute \src "libresoc.v:161618.5-161618.29" switch \initial - attribute \src "libresoc.v:161619.9-161619.17" + attribute \src "libresoc.v:161618.9-161618.17" case 1'1 case end @@ -335883,15 +332693,15 @@ module \pimem sync always update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8714 end - attribute \src "libresoc.v:161654.3-161669.6" - process $proc$libresoc.v:161654$8721 + attribute \src "libresoc.v:161653.3-161668.6" + process $proc$libresoc.v:161653$8721 assign { } { } assign { } { } assign { } { } assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:161655.5-161655.29" + attribute \src "libresoc.v:161654.5-161654.29" switch \initial - attribute \src "libresoc.v:161655.9-161655.17" + attribute \src "libresoc.v:161654.9-161654.17" case 1'1 case end @@ -335916,47 +332726,47 @@ module \pimem sync always update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] end - connect \$9 $not$libresoc.v:161123$8625_Y - connect \$11 $and$libresoc.v:161124$8626_Y - connect \$13 $not$libresoc.v:161125$8627_Y - connect \$15 $and$libresoc.v:161126$8628_Y - connect \$17 $not$libresoc.v:161127$8629_Y - connect \$1 $and$libresoc.v:161128$8630_Y - connect \$19 $and$libresoc.v:161129$8631_Y - connect \$21 $pos$libresoc.v:161130$8633_Y - connect \$23 $pos$libresoc.v:161131$8635_Y - connect \$25 $and$libresoc.v:161132$8636_Y - connect \$27 $and$libresoc.v:161133$8637_Y - connect \$29 $and$libresoc.v:161134$8638_Y - connect \$31 $and$libresoc.v:161135$8639_Y - connect \$33 $and$libresoc.v:161136$8640_Y - connect \$35 $not$libresoc.v:161137$8641_Y - connect \$38 $or$libresoc.v:161138$8642_Y - connect \$3 $or$libresoc.v:161139$8643_Y - connect \$37 $not$libresoc.v:161140$8644_Y - connect \$42 $and$libresoc.v:161141$8645_Y - connect \$44 $mul$libresoc.v:161142$8646_Y - connect \$46 $sshr$libresoc.v:161143$8647_Y - connect \$48 $and$libresoc.v:161144$8648_Y - connect \$50 $and$libresoc.v:161145$8649_Y - connect \$52 $not$libresoc.v:161146$8650_Y - connect \$54 $and$libresoc.v:161147$8651_Y - connect \$57 $mul$libresoc.v:161148$8652_Y - connect \$5 $not$libresoc.v:161149$8653_Y - connect \$59 $sshl$libresoc.v:161150$8654_Y - connect \$61 $and$libresoc.v:161151$8655_Y - connect \$63 $or$libresoc.v:161152$8656_Y - connect \$65 $and$libresoc.v:161153$8657_Y - connect \$67 $or$libresoc.v:161154$8658_Y - connect \$69 $and$libresoc.v:161155$8659_Y - connect \$71 $not$libresoc.v:161156$8660_Y - connect \$73 $not$libresoc.v:161157$8661_Y - connect \$75 $not$libresoc.v:161158$8662_Y - connect \$77 $and$libresoc.v:161159$8663_Y - connect \$7 $and$libresoc.v:161160$8664_Y - connect \$79 $not$libresoc.v:161161$8665_Y - connect \$81 $not$libresoc.v:161162$8666_Y - connect \$83 $and$libresoc.v:161163$8667_Y + connect \$9 $not$libresoc.v:161122$8625_Y + connect \$11 $and$libresoc.v:161123$8626_Y + connect \$13 $not$libresoc.v:161124$8627_Y + connect \$15 $and$libresoc.v:161125$8628_Y + connect \$17 $not$libresoc.v:161126$8629_Y + connect \$1 $and$libresoc.v:161127$8630_Y + connect \$19 $and$libresoc.v:161128$8631_Y + connect \$21 $pos$libresoc.v:161129$8633_Y + connect \$23 $pos$libresoc.v:161130$8635_Y + connect \$25 $and$libresoc.v:161131$8636_Y + connect \$27 $and$libresoc.v:161132$8637_Y + connect \$29 $and$libresoc.v:161133$8638_Y + connect \$31 $and$libresoc.v:161134$8639_Y + connect \$33 $and$libresoc.v:161135$8640_Y + connect \$35 $not$libresoc.v:161136$8641_Y + connect \$38 $or$libresoc.v:161137$8642_Y + connect \$3 $or$libresoc.v:161138$8643_Y + connect \$37 $not$libresoc.v:161139$8644_Y + connect \$42 $and$libresoc.v:161140$8645_Y + connect \$44 $mul$libresoc.v:161141$8646_Y + connect \$46 $sshr$libresoc.v:161142$8647_Y + connect \$48 $and$libresoc.v:161143$8648_Y + connect \$50 $and$libresoc.v:161144$8649_Y + connect \$52 $not$libresoc.v:161145$8650_Y + connect \$54 $and$libresoc.v:161146$8651_Y + connect \$57 $mul$libresoc.v:161147$8652_Y + connect \$5 $not$libresoc.v:161148$8653_Y + connect \$59 $sshl$libresoc.v:161149$8654_Y + connect \$61 $and$libresoc.v:161150$8655_Y + connect \$63 $or$libresoc.v:161151$8656_Y + connect \$65 $and$libresoc.v:161152$8657_Y + connect \$67 $or$libresoc.v:161153$8658_Y + connect \$69 $and$libresoc.v:161154$8659_Y + connect \$71 $not$libresoc.v:161155$8660_Y + connect \$73 $not$libresoc.v:161156$8661_Y + connect \$75 $not$libresoc.v:161157$8662_Y + connect \$77 $and$libresoc.v:161158$8663_Y + connect \$7 $and$libresoc.v:161159$8664_Y + connect \$79 $not$libresoc.v:161160$8665_Y + connect \$81 $not$libresoc.v:161161$8666_Y + connect \$83 $and$libresoc.v:161162$8667_Y connect \$41 \$46 connect \$56 \$59 connect \valid_l_r_valid \lsui_active_rise @@ -335979,111 +332789,111 @@ module \pimem connect \sts \ldst_port0_is_st_i connect \lds \ldst_port0_is_ld_i end -attribute \src "libresoc.v:161695.1-162475.10" +attribute \src "libresoc.v:161694.1-162474.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" attribute \generator "nMigen" module \pipe - attribute \src "libresoc.v:162438.3-162456.6" + attribute \src "libresoc.v:162437.3-162455.6" wire width 4 $0\cr_a$6$next[3:0]$8777 - attribute \src "libresoc.v:162302.3-162303.31" + attribute \src "libresoc.v:162301.3-162302.31" wire width 4 $0\cr_a$6[3:0]$8733 - attribute \src "libresoc.v:161709.13-161709.28" + attribute \src "libresoc.v:161708.13-161708.28" wire width 4 $0\cr_a$6[3:0]$8783 - attribute \src "libresoc.v:162438.3-162456.6" + attribute \src "libresoc.v:162437.3-162455.6" wire $0\cr_a_ok$next[0:0]$8776 - attribute \src "libresoc.v:162304.3-162305.31" + attribute \src "libresoc.v:162303.3-162304.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:162385.3-162399.6" + attribute \src "libresoc.v:162384.3-162398.6" wire width 14 $0\cr_op__fn_unit$3$next[13:0]$8757 - attribute \src "libresoc.v:162316.3-162317.51" + attribute \src "libresoc.v:162315.3-162316.51" wire width 14 $0\cr_op__fn_unit$3[13:0]$8743 - attribute \src "libresoc.v:161774.14-161774.43" + attribute \src "libresoc.v:161773.14-161773.43" wire width 14 $0\cr_op__fn_unit$3[13:0]$8786 - attribute \src "libresoc.v:162385.3-162399.6" + attribute \src "libresoc.v:162384.3-162398.6" wire width 32 $0\cr_op__insn$4$next[31:0]$8758 - attribute \src "libresoc.v:162318.3-162319.45" + attribute \src "libresoc.v:162317.3-162318.45" wire width 32 $0\cr_op__insn$4[31:0]$8745 - attribute \src "libresoc.v:161783.14-161783.37" + attribute \src "libresoc.v:161782.14-161782.37" wire width 32 $0\cr_op__insn$4[31:0]$8788 - attribute \src "libresoc.v:162385.3-162399.6" + attribute \src "libresoc.v:162384.3-162398.6" wire width 7 $0\cr_op__insn_type$2$next[6:0]$8759 - attribute \src "libresoc.v:162314.3-162315.55" + attribute \src "libresoc.v:162313.3-162314.55" wire width 7 $0\cr_op__insn_type$2[6:0]$8741 - attribute \src "libresoc.v:162017.13-162017.41" + attribute \src "libresoc.v:162016.13-162016.41" wire width 7 $0\cr_op__insn_type$2[6:0]$8790 - attribute \src "libresoc.v:162419.3-162437.6" + attribute \src "libresoc.v:162418.3-162436.6" wire width 32 $0\full_cr$5$next[31:0]$8770 - attribute \src "libresoc.v:162306.3-162307.37" + attribute \src "libresoc.v:162305.3-162306.37" wire width 32 $0\full_cr$5[31:0]$8736 - attribute \src "libresoc.v:162026.14-162026.33" + attribute \src "libresoc.v:162025.14-162025.33" wire width 32 $0\full_cr$5[31:0]$8792 - attribute \src "libresoc.v:162419.3-162437.6" + attribute \src "libresoc.v:162418.3-162436.6" wire $0\full_cr_ok$next[0:0]$8771 - attribute \src "libresoc.v:162308.3-162309.37" + attribute \src "libresoc.v:162307.3-162308.37" wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:161696.7-161696.20" + attribute \src "libresoc.v:161695.7-161695.20" wire $0\initial[0:0] - attribute \src "libresoc.v:162372.3-162384.6" + attribute \src "libresoc.v:162371.3-162383.6" wire width 2 $0\muxid$1$next[1:0]$8754 - attribute \src "libresoc.v:162320.3-162321.33" + attribute \src "libresoc.v:162319.3-162320.33" wire width 2 $0\muxid$1[1:0]$8747 - attribute \src "libresoc.v:162260.13-162260.29" + attribute \src "libresoc.v:162259.13-162259.29" wire width 2 $0\muxid$1[1:0]$8795 - attribute \src "libresoc.v:162400.3-162418.6" + attribute \src "libresoc.v:162399.3-162417.6" wire width 64 $0\o$next[63:0]$8764 - attribute \src "libresoc.v:162310.3-162311.19" + attribute \src "libresoc.v:162309.3-162310.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:162400.3-162418.6" + attribute \src "libresoc.v:162399.3-162417.6" wire $0\o_ok$next[0:0]$8765 - attribute \src "libresoc.v:162312.3-162313.25" + attribute \src "libresoc.v:162311.3-162312.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:162354.3-162371.6" + attribute \src "libresoc.v:162353.3-162370.6" wire $0\r_busy$next[0:0]$8750 - attribute \src "libresoc.v:162322.3-162323.29" + attribute \src "libresoc.v:162321.3-162322.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:162438.3-162456.6" + attribute \src "libresoc.v:162437.3-162455.6" wire width 4 $1\cr_a$6$next[3:0]$8779 - attribute \src "libresoc.v:162438.3-162456.6" + attribute \src "libresoc.v:162437.3-162455.6" wire $1\cr_a_ok$next[0:0]$8778 - attribute \src "libresoc.v:161714.7-161714.21" + attribute \src "libresoc.v:161713.7-161713.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:162385.3-162399.6" + attribute \src "libresoc.v:162384.3-162398.6" wire width 14 $1\cr_op__fn_unit$3$next[13:0]$8760 - attribute \src "libresoc.v:162385.3-162399.6" + attribute \src "libresoc.v:162384.3-162398.6" wire width 32 $1\cr_op__insn$4$next[31:0]$8761 - attribute \src "libresoc.v:162385.3-162399.6" + attribute \src "libresoc.v:162384.3-162398.6" wire width 7 $1\cr_op__insn_type$2$next[6:0]$8762 - attribute \src "libresoc.v:162419.3-162437.6" + attribute \src "libresoc.v:162418.3-162436.6" wire width 32 $1\full_cr$5$next[31:0]$8772 - attribute \src "libresoc.v:162419.3-162437.6" + attribute \src "libresoc.v:162418.3-162436.6" wire $1\full_cr_ok$next[0:0]$8773 - attribute \src "libresoc.v:162031.7-162031.24" + attribute \src "libresoc.v:162030.7-162030.24" wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:162372.3-162384.6" + attribute \src "libresoc.v:162371.3-162383.6" wire width 2 $1\muxid$1$next[1:0]$8755 - attribute \src "libresoc.v:162400.3-162418.6" + attribute \src "libresoc.v:162399.3-162417.6" wire width 64 $1\o$next[63:0]$8766 - attribute \src "libresoc.v:162273.14-162273.38" + attribute \src "libresoc.v:162272.14-162272.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:162400.3-162418.6" + attribute \src "libresoc.v:162399.3-162417.6" wire $1\o_ok$next[0:0]$8767 - attribute \src "libresoc.v:162280.7-162280.18" + attribute \src "libresoc.v:162279.7-162279.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:162354.3-162371.6" + attribute \src "libresoc.v:162353.3-162370.6" wire $1\r_busy$next[0:0]$8751 - attribute \src "libresoc.v:162294.7-162294.20" + attribute \src "libresoc.v:162293.7-162293.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:162438.3-162456.6" + attribute \src "libresoc.v:162437.3-162455.6" wire $2\cr_a_ok$next[0:0]$8780 - attribute \src "libresoc.v:162419.3-162437.6" + attribute \src "libresoc.v:162418.3-162436.6" wire $2\full_cr_ok$next[0:0]$8774 - attribute \src "libresoc.v:162400.3-162418.6" + attribute \src "libresoc.v:162399.3-162417.6" wire $2\o_ok$next[0:0]$8768 - attribute \src "libresoc.v:162354.3-162371.6" + attribute \src "libresoc.v:162353.3-162370.6" wire $2\r_busy$next[0:0]$8752 - attribute \src "libresoc.v:162301.18-162301.118" - wire $and$libresoc.v:162301$8731_Y + attribute \src "libresoc.v:162300.18-162300.118" + wire $and$libresoc.v:162300$8731_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" @@ -336416,7 +333226,7 @@ module \pipe wire \full_cr_ok$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \full_cr_ok$next - attribute \src "libresoc.v:161696.7-161696.15" + attribute \src "libresoc.v:161695.7-161695.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \main_cr_a @@ -336681,7 +333491,7 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 9 \rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:162301$8731 + cell $and $and$libresoc.v:162300$8731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -336689,10 +333499,10 @@ module \pipe parameter \Y_WIDTH 1 connect \A \p_valid_i$13 connect \B \p_ready_o - connect \Y $and$libresoc.v:162301$8731_Y + connect \Y $and$libresoc.v:162300$8731_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:162324.12-162345.4" + attribute \src "libresoc.v:162323.12-162344.4" cell \main$9 \main connect \cr_a \main_cr_a connect \cr_a$6 \main_cr_a$12 @@ -336716,199 +333526,199 @@ module \pipe connect \rb \main_rb end attribute \module_not_derived 1 - attribute \src "libresoc.v:162346.9-162349.4" + attribute \src "libresoc.v:162345.9-162348.4" cell \n$8 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:162350.9-162353.4" + attribute \src "libresoc.v:162349.9-162352.4" cell \p$7 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:161696.7-161696.20" - process $proc$libresoc.v:161696$8781 + attribute \src "libresoc.v:161695.7-161695.20" + process $proc$libresoc.v:161695$8781 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:161709.13-161709.28" - process $proc$libresoc.v:161709$8782 + attribute \src "libresoc.v:161708.13-161708.28" + process $proc$libresoc.v:161708$8782 assign { } { } assign $0\cr_a$6[3:0]$8783 4'0000 sync always sync init update \cr_a$6 $0\cr_a$6[3:0]$8783 end - attribute \src "libresoc.v:161714.7-161714.21" - process $proc$libresoc.v:161714$8784 + attribute \src "libresoc.v:161713.7-161713.21" + process $proc$libresoc.v:161713$8784 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:161774.14-161774.43" - process $proc$libresoc.v:161774$8785 + attribute \src "libresoc.v:161773.14-161773.43" + process $proc$libresoc.v:161773$8785 assign { } { } assign $0\cr_op__fn_unit$3[13:0]$8786 14'00000000000000 sync always sync init update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8786 end - attribute \src "libresoc.v:161783.14-161783.37" - process $proc$libresoc.v:161783$8787 + attribute \src "libresoc.v:161782.14-161782.37" + process $proc$libresoc.v:161782$8787 assign { } { } assign $0\cr_op__insn$4[31:0]$8788 0 sync always sync init update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8788 end - attribute \src "libresoc.v:162017.13-162017.41" - process $proc$libresoc.v:162017$8789 + attribute \src "libresoc.v:162016.13-162016.41" + process $proc$libresoc.v:162016$8789 assign { } { } assign $0\cr_op__insn_type$2[6:0]$8790 7'0000000 sync always sync init update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8790 end - attribute \src "libresoc.v:162026.14-162026.33" - process $proc$libresoc.v:162026$8791 + attribute \src "libresoc.v:162025.14-162025.33" + process $proc$libresoc.v:162025$8791 assign { } { } assign $0\full_cr$5[31:0]$8792 0 sync always sync init update \full_cr$5 $0\full_cr$5[31:0]$8792 end - attribute \src "libresoc.v:162031.7-162031.24" - process $proc$libresoc.v:162031$8793 + attribute \src "libresoc.v:162030.7-162030.24" + process $proc$libresoc.v:162030$8793 assign { } { } assign $1\full_cr_ok[0:0] 1'0 sync always sync init update \full_cr_ok $1\full_cr_ok[0:0] end - attribute \src "libresoc.v:162260.13-162260.29" - process $proc$libresoc.v:162260$8794 + attribute \src "libresoc.v:162259.13-162259.29" + process $proc$libresoc.v:162259$8794 assign { } { } assign $0\muxid$1[1:0]$8795 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$8795 end - attribute \src "libresoc.v:162273.14-162273.38" - process $proc$libresoc.v:162273$8796 + attribute \src "libresoc.v:162272.14-162272.38" + process $proc$libresoc.v:162272$8796 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:162280.7-162280.18" - process $proc$libresoc.v:162280$8797 + attribute \src "libresoc.v:162279.7-162279.18" + process $proc$libresoc.v:162279$8797 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:162294.7-162294.20" - process $proc$libresoc.v:162294$8798 + attribute \src "libresoc.v:162293.7-162293.20" + process $proc$libresoc.v:162293$8798 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:162302.3-162303.31" - process $proc$libresoc.v:162302$8732 + attribute \src "libresoc.v:162301.3-162302.31" + process $proc$libresoc.v:162301$8732 assign { } { } assign $0\cr_a$6[3:0]$8733 \cr_a$6$next sync posedge \coresync_clk update \cr_a$6 $0\cr_a$6[3:0]$8733 end - attribute \src "libresoc.v:162304.3-162305.31" - process $proc$libresoc.v:162304$8734 + attribute \src "libresoc.v:162303.3-162304.31" + process $proc$libresoc.v:162303$8734 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:162306.3-162307.37" - process $proc$libresoc.v:162306$8735 + attribute \src "libresoc.v:162305.3-162306.37" + process $proc$libresoc.v:162305$8735 assign { } { } assign $0\full_cr$5[31:0]$8736 \full_cr$5$next sync posedge \coresync_clk update \full_cr$5 $0\full_cr$5[31:0]$8736 end - attribute \src "libresoc.v:162308.3-162309.37" - process $proc$libresoc.v:162308$8737 + attribute \src "libresoc.v:162307.3-162308.37" + process $proc$libresoc.v:162307$8737 assign { } { } assign $0\full_cr_ok[0:0] \full_cr_ok$next sync posedge \coresync_clk update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:162310.3-162311.19" - process $proc$libresoc.v:162310$8738 + attribute \src "libresoc.v:162309.3-162310.19" + process $proc$libresoc.v:162309$8738 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:162312.3-162313.25" - process $proc$libresoc.v:162312$8739 + attribute \src "libresoc.v:162311.3-162312.25" + process $proc$libresoc.v:162311$8739 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:162314.3-162315.55" - process $proc$libresoc.v:162314$8740 + attribute \src "libresoc.v:162313.3-162314.55" + process $proc$libresoc.v:162313$8740 assign { } { } assign $0\cr_op__insn_type$2[6:0]$8741 \cr_op__insn_type$2$next sync posedge \coresync_clk update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8741 end - attribute \src "libresoc.v:162316.3-162317.51" - process $proc$libresoc.v:162316$8742 + attribute \src "libresoc.v:162315.3-162316.51" + process $proc$libresoc.v:162315$8742 assign { } { } assign $0\cr_op__fn_unit$3[13:0]$8743 \cr_op__fn_unit$3$next sync posedge \coresync_clk update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8743 end - attribute \src "libresoc.v:162318.3-162319.45" - process $proc$libresoc.v:162318$8744 + attribute \src "libresoc.v:162317.3-162318.45" + process $proc$libresoc.v:162317$8744 assign { } { } assign $0\cr_op__insn$4[31:0]$8745 \cr_op__insn$4$next sync posedge \coresync_clk update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8745 end - attribute \src "libresoc.v:162320.3-162321.33" - process $proc$libresoc.v:162320$8746 + attribute \src "libresoc.v:162319.3-162320.33" + process $proc$libresoc.v:162319$8746 assign { } { } assign $0\muxid$1[1:0]$8747 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$8747 end - attribute \src "libresoc.v:162322.3-162323.29" - process $proc$libresoc.v:162322$8748 + attribute \src "libresoc.v:162321.3-162322.29" + process $proc$libresoc.v:162321$8748 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:162354.3-162371.6" - process $proc$libresoc.v:162354$8749 + attribute \src "libresoc.v:162353.3-162370.6" + process $proc$libresoc.v:162353$8749 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$8750 $2\r_busy$next[0:0]$8752 - attribute \src "libresoc.v:162355.5-162355.29" + attribute \src "libresoc.v:162354.5-162354.29" switch \initial - attribute \src "libresoc.v:162355.9-162355.17" + attribute \src "libresoc.v:162354.9-162354.17" case 1'1 case end @@ -336937,14 +333747,14 @@ module \pipe sync always update \r_busy$next $0\r_busy$next[0:0]$8750 end - attribute \src "libresoc.v:162372.3-162384.6" - process $proc$libresoc.v:162372$8753 + attribute \src "libresoc.v:162371.3-162383.6" + process $proc$libresoc.v:162371$8753 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$8754 $1\muxid$1$next[1:0]$8755 - attribute \src "libresoc.v:162373.5-162373.29" + attribute \src "libresoc.v:162372.5-162372.29" switch \initial - attribute \src "libresoc.v:162373.9-162373.17" + attribute \src "libresoc.v:162372.9-162372.17" case 1'1 case end @@ -336964,8 +333774,8 @@ module \pipe sync always update \muxid$1$next $0\muxid$1$next[1:0]$8754 end - attribute \src "libresoc.v:162385.3-162399.6" - process $proc$libresoc.v:162385$8756 + attribute \src "libresoc.v:162384.3-162398.6" + process $proc$libresoc.v:162384$8756 assign { } { } assign { } { } assign { } { } @@ -336975,9 +333785,9 @@ module \pipe assign $0\cr_op__fn_unit$3$next[13:0]$8757 $1\cr_op__fn_unit$3$next[13:0]$8760 assign $0\cr_op__insn$4$next[31:0]$8758 $1\cr_op__insn$4$next[31:0]$8761 assign $0\cr_op__insn_type$2$next[6:0]$8759 $1\cr_op__insn_type$2$next[6:0]$8762 - attribute \src "libresoc.v:162386.5-162386.29" + attribute \src "libresoc.v:162385.5-162385.29" switch \initial - attribute \src "libresoc.v:162386.9-162386.17" + attribute \src "libresoc.v:162385.9-162385.17" case 1'1 case end @@ -337005,8 +333815,8 @@ module \pipe update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8758 update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8759 end - attribute \src "libresoc.v:162400.3-162418.6" - process $proc$libresoc.v:162400$8763 + attribute \src "libresoc.v:162399.3-162417.6" + process $proc$libresoc.v:162399$8763 assign { } { } assign { } { } assign { } { } @@ -337014,9 +333824,9 @@ module \pipe assign $0\o$next[63:0]$8764 $1\o$next[63:0]$8766 assign { } { } assign $0\o_ok$next[0:0]$8765 $2\o_ok$next[0:0]$8768 - attribute \src "libresoc.v:162401.5-162401.29" + attribute \src "libresoc.v:162400.5-162400.29" switch \initial - attribute \src "libresoc.v:162401.9-162401.17" + attribute \src "libresoc.v:162400.9-162400.17" case 1'1 case end @@ -337049,8 +333859,8 @@ module \pipe update \o$next $0\o$next[63:0]$8764 update \o_ok$next $0\o_ok$next[0:0]$8765 end - attribute \src "libresoc.v:162419.3-162437.6" - process $proc$libresoc.v:162419$8769 + attribute \src "libresoc.v:162418.3-162436.6" + process $proc$libresoc.v:162418$8769 assign { } { } assign { } { } assign { } { } @@ -337058,9 +333868,9 @@ module \pipe assign $0\full_cr$5$next[31:0]$8770 $1\full_cr$5$next[31:0]$8772 assign { } { } assign $0\full_cr_ok$next[0:0]$8771 $2\full_cr_ok$next[0:0]$8774 - attribute \src "libresoc.v:162420.5-162420.29" + attribute \src "libresoc.v:162419.5-162419.29" switch \initial - attribute \src "libresoc.v:162420.9-162420.17" + attribute \src "libresoc.v:162419.9-162419.17" case 1'1 case end @@ -337093,8 +333903,8 @@ module \pipe update \full_cr$5$next $0\full_cr$5$next[31:0]$8770 update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8771 end - attribute \src "libresoc.v:162438.3-162456.6" - process $proc$libresoc.v:162438$8775 + attribute \src "libresoc.v:162437.3-162455.6" + process $proc$libresoc.v:162437$8775 assign { } { } assign { } { } assign { } { } @@ -337102,9 +333912,9 @@ module \pipe assign { } { } assign $0\cr_a$6$next[3:0]$8777 $1\cr_a$6$next[3:0]$8779 assign $0\cr_a_ok$next[0:0]$8776 $2\cr_a_ok$next[0:0]$8780 - attribute \src "libresoc.v:162439.5-162439.29" + attribute \src "libresoc.v:162438.5-162438.29" switch \initial - attribute \src "libresoc.v:162439.9-162439.17" + attribute \src "libresoc.v:162438.9-162438.17" case 1'1 case end @@ -337137,7 +333947,7 @@ module \pipe update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8776 update \cr_a$6$next $0\cr_a$6$next[3:0]$8777 end - connect \$14 $and$libresoc.v:162301$8731_Y + connect \$14 $and$libresoc.v:162300$8731_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } @@ -337157,155 +333967,155 @@ module \pipe connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \main_muxid \muxid end -attribute \src "libresoc.v:162479.1-163339.10" +attribute \src "libresoc.v:162478.1-163338.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" attribute \generator "nMigen" module \pipe$19 - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire width 64 $0\br_op__cia$2$next[63:0]$8835 - attribute \src "libresoc.v:163151.3-163152.43" + attribute \src "libresoc.v:163150.3-163151.43" wire width 64 $0\br_op__cia$2[63:0]$8809 - attribute \src "libresoc.v:162487.14-162487.51" + attribute \src "libresoc.v:162486.14-162486.51" wire width 64 $0\br_op__cia$2[63:0]$8873 - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire width 14 $0\br_op__fn_unit$4$next[13:0]$8836 - attribute \src "libresoc.v:163155.3-163156.51" + attribute \src "libresoc.v:163154.3-163155.51" wire width 14 $0\br_op__fn_unit$4[13:0]$8813 - attribute \src "libresoc.v:162543.14-162543.43" + attribute \src "libresoc.v:162542.14-162542.43" wire width 14 $0\br_op__fn_unit$4[13:0]$8875 - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8837 - attribute \src "libresoc.v:163159.3-163160.65" + attribute \src "libresoc.v:163158.3-163159.65" wire width 64 $0\br_op__imm_data__data$6[63:0]$8817 - attribute \src "libresoc.v:162552.14-162552.62" + attribute \src "libresoc.v:162551.14-162551.62" wire width 64 $0\br_op__imm_data__data$6[63:0]$8877 - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire $0\br_op__imm_data__ok$7$next[0:0]$8838 - attribute \src "libresoc.v:163161.3-163162.61" + attribute \src "libresoc.v:163160.3-163161.61" wire $0\br_op__imm_data__ok$7[0:0]$8819 - attribute \src "libresoc.v:162561.7-162561.37" + attribute \src "libresoc.v:162560.7-162560.37" wire $0\br_op__imm_data__ok$7[0:0]$8879 - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire width 32 $0\br_op__insn$5$next[31:0]$8839 - attribute \src "libresoc.v:163157.3-163158.45" + attribute \src "libresoc.v:163156.3-163157.45" wire width 32 $0\br_op__insn$5[31:0]$8815 - attribute \src "libresoc.v:162570.14-162570.37" + attribute \src "libresoc.v:162569.14-162569.37" wire width 32 $0\br_op__insn$5[31:0]$8881 - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire width 7 $0\br_op__insn_type$3$next[6:0]$8840 - attribute \src "libresoc.v:163153.3-163154.55" + attribute \src "libresoc.v:163152.3-163153.55" wire width 7 $0\br_op__insn_type$3[6:0]$8811 - attribute \src "libresoc.v:162804.13-162804.41" + attribute \src "libresoc.v:162803.13-162803.41" wire width 7 $0\br_op__insn_type$3[6:0]$8883 - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire $0\br_op__is_32bit$9$next[0:0]$8841 - attribute \src "libresoc.v:163165.3-163166.53" + attribute \src "libresoc.v:163164.3-163165.53" wire $0\br_op__is_32bit$9[0:0]$8823 - attribute \src "libresoc.v:162813.7-162813.33" + attribute \src "libresoc.v:162812.7-162812.33" wire $0\br_op__is_32bit$9[0:0]$8885 - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire $0\br_op__lk$8$next[0:0]$8842 - attribute \src "libresoc.v:163163.3-163164.41" + attribute \src "libresoc.v:163162.3-163163.41" wire $0\br_op__lk$8[0:0]$8821 - attribute \src "libresoc.v:162822.7-162822.27" + attribute \src "libresoc.v:162821.7-162821.27" wire $0\br_op__lk$8[0:0]$8887 - attribute \src "libresoc.v:163267.3-163285.6" + attribute \src "libresoc.v:163266.3-163284.6" wire width 64 $0\fast1$10$next[63:0]$8854 - attribute \src "libresoc.v:163147.3-163148.35" + attribute \src "libresoc.v:163146.3-163147.35" wire width 64 $0\fast1$10[63:0]$8806 - attribute \src "libresoc.v:162835.14-162835.47" + attribute \src "libresoc.v:162834.14-162834.47" wire width 64 $0\fast1$10[63:0]$8889 - attribute \src "libresoc.v:163267.3-163285.6" + attribute \src "libresoc.v:163266.3-163284.6" wire $0\fast1_ok$next[0:0]$8855 - attribute \src "libresoc.v:163149.3-163150.33" + attribute \src "libresoc.v:163148.3-163149.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:163286.3-163304.6" + attribute \src "libresoc.v:163285.3-163303.6" wire width 64 $0\fast2$11$next[63:0]$8860 - attribute \src "libresoc.v:163143.3-163144.35" + attribute \src "libresoc.v:163142.3-163143.35" wire width 64 $0\fast2$11[63:0]$8803 - attribute \src "libresoc.v:162851.14-162851.47" + attribute \src "libresoc.v:162850.14-162850.47" wire width 64 $0\fast2$11[63:0]$8892 - attribute \src "libresoc.v:163286.3-163304.6" + attribute \src "libresoc.v:163285.3-163303.6" wire $0\fast2_ok$next[0:0]$8861 - attribute \src "libresoc.v:163145.3-163146.33" + attribute \src "libresoc.v:163144.3-163145.33" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:162480.7-162480.20" + attribute \src "libresoc.v:162479.7-162479.20" wire $0\initial[0:0] - attribute \src "libresoc.v:163226.3-163238.6" + attribute \src "libresoc.v:163225.3-163237.6" wire width 2 $0\muxid$1$next[1:0]$8832 - attribute \src "libresoc.v:163167.3-163168.33" + attribute \src "libresoc.v:163166.3-163167.33" wire width 2 $0\muxid$1[1:0]$8825 - attribute \src "libresoc.v:163101.13-163101.29" + attribute \src "libresoc.v:163100.13-163100.29" wire width 2 $0\muxid$1[1:0]$8895 - attribute \src "libresoc.v:163305.3-163323.6" + attribute \src "libresoc.v:163304.3-163322.6" wire width 64 $0\nia$next[63:0]$8866 - attribute \src "libresoc.v:163139.3-163140.23" + attribute \src "libresoc.v:163138.3-163139.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:163305.3-163323.6" + attribute \src "libresoc.v:163304.3-163322.6" wire $0\nia_ok$next[0:0]$8867 - attribute \src "libresoc.v:163141.3-163142.29" + attribute \src "libresoc.v:163140.3-163141.29" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:163208.3-163225.6" + attribute \src "libresoc.v:163207.3-163224.6" wire $0\r_busy$next[0:0]$8828 - attribute \src "libresoc.v:163169.3-163170.29" + attribute \src "libresoc.v:163168.3-163169.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire width 64 $1\br_op__cia$2$next[63:0]$8843 - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire width 14 $1\br_op__fn_unit$4$next[13:0]$8844 - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8845 - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire $1\br_op__imm_data__ok$7$next[0:0]$8846 - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire width 32 $1\br_op__insn$5$next[31:0]$8847 - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire width 7 $1\br_op__insn_type$3$next[6:0]$8848 - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire $1\br_op__is_32bit$9$next[0:0]$8849 - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire $1\br_op__lk$8$next[0:0]$8850 - attribute \src "libresoc.v:163267.3-163285.6" + attribute \src "libresoc.v:163266.3-163284.6" wire width 64 $1\fast1$10$next[63:0]$8856 - attribute \src "libresoc.v:163267.3-163285.6" + attribute \src "libresoc.v:163266.3-163284.6" wire $1\fast1_ok$next[0:0]$8857 - attribute \src "libresoc.v:162842.7-162842.22" + attribute \src "libresoc.v:162841.7-162841.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:163286.3-163304.6" + attribute \src "libresoc.v:163285.3-163303.6" wire width 64 $1\fast2$11$next[63:0]$8862 - attribute \src "libresoc.v:163286.3-163304.6" + attribute \src "libresoc.v:163285.3-163303.6" wire $1\fast2_ok$next[0:0]$8863 - attribute \src "libresoc.v:162858.7-162858.22" + attribute \src "libresoc.v:162857.7-162857.22" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:163226.3-163238.6" + attribute \src "libresoc.v:163225.3-163237.6" wire width 2 $1\muxid$1$next[1:0]$8833 - attribute \src "libresoc.v:163305.3-163323.6" + attribute \src "libresoc.v:163304.3-163322.6" wire width 64 $1\nia$next[63:0]$8868 - attribute \src "libresoc.v:163114.14-163114.40" + attribute \src "libresoc.v:163113.14-163113.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:163305.3-163323.6" + attribute \src "libresoc.v:163304.3-163322.6" wire $1\nia_ok$next[0:0]$8869 - attribute \src "libresoc.v:163121.7-163121.20" + attribute \src "libresoc.v:163120.7-163120.20" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:163208.3-163225.6" + attribute \src "libresoc.v:163207.3-163224.6" wire $1\r_busy$next[0:0]$8829 - attribute \src "libresoc.v:163135.7-163135.20" + attribute \src "libresoc.v:163134.7-163134.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8851 - attribute \src "libresoc.v:163239.3-163266.6" + attribute \src "libresoc.v:163238.3-163265.6" wire $2\br_op__imm_data__ok$7$next[0:0]$8852 - attribute \src "libresoc.v:163267.3-163285.6" + attribute \src "libresoc.v:163266.3-163284.6" wire $2\fast1_ok$next[0:0]$8858 - attribute \src "libresoc.v:163286.3-163304.6" + attribute \src "libresoc.v:163285.3-163303.6" wire $2\fast2_ok$next[0:0]$8864 - attribute \src "libresoc.v:163305.3-163323.6" + attribute \src "libresoc.v:163304.3-163322.6" wire $2\nia_ok$next[0:0]$8870 - attribute \src "libresoc.v:163208.3-163225.6" + attribute \src "libresoc.v:163207.3-163224.6" wire $2\r_busy$next[0:0]$8830 - attribute \src "libresoc.v:163138.18-163138.118" - wire $and$libresoc.v:163138$8799_Y + attribute \src "libresoc.v:163137.18-163137.118" + wire $and$libresoc.v:163137$8799_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -337676,7 +334486,7 @@ module \pipe$19 wire \fast2_ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast2_ok$next - attribute \src "libresoc.v:162480.7-162480.15" + attribute \src "libresoc.v:162479.7-162479.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_br_op__cia @@ -337951,7 +334761,7 @@ module \pipe$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:163138$8799 + cell $and $and$libresoc.v:163137$8799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -337959,10 +334769,10 @@ module \pipe$19 parameter \Y_WIDTH 1 connect \A \p_valid_i$23 connect \B \p_ready_o - connect \Y $and$libresoc.v:163138$8799_Y + connect \Y $and$libresoc.v:163137$8799_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:163171.13-163199.4" + attribute \src "libresoc.v:163170.13-163198.4" cell \main$22 \main connect \br_op__cia \main_br_op__cia connect \br_op__cia$2 \main_br_op__cia$13 @@ -337993,274 +334803,274 @@ module \pipe$19 connect \nia_ok \main_nia_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:163200.10-163203.4" + attribute \src "libresoc.v:163199.10-163202.4" cell \n$21 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:163204.10-163207.4" + attribute \src "libresoc.v:163203.10-163206.4" cell \p$20 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:162480.7-162480.20" - process $proc$libresoc.v:162480$8871 + attribute \src "libresoc.v:162479.7-162479.20" + process $proc$libresoc.v:162479$8871 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:162487.14-162487.51" - process $proc$libresoc.v:162487$8872 + attribute \src "libresoc.v:162486.14-162486.51" + process $proc$libresoc.v:162486$8872 assign { } { } assign $0\br_op__cia$2[63:0]$8873 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \br_op__cia$2 $0\br_op__cia$2[63:0]$8873 end - attribute \src "libresoc.v:162543.14-162543.43" - process $proc$libresoc.v:162543$8874 + attribute \src "libresoc.v:162542.14-162542.43" + process $proc$libresoc.v:162542$8874 assign { } { } assign $0\br_op__fn_unit$4[13:0]$8875 14'00000000000000 sync always sync init update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8875 end - attribute \src "libresoc.v:162552.14-162552.62" - process $proc$libresoc.v:162552$8876 + attribute \src "libresoc.v:162551.14-162551.62" + process $proc$libresoc.v:162551$8876 assign { } { } assign $0\br_op__imm_data__data$6[63:0]$8877 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8877 end - attribute \src "libresoc.v:162561.7-162561.37" - process $proc$libresoc.v:162561$8878 + attribute \src "libresoc.v:162560.7-162560.37" + process $proc$libresoc.v:162560$8878 assign { } { } assign $0\br_op__imm_data__ok$7[0:0]$8879 1'0 sync always sync init update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8879 end - attribute \src "libresoc.v:162570.14-162570.37" - process $proc$libresoc.v:162570$8880 + attribute \src "libresoc.v:162569.14-162569.37" + process $proc$libresoc.v:162569$8880 assign { } { } assign $0\br_op__insn$5[31:0]$8881 0 sync always sync init update \br_op__insn$5 $0\br_op__insn$5[31:0]$8881 end - attribute \src "libresoc.v:162804.13-162804.41" - process $proc$libresoc.v:162804$8882 + attribute \src "libresoc.v:162803.13-162803.41" + process $proc$libresoc.v:162803$8882 assign { } { } assign $0\br_op__insn_type$3[6:0]$8883 7'0000000 sync always sync init update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8883 end - attribute \src "libresoc.v:162813.7-162813.33" - process $proc$libresoc.v:162813$8884 + attribute \src "libresoc.v:162812.7-162812.33" + process $proc$libresoc.v:162812$8884 assign { } { } assign $0\br_op__is_32bit$9[0:0]$8885 1'0 sync always sync init update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8885 end - attribute \src "libresoc.v:162822.7-162822.27" - process $proc$libresoc.v:162822$8886 + attribute \src "libresoc.v:162821.7-162821.27" + process $proc$libresoc.v:162821$8886 assign { } { } assign $0\br_op__lk$8[0:0]$8887 1'0 sync always sync init update \br_op__lk$8 $0\br_op__lk$8[0:0]$8887 end - attribute \src "libresoc.v:162835.14-162835.47" - process $proc$libresoc.v:162835$8888 + attribute \src "libresoc.v:162834.14-162834.47" + process $proc$libresoc.v:162834$8888 assign { } { } assign $0\fast1$10[63:0]$8889 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast1$10 $0\fast1$10[63:0]$8889 end - attribute \src "libresoc.v:162842.7-162842.22" - process $proc$libresoc.v:162842$8890 + attribute \src "libresoc.v:162841.7-162841.22" + process $proc$libresoc.v:162841$8890 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:162851.14-162851.47" - process $proc$libresoc.v:162851$8891 + attribute \src "libresoc.v:162850.14-162850.47" + process $proc$libresoc.v:162850$8891 assign { } { } assign $0\fast2$11[63:0]$8892 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast2$11 $0\fast2$11[63:0]$8892 end - attribute \src "libresoc.v:162858.7-162858.22" - process $proc$libresoc.v:162858$8893 + attribute \src "libresoc.v:162857.7-162857.22" + process $proc$libresoc.v:162857$8893 assign { } { } assign $1\fast2_ok[0:0] 1'0 sync always sync init update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:163101.13-163101.29" - process $proc$libresoc.v:163101$8894 + attribute \src "libresoc.v:163100.13-163100.29" + process $proc$libresoc.v:163100$8894 assign { } { } assign $0\muxid$1[1:0]$8895 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$8895 end - attribute \src "libresoc.v:163114.14-163114.40" - process $proc$libresoc.v:163114$8896 + attribute \src "libresoc.v:163113.14-163113.40" + process $proc$libresoc.v:163113$8896 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:163121.7-163121.20" - process $proc$libresoc.v:163121$8897 + attribute \src "libresoc.v:163120.7-163120.20" + process $proc$libresoc.v:163120$8897 assign { } { } assign $1\nia_ok[0:0] 1'0 sync always sync init update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:163135.7-163135.20" - process $proc$libresoc.v:163135$8898 + attribute \src "libresoc.v:163134.7-163134.20" + process $proc$libresoc.v:163134$8898 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:163139.3-163140.23" - process $proc$libresoc.v:163139$8800 + attribute \src "libresoc.v:163138.3-163139.23" + process $proc$libresoc.v:163138$8800 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \coresync_clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:163141.3-163142.29" - process $proc$libresoc.v:163141$8801 + attribute \src "libresoc.v:163140.3-163141.29" + process $proc$libresoc.v:163140$8801 assign { } { } assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:163143.3-163144.35" - process $proc$libresoc.v:163143$8802 + attribute \src "libresoc.v:163142.3-163143.35" + process $proc$libresoc.v:163142$8802 assign { } { } assign $0\fast2$11[63:0]$8803 \fast2$11$next sync posedge \coresync_clk update \fast2$11 $0\fast2$11[63:0]$8803 end - attribute \src "libresoc.v:163145.3-163146.33" - process $proc$libresoc.v:163145$8804 + attribute \src "libresoc.v:163144.3-163145.33" + process $proc$libresoc.v:163144$8804 assign { } { } assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:163147.3-163148.35" - process $proc$libresoc.v:163147$8805 + attribute \src "libresoc.v:163146.3-163147.35" + process $proc$libresoc.v:163146$8805 assign { } { } assign $0\fast1$10[63:0]$8806 \fast1$10$next sync posedge \coresync_clk update \fast1$10 $0\fast1$10[63:0]$8806 end - attribute \src "libresoc.v:163149.3-163150.33" - process $proc$libresoc.v:163149$8807 + attribute \src "libresoc.v:163148.3-163149.33" + process $proc$libresoc.v:163148$8807 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:163151.3-163152.43" - process $proc$libresoc.v:163151$8808 + attribute \src "libresoc.v:163150.3-163151.43" + process $proc$libresoc.v:163150$8808 assign { } { } assign $0\br_op__cia$2[63:0]$8809 \br_op__cia$2$next sync posedge \coresync_clk update \br_op__cia$2 $0\br_op__cia$2[63:0]$8809 end - attribute \src "libresoc.v:163153.3-163154.55" - process $proc$libresoc.v:163153$8810 + attribute \src "libresoc.v:163152.3-163153.55" + process $proc$libresoc.v:163152$8810 assign { } { } assign $0\br_op__insn_type$3[6:0]$8811 \br_op__insn_type$3$next sync posedge \coresync_clk update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8811 end - attribute \src "libresoc.v:163155.3-163156.51" - process $proc$libresoc.v:163155$8812 + attribute \src "libresoc.v:163154.3-163155.51" + process $proc$libresoc.v:163154$8812 assign { } { } assign $0\br_op__fn_unit$4[13:0]$8813 \br_op__fn_unit$4$next sync posedge \coresync_clk update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8813 end - attribute \src "libresoc.v:163157.3-163158.45" - process $proc$libresoc.v:163157$8814 + attribute \src "libresoc.v:163156.3-163157.45" + process $proc$libresoc.v:163156$8814 assign { } { } assign $0\br_op__insn$5[31:0]$8815 \br_op__insn$5$next sync posedge \coresync_clk update \br_op__insn$5 $0\br_op__insn$5[31:0]$8815 end - attribute \src "libresoc.v:163159.3-163160.65" - process $proc$libresoc.v:163159$8816 + attribute \src "libresoc.v:163158.3-163159.65" + process $proc$libresoc.v:163158$8816 assign { } { } assign $0\br_op__imm_data__data$6[63:0]$8817 \br_op__imm_data__data$6$next sync posedge \coresync_clk update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8817 end - attribute \src "libresoc.v:163161.3-163162.61" - process $proc$libresoc.v:163161$8818 + attribute \src "libresoc.v:163160.3-163161.61" + process $proc$libresoc.v:163160$8818 assign { } { } assign $0\br_op__imm_data__ok$7[0:0]$8819 \br_op__imm_data__ok$7$next sync posedge \coresync_clk update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8819 end - attribute \src "libresoc.v:163163.3-163164.41" - process $proc$libresoc.v:163163$8820 + attribute \src "libresoc.v:163162.3-163163.41" + process $proc$libresoc.v:163162$8820 assign { } { } assign $0\br_op__lk$8[0:0]$8821 \br_op__lk$8$next sync posedge \coresync_clk update \br_op__lk$8 $0\br_op__lk$8[0:0]$8821 end - attribute \src "libresoc.v:163165.3-163166.53" - process $proc$libresoc.v:163165$8822 + attribute \src "libresoc.v:163164.3-163165.53" + process $proc$libresoc.v:163164$8822 assign { } { } assign $0\br_op__is_32bit$9[0:0]$8823 \br_op__is_32bit$9$next sync posedge \coresync_clk update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8823 end - attribute \src "libresoc.v:163167.3-163168.33" - process $proc$libresoc.v:163167$8824 + attribute \src "libresoc.v:163166.3-163167.33" + process $proc$libresoc.v:163166$8824 assign { } { } assign $0\muxid$1[1:0]$8825 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$8825 end - attribute \src "libresoc.v:163169.3-163170.29" - process $proc$libresoc.v:163169$8826 + attribute \src "libresoc.v:163168.3-163169.29" + process $proc$libresoc.v:163168$8826 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:163208.3-163225.6" - process $proc$libresoc.v:163208$8827 + attribute \src "libresoc.v:163207.3-163224.6" + process $proc$libresoc.v:163207$8827 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$8828 $2\r_busy$next[0:0]$8830 - attribute \src "libresoc.v:163209.5-163209.29" + attribute \src "libresoc.v:163208.5-163208.29" switch \initial - attribute \src "libresoc.v:163209.9-163209.17" + attribute \src "libresoc.v:163208.9-163208.17" case 1'1 case end @@ -338289,14 +335099,14 @@ module \pipe$19 sync always update \r_busy$next $0\r_busy$next[0:0]$8828 end - attribute \src "libresoc.v:163226.3-163238.6" - process $proc$libresoc.v:163226$8831 + attribute \src "libresoc.v:163225.3-163237.6" + process $proc$libresoc.v:163225$8831 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$8832 $1\muxid$1$next[1:0]$8833 - attribute \src "libresoc.v:163227.5-163227.29" + attribute \src "libresoc.v:163226.5-163226.29" switch \initial - attribute \src "libresoc.v:163227.9-163227.17" + attribute \src "libresoc.v:163226.9-163226.17" case 1'1 case end @@ -338316,8 +335126,8 @@ module \pipe$19 sync always update \muxid$1$next $0\muxid$1$next[1:0]$8832 end - attribute \src "libresoc.v:163239.3-163266.6" - process $proc$libresoc.v:163239$8834 + attribute \src "libresoc.v:163238.3-163265.6" + process $proc$libresoc.v:163238$8834 assign { } { } assign { } { } assign { } { } @@ -338344,9 +335154,9 @@ module \pipe$19 assign $0\br_op__lk$8$next[0:0]$8842 $1\br_op__lk$8$next[0:0]$8850 assign $0\br_op__imm_data__data$6$next[63:0]$8837 $2\br_op__imm_data__data$6$next[63:0]$8851 assign $0\br_op__imm_data__ok$7$next[0:0]$8838 $2\br_op__imm_data__ok$7$next[0:0]$8852 - attribute \src "libresoc.v:163240.5-163240.29" + attribute \src "libresoc.v:163239.5-163239.29" switch \initial - attribute \src "libresoc.v:163240.9-163240.17" + attribute \src "libresoc.v:163239.9-163239.17" case 1'1 case end @@ -338406,8 +335216,8 @@ module \pipe$19 update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8841 update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8842 end - attribute \src "libresoc.v:163267.3-163285.6" - process $proc$libresoc.v:163267$8853 + attribute \src "libresoc.v:163266.3-163284.6" + process $proc$libresoc.v:163266$8853 assign { } { } assign { } { } assign { } { } @@ -338415,9 +335225,9 @@ module \pipe$19 assign $0\fast1$10$next[63:0]$8854 $1\fast1$10$next[63:0]$8856 assign { } { } assign $0\fast1_ok$next[0:0]$8855 $2\fast1_ok$next[0:0]$8858 - attribute \src "libresoc.v:163268.5-163268.29" + attribute \src "libresoc.v:163267.5-163267.29" switch \initial - attribute \src "libresoc.v:163268.9-163268.17" + attribute \src "libresoc.v:163267.9-163267.17" case 1'1 case end @@ -338450,8 +335260,8 @@ module \pipe$19 update \fast1$10$next $0\fast1$10$next[63:0]$8854 update \fast1_ok$next $0\fast1_ok$next[0:0]$8855 end - attribute \src "libresoc.v:163286.3-163304.6" - process $proc$libresoc.v:163286$8859 + attribute \src "libresoc.v:163285.3-163303.6" + process $proc$libresoc.v:163285$8859 assign { } { } assign { } { } assign { } { } @@ -338459,9 +335269,9 @@ module \pipe$19 assign $0\fast2$11$next[63:0]$8860 $1\fast2$11$next[63:0]$8862 assign { } { } assign $0\fast2_ok$next[0:0]$8861 $2\fast2_ok$next[0:0]$8864 - attribute \src "libresoc.v:163287.5-163287.29" + attribute \src "libresoc.v:163286.5-163286.29" switch \initial - attribute \src "libresoc.v:163287.9-163287.17" + attribute \src "libresoc.v:163286.9-163286.17" case 1'1 case end @@ -338494,8 +335304,8 @@ module \pipe$19 update \fast2$11$next $0\fast2$11$next[63:0]$8860 update \fast2_ok$next $0\fast2_ok$next[0:0]$8861 end - attribute \src "libresoc.v:163305.3-163323.6" - process $proc$libresoc.v:163305$8865 + attribute \src "libresoc.v:163304.3-163322.6" + process $proc$libresoc.v:163304$8865 assign { } { } assign { } { } assign { } { } @@ -338503,9 +335313,9 @@ module \pipe$19 assign $0\nia$next[63:0]$8866 $1\nia$next[63:0]$8868 assign { } { } assign $0\nia_ok$next[0:0]$8867 $2\nia_ok$next[0:0]$8870 - attribute \src "libresoc.v:163306.5-163306.29" + attribute \src "libresoc.v:163305.5-163305.29" switch \initial - attribute \src "libresoc.v:163306.9-163306.17" + attribute \src "libresoc.v:163305.9-163305.17" case 1'1 case end @@ -338538,7 +335348,7 @@ module \pipe$19 update \nia$next $0\nia$next[63:0]$8866 update \nia_ok$next $0\nia_ok$next[0:0]$8867 end - connect \$24 $and$libresoc.v:163138$8799_Y + connect \$24 $and$libresoc.v:163137$8799_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } @@ -338555,173 +335365,173 @@ module \pipe$19 connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } connect \main_muxid \muxid end -attribute \src "libresoc.v:163343.1-164273.10" +attribute \src "libresoc.v:163342.1-164272.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" attribute \generator "nMigen" module \pipe$64 - attribute \src "libresoc.v:164176.3-164194.6" + attribute \src "libresoc.v:164175.3-164193.6" wire width 64 $0\fast1$7$next[63:0]$8958 - attribute \src "libresoc.v:164029.3-164030.33" + attribute \src "libresoc.v:164028.3-164029.33" wire width 64 $0\fast1$7[63:0]$8910 - attribute \src "libresoc.v:163357.14-163357.46" + attribute \src "libresoc.v:163356.14-163356.46" wire width 64 $0\fast1$7[63:0]$8982 - attribute \src "libresoc.v:164176.3-164194.6" + attribute \src "libresoc.v:164175.3-164193.6" wire $0\fast1_ok$next[0:0]$8957 - attribute \src "libresoc.v:164031.3-164032.33" + attribute \src "libresoc.v:164030.3-164031.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:163344.7-163344.20" + attribute \src "libresoc.v:163343.7-163343.20" wire $0\initial[0:0] - attribute \src "libresoc.v:164109.3-164121.6" + attribute \src "libresoc.v:164108.3-164120.6" wire width 2 $0\muxid$1$next[1:0]$8933 - attribute \src "libresoc.v:164049.3-164050.33" + attribute \src "libresoc.v:164048.3-164049.33" wire width 2 $0\muxid$1[1:0]$8926 - attribute \src "libresoc.v:163371.13-163371.29" + attribute \src "libresoc.v:163370.13-163370.29" wire width 2 $0\muxid$1[1:0]$8985 - attribute \src "libresoc.v:164138.3-164156.6" + attribute \src "libresoc.v:164137.3-164155.6" wire width 64 $0\o$next[63:0]$8945 - attribute \src "libresoc.v:164037.3-164038.19" + attribute \src "libresoc.v:164036.3-164037.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:164138.3-164156.6" + attribute \src "libresoc.v:164137.3-164155.6" wire $0\o_ok$next[0:0]$8946 - attribute \src "libresoc.v:164039.3-164040.25" + attribute \src "libresoc.v:164038.3-164039.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:164091.3-164108.6" + attribute \src "libresoc.v:164090.3-164107.6" wire $0\r_busy$next[0:0]$8929 - attribute \src "libresoc.v:164051.3-164052.29" + attribute \src "libresoc.v:164050.3-164051.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:164157.3-164175.6" + attribute \src "libresoc.v:164156.3-164174.6" wire width 64 $0\spr1$6$next[63:0]$8951 - attribute \src "libresoc.v:164033.3-164034.31" + attribute \src "libresoc.v:164032.3-164033.31" wire width 64 $0\spr1$6[63:0]$8913 - attribute \src "libresoc.v:163416.14-163416.45" + attribute \src "libresoc.v:163415.14-163415.45" wire width 64 $0\spr1$6[63:0]$8990 - attribute \src "libresoc.v:164157.3-164175.6" + attribute \src "libresoc.v:164156.3-164174.6" wire $0\spr1_ok$next[0:0]$8952 - attribute \src "libresoc.v:164035.3-164036.31" + attribute \src "libresoc.v:164034.3-164035.31" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:164122.3-164137.6" + attribute \src "libresoc.v:164121.3-164136.6" wire width 14 $0\spr_op__fn_unit$3$next[13:0]$8936 - attribute \src "libresoc.v:164043.3-164044.53" + attribute \src "libresoc.v:164042.3-164043.53" wire width 14 $0\spr_op__fn_unit$3[13:0]$8920 - attribute \src "libresoc.v:163713.14-163713.44" + attribute \src "libresoc.v:163712.14-163712.44" wire width 14 $0\spr_op__fn_unit$3[13:0]$8993 - attribute \src "libresoc.v:164122.3-164137.6" + attribute \src "libresoc.v:164121.3-164136.6" wire width 32 $0\spr_op__insn$4$next[31:0]$8937 - attribute \src "libresoc.v:164045.3-164046.47" + attribute \src "libresoc.v:164044.3-164045.47" wire width 32 $0\spr_op__insn$4[31:0]$8922 - attribute \src "libresoc.v:163722.14-163722.38" + attribute \src "libresoc.v:163721.14-163721.38" wire width 32 $0\spr_op__insn$4[31:0]$8995 - attribute \src "libresoc.v:164122.3-164137.6" + attribute \src "libresoc.v:164121.3-164136.6" wire width 7 $0\spr_op__insn_type$2$next[6:0]$8938 - attribute \src "libresoc.v:164041.3-164042.57" + attribute \src "libresoc.v:164040.3-164041.57" wire width 7 $0\spr_op__insn_type$2[6:0]$8918 - attribute \src "libresoc.v:163879.13-163879.42" + attribute \src "libresoc.v:163878.13-163878.42" wire width 7 $0\spr_op__insn_type$2[6:0]$8997 - attribute \src "libresoc.v:164122.3-164137.6" + attribute \src "libresoc.v:164121.3-164136.6" wire $0\spr_op__is_32bit$5$next[0:0]$8939 - attribute \src "libresoc.v:164047.3-164048.55" + attribute \src "libresoc.v:164046.3-164047.55" wire $0\spr_op__is_32bit$5[0:0]$8924 - attribute \src "libresoc.v:163965.7-163965.34" + attribute \src "libresoc.v:163964.7-163964.34" wire $0\spr_op__is_32bit$5[0:0]$8999 - attribute \src "libresoc.v:164233.3-164251.6" + attribute \src "libresoc.v:164232.3-164250.6" wire width 2 $0\xer_ca$10$next[1:0]$8975 - attribute \src "libresoc.v:164017.3-164018.37" + attribute \src "libresoc.v:164016.3-164017.37" wire width 2 $0\xer_ca$10[1:0]$8901 - attribute \src "libresoc.v:163972.13-163972.31" + attribute \src "libresoc.v:163971.13-163971.31" wire width 2 $0\xer_ca$10[1:0]$9001 - attribute \src "libresoc.v:164233.3-164251.6" + attribute \src "libresoc.v:164232.3-164250.6" wire $0\xer_ca_ok$next[0:0]$8976 - attribute \src "libresoc.v:164019.3-164020.35" + attribute \src "libresoc.v:164018.3-164019.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:164214.3-164232.6" + attribute \src "libresoc.v:164213.3-164231.6" wire width 2 $0\xer_ov$9$next[1:0]$8970 - attribute \src "libresoc.v:164021.3-164022.35" + attribute \src "libresoc.v:164020.3-164021.35" wire width 2 $0\xer_ov$9[1:0]$8904 - attribute \src "libresoc.v:163990.13-163990.30" + attribute \src "libresoc.v:163989.13-163989.30" wire width 2 $0\xer_ov$9[1:0]$9004 - attribute \src "libresoc.v:164214.3-164232.6" + attribute \src "libresoc.v:164213.3-164231.6" wire $0\xer_ov_ok$next[0:0]$8969 - attribute \src "libresoc.v:164023.3-164024.35" + attribute \src "libresoc.v:164022.3-164023.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:164195.3-164213.6" + attribute \src "libresoc.v:164194.3-164212.6" wire $0\xer_so$8$next[0:0]$8964 - attribute \src "libresoc.v:164025.3-164026.35" + attribute \src "libresoc.v:164024.3-164025.35" wire $0\xer_so$8[0:0]$8907 - attribute \src "libresoc.v:164006.7-164006.24" + attribute \src "libresoc.v:164005.7-164005.24" wire $0\xer_so$8[0:0]$9007 - attribute \src "libresoc.v:164195.3-164213.6" + attribute \src "libresoc.v:164194.3-164212.6" wire $0\xer_so_ok$next[0:0]$8963 - attribute \src "libresoc.v:164027.3-164028.35" + attribute \src "libresoc.v:164026.3-164027.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:164176.3-164194.6" + attribute \src "libresoc.v:164175.3-164193.6" wire width 64 $1\fast1$7$next[63:0]$8960 - attribute \src "libresoc.v:164176.3-164194.6" + attribute \src "libresoc.v:164175.3-164193.6" wire $1\fast1_ok$next[0:0]$8959 - attribute \src "libresoc.v:163362.7-163362.22" + attribute \src "libresoc.v:163361.7-163361.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:164109.3-164121.6" + attribute \src "libresoc.v:164108.3-164120.6" wire width 2 $1\muxid$1$next[1:0]$8934 - attribute \src "libresoc.v:164138.3-164156.6" + attribute \src "libresoc.v:164137.3-164155.6" wire width 64 $1\o$next[63:0]$8947 - attribute \src "libresoc.v:163384.14-163384.38" + attribute \src "libresoc.v:163383.14-163383.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:164138.3-164156.6" + attribute \src "libresoc.v:164137.3-164155.6" wire $1\o_ok$next[0:0]$8948 - attribute \src "libresoc.v:163391.7-163391.18" + attribute \src "libresoc.v:163390.7-163390.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:164091.3-164108.6" + attribute \src "libresoc.v:164090.3-164107.6" wire $1\r_busy$next[0:0]$8930 - attribute \src "libresoc.v:163405.7-163405.20" + attribute \src "libresoc.v:163404.7-163404.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:164157.3-164175.6" + attribute \src "libresoc.v:164156.3-164174.6" wire width 64 $1\spr1$6$next[63:0]$8953 - attribute \src "libresoc.v:164157.3-164175.6" + attribute \src "libresoc.v:164156.3-164174.6" wire $1\spr1_ok$next[0:0]$8954 - attribute \src "libresoc.v:163421.7-163421.21" + attribute \src "libresoc.v:163420.7-163420.21" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:164122.3-164137.6" + attribute \src "libresoc.v:164121.3-164136.6" wire width 14 $1\spr_op__fn_unit$3$next[13:0]$8940 - attribute \src "libresoc.v:164122.3-164137.6" + attribute \src "libresoc.v:164121.3-164136.6" wire width 32 $1\spr_op__insn$4$next[31:0]$8941 - attribute \src "libresoc.v:164122.3-164137.6" + attribute \src "libresoc.v:164121.3-164136.6" wire width 7 $1\spr_op__insn_type$2$next[6:0]$8942 - attribute \src "libresoc.v:164122.3-164137.6" + attribute \src "libresoc.v:164121.3-164136.6" wire $1\spr_op__is_32bit$5$next[0:0]$8943 - attribute \src "libresoc.v:164233.3-164251.6" + attribute \src "libresoc.v:164232.3-164250.6" wire width 2 $1\xer_ca$10$next[1:0]$8977 - attribute \src "libresoc.v:164233.3-164251.6" + attribute \src "libresoc.v:164232.3-164250.6" wire $1\xer_ca_ok$next[0:0]$8978 - attribute \src "libresoc.v:163979.7-163979.23" + attribute \src "libresoc.v:163978.7-163978.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:164214.3-164232.6" + attribute \src "libresoc.v:164213.3-164231.6" wire width 2 $1\xer_ov$9$next[1:0]$8972 - attribute \src "libresoc.v:164214.3-164232.6" + attribute \src "libresoc.v:164213.3-164231.6" wire $1\xer_ov_ok$next[0:0]$8971 - attribute \src "libresoc.v:163995.7-163995.23" + attribute \src "libresoc.v:163994.7-163994.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:164195.3-164213.6" + attribute \src "libresoc.v:164194.3-164212.6" wire $1\xer_so$8$next[0:0]$8966 - attribute \src "libresoc.v:164195.3-164213.6" + attribute \src "libresoc.v:164194.3-164212.6" wire $1\xer_so_ok$next[0:0]$8965 - attribute \src "libresoc.v:164011.7-164011.23" + attribute \src "libresoc.v:164010.7-164010.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:164176.3-164194.6" + attribute \src "libresoc.v:164175.3-164193.6" wire $2\fast1_ok$next[0:0]$8961 - attribute \src "libresoc.v:164138.3-164156.6" + attribute \src "libresoc.v:164137.3-164155.6" wire $2\o_ok$next[0:0]$8949 - attribute \src "libresoc.v:164091.3-164108.6" + attribute \src "libresoc.v:164090.3-164107.6" wire $2\r_busy$next[0:0]$8931 - attribute \src "libresoc.v:164157.3-164175.6" + attribute \src "libresoc.v:164156.3-164174.6" wire $2\spr1_ok$next[0:0]$8955 - attribute \src "libresoc.v:164233.3-164251.6" + attribute \src "libresoc.v:164232.3-164250.6" wire $2\xer_ca_ok$next[0:0]$8979 - attribute \src "libresoc.v:164214.3-164232.6" + attribute \src "libresoc.v:164213.3-164231.6" wire $2\xer_ov_ok$next[0:0]$8973 - attribute \src "libresoc.v:164195.3-164213.6" + attribute \src "libresoc.v:164194.3-164212.6" wire $2\xer_so_ok$next[0:0]$8967 - attribute \src "libresoc.v:164016.18-164016.118" - wire $and$libresoc.v:164016$8899_Y + attribute \src "libresoc.v:164015.18-164015.118" + wire $and$libresoc.v:164015$8899_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" @@ -338742,7 +335552,7 @@ module \pipe$64 wire \fast1_ok$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast1_ok$next - attribute \src "libresoc.v:163344.7-163344.15" + attribute \src "libresoc.v:163343.7-163343.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -339379,7 +336189,7 @@ module \pipe$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:164016$8899 + cell $and $and$libresoc.v:164015$8899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -339387,22 +336197,22 @@ module \pipe$64 parameter \Y_WIDTH 1 connect \A \p_valid_i$21 connect \B \p_ready_o - connect \Y $and$libresoc.v:164016$8899_Y + connect \Y $and$libresoc.v:164015$8899_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:164053.10-164056.4" + attribute \src "libresoc.v:164052.10-164055.4" cell \n$66 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:164057.10-164060.4" + attribute \src "libresoc.v:164056.10-164059.4" cell \p$65 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:164061.12-164090.4" + attribute \src "libresoc.v:164060.12-164089.4" cell \spr_main \spr_main connect \fast1 \spr_main_fast1 connect \fast1$7 \spr_main_fast1$17 @@ -339433,293 +336243,293 @@ module \pipe$64 connect \xer_so$8 \spr_main_xer_so$18 connect \xer_so_ok \spr_main_xer_so_ok end - attribute \src "libresoc.v:163344.7-163344.20" - process $proc$libresoc.v:163344$8980 + attribute \src "libresoc.v:163343.7-163343.20" + process $proc$libresoc.v:163343$8980 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:163357.14-163357.46" - process $proc$libresoc.v:163357$8981 + attribute \src "libresoc.v:163356.14-163356.46" + process $proc$libresoc.v:163356$8981 assign { } { } assign $0\fast1$7[63:0]$8982 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast1$7 $0\fast1$7[63:0]$8982 end - attribute \src "libresoc.v:163362.7-163362.22" - process $proc$libresoc.v:163362$8983 + attribute \src "libresoc.v:163361.7-163361.22" + process $proc$libresoc.v:163361$8983 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:163371.13-163371.29" - process $proc$libresoc.v:163371$8984 + attribute \src "libresoc.v:163370.13-163370.29" + process $proc$libresoc.v:163370$8984 assign { } { } assign $0\muxid$1[1:0]$8985 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$8985 end - attribute \src "libresoc.v:163384.14-163384.38" - process $proc$libresoc.v:163384$8986 + attribute \src "libresoc.v:163383.14-163383.38" + process $proc$libresoc.v:163383$8986 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:163391.7-163391.18" - process $proc$libresoc.v:163391$8987 + attribute \src "libresoc.v:163390.7-163390.18" + process $proc$libresoc.v:163390$8987 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:163405.7-163405.20" - process $proc$libresoc.v:163405$8988 + attribute \src "libresoc.v:163404.7-163404.20" + process $proc$libresoc.v:163404$8988 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:163416.14-163416.45" - process $proc$libresoc.v:163416$8989 + attribute \src "libresoc.v:163415.14-163415.45" + process $proc$libresoc.v:163415$8989 assign { } { } assign $0\spr1$6[63:0]$8990 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \spr1$6 $0\spr1$6[63:0]$8990 end - attribute \src "libresoc.v:163421.7-163421.21" - process $proc$libresoc.v:163421$8991 + attribute \src "libresoc.v:163420.7-163420.21" + process $proc$libresoc.v:163420$8991 assign { } { } assign $1\spr1_ok[0:0] 1'0 sync always sync init update \spr1_ok $1\spr1_ok[0:0] end - attribute \src "libresoc.v:163713.14-163713.44" - process $proc$libresoc.v:163713$8992 + attribute \src "libresoc.v:163712.14-163712.44" + process $proc$libresoc.v:163712$8992 assign { } { } assign $0\spr_op__fn_unit$3[13:0]$8993 14'00000000000000 sync always sync init update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8993 end - attribute \src "libresoc.v:163722.14-163722.38" - process $proc$libresoc.v:163722$8994 + attribute \src "libresoc.v:163721.14-163721.38" + process $proc$libresoc.v:163721$8994 assign { } { } assign $0\spr_op__insn$4[31:0]$8995 0 sync always sync init update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8995 end - attribute \src "libresoc.v:163879.13-163879.42" - process $proc$libresoc.v:163879$8996 + attribute \src "libresoc.v:163878.13-163878.42" + process $proc$libresoc.v:163878$8996 assign { } { } assign $0\spr_op__insn_type$2[6:0]$8997 7'0000000 sync always sync init update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8997 end - attribute \src "libresoc.v:163965.7-163965.34" - process $proc$libresoc.v:163965$8998 + attribute \src "libresoc.v:163964.7-163964.34" + process $proc$libresoc.v:163964$8998 assign { } { } assign $0\spr_op__is_32bit$5[0:0]$8999 1'0 sync always sync init update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8999 end - attribute \src "libresoc.v:163972.13-163972.31" - process $proc$libresoc.v:163972$9000 + attribute \src "libresoc.v:163971.13-163971.31" + process $proc$libresoc.v:163971$9000 assign { } { } assign $0\xer_ca$10[1:0]$9001 2'00 sync always sync init update \xer_ca$10 $0\xer_ca$10[1:0]$9001 end - attribute \src "libresoc.v:163979.7-163979.23" - process $proc$libresoc.v:163979$9002 + attribute \src "libresoc.v:163978.7-163978.23" + process $proc$libresoc.v:163978$9002 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:163990.13-163990.30" - process $proc$libresoc.v:163990$9003 + attribute \src "libresoc.v:163989.13-163989.30" + process $proc$libresoc.v:163989$9003 assign { } { } assign $0\xer_ov$9[1:0]$9004 2'00 sync always sync init update \xer_ov$9 $0\xer_ov$9[1:0]$9004 end - attribute \src "libresoc.v:163995.7-163995.23" - process $proc$libresoc.v:163995$9005 + attribute \src "libresoc.v:163994.7-163994.23" + process $proc$libresoc.v:163994$9005 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:164006.7-164006.24" - process $proc$libresoc.v:164006$9006 + attribute \src "libresoc.v:164005.7-164005.24" + process $proc$libresoc.v:164005$9006 assign { } { } assign $0\xer_so$8[0:0]$9007 1'0 sync always sync init update \xer_so$8 $0\xer_so$8[0:0]$9007 end - attribute \src "libresoc.v:164011.7-164011.23" - process $proc$libresoc.v:164011$9008 + attribute \src "libresoc.v:164010.7-164010.23" + process $proc$libresoc.v:164010$9008 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:164017.3-164018.37" - process $proc$libresoc.v:164017$8900 + attribute \src "libresoc.v:164016.3-164017.37" + process $proc$libresoc.v:164016$8900 assign { } { } assign $0\xer_ca$10[1:0]$8901 \xer_ca$10$next sync posedge \coresync_clk update \xer_ca$10 $0\xer_ca$10[1:0]$8901 end - attribute \src "libresoc.v:164019.3-164020.35" - process $proc$libresoc.v:164019$8902 + attribute \src "libresoc.v:164018.3-164019.35" + process $proc$libresoc.v:164018$8902 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:164021.3-164022.35" - process $proc$libresoc.v:164021$8903 + attribute \src "libresoc.v:164020.3-164021.35" + process $proc$libresoc.v:164020$8903 assign { } { } assign $0\xer_ov$9[1:0]$8904 \xer_ov$9$next sync posedge \coresync_clk update \xer_ov$9 $0\xer_ov$9[1:0]$8904 end - attribute \src "libresoc.v:164023.3-164024.35" - process $proc$libresoc.v:164023$8905 + attribute \src "libresoc.v:164022.3-164023.35" + process $proc$libresoc.v:164022$8905 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:164025.3-164026.35" - process $proc$libresoc.v:164025$8906 + attribute \src "libresoc.v:164024.3-164025.35" + process $proc$libresoc.v:164024$8906 assign { } { } assign $0\xer_so$8[0:0]$8907 \xer_so$8$next sync posedge \coresync_clk update \xer_so$8 $0\xer_so$8[0:0]$8907 end - attribute \src "libresoc.v:164027.3-164028.35" - process $proc$libresoc.v:164027$8908 + attribute \src "libresoc.v:164026.3-164027.35" + process $proc$libresoc.v:164026$8908 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:164029.3-164030.33" - process $proc$libresoc.v:164029$8909 + attribute \src "libresoc.v:164028.3-164029.33" + process $proc$libresoc.v:164028$8909 assign { } { } assign $0\fast1$7[63:0]$8910 \fast1$7$next sync posedge \coresync_clk update \fast1$7 $0\fast1$7[63:0]$8910 end - attribute \src "libresoc.v:164031.3-164032.33" - process $proc$libresoc.v:164031$8911 + attribute \src "libresoc.v:164030.3-164031.33" + process $proc$libresoc.v:164030$8911 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:164033.3-164034.31" - process $proc$libresoc.v:164033$8912 + attribute \src "libresoc.v:164032.3-164033.31" + process $proc$libresoc.v:164032$8912 assign { } { } assign $0\spr1$6[63:0]$8913 \spr1$6$next sync posedge \coresync_clk update \spr1$6 $0\spr1$6[63:0]$8913 end - attribute \src "libresoc.v:164035.3-164036.31" - process $proc$libresoc.v:164035$8914 + attribute \src "libresoc.v:164034.3-164035.31" + process $proc$libresoc.v:164034$8914 assign { } { } assign $0\spr1_ok[0:0] \spr1_ok$next sync posedge \coresync_clk update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:164037.3-164038.19" - process $proc$libresoc.v:164037$8915 + attribute \src "libresoc.v:164036.3-164037.19" + process $proc$libresoc.v:164036$8915 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:164039.3-164040.25" - process $proc$libresoc.v:164039$8916 + attribute \src "libresoc.v:164038.3-164039.25" + process $proc$libresoc.v:164038$8916 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:164041.3-164042.57" - process $proc$libresoc.v:164041$8917 + attribute \src "libresoc.v:164040.3-164041.57" + process $proc$libresoc.v:164040$8917 assign { } { } assign $0\spr_op__insn_type$2[6:0]$8918 \spr_op__insn_type$2$next sync posedge \coresync_clk update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8918 end - attribute \src "libresoc.v:164043.3-164044.53" - process $proc$libresoc.v:164043$8919 + attribute \src "libresoc.v:164042.3-164043.53" + process $proc$libresoc.v:164042$8919 assign { } { } assign $0\spr_op__fn_unit$3[13:0]$8920 \spr_op__fn_unit$3$next sync posedge \coresync_clk update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8920 end - attribute \src "libresoc.v:164045.3-164046.47" - process $proc$libresoc.v:164045$8921 + attribute \src "libresoc.v:164044.3-164045.47" + process $proc$libresoc.v:164044$8921 assign { } { } assign $0\spr_op__insn$4[31:0]$8922 \spr_op__insn$4$next sync posedge \coresync_clk update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8922 end - attribute \src "libresoc.v:164047.3-164048.55" - process $proc$libresoc.v:164047$8923 + attribute \src "libresoc.v:164046.3-164047.55" + process $proc$libresoc.v:164046$8923 assign { } { } assign $0\spr_op__is_32bit$5[0:0]$8924 \spr_op__is_32bit$5$next sync posedge \coresync_clk update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8924 end - attribute \src "libresoc.v:164049.3-164050.33" - process $proc$libresoc.v:164049$8925 + attribute \src "libresoc.v:164048.3-164049.33" + process $proc$libresoc.v:164048$8925 assign { } { } assign $0\muxid$1[1:0]$8926 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$8926 end - attribute \src "libresoc.v:164051.3-164052.29" - process $proc$libresoc.v:164051$8927 + attribute \src "libresoc.v:164050.3-164051.29" + process $proc$libresoc.v:164050$8927 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:164091.3-164108.6" - process $proc$libresoc.v:164091$8928 + attribute \src "libresoc.v:164090.3-164107.6" + process $proc$libresoc.v:164090$8928 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$8929 $2\r_busy$next[0:0]$8931 - attribute \src "libresoc.v:164092.5-164092.29" + attribute \src "libresoc.v:164091.5-164091.29" switch \initial - attribute \src "libresoc.v:164092.9-164092.17" + attribute \src "libresoc.v:164091.9-164091.17" case 1'1 case end @@ -339748,14 +336558,14 @@ module \pipe$64 sync always update \r_busy$next $0\r_busy$next[0:0]$8929 end - attribute \src "libresoc.v:164109.3-164121.6" - process $proc$libresoc.v:164109$8932 + attribute \src "libresoc.v:164108.3-164120.6" + process $proc$libresoc.v:164108$8932 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$8933 $1\muxid$1$next[1:0]$8934 - attribute \src "libresoc.v:164110.5-164110.29" + attribute \src "libresoc.v:164109.5-164109.29" switch \initial - attribute \src "libresoc.v:164110.9-164110.17" + attribute \src "libresoc.v:164109.9-164109.17" case 1'1 case end @@ -339775,8 +336585,8 @@ module \pipe$64 sync always update \muxid$1$next $0\muxid$1$next[1:0]$8933 end - attribute \src "libresoc.v:164122.3-164137.6" - process $proc$libresoc.v:164122$8935 + attribute \src "libresoc.v:164121.3-164136.6" + process $proc$libresoc.v:164121$8935 assign { } { } assign { } { } assign { } { } @@ -339789,9 +336599,9 @@ module \pipe$64 assign $0\spr_op__insn$4$next[31:0]$8937 $1\spr_op__insn$4$next[31:0]$8941 assign $0\spr_op__insn_type$2$next[6:0]$8938 $1\spr_op__insn_type$2$next[6:0]$8942 assign $0\spr_op__is_32bit$5$next[0:0]$8939 $1\spr_op__is_32bit$5$next[0:0]$8943 - attribute \src "libresoc.v:164123.5-164123.29" + attribute \src "libresoc.v:164122.5-164122.29" switch \initial - attribute \src "libresoc.v:164123.9-164123.17" + attribute \src "libresoc.v:164122.9-164122.17" case 1'1 case end @@ -339823,8 +336633,8 @@ module \pipe$64 update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8938 update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8939 end - attribute \src "libresoc.v:164138.3-164156.6" - process $proc$libresoc.v:164138$8944 + attribute \src "libresoc.v:164137.3-164155.6" + process $proc$libresoc.v:164137$8944 assign { } { } assign { } { } assign { } { } @@ -339832,9 +336642,9 @@ module \pipe$64 assign $0\o$next[63:0]$8945 $1\o$next[63:0]$8947 assign { } { } assign $0\o_ok$next[0:0]$8946 $2\o_ok$next[0:0]$8949 - attribute \src "libresoc.v:164139.5-164139.29" + attribute \src "libresoc.v:164138.5-164138.29" switch \initial - attribute \src "libresoc.v:164139.9-164139.17" + attribute \src "libresoc.v:164138.9-164138.17" case 1'1 case end @@ -339867,8 +336677,8 @@ module \pipe$64 update \o$next $0\o$next[63:0]$8945 update \o_ok$next $0\o_ok$next[0:0]$8946 end - attribute \src "libresoc.v:164157.3-164175.6" - process $proc$libresoc.v:164157$8950 + attribute \src "libresoc.v:164156.3-164174.6" + process $proc$libresoc.v:164156$8950 assign { } { } assign { } { } assign { } { } @@ -339876,9 +336686,9 @@ module \pipe$64 assign $0\spr1$6$next[63:0]$8951 $1\spr1$6$next[63:0]$8953 assign { } { } assign $0\spr1_ok$next[0:0]$8952 $2\spr1_ok$next[0:0]$8955 - attribute \src "libresoc.v:164158.5-164158.29" + attribute \src "libresoc.v:164157.5-164157.29" switch \initial - attribute \src "libresoc.v:164158.9-164158.17" + attribute \src "libresoc.v:164157.9-164157.17" case 1'1 case end @@ -339911,8 +336721,8 @@ module \pipe$64 update \spr1$6$next $0\spr1$6$next[63:0]$8951 update \spr1_ok$next $0\spr1_ok$next[0:0]$8952 end - attribute \src "libresoc.v:164176.3-164194.6" - process $proc$libresoc.v:164176$8956 + attribute \src "libresoc.v:164175.3-164193.6" + process $proc$libresoc.v:164175$8956 assign { } { } assign { } { } assign { } { } @@ -339920,9 +336730,9 @@ module \pipe$64 assign { } { } assign $0\fast1$7$next[63:0]$8958 $1\fast1$7$next[63:0]$8960 assign $0\fast1_ok$next[0:0]$8957 $2\fast1_ok$next[0:0]$8961 - attribute \src "libresoc.v:164177.5-164177.29" + attribute \src "libresoc.v:164176.5-164176.29" switch \initial - attribute \src "libresoc.v:164177.9-164177.17" + attribute \src "libresoc.v:164176.9-164176.17" case 1'1 case end @@ -339955,8 +336765,8 @@ module \pipe$64 update \fast1_ok$next $0\fast1_ok$next[0:0]$8957 update \fast1$7$next $0\fast1$7$next[63:0]$8958 end - attribute \src "libresoc.v:164195.3-164213.6" - process $proc$libresoc.v:164195$8962 + attribute \src "libresoc.v:164194.3-164212.6" + process $proc$libresoc.v:164194$8962 assign { } { } assign { } { } assign { } { } @@ -339964,9 +336774,9 @@ module \pipe$64 assign { } { } assign $0\xer_so$8$next[0:0]$8964 $1\xer_so$8$next[0:0]$8966 assign $0\xer_so_ok$next[0:0]$8963 $2\xer_so_ok$next[0:0]$8967 - attribute \src "libresoc.v:164196.5-164196.29" + attribute \src "libresoc.v:164195.5-164195.29" switch \initial - attribute \src "libresoc.v:164196.9-164196.17" + attribute \src "libresoc.v:164195.9-164195.17" case 1'1 case end @@ -339999,8 +336809,8 @@ module \pipe$64 update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8963 update \xer_so$8$next $0\xer_so$8$next[0:0]$8964 end - attribute \src "libresoc.v:164214.3-164232.6" - process $proc$libresoc.v:164214$8968 + attribute \src "libresoc.v:164213.3-164231.6" + process $proc$libresoc.v:164213$8968 assign { } { } assign { } { } assign { } { } @@ -340008,9 +336818,9 @@ module \pipe$64 assign { } { } assign $0\xer_ov$9$next[1:0]$8970 $1\xer_ov$9$next[1:0]$8972 assign $0\xer_ov_ok$next[0:0]$8969 $2\xer_ov_ok$next[0:0]$8973 - attribute \src "libresoc.v:164215.5-164215.29" + attribute \src "libresoc.v:164214.5-164214.29" switch \initial - attribute \src "libresoc.v:164215.9-164215.17" + attribute \src "libresoc.v:164214.9-164214.17" case 1'1 case end @@ -340043,8 +336853,8 @@ module \pipe$64 update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8969 update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8970 end - attribute \src "libresoc.v:164233.3-164251.6" - process $proc$libresoc.v:164233$8974 + attribute \src "libresoc.v:164232.3-164250.6" + process $proc$libresoc.v:164232$8974 assign { } { } assign { } { } assign { } { } @@ -340052,9 +336862,9 @@ module \pipe$64 assign $0\xer_ca$10$next[1:0]$8975 $1\xer_ca$10$next[1:0]$8977 assign { } { } assign $0\xer_ca_ok$next[0:0]$8976 $2\xer_ca_ok$next[0:0]$8979 - attribute \src "libresoc.v:164234.5-164234.29" + attribute \src "libresoc.v:164233.5-164233.29" switch \initial - attribute \src "libresoc.v:164234.9-164234.17" + attribute \src "libresoc.v:164233.9-164233.17" case 1'1 case end @@ -340087,7 +336897,7 @@ module \pipe$64 update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8975 update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8976 end - connect \$22 $and$libresoc.v:164016$8899_Y + connect \$22 $and$libresoc.v:164015$8899_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } @@ -340110,279 +336920,279 @@ module \pipe$64 connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \spr_main_muxid \muxid end -attribute \src "libresoc.v:164277.1-165769.10" +attribute \src "libresoc.v:164276.1-165768.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" attribute \generator "nMigen" module \pipe1 - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire width 4 $0\alu_op__data_len$next[3:0]$9072 - attribute \src "libresoc.v:165459.3-165460.49" + attribute \src "libresoc.v:165458.3-165459.49" wire width 4 $0\alu_op__data_len[3:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire width 14 $0\alu_op__fn_unit$next[13:0]$9073 - attribute \src "libresoc.v:165429.3-165430.47" + attribute \src "libresoc.v:165428.3-165429.47" wire width 14 $0\alu_op__fn_unit[13:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire width 64 $0\alu_op__imm_data__data$next[63:0]$9074 - attribute \src "libresoc.v:165431.3-165432.61" + attribute \src "libresoc.v:165430.3-165431.61" wire width 64 $0\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $0\alu_op__imm_data__ok$next[0:0]$9075 - attribute \src "libresoc.v:165433.3-165434.57" + attribute \src "libresoc.v:165432.3-165433.57" wire $0\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire width 2 $0\alu_op__input_carry$next[1:0]$9076 - attribute \src "libresoc.v:165451.3-165452.55" + attribute \src "libresoc.v:165450.3-165451.55" wire width 2 $0\alu_op__input_carry[1:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire width 32 $0\alu_op__insn$next[31:0]$9077 - attribute \src "libresoc.v:165461.3-165462.41" + attribute \src "libresoc.v:165460.3-165461.41" wire width 32 $0\alu_op__insn[31:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire width 7 $0\alu_op__insn_type$next[6:0]$9078 - attribute \src "libresoc.v:165427.3-165428.51" + attribute \src "libresoc.v:165426.3-165427.51" wire width 7 $0\alu_op__insn_type[6:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $0\alu_op__invert_in$next[0:0]$9079 - attribute \src "libresoc.v:165443.3-165444.51" + attribute \src "libresoc.v:165442.3-165443.51" wire $0\alu_op__invert_in[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $0\alu_op__invert_out$next[0:0]$9080 - attribute \src "libresoc.v:165447.3-165448.53" + attribute \src "libresoc.v:165446.3-165447.53" wire $0\alu_op__invert_out[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $0\alu_op__is_32bit$next[0:0]$9081 - attribute \src "libresoc.v:165455.3-165456.49" + attribute \src "libresoc.v:165454.3-165455.49" wire $0\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $0\alu_op__is_signed$next[0:0]$9082 - attribute \src "libresoc.v:165457.3-165458.51" + attribute \src "libresoc.v:165456.3-165457.51" wire $0\alu_op__is_signed[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $0\alu_op__oe__oe$next[0:0]$9083 - attribute \src "libresoc.v:165439.3-165440.45" + attribute \src "libresoc.v:165438.3-165439.45" wire $0\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $0\alu_op__oe__ok$next[0:0]$9084 - attribute \src "libresoc.v:165441.3-165442.45" + attribute \src "libresoc.v:165440.3-165441.45" wire $0\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $0\alu_op__output_carry$next[0:0]$9085 - attribute \src "libresoc.v:165453.3-165454.57" + attribute \src "libresoc.v:165452.3-165453.57" wire $0\alu_op__output_carry[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $0\alu_op__rc__ok$next[0:0]$9086 - attribute \src "libresoc.v:165437.3-165438.45" + attribute \src "libresoc.v:165436.3-165437.45" wire $0\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $0\alu_op__rc__rc$next[0:0]$9087 - attribute \src "libresoc.v:165435.3-165436.45" + attribute \src "libresoc.v:165434.3-165435.45" wire $0\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $0\alu_op__write_cr0$next[0:0]$9088 - attribute \src "libresoc.v:165449.3-165450.51" + attribute \src "libresoc.v:165448.3-165449.51" wire $0\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $0\alu_op__zero_a$next[0:0]$9089 - attribute \src "libresoc.v:165445.3-165446.45" + attribute \src "libresoc.v:165444.3-165445.45" wire $0\alu_op__zero_a[0:0] - attribute \src "libresoc.v:165576.3-165594.6" + attribute \src "libresoc.v:165575.3-165593.6" wire width 4 $0\cr_a$next[3:0]$9041 - attribute \src "libresoc.v:165419.3-165420.25" + attribute \src "libresoc.v:165418.3-165419.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:165576.3-165594.6" + attribute \src "libresoc.v:165575.3-165593.6" wire $0\cr_a_ok$next[0:0]$9042 - attribute \src "libresoc.v:165421.3-165422.31" + attribute \src "libresoc.v:165420.3-165421.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:164278.7-164278.20" + attribute \src "libresoc.v:164277.7-164277.20" wire $0\initial[0:0] - attribute \src "libresoc.v:165670.3-165682.6" + attribute \src "libresoc.v:165669.3-165681.6" wire width 2 $0\muxid$next[1:0]$9069 - attribute \src "libresoc.v:165463.3-165464.27" + attribute \src "libresoc.v:165462.3-165463.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:165725.3-165743.6" + attribute \src "libresoc.v:165724.3-165742.6" wire width 64 $0\o$next[63:0]$9115 - attribute \src "libresoc.v:165423.3-165424.19" + attribute \src "libresoc.v:165422.3-165423.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:165725.3-165743.6" + attribute \src "libresoc.v:165724.3-165742.6" wire $0\o_ok$next[0:0]$9116 - attribute \src "libresoc.v:165425.3-165426.25" + attribute \src "libresoc.v:165424.3-165425.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:165652.3-165669.6" + attribute \src "libresoc.v:165651.3-165668.6" wire $0\r_busy$next[0:0]$9065 - attribute \src "libresoc.v:165465.3-165466.29" + attribute \src "libresoc.v:165464.3-165465.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:165595.3-165613.6" + attribute \src "libresoc.v:165594.3-165612.6" wire width 2 $0\xer_ca$next[1:0]$9048 - attribute \src "libresoc.v:165415.3-165416.29" + attribute \src "libresoc.v:165414.3-165415.29" wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:165595.3-165613.6" + attribute \src "libresoc.v:165594.3-165612.6" wire $0\xer_ca_ok$next[0:0]$9047 - attribute \src "libresoc.v:165417.3-165418.35" + attribute \src "libresoc.v:165416.3-165417.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:165614.3-165632.6" + attribute \src "libresoc.v:165613.3-165631.6" wire width 2 $0\xer_ov$next[1:0]$9053 - attribute \src "libresoc.v:165411.3-165412.29" + attribute \src "libresoc.v:165410.3-165411.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:165614.3-165632.6" + attribute \src "libresoc.v:165613.3-165631.6" wire $0\xer_ov_ok$next[0:0]$9054 - attribute \src "libresoc.v:165413.3-165414.35" + attribute \src "libresoc.v:165412.3-165413.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:165633.3-165651.6" + attribute \src "libresoc.v:165632.3-165650.6" wire $0\xer_so$next[0:0]$9059 - attribute \src "libresoc.v:165407.3-165408.29" + attribute \src "libresoc.v:165406.3-165407.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:165633.3-165651.6" + attribute \src "libresoc.v:165632.3-165650.6" wire $0\xer_so_ok$next[0:0]$9060 - attribute \src "libresoc.v:165409.3-165410.35" + attribute \src "libresoc.v:165408.3-165409.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire width 4 $1\alu_op__data_len$next[3:0]$9090 - attribute \src "libresoc.v:164283.13-164283.36" + attribute \src "libresoc.v:164282.13-164282.36" wire width 4 $1\alu_op__data_len[3:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire width 14 $1\alu_op__fn_unit$next[13:0]$9091 - attribute \src "libresoc.v:164307.14-164307.40" + attribute \src "libresoc.v:164306.14-164306.40" wire width 14 $1\alu_op__fn_unit[13:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire width 64 $1\alu_op__imm_data__data$next[63:0]$9092 - attribute \src "libresoc.v:164346.14-164346.59" + attribute \src "libresoc.v:164345.14-164345.59" wire width 64 $1\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $1\alu_op__imm_data__ok$next[0:0]$9093 - attribute \src "libresoc.v:164355.7-164355.34" + attribute \src "libresoc.v:164354.7-164354.34" wire $1\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire width 2 $1\alu_op__input_carry$next[1:0]$9094 - attribute \src "libresoc.v:164368.13-164368.39" + attribute \src "libresoc.v:164367.13-164367.39" wire width 2 $1\alu_op__input_carry[1:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire width 32 $1\alu_op__insn$next[31:0]$9095 - attribute \src "libresoc.v:164385.14-164385.34" + attribute \src "libresoc.v:164384.14-164384.34" wire width 32 $1\alu_op__insn[31:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire width 7 $1\alu_op__insn_type$next[6:0]$9096 - attribute \src "libresoc.v:164469.13-164469.38" + attribute \src "libresoc.v:164468.13-164468.38" wire width 7 $1\alu_op__insn_type[6:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $1\alu_op__invert_in$next[0:0]$9097 - attribute \src "libresoc.v:164628.7-164628.31" + attribute \src "libresoc.v:164627.7-164627.31" wire $1\alu_op__invert_in[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $1\alu_op__invert_out$next[0:0]$9098 - attribute \src "libresoc.v:164637.7-164637.32" + attribute \src "libresoc.v:164636.7-164636.32" wire $1\alu_op__invert_out[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $1\alu_op__is_32bit$next[0:0]$9099 - attribute \src "libresoc.v:164646.7-164646.30" + attribute \src "libresoc.v:164645.7-164645.30" wire $1\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $1\alu_op__is_signed$next[0:0]$9100 - attribute \src "libresoc.v:164655.7-164655.31" + attribute \src "libresoc.v:164654.7-164654.31" wire $1\alu_op__is_signed[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $1\alu_op__oe__oe$next[0:0]$9101 - attribute \src "libresoc.v:164664.7-164664.28" + attribute \src "libresoc.v:164663.7-164663.28" wire $1\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $1\alu_op__oe__ok$next[0:0]$9102 - attribute \src "libresoc.v:164673.7-164673.28" + attribute \src "libresoc.v:164672.7-164672.28" wire $1\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $1\alu_op__output_carry$next[0:0]$9103 - attribute \src "libresoc.v:164682.7-164682.34" + attribute \src "libresoc.v:164681.7-164681.34" wire $1\alu_op__output_carry[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $1\alu_op__rc__ok$next[0:0]$9104 - attribute \src "libresoc.v:164691.7-164691.28" + attribute \src "libresoc.v:164690.7-164690.28" wire $1\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $1\alu_op__rc__rc$next[0:0]$9105 - attribute \src "libresoc.v:164700.7-164700.28" + attribute \src "libresoc.v:164699.7-164699.28" wire $1\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $1\alu_op__write_cr0$next[0:0]$9106 - attribute \src "libresoc.v:164709.7-164709.31" + attribute \src "libresoc.v:164708.7-164708.31" wire $1\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $1\alu_op__zero_a$next[0:0]$9107 - attribute \src "libresoc.v:164718.7-164718.28" + attribute \src "libresoc.v:164717.7-164717.28" wire $1\alu_op__zero_a[0:0] - attribute \src "libresoc.v:165576.3-165594.6" + attribute \src "libresoc.v:165575.3-165593.6" wire width 4 $1\cr_a$next[3:0]$9043 - attribute \src "libresoc.v:164731.13-164731.24" + attribute \src "libresoc.v:164730.13-164730.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:165576.3-165594.6" + attribute \src "libresoc.v:165575.3-165593.6" wire $1\cr_a_ok$next[0:0]$9044 - attribute \src "libresoc.v:164738.7-164738.21" + attribute \src "libresoc.v:164737.7-164737.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:165670.3-165682.6" + attribute \src "libresoc.v:165669.3-165681.6" wire width 2 $1\muxid$next[1:0]$9070 - attribute \src "libresoc.v:165315.13-165315.25" + attribute \src "libresoc.v:165314.13-165314.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:165725.3-165743.6" + attribute \src "libresoc.v:165724.3-165742.6" wire width 64 $1\o$next[63:0]$9117 - attribute \src "libresoc.v:165330.14-165330.38" + attribute \src "libresoc.v:165329.14-165329.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:165725.3-165743.6" + attribute \src "libresoc.v:165724.3-165742.6" wire $1\o_ok$next[0:0]$9118 - attribute \src "libresoc.v:165337.7-165337.18" + attribute \src "libresoc.v:165336.7-165336.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:165652.3-165669.6" + attribute \src "libresoc.v:165651.3-165668.6" wire $1\r_busy$next[0:0]$9066 - attribute \src "libresoc.v:165351.7-165351.20" + attribute \src "libresoc.v:165350.7-165350.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:165595.3-165613.6" + attribute \src "libresoc.v:165594.3-165612.6" wire width 2 $1\xer_ca$next[1:0]$9050 - attribute \src "libresoc.v:165360.13-165360.26" + attribute \src "libresoc.v:165359.13-165359.26" wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:165595.3-165613.6" + attribute \src "libresoc.v:165594.3-165612.6" wire $1\xer_ca_ok$next[0:0]$9049 - attribute \src "libresoc.v:165369.7-165369.23" + attribute \src "libresoc.v:165368.7-165368.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:165614.3-165632.6" + attribute \src "libresoc.v:165613.3-165631.6" wire width 2 $1\xer_ov$next[1:0]$9055 - attribute \src "libresoc.v:165376.13-165376.26" + attribute \src "libresoc.v:165375.13-165375.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:165614.3-165632.6" + attribute \src "libresoc.v:165613.3-165631.6" wire $1\xer_ov_ok$next[0:0]$9056 - attribute \src "libresoc.v:165383.7-165383.23" + attribute \src "libresoc.v:165382.7-165382.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:165633.3-165651.6" + attribute \src "libresoc.v:165632.3-165650.6" wire $1\xer_so$next[0:0]$9061 - attribute \src "libresoc.v:165390.7-165390.20" + attribute \src "libresoc.v:165389.7-165389.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:165633.3-165651.6" + attribute \src "libresoc.v:165632.3-165650.6" wire $1\xer_so_ok$next[0:0]$9062 - attribute \src "libresoc.v:165399.7-165399.23" + attribute \src "libresoc.v:165398.7-165398.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire width 64 $2\alu_op__imm_data__data$next[63:0]$9108 - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $2\alu_op__imm_data__ok$next[0:0]$9109 - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $2\alu_op__oe__oe$next[0:0]$9110 - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $2\alu_op__oe__ok$next[0:0]$9111 - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $2\alu_op__rc__ok$next[0:0]$9112 - attribute \src "libresoc.v:165683.3-165724.6" + attribute \src "libresoc.v:165682.3-165723.6" wire $2\alu_op__rc__rc$next[0:0]$9113 - attribute \src "libresoc.v:165576.3-165594.6" + attribute \src "libresoc.v:165575.3-165593.6" wire $2\cr_a_ok$next[0:0]$9045 - attribute \src "libresoc.v:165725.3-165743.6" + attribute \src "libresoc.v:165724.3-165742.6" wire $2\o_ok$next[0:0]$9119 - attribute \src "libresoc.v:165652.3-165669.6" + attribute \src "libresoc.v:165651.3-165668.6" wire $2\r_busy$next[0:0]$9067 - attribute \src "libresoc.v:165595.3-165613.6" + attribute \src "libresoc.v:165594.3-165612.6" wire $2\xer_ca_ok$next[0:0]$9051 - attribute \src "libresoc.v:165614.3-165632.6" + attribute \src "libresoc.v:165613.3-165631.6" wire $2\xer_ov_ok$next[0:0]$9057 - attribute \src "libresoc.v:165633.3-165651.6" + attribute \src "libresoc.v:165632.3-165650.6" wire $2\xer_so_ok$next[0:0]$9063 - attribute \src "libresoc.v:165406.18-165406.118" - wire $and$libresoc.v:165406$9009_Y + attribute \src "libresoc.v:165405.18-165405.118" + wire $and$libresoc.v:165405$9009_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -340827,7 +337637,7 @@ module \pipe1 wire \cr_a_ok$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:164278.7-164278.15" + attribute \src "libresoc.v:164277.7-164277.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_alu_op__data_len @@ -341484,7 +338294,7 @@ module \pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:165406$9009 + cell $and $and$libresoc.v:165405$9009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -341492,10 +338302,10 @@ module \pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$66 connect \B \p_ready_o - connect \Y $and$libresoc.v:165406$9009_Y + connect \Y $and$libresoc.v:165405$9009_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:165467.11-165514.4" + attribute \src "libresoc.v:165466.11-165513.4" cell \input \input connect \alu_op__data_len \input_alu_op__data_len connect \alu_op__data_len$18 \input_alu_op__data_len$39 @@ -341545,7 +338355,7 @@ module \pipe1 connect \xer_so$22 \input_xer_so$43 end attribute \module_not_derived 1 - attribute \src "libresoc.v:165515.8-165567.4" + attribute \src "libresoc.v:165514.8-165566.4" cell \main \main connect \alu_op__data_len \main_alu_op__data_len connect \alu_op__data_len$18 \main_alu_op__data_len$62 @@ -341600,477 +338410,477 @@ module \pipe1 connect \xer_so$21 \main_xer_so$65 end attribute \module_not_derived 1 - attribute \src "libresoc.v:165568.9-165571.4" + attribute \src "libresoc.v:165567.9-165570.4" cell \n$2 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:165572.9-165575.4" + attribute \src "libresoc.v:165571.9-165574.4" cell \p$1 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:164278.7-164278.20" - process $proc$libresoc.v:164278$9120 + attribute \src "libresoc.v:164277.7-164277.20" + process $proc$libresoc.v:164277$9120 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:164283.13-164283.36" - process $proc$libresoc.v:164283$9121 + attribute \src "libresoc.v:164282.13-164282.36" + process $proc$libresoc.v:164282$9121 assign { } { } assign $1\alu_op__data_len[3:0] 4'0000 sync always sync init update \alu_op__data_len $1\alu_op__data_len[3:0] end - attribute \src "libresoc.v:164307.14-164307.40" - process $proc$libresoc.v:164307$9122 + attribute \src "libresoc.v:164306.14-164306.40" + process $proc$libresoc.v:164306$9122 assign { } { } assign $1\alu_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_op__fn_unit $1\alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:164346.14-164346.59" - process $proc$libresoc.v:164346$9123 + attribute \src "libresoc.v:164345.14-164345.59" + process $proc$libresoc.v:164345$9123 assign { } { } assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:164355.7-164355.34" - process $proc$libresoc.v:164355$9124 + attribute \src "libresoc.v:164354.7-164354.34" + process $proc$libresoc.v:164354$9124 assign { } { } assign $1\alu_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:164368.13-164368.39" - process $proc$libresoc.v:164368$9125 + attribute \src "libresoc.v:164367.13-164367.39" + process $proc$libresoc.v:164367$9125 assign { } { } assign $1\alu_op__input_carry[1:0] 2'00 sync always sync init update \alu_op__input_carry $1\alu_op__input_carry[1:0] end - attribute \src "libresoc.v:164385.14-164385.34" - process $proc$libresoc.v:164385$9126 + attribute \src "libresoc.v:164384.14-164384.34" + process $proc$libresoc.v:164384$9126 assign { } { } assign $1\alu_op__insn[31:0] 0 sync always sync init update \alu_op__insn $1\alu_op__insn[31:0] end - attribute \src "libresoc.v:164469.13-164469.38" - process $proc$libresoc.v:164469$9127 + attribute \src "libresoc.v:164468.13-164468.38" + process $proc$libresoc.v:164468$9127 assign { } { } assign $1\alu_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_op__insn_type $1\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:164628.7-164628.31" - process $proc$libresoc.v:164628$9128 + attribute \src "libresoc.v:164627.7-164627.31" + process $proc$libresoc.v:164627$9128 assign { } { } assign $1\alu_op__invert_in[0:0] 1'0 sync always sync init update \alu_op__invert_in $1\alu_op__invert_in[0:0] end - attribute \src "libresoc.v:164637.7-164637.32" - process $proc$libresoc.v:164637$9129 + attribute \src "libresoc.v:164636.7-164636.32" + process $proc$libresoc.v:164636$9129 assign { } { } assign $1\alu_op__invert_out[0:0] 1'0 sync always sync init update \alu_op__invert_out $1\alu_op__invert_out[0:0] end - attribute \src "libresoc.v:164646.7-164646.30" - process $proc$libresoc.v:164646$9130 + attribute \src "libresoc.v:164645.7-164645.30" + process $proc$libresoc.v:164645$9130 assign { } { } assign $1\alu_op__is_32bit[0:0] 1'0 sync always sync init update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:164655.7-164655.31" - process $proc$libresoc.v:164655$9131 + attribute \src "libresoc.v:164654.7-164654.31" + process $proc$libresoc.v:164654$9131 assign { } { } assign $1\alu_op__is_signed[0:0] 1'0 sync always sync init update \alu_op__is_signed $1\alu_op__is_signed[0:0] end - attribute \src "libresoc.v:164664.7-164664.28" - process $proc$libresoc.v:164664$9132 + attribute \src "libresoc.v:164663.7-164663.28" + process $proc$libresoc.v:164663$9132 assign { } { } assign $1\alu_op__oe__oe[0:0] 1'0 sync always sync init update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:164673.7-164673.28" - process $proc$libresoc.v:164673$9133 + attribute \src "libresoc.v:164672.7-164672.28" + process $proc$libresoc.v:164672$9133 assign { } { } assign $1\alu_op__oe__ok[0:0] 1'0 sync always sync init update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:164682.7-164682.34" - process $proc$libresoc.v:164682$9134 + attribute \src "libresoc.v:164681.7-164681.34" + process $proc$libresoc.v:164681$9134 assign { } { } assign $1\alu_op__output_carry[0:0] 1'0 sync always sync init update \alu_op__output_carry $1\alu_op__output_carry[0:0] end - attribute \src "libresoc.v:164691.7-164691.28" - process $proc$libresoc.v:164691$9135 + attribute \src "libresoc.v:164690.7-164690.28" + process $proc$libresoc.v:164690$9135 assign { } { } assign $1\alu_op__rc__ok[0:0] 1'0 sync always sync init update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:164700.7-164700.28" - process $proc$libresoc.v:164700$9136 + attribute \src "libresoc.v:164699.7-164699.28" + process $proc$libresoc.v:164699$9136 assign { } { } assign $1\alu_op__rc__rc[0:0] 1'0 sync always sync init update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:164709.7-164709.31" - process $proc$libresoc.v:164709$9137 + attribute \src "libresoc.v:164708.7-164708.31" + process $proc$libresoc.v:164708$9137 assign { } { } assign $1\alu_op__write_cr0[0:0] 1'0 sync always sync init update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:164718.7-164718.28" - process $proc$libresoc.v:164718$9138 + attribute \src "libresoc.v:164717.7-164717.28" + process $proc$libresoc.v:164717$9138 assign { } { } assign $1\alu_op__zero_a[0:0] 1'0 sync always sync init update \alu_op__zero_a $1\alu_op__zero_a[0:0] end - attribute \src "libresoc.v:164731.13-164731.24" - process $proc$libresoc.v:164731$9139 + attribute \src "libresoc.v:164730.13-164730.24" + process $proc$libresoc.v:164730$9139 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:164738.7-164738.21" - process $proc$libresoc.v:164738$9140 + attribute \src "libresoc.v:164737.7-164737.21" + process $proc$libresoc.v:164737$9140 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:165315.13-165315.25" - process $proc$libresoc.v:165315$9141 + attribute \src "libresoc.v:165314.13-165314.25" + process $proc$libresoc.v:165314$9141 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:165330.14-165330.38" - process $proc$libresoc.v:165330$9142 + attribute \src "libresoc.v:165329.14-165329.38" + process $proc$libresoc.v:165329$9142 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:165337.7-165337.18" - process $proc$libresoc.v:165337$9143 + attribute \src "libresoc.v:165336.7-165336.18" + process $proc$libresoc.v:165336$9143 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:165351.7-165351.20" - process $proc$libresoc.v:165351$9144 + attribute \src "libresoc.v:165350.7-165350.20" + process $proc$libresoc.v:165350$9144 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:165360.13-165360.26" - process $proc$libresoc.v:165360$9145 + attribute \src "libresoc.v:165359.13-165359.26" + process $proc$libresoc.v:165359$9145 assign { } { } assign $1\xer_ca[1:0] 2'00 sync always sync init update \xer_ca $1\xer_ca[1:0] end - attribute \src "libresoc.v:165369.7-165369.23" - process $proc$libresoc.v:165369$9146 + attribute \src "libresoc.v:165368.7-165368.23" + process $proc$libresoc.v:165368$9146 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:165376.13-165376.26" - process $proc$libresoc.v:165376$9147 + attribute \src "libresoc.v:165375.13-165375.26" + process $proc$libresoc.v:165375$9147 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:165383.7-165383.23" - process $proc$libresoc.v:165383$9148 + attribute \src "libresoc.v:165382.7-165382.23" + process $proc$libresoc.v:165382$9148 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:165390.7-165390.20" - process $proc$libresoc.v:165390$9149 + attribute \src "libresoc.v:165389.7-165389.20" + process $proc$libresoc.v:165389$9149 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:165399.7-165399.23" - process $proc$libresoc.v:165399$9150 + attribute \src "libresoc.v:165398.7-165398.23" + process $proc$libresoc.v:165398$9150 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:165407.3-165408.29" - process $proc$libresoc.v:165407$9010 + attribute \src "libresoc.v:165406.3-165407.29" + process $proc$libresoc.v:165406$9010 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:165409.3-165410.35" - process $proc$libresoc.v:165409$9011 + attribute \src "libresoc.v:165408.3-165409.35" + process $proc$libresoc.v:165408$9011 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:165411.3-165412.29" - process $proc$libresoc.v:165411$9012 + attribute \src "libresoc.v:165410.3-165411.29" + process $proc$libresoc.v:165410$9012 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:165413.3-165414.35" - process $proc$libresoc.v:165413$9013 + attribute \src "libresoc.v:165412.3-165413.35" + process $proc$libresoc.v:165412$9013 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:165415.3-165416.29" - process $proc$libresoc.v:165415$9014 + attribute \src "libresoc.v:165414.3-165415.29" + process $proc$libresoc.v:165414$9014 assign { } { } assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:165417.3-165418.35" - process $proc$libresoc.v:165417$9015 + attribute \src "libresoc.v:165416.3-165417.35" + process $proc$libresoc.v:165416$9015 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:165419.3-165420.25" - process $proc$libresoc.v:165419$9016 + attribute \src "libresoc.v:165418.3-165419.25" + process $proc$libresoc.v:165418$9016 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:165421.3-165422.31" - process $proc$libresoc.v:165421$9017 + attribute \src "libresoc.v:165420.3-165421.31" + process $proc$libresoc.v:165420$9017 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:165423.3-165424.19" - process $proc$libresoc.v:165423$9018 + attribute \src "libresoc.v:165422.3-165423.19" + process $proc$libresoc.v:165422$9018 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:165425.3-165426.25" - process $proc$libresoc.v:165425$9019 + attribute \src "libresoc.v:165424.3-165425.25" + process $proc$libresoc.v:165424$9019 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:165427.3-165428.51" - process $proc$libresoc.v:165427$9020 + attribute \src "libresoc.v:165426.3-165427.51" + process $proc$libresoc.v:165426$9020 assign { } { } assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next sync posedge \coresync_clk update \alu_op__insn_type $0\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:165429.3-165430.47" - process $proc$libresoc.v:165429$9021 + attribute \src "libresoc.v:165428.3-165429.47" + process $proc$libresoc.v:165428$9021 assign { } { } assign $0\alu_op__fn_unit[13:0] \alu_op__fn_unit$next sync posedge \coresync_clk update \alu_op__fn_unit $0\alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:165431.3-165432.61" - process $proc$libresoc.v:165431$9022 + attribute \src "libresoc.v:165430.3-165431.61" + process $proc$libresoc.v:165430$9022 assign { } { } assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next sync posedge \coresync_clk update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:165433.3-165434.57" - process $proc$libresoc.v:165433$9023 + attribute \src "libresoc.v:165432.3-165433.57" + process $proc$libresoc.v:165432$9023 assign { } { } assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next sync posedge \coresync_clk update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:165435.3-165436.45" - process $proc$libresoc.v:165435$9024 + attribute \src "libresoc.v:165434.3-165435.45" + process $proc$libresoc.v:165434$9024 assign { } { } assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next sync posedge \coresync_clk update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:165437.3-165438.45" - process $proc$libresoc.v:165437$9025 + attribute \src "libresoc.v:165436.3-165437.45" + process $proc$libresoc.v:165436$9025 assign { } { } assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next sync posedge \coresync_clk update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:165439.3-165440.45" - process $proc$libresoc.v:165439$9026 + attribute \src "libresoc.v:165438.3-165439.45" + process $proc$libresoc.v:165438$9026 assign { } { } assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next sync posedge \coresync_clk update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:165441.3-165442.45" - process $proc$libresoc.v:165441$9027 + attribute \src "libresoc.v:165440.3-165441.45" + process $proc$libresoc.v:165440$9027 assign { } { } assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next sync posedge \coresync_clk update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:165443.3-165444.51" - process $proc$libresoc.v:165443$9028 + attribute \src "libresoc.v:165442.3-165443.51" + process $proc$libresoc.v:165442$9028 assign { } { } assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next sync posedge \coresync_clk update \alu_op__invert_in $0\alu_op__invert_in[0:0] end - attribute \src "libresoc.v:165445.3-165446.45" - process $proc$libresoc.v:165445$9029 + attribute \src "libresoc.v:165444.3-165445.45" + process $proc$libresoc.v:165444$9029 assign { } { } assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next sync posedge \coresync_clk update \alu_op__zero_a $0\alu_op__zero_a[0:0] end - attribute \src "libresoc.v:165447.3-165448.53" - process $proc$libresoc.v:165447$9030 + attribute \src "libresoc.v:165446.3-165447.53" + process $proc$libresoc.v:165446$9030 assign { } { } assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next sync posedge \coresync_clk update \alu_op__invert_out $0\alu_op__invert_out[0:0] end - attribute \src "libresoc.v:165449.3-165450.51" - process $proc$libresoc.v:165449$9031 + attribute \src "libresoc.v:165448.3-165449.51" + process $proc$libresoc.v:165448$9031 assign { } { } assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next sync posedge \coresync_clk update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:165451.3-165452.55" - process $proc$libresoc.v:165451$9032 + attribute \src "libresoc.v:165450.3-165451.55" + process $proc$libresoc.v:165450$9032 assign { } { } assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next sync posedge \coresync_clk update \alu_op__input_carry $0\alu_op__input_carry[1:0] end - attribute \src "libresoc.v:165453.3-165454.57" - process $proc$libresoc.v:165453$9033 + attribute \src "libresoc.v:165452.3-165453.57" + process $proc$libresoc.v:165452$9033 assign { } { } assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next sync posedge \coresync_clk update \alu_op__output_carry $0\alu_op__output_carry[0:0] end - attribute \src "libresoc.v:165455.3-165456.49" - process $proc$libresoc.v:165455$9034 + attribute \src "libresoc.v:165454.3-165455.49" + process $proc$libresoc.v:165454$9034 assign { } { } assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next sync posedge \coresync_clk update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:165457.3-165458.51" - process $proc$libresoc.v:165457$9035 + attribute \src "libresoc.v:165456.3-165457.51" + process $proc$libresoc.v:165456$9035 assign { } { } assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next sync posedge \coresync_clk update \alu_op__is_signed $0\alu_op__is_signed[0:0] end - attribute \src "libresoc.v:165459.3-165460.49" - process $proc$libresoc.v:165459$9036 + attribute \src "libresoc.v:165458.3-165459.49" + process $proc$libresoc.v:165458$9036 assign { } { } assign $0\alu_op__data_len[3:0] \alu_op__data_len$next sync posedge \coresync_clk update \alu_op__data_len $0\alu_op__data_len[3:0] end - attribute \src "libresoc.v:165461.3-165462.41" - process $proc$libresoc.v:165461$9037 + attribute \src "libresoc.v:165460.3-165461.41" + process $proc$libresoc.v:165460$9037 assign { } { } assign $0\alu_op__insn[31:0] \alu_op__insn$next sync posedge \coresync_clk update \alu_op__insn $0\alu_op__insn[31:0] end - attribute \src "libresoc.v:165463.3-165464.27" - process $proc$libresoc.v:165463$9038 + attribute \src "libresoc.v:165462.3-165463.27" + process $proc$libresoc.v:165462$9038 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:165465.3-165466.29" - process $proc$libresoc.v:165465$9039 + attribute \src "libresoc.v:165464.3-165465.29" + process $proc$libresoc.v:165464$9039 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:165576.3-165594.6" - process $proc$libresoc.v:165576$9040 + attribute \src "libresoc.v:165575.3-165593.6" + process $proc$libresoc.v:165575$9040 assign { } { } assign { } { } assign { } { } @@ -342078,9 +338888,9 @@ module \pipe1 assign $0\cr_a$next[3:0]$9041 $1\cr_a$next[3:0]$9043 assign { } { } assign $0\cr_a_ok$next[0:0]$9042 $2\cr_a_ok$next[0:0]$9045 - attribute \src "libresoc.v:165577.5-165577.29" + attribute \src "libresoc.v:165576.5-165576.29" switch \initial - attribute \src "libresoc.v:165577.9-165577.17" + attribute \src "libresoc.v:165576.9-165576.17" case 1'1 case end @@ -342113,8 +338923,8 @@ module \pipe1 update \cr_a$next $0\cr_a$next[3:0]$9041 update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9042 end - attribute \src "libresoc.v:165595.3-165613.6" - process $proc$libresoc.v:165595$9046 + attribute \src "libresoc.v:165594.3-165612.6" + process $proc$libresoc.v:165594$9046 assign { } { } assign { } { } assign { } { } @@ -342122,9 +338932,9 @@ module \pipe1 assign { } { } assign $0\xer_ca$next[1:0]$9048 $1\xer_ca$next[1:0]$9050 assign $0\xer_ca_ok$next[0:0]$9047 $2\xer_ca_ok$next[0:0]$9051 - attribute \src "libresoc.v:165596.5-165596.29" + attribute \src "libresoc.v:165595.5-165595.29" switch \initial - attribute \src "libresoc.v:165596.9-165596.17" + attribute \src "libresoc.v:165595.9-165595.17" case 1'1 case end @@ -342157,8 +338967,8 @@ module \pipe1 update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9047 update \xer_ca$next $0\xer_ca$next[1:0]$9048 end - attribute \src "libresoc.v:165614.3-165632.6" - process $proc$libresoc.v:165614$9052 + attribute \src "libresoc.v:165613.3-165631.6" + process $proc$libresoc.v:165613$9052 assign { } { } assign { } { } assign { } { } @@ -342166,9 +338976,9 @@ module \pipe1 assign $0\xer_ov$next[1:0]$9053 $1\xer_ov$next[1:0]$9055 assign { } { } assign $0\xer_ov_ok$next[0:0]$9054 $2\xer_ov_ok$next[0:0]$9057 - attribute \src "libresoc.v:165615.5-165615.29" + attribute \src "libresoc.v:165614.5-165614.29" switch \initial - attribute \src "libresoc.v:165615.9-165615.17" + attribute \src "libresoc.v:165614.9-165614.17" case 1'1 case end @@ -342201,8 +339011,8 @@ module \pipe1 update \xer_ov$next $0\xer_ov$next[1:0]$9053 update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9054 end - attribute \src "libresoc.v:165633.3-165651.6" - process $proc$libresoc.v:165633$9058 + attribute \src "libresoc.v:165632.3-165650.6" + process $proc$libresoc.v:165632$9058 assign { } { } assign { } { } assign { } { } @@ -342210,9 +339020,9 @@ module \pipe1 assign $0\xer_so$next[0:0]$9059 $1\xer_so$next[0:0]$9061 assign { } { } assign $0\xer_so_ok$next[0:0]$9060 $2\xer_so_ok$next[0:0]$9063 - attribute \src "libresoc.v:165634.5-165634.29" + attribute \src "libresoc.v:165633.5-165633.29" switch \initial - attribute \src "libresoc.v:165634.9-165634.17" + attribute \src "libresoc.v:165633.9-165633.17" case 1'1 case end @@ -342245,15 +339055,15 @@ module \pipe1 update \xer_so$next $0\xer_so$next[0:0]$9059 update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9060 end - attribute \src "libresoc.v:165652.3-165669.6" - process $proc$libresoc.v:165652$9064 + attribute \src "libresoc.v:165651.3-165668.6" + process $proc$libresoc.v:165651$9064 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9065 $2\r_busy$next[0:0]$9067 - attribute \src "libresoc.v:165653.5-165653.29" + attribute \src "libresoc.v:165652.5-165652.29" switch \initial - attribute \src "libresoc.v:165653.9-165653.17" + attribute \src "libresoc.v:165652.9-165652.17" case 1'1 case end @@ -342282,14 +339092,14 @@ module \pipe1 sync always update \r_busy$next $0\r_busy$next[0:0]$9065 end - attribute \src "libresoc.v:165670.3-165682.6" - process $proc$libresoc.v:165670$9068 + attribute \src "libresoc.v:165669.3-165681.6" + process $proc$libresoc.v:165669$9068 assign { } { } assign { } { } assign $0\muxid$next[1:0]$9069 $1\muxid$next[1:0]$9070 - attribute \src "libresoc.v:165671.5-165671.29" + attribute \src "libresoc.v:165670.5-165670.29" switch \initial - attribute \src "libresoc.v:165671.9-165671.17" + attribute \src "libresoc.v:165670.9-165670.17" case 1'1 case end @@ -342309,8 +339119,8 @@ module \pipe1 sync always update \muxid$next $0\muxid$next[1:0]$9069 end - attribute \src "libresoc.v:165683.3-165724.6" - process $proc$libresoc.v:165683$9071 + attribute \src "libresoc.v:165682.3-165723.6" + process $proc$libresoc.v:165682$9071 assign { } { } assign { } { } assign { } { } @@ -342371,9 +339181,9 @@ module \pipe1 assign $0\alu_op__oe__ok$next[0:0]$9084 $2\alu_op__oe__ok$next[0:0]$9111 assign $0\alu_op__rc__ok$next[0:0]$9086 $2\alu_op__rc__ok$next[0:0]$9112 assign $0\alu_op__rc__rc$next[0:0]$9087 $2\alu_op__rc__rc$next[0:0]$9113 - attribute \src "libresoc.v:165684.5-165684.29" + attribute \src "libresoc.v:165683.5-165683.29" switch \initial - attribute \src "libresoc.v:165684.9-165684.17" + attribute \src "libresoc.v:165683.9-165683.17" case 1'1 case end @@ -342485,8 +339295,8 @@ module \pipe1 update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9088 update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9089 end - attribute \src "libresoc.v:165725.3-165743.6" - process $proc$libresoc.v:165725$9114 + attribute \src "libresoc.v:165724.3-165742.6" + process $proc$libresoc.v:165724$9114 assign { } { } assign { } { } assign { } { } @@ -342494,9 +339304,9 @@ module \pipe1 assign $0\o$next[63:0]$9115 $1\o$next[63:0]$9117 assign { } { } assign $0\o_ok$next[0:0]$9116 $2\o_ok$next[0:0]$9119 - attribute \src "libresoc.v:165726.5-165726.29" + attribute \src "libresoc.v:165725.5-165725.29" switch \initial - attribute \src "libresoc.v:165726.9-165726.17" + attribute \src "libresoc.v:165725.9-165725.17" case 1'1 case end @@ -342529,7 +339339,7 @@ module \pipe1 update \o$next $0\o$next[63:0]$9115 update \o_ok$next $0\o_ok$next[0:0]$9116 end - connect \$67 $and$libresoc.v:165406$9009_Y + connect \$67 $and$libresoc.v:165405$9009_Y connect \xer_so_ok$98 1'0 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy @@ -342556,253 +339366,253 @@ module \pipe1 connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:165773.1-167209.10" +attribute \src "libresoc.v:165772.1-167208.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" attribute \generator "nMigen" module \pipe1$110 - attribute \src "libresoc.v:167142.3-167160.6" + attribute \src "libresoc.v:167141.3-167159.6" wire width 4 $0\cr_a$next[3:0]$9240 - attribute \src "libresoc.v:166884.3-166885.25" + attribute \src "libresoc.v:166883.3-166884.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:167142.3-167160.6" + attribute \src "libresoc.v:167141.3-167159.6" wire $0\cr_a_ok$next[0:0]$9241 - attribute \src "libresoc.v:166886.3-166887.31" + attribute \src "libresoc.v:166885.3-166886.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:165774.7-165774.20" + attribute \src "libresoc.v:165773.7-165773.20" wire $0\initial[0:0] - attribute \src "libresoc.v:167069.3-167081.6" + attribute \src "libresoc.v:167068.3-167080.6" wire width 2 $0\muxid$next[1:0]$9190 - attribute \src "libresoc.v:166926.3-166927.27" + attribute \src "libresoc.v:166925.3-166926.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:167123.3-167141.6" + attribute \src "libresoc.v:167122.3-167140.6" wire width 64 $0\o$next[63:0]$9234 - attribute \src "libresoc.v:166888.3-166889.19" + attribute \src "libresoc.v:166887.3-166888.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:167123.3-167141.6" + attribute \src "libresoc.v:167122.3-167140.6" wire $0\o_ok$next[0:0]$9235 - attribute \src "libresoc.v:166890.3-166891.25" + attribute \src "libresoc.v:166889.3-166890.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:167051.3-167068.6" + attribute \src "libresoc.v:167050.3-167067.6" wire $0\r_busy$next[0:0]$9186 - attribute \src "libresoc.v:166928.3-166929.29" + attribute \src "libresoc.v:166927.3-166928.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire width 14 $0\sr_op__fn_unit$next[13:0]$9193 - attribute \src "libresoc.v:166894.3-166895.45" + attribute \src "libresoc.v:166893.3-166894.45" wire width 14 $0\sr_op__fn_unit[13:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire width 64 $0\sr_op__imm_data__data$next[63:0]$9194 - attribute \src "libresoc.v:166896.3-166897.59" + attribute \src "libresoc.v:166895.3-166896.59" wire width 64 $0\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $0\sr_op__imm_data__ok$next[0:0]$9195 - attribute \src "libresoc.v:166898.3-166899.55" + attribute \src "libresoc.v:166897.3-166898.55" wire $0\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire width 2 $0\sr_op__input_carry$next[1:0]$9196 - attribute \src "libresoc.v:166912.3-166913.53" + attribute \src "libresoc.v:166911.3-166912.53" wire width 2 $0\sr_op__input_carry[1:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $0\sr_op__input_cr$next[0:0]$9197 - attribute \src "libresoc.v:166916.3-166917.47" + attribute \src "libresoc.v:166915.3-166916.47" wire $0\sr_op__input_cr[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire width 32 $0\sr_op__insn$next[31:0]$9198 - attribute \src "libresoc.v:166924.3-166925.39" + attribute \src "libresoc.v:166923.3-166924.39" wire width 32 $0\sr_op__insn[31:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire width 7 $0\sr_op__insn_type$next[6:0]$9199 - attribute \src "libresoc.v:166892.3-166893.49" + attribute \src "libresoc.v:166891.3-166892.49" wire width 7 $0\sr_op__insn_type[6:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $0\sr_op__invert_in$next[0:0]$9200 - attribute \src "libresoc.v:166910.3-166911.49" + attribute \src "libresoc.v:166909.3-166910.49" wire $0\sr_op__invert_in[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $0\sr_op__is_32bit$next[0:0]$9201 - attribute \src "libresoc.v:166920.3-166921.47" + attribute \src "libresoc.v:166919.3-166920.47" wire $0\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $0\sr_op__is_signed$next[0:0]$9202 - attribute \src "libresoc.v:166922.3-166923.49" + attribute \src "libresoc.v:166921.3-166922.49" wire $0\sr_op__is_signed[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $0\sr_op__oe__oe$next[0:0]$9203 - attribute \src "libresoc.v:166904.3-166905.43" + attribute \src "libresoc.v:166903.3-166904.43" wire $0\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $0\sr_op__oe__ok$next[0:0]$9204 - attribute \src "libresoc.v:166906.3-166907.43" + attribute \src "libresoc.v:166905.3-166906.43" wire $0\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $0\sr_op__output_carry$next[0:0]$9205 - attribute \src "libresoc.v:166914.3-166915.55" + attribute \src "libresoc.v:166913.3-166914.55" wire $0\sr_op__output_carry[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $0\sr_op__output_cr$next[0:0]$9206 - attribute \src "libresoc.v:166918.3-166919.49" + attribute \src "libresoc.v:166917.3-166918.49" wire $0\sr_op__output_cr[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $0\sr_op__rc__ok$next[0:0]$9207 - attribute \src "libresoc.v:166902.3-166903.43" + attribute \src "libresoc.v:166901.3-166902.43" wire $0\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $0\sr_op__rc__rc$next[0:0]$9208 - attribute \src "libresoc.v:166900.3-166901.43" + attribute \src "libresoc.v:166899.3-166900.43" wire $0\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $0\sr_op__write_cr0$next[0:0]$9209 - attribute \src "libresoc.v:166908.3-166909.49" + attribute \src "libresoc.v:166907.3-166908.49" wire $0\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:167032.3-167050.6" + attribute \src "libresoc.v:167031.3-167049.6" wire width 2 $0\xer_ca$next[1:0]$9181 - attribute \src "libresoc.v:166876.3-166877.29" + attribute \src "libresoc.v:166875.3-166876.29" wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:167032.3-167050.6" + attribute \src "libresoc.v:167031.3-167049.6" wire $0\xer_ca_ok$next[0:0]$9180 - attribute \src "libresoc.v:166878.3-166879.35" + attribute \src "libresoc.v:166877.3-166878.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:167161.3-167179.6" + attribute \src "libresoc.v:167160.3-167178.6" wire $0\xer_so$next[0:0]$9246 - attribute \src "libresoc.v:166880.3-166881.29" + attribute \src "libresoc.v:166879.3-166880.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:167161.3-167179.6" + attribute \src "libresoc.v:167160.3-167178.6" wire $0\xer_so_ok$next[0:0]$9247 - attribute \src "libresoc.v:166882.3-166883.35" + attribute \src "libresoc.v:166881.3-166882.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:167142.3-167160.6" + attribute \src "libresoc.v:167141.3-167159.6" wire width 4 $1\cr_a$next[3:0]$9242 - attribute \src "libresoc.v:165783.13-165783.24" + attribute \src "libresoc.v:165782.13-165782.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:167142.3-167160.6" + attribute \src "libresoc.v:167141.3-167159.6" wire $1\cr_a_ok$next[0:0]$9243 - attribute \src "libresoc.v:165792.7-165792.21" + attribute \src "libresoc.v:165791.7-165791.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:167069.3-167081.6" + attribute \src "libresoc.v:167068.3-167080.6" wire width 2 $1\muxid$next[1:0]$9191 - attribute \src "libresoc.v:166357.13-166357.25" + attribute \src "libresoc.v:166356.13-166356.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:167123.3-167141.6" + attribute \src "libresoc.v:167122.3-167140.6" wire width 64 $1\o$next[63:0]$9236 - attribute \src "libresoc.v:166372.14-166372.38" + attribute \src "libresoc.v:166371.14-166371.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:167123.3-167141.6" + attribute \src "libresoc.v:167122.3-167140.6" wire $1\o_ok$next[0:0]$9237 - attribute \src "libresoc.v:166379.7-166379.18" + attribute \src "libresoc.v:166378.7-166378.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:167051.3-167068.6" + attribute \src "libresoc.v:167050.3-167067.6" wire $1\r_busy$next[0:0]$9187 - attribute \src "libresoc.v:166393.7-166393.20" + attribute \src "libresoc.v:166392.7-166392.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire width 14 $1\sr_op__fn_unit$next[13:0]$9210 - attribute \src "libresoc.v:166419.14-166419.39" + attribute \src "libresoc.v:166418.14-166418.39" wire width 14 $1\sr_op__fn_unit[13:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire width 64 $1\sr_op__imm_data__data$next[63:0]$9211 - attribute \src "libresoc.v:166458.14-166458.58" + attribute \src "libresoc.v:166457.14-166457.58" wire width 64 $1\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $1\sr_op__imm_data__ok$next[0:0]$9212 - attribute \src "libresoc.v:166467.7-166467.33" + attribute \src "libresoc.v:166466.7-166466.33" wire $1\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire width 2 $1\sr_op__input_carry$next[1:0]$9213 - attribute \src "libresoc.v:166480.13-166480.38" + attribute \src "libresoc.v:166479.13-166479.38" wire width 2 $1\sr_op__input_carry[1:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $1\sr_op__input_cr$next[0:0]$9214 - attribute \src "libresoc.v:166497.7-166497.29" + attribute \src "libresoc.v:166496.7-166496.29" wire $1\sr_op__input_cr[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire width 32 $1\sr_op__insn$next[31:0]$9215 - attribute \src "libresoc.v:166506.14-166506.33" + attribute \src "libresoc.v:166505.14-166505.33" wire width 32 $1\sr_op__insn[31:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire width 7 $1\sr_op__insn_type$next[6:0]$9216 - attribute \src "libresoc.v:166590.13-166590.37" + attribute \src "libresoc.v:166589.13-166589.37" wire width 7 $1\sr_op__insn_type[6:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $1\sr_op__invert_in$next[0:0]$9217 - attribute \src "libresoc.v:166749.7-166749.30" + attribute \src "libresoc.v:166748.7-166748.30" wire $1\sr_op__invert_in[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $1\sr_op__is_32bit$next[0:0]$9218 - attribute \src "libresoc.v:166758.7-166758.29" + attribute \src "libresoc.v:166757.7-166757.29" wire $1\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $1\sr_op__is_signed$next[0:0]$9219 - attribute \src "libresoc.v:166767.7-166767.30" + attribute \src "libresoc.v:166766.7-166766.30" wire $1\sr_op__is_signed[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $1\sr_op__oe__oe$next[0:0]$9220 - attribute \src "libresoc.v:166776.7-166776.27" + attribute \src "libresoc.v:166775.7-166775.27" wire $1\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $1\sr_op__oe__ok$next[0:0]$9221 - attribute \src "libresoc.v:166785.7-166785.27" + attribute \src "libresoc.v:166784.7-166784.27" wire $1\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $1\sr_op__output_carry$next[0:0]$9222 - attribute \src "libresoc.v:166794.7-166794.33" + attribute \src "libresoc.v:166793.7-166793.33" wire $1\sr_op__output_carry[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $1\sr_op__output_cr$next[0:0]$9223 - attribute \src "libresoc.v:166803.7-166803.30" + attribute \src "libresoc.v:166802.7-166802.30" wire $1\sr_op__output_cr[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $1\sr_op__rc__ok$next[0:0]$9224 - attribute \src "libresoc.v:166812.7-166812.27" + attribute \src "libresoc.v:166811.7-166811.27" wire $1\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $1\sr_op__rc__rc$next[0:0]$9225 - attribute \src "libresoc.v:166821.7-166821.27" + attribute \src "libresoc.v:166820.7-166820.27" wire $1\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $1\sr_op__write_cr0$next[0:0]$9226 - attribute \src "libresoc.v:166830.7-166830.30" + attribute \src "libresoc.v:166829.7-166829.30" wire $1\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:167032.3-167050.6" + attribute \src "libresoc.v:167031.3-167049.6" wire width 2 $1\xer_ca$next[1:0]$9183 - attribute \src "libresoc.v:166839.13-166839.26" + attribute \src "libresoc.v:166838.13-166838.26" wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:167032.3-167050.6" + attribute \src "libresoc.v:167031.3-167049.6" wire $1\xer_ca_ok$next[0:0]$9182 - attribute \src "libresoc.v:166850.7-166850.23" + attribute \src "libresoc.v:166849.7-166849.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:167161.3-167179.6" + attribute \src "libresoc.v:167160.3-167178.6" wire $1\xer_so$next[0:0]$9248 - attribute \src "libresoc.v:166859.7-166859.20" + attribute \src "libresoc.v:166858.7-166858.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:167161.3-167179.6" + attribute \src "libresoc.v:167160.3-167178.6" wire $1\xer_so_ok$next[0:0]$9249 - attribute \src "libresoc.v:166868.7-166868.23" + attribute \src "libresoc.v:166867.7-166867.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:167142.3-167160.6" + attribute \src "libresoc.v:167141.3-167159.6" wire $2\cr_a_ok$next[0:0]$9244 - attribute \src "libresoc.v:167123.3-167141.6" + attribute \src "libresoc.v:167122.3-167140.6" wire $2\o_ok$next[0:0]$9238 - attribute \src "libresoc.v:167051.3-167068.6" + attribute \src "libresoc.v:167050.3-167067.6" wire $2\r_busy$next[0:0]$9188 - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire width 64 $2\sr_op__imm_data__data$next[63:0]$9227 - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $2\sr_op__imm_data__ok$next[0:0]$9228 - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $2\sr_op__oe__oe$next[0:0]$9229 - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $2\sr_op__oe__ok$next[0:0]$9230 - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $2\sr_op__rc__ok$next[0:0]$9231 - attribute \src "libresoc.v:167082.3-167122.6" + attribute \src "libresoc.v:167081.3-167121.6" wire $2\sr_op__rc__rc$next[0:0]$9232 - attribute \src "libresoc.v:167032.3-167050.6" + attribute \src "libresoc.v:167031.3-167049.6" wire $2\xer_ca_ok$next[0:0]$9184 - attribute \src "libresoc.v:167161.3-167179.6" + attribute \src "libresoc.v:167160.3-167178.6" wire $2\xer_so_ok$next[0:0]$9250 - attribute \src "libresoc.v:166875.18-166875.118" - wire $and$libresoc.v:166875$9151_Y + attribute \src "libresoc.v:166874.18-166874.118" + wire $and$libresoc.v:166874$9151_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$65 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" @@ -342825,7 +339635,7 @@ module \pipe1$110 wire \cr_a_ok$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:165774.7-165774.15" + attribute \src "libresoc.v:165773.7-165773.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid @@ -343880,7 +340690,7 @@ module \pipe1$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:166875$9151 + cell $and $and$libresoc.v:166874$9151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -343888,10 +340698,10 @@ module \pipe1$110 parameter \Y_WIDTH 1 connect \A \p_valid_i$64 connect \B \p_ready_o - connect \Y $and$libresoc.v:166875$9151_Y + connect \Y $and$libresoc.v:166874$9151_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:166930.15-166977.4" + attribute \src "libresoc.v:166929.15-166976.4" cell \input$113 \input connect \muxid \input_muxid connect \muxid$1 \input_muxid$21 @@ -343941,7 +340751,7 @@ module \pipe1$110 connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:166978.14-167023.4" + attribute \src "libresoc.v:166977.14-167022.4" cell \main$114 \main connect \muxid \main_muxid connect \muxid$1 \main_muxid$44 @@ -343989,432 +340799,432 @@ module \pipe1$110 connect \xer_so$19 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:167024.11-167027.4" + attribute \src "libresoc.v:167023.11-167026.4" cell \n$112 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:167028.11-167031.4" + attribute \src "libresoc.v:167027.11-167030.4" cell \p$111 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:165774.7-165774.20" - process $proc$libresoc.v:165774$9251 + attribute \src "libresoc.v:165773.7-165773.20" + process $proc$libresoc.v:165773$9251 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:165783.13-165783.24" - process $proc$libresoc.v:165783$9252 + attribute \src "libresoc.v:165782.13-165782.24" + process $proc$libresoc.v:165782$9252 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:165792.7-165792.21" - process $proc$libresoc.v:165792$9253 + attribute \src "libresoc.v:165791.7-165791.21" + process $proc$libresoc.v:165791$9253 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:166357.13-166357.25" - process $proc$libresoc.v:166357$9254 + attribute \src "libresoc.v:166356.13-166356.25" + process $proc$libresoc.v:166356$9254 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:166372.14-166372.38" - process $proc$libresoc.v:166372$9255 + attribute \src "libresoc.v:166371.14-166371.38" + process $proc$libresoc.v:166371$9255 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:166379.7-166379.18" - process $proc$libresoc.v:166379$9256 + attribute \src "libresoc.v:166378.7-166378.18" + process $proc$libresoc.v:166378$9256 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:166393.7-166393.20" - process $proc$libresoc.v:166393$9257 + attribute \src "libresoc.v:166392.7-166392.20" + process $proc$libresoc.v:166392$9257 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:166419.14-166419.39" - process $proc$libresoc.v:166419$9258 + attribute \src "libresoc.v:166418.14-166418.39" + process $proc$libresoc.v:166418$9258 assign { } { } assign $1\sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \sr_op__fn_unit $1\sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:166458.14-166458.58" - process $proc$libresoc.v:166458$9259 + attribute \src "libresoc.v:166457.14-166457.58" + process $proc$libresoc.v:166457$9259 assign { } { } assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:166467.7-166467.33" - process $proc$libresoc.v:166467$9260 + attribute \src "libresoc.v:166466.7-166466.33" + process $proc$libresoc.v:166466$9260 assign { } { } assign $1\sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:166480.13-166480.38" - process $proc$libresoc.v:166480$9261 + attribute \src "libresoc.v:166479.13-166479.38" + process $proc$libresoc.v:166479$9261 assign { } { } assign $1\sr_op__input_carry[1:0] 2'00 sync always sync init update \sr_op__input_carry $1\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:166497.7-166497.29" - process $proc$libresoc.v:166497$9262 + attribute \src "libresoc.v:166496.7-166496.29" + process $proc$libresoc.v:166496$9262 assign { } { } assign $1\sr_op__input_cr[0:0] 1'0 sync always sync init update \sr_op__input_cr $1\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:166506.14-166506.33" - process $proc$libresoc.v:166506$9263 + attribute \src "libresoc.v:166505.14-166505.33" + process $proc$libresoc.v:166505$9263 assign { } { } assign $1\sr_op__insn[31:0] 0 sync always sync init update \sr_op__insn $1\sr_op__insn[31:0] end - attribute \src "libresoc.v:166590.13-166590.37" - process $proc$libresoc.v:166590$9264 + attribute \src "libresoc.v:166589.13-166589.37" + process $proc$libresoc.v:166589$9264 assign { } { } assign $1\sr_op__insn_type[6:0] 7'0000000 sync always sync init update \sr_op__insn_type $1\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:166749.7-166749.30" - process $proc$libresoc.v:166749$9265 + attribute \src "libresoc.v:166748.7-166748.30" + process $proc$libresoc.v:166748$9265 assign { } { } assign $1\sr_op__invert_in[0:0] 1'0 sync always sync init update \sr_op__invert_in $1\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:166758.7-166758.29" - process $proc$libresoc.v:166758$9266 + attribute \src "libresoc.v:166757.7-166757.29" + process $proc$libresoc.v:166757$9266 assign { } { } assign $1\sr_op__is_32bit[0:0] 1'0 sync always sync init update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:166767.7-166767.30" - process $proc$libresoc.v:166767$9267 + attribute \src "libresoc.v:166766.7-166766.30" + process $proc$libresoc.v:166766$9267 assign { } { } assign $1\sr_op__is_signed[0:0] 1'0 sync always sync init update \sr_op__is_signed $1\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:166776.7-166776.27" - process $proc$libresoc.v:166776$9268 + attribute \src "libresoc.v:166775.7-166775.27" + process $proc$libresoc.v:166775$9268 assign { } { } assign $1\sr_op__oe__oe[0:0] 1'0 sync always sync init update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:166785.7-166785.27" - process $proc$libresoc.v:166785$9269 + attribute \src "libresoc.v:166784.7-166784.27" + process $proc$libresoc.v:166784$9269 assign { } { } assign $1\sr_op__oe__ok[0:0] 1'0 sync always sync init update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:166794.7-166794.33" - process $proc$libresoc.v:166794$9270 + attribute \src "libresoc.v:166793.7-166793.33" + process $proc$libresoc.v:166793$9270 assign { } { } assign $1\sr_op__output_carry[0:0] 1'0 sync always sync init update \sr_op__output_carry $1\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:166803.7-166803.30" - process $proc$libresoc.v:166803$9271 + attribute \src "libresoc.v:166802.7-166802.30" + process $proc$libresoc.v:166802$9271 assign { } { } assign $1\sr_op__output_cr[0:0] 1'0 sync always sync init update \sr_op__output_cr $1\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:166812.7-166812.27" - process $proc$libresoc.v:166812$9272 + attribute \src "libresoc.v:166811.7-166811.27" + process $proc$libresoc.v:166811$9272 assign { } { } assign $1\sr_op__rc__ok[0:0] 1'0 sync always sync init update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:166821.7-166821.27" - process $proc$libresoc.v:166821$9273 + attribute \src "libresoc.v:166820.7-166820.27" + process $proc$libresoc.v:166820$9273 assign { } { } assign $1\sr_op__rc__rc[0:0] 1'0 sync always sync init update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:166830.7-166830.30" - process $proc$libresoc.v:166830$9274 + attribute \src "libresoc.v:166829.7-166829.30" + process $proc$libresoc.v:166829$9274 assign { } { } assign $1\sr_op__write_cr0[0:0] 1'0 sync always sync init update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:166839.13-166839.26" - process $proc$libresoc.v:166839$9275 + attribute \src "libresoc.v:166838.13-166838.26" + process $proc$libresoc.v:166838$9275 assign { } { } assign $1\xer_ca[1:0] 2'00 sync always sync init update \xer_ca $1\xer_ca[1:0] end - attribute \src "libresoc.v:166850.7-166850.23" - process $proc$libresoc.v:166850$9276 + attribute \src "libresoc.v:166849.7-166849.23" + process $proc$libresoc.v:166849$9276 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:166859.7-166859.20" - process $proc$libresoc.v:166859$9277 + attribute \src "libresoc.v:166858.7-166858.20" + process $proc$libresoc.v:166858$9277 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:166868.7-166868.23" - process $proc$libresoc.v:166868$9278 + attribute \src "libresoc.v:166867.7-166867.23" + process $proc$libresoc.v:166867$9278 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:166876.3-166877.29" - process $proc$libresoc.v:166876$9152 + attribute \src "libresoc.v:166875.3-166876.29" + process $proc$libresoc.v:166875$9152 assign { } { } assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:166878.3-166879.35" - process $proc$libresoc.v:166878$9153 + attribute \src "libresoc.v:166877.3-166878.35" + process $proc$libresoc.v:166877$9153 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:166880.3-166881.29" - process $proc$libresoc.v:166880$9154 + attribute \src "libresoc.v:166879.3-166880.29" + process $proc$libresoc.v:166879$9154 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:166882.3-166883.35" - process $proc$libresoc.v:166882$9155 + attribute \src "libresoc.v:166881.3-166882.35" + process $proc$libresoc.v:166881$9155 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:166884.3-166885.25" - process $proc$libresoc.v:166884$9156 + attribute \src "libresoc.v:166883.3-166884.25" + process $proc$libresoc.v:166883$9156 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:166886.3-166887.31" - process $proc$libresoc.v:166886$9157 + attribute \src "libresoc.v:166885.3-166886.31" + process $proc$libresoc.v:166885$9157 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:166888.3-166889.19" - process $proc$libresoc.v:166888$9158 + attribute \src "libresoc.v:166887.3-166888.19" + process $proc$libresoc.v:166887$9158 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:166890.3-166891.25" - process $proc$libresoc.v:166890$9159 + attribute \src "libresoc.v:166889.3-166890.25" + process $proc$libresoc.v:166889$9159 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:166892.3-166893.49" - process $proc$libresoc.v:166892$9160 + attribute \src "libresoc.v:166891.3-166892.49" + process $proc$libresoc.v:166891$9160 assign { } { } assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next sync posedge \coresync_clk update \sr_op__insn_type $0\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:166894.3-166895.45" - process $proc$libresoc.v:166894$9161 + attribute \src "libresoc.v:166893.3-166894.45" + process $proc$libresoc.v:166893$9161 assign { } { } assign $0\sr_op__fn_unit[13:0] \sr_op__fn_unit$next sync posedge \coresync_clk update \sr_op__fn_unit $0\sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:166896.3-166897.59" - process $proc$libresoc.v:166896$9162 + attribute \src "libresoc.v:166895.3-166896.59" + process $proc$libresoc.v:166895$9162 assign { } { } assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next sync posedge \coresync_clk update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:166898.3-166899.55" - process $proc$libresoc.v:166898$9163 + attribute \src "libresoc.v:166897.3-166898.55" + process $proc$libresoc.v:166897$9163 assign { } { } assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next sync posedge \coresync_clk update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:166900.3-166901.43" - process $proc$libresoc.v:166900$9164 + attribute \src "libresoc.v:166899.3-166900.43" + process $proc$libresoc.v:166899$9164 assign { } { } assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next sync posedge \coresync_clk update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:166902.3-166903.43" - process $proc$libresoc.v:166902$9165 + attribute \src "libresoc.v:166901.3-166902.43" + process $proc$libresoc.v:166901$9165 assign { } { } assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next sync posedge \coresync_clk update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:166904.3-166905.43" - process $proc$libresoc.v:166904$9166 + attribute \src "libresoc.v:166903.3-166904.43" + process $proc$libresoc.v:166903$9166 assign { } { } assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next sync posedge \coresync_clk update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:166906.3-166907.43" - process $proc$libresoc.v:166906$9167 + attribute \src "libresoc.v:166905.3-166906.43" + process $proc$libresoc.v:166905$9167 assign { } { } assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next sync posedge \coresync_clk update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:166908.3-166909.49" - process $proc$libresoc.v:166908$9168 + attribute \src "libresoc.v:166907.3-166908.49" + process $proc$libresoc.v:166907$9168 assign { } { } assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next sync posedge \coresync_clk update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:166910.3-166911.49" - process $proc$libresoc.v:166910$9169 + attribute \src "libresoc.v:166909.3-166910.49" + process $proc$libresoc.v:166909$9169 assign { } { } assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next sync posedge \coresync_clk update \sr_op__invert_in $0\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:166912.3-166913.53" - process $proc$libresoc.v:166912$9170 + attribute \src "libresoc.v:166911.3-166912.53" + process $proc$libresoc.v:166911$9170 assign { } { } assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next sync posedge \coresync_clk update \sr_op__input_carry $0\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:166914.3-166915.55" - process $proc$libresoc.v:166914$9171 + attribute \src "libresoc.v:166913.3-166914.55" + process $proc$libresoc.v:166913$9171 assign { } { } assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next sync posedge \coresync_clk update \sr_op__output_carry $0\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:166916.3-166917.47" - process $proc$libresoc.v:166916$9172 + attribute \src "libresoc.v:166915.3-166916.47" + process $proc$libresoc.v:166915$9172 assign { } { } assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next sync posedge \coresync_clk update \sr_op__input_cr $0\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:166918.3-166919.49" - process $proc$libresoc.v:166918$9173 + attribute \src "libresoc.v:166917.3-166918.49" + process $proc$libresoc.v:166917$9173 assign { } { } assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next sync posedge \coresync_clk update \sr_op__output_cr $0\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:166920.3-166921.47" - process $proc$libresoc.v:166920$9174 + attribute \src "libresoc.v:166919.3-166920.47" + process $proc$libresoc.v:166919$9174 assign { } { } assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next sync posedge \coresync_clk update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:166922.3-166923.49" - process $proc$libresoc.v:166922$9175 + attribute \src "libresoc.v:166921.3-166922.49" + process $proc$libresoc.v:166921$9175 assign { } { } assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next sync posedge \coresync_clk update \sr_op__is_signed $0\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:166924.3-166925.39" - process $proc$libresoc.v:166924$9176 + attribute \src "libresoc.v:166923.3-166924.39" + process $proc$libresoc.v:166923$9176 assign { } { } assign $0\sr_op__insn[31:0] \sr_op__insn$next sync posedge \coresync_clk update \sr_op__insn $0\sr_op__insn[31:0] end - attribute \src "libresoc.v:166926.3-166927.27" - process $proc$libresoc.v:166926$9177 + attribute \src "libresoc.v:166925.3-166926.27" + process $proc$libresoc.v:166925$9177 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:166928.3-166929.29" - process $proc$libresoc.v:166928$9178 + attribute \src "libresoc.v:166927.3-166928.29" + process $proc$libresoc.v:166927$9178 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:167032.3-167050.6" - process $proc$libresoc.v:167032$9179 + attribute \src "libresoc.v:167031.3-167049.6" + process $proc$libresoc.v:167031$9179 assign { } { } assign { } { } assign { } { } @@ -344422,9 +341232,9 @@ module \pipe1$110 assign { } { } assign $0\xer_ca$next[1:0]$9181 $1\xer_ca$next[1:0]$9183 assign $0\xer_ca_ok$next[0:0]$9180 $2\xer_ca_ok$next[0:0]$9184 - attribute \src "libresoc.v:167033.5-167033.29" + attribute \src "libresoc.v:167032.5-167032.29" switch \initial - attribute \src "libresoc.v:167033.9-167033.17" + attribute \src "libresoc.v:167032.9-167032.17" case 1'1 case end @@ -344457,15 +341267,15 @@ module \pipe1$110 update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9180 update \xer_ca$next $0\xer_ca$next[1:0]$9181 end - attribute \src "libresoc.v:167051.3-167068.6" - process $proc$libresoc.v:167051$9185 + attribute \src "libresoc.v:167050.3-167067.6" + process $proc$libresoc.v:167050$9185 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9186 $2\r_busy$next[0:0]$9188 - attribute \src "libresoc.v:167052.5-167052.29" + attribute \src "libresoc.v:167051.5-167051.29" switch \initial - attribute \src "libresoc.v:167052.9-167052.17" + attribute \src "libresoc.v:167051.9-167051.17" case 1'1 case end @@ -344494,14 +341304,14 @@ module \pipe1$110 sync always update \r_busy$next $0\r_busy$next[0:0]$9186 end - attribute \src "libresoc.v:167069.3-167081.6" - process $proc$libresoc.v:167069$9189 + attribute \src "libresoc.v:167068.3-167080.6" + process $proc$libresoc.v:167068$9189 assign { } { } assign { } { } assign $0\muxid$next[1:0]$9190 $1\muxid$next[1:0]$9191 - attribute \src "libresoc.v:167070.5-167070.29" + attribute \src "libresoc.v:167069.5-167069.29" switch \initial - attribute \src "libresoc.v:167070.9-167070.17" + attribute \src "libresoc.v:167069.9-167069.17" case 1'1 case end @@ -344521,8 +341331,8 @@ module \pipe1$110 sync always update \muxid$next $0\muxid$next[1:0]$9190 end - attribute \src "libresoc.v:167082.3-167122.6" - process $proc$libresoc.v:167082$9192 + attribute \src "libresoc.v:167081.3-167121.6" + process $proc$libresoc.v:167081$9192 assign { } { } assign { } { } assign { } { } @@ -344580,9 +341390,9 @@ module \pipe1$110 assign $0\sr_op__oe__ok$next[0:0]$9204 $2\sr_op__oe__ok$next[0:0]$9230 assign $0\sr_op__rc__ok$next[0:0]$9207 $2\sr_op__rc__ok$next[0:0]$9231 assign $0\sr_op__rc__rc$next[0:0]$9208 $2\sr_op__rc__rc$next[0:0]$9232 - attribute \src "libresoc.v:167083.5-167083.29" + attribute \src "libresoc.v:167082.5-167082.29" switch \initial - attribute \src "libresoc.v:167083.9-167083.17" + attribute \src "libresoc.v:167082.9-167082.17" case 1'1 case end @@ -344690,8 +341500,8 @@ module \pipe1$110 update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9208 update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9209 end - attribute \src "libresoc.v:167123.3-167141.6" - process $proc$libresoc.v:167123$9233 + attribute \src "libresoc.v:167122.3-167140.6" + process $proc$libresoc.v:167122$9233 assign { } { } assign { } { } assign { } { } @@ -344699,9 +341509,9 @@ module \pipe1$110 assign $0\o$next[63:0]$9234 $1\o$next[63:0]$9236 assign { } { } assign $0\o_ok$next[0:0]$9235 $2\o_ok$next[0:0]$9238 - attribute \src "libresoc.v:167124.5-167124.29" + attribute \src "libresoc.v:167123.5-167123.29" switch \initial - attribute \src "libresoc.v:167124.9-167124.17" + attribute \src "libresoc.v:167123.9-167123.17" case 1'1 case end @@ -344734,8 +341544,8 @@ module \pipe1$110 update \o$next $0\o$next[63:0]$9234 update \o_ok$next $0\o_ok$next[0:0]$9235 end - attribute \src "libresoc.v:167142.3-167160.6" - process $proc$libresoc.v:167142$9239 + attribute \src "libresoc.v:167141.3-167159.6" + process $proc$libresoc.v:167141$9239 assign { } { } assign { } { } assign { } { } @@ -344743,9 +341553,9 @@ module \pipe1$110 assign $0\cr_a$next[3:0]$9240 $1\cr_a$next[3:0]$9242 assign { } { } assign $0\cr_a_ok$next[0:0]$9241 $2\cr_a_ok$next[0:0]$9244 - attribute \src "libresoc.v:167143.5-167143.29" + attribute \src "libresoc.v:167142.5-167142.29" switch \initial - attribute \src "libresoc.v:167143.9-167143.17" + attribute \src "libresoc.v:167142.9-167142.17" case 1'1 case end @@ -344778,8 +341588,8 @@ module \pipe1$110 update \cr_a$next $0\cr_a$next[3:0]$9240 update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9241 end - attribute \src "libresoc.v:167161.3-167179.6" - process $proc$libresoc.v:167161$9245 + attribute \src "libresoc.v:167160.3-167178.6" + process $proc$libresoc.v:167160$9245 assign { } { } assign { } { } assign { } { } @@ -344787,9 +341597,9 @@ module \pipe1$110 assign $0\xer_so$next[0:0]$9246 $1\xer_so$next[0:0]$9248 assign { } { } assign $0\xer_so_ok$next[0:0]$9247 $2\xer_so_ok$next[0:0]$9250 - attribute \src "libresoc.v:167162.5-167162.29" + attribute \src "libresoc.v:167161.5-167161.29" switch \initial - attribute \src "libresoc.v:167162.9-167162.17" + attribute \src "libresoc.v:167161.9-167161.17" case 1'1 case end @@ -344822,7 +341632,7 @@ module \pipe1$110 update \xer_so$next $0\xer_so$next[0:0]$9246 update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9247 end - connect \$65 $and$libresoc.v:166875$9151_Y + connect \$65 $and$libresoc.v:166874$9151_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 @@ -344853,137 +341663,137 @@ module \pipe1$110 connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:167213.1-168061.10" +attribute \src "libresoc.v:167212.1-168060.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" attribute \generator "nMigen" module \pipe1$32 - attribute \src "libresoc.v:168018.3-168030.6" + attribute \src "libresoc.v:168017.3-168029.6" wire width 64 $0\fast1$next[63:0]$9328 - attribute \src "libresoc.v:167874.3-167875.27" + attribute \src "libresoc.v:167873.3-167874.27" wire width 64 $0\fast1[63:0] - attribute \src "libresoc.v:168031.3-168043.6" + attribute \src "libresoc.v:168030.3-168042.6" wire width 64 $0\fast2$next[63:0]$9331 - attribute \src "libresoc.v:167872.3-167873.27" + attribute \src "libresoc.v:167871.3-167872.27" wire width 64 $0\fast2[63:0] - attribute \src "libresoc.v:167214.7-167214.20" + attribute \src "libresoc.v:167213.7-167213.20" wire $0\initial[0:0] - attribute \src "libresoc.v:167958.3-167970.6" + attribute \src "libresoc.v:167957.3-167969.6" wire width 2 $0\muxid$next[1:0]$9300 - attribute \src "libresoc.v:167898.3-167899.27" + attribute \src "libresoc.v:167897.3-167898.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:167940.3-167957.6" + attribute \src "libresoc.v:167939.3-167956.6" wire $0\r_busy$next[0:0]$9296 - attribute \src "libresoc.v:167900.3-167901.29" + attribute \src "libresoc.v:167899.3-167900.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:167992.3-168004.6" + attribute \src "libresoc.v:167991.3-168003.6" wire width 64 $0\ra$next[63:0]$9322 - attribute \src "libresoc.v:167878.3-167879.21" + attribute \src "libresoc.v:167877.3-167878.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:168005.3-168017.6" + attribute \src "libresoc.v:168004.3-168016.6" wire width 64 $0\rb$next[63:0]$9325 - attribute \src "libresoc.v:167876.3-167877.21" + attribute \src "libresoc.v:167875.3-167876.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire width 64 $0\trap_op__cia$next[63:0]$9303 - attribute \src "libresoc.v:167888.3-167889.41" + attribute \src "libresoc.v:167887.3-167888.41" wire width 64 $0\trap_op__cia[63:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire width 14 $0\trap_op__fn_unit$next[13:0]$9304 - attribute \src "libresoc.v:167882.3-167883.49" + attribute \src "libresoc.v:167881.3-167882.49" wire width 14 $0\trap_op__fn_unit[13:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire width 32 $0\trap_op__insn$next[31:0]$9305 - attribute \src "libresoc.v:167884.3-167885.43" + attribute \src "libresoc.v:167883.3-167884.43" wire width 32 $0\trap_op__insn[31:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire width 7 $0\trap_op__insn_type$next[6:0]$9306 - attribute \src "libresoc.v:167880.3-167881.53" + attribute \src "libresoc.v:167879.3-167880.53" wire width 7 $0\trap_op__insn_type[6:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire $0\trap_op__is_32bit$next[0:0]$9307 - attribute \src "libresoc.v:167890.3-167891.51" + attribute \src "libresoc.v:167889.3-167890.51" wire $0\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire width 8 $0\trap_op__ldst_exc$next[7:0]$9308 - attribute \src "libresoc.v:167896.3-167897.51" + attribute \src "libresoc.v:167895.3-167896.51" wire width 8 $0\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire width 64 $0\trap_op__msr$next[63:0]$9309 - attribute \src "libresoc.v:167886.3-167887.41" + attribute \src "libresoc.v:167885.3-167886.41" wire width 64 $0\trap_op__msr[63:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire width 13 $0\trap_op__trapaddr$next[12:0]$9310 - attribute \src "libresoc.v:167894.3-167895.51" + attribute \src "libresoc.v:167893.3-167894.51" wire width 13 $0\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire width 8 $0\trap_op__traptype$next[7:0]$9311 - attribute \src "libresoc.v:167892.3-167893.51" + attribute \src "libresoc.v:167891.3-167892.51" wire width 8 $0\trap_op__traptype[7:0] - attribute \src "libresoc.v:168018.3-168030.6" + attribute \src "libresoc.v:168017.3-168029.6" wire width 64 $1\fast1$next[63:0]$9329 - attribute \src "libresoc.v:167459.14-167459.42" + attribute \src "libresoc.v:167458.14-167458.42" wire width 64 $1\fast1[63:0] - attribute \src "libresoc.v:168031.3-168043.6" + attribute \src "libresoc.v:168030.3-168042.6" wire width 64 $1\fast2$next[63:0]$9332 - attribute \src "libresoc.v:167468.14-167468.42" + attribute \src "libresoc.v:167467.14-167467.42" wire width 64 $1\fast2[63:0] - attribute \src "libresoc.v:167958.3-167970.6" + attribute \src "libresoc.v:167957.3-167969.6" wire width 2 $1\muxid$next[1:0]$9301 - attribute \src "libresoc.v:167477.13-167477.25" + attribute \src "libresoc.v:167476.13-167476.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:167940.3-167957.6" + attribute \src "libresoc.v:167939.3-167956.6" wire $1\r_busy$next[0:0]$9297 - attribute \src "libresoc.v:167499.7-167499.20" + attribute \src "libresoc.v:167498.7-167498.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:167992.3-168004.6" + attribute \src "libresoc.v:167991.3-168003.6" wire width 64 $1\ra$next[63:0]$9323 - attribute \src "libresoc.v:167504.14-167504.39" + attribute \src "libresoc.v:167503.14-167503.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:168005.3-168017.6" + attribute \src "libresoc.v:168004.3-168016.6" wire width 64 $1\rb$next[63:0]$9326 - attribute \src "libresoc.v:167513.14-167513.39" + attribute \src "libresoc.v:167512.14-167512.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire width 64 $1\trap_op__cia$next[63:0]$9312 - attribute \src "libresoc.v:167522.14-167522.49" + attribute \src "libresoc.v:167521.14-167521.49" wire width 64 $1\trap_op__cia[63:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire width 14 $1\trap_op__fn_unit$next[13:0]$9313 - attribute \src "libresoc.v:167546.14-167546.41" + attribute \src "libresoc.v:167545.14-167545.41" wire width 14 $1\trap_op__fn_unit[13:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire width 32 $1\trap_op__insn$next[31:0]$9314 - attribute \src "libresoc.v:167585.14-167585.35" + attribute \src "libresoc.v:167584.14-167584.35" wire width 32 $1\trap_op__insn[31:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire width 7 $1\trap_op__insn_type$next[6:0]$9315 - attribute \src "libresoc.v:167669.13-167669.39" + attribute \src "libresoc.v:167668.13-167668.39" wire width 7 $1\trap_op__insn_type[6:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire $1\trap_op__is_32bit$next[0:0]$9316 - attribute \src "libresoc.v:167828.7-167828.31" + attribute \src "libresoc.v:167827.7-167827.31" wire $1\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire width 8 $1\trap_op__ldst_exc$next[7:0]$9317 - attribute \src "libresoc.v:167837.13-167837.38" + attribute \src "libresoc.v:167836.13-167836.38" wire width 8 $1\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire width 64 $1\trap_op__msr$next[63:0]$9318 - attribute \src "libresoc.v:167846.14-167846.49" + attribute \src "libresoc.v:167845.14-167845.49" wire width 64 $1\trap_op__msr[63:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire width 13 $1\trap_op__trapaddr$next[12:0]$9319 - attribute \src "libresoc.v:167855.14-167855.42" + attribute \src "libresoc.v:167854.14-167854.42" wire width 13 $1\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:167971.3-167991.6" + attribute \src "libresoc.v:167970.3-167990.6" wire width 8 $1\trap_op__traptype$next[7:0]$9320 - attribute \src "libresoc.v:167864.13-167864.38" + attribute \src "libresoc.v:167863.13-167863.38" wire width 8 $1\trap_op__traptype[7:0] - attribute \src "libresoc.v:167940.3-167957.6" + attribute \src "libresoc.v:167939.3-167956.6" wire $2\r_busy$next[0:0]$9298 - attribute \src "libresoc.v:167871.18-167871.118" - wire $and$libresoc.v:167871$9279_Y + attribute \src "libresoc.v:167870.18-167870.118" + wire $and$libresoc.v:167870$9279_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$30 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" @@ -345242,7 +342052,7 @@ module \pipe1$32 wire width 64 \fast2$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \fast2$next - attribute \src "libresoc.v:167214.7-167214.15" + attribute \src "libresoc.v:167213.7-167213.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid @@ -345629,7 +342439,7 @@ module \pipe1$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:167871$9279 + cell $and $and$libresoc.v:167870$9279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -345637,10 +342447,10 @@ module \pipe1$32 parameter \Y_WIDTH 1 connect \A \p_valid_i$29 connect \B \p_ready_o - connect \Y $and$libresoc.v:167871$9279_Y + connect \Y $and$libresoc.v:167870$9279_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:167902.9-167931.4" + attribute \src "libresoc.v:167901.9-167930.4" cell \dummy \dummy connect \fast1 \dummy_fast1 connect \fast1$13 \dummy_fast1$27 @@ -345672,259 +342482,259 @@ module \pipe1$32 connect \trap_op__traptype$8 \dummy_trap_op__traptype$22 end attribute \module_not_derived 1 - attribute \src "libresoc.v:167932.10-167935.4" + attribute \src "libresoc.v:167931.10-167934.4" cell \n$34 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:167936.10-167939.4" + attribute \src "libresoc.v:167935.10-167938.4" cell \p$33 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:167214.7-167214.20" - process $proc$libresoc.v:167214$9333 + attribute \src "libresoc.v:167213.7-167213.20" + process $proc$libresoc.v:167213$9333 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:167459.14-167459.42" - process $proc$libresoc.v:167459$9334 + attribute \src "libresoc.v:167458.14-167458.42" + process $proc$libresoc.v:167458$9334 assign { } { } assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast1 $1\fast1[63:0] end - attribute \src "libresoc.v:167468.14-167468.42" - process $proc$libresoc.v:167468$9335 + attribute \src "libresoc.v:167467.14-167467.42" + process $proc$libresoc.v:167467$9335 assign { } { } assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast2 $1\fast2[63:0] end - attribute \src "libresoc.v:167477.13-167477.25" - process $proc$libresoc.v:167477$9336 + attribute \src "libresoc.v:167476.13-167476.25" + process $proc$libresoc.v:167476$9336 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:167499.7-167499.20" - process $proc$libresoc.v:167499$9337 + attribute \src "libresoc.v:167498.7-167498.20" + process $proc$libresoc.v:167498$9337 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:167504.14-167504.39" - process $proc$libresoc.v:167504$9338 + attribute \src "libresoc.v:167503.14-167503.39" + process $proc$libresoc.v:167503$9338 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:167513.14-167513.39" - process $proc$libresoc.v:167513$9339 + attribute \src "libresoc.v:167512.14-167512.39" + process $proc$libresoc.v:167512$9339 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:167522.14-167522.49" - process $proc$libresoc.v:167522$9340 + attribute \src "libresoc.v:167521.14-167521.49" + process $proc$libresoc.v:167521$9340 assign { } { } assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__cia $1\trap_op__cia[63:0] end - attribute \src "libresoc.v:167546.14-167546.41" - process $proc$libresoc.v:167546$9341 + attribute \src "libresoc.v:167545.14-167545.41" + process $proc$libresoc.v:167545$9341 assign { } { } assign $1\trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \trap_op__fn_unit $1\trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:167585.14-167585.35" - process $proc$libresoc.v:167585$9342 + attribute \src "libresoc.v:167584.14-167584.35" + process $proc$libresoc.v:167584$9342 assign { } { } assign $1\trap_op__insn[31:0] 0 sync always sync init update \trap_op__insn $1\trap_op__insn[31:0] end - attribute \src "libresoc.v:167669.13-167669.39" - process $proc$libresoc.v:167669$9343 + attribute \src "libresoc.v:167668.13-167668.39" + process $proc$libresoc.v:167668$9343 assign { } { } assign $1\trap_op__insn_type[6:0] 7'0000000 sync always sync init update \trap_op__insn_type $1\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:167828.7-167828.31" - process $proc$libresoc.v:167828$9344 + attribute \src "libresoc.v:167827.7-167827.31" + process $proc$libresoc.v:167827$9344 assign { } { } assign $1\trap_op__is_32bit[0:0] 1'0 sync always sync init update \trap_op__is_32bit $1\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:167837.13-167837.38" - process $proc$libresoc.v:167837$9345 + attribute \src "libresoc.v:167836.13-167836.38" + process $proc$libresoc.v:167836$9345 assign { } { } assign $1\trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:167846.14-167846.49" - process $proc$libresoc.v:167846$9346 + attribute \src "libresoc.v:167845.14-167845.49" + process $proc$libresoc.v:167845$9346 assign { } { } assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__msr $1\trap_op__msr[63:0] end - attribute \src "libresoc.v:167855.14-167855.42" - process $proc$libresoc.v:167855$9347 + attribute \src "libresoc.v:167854.14-167854.42" + process $proc$libresoc.v:167854$9347 assign { } { } assign $1\trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \trap_op__trapaddr $1\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:167864.13-167864.38" - process $proc$libresoc.v:167864$9348 + attribute \src "libresoc.v:167863.13-167863.38" + process $proc$libresoc.v:167863$9348 assign { } { } assign $1\trap_op__traptype[7:0] 8'00000000 sync always sync init update \trap_op__traptype $1\trap_op__traptype[7:0] end - attribute \src "libresoc.v:167872.3-167873.27" - process $proc$libresoc.v:167872$9280 + attribute \src "libresoc.v:167871.3-167872.27" + process $proc$libresoc.v:167871$9280 assign { } { } assign $0\fast2[63:0] \fast2$next sync posedge \coresync_clk update \fast2 $0\fast2[63:0] end - attribute \src "libresoc.v:167874.3-167875.27" - process $proc$libresoc.v:167874$9281 + attribute \src "libresoc.v:167873.3-167874.27" + process $proc$libresoc.v:167873$9281 assign { } { } assign $0\fast1[63:0] \fast1$next sync posedge \coresync_clk update \fast1 $0\fast1[63:0] end - attribute \src "libresoc.v:167876.3-167877.21" - process $proc$libresoc.v:167876$9282 + attribute \src "libresoc.v:167875.3-167876.21" + process $proc$libresoc.v:167875$9282 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:167878.3-167879.21" - process $proc$libresoc.v:167878$9283 + attribute \src "libresoc.v:167877.3-167878.21" + process $proc$libresoc.v:167877$9283 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:167880.3-167881.53" - process $proc$libresoc.v:167880$9284 + attribute \src "libresoc.v:167879.3-167880.53" + process $proc$libresoc.v:167879$9284 assign { } { } assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next sync posedge \coresync_clk update \trap_op__insn_type $0\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:167882.3-167883.49" - process $proc$libresoc.v:167882$9285 + attribute \src "libresoc.v:167881.3-167882.49" + process $proc$libresoc.v:167881$9285 assign { } { } assign $0\trap_op__fn_unit[13:0] \trap_op__fn_unit$next sync posedge \coresync_clk update \trap_op__fn_unit $0\trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:167884.3-167885.43" - process $proc$libresoc.v:167884$9286 + attribute \src "libresoc.v:167883.3-167884.43" + process $proc$libresoc.v:167883$9286 assign { } { } assign $0\trap_op__insn[31:0] \trap_op__insn$next sync posedge \coresync_clk update \trap_op__insn $0\trap_op__insn[31:0] end - attribute \src "libresoc.v:167886.3-167887.41" - process $proc$libresoc.v:167886$9287 + attribute \src "libresoc.v:167885.3-167886.41" + process $proc$libresoc.v:167885$9287 assign { } { } assign $0\trap_op__msr[63:0] \trap_op__msr$next sync posedge \coresync_clk update \trap_op__msr $0\trap_op__msr[63:0] end - attribute \src "libresoc.v:167888.3-167889.41" - process $proc$libresoc.v:167888$9288 + attribute \src "libresoc.v:167887.3-167888.41" + process $proc$libresoc.v:167887$9288 assign { } { } assign $0\trap_op__cia[63:0] \trap_op__cia$next sync posedge \coresync_clk update \trap_op__cia $0\trap_op__cia[63:0] end - attribute \src "libresoc.v:167890.3-167891.51" - process $proc$libresoc.v:167890$9289 + attribute \src "libresoc.v:167889.3-167890.51" + process $proc$libresoc.v:167889$9289 assign { } { } assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next sync posedge \coresync_clk update \trap_op__is_32bit $0\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:167892.3-167893.51" - process $proc$libresoc.v:167892$9290 + attribute \src "libresoc.v:167891.3-167892.51" + process $proc$libresoc.v:167891$9290 assign { } { } assign $0\trap_op__traptype[7:0] \trap_op__traptype$next sync posedge \coresync_clk update \trap_op__traptype $0\trap_op__traptype[7:0] end - attribute \src "libresoc.v:167894.3-167895.51" - process $proc$libresoc.v:167894$9291 + attribute \src "libresoc.v:167893.3-167894.51" + process $proc$libresoc.v:167893$9291 assign { } { } assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next sync posedge \coresync_clk update \trap_op__trapaddr $0\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:167896.3-167897.51" - process $proc$libresoc.v:167896$9292 + attribute \src "libresoc.v:167895.3-167896.51" + process $proc$libresoc.v:167895$9292 assign { } { } assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next sync posedge \coresync_clk update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:167898.3-167899.27" - process $proc$libresoc.v:167898$9293 + attribute \src "libresoc.v:167897.3-167898.27" + process $proc$libresoc.v:167897$9293 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:167900.3-167901.29" - process $proc$libresoc.v:167900$9294 + attribute \src "libresoc.v:167899.3-167900.29" + process $proc$libresoc.v:167899$9294 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:167940.3-167957.6" - process $proc$libresoc.v:167940$9295 + attribute \src "libresoc.v:167939.3-167956.6" + process $proc$libresoc.v:167939$9295 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9296 $2\r_busy$next[0:0]$9298 - attribute \src "libresoc.v:167941.5-167941.29" + attribute \src "libresoc.v:167940.5-167940.29" switch \initial - attribute \src "libresoc.v:167941.9-167941.17" + attribute \src "libresoc.v:167940.9-167940.17" case 1'1 case end @@ -345953,14 +342763,14 @@ module \pipe1$32 sync always update \r_busy$next $0\r_busy$next[0:0]$9296 end - attribute \src "libresoc.v:167958.3-167970.6" - process $proc$libresoc.v:167958$9299 + attribute \src "libresoc.v:167957.3-167969.6" + process $proc$libresoc.v:167957$9299 assign { } { } assign { } { } assign $0\muxid$next[1:0]$9300 $1\muxid$next[1:0]$9301 - attribute \src "libresoc.v:167959.5-167959.29" + attribute \src "libresoc.v:167958.5-167958.29" switch \initial - attribute \src "libresoc.v:167959.9-167959.17" + attribute \src "libresoc.v:167958.9-167958.17" case 1'1 case end @@ -345980,8 +342790,8 @@ module \pipe1$32 sync always update \muxid$next $0\muxid$next[1:0]$9300 end - attribute \src "libresoc.v:167971.3-167991.6" - process $proc$libresoc.v:167971$9302 + attribute \src "libresoc.v:167970.3-167990.6" + process $proc$libresoc.v:167970$9302 assign { } { } assign { } { } assign { } { } @@ -346009,9 +342819,9 @@ module \pipe1$32 assign $0\trap_op__msr$next[63:0]$9309 $1\trap_op__msr$next[63:0]$9318 assign $0\trap_op__trapaddr$next[12:0]$9310 $1\trap_op__trapaddr$next[12:0]$9319 assign $0\trap_op__traptype$next[7:0]$9311 $1\trap_op__traptype$next[7:0]$9320 - attribute \src "libresoc.v:167972.5-167972.29" + attribute \src "libresoc.v:167971.5-167971.29" switch \initial - attribute \src "libresoc.v:167972.9-167972.17" + attribute \src "libresoc.v:167971.9-167971.17" case 1'1 case end @@ -346063,14 +342873,14 @@ module \pipe1$32 update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9310 update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9311 end - attribute \src "libresoc.v:167992.3-168004.6" - process $proc$libresoc.v:167992$9321 + attribute \src "libresoc.v:167991.3-168003.6" + process $proc$libresoc.v:167991$9321 assign { } { } assign { } { } assign $0\ra$next[63:0]$9322 $1\ra$next[63:0]$9323 - attribute \src "libresoc.v:167993.5-167993.29" + attribute \src "libresoc.v:167992.5-167992.29" switch \initial - attribute \src "libresoc.v:167993.9-167993.17" + attribute \src "libresoc.v:167992.9-167992.17" case 1'1 case end @@ -346090,14 +342900,14 @@ module \pipe1$32 sync always update \ra$next $0\ra$next[63:0]$9322 end - attribute \src "libresoc.v:168005.3-168017.6" - process $proc$libresoc.v:168005$9324 + attribute \src "libresoc.v:168004.3-168016.6" + process $proc$libresoc.v:168004$9324 assign { } { } assign { } { } assign $0\rb$next[63:0]$9325 $1\rb$next[63:0]$9326 - attribute \src "libresoc.v:168006.5-168006.29" + attribute \src "libresoc.v:168005.5-168005.29" switch \initial - attribute \src "libresoc.v:168006.9-168006.17" + attribute \src "libresoc.v:168005.9-168005.17" case 1'1 case end @@ -346117,14 +342927,14 @@ module \pipe1$32 sync always update \rb$next $0\rb$next[63:0]$9325 end - attribute \src "libresoc.v:168018.3-168030.6" - process $proc$libresoc.v:168018$9327 + attribute \src "libresoc.v:168017.3-168029.6" + process $proc$libresoc.v:168017$9327 assign { } { } assign { } { } assign $0\fast1$next[63:0]$9328 $1\fast1$next[63:0]$9329 - attribute \src "libresoc.v:168019.5-168019.29" + attribute \src "libresoc.v:168018.5-168018.29" switch \initial - attribute \src "libresoc.v:168019.9-168019.17" + attribute \src "libresoc.v:168018.9-168018.17" case 1'1 case end @@ -346144,14 +342954,14 @@ module \pipe1$32 sync always update \fast1$next $0\fast1$next[63:0]$9328 end - attribute \src "libresoc.v:168031.3-168043.6" - process $proc$libresoc.v:168031$9330 + attribute \src "libresoc.v:168030.3-168042.6" + process $proc$libresoc.v:168030$9330 assign { } { } assign { } { } assign $0\fast2$next[63:0]$9331 $1\fast2$next[63:0]$9332 - attribute \src "libresoc.v:168032.5-168032.29" + attribute \src "libresoc.v:168031.5-168031.29" switch \initial - attribute \src "libresoc.v:168032.9-168032.17" + attribute \src "libresoc.v:168031.9-168031.17" case 1'1 case end @@ -346171,7 +342981,7 @@ module \pipe1$32 sync always update \fast2$next $0\fast2$next[63:0]$9331 end - connect \$30 $and$libresoc.v:167871$9279_Y + connect \$30 $and$libresoc.v:167870$9279_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \fast2$45 \dummy_fast2$28 @@ -346190,279 +343000,279 @@ module \pipe1$32 connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } connect \dummy_muxid \muxid$1 end -attribute \src "libresoc.v:168065.1-169250.10" +attribute \src "libresoc.v:168064.1-169249.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" attribute \generator "nMigen" module \pipe2 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire width 4 $0\alu_op__data_len$18$next[3:0]$9417 - attribute \src "libresoc.v:168991.3-168992.57" + attribute \src "libresoc.v:168990.3-168991.57" wire width 4 $0\alu_op__data_len$18[3:0]$9403 - attribute \src "libresoc.v:168073.13-168073.41" + attribute \src "libresoc.v:168072.13-168072.41" wire width 4 $0\alu_op__data_len$18[3:0]$9491 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire width 14 $0\alu_op__fn_unit$3$next[13:0]$9418 - attribute \src "libresoc.v:168961.3-168962.53" + attribute \src "libresoc.v:168960.3-168961.53" wire width 14 $0\alu_op__fn_unit$3[13:0]$9373 - attribute \src "libresoc.v:168112.14-168112.44" + attribute \src "libresoc.v:168111.14-168111.44" wire width 14 $0\alu_op__fn_unit$3[13:0]$9493 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9419 - attribute \src "libresoc.v:168963.3-168964.67" + attribute \src "libresoc.v:168962.3-168963.67" wire width 64 $0\alu_op__imm_data__data$4[63:0]$9375 - attribute \src "libresoc.v:168136.14-168136.63" + attribute \src "libresoc.v:168135.14-168135.63" wire width 64 $0\alu_op__imm_data__data$4[63:0]$9495 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $0\alu_op__imm_data__ok$5$next[0:0]$9420 - attribute \src "libresoc.v:168965.3-168966.63" + attribute \src "libresoc.v:168964.3-168965.63" wire $0\alu_op__imm_data__ok$5[0:0]$9377 - attribute \src "libresoc.v:168145.7-168145.38" + attribute \src "libresoc.v:168144.7-168144.38" wire $0\alu_op__imm_data__ok$5[0:0]$9497 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire width 2 $0\alu_op__input_carry$14$next[1:0]$9421 - attribute \src "libresoc.v:168983.3-168984.63" + attribute \src "libresoc.v:168982.3-168983.63" wire width 2 $0\alu_op__input_carry$14[1:0]$9395 - attribute \src "libresoc.v:168162.13-168162.44" + attribute \src "libresoc.v:168161.13-168161.44" wire width 2 $0\alu_op__input_carry$14[1:0]$9499 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire width 32 $0\alu_op__insn$19$next[31:0]$9422 - attribute \src "libresoc.v:168993.3-168994.49" + attribute \src "libresoc.v:168992.3-168993.49" wire width 32 $0\alu_op__insn$19[31:0]$9405 - attribute \src "libresoc.v:168175.14-168175.39" + attribute \src "libresoc.v:168174.14-168174.39" wire width 32 $0\alu_op__insn$19[31:0]$9501 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire width 7 $0\alu_op__insn_type$2$next[6:0]$9423 - attribute \src "libresoc.v:168959.3-168960.57" + attribute \src "libresoc.v:168958.3-168959.57" wire width 7 $0\alu_op__insn_type$2[6:0]$9371 - attribute \src "libresoc.v:168334.13-168334.42" + attribute \src "libresoc.v:168333.13-168333.42" wire width 7 $0\alu_op__insn_type$2[6:0]$9503 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $0\alu_op__invert_in$10$next[0:0]$9424 - attribute \src "libresoc.v:168975.3-168976.59" + attribute \src "libresoc.v:168974.3-168975.59" wire $0\alu_op__invert_in$10[0:0]$9387 - attribute \src "libresoc.v:168418.7-168418.36" + attribute \src "libresoc.v:168417.7-168417.36" wire $0\alu_op__invert_in$10[0:0]$9505 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $0\alu_op__invert_out$12$next[0:0]$9425 - attribute \src "libresoc.v:168979.3-168980.61" + attribute \src "libresoc.v:168978.3-168979.61" wire $0\alu_op__invert_out$12[0:0]$9391 - attribute \src "libresoc.v:168427.7-168427.37" + attribute \src "libresoc.v:168426.7-168426.37" wire $0\alu_op__invert_out$12[0:0]$9507 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $0\alu_op__is_32bit$16$next[0:0]$9426 - attribute \src "libresoc.v:168987.3-168988.57" + attribute \src "libresoc.v:168986.3-168987.57" wire $0\alu_op__is_32bit$16[0:0]$9399 - attribute \src "libresoc.v:168436.7-168436.35" + attribute \src "libresoc.v:168435.7-168435.35" wire $0\alu_op__is_32bit$16[0:0]$9509 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $0\alu_op__is_signed$17$next[0:0]$9427 - attribute \src "libresoc.v:168989.3-168990.59" + attribute \src "libresoc.v:168988.3-168989.59" wire $0\alu_op__is_signed$17[0:0]$9401 - attribute \src "libresoc.v:168445.7-168445.36" + attribute \src "libresoc.v:168444.7-168444.36" wire $0\alu_op__is_signed$17[0:0]$9511 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $0\alu_op__oe__oe$8$next[0:0]$9428 - attribute \src "libresoc.v:168971.3-168972.51" + attribute \src "libresoc.v:168970.3-168971.51" wire $0\alu_op__oe__oe$8[0:0]$9383 - attribute \src "libresoc.v:168456.7-168456.32" + attribute \src "libresoc.v:168455.7-168455.32" wire $0\alu_op__oe__oe$8[0:0]$9513 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $0\alu_op__oe__ok$9$next[0:0]$9429 - attribute \src "libresoc.v:168973.3-168974.51" + attribute \src "libresoc.v:168972.3-168973.51" wire $0\alu_op__oe__ok$9[0:0]$9385 - attribute \src "libresoc.v:168465.7-168465.32" + attribute \src "libresoc.v:168464.7-168464.32" wire $0\alu_op__oe__ok$9[0:0]$9515 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $0\alu_op__output_carry$15$next[0:0]$9430 - attribute \src "libresoc.v:168985.3-168986.65" + attribute \src "libresoc.v:168984.3-168985.65" wire $0\alu_op__output_carry$15[0:0]$9397 - attribute \src "libresoc.v:168472.7-168472.39" + attribute \src "libresoc.v:168471.7-168471.39" wire $0\alu_op__output_carry$15[0:0]$9517 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $0\alu_op__rc__ok$7$next[0:0]$9431 - attribute \src "libresoc.v:168969.3-168970.51" + attribute \src "libresoc.v:168968.3-168969.51" wire $0\alu_op__rc__ok$7[0:0]$9381 - attribute \src "libresoc.v:168483.7-168483.32" + attribute \src "libresoc.v:168482.7-168482.32" wire $0\alu_op__rc__ok$7[0:0]$9519 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $0\alu_op__rc__rc$6$next[0:0]$9432 - attribute \src "libresoc.v:168967.3-168968.51" + attribute \src "libresoc.v:168966.3-168967.51" wire $0\alu_op__rc__rc$6[0:0]$9379 - attribute \src "libresoc.v:168490.7-168490.32" + attribute \src "libresoc.v:168489.7-168489.32" wire $0\alu_op__rc__rc$6[0:0]$9521 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $0\alu_op__write_cr0$13$next[0:0]$9433 - attribute \src "libresoc.v:168981.3-168982.59" + attribute \src "libresoc.v:168980.3-168981.59" wire $0\alu_op__write_cr0$13[0:0]$9393 - attribute \src "libresoc.v:168499.7-168499.36" + attribute \src "libresoc.v:168498.7-168498.36" wire $0\alu_op__write_cr0$13[0:0]$9523 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $0\alu_op__zero_a$11$next[0:0]$9434 - attribute \src "libresoc.v:168977.3-168978.53" + attribute \src "libresoc.v:168976.3-168977.53" wire $0\alu_op__zero_a$11[0:0]$9389 - attribute \src "libresoc.v:168508.7-168508.33" + attribute \src "libresoc.v:168507.7-168507.33" wire $0\alu_op__zero_a$11[0:0]$9525 - attribute \src "libresoc.v:169155.3-169173.6" + attribute \src "libresoc.v:169154.3-169172.6" wire width 4 $0\cr_a$22$next[3:0]$9466 - attribute \src "libresoc.v:168951.3-168952.33" + attribute \src "libresoc.v:168950.3-168951.33" wire width 4 $0\cr_a$22[3:0]$9363 - attribute \src "libresoc.v:168521.13-168521.29" + attribute \src "libresoc.v:168520.13-168520.29" wire width 4 $0\cr_a$22[3:0]$9527 - attribute \src "libresoc.v:169155.3-169173.6" + attribute \src "libresoc.v:169154.3-169172.6" wire $0\cr_a_ok$23$next[0:0]$9467 - attribute \src "libresoc.v:168953.3-168954.39" + attribute \src "libresoc.v:168952.3-168953.39" wire $0\cr_a_ok$23[0:0]$9365 - attribute \src "libresoc.v:168530.7-168530.26" + attribute \src "libresoc.v:168529.7-168529.26" wire $0\cr_a_ok$23[0:0]$9529 - attribute \src "libresoc.v:168066.7-168066.20" + attribute \src "libresoc.v:168065.7-168065.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169081.3-169093.6" + attribute \src "libresoc.v:169080.3-169092.6" wire width 2 $0\muxid$1$next[1:0]$9414 - attribute \src "libresoc.v:168995.3-168996.33" + attribute \src "libresoc.v:168994.3-168995.33" wire width 2 $0\muxid$1[1:0]$9407 - attribute \src "libresoc.v:168541.13-168541.29" + attribute \src "libresoc.v:168540.13-168540.29" wire width 2 $0\muxid$1[1:0]$9531 - attribute \src "libresoc.v:169136.3-169154.6" + attribute \src "libresoc.v:169135.3-169153.6" wire width 64 $0\o$20$next[63:0]$9460 - attribute \src "libresoc.v:168955.3-168956.27" + attribute \src "libresoc.v:168954.3-168955.27" wire width 64 $0\o$20[63:0]$9367 - attribute \src "libresoc.v:168556.14-168556.43" + attribute \src "libresoc.v:168555.14-168555.43" wire width 64 $0\o$20[63:0]$9533 - attribute \src "libresoc.v:169136.3-169154.6" + attribute \src "libresoc.v:169135.3-169153.6" wire $0\o_ok$21$next[0:0]$9461 - attribute \src "libresoc.v:168957.3-168958.33" + attribute \src "libresoc.v:168956.3-168957.33" wire $0\o_ok$21[0:0]$9369 - attribute \src "libresoc.v:168565.7-168565.23" + attribute \src "libresoc.v:168564.7-168564.23" wire $0\o_ok$21[0:0]$9535 - attribute \src "libresoc.v:169063.3-169080.6" + attribute \src "libresoc.v:169062.3-169079.6" wire $0\r_busy$next[0:0]$9410 - attribute \src "libresoc.v:168997.3-168998.29" + attribute \src "libresoc.v:168996.3-168997.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:169174.3-169192.6" + attribute \src "libresoc.v:169173.3-169191.6" wire width 2 $0\xer_ca$24$next[1:0]$9472 - attribute \src "libresoc.v:168947.3-168948.37" + attribute \src "libresoc.v:168946.3-168947.37" wire width 2 $0\xer_ca$24[1:0]$9359 - attribute \src "libresoc.v:168882.13-168882.31" + attribute \src "libresoc.v:168881.13-168881.31" wire width 2 $0\xer_ca$24[1:0]$9538 - attribute \src "libresoc.v:169174.3-169192.6" + attribute \src "libresoc.v:169173.3-169191.6" wire $0\xer_ca_ok$25$next[0:0]$9473 - attribute \src "libresoc.v:168949.3-168950.43" + attribute \src "libresoc.v:168948.3-168949.43" wire $0\xer_ca_ok$25[0:0]$9361 - attribute \src "libresoc.v:168891.7-168891.28" + attribute \src "libresoc.v:168890.7-168890.28" wire $0\xer_ca_ok$25[0:0]$9540 - attribute \src "libresoc.v:169193.3-169211.6" + attribute \src "libresoc.v:169192.3-169210.6" wire width 2 $0\xer_ov$26$next[1:0]$9478 - attribute \src "libresoc.v:168943.3-168944.37" + attribute \src "libresoc.v:168942.3-168943.37" wire width 2 $0\xer_ov$26[1:0]$9355 - attribute \src "libresoc.v:168902.13-168902.31" + attribute \src "libresoc.v:168901.13-168901.31" wire width 2 $0\xer_ov$26[1:0]$9542 - attribute \src "libresoc.v:169193.3-169211.6" + attribute \src "libresoc.v:169192.3-169210.6" wire $0\xer_ov_ok$27$next[0:0]$9479 - attribute \src "libresoc.v:168945.3-168946.43" + attribute \src "libresoc.v:168944.3-168945.43" wire $0\xer_ov_ok$27[0:0]$9357 - attribute \src "libresoc.v:168911.7-168911.28" + attribute \src "libresoc.v:168910.7-168910.28" wire $0\xer_ov_ok$27[0:0]$9544 - attribute \src "libresoc.v:169212.3-169230.6" + attribute \src "libresoc.v:169211.3-169229.6" wire $0\xer_so$28$next[0:0]$9484 - attribute \src "libresoc.v:168939.3-168940.37" + attribute \src "libresoc.v:168938.3-168939.37" wire $0\xer_so$28[0:0]$9351 - attribute \src "libresoc.v:168922.7-168922.25" + attribute \src "libresoc.v:168921.7-168921.25" wire $0\xer_so$28[0:0]$9546 - attribute \src "libresoc.v:169212.3-169230.6" + attribute \src "libresoc.v:169211.3-169229.6" wire $0\xer_so_ok$29$next[0:0]$9485 - attribute \src "libresoc.v:168941.3-168942.43" + attribute \src "libresoc.v:168940.3-168941.43" wire $0\xer_so_ok$29[0:0]$9353 - attribute \src "libresoc.v:168931.7-168931.28" + attribute \src "libresoc.v:168930.7-168930.28" wire $0\xer_so_ok$29[0:0]$9548 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire width 4 $1\alu_op__data_len$18$next[3:0]$9435 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire width 14 $1\alu_op__fn_unit$3$next[13:0]$9436 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9437 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $1\alu_op__imm_data__ok$5$next[0:0]$9438 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire width 2 $1\alu_op__input_carry$14$next[1:0]$9439 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire width 32 $1\alu_op__insn$19$next[31:0]$9440 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire width 7 $1\alu_op__insn_type$2$next[6:0]$9441 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $1\alu_op__invert_in$10$next[0:0]$9442 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $1\alu_op__invert_out$12$next[0:0]$9443 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $1\alu_op__is_32bit$16$next[0:0]$9444 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $1\alu_op__is_signed$17$next[0:0]$9445 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $1\alu_op__oe__oe$8$next[0:0]$9446 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $1\alu_op__oe__ok$9$next[0:0]$9447 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $1\alu_op__output_carry$15$next[0:0]$9448 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $1\alu_op__rc__ok$7$next[0:0]$9449 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $1\alu_op__rc__rc$6$next[0:0]$9450 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $1\alu_op__write_cr0$13$next[0:0]$9451 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $1\alu_op__zero_a$11$next[0:0]$9452 - attribute \src "libresoc.v:169155.3-169173.6" + attribute \src "libresoc.v:169154.3-169172.6" wire width 4 $1\cr_a$22$next[3:0]$9468 - attribute \src "libresoc.v:169155.3-169173.6" + attribute \src "libresoc.v:169154.3-169172.6" wire $1\cr_a_ok$23$next[0:0]$9469 - attribute \src "libresoc.v:169081.3-169093.6" + attribute \src "libresoc.v:169080.3-169092.6" wire width 2 $1\muxid$1$next[1:0]$9415 - attribute \src "libresoc.v:169136.3-169154.6" + attribute \src "libresoc.v:169135.3-169153.6" wire width 64 $1\o$20$next[63:0]$9462 - attribute \src "libresoc.v:169136.3-169154.6" + attribute \src "libresoc.v:169135.3-169153.6" wire $1\o_ok$21$next[0:0]$9463 - attribute \src "libresoc.v:169063.3-169080.6" + attribute \src "libresoc.v:169062.3-169079.6" wire $1\r_busy$next[0:0]$9411 - attribute \src "libresoc.v:168875.7-168875.20" + attribute \src "libresoc.v:168874.7-168874.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:169174.3-169192.6" + attribute \src "libresoc.v:169173.3-169191.6" wire width 2 $1\xer_ca$24$next[1:0]$9474 - attribute \src "libresoc.v:169174.3-169192.6" + attribute \src "libresoc.v:169173.3-169191.6" wire $1\xer_ca_ok$25$next[0:0]$9475 - attribute \src "libresoc.v:169193.3-169211.6" + attribute \src "libresoc.v:169192.3-169210.6" wire width 2 $1\xer_ov$26$next[1:0]$9480 - attribute \src "libresoc.v:169193.3-169211.6" + attribute \src "libresoc.v:169192.3-169210.6" wire $1\xer_ov_ok$27$next[0:0]$9481 - attribute \src "libresoc.v:169212.3-169230.6" + attribute \src "libresoc.v:169211.3-169229.6" wire $1\xer_so$28$next[0:0]$9486 - attribute \src "libresoc.v:169212.3-169230.6" + attribute \src "libresoc.v:169211.3-169229.6" wire $1\xer_so_ok$29$next[0:0]$9487 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9453 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $2\alu_op__imm_data__ok$5$next[0:0]$9454 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $2\alu_op__oe__oe$8$next[0:0]$9455 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $2\alu_op__oe__ok$9$next[0:0]$9456 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $2\alu_op__rc__ok$7$next[0:0]$9457 - attribute \src "libresoc.v:169094.3-169135.6" + attribute \src "libresoc.v:169093.3-169134.6" wire $2\alu_op__rc__rc$6$next[0:0]$9458 - attribute \src "libresoc.v:169155.3-169173.6" + attribute \src "libresoc.v:169154.3-169172.6" wire $2\cr_a_ok$23$next[0:0]$9470 - attribute \src "libresoc.v:169136.3-169154.6" + attribute \src "libresoc.v:169135.3-169153.6" wire $2\o_ok$21$next[0:0]$9464 - attribute \src "libresoc.v:169063.3-169080.6" + attribute \src "libresoc.v:169062.3-169079.6" wire $2\r_busy$next[0:0]$9412 - attribute \src "libresoc.v:169174.3-169192.6" + attribute \src "libresoc.v:169173.3-169191.6" wire $2\xer_ca_ok$25$next[0:0]$9476 - attribute \src "libresoc.v:169193.3-169211.6" + attribute \src "libresoc.v:169192.3-169210.6" wire $2\xer_ov_ok$27$next[0:0]$9482 - attribute \src "libresoc.v:169212.3-169230.6" + attribute \src "libresoc.v:169211.3-169229.6" wire $2\xer_so_ok$29$next[0:0]$9488 - attribute \src "libresoc.v:168938.18-168938.118" - wire $and$libresoc.v:168938$9349_Y + attribute \src "libresoc.v:168937.18-168937.118" + wire $and$libresoc.v:168937$9349_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -346913,7 +343723,7 @@ module \pipe2 wire \cr_a_ok$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$84 - attribute \src "libresoc.v:168066.7-168066.15" + attribute \src "libresoc.v:168065.7-168065.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -347308,7 +344118,7 @@ module \pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:168938$9349 + cell $and $and$libresoc.v:168937$9349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347316,16 +344126,16 @@ module \pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$59 connect \B \p_ready_o - connect \Y $and$libresoc.v:168938$9349_Y + connect \Y $and$libresoc.v:168937$9349_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:168999.9-169002.4" + attribute \src "libresoc.v:168998.9-169001.4" cell \n$4 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:169003.12-169058.4" + attribute \src "libresoc.v:169002.12-169057.4" cell \output \output connect \alu_op__data_len \output_alu_op__data_len connect \alu_op__data_len$18 \output_alu_op__data_len$47 @@ -347383,478 +344193,478 @@ module \pipe2 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:169059.9-169062.4" + attribute \src "libresoc.v:169058.9-169061.4" cell \p$3 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:168066.7-168066.20" - process $proc$libresoc.v:168066$9489 + attribute \src "libresoc.v:168065.7-168065.20" + process $proc$libresoc.v:168065$9489 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:168073.13-168073.41" - process $proc$libresoc.v:168073$9490 + attribute \src "libresoc.v:168072.13-168072.41" + process $proc$libresoc.v:168072$9490 assign { } { } assign $0\alu_op__data_len$18[3:0]$9491 4'0000 sync always sync init update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9491 end - attribute \src "libresoc.v:168112.14-168112.44" - process $proc$libresoc.v:168112$9492 + attribute \src "libresoc.v:168111.14-168111.44" + process $proc$libresoc.v:168111$9492 assign { } { } assign $0\alu_op__fn_unit$3[13:0]$9493 14'00000000000000 sync always sync init update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9493 end - attribute \src "libresoc.v:168136.14-168136.63" - process $proc$libresoc.v:168136$9494 + attribute \src "libresoc.v:168135.14-168135.63" + process $proc$libresoc.v:168135$9494 assign { } { } assign $0\alu_op__imm_data__data$4[63:0]$9495 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9495 end - attribute \src "libresoc.v:168145.7-168145.38" - process $proc$libresoc.v:168145$9496 + attribute \src "libresoc.v:168144.7-168144.38" + process $proc$libresoc.v:168144$9496 assign { } { } assign $0\alu_op__imm_data__ok$5[0:0]$9497 1'0 sync always sync init update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9497 end - attribute \src "libresoc.v:168162.13-168162.44" - process $proc$libresoc.v:168162$9498 + attribute \src "libresoc.v:168161.13-168161.44" + process $proc$libresoc.v:168161$9498 assign { } { } assign $0\alu_op__input_carry$14[1:0]$9499 2'00 sync always sync init update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9499 end - attribute \src "libresoc.v:168175.14-168175.39" - process $proc$libresoc.v:168175$9500 + attribute \src "libresoc.v:168174.14-168174.39" + process $proc$libresoc.v:168174$9500 assign { } { } assign $0\alu_op__insn$19[31:0]$9501 0 sync always sync init update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9501 end - attribute \src "libresoc.v:168334.13-168334.42" - process $proc$libresoc.v:168334$9502 + attribute \src "libresoc.v:168333.13-168333.42" + process $proc$libresoc.v:168333$9502 assign { } { } assign $0\alu_op__insn_type$2[6:0]$9503 7'0000000 sync always sync init update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9503 end - attribute \src "libresoc.v:168418.7-168418.36" - process $proc$libresoc.v:168418$9504 + attribute \src "libresoc.v:168417.7-168417.36" + process $proc$libresoc.v:168417$9504 assign { } { } assign $0\alu_op__invert_in$10[0:0]$9505 1'0 sync always sync init update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9505 end - attribute \src "libresoc.v:168427.7-168427.37" - process $proc$libresoc.v:168427$9506 + attribute \src "libresoc.v:168426.7-168426.37" + process $proc$libresoc.v:168426$9506 assign { } { } assign $0\alu_op__invert_out$12[0:0]$9507 1'0 sync always sync init update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9507 end - attribute \src "libresoc.v:168436.7-168436.35" - process $proc$libresoc.v:168436$9508 + attribute \src "libresoc.v:168435.7-168435.35" + process $proc$libresoc.v:168435$9508 assign { } { } assign $0\alu_op__is_32bit$16[0:0]$9509 1'0 sync always sync init update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9509 end - attribute \src "libresoc.v:168445.7-168445.36" - process $proc$libresoc.v:168445$9510 + attribute \src "libresoc.v:168444.7-168444.36" + process $proc$libresoc.v:168444$9510 assign { } { } assign $0\alu_op__is_signed$17[0:0]$9511 1'0 sync always sync init update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9511 end - attribute \src "libresoc.v:168456.7-168456.32" - process $proc$libresoc.v:168456$9512 + attribute \src "libresoc.v:168455.7-168455.32" + process $proc$libresoc.v:168455$9512 assign { } { } assign $0\alu_op__oe__oe$8[0:0]$9513 1'0 sync always sync init update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9513 end - attribute \src "libresoc.v:168465.7-168465.32" - process $proc$libresoc.v:168465$9514 + attribute \src "libresoc.v:168464.7-168464.32" + process $proc$libresoc.v:168464$9514 assign { } { } assign $0\alu_op__oe__ok$9[0:0]$9515 1'0 sync always sync init update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9515 end - attribute \src "libresoc.v:168472.7-168472.39" - process $proc$libresoc.v:168472$9516 + attribute \src "libresoc.v:168471.7-168471.39" + process $proc$libresoc.v:168471$9516 assign { } { } assign $0\alu_op__output_carry$15[0:0]$9517 1'0 sync always sync init update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9517 end - attribute \src "libresoc.v:168483.7-168483.32" - process $proc$libresoc.v:168483$9518 + attribute \src "libresoc.v:168482.7-168482.32" + process $proc$libresoc.v:168482$9518 assign { } { } assign $0\alu_op__rc__ok$7[0:0]$9519 1'0 sync always sync init update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9519 end - attribute \src "libresoc.v:168490.7-168490.32" - process $proc$libresoc.v:168490$9520 + attribute \src "libresoc.v:168489.7-168489.32" + process $proc$libresoc.v:168489$9520 assign { } { } assign $0\alu_op__rc__rc$6[0:0]$9521 1'0 sync always sync init update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9521 end - attribute \src "libresoc.v:168499.7-168499.36" - process $proc$libresoc.v:168499$9522 + attribute \src "libresoc.v:168498.7-168498.36" + process $proc$libresoc.v:168498$9522 assign { } { } assign $0\alu_op__write_cr0$13[0:0]$9523 1'0 sync always sync init update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9523 end - attribute \src "libresoc.v:168508.7-168508.33" - process $proc$libresoc.v:168508$9524 + attribute \src "libresoc.v:168507.7-168507.33" + process $proc$libresoc.v:168507$9524 assign { } { } assign $0\alu_op__zero_a$11[0:0]$9525 1'0 sync always sync init update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9525 end - attribute \src "libresoc.v:168521.13-168521.29" - process $proc$libresoc.v:168521$9526 + attribute \src "libresoc.v:168520.13-168520.29" + process $proc$libresoc.v:168520$9526 assign { } { } assign $0\cr_a$22[3:0]$9527 4'0000 sync always sync init update \cr_a$22 $0\cr_a$22[3:0]$9527 end - attribute \src "libresoc.v:168530.7-168530.26" - process $proc$libresoc.v:168530$9528 + attribute \src "libresoc.v:168529.7-168529.26" + process $proc$libresoc.v:168529$9528 assign { } { } assign $0\cr_a_ok$23[0:0]$9529 1'0 sync always sync init update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9529 end - attribute \src "libresoc.v:168541.13-168541.29" - process $proc$libresoc.v:168541$9530 + attribute \src "libresoc.v:168540.13-168540.29" + process $proc$libresoc.v:168540$9530 assign { } { } assign $0\muxid$1[1:0]$9531 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$9531 end - attribute \src "libresoc.v:168556.14-168556.43" - process $proc$libresoc.v:168556$9532 + attribute \src "libresoc.v:168555.14-168555.43" + process $proc$libresoc.v:168555$9532 assign { } { } assign $0\o$20[63:0]$9533 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o$20 $0\o$20[63:0]$9533 end - attribute \src "libresoc.v:168565.7-168565.23" - process $proc$libresoc.v:168565$9534 + attribute \src "libresoc.v:168564.7-168564.23" + process $proc$libresoc.v:168564$9534 assign { } { } assign $0\o_ok$21[0:0]$9535 1'0 sync always sync init update \o_ok$21 $0\o_ok$21[0:0]$9535 end - attribute \src "libresoc.v:168875.7-168875.20" - process $proc$libresoc.v:168875$9536 + attribute \src "libresoc.v:168874.7-168874.20" + process $proc$libresoc.v:168874$9536 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:168882.13-168882.31" - process $proc$libresoc.v:168882$9537 + attribute \src "libresoc.v:168881.13-168881.31" + process $proc$libresoc.v:168881$9537 assign { } { } assign $0\xer_ca$24[1:0]$9538 2'00 sync always sync init update \xer_ca$24 $0\xer_ca$24[1:0]$9538 end - attribute \src "libresoc.v:168891.7-168891.28" - process $proc$libresoc.v:168891$9539 + attribute \src "libresoc.v:168890.7-168890.28" + process $proc$libresoc.v:168890$9539 assign { } { } assign $0\xer_ca_ok$25[0:0]$9540 1'0 sync always sync init update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9540 end - attribute \src "libresoc.v:168902.13-168902.31" - process $proc$libresoc.v:168902$9541 + attribute \src "libresoc.v:168901.13-168901.31" + process $proc$libresoc.v:168901$9541 assign { } { } assign $0\xer_ov$26[1:0]$9542 2'00 sync always sync init update \xer_ov$26 $0\xer_ov$26[1:0]$9542 end - attribute \src "libresoc.v:168911.7-168911.28" - process $proc$libresoc.v:168911$9543 + attribute \src "libresoc.v:168910.7-168910.28" + process $proc$libresoc.v:168910$9543 assign { } { } assign $0\xer_ov_ok$27[0:0]$9544 1'0 sync always sync init update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9544 end - attribute \src "libresoc.v:168922.7-168922.25" - process $proc$libresoc.v:168922$9545 + attribute \src "libresoc.v:168921.7-168921.25" + process $proc$libresoc.v:168921$9545 assign { } { } assign $0\xer_so$28[0:0]$9546 1'0 sync always sync init update \xer_so$28 $0\xer_so$28[0:0]$9546 end - attribute \src "libresoc.v:168931.7-168931.28" - process $proc$libresoc.v:168931$9547 + attribute \src "libresoc.v:168930.7-168930.28" + process $proc$libresoc.v:168930$9547 assign { } { } assign $0\xer_so_ok$29[0:0]$9548 1'0 sync always sync init update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9548 end - attribute \src "libresoc.v:168939.3-168940.37" - process $proc$libresoc.v:168939$9350 + attribute \src "libresoc.v:168938.3-168939.37" + process $proc$libresoc.v:168938$9350 assign { } { } assign $0\xer_so$28[0:0]$9351 \xer_so$28$next sync posedge \coresync_clk update \xer_so$28 $0\xer_so$28[0:0]$9351 end - attribute \src "libresoc.v:168941.3-168942.43" - process $proc$libresoc.v:168941$9352 + attribute \src "libresoc.v:168940.3-168941.43" + process $proc$libresoc.v:168940$9352 assign { } { } assign $0\xer_so_ok$29[0:0]$9353 \xer_so_ok$29$next sync posedge \coresync_clk update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9353 end - attribute \src "libresoc.v:168943.3-168944.37" - process $proc$libresoc.v:168943$9354 + attribute \src "libresoc.v:168942.3-168943.37" + process $proc$libresoc.v:168942$9354 assign { } { } assign $0\xer_ov$26[1:0]$9355 \xer_ov$26$next sync posedge \coresync_clk update \xer_ov$26 $0\xer_ov$26[1:0]$9355 end - attribute \src "libresoc.v:168945.3-168946.43" - process $proc$libresoc.v:168945$9356 + attribute \src "libresoc.v:168944.3-168945.43" + process $proc$libresoc.v:168944$9356 assign { } { } assign $0\xer_ov_ok$27[0:0]$9357 \xer_ov_ok$27$next sync posedge \coresync_clk update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9357 end - attribute \src "libresoc.v:168947.3-168948.37" - process $proc$libresoc.v:168947$9358 + attribute \src "libresoc.v:168946.3-168947.37" + process $proc$libresoc.v:168946$9358 assign { } { } assign $0\xer_ca$24[1:0]$9359 \xer_ca$24$next sync posedge \coresync_clk update \xer_ca$24 $0\xer_ca$24[1:0]$9359 end - attribute \src "libresoc.v:168949.3-168950.43" - process $proc$libresoc.v:168949$9360 + attribute \src "libresoc.v:168948.3-168949.43" + process $proc$libresoc.v:168948$9360 assign { } { } assign $0\xer_ca_ok$25[0:0]$9361 \xer_ca_ok$25$next sync posedge \coresync_clk update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9361 end - attribute \src "libresoc.v:168951.3-168952.33" - process $proc$libresoc.v:168951$9362 + attribute \src "libresoc.v:168950.3-168951.33" + process $proc$libresoc.v:168950$9362 assign { } { } assign $0\cr_a$22[3:0]$9363 \cr_a$22$next sync posedge \coresync_clk update \cr_a$22 $0\cr_a$22[3:0]$9363 end - attribute \src "libresoc.v:168953.3-168954.39" - process $proc$libresoc.v:168953$9364 + attribute \src "libresoc.v:168952.3-168953.39" + process $proc$libresoc.v:168952$9364 assign { } { } assign $0\cr_a_ok$23[0:0]$9365 \cr_a_ok$23$next sync posedge \coresync_clk update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9365 end - attribute \src "libresoc.v:168955.3-168956.27" - process $proc$libresoc.v:168955$9366 + attribute \src "libresoc.v:168954.3-168955.27" + process $proc$libresoc.v:168954$9366 assign { } { } assign $0\o$20[63:0]$9367 \o$20$next sync posedge \coresync_clk update \o$20 $0\o$20[63:0]$9367 end - attribute \src "libresoc.v:168957.3-168958.33" - process $proc$libresoc.v:168957$9368 + attribute \src "libresoc.v:168956.3-168957.33" + process $proc$libresoc.v:168956$9368 assign { } { } assign $0\o_ok$21[0:0]$9369 \o_ok$21$next sync posedge \coresync_clk update \o_ok$21 $0\o_ok$21[0:0]$9369 end - attribute \src "libresoc.v:168959.3-168960.57" - process $proc$libresoc.v:168959$9370 + attribute \src "libresoc.v:168958.3-168959.57" + process $proc$libresoc.v:168958$9370 assign { } { } assign $0\alu_op__insn_type$2[6:0]$9371 \alu_op__insn_type$2$next sync posedge \coresync_clk update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9371 end - attribute \src "libresoc.v:168961.3-168962.53" - process $proc$libresoc.v:168961$9372 + attribute \src "libresoc.v:168960.3-168961.53" + process $proc$libresoc.v:168960$9372 assign { } { } assign $0\alu_op__fn_unit$3[13:0]$9373 \alu_op__fn_unit$3$next sync posedge \coresync_clk update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9373 end - attribute \src "libresoc.v:168963.3-168964.67" - process $proc$libresoc.v:168963$9374 + attribute \src "libresoc.v:168962.3-168963.67" + process $proc$libresoc.v:168962$9374 assign { } { } assign $0\alu_op__imm_data__data$4[63:0]$9375 \alu_op__imm_data__data$4$next sync posedge \coresync_clk update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9375 end - attribute \src "libresoc.v:168965.3-168966.63" - process $proc$libresoc.v:168965$9376 + attribute \src "libresoc.v:168964.3-168965.63" + process $proc$libresoc.v:168964$9376 assign { } { } assign $0\alu_op__imm_data__ok$5[0:0]$9377 \alu_op__imm_data__ok$5$next sync posedge \coresync_clk update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9377 end - attribute \src "libresoc.v:168967.3-168968.51" - process $proc$libresoc.v:168967$9378 + attribute \src "libresoc.v:168966.3-168967.51" + process $proc$libresoc.v:168966$9378 assign { } { } assign $0\alu_op__rc__rc$6[0:0]$9379 \alu_op__rc__rc$6$next sync posedge \coresync_clk update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9379 end - attribute \src "libresoc.v:168969.3-168970.51" - process $proc$libresoc.v:168969$9380 + attribute \src "libresoc.v:168968.3-168969.51" + process $proc$libresoc.v:168968$9380 assign { } { } assign $0\alu_op__rc__ok$7[0:0]$9381 \alu_op__rc__ok$7$next sync posedge \coresync_clk update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9381 end - attribute \src "libresoc.v:168971.3-168972.51" - process $proc$libresoc.v:168971$9382 + attribute \src "libresoc.v:168970.3-168971.51" + process $proc$libresoc.v:168970$9382 assign { } { } assign $0\alu_op__oe__oe$8[0:0]$9383 \alu_op__oe__oe$8$next sync posedge \coresync_clk update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9383 end - attribute \src "libresoc.v:168973.3-168974.51" - process $proc$libresoc.v:168973$9384 + attribute \src "libresoc.v:168972.3-168973.51" + process $proc$libresoc.v:168972$9384 assign { } { } assign $0\alu_op__oe__ok$9[0:0]$9385 \alu_op__oe__ok$9$next sync posedge \coresync_clk update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9385 end - attribute \src "libresoc.v:168975.3-168976.59" - process $proc$libresoc.v:168975$9386 + attribute \src "libresoc.v:168974.3-168975.59" + process $proc$libresoc.v:168974$9386 assign { } { } assign $0\alu_op__invert_in$10[0:0]$9387 \alu_op__invert_in$10$next sync posedge \coresync_clk update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9387 end - attribute \src "libresoc.v:168977.3-168978.53" - process $proc$libresoc.v:168977$9388 + attribute \src "libresoc.v:168976.3-168977.53" + process $proc$libresoc.v:168976$9388 assign { } { } assign $0\alu_op__zero_a$11[0:0]$9389 \alu_op__zero_a$11$next sync posedge \coresync_clk update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9389 end - attribute \src "libresoc.v:168979.3-168980.61" - process $proc$libresoc.v:168979$9390 + attribute \src "libresoc.v:168978.3-168979.61" + process $proc$libresoc.v:168978$9390 assign { } { } assign $0\alu_op__invert_out$12[0:0]$9391 \alu_op__invert_out$12$next sync posedge \coresync_clk update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9391 end - attribute \src "libresoc.v:168981.3-168982.59" - process $proc$libresoc.v:168981$9392 + attribute \src "libresoc.v:168980.3-168981.59" + process $proc$libresoc.v:168980$9392 assign { } { } assign $0\alu_op__write_cr0$13[0:0]$9393 \alu_op__write_cr0$13$next sync posedge \coresync_clk update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9393 end - attribute \src "libresoc.v:168983.3-168984.63" - process $proc$libresoc.v:168983$9394 + attribute \src "libresoc.v:168982.3-168983.63" + process $proc$libresoc.v:168982$9394 assign { } { } assign $0\alu_op__input_carry$14[1:0]$9395 \alu_op__input_carry$14$next sync posedge \coresync_clk update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9395 end - attribute \src "libresoc.v:168985.3-168986.65" - process $proc$libresoc.v:168985$9396 + attribute \src "libresoc.v:168984.3-168985.65" + process $proc$libresoc.v:168984$9396 assign { } { } assign $0\alu_op__output_carry$15[0:0]$9397 \alu_op__output_carry$15$next sync posedge \coresync_clk update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9397 end - attribute \src "libresoc.v:168987.3-168988.57" - process $proc$libresoc.v:168987$9398 + attribute \src "libresoc.v:168986.3-168987.57" + process $proc$libresoc.v:168986$9398 assign { } { } assign $0\alu_op__is_32bit$16[0:0]$9399 \alu_op__is_32bit$16$next sync posedge \coresync_clk update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9399 end - attribute \src "libresoc.v:168989.3-168990.59" - process $proc$libresoc.v:168989$9400 + attribute \src "libresoc.v:168988.3-168989.59" + process $proc$libresoc.v:168988$9400 assign { } { } assign $0\alu_op__is_signed$17[0:0]$9401 \alu_op__is_signed$17$next sync posedge \coresync_clk update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9401 end - attribute \src "libresoc.v:168991.3-168992.57" - process $proc$libresoc.v:168991$9402 + attribute \src "libresoc.v:168990.3-168991.57" + process $proc$libresoc.v:168990$9402 assign { } { } assign $0\alu_op__data_len$18[3:0]$9403 \alu_op__data_len$18$next sync posedge \coresync_clk update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9403 end - attribute \src "libresoc.v:168993.3-168994.49" - process $proc$libresoc.v:168993$9404 + attribute \src "libresoc.v:168992.3-168993.49" + process $proc$libresoc.v:168992$9404 assign { } { } assign $0\alu_op__insn$19[31:0]$9405 \alu_op__insn$19$next sync posedge \coresync_clk update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9405 end - attribute \src "libresoc.v:168995.3-168996.33" - process $proc$libresoc.v:168995$9406 + attribute \src "libresoc.v:168994.3-168995.33" + process $proc$libresoc.v:168994$9406 assign { } { } assign $0\muxid$1[1:0]$9407 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$9407 end - attribute \src "libresoc.v:168997.3-168998.29" - process $proc$libresoc.v:168997$9408 + attribute \src "libresoc.v:168996.3-168997.29" + process $proc$libresoc.v:168996$9408 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:169063.3-169080.6" - process $proc$libresoc.v:169063$9409 + attribute \src "libresoc.v:169062.3-169079.6" + process $proc$libresoc.v:169062$9409 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9410 $2\r_busy$next[0:0]$9412 - attribute \src "libresoc.v:169064.5-169064.29" + attribute \src "libresoc.v:169063.5-169063.29" switch \initial - attribute \src "libresoc.v:169064.9-169064.17" + attribute \src "libresoc.v:169063.9-169063.17" case 1'1 case end @@ -347883,14 +344693,14 @@ module \pipe2 sync always update \r_busy$next $0\r_busy$next[0:0]$9410 end - attribute \src "libresoc.v:169081.3-169093.6" - process $proc$libresoc.v:169081$9413 + attribute \src "libresoc.v:169080.3-169092.6" + process $proc$libresoc.v:169080$9413 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$9414 $1\muxid$1$next[1:0]$9415 - attribute \src "libresoc.v:169082.5-169082.29" + attribute \src "libresoc.v:169081.5-169081.29" switch \initial - attribute \src "libresoc.v:169082.9-169082.17" + attribute \src "libresoc.v:169081.9-169081.17" case 1'1 case end @@ -347910,8 +344720,8 @@ module \pipe2 sync always update \muxid$1$next $0\muxid$1$next[1:0]$9414 end - attribute \src "libresoc.v:169094.3-169135.6" - process $proc$libresoc.v:169094$9416 + attribute \src "libresoc.v:169093.3-169134.6" + process $proc$libresoc.v:169093$9416 assign { } { } assign { } { } assign { } { } @@ -347972,9 +344782,9 @@ module \pipe2 assign $0\alu_op__oe__ok$9$next[0:0]$9429 $2\alu_op__oe__ok$9$next[0:0]$9456 assign $0\alu_op__rc__ok$7$next[0:0]$9431 $2\alu_op__rc__ok$7$next[0:0]$9457 assign $0\alu_op__rc__rc$6$next[0:0]$9432 $2\alu_op__rc__rc$6$next[0:0]$9458 - attribute \src "libresoc.v:169095.5-169095.29" + attribute \src "libresoc.v:169094.5-169094.29" switch \initial - attribute \src "libresoc.v:169095.9-169095.17" + attribute \src "libresoc.v:169094.9-169094.17" case 1'1 case end @@ -348086,8 +344896,8 @@ module \pipe2 update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9433 update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9434 end - attribute \src "libresoc.v:169136.3-169154.6" - process $proc$libresoc.v:169136$9459 + attribute \src "libresoc.v:169135.3-169153.6" + process $proc$libresoc.v:169135$9459 assign { } { } assign { } { } assign { } { } @@ -348095,9 +344905,9 @@ module \pipe2 assign $0\o$20$next[63:0]$9460 $1\o$20$next[63:0]$9462 assign { } { } assign $0\o_ok$21$next[0:0]$9461 $2\o_ok$21$next[0:0]$9464 - attribute \src "libresoc.v:169137.5-169137.29" + attribute \src "libresoc.v:169136.5-169136.29" switch \initial - attribute \src "libresoc.v:169137.9-169137.17" + attribute \src "libresoc.v:169136.9-169136.17" case 1'1 case end @@ -348130,8 +344940,8 @@ module \pipe2 update \o$20$next $0\o$20$next[63:0]$9460 update \o_ok$21$next $0\o_ok$21$next[0:0]$9461 end - attribute \src "libresoc.v:169155.3-169173.6" - process $proc$libresoc.v:169155$9465 + attribute \src "libresoc.v:169154.3-169172.6" + process $proc$libresoc.v:169154$9465 assign { } { } assign { } { } assign { } { } @@ -348139,9 +344949,9 @@ module \pipe2 assign $0\cr_a$22$next[3:0]$9466 $1\cr_a$22$next[3:0]$9468 assign { } { } assign $0\cr_a_ok$23$next[0:0]$9467 $2\cr_a_ok$23$next[0:0]$9470 - attribute \src "libresoc.v:169156.5-169156.29" + attribute \src "libresoc.v:169155.5-169155.29" switch \initial - attribute \src "libresoc.v:169156.9-169156.17" + attribute \src "libresoc.v:169155.9-169155.17" case 1'1 case end @@ -348174,8 +344984,8 @@ module \pipe2 update \cr_a$22$next $0\cr_a$22$next[3:0]$9466 update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9467 end - attribute \src "libresoc.v:169174.3-169192.6" - process $proc$libresoc.v:169174$9471 + attribute \src "libresoc.v:169173.3-169191.6" + process $proc$libresoc.v:169173$9471 assign { } { } assign { } { } assign { } { } @@ -348183,9 +344993,9 @@ module \pipe2 assign $0\xer_ca$24$next[1:0]$9472 $1\xer_ca$24$next[1:0]$9474 assign { } { } assign $0\xer_ca_ok$25$next[0:0]$9473 $2\xer_ca_ok$25$next[0:0]$9476 - attribute \src "libresoc.v:169175.5-169175.29" + attribute \src "libresoc.v:169174.5-169174.29" switch \initial - attribute \src "libresoc.v:169175.9-169175.17" + attribute \src "libresoc.v:169174.9-169174.17" case 1'1 case end @@ -348218,8 +345028,8 @@ module \pipe2 update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9472 update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9473 end - attribute \src "libresoc.v:169193.3-169211.6" - process $proc$libresoc.v:169193$9477 + attribute \src "libresoc.v:169192.3-169210.6" + process $proc$libresoc.v:169192$9477 assign { } { } assign { } { } assign { } { } @@ -348227,9 +345037,9 @@ module \pipe2 assign $0\xer_ov$26$next[1:0]$9478 $1\xer_ov$26$next[1:0]$9480 assign { } { } assign $0\xer_ov_ok$27$next[0:0]$9479 $2\xer_ov_ok$27$next[0:0]$9482 - attribute \src "libresoc.v:169194.5-169194.29" + attribute \src "libresoc.v:169193.5-169193.29" switch \initial - attribute \src "libresoc.v:169194.9-169194.17" + attribute \src "libresoc.v:169193.9-169193.17" case 1'1 case end @@ -348262,8 +345072,8 @@ module \pipe2 update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9478 update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9479 end - attribute \src "libresoc.v:169212.3-169230.6" - process $proc$libresoc.v:169212$9483 + attribute \src "libresoc.v:169211.3-169229.6" + process $proc$libresoc.v:169211$9483 assign { } { } assign { } { } assign { } { } @@ -348271,9 +345081,9 @@ module \pipe2 assign $0\xer_so$28$next[0:0]$9484 $1\xer_so$28$next[0:0]$9486 assign { } { } assign $0\xer_so_ok$29$next[0:0]$9485 $2\xer_so_ok$29$next[0:0]$9488 - attribute \src "libresoc.v:169213.5-169213.29" + attribute \src "libresoc.v:169212.5-169212.29" switch \initial - attribute \src "libresoc.v:169213.9-169213.17" + attribute \src "libresoc.v:169212.9-169212.17" case 1'1 case end @@ -348306,7 +345116,7 @@ module \pipe2 update \xer_so$28$next $0\xer_so$28$next[0:0]$9484 update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9485 end - connect \$60 $and$libresoc.v:168938$9349_Y + connect \$60 $and$libresoc.v:168937$9349_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } @@ -348327,235 +345137,235 @@ module \pipe2 connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \output_muxid \muxid end -attribute \src "libresoc.v:169254.1-170323.10" +attribute \src "libresoc.v:169253.1-170322.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" attribute \generator "nMigen" module \pipe2$115 - attribute \src "libresoc.v:170269.3-170287.6" + attribute \src "libresoc.v:170268.3-170286.6" wire width 4 $0\cr_a$21$next[3:0]$9654 - attribute \src "libresoc.v:170075.3-170076.33" + attribute \src "libresoc.v:170074.3-170075.33" wire width 4 $0\cr_a$21[3:0]$9555 - attribute \src "libresoc.v:169266.13-169266.29" + attribute \src "libresoc.v:169265.13-169265.29" wire width 4 $0\cr_a$21[3:0]$9667 - attribute \src "libresoc.v:170269.3-170287.6" + attribute \src "libresoc.v:170268.3-170286.6" wire $0\cr_a_ok$22$next[0:0]$9655 - attribute \src "libresoc.v:170077.3-170078.39" + attribute \src "libresoc.v:170076.3-170077.39" wire $0\cr_a_ok$22[0:0]$9557 - attribute \src "libresoc.v:169275.7-169275.26" + attribute \src "libresoc.v:169274.7-169274.26" wire $0\cr_a_ok$22[0:0]$9669 - attribute \src "libresoc.v:169255.7-169255.20" + attribute \src "libresoc.v:169254.7-169254.20" wire $0\initial[0:0] - attribute \src "libresoc.v:170196.3-170208.6" + attribute \src "libresoc.v:170195.3-170207.6" wire width 2 $0\muxid$1$next[1:0]$9604 - attribute \src "libresoc.v:170117.3-170118.33" + attribute \src "libresoc.v:170116.3-170117.33" wire width 2 $0\muxid$1[1:0]$9597 - attribute \src "libresoc.v:169286.13-169286.29" + attribute \src "libresoc.v:169285.13-169285.29" wire width 2 $0\muxid$1[1:0]$9671 - attribute \src "libresoc.v:170250.3-170268.6" + attribute \src "libresoc.v:170249.3-170267.6" wire width 64 $0\o$19$next[63:0]$9648 - attribute \src "libresoc.v:170079.3-170080.27" + attribute \src "libresoc.v:170078.3-170079.27" wire width 64 $0\o$19[63:0]$9559 - attribute \src "libresoc.v:169301.14-169301.43" + attribute \src "libresoc.v:169300.14-169300.43" wire width 64 $0\o$19[63:0]$9673 - attribute \src "libresoc.v:170250.3-170268.6" + attribute \src "libresoc.v:170249.3-170267.6" wire $0\o_ok$20$next[0:0]$9649 - attribute \src "libresoc.v:170081.3-170082.33" + attribute \src "libresoc.v:170080.3-170081.33" wire $0\o_ok$20[0:0]$9561 - attribute \src "libresoc.v:169310.7-169310.23" + attribute \src "libresoc.v:169309.7-169309.23" wire $0\o_ok$20[0:0]$9675 - attribute \src "libresoc.v:170178.3-170195.6" + attribute \src "libresoc.v:170177.3-170194.6" wire $0\r_busy$next[0:0]$9600 - attribute \src "libresoc.v:170119.3-170120.29" + attribute \src "libresoc.v:170118.3-170119.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire width 14 $0\sr_op__fn_unit$3$next[13:0]$9607 - attribute \src "libresoc.v:170085.3-170086.51" + attribute \src "libresoc.v:170084.3-170085.51" wire width 14 $0\sr_op__fn_unit$3[13:0]$9565 - attribute \src "libresoc.v:169643.14-169643.43" + attribute \src "libresoc.v:169642.14-169642.43" wire width 14 $0\sr_op__fn_unit$3[13:0]$9678 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9608 - attribute \src "libresoc.v:170087.3-170088.65" + attribute \src "libresoc.v:170086.3-170087.65" wire width 64 $0\sr_op__imm_data__data$4[63:0]$9567 - attribute \src "libresoc.v:169667.14-169667.62" + attribute \src "libresoc.v:169666.14-169666.62" wire width 64 $0\sr_op__imm_data__data$4[63:0]$9680 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $0\sr_op__imm_data__ok$5$next[0:0]$9609 - attribute \src "libresoc.v:170089.3-170090.61" + attribute \src "libresoc.v:170088.3-170089.61" wire $0\sr_op__imm_data__ok$5[0:0]$9569 - attribute \src "libresoc.v:169676.7-169676.37" + attribute \src "libresoc.v:169675.7-169675.37" wire $0\sr_op__imm_data__ok$5[0:0]$9682 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire width 2 $0\sr_op__input_carry$12$next[1:0]$9610 - attribute \src "libresoc.v:170103.3-170104.61" + attribute \src "libresoc.v:170102.3-170103.61" wire width 2 $0\sr_op__input_carry$12[1:0]$9583 - attribute \src "libresoc.v:169693.13-169693.43" + attribute \src "libresoc.v:169692.13-169692.43" wire width 2 $0\sr_op__input_carry$12[1:0]$9684 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $0\sr_op__input_cr$14$next[0:0]$9611 - attribute \src "libresoc.v:170107.3-170108.55" + attribute \src "libresoc.v:170106.3-170107.55" wire $0\sr_op__input_cr$14[0:0]$9587 - attribute \src "libresoc.v:169706.7-169706.34" + attribute \src "libresoc.v:169705.7-169705.34" wire $0\sr_op__input_cr$14[0:0]$9686 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire width 32 $0\sr_op__insn$18$next[31:0]$9612 - attribute \src "libresoc.v:170115.3-170116.47" + attribute \src "libresoc.v:170114.3-170115.47" wire width 32 $0\sr_op__insn$18[31:0]$9595 - attribute \src "libresoc.v:169715.14-169715.38" + attribute \src "libresoc.v:169714.14-169714.38" wire width 32 $0\sr_op__insn$18[31:0]$9688 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire width 7 $0\sr_op__insn_type$2$next[6:0]$9613 - attribute \src "libresoc.v:170083.3-170084.55" + attribute \src "libresoc.v:170082.3-170083.55" wire width 7 $0\sr_op__insn_type$2[6:0]$9563 - attribute \src "libresoc.v:169874.13-169874.41" + attribute \src "libresoc.v:169873.13-169873.41" wire width 7 $0\sr_op__insn_type$2[6:0]$9690 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $0\sr_op__invert_in$11$next[0:0]$9614 - attribute \src "libresoc.v:170101.3-170102.57" + attribute \src "libresoc.v:170100.3-170101.57" wire $0\sr_op__invert_in$11[0:0]$9581 - attribute \src "libresoc.v:169958.7-169958.35" + attribute \src "libresoc.v:169957.7-169957.35" wire $0\sr_op__invert_in$11[0:0]$9692 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $0\sr_op__is_32bit$16$next[0:0]$9615 - attribute \src "libresoc.v:170111.3-170112.55" + attribute \src "libresoc.v:170110.3-170111.55" wire $0\sr_op__is_32bit$16[0:0]$9591 - attribute \src "libresoc.v:169967.7-169967.34" + attribute \src "libresoc.v:169966.7-169966.34" wire $0\sr_op__is_32bit$16[0:0]$9694 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $0\sr_op__is_signed$17$next[0:0]$9616 - attribute \src "libresoc.v:170113.3-170114.57" + attribute \src "libresoc.v:170112.3-170113.57" wire $0\sr_op__is_signed$17[0:0]$9593 - attribute \src "libresoc.v:169976.7-169976.35" + attribute \src "libresoc.v:169975.7-169975.35" wire $0\sr_op__is_signed$17[0:0]$9696 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $0\sr_op__oe__oe$8$next[0:0]$9617 - attribute \src "libresoc.v:170095.3-170096.49" + attribute \src "libresoc.v:170094.3-170095.49" wire $0\sr_op__oe__oe$8[0:0]$9575 - attribute \src "libresoc.v:169987.7-169987.31" + attribute \src "libresoc.v:169986.7-169986.31" wire $0\sr_op__oe__oe$8[0:0]$9698 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $0\sr_op__oe__ok$9$next[0:0]$9618 - attribute \src "libresoc.v:170097.3-170098.49" + attribute \src "libresoc.v:170096.3-170097.49" wire $0\sr_op__oe__ok$9[0:0]$9577 - attribute \src "libresoc.v:169996.7-169996.31" + attribute \src "libresoc.v:169995.7-169995.31" wire $0\sr_op__oe__ok$9[0:0]$9700 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $0\sr_op__output_carry$13$next[0:0]$9619 - attribute \src "libresoc.v:170105.3-170106.63" + attribute \src "libresoc.v:170104.3-170105.63" wire $0\sr_op__output_carry$13[0:0]$9585 - attribute \src "libresoc.v:170003.7-170003.38" + attribute \src "libresoc.v:170002.7-170002.38" wire $0\sr_op__output_carry$13[0:0]$9702 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $0\sr_op__output_cr$15$next[0:0]$9620 - attribute \src "libresoc.v:170109.3-170110.57" + attribute \src "libresoc.v:170108.3-170109.57" wire $0\sr_op__output_cr$15[0:0]$9589 - attribute \src "libresoc.v:170012.7-170012.35" + attribute \src "libresoc.v:170011.7-170011.35" wire $0\sr_op__output_cr$15[0:0]$9704 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $0\sr_op__rc__ok$7$next[0:0]$9621 - attribute \src "libresoc.v:170093.3-170094.49" + attribute \src "libresoc.v:170092.3-170093.49" wire $0\sr_op__rc__ok$7[0:0]$9573 - attribute \src "libresoc.v:170023.7-170023.31" + attribute \src "libresoc.v:170022.7-170022.31" wire $0\sr_op__rc__ok$7[0:0]$9706 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $0\sr_op__rc__rc$6$next[0:0]$9622 - attribute \src "libresoc.v:170091.3-170092.49" + attribute \src "libresoc.v:170090.3-170091.49" wire $0\sr_op__rc__rc$6[0:0]$9571 - attribute \src "libresoc.v:170032.7-170032.31" + attribute \src "libresoc.v:170031.7-170031.31" wire $0\sr_op__rc__rc$6[0:0]$9708 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $0\sr_op__write_cr0$10$next[0:0]$9623 - attribute \src "libresoc.v:170099.3-170100.57" + attribute \src "libresoc.v:170098.3-170099.57" wire $0\sr_op__write_cr0$10[0:0]$9579 - attribute \src "libresoc.v:170039.7-170039.35" + attribute \src "libresoc.v:170038.7-170038.35" wire $0\sr_op__write_cr0$10[0:0]$9710 - attribute \src "libresoc.v:170288.3-170306.6" + attribute \src "libresoc.v:170287.3-170305.6" wire width 2 $0\xer_ca$23$next[1:0]$9660 - attribute \src "libresoc.v:170071.3-170072.37" + attribute \src "libresoc.v:170070.3-170071.37" wire width 2 $0\xer_ca$23[1:0]$9551 - attribute \src "libresoc.v:170048.13-170048.31" + attribute \src "libresoc.v:170047.13-170047.31" wire width 2 $0\xer_ca$23[1:0]$9712 - attribute \src "libresoc.v:170288.3-170306.6" + attribute \src "libresoc.v:170287.3-170305.6" wire $0\xer_ca_ok$24$next[0:0]$9661 - attribute \src "libresoc.v:170073.3-170074.43" + attribute \src "libresoc.v:170072.3-170073.43" wire $0\xer_ca_ok$24[0:0]$9553 - attribute \src "libresoc.v:170057.7-170057.28" + attribute \src "libresoc.v:170056.7-170056.28" wire $0\xer_ca_ok$24[0:0]$9714 - attribute \src "libresoc.v:170269.3-170287.6" + attribute \src "libresoc.v:170268.3-170286.6" wire width 4 $1\cr_a$21$next[3:0]$9656 - attribute \src "libresoc.v:170269.3-170287.6" + attribute \src "libresoc.v:170268.3-170286.6" wire $1\cr_a_ok$22$next[0:0]$9657 - attribute \src "libresoc.v:170196.3-170208.6" + attribute \src "libresoc.v:170195.3-170207.6" wire width 2 $1\muxid$1$next[1:0]$9605 - attribute \src "libresoc.v:170250.3-170268.6" + attribute \src "libresoc.v:170249.3-170267.6" wire width 64 $1\o$19$next[63:0]$9650 - attribute \src "libresoc.v:170250.3-170268.6" + attribute \src "libresoc.v:170249.3-170267.6" wire $1\o_ok$20$next[0:0]$9651 - attribute \src "libresoc.v:170178.3-170195.6" + attribute \src "libresoc.v:170177.3-170194.6" wire $1\r_busy$next[0:0]$9601 - attribute \src "libresoc.v:169606.7-169606.20" + attribute \src "libresoc.v:169605.7-169605.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire width 14 $1\sr_op__fn_unit$3$next[13:0]$9624 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9625 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $1\sr_op__imm_data__ok$5$next[0:0]$9626 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire width 2 $1\sr_op__input_carry$12$next[1:0]$9627 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $1\sr_op__input_cr$14$next[0:0]$9628 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire width 32 $1\sr_op__insn$18$next[31:0]$9629 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire width 7 $1\sr_op__insn_type$2$next[6:0]$9630 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $1\sr_op__invert_in$11$next[0:0]$9631 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $1\sr_op__is_32bit$16$next[0:0]$9632 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $1\sr_op__is_signed$17$next[0:0]$9633 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $1\sr_op__oe__oe$8$next[0:0]$9634 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $1\sr_op__oe__ok$9$next[0:0]$9635 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $1\sr_op__output_carry$13$next[0:0]$9636 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $1\sr_op__output_cr$15$next[0:0]$9637 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $1\sr_op__rc__ok$7$next[0:0]$9638 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $1\sr_op__rc__rc$6$next[0:0]$9639 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $1\sr_op__write_cr0$10$next[0:0]$9640 - attribute \src "libresoc.v:170288.3-170306.6" + attribute \src "libresoc.v:170287.3-170305.6" wire width 2 $1\xer_ca$23$next[1:0]$9662 - attribute \src "libresoc.v:170288.3-170306.6" + attribute \src "libresoc.v:170287.3-170305.6" wire $1\xer_ca_ok$24$next[0:0]$9663 - attribute \src "libresoc.v:170269.3-170287.6" + attribute \src "libresoc.v:170268.3-170286.6" wire $2\cr_a_ok$22$next[0:0]$9658 - attribute \src "libresoc.v:170250.3-170268.6" + attribute \src "libresoc.v:170249.3-170267.6" wire $2\o_ok$20$next[0:0]$9652 - attribute \src "libresoc.v:170178.3-170195.6" + attribute \src "libresoc.v:170177.3-170194.6" wire $2\r_busy$next[0:0]$9602 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9641 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $2\sr_op__imm_data__ok$5$next[0:0]$9642 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $2\sr_op__oe__oe$8$next[0:0]$9643 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $2\sr_op__oe__ok$9$next[0:0]$9644 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $2\sr_op__rc__ok$7$next[0:0]$9645 - attribute \src "libresoc.v:170209.3-170249.6" + attribute \src "libresoc.v:170208.3-170248.6" wire $2\sr_op__rc__rc$6$next[0:0]$9646 - attribute \src "libresoc.v:170288.3-170306.6" + attribute \src "libresoc.v:170287.3-170305.6" wire $2\xer_ca_ok$24$next[0:0]$9664 - attribute \src "libresoc.v:170070.18-170070.118" - wire $and$libresoc.v:170070$9549_Y + attribute \src "libresoc.v:170069.18-170069.118" + wire $and$libresoc.v:170069$9549_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" @@ -348580,7 +345390,7 @@ module \pipe2$115 wire \cr_a_ok$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$74 - attribute \src "libresoc.v:169255.7-169255.15" + attribute \src "libresoc.v:169254.7-169254.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -349349,7 +346159,7 @@ module \pipe2$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:170070$9549 + cell $and $and$libresoc.v:170069$9549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -349357,16 +346167,16 @@ module \pipe2$115 parameter \Y_WIDTH 1 connect \A \p_valid_i$50 connect \B \p_ready_o - connect \Y $and$libresoc.v:170070$9549_Y + connect \Y $and$libresoc.v:170069$9549_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:170121.11-170124.4" + attribute \src "libresoc.v:170120.11-170123.4" cell \n$117 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:170125.16-170173.4" + attribute \src "libresoc.v:170124.16-170172.4" cell \output$118 \output connect \cr_a \output_cr_a connect \cr_a$21 \output_cr_a$45 @@ -349417,403 +346227,403 @@ module \pipe2$115 connect \xer_so \output_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:170174.11-170177.4" + attribute \src "libresoc.v:170173.11-170176.4" cell \p$116 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:169255.7-169255.20" - process $proc$libresoc.v:169255$9665 + attribute \src "libresoc.v:169254.7-169254.20" + process $proc$libresoc.v:169254$9665 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169266.13-169266.29" - process $proc$libresoc.v:169266$9666 + attribute \src "libresoc.v:169265.13-169265.29" + process $proc$libresoc.v:169265$9666 assign { } { } assign $0\cr_a$21[3:0]$9667 4'0000 sync always sync init update \cr_a$21 $0\cr_a$21[3:0]$9667 end - attribute \src "libresoc.v:169275.7-169275.26" - process $proc$libresoc.v:169275$9668 + attribute \src "libresoc.v:169274.7-169274.26" + process $proc$libresoc.v:169274$9668 assign { } { } assign $0\cr_a_ok$22[0:0]$9669 1'0 sync always sync init update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9669 end - attribute \src "libresoc.v:169286.13-169286.29" - process $proc$libresoc.v:169286$9670 + attribute \src "libresoc.v:169285.13-169285.29" + process $proc$libresoc.v:169285$9670 assign { } { } assign $0\muxid$1[1:0]$9671 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$9671 end - attribute \src "libresoc.v:169301.14-169301.43" - process $proc$libresoc.v:169301$9672 + attribute \src "libresoc.v:169300.14-169300.43" + process $proc$libresoc.v:169300$9672 assign { } { } assign $0\o$19[63:0]$9673 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o$19 $0\o$19[63:0]$9673 end - attribute \src "libresoc.v:169310.7-169310.23" - process $proc$libresoc.v:169310$9674 + attribute \src "libresoc.v:169309.7-169309.23" + process $proc$libresoc.v:169309$9674 assign { } { } assign $0\o_ok$20[0:0]$9675 1'0 sync always sync init update \o_ok$20 $0\o_ok$20[0:0]$9675 end - attribute \src "libresoc.v:169606.7-169606.20" - process $proc$libresoc.v:169606$9676 + attribute \src "libresoc.v:169605.7-169605.20" + process $proc$libresoc.v:169605$9676 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:169643.14-169643.43" - process $proc$libresoc.v:169643$9677 + attribute \src "libresoc.v:169642.14-169642.43" + process $proc$libresoc.v:169642$9677 assign { } { } assign $0\sr_op__fn_unit$3[13:0]$9678 14'00000000000000 sync always sync init update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9678 end - attribute \src "libresoc.v:169667.14-169667.62" - process $proc$libresoc.v:169667$9679 + attribute \src "libresoc.v:169666.14-169666.62" + process $proc$libresoc.v:169666$9679 assign { } { } assign $0\sr_op__imm_data__data$4[63:0]$9680 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9680 end - attribute \src "libresoc.v:169676.7-169676.37" - process $proc$libresoc.v:169676$9681 + attribute \src "libresoc.v:169675.7-169675.37" + process $proc$libresoc.v:169675$9681 assign { } { } assign $0\sr_op__imm_data__ok$5[0:0]$9682 1'0 sync always sync init update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9682 end - attribute \src "libresoc.v:169693.13-169693.43" - process $proc$libresoc.v:169693$9683 + attribute \src "libresoc.v:169692.13-169692.43" + process $proc$libresoc.v:169692$9683 assign { } { } assign $0\sr_op__input_carry$12[1:0]$9684 2'00 sync always sync init update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9684 end - attribute \src "libresoc.v:169706.7-169706.34" - process $proc$libresoc.v:169706$9685 + attribute \src "libresoc.v:169705.7-169705.34" + process $proc$libresoc.v:169705$9685 assign { } { } assign $0\sr_op__input_cr$14[0:0]$9686 1'0 sync always sync init update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9686 end - attribute \src "libresoc.v:169715.14-169715.38" - process $proc$libresoc.v:169715$9687 + attribute \src "libresoc.v:169714.14-169714.38" + process $proc$libresoc.v:169714$9687 assign { } { } assign $0\sr_op__insn$18[31:0]$9688 0 sync always sync init update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9688 end - attribute \src "libresoc.v:169874.13-169874.41" - process $proc$libresoc.v:169874$9689 + attribute \src "libresoc.v:169873.13-169873.41" + process $proc$libresoc.v:169873$9689 assign { } { } assign $0\sr_op__insn_type$2[6:0]$9690 7'0000000 sync always sync init update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9690 end - attribute \src "libresoc.v:169958.7-169958.35" - process $proc$libresoc.v:169958$9691 + attribute \src "libresoc.v:169957.7-169957.35" + process $proc$libresoc.v:169957$9691 assign { } { } assign $0\sr_op__invert_in$11[0:0]$9692 1'0 sync always sync init update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9692 end - attribute \src "libresoc.v:169967.7-169967.34" - process $proc$libresoc.v:169967$9693 + attribute \src "libresoc.v:169966.7-169966.34" + process $proc$libresoc.v:169966$9693 assign { } { } assign $0\sr_op__is_32bit$16[0:0]$9694 1'0 sync always sync init update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9694 end - attribute \src "libresoc.v:169976.7-169976.35" - process $proc$libresoc.v:169976$9695 + attribute \src "libresoc.v:169975.7-169975.35" + process $proc$libresoc.v:169975$9695 assign { } { } assign $0\sr_op__is_signed$17[0:0]$9696 1'0 sync always sync init update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9696 end - attribute \src "libresoc.v:169987.7-169987.31" - process $proc$libresoc.v:169987$9697 + attribute \src "libresoc.v:169986.7-169986.31" + process $proc$libresoc.v:169986$9697 assign { } { } assign $0\sr_op__oe__oe$8[0:0]$9698 1'0 sync always sync init update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9698 end - attribute \src "libresoc.v:169996.7-169996.31" - process $proc$libresoc.v:169996$9699 + attribute \src "libresoc.v:169995.7-169995.31" + process $proc$libresoc.v:169995$9699 assign { } { } assign $0\sr_op__oe__ok$9[0:0]$9700 1'0 sync always sync init update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9700 end - attribute \src "libresoc.v:170003.7-170003.38" - process $proc$libresoc.v:170003$9701 + attribute \src "libresoc.v:170002.7-170002.38" + process $proc$libresoc.v:170002$9701 assign { } { } assign $0\sr_op__output_carry$13[0:0]$9702 1'0 sync always sync init update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9702 end - attribute \src "libresoc.v:170012.7-170012.35" - process $proc$libresoc.v:170012$9703 + attribute \src "libresoc.v:170011.7-170011.35" + process $proc$libresoc.v:170011$9703 assign { } { } assign $0\sr_op__output_cr$15[0:0]$9704 1'0 sync always sync init update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9704 end - attribute \src "libresoc.v:170023.7-170023.31" - process $proc$libresoc.v:170023$9705 + attribute \src "libresoc.v:170022.7-170022.31" + process $proc$libresoc.v:170022$9705 assign { } { } assign $0\sr_op__rc__ok$7[0:0]$9706 1'0 sync always sync init update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9706 end - attribute \src "libresoc.v:170032.7-170032.31" - process $proc$libresoc.v:170032$9707 + attribute \src "libresoc.v:170031.7-170031.31" + process $proc$libresoc.v:170031$9707 assign { } { } assign $0\sr_op__rc__rc$6[0:0]$9708 1'0 sync always sync init update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9708 end - attribute \src "libresoc.v:170039.7-170039.35" - process $proc$libresoc.v:170039$9709 + attribute \src "libresoc.v:170038.7-170038.35" + process $proc$libresoc.v:170038$9709 assign { } { } assign $0\sr_op__write_cr0$10[0:0]$9710 1'0 sync always sync init update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9710 end - attribute \src "libresoc.v:170048.13-170048.31" - process $proc$libresoc.v:170048$9711 + attribute \src "libresoc.v:170047.13-170047.31" + process $proc$libresoc.v:170047$9711 assign { } { } assign $0\xer_ca$23[1:0]$9712 2'00 sync always sync init update \xer_ca$23 $0\xer_ca$23[1:0]$9712 end - attribute \src "libresoc.v:170057.7-170057.28" - process $proc$libresoc.v:170057$9713 + attribute \src "libresoc.v:170056.7-170056.28" + process $proc$libresoc.v:170056$9713 assign { } { } assign $0\xer_ca_ok$24[0:0]$9714 1'0 sync always sync init update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9714 end - attribute \src "libresoc.v:170071.3-170072.37" - process $proc$libresoc.v:170071$9550 + attribute \src "libresoc.v:170070.3-170071.37" + process $proc$libresoc.v:170070$9550 assign { } { } assign $0\xer_ca$23[1:0]$9551 \xer_ca$23$next sync posedge \coresync_clk update \xer_ca$23 $0\xer_ca$23[1:0]$9551 end - attribute \src "libresoc.v:170073.3-170074.43" - process $proc$libresoc.v:170073$9552 + attribute \src "libresoc.v:170072.3-170073.43" + process $proc$libresoc.v:170072$9552 assign { } { } assign $0\xer_ca_ok$24[0:0]$9553 \xer_ca_ok$24$next sync posedge \coresync_clk update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9553 end - attribute \src "libresoc.v:170075.3-170076.33" - process $proc$libresoc.v:170075$9554 + attribute \src "libresoc.v:170074.3-170075.33" + process $proc$libresoc.v:170074$9554 assign { } { } assign $0\cr_a$21[3:0]$9555 \cr_a$21$next sync posedge \coresync_clk update \cr_a$21 $0\cr_a$21[3:0]$9555 end - attribute \src "libresoc.v:170077.3-170078.39" - process $proc$libresoc.v:170077$9556 + attribute \src "libresoc.v:170076.3-170077.39" + process $proc$libresoc.v:170076$9556 assign { } { } assign $0\cr_a_ok$22[0:0]$9557 \cr_a_ok$22$next sync posedge \coresync_clk update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9557 end - attribute \src "libresoc.v:170079.3-170080.27" - process $proc$libresoc.v:170079$9558 + attribute \src "libresoc.v:170078.3-170079.27" + process $proc$libresoc.v:170078$9558 assign { } { } assign $0\o$19[63:0]$9559 \o$19$next sync posedge \coresync_clk update \o$19 $0\o$19[63:0]$9559 end - attribute \src "libresoc.v:170081.3-170082.33" - process $proc$libresoc.v:170081$9560 + attribute \src "libresoc.v:170080.3-170081.33" + process $proc$libresoc.v:170080$9560 assign { } { } assign $0\o_ok$20[0:0]$9561 \o_ok$20$next sync posedge \coresync_clk update \o_ok$20 $0\o_ok$20[0:0]$9561 end - attribute \src "libresoc.v:170083.3-170084.55" - process $proc$libresoc.v:170083$9562 + attribute \src "libresoc.v:170082.3-170083.55" + process $proc$libresoc.v:170082$9562 assign { } { } assign $0\sr_op__insn_type$2[6:0]$9563 \sr_op__insn_type$2$next sync posedge \coresync_clk update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9563 end - attribute \src "libresoc.v:170085.3-170086.51" - process $proc$libresoc.v:170085$9564 + attribute \src "libresoc.v:170084.3-170085.51" + process $proc$libresoc.v:170084$9564 assign { } { } assign $0\sr_op__fn_unit$3[13:0]$9565 \sr_op__fn_unit$3$next sync posedge \coresync_clk update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9565 end - attribute \src "libresoc.v:170087.3-170088.65" - process $proc$libresoc.v:170087$9566 + attribute \src "libresoc.v:170086.3-170087.65" + process $proc$libresoc.v:170086$9566 assign { } { } assign $0\sr_op__imm_data__data$4[63:0]$9567 \sr_op__imm_data__data$4$next sync posedge \coresync_clk update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9567 end - attribute \src "libresoc.v:170089.3-170090.61" - process $proc$libresoc.v:170089$9568 + attribute \src "libresoc.v:170088.3-170089.61" + process $proc$libresoc.v:170088$9568 assign { } { } assign $0\sr_op__imm_data__ok$5[0:0]$9569 \sr_op__imm_data__ok$5$next sync posedge \coresync_clk update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9569 end - attribute \src "libresoc.v:170091.3-170092.49" - process $proc$libresoc.v:170091$9570 + attribute \src "libresoc.v:170090.3-170091.49" + process $proc$libresoc.v:170090$9570 assign { } { } assign $0\sr_op__rc__rc$6[0:0]$9571 \sr_op__rc__rc$6$next sync posedge \coresync_clk update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9571 end - attribute \src "libresoc.v:170093.3-170094.49" - process $proc$libresoc.v:170093$9572 + attribute \src "libresoc.v:170092.3-170093.49" + process $proc$libresoc.v:170092$9572 assign { } { } assign $0\sr_op__rc__ok$7[0:0]$9573 \sr_op__rc__ok$7$next sync posedge \coresync_clk update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9573 end - attribute \src "libresoc.v:170095.3-170096.49" - process $proc$libresoc.v:170095$9574 + attribute \src "libresoc.v:170094.3-170095.49" + process $proc$libresoc.v:170094$9574 assign { } { } assign $0\sr_op__oe__oe$8[0:0]$9575 \sr_op__oe__oe$8$next sync posedge \coresync_clk update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9575 end - attribute \src "libresoc.v:170097.3-170098.49" - process $proc$libresoc.v:170097$9576 + attribute \src "libresoc.v:170096.3-170097.49" + process $proc$libresoc.v:170096$9576 assign { } { } assign $0\sr_op__oe__ok$9[0:0]$9577 \sr_op__oe__ok$9$next sync posedge \coresync_clk update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9577 end - attribute \src "libresoc.v:170099.3-170100.57" - process $proc$libresoc.v:170099$9578 + attribute \src "libresoc.v:170098.3-170099.57" + process $proc$libresoc.v:170098$9578 assign { } { } assign $0\sr_op__write_cr0$10[0:0]$9579 \sr_op__write_cr0$10$next sync posedge \coresync_clk update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9579 end - attribute \src "libresoc.v:170101.3-170102.57" - process $proc$libresoc.v:170101$9580 + attribute \src "libresoc.v:170100.3-170101.57" + process $proc$libresoc.v:170100$9580 assign { } { } assign $0\sr_op__invert_in$11[0:0]$9581 \sr_op__invert_in$11$next sync posedge \coresync_clk update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9581 end - attribute \src "libresoc.v:170103.3-170104.61" - process $proc$libresoc.v:170103$9582 + attribute \src "libresoc.v:170102.3-170103.61" + process $proc$libresoc.v:170102$9582 assign { } { } assign $0\sr_op__input_carry$12[1:0]$9583 \sr_op__input_carry$12$next sync posedge \coresync_clk update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9583 end - attribute \src "libresoc.v:170105.3-170106.63" - process $proc$libresoc.v:170105$9584 + attribute \src "libresoc.v:170104.3-170105.63" + process $proc$libresoc.v:170104$9584 assign { } { } assign $0\sr_op__output_carry$13[0:0]$9585 \sr_op__output_carry$13$next sync posedge \coresync_clk update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9585 end - attribute \src "libresoc.v:170107.3-170108.55" - process $proc$libresoc.v:170107$9586 + attribute \src "libresoc.v:170106.3-170107.55" + process $proc$libresoc.v:170106$9586 assign { } { } assign $0\sr_op__input_cr$14[0:0]$9587 \sr_op__input_cr$14$next sync posedge \coresync_clk update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9587 end - attribute \src "libresoc.v:170109.3-170110.57" - process $proc$libresoc.v:170109$9588 + attribute \src "libresoc.v:170108.3-170109.57" + process $proc$libresoc.v:170108$9588 assign { } { } assign $0\sr_op__output_cr$15[0:0]$9589 \sr_op__output_cr$15$next sync posedge \coresync_clk update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9589 end - attribute \src "libresoc.v:170111.3-170112.55" - process $proc$libresoc.v:170111$9590 + attribute \src "libresoc.v:170110.3-170111.55" + process $proc$libresoc.v:170110$9590 assign { } { } assign $0\sr_op__is_32bit$16[0:0]$9591 \sr_op__is_32bit$16$next sync posedge \coresync_clk update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9591 end - attribute \src "libresoc.v:170113.3-170114.57" - process $proc$libresoc.v:170113$9592 + attribute \src "libresoc.v:170112.3-170113.57" + process $proc$libresoc.v:170112$9592 assign { } { } assign $0\sr_op__is_signed$17[0:0]$9593 \sr_op__is_signed$17$next sync posedge \coresync_clk update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9593 end - attribute \src "libresoc.v:170115.3-170116.47" - process $proc$libresoc.v:170115$9594 + attribute \src "libresoc.v:170114.3-170115.47" + process $proc$libresoc.v:170114$9594 assign { } { } assign $0\sr_op__insn$18[31:0]$9595 \sr_op__insn$18$next sync posedge \coresync_clk update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9595 end - attribute \src "libresoc.v:170117.3-170118.33" - process $proc$libresoc.v:170117$9596 + attribute \src "libresoc.v:170116.3-170117.33" + process $proc$libresoc.v:170116$9596 assign { } { } assign $0\muxid$1[1:0]$9597 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$9597 end - attribute \src "libresoc.v:170119.3-170120.29" - process $proc$libresoc.v:170119$9598 + attribute \src "libresoc.v:170118.3-170119.29" + process $proc$libresoc.v:170118$9598 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:170178.3-170195.6" - process $proc$libresoc.v:170178$9599 + attribute \src "libresoc.v:170177.3-170194.6" + process $proc$libresoc.v:170177$9599 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9600 $2\r_busy$next[0:0]$9602 - attribute \src "libresoc.v:170179.5-170179.29" + attribute \src "libresoc.v:170178.5-170178.29" switch \initial - attribute \src "libresoc.v:170179.9-170179.17" + attribute \src "libresoc.v:170178.9-170178.17" case 1'1 case end @@ -349842,14 +346652,14 @@ module \pipe2$115 sync always update \r_busy$next $0\r_busy$next[0:0]$9600 end - attribute \src "libresoc.v:170196.3-170208.6" - process $proc$libresoc.v:170196$9603 + attribute \src "libresoc.v:170195.3-170207.6" + process $proc$libresoc.v:170195$9603 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$9604 $1\muxid$1$next[1:0]$9605 - attribute \src "libresoc.v:170197.5-170197.29" + attribute \src "libresoc.v:170196.5-170196.29" switch \initial - attribute \src "libresoc.v:170197.9-170197.17" + attribute \src "libresoc.v:170196.9-170196.17" case 1'1 case end @@ -349869,8 +346679,8 @@ module \pipe2$115 sync always update \muxid$1$next $0\muxid$1$next[1:0]$9604 end - attribute \src "libresoc.v:170209.3-170249.6" - process $proc$libresoc.v:170209$9606 + attribute \src "libresoc.v:170208.3-170248.6" + process $proc$libresoc.v:170208$9606 assign { } { } assign { } { } assign { } { } @@ -349928,9 +346738,9 @@ module \pipe2$115 assign $0\sr_op__oe__ok$9$next[0:0]$9618 $2\sr_op__oe__ok$9$next[0:0]$9644 assign $0\sr_op__rc__ok$7$next[0:0]$9621 $2\sr_op__rc__ok$7$next[0:0]$9645 assign $0\sr_op__rc__rc$6$next[0:0]$9622 $2\sr_op__rc__rc$6$next[0:0]$9646 - attribute \src "libresoc.v:170210.5-170210.29" + attribute \src "libresoc.v:170209.5-170209.29" switch \initial - attribute \src "libresoc.v:170210.9-170210.17" + attribute \src "libresoc.v:170209.9-170209.17" case 1'1 case end @@ -350038,8 +346848,8 @@ module \pipe2$115 update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9622 update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9623 end - attribute \src "libresoc.v:170250.3-170268.6" - process $proc$libresoc.v:170250$9647 + attribute \src "libresoc.v:170249.3-170267.6" + process $proc$libresoc.v:170249$9647 assign { } { } assign { } { } assign { } { } @@ -350047,9 +346857,9 @@ module \pipe2$115 assign $0\o$19$next[63:0]$9648 $1\o$19$next[63:0]$9650 assign { } { } assign $0\o_ok$20$next[0:0]$9649 $2\o_ok$20$next[0:0]$9652 - attribute \src "libresoc.v:170251.5-170251.29" + attribute \src "libresoc.v:170250.5-170250.29" switch \initial - attribute \src "libresoc.v:170251.9-170251.17" + attribute \src "libresoc.v:170250.9-170250.17" case 1'1 case end @@ -350082,8 +346892,8 @@ module \pipe2$115 update \o$19$next $0\o$19$next[63:0]$9648 update \o_ok$20$next $0\o_ok$20$next[0:0]$9649 end - attribute \src "libresoc.v:170269.3-170287.6" - process $proc$libresoc.v:170269$9653 + attribute \src "libresoc.v:170268.3-170286.6" + process $proc$libresoc.v:170268$9653 assign { } { } assign { } { } assign { } { } @@ -350091,9 +346901,9 @@ module \pipe2$115 assign $0\cr_a$21$next[3:0]$9654 $1\cr_a$21$next[3:0]$9656 assign { } { } assign $0\cr_a_ok$22$next[0:0]$9655 $2\cr_a_ok$22$next[0:0]$9658 - attribute \src "libresoc.v:170270.5-170270.29" + attribute \src "libresoc.v:170269.5-170269.29" switch \initial - attribute \src "libresoc.v:170270.9-170270.17" + attribute \src "libresoc.v:170269.9-170269.17" case 1'1 case end @@ -350126,8 +346936,8 @@ module \pipe2$115 update \cr_a$21$next $0\cr_a$21$next[3:0]$9654 update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9655 end - attribute \src "libresoc.v:170288.3-170306.6" - process $proc$libresoc.v:170288$9659 + attribute \src "libresoc.v:170287.3-170305.6" + process $proc$libresoc.v:170287$9659 assign { } { } assign { } { } assign { } { } @@ -350135,9 +346945,9 @@ module \pipe2$115 assign $0\xer_ca$23$next[1:0]$9660 $1\xer_ca$23$next[1:0]$9662 assign { } { } assign $0\xer_ca_ok$24$next[0:0]$9661 $2\xer_ca_ok$24$next[0:0]$9664 - attribute \src "libresoc.v:170289.5-170289.29" + attribute \src "libresoc.v:170288.5-170288.29" switch \initial - attribute \src "libresoc.v:170289.9-170289.17" + attribute \src "libresoc.v:170288.9-170288.17" case 1'1 case end @@ -350170,7 +346980,7 @@ module \pipe2$115 update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9660 update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9661 end - connect \$51 $and$libresoc.v:170070$9549_Y + connect \$51 $and$libresoc.v:170069$9549_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 } @@ -350188,195 +346998,195 @@ module \pipe2$115 connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \output_muxid \muxid end -attribute \src "libresoc.v:170327.1-171291.10" +attribute \src "libresoc.v:170326.1-171290.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" attribute \generator "nMigen" module \pipe2$35 - attribute \src "libresoc.v:171197.3-171215.6" + attribute \src "libresoc.v:171196.3-171214.6" wire width 64 $0\fast1$11$next[63:0]$9783 - attribute \src "libresoc.v:171052.3-171053.35" + attribute \src "libresoc.v:171051.3-171052.35" wire width 64 $0\fast1$11[63:0]$9724 - attribute \src "libresoc.v:170339.14-170339.47" + attribute \src "libresoc.v:170338.14-170338.47" wire width 64 $0\fast1$11[63:0]$9807 - attribute \src "libresoc.v:171197.3-171215.6" + attribute \src "libresoc.v:171196.3-171214.6" wire $0\fast1_ok$next[0:0]$9782 - attribute \src "libresoc.v:171054.3-171055.33" + attribute \src "libresoc.v:171053.3-171054.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:171216.3-171234.6" + attribute \src "libresoc.v:171215.3-171233.6" wire width 64 $0\fast2$12$next[63:0]$9789 - attribute \src "libresoc.v:171048.3-171049.35" + attribute \src "libresoc.v:171047.3-171048.35" wire width 64 $0\fast2$12[63:0]$9721 - attribute \src "libresoc.v:170355.14-170355.47" + attribute \src "libresoc.v:170354.14-170354.47" wire width 64 $0\fast2$12[63:0]$9810 - attribute \src "libresoc.v:171216.3-171234.6" + attribute \src "libresoc.v:171215.3-171233.6" wire $0\fast2_ok$next[0:0]$9788 - attribute \src "libresoc.v:171050.3-171051.33" + attribute \src "libresoc.v:171049.3-171050.33" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:170328.7-170328.20" + attribute \src "libresoc.v:170327.7-170327.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171254.3-171272.6" + attribute \src "libresoc.v:171253.3-171271.6" wire width 64 $0\msr$next[63:0]$9800 - attribute \src "libresoc.v:171040.3-171041.23" + attribute \src "libresoc.v:171039.3-171040.23" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:171254.3-171272.6" + attribute \src "libresoc.v:171253.3-171271.6" wire $0\msr_ok$next[0:0]$9801 - attribute \src "libresoc.v:171042.3-171043.29" + attribute \src "libresoc.v:171041.3-171042.29" wire $0\msr_ok[0:0] - attribute \src "libresoc.v:171144.3-171156.6" + attribute \src "libresoc.v:171143.3-171155.6" wire width 2 $0\muxid$1$next[1:0]$9754 - attribute \src "libresoc.v:171078.3-171079.33" + attribute \src "libresoc.v:171077.3-171078.33" wire width 2 $0\muxid$1[1:0]$9747 - attribute \src "libresoc.v:170633.13-170633.29" + attribute \src "libresoc.v:170632.13-170632.29" wire width 2 $0\muxid$1[1:0]$9815 - attribute \src "libresoc.v:171235.3-171253.6" + attribute \src "libresoc.v:171234.3-171252.6" wire width 64 $0\nia$next[63:0]$9794 - attribute \src "libresoc.v:171044.3-171045.23" + attribute \src "libresoc.v:171043.3-171044.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:171235.3-171253.6" + attribute \src "libresoc.v:171234.3-171252.6" wire $0\nia_ok$next[0:0]$9795 - attribute \src "libresoc.v:171046.3-171047.29" + attribute \src "libresoc.v:171045.3-171046.29" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:171178.3-171196.6" + attribute \src "libresoc.v:171177.3-171195.6" wire width 64 $0\o$next[63:0]$9776 - attribute \src "libresoc.v:171056.3-171057.19" + attribute \src "libresoc.v:171055.3-171056.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:171178.3-171196.6" + attribute \src "libresoc.v:171177.3-171195.6" wire $0\o_ok$next[0:0]$9777 - attribute \src "libresoc.v:171058.3-171059.25" + attribute \src "libresoc.v:171057.3-171058.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:171126.3-171143.6" + attribute \src "libresoc.v:171125.3-171142.6" wire $0\r_busy$next[0:0]$9750 - attribute \src "libresoc.v:171080.3-171081.29" + attribute \src "libresoc.v:171079.3-171080.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire width 64 $0\trap_op__cia$6$next[63:0]$9757 - attribute \src "libresoc.v:171068.3-171069.47" + attribute \src "libresoc.v:171067.3-171068.47" wire width 64 $0\trap_op__cia$6[63:0]$9737 - attribute \src "libresoc.v:170694.14-170694.53" + attribute \src "libresoc.v:170693.14-170693.53" wire width 64 $0\trap_op__cia$6[63:0]$9822 - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire width 14 $0\trap_op__fn_unit$3$next[13:0]$9758 - attribute \src "libresoc.v:171062.3-171063.55" + attribute \src "libresoc.v:171061.3-171062.55" wire width 14 $0\trap_op__fn_unit$3[13:0]$9731 - attribute \src "libresoc.v:170731.14-170731.45" + attribute \src "libresoc.v:170730.14-170730.45" wire width 14 $0\trap_op__fn_unit$3[13:0]$9824 - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire width 32 $0\trap_op__insn$4$next[31:0]$9759 - attribute \src "libresoc.v:171064.3-171065.49" + attribute \src "libresoc.v:171063.3-171064.49" wire width 32 $0\trap_op__insn$4[31:0]$9733 - attribute \src "libresoc.v:170757.14-170757.39" + attribute \src "libresoc.v:170756.14-170756.39" wire width 32 $0\trap_op__insn$4[31:0]$9826 - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire width 7 $0\trap_op__insn_type$2$next[6:0]$9760 - attribute \src "libresoc.v:171060.3-171061.59" + attribute \src "libresoc.v:171059.3-171060.59" wire width 7 $0\trap_op__insn_type$2[6:0]$9729 - attribute \src "libresoc.v:170914.13-170914.43" + attribute \src "libresoc.v:170913.13-170913.43" wire width 7 $0\trap_op__insn_type$2[6:0]$9828 - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire $0\trap_op__is_32bit$7$next[0:0]$9761 - attribute \src "libresoc.v:171070.3-171071.57" + attribute \src "libresoc.v:171069.3-171070.57" wire $0\trap_op__is_32bit$7[0:0]$9739 - attribute \src "libresoc.v:171000.7-171000.35" + attribute \src "libresoc.v:170999.7-170999.35" wire $0\trap_op__is_32bit$7[0:0]$9830 - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9762 - attribute \src "libresoc.v:171076.3-171077.59" + attribute \src "libresoc.v:171075.3-171076.59" wire width 8 $0\trap_op__ldst_exc$10[7:0]$9745 - attribute \src "libresoc.v:171007.13-171007.43" + attribute \src "libresoc.v:171006.13-171006.43" wire width 8 $0\trap_op__ldst_exc$10[7:0]$9832 - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire width 64 $0\trap_op__msr$5$next[63:0]$9763 - attribute \src "libresoc.v:171066.3-171067.47" + attribute \src "libresoc.v:171065.3-171066.47" wire width 64 $0\trap_op__msr$5[63:0]$9735 - attribute \src "libresoc.v:171018.14-171018.53" + attribute \src "libresoc.v:171017.14-171017.53" wire width 64 $0\trap_op__msr$5[63:0]$9834 - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9764 - attribute \src "libresoc.v:171074.3-171075.57" + attribute \src "libresoc.v:171073.3-171074.57" wire width 13 $0\trap_op__trapaddr$9[12:0]$9743 - attribute \src "libresoc.v:171027.14-171027.46" + attribute \src "libresoc.v:171026.14-171026.46" wire width 13 $0\trap_op__trapaddr$9[12:0]$9836 - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire width 8 $0\trap_op__traptype$8$next[7:0]$9765 - attribute \src "libresoc.v:171072.3-171073.57" + attribute \src "libresoc.v:171071.3-171072.57" wire width 8 $0\trap_op__traptype$8[7:0]$9741 - attribute \src "libresoc.v:171036.13-171036.42" + attribute \src "libresoc.v:171035.13-171035.42" wire width 8 $0\trap_op__traptype$8[7:0]$9838 - attribute \src "libresoc.v:171197.3-171215.6" + attribute \src "libresoc.v:171196.3-171214.6" wire width 64 $1\fast1$11$next[63:0]$9785 - attribute \src "libresoc.v:171197.3-171215.6" + attribute \src "libresoc.v:171196.3-171214.6" wire $1\fast1_ok$next[0:0]$9784 - attribute \src "libresoc.v:170346.7-170346.22" + attribute \src "libresoc.v:170345.7-170345.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:171216.3-171234.6" + attribute \src "libresoc.v:171215.3-171233.6" wire width 64 $1\fast2$12$next[63:0]$9791 - attribute \src "libresoc.v:171216.3-171234.6" + attribute \src "libresoc.v:171215.3-171233.6" wire $1\fast2_ok$next[0:0]$9790 - attribute \src "libresoc.v:170362.7-170362.22" + attribute \src "libresoc.v:170361.7-170361.22" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:171254.3-171272.6" + attribute \src "libresoc.v:171253.3-171271.6" wire width 64 $1\msr$next[63:0]$9802 - attribute \src "libresoc.v:170617.14-170617.40" + attribute \src "libresoc.v:170616.14-170616.40" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:171254.3-171272.6" + attribute \src "libresoc.v:171253.3-171271.6" wire $1\msr_ok$next[0:0]$9803 - attribute \src "libresoc.v:170624.7-170624.20" + attribute \src "libresoc.v:170623.7-170623.20" wire $1\msr_ok[0:0] - attribute \src "libresoc.v:171144.3-171156.6" + attribute \src "libresoc.v:171143.3-171155.6" wire width 2 $1\muxid$1$next[1:0]$9755 - attribute \src "libresoc.v:171235.3-171253.6" + attribute \src "libresoc.v:171234.3-171252.6" wire width 64 $1\nia$next[63:0]$9796 - attribute \src "libresoc.v:170646.14-170646.40" + attribute \src "libresoc.v:170645.14-170645.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:171235.3-171253.6" + attribute \src "libresoc.v:171234.3-171252.6" wire $1\nia_ok$next[0:0]$9797 - attribute \src "libresoc.v:170653.7-170653.20" + attribute \src "libresoc.v:170652.7-170652.20" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:171178.3-171196.6" + attribute \src "libresoc.v:171177.3-171195.6" wire width 64 $1\o$next[63:0]$9778 - attribute \src "libresoc.v:170660.14-170660.38" + attribute \src "libresoc.v:170659.14-170659.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:171178.3-171196.6" + attribute \src "libresoc.v:171177.3-171195.6" wire $1\o_ok$next[0:0]$9779 - attribute \src "libresoc.v:170667.7-170667.18" + attribute \src "libresoc.v:170666.7-170666.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:171126.3-171143.6" + attribute \src "libresoc.v:171125.3-171142.6" wire $1\r_busy$next[0:0]$9751 - attribute \src "libresoc.v:170681.7-170681.20" + attribute \src "libresoc.v:170680.7-170680.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire width 64 $1\trap_op__cia$6$next[63:0]$9766 - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire width 14 $1\trap_op__fn_unit$3$next[13:0]$9767 - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire width 32 $1\trap_op__insn$4$next[31:0]$9768 - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire width 7 $1\trap_op__insn_type$2$next[6:0]$9769 - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire $1\trap_op__is_32bit$7$next[0:0]$9770 - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9771 - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire width 64 $1\trap_op__msr$5$next[63:0]$9772 - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9773 - attribute \src "libresoc.v:171157.3-171177.6" + attribute \src "libresoc.v:171156.3-171176.6" wire width 8 $1\trap_op__traptype$8$next[7:0]$9774 - attribute \src "libresoc.v:171197.3-171215.6" + attribute \src "libresoc.v:171196.3-171214.6" wire $2\fast1_ok$next[0:0]$9786 - attribute \src "libresoc.v:171216.3-171234.6" + attribute \src "libresoc.v:171215.3-171233.6" wire $2\fast2_ok$next[0:0]$9792 - attribute \src "libresoc.v:171254.3-171272.6" + attribute \src "libresoc.v:171253.3-171271.6" wire $2\msr_ok$next[0:0]$9804 - attribute \src "libresoc.v:171235.3-171253.6" + attribute \src "libresoc.v:171234.3-171252.6" wire $2\nia_ok$next[0:0]$9798 - attribute \src "libresoc.v:171178.3-171196.6" + attribute \src "libresoc.v:171177.3-171195.6" wire $2\o_ok$next[0:0]$9780 - attribute \src "libresoc.v:171126.3-171143.6" + attribute \src "libresoc.v:171125.3-171142.6" wire $2\r_busy$next[0:0]$9752 - attribute \src "libresoc.v:171039.18-171039.118" - wire $and$libresoc.v:171039$9715_Y + attribute \src "libresoc.v:171038.18-171038.118" + wire $and$libresoc.v:171038$9715_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" @@ -350411,7 +347221,7 @@ module \pipe2$35 wire \fast2_ok$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast2_ok$next - attribute \src "libresoc.v:170328.7-170328.15" + attribute \src "libresoc.v:170327.7-170327.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_fast1 @@ -351070,7 +347880,7 @@ module \pipe2$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$8$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:171039$9715 + cell $and $and$libresoc.v:171038$9715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351078,10 +347888,10 @@ module \pipe2$35 parameter \Y_WIDTH 1 connect \A \p_valid_i$25 connect \B \p_ready_o - connect \Y $and$libresoc.v:171039$9715_Y + connect \Y $and$libresoc.v:171038$9715_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:171082.13-171117.4" + attribute \src "libresoc.v:171081.13-171116.4" cell \main$38 \main connect \fast1 \main_fast1 connect \fast1$11 \main_fast1$23 @@ -351119,349 +347929,349 @@ module \pipe2$35 connect \trap_op__traptype$8 \main_trap_op__traptype$20 end attribute \module_not_derived 1 - attribute \src "libresoc.v:171118.10-171121.4" + attribute \src "libresoc.v:171117.10-171120.4" cell \n$37 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:171122.10-171125.4" + attribute \src "libresoc.v:171121.10-171124.4" cell \p$36 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:170328.7-170328.20" - process $proc$libresoc.v:170328$9805 + attribute \src "libresoc.v:170327.7-170327.20" + process $proc$libresoc.v:170327$9805 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:170339.14-170339.47" - process $proc$libresoc.v:170339$9806 + attribute \src "libresoc.v:170338.14-170338.47" + process $proc$libresoc.v:170338$9806 assign { } { } assign $0\fast1$11[63:0]$9807 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast1$11 $0\fast1$11[63:0]$9807 end - attribute \src "libresoc.v:170346.7-170346.22" - process $proc$libresoc.v:170346$9808 + attribute \src "libresoc.v:170345.7-170345.22" + process $proc$libresoc.v:170345$9808 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:170355.14-170355.47" - process $proc$libresoc.v:170355$9809 + attribute \src "libresoc.v:170354.14-170354.47" + process $proc$libresoc.v:170354$9809 assign { } { } assign $0\fast2$12[63:0]$9810 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast2$12 $0\fast2$12[63:0]$9810 end - attribute \src "libresoc.v:170362.7-170362.22" - process $proc$libresoc.v:170362$9811 + attribute \src "libresoc.v:170361.7-170361.22" + process $proc$libresoc.v:170361$9811 assign { } { } assign $1\fast2_ok[0:0] 1'0 sync always sync init update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:170617.14-170617.40" - process $proc$libresoc.v:170617$9812 + attribute \src "libresoc.v:170616.14-170616.40" + process $proc$libresoc.v:170616$9812 assign { } { } assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr $1\msr[63:0] end - attribute \src "libresoc.v:170624.7-170624.20" - process $proc$libresoc.v:170624$9813 + attribute \src "libresoc.v:170623.7-170623.20" + process $proc$libresoc.v:170623$9813 assign { } { } assign $1\msr_ok[0:0] 1'0 sync always sync init update \msr_ok $1\msr_ok[0:0] end - attribute \src "libresoc.v:170633.13-170633.29" - process $proc$libresoc.v:170633$9814 + attribute \src "libresoc.v:170632.13-170632.29" + process $proc$libresoc.v:170632$9814 assign { } { } assign $0\muxid$1[1:0]$9815 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$9815 end - attribute \src "libresoc.v:170646.14-170646.40" - process $proc$libresoc.v:170646$9816 + attribute \src "libresoc.v:170645.14-170645.40" + process $proc$libresoc.v:170645$9816 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:170653.7-170653.20" - process $proc$libresoc.v:170653$9817 + attribute \src "libresoc.v:170652.7-170652.20" + process $proc$libresoc.v:170652$9817 assign { } { } assign $1\nia_ok[0:0] 1'0 sync always sync init update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:170660.14-170660.38" - process $proc$libresoc.v:170660$9818 + attribute \src "libresoc.v:170659.14-170659.38" + process $proc$libresoc.v:170659$9818 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:170667.7-170667.18" - process $proc$libresoc.v:170667$9819 + attribute \src "libresoc.v:170666.7-170666.18" + process $proc$libresoc.v:170666$9819 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:170681.7-170681.20" - process $proc$libresoc.v:170681$9820 + attribute \src "libresoc.v:170680.7-170680.20" + process $proc$libresoc.v:170680$9820 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:170694.14-170694.53" - process $proc$libresoc.v:170694$9821 + attribute \src "libresoc.v:170693.14-170693.53" + process $proc$libresoc.v:170693$9821 assign { } { } assign $0\trap_op__cia$6[63:0]$9822 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9822 end - attribute \src "libresoc.v:170731.14-170731.45" - process $proc$libresoc.v:170731$9823 + attribute \src "libresoc.v:170730.14-170730.45" + process $proc$libresoc.v:170730$9823 assign { } { } assign $0\trap_op__fn_unit$3[13:0]$9824 14'00000000000000 sync always sync init update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9824 end - attribute \src "libresoc.v:170757.14-170757.39" - process $proc$libresoc.v:170757$9825 + attribute \src "libresoc.v:170756.14-170756.39" + process $proc$libresoc.v:170756$9825 assign { } { } assign $0\trap_op__insn$4[31:0]$9826 0 sync always sync init update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9826 end - attribute \src "libresoc.v:170914.13-170914.43" - process $proc$libresoc.v:170914$9827 + attribute \src "libresoc.v:170913.13-170913.43" + process $proc$libresoc.v:170913$9827 assign { } { } assign $0\trap_op__insn_type$2[6:0]$9828 7'0000000 sync always sync init update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9828 end - attribute \src "libresoc.v:171000.7-171000.35" - process $proc$libresoc.v:171000$9829 + attribute \src "libresoc.v:170999.7-170999.35" + process $proc$libresoc.v:170999$9829 assign { } { } assign $0\trap_op__is_32bit$7[0:0]$9830 1'0 sync always sync init update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9830 end - attribute \src "libresoc.v:171007.13-171007.43" - process $proc$libresoc.v:171007$9831 + attribute \src "libresoc.v:171006.13-171006.43" + process $proc$libresoc.v:171006$9831 assign { } { } assign $0\trap_op__ldst_exc$10[7:0]$9832 8'00000000 sync always sync init update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9832 end - attribute \src "libresoc.v:171018.14-171018.53" - process $proc$libresoc.v:171018$9833 + attribute \src "libresoc.v:171017.14-171017.53" + process $proc$libresoc.v:171017$9833 assign { } { } assign $0\trap_op__msr$5[63:0]$9834 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9834 end - attribute \src "libresoc.v:171027.14-171027.46" - process $proc$libresoc.v:171027$9835 + attribute \src "libresoc.v:171026.14-171026.46" + process $proc$libresoc.v:171026$9835 assign { } { } assign $0\trap_op__trapaddr$9[12:0]$9836 13'0000000000000 sync always sync init update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9836 end - attribute \src "libresoc.v:171036.13-171036.42" - process $proc$libresoc.v:171036$9837 + attribute \src "libresoc.v:171035.13-171035.42" + process $proc$libresoc.v:171035$9837 assign { } { } assign $0\trap_op__traptype$8[7:0]$9838 8'00000000 sync always sync init update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9838 end - attribute \src "libresoc.v:171040.3-171041.23" - process $proc$libresoc.v:171040$9716 + attribute \src "libresoc.v:171039.3-171040.23" + process $proc$libresoc.v:171039$9716 assign { } { } assign $0\msr[63:0] \msr$next sync posedge \coresync_clk update \msr $0\msr[63:0] end - attribute \src "libresoc.v:171042.3-171043.29" - process $proc$libresoc.v:171042$9717 + attribute \src "libresoc.v:171041.3-171042.29" + process $proc$libresoc.v:171041$9717 assign { } { } assign $0\msr_ok[0:0] \msr_ok$next sync posedge \coresync_clk update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:171044.3-171045.23" - process $proc$libresoc.v:171044$9718 + attribute \src "libresoc.v:171043.3-171044.23" + process $proc$libresoc.v:171043$9718 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \coresync_clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:171046.3-171047.29" - process $proc$libresoc.v:171046$9719 + attribute \src "libresoc.v:171045.3-171046.29" + process $proc$libresoc.v:171045$9719 assign { } { } assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:171048.3-171049.35" - process $proc$libresoc.v:171048$9720 + attribute \src "libresoc.v:171047.3-171048.35" + process $proc$libresoc.v:171047$9720 assign { } { } assign $0\fast2$12[63:0]$9721 \fast2$12$next sync posedge \coresync_clk update \fast2$12 $0\fast2$12[63:0]$9721 end - attribute \src "libresoc.v:171050.3-171051.33" - process $proc$libresoc.v:171050$9722 + attribute \src "libresoc.v:171049.3-171050.33" + process $proc$libresoc.v:171049$9722 assign { } { } assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:171052.3-171053.35" - process $proc$libresoc.v:171052$9723 + attribute \src "libresoc.v:171051.3-171052.35" + process $proc$libresoc.v:171051$9723 assign { } { } assign $0\fast1$11[63:0]$9724 \fast1$11$next sync posedge \coresync_clk update \fast1$11 $0\fast1$11[63:0]$9724 end - attribute \src "libresoc.v:171054.3-171055.33" - process $proc$libresoc.v:171054$9725 + attribute \src "libresoc.v:171053.3-171054.33" + process $proc$libresoc.v:171053$9725 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:171056.3-171057.19" - process $proc$libresoc.v:171056$9726 + attribute \src "libresoc.v:171055.3-171056.19" + process $proc$libresoc.v:171055$9726 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:171058.3-171059.25" - process $proc$libresoc.v:171058$9727 + attribute \src "libresoc.v:171057.3-171058.25" + process $proc$libresoc.v:171057$9727 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:171060.3-171061.59" - process $proc$libresoc.v:171060$9728 + attribute \src "libresoc.v:171059.3-171060.59" + process $proc$libresoc.v:171059$9728 assign { } { } assign $0\trap_op__insn_type$2[6:0]$9729 \trap_op__insn_type$2$next sync posedge \coresync_clk update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9729 end - attribute \src "libresoc.v:171062.3-171063.55" - process $proc$libresoc.v:171062$9730 + attribute \src "libresoc.v:171061.3-171062.55" + process $proc$libresoc.v:171061$9730 assign { } { } assign $0\trap_op__fn_unit$3[13:0]$9731 \trap_op__fn_unit$3$next sync posedge \coresync_clk update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9731 end - attribute \src "libresoc.v:171064.3-171065.49" - process $proc$libresoc.v:171064$9732 + attribute \src "libresoc.v:171063.3-171064.49" + process $proc$libresoc.v:171063$9732 assign { } { } assign $0\trap_op__insn$4[31:0]$9733 \trap_op__insn$4$next sync posedge \coresync_clk update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9733 end - attribute \src "libresoc.v:171066.3-171067.47" - process $proc$libresoc.v:171066$9734 + attribute \src "libresoc.v:171065.3-171066.47" + process $proc$libresoc.v:171065$9734 assign { } { } assign $0\trap_op__msr$5[63:0]$9735 \trap_op__msr$5$next sync posedge \coresync_clk update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9735 end - attribute \src "libresoc.v:171068.3-171069.47" - process $proc$libresoc.v:171068$9736 + attribute \src "libresoc.v:171067.3-171068.47" + process $proc$libresoc.v:171067$9736 assign { } { } assign $0\trap_op__cia$6[63:0]$9737 \trap_op__cia$6$next sync posedge \coresync_clk update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9737 end - attribute \src "libresoc.v:171070.3-171071.57" - process $proc$libresoc.v:171070$9738 + attribute \src "libresoc.v:171069.3-171070.57" + process $proc$libresoc.v:171069$9738 assign { } { } assign $0\trap_op__is_32bit$7[0:0]$9739 \trap_op__is_32bit$7$next sync posedge \coresync_clk update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9739 end - attribute \src "libresoc.v:171072.3-171073.57" - process $proc$libresoc.v:171072$9740 + attribute \src "libresoc.v:171071.3-171072.57" + process $proc$libresoc.v:171071$9740 assign { } { } assign $0\trap_op__traptype$8[7:0]$9741 \trap_op__traptype$8$next sync posedge \coresync_clk update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9741 end - attribute \src "libresoc.v:171074.3-171075.57" - process $proc$libresoc.v:171074$9742 + attribute \src "libresoc.v:171073.3-171074.57" + process $proc$libresoc.v:171073$9742 assign { } { } assign $0\trap_op__trapaddr$9[12:0]$9743 \trap_op__trapaddr$9$next sync posedge \coresync_clk update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9743 end - attribute \src "libresoc.v:171076.3-171077.59" - process $proc$libresoc.v:171076$9744 + attribute \src "libresoc.v:171075.3-171076.59" + process $proc$libresoc.v:171075$9744 assign { } { } assign $0\trap_op__ldst_exc$10[7:0]$9745 \trap_op__ldst_exc$10$next sync posedge \coresync_clk update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9745 end - attribute \src "libresoc.v:171078.3-171079.33" - process $proc$libresoc.v:171078$9746 + attribute \src "libresoc.v:171077.3-171078.33" + process $proc$libresoc.v:171077$9746 assign { } { } assign $0\muxid$1[1:0]$9747 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$9747 end - attribute \src "libresoc.v:171080.3-171081.29" - process $proc$libresoc.v:171080$9748 + attribute \src "libresoc.v:171079.3-171080.29" + process $proc$libresoc.v:171079$9748 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:171126.3-171143.6" - process $proc$libresoc.v:171126$9749 + attribute \src "libresoc.v:171125.3-171142.6" + process $proc$libresoc.v:171125$9749 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9750 $2\r_busy$next[0:0]$9752 - attribute \src "libresoc.v:171127.5-171127.29" + attribute \src "libresoc.v:171126.5-171126.29" switch \initial - attribute \src "libresoc.v:171127.9-171127.17" + attribute \src "libresoc.v:171126.9-171126.17" case 1'1 case end @@ -351490,14 +348300,14 @@ module \pipe2$35 sync always update \r_busy$next $0\r_busy$next[0:0]$9750 end - attribute \src "libresoc.v:171144.3-171156.6" - process $proc$libresoc.v:171144$9753 + attribute \src "libresoc.v:171143.3-171155.6" + process $proc$libresoc.v:171143$9753 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$9754 $1\muxid$1$next[1:0]$9755 - attribute \src "libresoc.v:171145.5-171145.29" + attribute \src "libresoc.v:171144.5-171144.29" switch \initial - attribute \src "libresoc.v:171145.9-171145.17" + attribute \src "libresoc.v:171144.9-171144.17" case 1'1 case end @@ -351517,8 +348327,8 @@ module \pipe2$35 sync always update \muxid$1$next $0\muxid$1$next[1:0]$9754 end - attribute \src "libresoc.v:171157.3-171177.6" - process $proc$libresoc.v:171157$9756 + attribute \src "libresoc.v:171156.3-171176.6" + process $proc$libresoc.v:171156$9756 assign { } { } assign { } { } assign { } { } @@ -351546,9 +348356,9 @@ module \pipe2$35 assign $0\trap_op__msr$5$next[63:0]$9763 $1\trap_op__msr$5$next[63:0]$9772 assign $0\trap_op__trapaddr$9$next[12:0]$9764 $1\trap_op__trapaddr$9$next[12:0]$9773 assign $0\trap_op__traptype$8$next[7:0]$9765 $1\trap_op__traptype$8$next[7:0]$9774 - attribute \src "libresoc.v:171158.5-171158.29" + attribute \src "libresoc.v:171157.5-171157.29" switch \initial - attribute \src "libresoc.v:171158.9-171158.17" + attribute \src "libresoc.v:171157.9-171157.17" case 1'1 case end @@ -351600,8 +348410,8 @@ module \pipe2$35 update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9764 update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9765 end - attribute \src "libresoc.v:171178.3-171196.6" - process $proc$libresoc.v:171178$9775 + attribute \src "libresoc.v:171177.3-171195.6" + process $proc$libresoc.v:171177$9775 assign { } { } assign { } { } assign { } { } @@ -351609,9 +348419,9 @@ module \pipe2$35 assign $0\o$next[63:0]$9776 $1\o$next[63:0]$9778 assign { } { } assign $0\o_ok$next[0:0]$9777 $2\o_ok$next[0:0]$9780 - attribute \src "libresoc.v:171179.5-171179.29" + attribute \src "libresoc.v:171178.5-171178.29" switch \initial - attribute \src "libresoc.v:171179.9-171179.17" + attribute \src "libresoc.v:171178.9-171178.17" case 1'1 case end @@ -351644,8 +348454,8 @@ module \pipe2$35 update \o$next $0\o$next[63:0]$9776 update \o_ok$next $0\o_ok$next[0:0]$9777 end - attribute \src "libresoc.v:171197.3-171215.6" - process $proc$libresoc.v:171197$9781 + attribute \src "libresoc.v:171196.3-171214.6" + process $proc$libresoc.v:171196$9781 assign { } { } assign { } { } assign { } { } @@ -351653,9 +348463,9 @@ module \pipe2$35 assign { } { } assign $0\fast1$11$next[63:0]$9783 $1\fast1$11$next[63:0]$9785 assign $0\fast1_ok$next[0:0]$9782 $2\fast1_ok$next[0:0]$9786 - attribute \src "libresoc.v:171198.5-171198.29" + attribute \src "libresoc.v:171197.5-171197.29" switch \initial - attribute \src "libresoc.v:171198.9-171198.17" + attribute \src "libresoc.v:171197.9-171197.17" case 1'1 case end @@ -351688,8 +348498,8 @@ module \pipe2$35 update \fast1_ok$next $0\fast1_ok$next[0:0]$9782 update \fast1$11$next $0\fast1$11$next[63:0]$9783 end - attribute \src "libresoc.v:171216.3-171234.6" - process $proc$libresoc.v:171216$9787 + attribute \src "libresoc.v:171215.3-171233.6" + process $proc$libresoc.v:171215$9787 assign { } { } assign { } { } assign { } { } @@ -351697,9 +348507,9 @@ module \pipe2$35 assign { } { } assign $0\fast2$12$next[63:0]$9789 $1\fast2$12$next[63:0]$9791 assign $0\fast2_ok$next[0:0]$9788 $2\fast2_ok$next[0:0]$9792 - attribute \src "libresoc.v:171217.5-171217.29" + attribute \src "libresoc.v:171216.5-171216.29" switch \initial - attribute \src "libresoc.v:171217.9-171217.17" + attribute \src "libresoc.v:171216.9-171216.17" case 1'1 case end @@ -351732,8 +348542,8 @@ module \pipe2$35 update \fast2_ok$next $0\fast2_ok$next[0:0]$9788 update \fast2$12$next $0\fast2$12$next[63:0]$9789 end - attribute \src "libresoc.v:171235.3-171253.6" - process $proc$libresoc.v:171235$9793 + attribute \src "libresoc.v:171234.3-171252.6" + process $proc$libresoc.v:171234$9793 assign { } { } assign { } { } assign { } { } @@ -351741,9 +348551,9 @@ module \pipe2$35 assign $0\nia$next[63:0]$9794 $1\nia$next[63:0]$9796 assign { } { } assign $0\nia_ok$next[0:0]$9795 $2\nia_ok$next[0:0]$9798 - attribute \src "libresoc.v:171236.5-171236.29" + attribute \src "libresoc.v:171235.5-171235.29" switch \initial - attribute \src "libresoc.v:171236.9-171236.17" + attribute \src "libresoc.v:171235.9-171235.17" case 1'1 case end @@ -351776,8 +348586,8 @@ module \pipe2$35 update \nia$next $0\nia$next[63:0]$9794 update \nia_ok$next $0\nia_ok$next[0:0]$9795 end - attribute \src "libresoc.v:171254.3-171272.6" - process $proc$libresoc.v:171254$9799 + attribute \src "libresoc.v:171253.3-171271.6" + process $proc$libresoc.v:171253$9799 assign { } { } assign { } { } assign { } { } @@ -351785,9 +348595,9 @@ module \pipe2$35 assign $0\msr$next[63:0]$9800 $1\msr$next[63:0]$9802 assign { } { } assign $0\msr_ok$next[0:0]$9801 $2\msr_ok$next[0:0]$9804 - attribute \src "libresoc.v:171255.5-171255.29" + attribute \src "libresoc.v:171254.5-171254.29" switch \initial - attribute \src "libresoc.v:171255.9-171255.17" + attribute \src "libresoc.v:171254.9-171254.17" case 1'1 case end @@ -351820,7 +348630,7 @@ module \pipe2$35 update \msr$next $0\msr$next[63:0]$9800 update \msr_ok$next $0\msr_ok$next[0:0]$9801 end - connect \$26 $and$libresoc.v:171039$9715_Y + connect \$26 $and$libresoc.v:171038$9715_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr } @@ -351840,261 +348650,261 @@ module \pipe2$35 connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \main_muxid \muxid end -attribute \src "libresoc.v:171295.1-172798.10" +attribute \src "libresoc.v:171294.1-172797.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" attribute \generator "nMigen" module \pipe_end - attribute \src "libresoc.v:172636.3-172654.6" + attribute \src "libresoc.v:172635.3-172653.6" wire width 4 $0\cr_a$next[3:0]$9895 - attribute \src "libresoc.v:172455.3-172456.25" + attribute \src "libresoc.v:172454.3-172455.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:172636.3-172654.6" + attribute \src "libresoc.v:172635.3-172653.6" wire $0\cr_a_ok$next[0:0]$9896 - attribute \src "libresoc.v:172457.3-172458.31" + attribute \src "libresoc.v:172456.3-172457.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:171296.7-171296.20" + attribute \src "libresoc.v:171295.7-171295.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire width 4 $0\logical_op__data_len$18$next[3:0]$9920 - attribute \src "libresoc.v:172495.3-172496.65" + attribute \src "libresoc.v:172494.3-172495.65" wire width 4 $0\logical_op__data_len$18[3:0]$9882 - attribute \src "libresoc.v:171337.13-171337.45" + attribute \src "libresoc.v:171336.13-171336.45" wire width 4 $0\logical_op__data_len$18[3:0]$9966 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire width 14 $0\logical_op__fn_unit$3$next[13:0]$9921 - attribute \src "libresoc.v:172465.3-172466.61" + attribute \src "libresoc.v:172464.3-172465.61" wire width 14 $0\logical_op__fn_unit$3[13:0]$9852 - attribute \src "libresoc.v:171376.14-171376.48" + attribute \src "libresoc.v:171375.14-171375.48" wire width 14 $0\logical_op__fn_unit$3[13:0]$9968 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9922 - attribute \src "libresoc.v:172467.3-172468.75" + attribute \src "libresoc.v:172466.3-172467.75" wire width 64 $0\logical_op__imm_data__data$4[63:0]$9854 - attribute \src "libresoc.v:171400.14-171400.67" + attribute \src "libresoc.v:171399.14-171399.67" wire width 64 $0\logical_op__imm_data__data$4[63:0]$9970 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $0\logical_op__imm_data__ok$5$next[0:0]$9923 - attribute \src "libresoc.v:172469.3-172470.71" + attribute \src "libresoc.v:172468.3-172469.71" wire $0\logical_op__imm_data__ok$5[0:0]$9856 - attribute \src "libresoc.v:171409.7-171409.42" + attribute \src "libresoc.v:171408.7-171408.42" wire $0\logical_op__imm_data__ok$5[0:0]$9972 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire width 2 $0\logical_op__input_carry$12$next[1:0]$9924 - attribute \src "libresoc.v:172483.3-172484.71" + attribute \src "libresoc.v:172482.3-172483.71" wire width 2 $0\logical_op__input_carry$12[1:0]$9870 - attribute \src "libresoc.v:171426.13-171426.48" + attribute \src "libresoc.v:171425.13-171425.48" wire width 2 $0\logical_op__input_carry$12[1:0]$9974 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire width 32 $0\logical_op__insn$19$next[31:0]$9925 - attribute \src "libresoc.v:172497.3-172498.57" + attribute \src "libresoc.v:172496.3-172497.57" wire width 32 $0\logical_op__insn$19[31:0]$9884 - attribute \src "libresoc.v:171439.14-171439.43" + attribute \src "libresoc.v:171438.14-171438.43" wire width 32 $0\logical_op__insn$19[31:0]$9976 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire width 7 $0\logical_op__insn_type$2$next[6:0]$9926 - attribute \src "libresoc.v:172463.3-172464.65" + attribute \src "libresoc.v:172462.3-172463.65" wire width 7 $0\logical_op__insn_type$2[6:0]$9850 - attribute \src "libresoc.v:171598.13-171598.46" + attribute \src "libresoc.v:171597.13-171597.46" wire width 7 $0\logical_op__insn_type$2[6:0]$9978 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $0\logical_op__invert_in$10$next[0:0]$9927 - attribute \src "libresoc.v:172479.3-172480.67" + attribute \src "libresoc.v:172478.3-172479.67" wire $0\logical_op__invert_in$10[0:0]$9866 - attribute \src "libresoc.v:171682.7-171682.40" + attribute \src "libresoc.v:171681.7-171681.40" wire $0\logical_op__invert_in$10[0:0]$9980 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $0\logical_op__invert_out$13$next[0:0]$9928 - attribute \src "libresoc.v:172485.3-172486.69" + attribute \src "libresoc.v:172484.3-172485.69" wire $0\logical_op__invert_out$13[0:0]$9872 - attribute \src "libresoc.v:171691.7-171691.41" + attribute \src "libresoc.v:171690.7-171690.41" wire $0\logical_op__invert_out$13[0:0]$9982 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $0\logical_op__is_32bit$16$next[0:0]$9929 - attribute \src "libresoc.v:172491.3-172492.65" + attribute \src "libresoc.v:172490.3-172491.65" wire $0\logical_op__is_32bit$16[0:0]$9878 - attribute \src "libresoc.v:171700.7-171700.39" + attribute \src "libresoc.v:171699.7-171699.39" wire $0\logical_op__is_32bit$16[0:0]$9984 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $0\logical_op__is_signed$17$next[0:0]$9930 - attribute \src "libresoc.v:172493.3-172494.67" + attribute \src "libresoc.v:172492.3-172493.67" wire $0\logical_op__is_signed$17[0:0]$9880 - attribute \src "libresoc.v:171709.7-171709.40" + attribute \src "libresoc.v:171708.7-171708.40" wire $0\logical_op__is_signed$17[0:0]$9986 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $0\logical_op__oe__oe$8$next[0:0]$9931 - attribute \src "libresoc.v:172475.3-172476.59" + attribute \src "libresoc.v:172474.3-172475.59" wire $0\logical_op__oe__oe$8[0:0]$9862 - attribute \src "libresoc.v:171718.7-171718.36" + attribute \src "libresoc.v:171717.7-171717.36" wire $0\logical_op__oe__oe$8[0:0]$9988 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $0\logical_op__oe__ok$9$next[0:0]$9932 - attribute \src "libresoc.v:172477.3-172478.59" + attribute \src "libresoc.v:172476.3-172477.59" wire $0\logical_op__oe__ok$9[0:0]$9864 - attribute \src "libresoc.v:171729.7-171729.36" + attribute \src "libresoc.v:171728.7-171728.36" wire $0\logical_op__oe__ok$9[0:0]$9990 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $0\logical_op__output_carry$15$next[0:0]$9933 - attribute \src "libresoc.v:172489.3-172490.73" + attribute \src "libresoc.v:172488.3-172489.73" wire $0\logical_op__output_carry$15[0:0]$9876 - attribute \src "libresoc.v:171736.7-171736.43" + attribute \src "libresoc.v:171735.7-171735.43" wire $0\logical_op__output_carry$15[0:0]$9992 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $0\logical_op__rc__ok$7$next[0:0]$9934 - attribute \src "libresoc.v:172473.3-172474.59" + attribute \src "libresoc.v:172472.3-172473.59" wire $0\logical_op__rc__ok$7[0:0]$9860 - attribute \src "libresoc.v:171745.7-171745.36" + attribute \src "libresoc.v:171744.7-171744.36" wire $0\logical_op__rc__ok$7[0:0]$9994 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $0\logical_op__rc__rc$6$next[0:0]$9935 - attribute \src "libresoc.v:172471.3-172472.59" + attribute \src "libresoc.v:172470.3-172471.59" wire $0\logical_op__rc__rc$6[0:0]$9858 - attribute \src "libresoc.v:171754.7-171754.36" + attribute \src "libresoc.v:171753.7-171753.36" wire $0\logical_op__rc__rc$6[0:0]$9996 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $0\logical_op__write_cr0$14$next[0:0]$9936 - attribute \src "libresoc.v:172487.3-172488.67" + attribute \src "libresoc.v:172486.3-172487.67" wire $0\logical_op__write_cr0$14[0:0]$9874 - attribute \src "libresoc.v:171763.7-171763.40" + attribute \src "libresoc.v:171762.7-171762.40" wire $0\logical_op__write_cr0$14[0:0]$9998 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $0\logical_op__zero_a$11$next[0:0]$9937 - attribute \src "libresoc.v:171772.7-171772.37" + attribute \src "libresoc.v:171771.7-171771.37" wire $0\logical_op__zero_a$11[0:0]$10000 - attribute \src "libresoc.v:172481.3-172482.61" + attribute \src "libresoc.v:172480.3-172481.61" wire $0\logical_op__zero_a$11[0:0]$9868 - attribute \src "libresoc.v:172711.3-172723.6" + attribute \src "libresoc.v:172710.3-172722.6" wire width 2 $0\muxid$1$next[1:0]$9917 - attribute \src "libresoc.v:171781.13-171781.29" + attribute \src "libresoc.v:171780.13-171780.29" wire width 2 $0\muxid$1[1:0]$10002 - attribute \src "libresoc.v:172499.3-172500.33" + attribute \src "libresoc.v:172498.3-172499.33" wire width 2 $0\muxid$1[1:0]$9886 - attribute \src "libresoc.v:172617.3-172635.6" + attribute \src "libresoc.v:172616.3-172634.6" wire width 64 $0\o$next[63:0]$9889 - attribute \src "libresoc.v:172459.3-172460.19" + attribute \src "libresoc.v:172458.3-172459.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:172617.3-172635.6" + attribute \src "libresoc.v:172616.3-172634.6" wire $0\o_ok$next[0:0]$9890 - attribute \src "libresoc.v:172461.3-172462.25" + attribute \src "libresoc.v:172460.3-172461.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:172693.3-172710.6" + attribute \src "libresoc.v:172692.3-172709.6" wire $0\r_busy$next[0:0]$9913 - attribute \src "libresoc.v:172501.3-172502.29" + attribute \src "libresoc.v:172500.3-172501.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:172655.3-172673.6" + attribute \src "libresoc.v:172654.3-172672.6" wire width 2 $0\xer_ov$next[1:0]$9901 - attribute \src "libresoc.v:172451.3-172452.29" + attribute \src "libresoc.v:172450.3-172451.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:172655.3-172673.6" + attribute \src "libresoc.v:172654.3-172672.6" wire $0\xer_ov_ok$next[0:0]$9902 - attribute \src "libresoc.v:172453.3-172454.35" + attribute \src "libresoc.v:172452.3-172453.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:172674.3-172692.6" + attribute \src "libresoc.v:172673.3-172691.6" wire $0\xer_so$20$next[0:0]$9908 - attribute \src "libresoc.v:172432.7-172432.25" + attribute \src "libresoc.v:172431.7-172431.25" wire $0\xer_so$20[0:0]$10009 - attribute \src "libresoc.v:172447.3-172448.37" + attribute \src "libresoc.v:172446.3-172447.37" wire $0\xer_so$20[0:0]$9841 - attribute \src "libresoc.v:172674.3-172692.6" + attribute \src "libresoc.v:172673.3-172691.6" wire $0\xer_so_ok$next[0:0]$9907 - attribute \src "libresoc.v:172449.3-172450.35" + attribute \src "libresoc.v:172448.3-172449.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:172636.3-172654.6" + attribute \src "libresoc.v:172635.3-172653.6" wire width 4 $1\cr_a$next[3:0]$9897 - attribute \src "libresoc.v:171305.13-171305.24" + attribute \src "libresoc.v:171304.13-171304.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:172636.3-172654.6" + attribute \src "libresoc.v:172635.3-172653.6" wire $1\cr_a_ok$next[0:0]$9898 - attribute \src "libresoc.v:171314.7-171314.21" + attribute \src "libresoc.v:171313.7-171313.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire width 4 $1\logical_op__data_len$18$next[3:0]$9938 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire width 14 $1\logical_op__fn_unit$3$next[13:0]$9939 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9940 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $1\logical_op__imm_data__ok$5$next[0:0]$9941 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire width 2 $1\logical_op__input_carry$12$next[1:0]$9942 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire width 32 $1\logical_op__insn$19$next[31:0]$9943 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire width 7 $1\logical_op__insn_type$2$next[6:0]$9944 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $1\logical_op__invert_in$10$next[0:0]$9945 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $1\logical_op__invert_out$13$next[0:0]$9946 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $1\logical_op__is_32bit$16$next[0:0]$9947 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $1\logical_op__is_signed$17$next[0:0]$9948 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $1\logical_op__oe__oe$8$next[0:0]$9949 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $1\logical_op__oe__ok$9$next[0:0]$9950 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $1\logical_op__output_carry$15$next[0:0]$9951 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $1\logical_op__rc__ok$7$next[0:0]$9952 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $1\logical_op__rc__rc$6$next[0:0]$9953 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $1\logical_op__write_cr0$14$next[0:0]$9954 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $1\logical_op__zero_a$11$next[0:0]$9955 - attribute \src "libresoc.v:172711.3-172723.6" + attribute \src "libresoc.v:172710.3-172722.6" wire width 2 $1\muxid$1$next[1:0]$9918 - attribute \src "libresoc.v:172617.3-172635.6" + attribute \src "libresoc.v:172616.3-172634.6" wire width 64 $1\o$next[63:0]$9891 - attribute \src "libresoc.v:171794.14-171794.38" + attribute \src "libresoc.v:171793.14-171793.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:172617.3-172635.6" + attribute \src "libresoc.v:172616.3-172634.6" wire $1\o_ok$next[0:0]$9892 - attribute \src "libresoc.v:171801.7-171801.18" + attribute \src "libresoc.v:171800.7-171800.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:172693.3-172710.6" + attribute \src "libresoc.v:172692.3-172709.6" wire $1\r_busy$next[0:0]$9914 - attribute \src "libresoc.v:172397.7-172397.20" + attribute \src "libresoc.v:172396.7-172396.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:172655.3-172673.6" + attribute \src "libresoc.v:172654.3-172672.6" wire width 2 $1\xer_ov$next[1:0]$9903 - attribute \src "libresoc.v:172412.13-172412.26" + attribute \src "libresoc.v:172411.13-172411.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:172655.3-172673.6" + attribute \src "libresoc.v:172654.3-172672.6" wire $1\xer_ov_ok$next[0:0]$9904 - attribute \src "libresoc.v:172419.7-172419.23" + attribute \src "libresoc.v:172418.7-172418.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:172674.3-172692.6" + attribute \src "libresoc.v:172673.3-172691.6" wire $1\xer_so$20$next[0:0]$9910 - attribute \src "libresoc.v:172674.3-172692.6" + attribute \src "libresoc.v:172673.3-172691.6" wire $1\xer_so_ok$next[0:0]$9909 - attribute \src "libresoc.v:172437.7-172437.23" + attribute \src "libresoc.v:172436.7-172436.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:172636.3-172654.6" + attribute \src "libresoc.v:172635.3-172653.6" wire $2\cr_a_ok$next[0:0]$9899 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9956 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $2\logical_op__imm_data__ok$5$next[0:0]$9957 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $2\logical_op__oe__oe$8$next[0:0]$9958 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $2\logical_op__oe__ok$9$next[0:0]$9959 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $2\logical_op__rc__ok$7$next[0:0]$9960 - attribute \src "libresoc.v:172724.3-172765.6" + attribute \src "libresoc.v:172723.3-172764.6" wire $2\logical_op__rc__rc$6$next[0:0]$9961 - attribute \src "libresoc.v:172617.3-172635.6" + attribute \src "libresoc.v:172616.3-172634.6" wire $2\o_ok$next[0:0]$9893 - attribute \src "libresoc.v:172693.3-172710.6" + attribute \src "libresoc.v:172692.3-172709.6" wire $2\r_busy$next[0:0]$9915 - attribute \src "libresoc.v:172655.3-172673.6" + attribute \src "libresoc.v:172654.3-172672.6" wire $2\xer_ov_ok$next[0:0]$9905 - attribute \src "libresoc.v:172674.3-172692.6" + attribute \src "libresoc.v:172673.3-172691.6" wire $2\xer_so_ok$next[0:0]$9911 - attribute \src "libresoc.v:172446.18-172446.118" - wire $and$libresoc.v:172446$9839_Y + attribute \src "libresoc.v:172445.18-172445.118" + wire $and$libresoc.v:172445$9839_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" @@ -352129,7 +348939,7 @@ module \pipe_end wire input 27 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 26 \divisor_neg - attribute \src "libresoc.v:171296.7-171296.15" + attribute \src "libresoc.v:171295.7-171295.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -353220,7 +350030,7 @@ module \pipe_end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:172446$9839 + cell $and $and$libresoc.v:172445$9839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -353228,16 +350038,16 @@ module \pipe_end parameter \Y_WIDTH 1 connect \A \p_valid_i$73 connect \B \p_ready_o - connect \Y $and$libresoc.v:172446$9839_Y + connect \Y $and$libresoc.v:172445$9839_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:172503.10-172506.4" + attribute \src "libresoc.v:172502.10-172505.4" cell \n$82 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:172507.15-172559.4" + attribute \src "libresoc.v:172506.15-172558.4" cell \output$83 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$62 @@ -353292,7 +350102,7 @@ module \pipe_end connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:172560.16-172612.4" + attribute \src "libresoc.v:172559.16-172611.4" cell \output_stage \output_stage connect \div_by_zero \output_stage_div_by_zero connect \dive_abs_ov32 \output_stage_dive_abs_ov32 @@ -353347,441 +350157,441 @@ module \pipe_end connect \xer_so$20 \output_stage_xer_so$40 end attribute \module_not_derived 1 - attribute \src "libresoc.v:172613.10-172616.4" + attribute \src "libresoc.v:172612.10-172615.4" cell \p$81 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:171296.7-171296.20" - process $proc$libresoc.v:171296$9962 + attribute \src "libresoc.v:171295.7-171295.20" + process $proc$libresoc.v:171295$9962 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171305.13-171305.24" - process $proc$libresoc.v:171305$9963 + attribute \src "libresoc.v:171304.13-171304.24" + process $proc$libresoc.v:171304$9963 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:171314.7-171314.21" - process $proc$libresoc.v:171314$9964 + attribute \src "libresoc.v:171313.7-171313.21" + process $proc$libresoc.v:171313$9964 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:171337.13-171337.45" - process $proc$libresoc.v:171337$9965 + attribute \src "libresoc.v:171336.13-171336.45" + process $proc$libresoc.v:171336$9965 assign { } { } assign $0\logical_op__data_len$18[3:0]$9966 4'0000 sync always sync init update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9966 end - attribute \src "libresoc.v:171376.14-171376.48" - process $proc$libresoc.v:171376$9967 + attribute \src "libresoc.v:171375.14-171375.48" + process $proc$libresoc.v:171375$9967 assign { } { } assign $0\logical_op__fn_unit$3[13:0]$9968 14'00000000000000 sync always sync init update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9968 end - attribute \src "libresoc.v:171400.14-171400.67" - process $proc$libresoc.v:171400$9969 + attribute \src "libresoc.v:171399.14-171399.67" + process $proc$libresoc.v:171399$9969 assign { } { } assign $0\logical_op__imm_data__data$4[63:0]$9970 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9970 end - attribute \src "libresoc.v:171409.7-171409.42" - process $proc$libresoc.v:171409$9971 + attribute \src "libresoc.v:171408.7-171408.42" + process $proc$libresoc.v:171408$9971 assign { } { } assign $0\logical_op__imm_data__ok$5[0:0]$9972 1'0 sync always sync init update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9972 end - attribute \src "libresoc.v:171426.13-171426.48" - process $proc$libresoc.v:171426$9973 + attribute \src "libresoc.v:171425.13-171425.48" + process $proc$libresoc.v:171425$9973 assign { } { } assign $0\logical_op__input_carry$12[1:0]$9974 2'00 sync always sync init update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9974 end - attribute \src "libresoc.v:171439.14-171439.43" - process $proc$libresoc.v:171439$9975 + attribute \src "libresoc.v:171438.14-171438.43" + process $proc$libresoc.v:171438$9975 assign { } { } assign $0\logical_op__insn$19[31:0]$9976 0 sync always sync init update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9976 end - attribute \src "libresoc.v:171598.13-171598.46" - process $proc$libresoc.v:171598$9977 + attribute \src "libresoc.v:171597.13-171597.46" + process $proc$libresoc.v:171597$9977 assign { } { } assign $0\logical_op__insn_type$2[6:0]$9978 7'0000000 sync always sync init update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9978 end - attribute \src "libresoc.v:171682.7-171682.40" - process $proc$libresoc.v:171682$9979 + attribute \src "libresoc.v:171681.7-171681.40" + process $proc$libresoc.v:171681$9979 assign { } { } assign $0\logical_op__invert_in$10[0:0]$9980 1'0 sync always sync init update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9980 end - attribute \src "libresoc.v:171691.7-171691.41" - process $proc$libresoc.v:171691$9981 + attribute \src "libresoc.v:171690.7-171690.41" + process $proc$libresoc.v:171690$9981 assign { } { } assign $0\logical_op__invert_out$13[0:0]$9982 1'0 sync always sync init update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9982 end - attribute \src "libresoc.v:171700.7-171700.39" - process $proc$libresoc.v:171700$9983 + attribute \src "libresoc.v:171699.7-171699.39" + process $proc$libresoc.v:171699$9983 assign { } { } assign $0\logical_op__is_32bit$16[0:0]$9984 1'0 sync always sync init update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9984 end - attribute \src "libresoc.v:171709.7-171709.40" - process $proc$libresoc.v:171709$9985 + attribute \src "libresoc.v:171708.7-171708.40" + process $proc$libresoc.v:171708$9985 assign { } { } assign $0\logical_op__is_signed$17[0:0]$9986 1'0 sync always sync init update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9986 end - attribute \src "libresoc.v:171718.7-171718.36" - process $proc$libresoc.v:171718$9987 + attribute \src "libresoc.v:171717.7-171717.36" + process $proc$libresoc.v:171717$9987 assign { } { } assign $0\logical_op__oe__oe$8[0:0]$9988 1'0 sync always sync init update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9988 end - attribute \src "libresoc.v:171729.7-171729.36" - process $proc$libresoc.v:171729$9989 + attribute \src "libresoc.v:171728.7-171728.36" + process $proc$libresoc.v:171728$9989 assign { } { } assign $0\logical_op__oe__ok$9[0:0]$9990 1'0 sync always sync init update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9990 end - attribute \src "libresoc.v:171736.7-171736.43" - process $proc$libresoc.v:171736$9991 + attribute \src "libresoc.v:171735.7-171735.43" + process $proc$libresoc.v:171735$9991 assign { } { } assign $0\logical_op__output_carry$15[0:0]$9992 1'0 sync always sync init update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9992 end - attribute \src "libresoc.v:171745.7-171745.36" - process $proc$libresoc.v:171745$9993 + attribute \src "libresoc.v:171744.7-171744.36" + process $proc$libresoc.v:171744$9993 assign { } { } assign $0\logical_op__rc__ok$7[0:0]$9994 1'0 sync always sync init update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9994 end - attribute \src "libresoc.v:171754.7-171754.36" - process $proc$libresoc.v:171754$9995 + attribute \src "libresoc.v:171753.7-171753.36" + process $proc$libresoc.v:171753$9995 assign { } { } assign $0\logical_op__rc__rc$6[0:0]$9996 1'0 sync always sync init update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9996 end - attribute \src "libresoc.v:171763.7-171763.40" - process $proc$libresoc.v:171763$9997 + attribute \src "libresoc.v:171762.7-171762.40" + process $proc$libresoc.v:171762$9997 assign { } { } assign $0\logical_op__write_cr0$14[0:0]$9998 1'0 sync always sync init update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9998 end - attribute \src "libresoc.v:171772.7-171772.37" - process $proc$libresoc.v:171772$9999 + attribute \src "libresoc.v:171771.7-171771.37" + process $proc$libresoc.v:171771$9999 assign { } { } assign $0\logical_op__zero_a$11[0:0]$10000 1'0 sync always sync init update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$10000 end - attribute \src "libresoc.v:171781.13-171781.29" - process $proc$libresoc.v:171781$10001 + attribute \src "libresoc.v:171780.13-171780.29" + process $proc$libresoc.v:171780$10001 assign { } { } assign $0\muxid$1[1:0]$10002 2'00 sync always sync init update \muxid$1 $0\muxid$1[1:0]$10002 end - attribute \src "libresoc.v:171794.14-171794.38" - process $proc$libresoc.v:171794$10003 + attribute \src "libresoc.v:171793.14-171793.38" + process $proc$libresoc.v:171793$10003 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:171801.7-171801.18" - process $proc$libresoc.v:171801$10004 + attribute \src "libresoc.v:171800.7-171800.18" + process $proc$libresoc.v:171800$10004 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:172397.7-172397.20" - process $proc$libresoc.v:172397$10005 + attribute \src "libresoc.v:172396.7-172396.20" + process $proc$libresoc.v:172396$10005 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:172412.13-172412.26" - process $proc$libresoc.v:172412$10006 + attribute \src "libresoc.v:172411.13-172411.26" + process $proc$libresoc.v:172411$10006 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:172419.7-172419.23" - process $proc$libresoc.v:172419$10007 + attribute \src "libresoc.v:172418.7-172418.23" + process $proc$libresoc.v:172418$10007 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:172432.7-172432.25" - process $proc$libresoc.v:172432$10008 + attribute \src "libresoc.v:172431.7-172431.25" + process $proc$libresoc.v:172431$10008 assign { } { } assign $0\xer_so$20[0:0]$10009 1'0 sync always sync init update \xer_so$20 $0\xer_so$20[0:0]$10009 end - attribute \src "libresoc.v:172437.7-172437.23" - process $proc$libresoc.v:172437$10010 + attribute \src "libresoc.v:172436.7-172436.23" + process $proc$libresoc.v:172436$10010 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:172447.3-172448.37" - process $proc$libresoc.v:172447$9840 + attribute \src "libresoc.v:172446.3-172447.37" + process $proc$libresoc.v:172446$9840 assign { } { } assign $0\xer_so$20[0:0]$9841 \xer_so$20$next sync posedge \coresync_clk update \xer_so$20 $0\xer_so$20[0:0]$9841 end - attribute \src "libresoc.v:172449.3-172450.35" - process $proc$libresoc.v:172449$9842 + attribute \src "libresoc.v:172448.3-172449.35" + process $proc$libresoc.v:172448$9842 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:172451.3-172452.29" - process $proc$libresoc.v:172451$9843 + attribute \src "libresoc.v:172450.3-172451.29" + process $proc$libresoc.v:172450$9843 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:172453.3-172454.35" - process $proc$libresoc.v:172453$9844 + attribute \src "libresoc.v:172452.3-172453.35" + process $proc$libresoc.v:172452$9844 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:172455.3-172456.25" - process $proc$libresoc.v:172455$9845 + attribute \src "libresoc.v:172454.3-172455.25" + process $proc$libresoc.v:172454$9845 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:172457.3-172458.31" - process $proc$libresoc.v:172457$9846 + attribute \src "libresoc.v:172456.3-172457.31" + process $proc$libresoc.v:172456$9846 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:172459.3-172460.19" - process $proc$libresoc.v:172459$9847 + attribute \src "libresoc.v:172458.3-172459.19" + process $proc$libresoc.v:172458$9847 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:172461.3-172462.25" - process $proc$libresoc.v:172461$9848 + attribute \src "libresoc.v:172460.3-172461.25" + process $proc$libresoc.v:172460$9848 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:172463.3-172464.65" - process $proc$libresoc.v:172463$9849 + attribute \src "libresoc.v:172462.3-172463.65" + process $proc$libresoc.v:172462$9849 assign { } { } assign $0\logical_op__insn_type$2[6:0]$9850 \logical_op__insn_type$2$next sync posedge \coresync_clk update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9850 end - attribute \src "libresoc.v:172465.3-172466.61" - process $proc$libresoc.v:172465$9851 + attribute \src "libresoc.v:172464.3-172465.61" + process $proc$libresoc.v:172464$9851 assign { } { } assign $0\logical_op__fn_unit$3[13:0]$9852 \logical_op__fn_unit$3$next sync posedge \coresync_clk update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9852 end - attribute \src "libresoc.v:172467.3-172468.75" - process $proc$libresoc.v:172467$9853 + attribute \src "libresoc.v:172466.3-172467.75" + process $proc$libresoc.v:172466$9853 assign { } { } assign $0\logical_op__imm_data__data$4[63:0]$9854 \logical_op__imm_data__data$4$next sync posedge \coresync_clk update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9854 end - attribute \src "libresoc.v:172469.3-172470.71" - process $proc$libresoc.v:172469$9855 + attribute \src "libresoc.v:172468.3-172469.71" + process $proc$libresoc.v:172468$9855 assign { } { } assign $0\logical_op__imm_data__ok$5[0:0]$9856 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9856 end - attribute \src "libresoc.v:172471.3-172472.59" - process $proc$libresoc.v:172471$9857 + attribute \src "libresoc.v:172470.3-172471.59" + process $proc$libresoc.v:172470$9857 assign { } { } assign $0\logical_op__rc__rc$6[0:0]$9858 \logical_op__rc__rc$6$next sync posedge \coresync_clk update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9858 end - attribute \src "libresoc.v:172473.3-172474.59" - process $proc$libresoc.v:172473$9859 + attribute \src "libresoc.v:172472.3-172473.59" + process $proc$libresoc.v:172472$9859 assign { } { } assign $0\logical_op__rc__ok$7[0:0]$9860 \logical_op__rc__ok$7$next sync posedge \coresync_clk update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9860 end - attribute \src "libresoc.v:172475.3-172476.59" - process $proc$libresoc.v:172475$9861 + attribute \src "libresoc.v:172474.3-172475.59" + process $proc$libresoc.v:172474$9861 assign { } { } assign $0\logical_op__oe__oe$8[0:0]$9862 \logical_op__oe__oe$8$next sync posedge \coresync_clk update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9862 end - attribute \src "libresoc.v:172477.3-172478.59" - process $proc$libresoc.v:172477$9863 + attribute \src "libresoc.v:172476.3-172477.59" + process $proc$libresoc.v:172476$9863 assign { } { } assign $0\logical_op__oe__ok$9[0:0]$9864 \logical_op__oe__ok$9$next sync posedge \coresync_clk update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9864 end - attribute \src "libresoc.v:172479.3-172480.67" - process $proc$libresoc.v:172479$9865 + attribute \src "libresoc.v:172478.3-172479.67" + process $proc$libresoc.v:172478$9865 assign { } { } assign $0\logical_op__invert_in$10[0:0]$9866 \logical_op__invert_in$10$next sync posedge \coresync_clk update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9866 end - attribute \src "libresoc.v:172481.3-172482.61" - process $proc$libresoc.v:172481$9867 + attribute \src "libresoc.v:172480.3-172481.61" + process $proc$libresoc.v:172480$9867 assign { } { } assign $0\logical_op__zero_a$11[0:0]$9868 \logical_op__zero_a$11$next sync posedge \coresync_clk update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9868 end - attribute \src "libresoc.v:172483.3-172484.71" - process $proc$libresoc.v:172483$9869 + attribute \src "libresoc.v:172482.3-172483.71" + process $proc$libresoc.v:172482$9869 assign { } { } assign $0\logical_op__input_carry$12[1:0]$9870 \logical_op__input_carry$12$next sync posedge \coresync_clk update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9870 end - attribute \src "libresoc.v:172485.3-172486.69" - process $proc$libresoc.v:172485$9871 + attribute \src "libresoc.v:172484.3-172485.69" + process $proc$libresoc.v:172484$9871 assign { } { } assign $0\logical_op__invert_out$13[0:0]$9872 \logical_op__invert_out$13$next sync posedge \coresync_clk update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9872 end - attribute \src "libresoc.v:172487.3-172488.67" - process $proc$libresoc.v:172487$9873 + attribute \src "libresoc.v:172486.3-172487.67" + process $proc$libresoc.v:172486$9873 assign { } { } assign $0\logical_op__write_cr0$14[0:0]$9874 \logical_op__write_cr0$14$next sync posedge \coresync_clk update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9874 end - attribute \src "libresoc.v:172489.3-172490.73" - process $proc$libresoc.v:172489$9875 + attribute \src "libresoc.v:172488.3-172489.73" + process $proc$libresoc.v:172488$9875 assign { } { } assign $0\logical_op__output_carry$15[0:0]$9876 \logical_op__output_carry$15$next sync posedge \coresync_clk update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9876 end - attribute \src "libresoc.v:172491.3-172492.65" - process $proc$libresoc.v:172491$9877 + attribute \src "libresoc.v:172490.3-172491.65" + process $proc$libresoc.v:172490$9877 assign { } { } assign $0\logical_op__is_32bit$16[0:0]$9878 \logical_op__is_32bit$16$next sync posedge \coresync_clk update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9878 end - attribute \src "libresoc.v:172493.3-172494.67" - process $proc$libresoc.v:172493$9879 + attribute \src "libresoc.v:172492.3-172493.67" + process $proc$libresoc.v:172492$9879 assign { } { } assign $0\logical_op__is_signed$17[0:0]$9880 \logical_op__is_signed$17$next sync posedge \coresync_clk update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9880 end - attribute \src "libresoc.v:172495.3-172496.65" - process $proc$libresoc.v:172495$9881 + attribute \src "libresoc.v:172494.3-172495.65" + process $proc$libresoc.v:172494$9881 assign { } { } assign $0\logical_op__data_len$18[3:0]$9882 \logical_op__data_len$18$next sync posedge \coresync_clk update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9882 end - attribute \src "libresoc.v:172497.3-172498.57" - process $proc$libresoc.v:172497$9883 + attribute \src "libresoc.v:172496.3-172497.57" + process $proc$libresoc.v:172496$9883 assign { } { } assign $0\logical_op__insn$19[31:0]$9884 \logical_op__insn$19$next sync posedge \coresync_clk update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9884 end - attribute \src "libresoc.v:172499.3-172500.33" - process $proc$libresoc.v:172499$9885 + attribute \src "libresoc.v:172498.3-172499.33" + process $proc$libresoc.v:172498$9885 assign { } { } assign $0\muxid$1[1:0]$9886 \muxid$1$next sync posedge \coresync_clk update \muxid$1 $0\muxid$1[1:0]$9886 end - attribute \src "libresoc.v:172501.3-172502.29" - process $proc$libresoc.v:172501$9887 + attribute \src "libresoc.v:172500.3-172501.29" + process $proc$libresoc.v:172500$9887 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:172617.3-172635.6" - process $proc$libresoc.v:172617$9888 + attribute \src "libresoc.v:172616.3-172634.6" + process $proc$libresoc.v:172616$9888 assign { } { } assign { } { } assign { } { } @@ -353789,9 +350599,9 @@ module \pipe_end assign $0\o$next[63:0]$9889 $1\o$next[63:0]$9891 assign { } { } assign $0\o_ok$next[0:0]$9890 $2\o_ok$next[0:0]$9893 - attribute \src "libresoc.v:172618.5-172618.29" + attribute \src "libresoc.v:172617.5-172617.29" switch \initial - attribute \src "libresoc.v:172618.9-172618.17" + attribute \src "libresoc.v:172617.9-172617.17" case 1'1 case end @@ -353824,8 +350634,8 @@ module \pipe_end update \o$next $0\o$next[63:0]$9889 update \o_ok$next $0\o_ok$next[0:0]$9890 end - attribute \src "libresoc.v:172636.3-172654.6" - process $proc$libresoc.v:172636$9894 + attribute \src "libresoc.v:172635.3-172653.6" + process $proc$libresoc.v:172635$9894 assign { } { } assign { } { } assign { } { } @@ -353833,9 +350643,9 @@ module \pipe_end assign $0\cr_a$next[3:0]$9895 $1\cr_a$next[3:0]$9897 assign { } { } assign $0\cr_a_ok$next[0:0]$9896 $2\cr_a_ok$next[0:0]$9899 - attribute \src "libresoc.v:172637.5-172637.29" + attribute \src "libresoc.v:172636.5-172636.29" switch \initial - attribute \src "libresoc.v:172637.9-172637.17" + attribute \src "libresoc.v:172636.9-172636.17" case 1'1 case end @@ -353868,8 +350678,8 @@ module \pipe_end update \cr_a$next $0\cr_a$next[3:0]$9895 update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9896 end - attribute \src "libresoc.v:172655.3-172673.6" - process $proc$libresoc.v:172655$9900 + attribute \src "libresoc.v:172654.3-172672.6" + process $proc$libresoc.v:172654$9900 assign { } { } assign { } { } assign { } { } @@ -353877,9 +350687,9 @@ module \pipe_end assign $0\xer_ov$next[1:0]$9901 $1\xer_ov$next[1:0]$9903 assign { } { } assign $0\xer_ov_ok$next[0:0]$9902 $2\xer_ov_ok$next[0:0]$9905 - attribute \src "libresoc.v:172656.5-172656.29" + attribute \src "libresoc.v:172655.5-172655.29" switch \initial - attribute \src "libresoc.v:172656.9-172656.17" + attribute \src "libresoc.v:172655.9-172655.17" case 1'1 case end @@ -353912,8 +350722,8 @@ module \pipe_end update \xer_ov$next $0\xer_ov$next[1:0]$9901 update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9902 end - attribute \src "libresoc.v:172674.3-172692.6" - process $proc$libresoc.v:172674$9906 + attribute \src "libresoc.v:172673.3-172691.6" + process $proc$libresoc.v:172673$9906 assign { } { } assign { } { } assign { } { } @@ -353921,9 +350731,9 @@ module \pipe_end assign { } { } assign $0\xer_so$20$next[0:0]$9908 $1\xer_so$20$next[0:0]$9910 assign $0\xer_so_ok$next[0:0]$9907 $2\xer_so_ok$next[0:0]$9911 - attribute \src "libresoc.v:172675.5-172675.29" + attribute \src "libresoc.v:172674.5-172674.29" switch \initial - attribute \src "libresoc.v:172675.9-172675.17" + attribute \src "libresoc.v:172674.9-172674.17" case 1'1 case end @@ -353956,15 +350766,15 @@ module \pipe_end update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9907 update \xer_so$20$next $0\xer_so$20$next[0:0]$9908 end - attribute \src "libresoc.v:172693.3-172710.6" - process $proc$libresoc.v:172693$9912 + attribute \src "libresoc.v:172692.3-172709.6" + process $proc$libresoc.v:172692$9912 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$9913 $2\r_busy$next[0:0]$9915 - attribute \src "libresoc.v:172694.5-172694.29" + attribute \src "libresoc.v:172693.5-172693.29" switch \initial - attribute \src "libresoc.v:172694.9-172694.17" + attribute \src "libresoc.v:172693.9-172693.17" case 1'1 case end @@ -353993,14 +350803,14 @@ module \pipe_end sync always update \r_busy$next $0\r_busy$next[0:0]$9913 end - attribute \src "libresoc.v:172711.3-172723.6" - process $proc$libresoc.v:172711$9916 + attribute \src "libresoc.v:172710.3-172722.6" + process $proc$libresoc.v:172710$9916 assign { } { } assign { } { } assign $0\muxid$1$next[1:0]$9917 $1\muxid$1$next[1:0]$9918 - attribute \src "libresoc.v:172712.5-172712.29" + attribute \src "libresoc.v:172711.5-172711.29" switch \initial - attribute \src "libresoc.v:172712.9-172712.17" + attribute \src "libresoc.v:172711.9-172711.17" case 1'1 case end @@ -354020,8 +350830,8 @@ module \pipe_end sync always update \muxid$1$next $0\muxid$1$next[1:0]$9917 end - attribute \src "libresoc.v:172724.3-172765.6" - process $proc$libresoc.v:172724$9919 + attribute \src "libresoc.v:172723.3-172764.6" + process $proc$libresoc.v:172723$9919 assign { } { } assign { } { } assign { } { } @@ -354082,9 +350892,9 @@ module \pipe_end assign $0\logical_op__oe__ok$9$next[0:0]$9932 $2\logical_op__oe__ok$9$next[0:0]$9959 assign $0\logical_op__rc__ok$7$next[0:0]$9934 $2\logical_op__rc__ok$7$next[0:0]$9960 assign $0\logical_op__rc__rc$6$next[0:0]$9935 $2\logical_op__rc__rc$6$next[0:0]$9961 - attribute \src "libresoc.v:172725.5-172725.29" + attribute \src "libresoc.v:172724.5-172724.29" switch \initial - attribute \src "libresoc.v:172725.9-172725.17" + attribute \src "libresoc.v:172724.9-172724.17" case 1'1 case end @@ -354196,7 +351006,7 @@ module \pipe_end update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9936 update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9937 end - connect \$74 $and$libresoc.v:172446$9839_Y + connect \$74 $and$libresoc.v:172445$9839_Y connect \cr_a$68 4'0000 connect \cr_a_ok$69 1'0 connect \xer_so_ok$72 1'0 @@ -354230,381 +351040,381 @@ module \pipe_end connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_stage_muxid \muxid end -attribute \src "libresoc.v:172802.1-173789.10" +attribute \src "libresoc.v:172801.1-173788.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" attribute \generator "nMigen" module \pipe_middle_0 - attribute \src "libresoc.v:173714.3-173728.6" + attribute \src "libresoc.v:173713.3-173727.6" wire $0\div_by_zero$54$next[0:0]$10190 - attribute \src "libresoc.v:173388.3-173389.47" + attribute \src "libresoc.v:173387.3-173388.47" wire $0\div_by_zero$54[0:0]$10025 - attribute \src "libresoc.v:172825.7-172825.30" + attribute \src "libresoc.v:172824.7-172824.30" wire $0\div_by_zero$54[0:0]$10207 - attribute \src "libresoc.v:173510.3-173521.6" + attribute \src "libresoc.v:173509.3-173520.6" wire width 64 $0\div_state_next_divisor[63:0] - attribute \src "libresoc.v:173498.3-173509.6" + attribute \src "libresoc.v:173497.3-173508.6" wire width 128 $0\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:173486.3-173497.6" + attribute \src "libresoc.v:173485.3-173496.6" wire width 7 $0\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:173684.3-173698.6" + attribute \src "libresoc.v:173683.3-173697.6" wire $0\dive_abs_ov32$52$next[0:0]$10182 - attribute \src "libresoc.v:173392.3-173393.51" + attribute \src "libresoc.v:173391.3-173392.51" wire $0\dive_abs_ov32$52[0:0]$10029 - attribute \src "libresoc.v:172849.7-172849.32" + attribute \src "libresoc.v:172848.7-172848.32" wire $0\dive_abs_ov32$52[0:0]$10209 - attribute \src "libresoc.v:173699.3-173713.6" + attribute \src "libresoc.v:173698.3-173712.6" wire $0\dive_abs_ov64$53$next[0:0]$10186 - attribute \src "libresoc.v:173390.3-173391.51" + attribute \src "libresoc.v:173389.3-173390.51" wire $0\dive_abs_ov64$53[0:0]$10027 - attribute \src "libresoc.v:172857.7-172857.32" + attribute \src "libresoc.v:172856.7-172856.32" wire $0\dive_abs_ov64$53[0:0]$10211 - attribute \src "libresoc.v:173729.3-173743.6" + attribute \src "libresoc.v:173728.3-173742.6" wire width 128 $0\dividend$68$next[127:0]$10194 - attribute \src "libresoc.v:173386.3-173387.41" + attribute \src "libresoc.v:173385.3-173386.41" wire width 128 $0\dividend$68[127:0]$10023 - attribute \src "libresoc.v:172863.15-172863.68" + attribute \src "libresoc.v:172862.15-172862.68" wire width 128 $0\dividend$68[127:0]$10213 - attribute \src "libresoc.v:173669.3-173683.6" + attribute \src "libresoc.v:173668.3-173682.6" wire $0\dividend_neg$51$next[0:0]$10178 - attribute \src "libresoc.v:173394.3-173395.49" + attribute \src "libresoc.v:173393.3-173394.49" wire $0\dividend_neg$51[0:0]$10031 - attribute \src "libresoc.v:172871.7-172871.31" + attribute \src "libresoc.v:172870.7-172870.31" wire $0\dividend_neg$51[0:0]$10215 - attribute \src "libresoc.v:173654.3-173668.6" + attribute \src "libresoc.v:173653.3-173667.6" wire $0\divisor_neg$50$next[0:0]$10174 - attribute \src "libresoc.v:173396.3-173397.47" + attribute \src "libresoc.v:173395.3-173396.47" wire $0\divisor_neg$50[0:0]$10033 - attribute \src "libresoc.v:172879.7-172879.30" + attribute \src "libresoc.v:172878.7-172878.30" wire $0\divisor_neg$50[0:0]$10217 - attribute \src "libresoc.v:173744.3-173758.6" + attribute \src "libresoc.v:173743.3-173757.6" wire width 64 $0\divisor_radicand$65$next[63:0]$10198 - attribute \src "libresoc.v:173384.3-173385.57" + attribute \src "libresoc.v:173383.3-173384.57" wire width 64 $0\divisor_radicand$65[63:0]$10021 - attribute \src "libresoc.v:172885.14-172885.58" + attribute \src "libresoc.v:172884.14-172884.58" wire width 64 $0\divisor_radicand$65[63:0]$10219 - attribute \src "libresoc.v:173522.3-173549.6" + attribute \src "libresoc.v:173521.3-173548.6" wire $0\empty$next[0:0]$10091 - attribute \src "libresoc.v:173442.3-173443.27" + attribute \src "libresoc.v:173441.3-173442.27" wire $0\empty[0:0] - attribute \src "libresoc.v:172803.7-172803.20" + attribute \src "libresoc.v:172802.7-172802.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 4 $0\logical_op__data_len$45$next[3:0]$10101 - attribute \src "libresoc.v:173436.3-173437.65" + attribute \src "libresoc.v:173435.3-173436.65" wire width 4 $0\logical_op__data_len$45[3:0]$10073 - attribute \src "libresoc.v:172897.13-172897.45" + attribute \src "libresoc.v:172896.13-172896.45" wire width 4 $0\logical_op__data_len$45[3:0]$10222 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 14 $0\logical_op__fn_unit$30$next[13:0]$10102 - attribute \src "libresoc.v:173406.3-173407.63" + attribute \src "libresoc.v:173405.3-173406.63" wire width 14 $0\logical_op__fn_unit$30[13:0]$10043 - attribute \src "libresoc.v:172950.14-172950.49" + attribute \src "libresoc.v:172949.14-172949.49" wire width 14 $0\logical_op__fn_unit$30[13:0]$10224 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10103 - attribute \src "libresoc.v:173408.3-173409.77" + attribute \src "libresoc.v:173407.3-173408.77" wire width 64 $0\logical_op__imm_data__data$31[63:0]$10045 - attribute \src "libresoc.v:172956.14-172956.68" + attribute \src "libresoc.v:172955.14-172955.68" wire width 64 $0\logical_op__imm_data__data$31[63:0]$10226 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $0\logical_op__imm_data__ok$32$next[0:0]$10104 - attribute \src "libresoc.v:173410.3-173411.73" + attribute \src "libresoc.v:173409.3-173410.73" wire $0\logical_op__imm_data__ok$32[0:0]$10047 - attribute \src "libresoc.v:172964.7-172964.43" + attribute \src "libresoc.v:172963.7-172963.43" wire $0\logical_op__imm_data__ok$32[0:0]$10228 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 2 $0\logical_op__input_carry$39$next[1:0]$10105 - attribute \src "libresoc.v:173424.3-173425.71" + attribute \src "libresoc.v:173423.3-173424.71" wire width 2 $0\logical_op__input_carry$39[1:0]$10061 - attribute \src "libresoc.v:172986.13-172986.48" + attribute \src "libresoc.v:172985.13-172985.48" wire width 2 $0\logical_op__input_carry$39[1:0]$10230 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 32 $0\logical_op__insn$46$next[31:0]$10106 - attribute \src "libresoc.v:173438.3-173439.57" + attribute \src "libresoc.v:173437.3-173438.57" wire width 32 $0\logical_op__insn$46[31:0]$10075 - attribute \src "libresoc.v:172994.14-172994.43" + attribute \src "libresoc.v:172993.14-172993.43" wire width 32 $0\logical_op__insn$46[31:0]$10232 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 7 $0\logical_op__insn_type$29$next[6:0]$10107 - attribute \src "libresoc.v:173404.3-173405.67" + attribute \src "libresoc.v:173403.3-173404.67" wire width 7 $0\logical_op__insn_type$29[6:0]$10041 - attribute \src "libresoc.v:173227.13-173227.47" + attribute \src "libresoc.v:173226.13-173226.47" wire width 7 $0\logical_op__insn_type$29[6:0]$10234 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $0\logical_op__invert_in$37$next[0:0]$10108 - attribute \src "libresoc.v:173420.3-173421.67" + attribute \src "libresoc.v:173419.3-173420.67" wire $0\logical_op__invert_in$37[0:0]$10057 - attribute \src "libresoc.v:173235.7-173235.40" + attribute \src "libresoc.v:173234.7-173234.40" wire $0\logical_op__invert_in$37[0:0]$10236 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $0\logical_op__invert_out$40$next[0:0]$10109 - attribute \src "libresoc.v:173426.3-173427.69" + attribute \src "libresoc.v:173425.3-173426.69" wire $0\logical_op__invert_out$40[0:0]$10063 - attribute \src "libresoc.v:173243.7-173243.41" + attribute \src "libresoc.v:173242.7-173242.41" wire $0\logical_op__invert_out$40[0:0]$10238 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $0\logical_op__is_32bit$43$next[0:0]$10110 - attribute \src "libresoc.v:173432.3-173433.65" + attribute \src "libresoc.v:173431.3-173432.65" wire $0\logical_op__is_32bit$43[0:0]$10069 - attribute \src "libresoc.v:173251.7-173251.39" + attribute \src "libresoc.v:173250.7-173250.39" wire $0\logical_op__is_32bit$43[0:0]$10240 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $0\logical_op__is_signed$44$next[0:0]$10111 - attribute \src "libresoc.v:173434.3-173435.67" + attribute \src "libresoc.v:173433.3-173434.67" wire $0\logical_op__is_signed$44[0:0]$10071 - attribute \src "libresoc.v:173259.7-173259.40" + attribute \src "libresoc.v:173258.7-173258.40" wire $0\logical_op__is_signed$44[0:0]$10242 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $0\logical_op__oe__oe$35$next[0:0]$10112 - attribute \src "libresoc.v:173416.3-173417.61" + attribute \src "libresoc.v:173415.3-173416.61" wire $0\logical_op__oe__oe$35[0:0]$10053 - attribute \src "libresoc.v:173265.7-173265.37" + attribute \src "libresoc.v:173264.7-173264.37" wire $0\logical_op__oe__oe$35[0:0]$10244 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $0\logical_op__oe__ok$36$next[0:0]$10113 - attribute \src "libresoc.v:173418.3-173419.61" + attribute \src "libresoc.v:173417.3-173418.61" wire $0\logical_op__oe__ok$36[0:0]$10055 - attribute \src "libresoc.v:173273.7-173273.37" + attribute \src "libresoc.v:173272.7-173272.37" wire $0\logical_op__oe__ok$36[0:0]$10246 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $0\logical_op__output_carry$42$next[0:0]$10114 - attribute \src "libresoc.v:173430.3-173431.73" + attribute \src "libresoc.v:173429.3-173430.73" wire $0\logical_op__output_carry$42[0:0]$10067 - attribute \src "libresoc.v:173283.7-173283.43" + attribute \src "libresoc.v:173282.7-173282.43" wire $0\logical_op__output_carry$42[0:0]$10248 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $0\logical_op__rc__ok$34$next[0:0]$10115 - attribute \src "libresoc.v:173414.3-173415.61" + attribute \src "libresoc.v:173413.3-173414.61" wire $0\logical_op__rc__ok$34[0:0]$10051 - attribute \src "libresoc.v:173289.7-173289.37" + attribute \src "libresoc.v:173288.7-173288.37" wire $0\logical_op__rc__ok$34[0:0]$10250 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $0\logical_op__rc__rc$33$next[0:0]$10116 - attribute \src "libresoc.v:173412.3-173413.61" + attribute \src "libresoc.v:173411.3-173412.61" wire $0\logical_op__rc__rc$33[0:0]$10049 - attribute \src "libresoc.v:173297.7-173297.37" + attribute \src "libresoc.v:173296.7-173296.37" wire $0\logical_op__rc__rc$33[0:0]$10252 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $0\logical_op__write_cr0$41$next[0:0]$10117 - attribute \src "libresoc.v:173428.3-173429.67" + attribute \src "libresoc.v:173427.3-173428.67" wire $0\logical_op__write_cr0$41[0:0]$10065 - attribute \src "libresoc.v:173307.7-173307.40" + attribute \src "libresoc.v:173306.7-173306.40" wire $0\logical_op__write_cr0$41[0:0]$10254 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $0\logical_op__zero_a$38$next[0:0]$10118 - attribute \src "libresoc.v:173422.3-173423.61" + attribute \src "libresoc.v:173421.3-173422.61" wire $0\logical_op__zero_a$38[0:0]$10059 - attribute \src "libresoc.v:173315.7-173315.37" + attribute \src "libresoc.v:173314.7-173314.37" wire $0\logical_op__zero_a$38[0:0]$10256 - attribute \src "libresoc.v:173550.3-173564.6" + attribute \src "libresoc.v:173549.3-173563.6" wire width 2 $0\muxid$28$next[1:0]$10097 - attribute \src "libresoc.v:173440.3-173441.35" + attribute \src "libresoc.v:173439.3-173440.35" wire width 2 $0\muxid$28[1:0]$10077 - attribute \src "libresoc.v:173323.13-173323.30" + attribute \src "libresoc.v:173322.13-173322.30" wire width 2 $0\muxid$28[1:0]$10258 - attribute \src "libresoc.v:173759.3-173773.6" + attribute \src "libresoc.v:173758.3-173772.6" wire width 2 $0\operation$69$next[1:0]$10202 - attribute \src "libresoc.v:173382.3-173383.43" + attribute \src "libresoc.v:173381.3-173382.43" wire width 2 $0\operation$69[1:0]$10019 - attribute \src "libresoc.v:173333.13-173333.34" + attribute \src "libresoc.v:173332.13-173332.34" wire width 2 $0\operation$69[1:0]$10260 - attribute \src "libresoc.v:173609.3-173623.6" + attribute \src "libresoc.v:173608.3-173622.6" wire width 64 $0\ra$47$next[63:0]$10162 - attribute \src "libresoc.v:173402.3-173403.29" + attribute \src "libresoc.v:173401.3-173402.29" wire width 64 $0\ra$47[63:0]$10039 - attribute \src "libresoc.v:173347.14-173347.44" + attribute \src "libresoc.v:173346.14-173346.44" wire width 64 $0\ra$47[63:0]$10262 - attribute \src "libresoc.v:173624.3-173638.6" + attribute \src "libresoc.v:173623.3-173637.6" wire width 64 $0\rb$48$next[63:0]$10166 - attribute \src "libresoc.v:173400.3-173401.29" + attribute \src "libresoc.v:173399.3-173400.29" wire width 64 $0\rb$48[63:0]$10037 - attribute \src "libresoc.v:173355.14-173355.44" + attribute \src "libresoc.v:173354.14-173354.44" wire width 64 $0\rb$48[63:0]$10264 - attribute \src "libresoc.v:173477.3-173485.6" + attribute \src "libresoc.v:173476.3-173484.6" wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10085 - attribute \src "libresoc.v:173444.3-173445.75" + attribute \src "libresoc.v:173443.3-173444.75" wire width 128 $0\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:173468.3-173476.6" + attribute \src "libresoc.v:173467.3-173475.6" wire width 7 $0\saved_state_q_bits_known$next[6:0]$10082 - attribute \src "libresoc.v:173446.3-173447.65" + attribute \src "libresoc.v:173445.3-173446.65" wire width 7 $0\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:173639.3-173653.6" + attribute \src "libresoc.v:173638.3-173652.6" wire $0\xer_so$49$next[0:0]$10170 - attribute \src "libresoc.v:173398.3-173399.37" + attribute \src "libresoc.v:173397.3-173398.37" wire $0\xer_so$49[0:0]$10035 - attribute \src "libresoc.v:173373.7-173373.25" + attribute \src "libresoc.v:173372.7-173372.25" wire $0\xer_so$49[0:0]$10268 - attribute \src "libresoc.v:173714.3-173728.6" + attribute \src "libresoc.v:173713.3-173727.6" wire $1\div_by_zero$54$next[0:0]$10191 - attribute \src "libresoc.v:173510.3-173521.6" + attribute \src "libresoc.v:173509.3-173520.6" wire width 64 $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:173498.3-173509.6" + attribute \src "libresoc.v:173497.3-173508.6" wire width 128 $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:173486.3-173497.6" + attribute \src "libresoc.v:173485.3-173496.6" wire width 7 $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:173684.3-173698.6" + attribute \src "libresoc.v:173683.3-173697.6" wire $1\dive_abs_ov32$52$next[0:0]$10183 - attribute \src "libresoc.v:173699.3-173713.6" + attribute \src "libresoc.v:173698.3-173712.6" wire $1\dive_abs_ov64$53$next[0:0]$10187 - attribute \src "libresoc.v:173729.3-173743.6" + attribute \src "libresoc.v:173728.3-173742.6" wire width 128 $1\dividend$68$next[127:0]$10195 - attribute \src "libresoc.v:173669.3-173683.6" + attribute \src "libresoc.v:173668.3-173682.6" wire $1\dividend_neg$51$next[0:0]$10179 - attribute \src "libresoc.v:173654.3-173668.6" + attribute \src "libresoc.v:173653.3-173667.6" wire $1\divisor_neg$50$next[0:0]$10175 - attribute \src "libresoc.v:173744.3-173758.6" + attribute \src "libresoc.v:173743.3-173757.6" wire width 64 $1\divisor_radicand$65$next[63:0]$10199 - attribute \src "libresoc.v:173522.3-173549.6" + attribute \src "libresoc.v:173521.3-173548.6" wire $1\empty$next[0:0]$10092 - attribute \src "libresoc.v:172889.7-172889.19" + attribute \src "libresoc.v:172888.7-172888.19" wire $1\empty[0:0] - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 4 $1\logical_op__data_len$45$next[3:0]$10119 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 14 $1\logical_op__fn_unit$30$next[13:0]$10120 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10121 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $1\logical_op__imm_data__ok$32$next[0:0]$10122 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 2 $1\logical_op__input_carry$39$next[1:0]$10123 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 32 $1\logical_op__insn$46$next[31:0]$10124 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 7 $1\logical_op__insn_type$29$next[6:0]$10125 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $1\logical_op__invert_in$37$next[0:0]$10126 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $1\logical_op__invert_out$40$next[0:0]$10127 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $1\logical_op__is_32bit$43$next[0:0]$10128 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $1\logical_op__is_signed$44$next[0:0]$10129 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $1\logical_op__oe__oe$35$next[0:0]$10130 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $1\logical_op__oe__ok$36$next[0:0]$10131 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $1\logical_op__output_carry$42$next[0:0]$10132 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $1\logical_op__rc__ok$34$next[0:0]$10133 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $1\logical_op__rc__rc$33$next[0:0]$10134 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $1\logical_op__write_cr0$41$next[0:0]$10135 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $1\logical_op__zero_a$38$next[0:0]$10136 - attribute \src "libresoc.v:173550.3-173564.6" + attribute \src "libresoc.v:173549.3-173563.6" wire width 2 $1\muxid$28$next[1:0]$10098 - attribute \src "libresoc.v:173759.3-173773.6" + attribute \src "libresoc.v:173758.3-173772.6" wire width 2 $1\operation$69$next[1:0]$10203 - attribute \src "libresoc.v:173609.3-173623.6" + attribute \src "libresoc.v:173608.3-173622.6" wire width 64 $1\ra$47$next[63:0]$10163 - attribute \src "libresoc.v:173624.3-173638.6" + attribute \src "libresoc.v:173623.3-173637.6" wire width 64 $1\rb$48$next[63:0]$10167 - attribute \src "libresoc.v:173477.3-173485.6" + attribute \src "libresoc.v:173476.3-173484.6" wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10086 - attribute \src "libresoc.v:173361.15-173361.84" + attribute \src "libresoc.v:173360.15-173360.84" wire width 128 $1\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:173468.3-173476.6" + attribute \src "libresoc.v:173467.3-173475.6" wire width 7 $1\saved_state_q_bits_known$next[6:0]$10083 - attribute \src "libresoc.v:173365.13-173365.45" + attribute \src "libresoc.v:173364.13-173364.45" wire width 7 $1\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:173639.3-173653.6" + attribute \src "libresoc.v:173638.3-173652.6" wire $1\xer_so$49$next[0:0]$10171 - attribute \src "libresoc.v:173714.3-173728.6" + attribute \src "libresoc.v:173713.3-173727.6" wire $2\div_by_zero$54$next[0:0]$10192 - attribute \src "libresoc.v:173684.3-173698.6" + attribute \src "libresoc.v:173683.3-173697.6" wire $2\dive_abs_ov32$52$next[0:0]$10184 - attribute \src "libresoc.v:173699.3-173713.6" + attribute \src "libresoc.v:173698.3-173712.6" wire $2\dive_abs_ov64$53$next[0:0]$10188 - attribute \src "libresoc.v:173729.3-173743.6" + attribute \src "libresoc.v:173728.3-173742.6" wire width 128 $2\dividend$68$next[127:0]$10196 - attribute \src "libresoc.v:173669.3-173683.6" + attribute \src "libresoc.v:173668.3-173682.6" wire $2\dividend_neg$51$next[0:0]$10180 - attribute \src "libresoc.v:173654.3-173668.6" + attribute \src "libresoc.v:173653.3-173667.6" wire $2\divisor_neg$50$next[0:0]$10176 - attribute \src "libresoc.v:173744.3-173758.6" + attribute \src "libresoc.v:173743.3-173757.6" wire width 64 $2\divisor_radicand$65$next[63:0]$10200 - attribute \src "libresoc.v:173522.3-173549.6" + attribute \src "libresoc.v:173521.3-173548.6" wire $2\empty$next[0:0]$10093 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 4 $2\logical_op__data_len$45$next[3:0]$10137 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 14 $2\logical_op__fn_unit$30$next[13:0]$10138 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10139 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $2\logical_op__imm_data__ok$32$next[0:0]$10140 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 2 $2\logical_op__input_carry$39$next[1:0]$10141 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 32 $2\logical_op__insn$46$next[31:0]$10142 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 7 $2\logical_op__insn_type$29$next[6:0]$10143 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $2\logical_op__invert_in$37$next[0:0]$10144 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $2\logical_op__invert_out$40$next[0:0]$10145 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $2\logical_op__is_32bit$43$next[0:0]$10146 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $2\logical_op__is_signed$44$next[0:0]$10147 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $2\logical_op__oe__oe$35$next[0:0]$10148 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $2\logical_op__oe__ok$36$next[0:0]$10149 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $2\logical_op__output_carry$42$next[0:0]$10150 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $2\logical_op__rc__ok$34$next[0:0]$10151 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $2\logical_op__rc__rc$33$next[0:0]$10152 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $2\logical_op__write_cr0$41$next[0:0]$10153 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $2\logical_op__zero_a$38$next[0:0]$10154 - attribute \src "libresoc.v:173550.3-173564.6" + attribute \src "libresoc.v:173549.3-173563.6" wire width 2 $2\muxid$28$next[1:0]$10099 - attribute \src "libresoc.v:173759.3-173773.6" + attribute \src "libresoc.v:173758.3-173772.6" wire width 2 $2\operation$69$next[1:0]$10204 - attribute \src "libresoc.v:173609.3-173623.6" + attribute \src "libresoc.v:173608.3-173622.6" wire width 64 $2\ra$47$next[63:0]$10164 - attribute \src "libresoc.v:173624.3-173638.6" + attribute \src "libresoc.v:173623.3-173637.6" wire width 64 $2\rb$48$next[63:0]$10168 - attribute \src "libresoc.v:173639.3-173653.6" + attribute \src "libresoc.v:173638.3-173652.6" wire $2\xer_so$49$next[0:0]$10172 - attribute \src "libresoc.v:173522.3-173549.6" + attribute \src "libresoc.v:173521.3-173548.6" wire $3\empty$next[0:0]$10094 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10155 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $3\logical_op__imm_data__ok$32$next[0:0]$10156 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $3\logical_op__oe__oe$35$next[0:0]$10157 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $3\logical_op__oe__ok$36$next[0:0]$10158 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $3\logical_op__rc__ok$34$next[0:0]$10159 - attribute \src "libresoc.v:173565.3-173608.6" + attribute \src "libresoc.v:173564.3-173607.6" wire $3\logical_op__rc__rc$33$next[0:0]$10160 - attribute \src "libresoc.v:173522.3-173549.6" + attribute \src "libresoc.v:173521.3-173548.6" wire $4\empty$next[0:0]$10095 - attribute \src "libresoc.v:173380.18-173380.98" - wire $and$libresoc.v:173380$10016_Y - attribute \src "libresoc.v:173381.18-173381.107" - wire $and$libresoc.v:173381$10017_Y - attribute \src "libresoc.v:173377.18-173377.92" - wire width 192 $extend$libresoc.v:173377$10012_Y - attribute \src "libresoc.v:173379.18-173379.119" - wire $ge$libresoc.v:173379$10015_Y - attribute \src "libresoc.v:173378.18-173378.93" - wire $not$libresoc.v:173378$10014_Y - attribute \src "libresoc.v:173377.18-173377.92" - wire width 192 $pos$libresoc.v:173377$10013_Y - attribute \src "libresoc.v:173376.18-173376.138" - wire width 191 $sshl$libresoc.v:173376$10011_Y + attribute \src "libresoc.v:173379.18-173379.98" + wire $and$libresoc.v:173379$10016_Y + attribute \src "libresoc.v:173380.18-173380.107" + wire $and$libresoc.v:173380$10017_Y + attribute \src "libresoc.v:173376.18-173376.92" + wire width 192 $extend$libresoc.v:173376$10012_Y + attribute \src "libresoc.v:173378.18-173378.119" + wire $ge$libresoc.v:173378$10015_Y + attribute \src "libresoc.v:173377.18-173377.93" + wire $not$libresoc.v:173377$10014_Y + attribute \src "libresoc.v:173376.18-173376.92" + wire width 192 $pos$libresoc.v:173376$10013_Y + attribute \src "libresoc.v:173375.18-173375.138" + wire width 191 $sshl$libresoc.v:173375$10011_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" wire width 192 \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" @@ -354693,7 +351503,7 @@ module \pipe_middle_0 wire \empty attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" wire \empty$next - attribute \src "libresoc.v:172803.7-172803.15" + attribute \src "libresoc.v:172802.7-172802.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -355180,7 +351990,7 @@ module \pipe_middle_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$49$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $and $and$libresoc.v:173380$10016 + cell $and $and$libresoc.v:173379$10016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355188,10 +351998,10 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 - connect \Y $and$libresoc.v:173380$10016_Y + connect \Y $and$libresoc.v:173379$10016_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - cell $and $and$libresoc.v:173381$10017 + cell $and $and$libresoc.v:173380$10017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -355199,18 +352009,18 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:173381$10017_Y + connect \Y $and$libresoc.v:173380$10017_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $extend$libresoc.v:173377$10012 + cell $pos $extend$libresoc.v:173376$10012 parameter \A_SIGNED 0 parameter \A_WIDTH 191 parameter \Y_WIDTH 192 connect \A \$56 - connect \Y $extend$libresoc.v:173377$10012_Y + connect \Y $extend$libresoc.v:173376$10012_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:173379$10015 + cell $ge $ge$libresoc.v:173378$10015 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -355218,26 +352028,26 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \saved_state_q_bits_known connect \B 6'111111 - connect \Y $ge$libresoc.v:173379$10015_Y + connect \Y $ge$libresoc.v:173378$10015_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $not $not$libresoc.v:173378$10014 + cell $not $not$libresoc.v:173377$10014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \empty - connect \Y $not$libresoc.v:173378$10014_Y + connect \Y $not$libresoc.v:173377$10014_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $pos$libresoc.v:173377$10013 + cell $pos $pos$libresoc.v:173376$10013 parameter \A_SIGNED 0 parameter \A_WIDTH 192 parameter \Y_WIDTH 192 - connect \A $extend$libresoc.v:173377$10012_Y - connect \Y $pos$libresoc.v:173377$10013_Y + connect \A $extend$libresoc.v:173376$10012_Y + connect \Y $pos$libresoc.v:173376$10013_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $sshl $sshl$libresoc.v:173376$10011 + cell $sshl $sshl$libresoc.v:173375$10011 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -355245,17 +352055,17 @@ module \pipe_middle_0 parameter \Y_WIDTH 191 connect \A \div_state_next_o_dividend_quotient [127:64] connect \B 7'1000000 - connect \Y $sshl$libresoc.v:173376$10011_Y + connect \Y $sshl$libresoc.v:173375$10011_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:173448.18-173452.4" + attribute \src "libresoc.v:173447.18-173451.4" cell \div_state_init \div_state_init connect \dividend \div_state_init_dividend connect \o_dividend_quotient \div_state_init_o_dividend_quotient connect \o_q_bits_known \div_state_init_o_q_bits_known end attribute \module_not_derived 1 - attribute \src "libresoc.v:173453.18-173459.4" + attribute \src "libresoc.v:173452.18-173458.4" cell \div_state_next \div_state_next connect \divisor \div_state_next_divisor connect \i_dividend_quotient \div_state_next_i_dividend_quotient @@ -355264,528 +352074,528 @@ module \pipe_middle_0 connect \o_q_bits_known \div_state_next_o_q_bits_known end attribute \module_not_derived 1 - attribute \src "libresoc.v:173460.10-173463.4" + attribute \src "libresoc.v:173459.10-173462.4" cell \n$80 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:173464.10-173467.4" + attribute \src "libresoc.v:173463.10-173466.4" cell \p$79 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:172803.7-172803.20" - process $proc$libresoc.v:172803$10205 + attribute \src "libresoc.v:172802.7-172802.20" + process $proc$libresoc.v:172802$10205 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172825.7-172825.30" - process $proc$libresoc.v:172825$10206 + attribute \src "libresoc.v:172824.7-172824.30" + process $proc$libresoc.v:172824$10206 assign { } { } assign $0\div_by_zero$54[0:0]$10207 1'0 sync always sync init update \div_by_zero$54 $0\div_by_zero$54[0:0]$10207 end - attribute \src "libresoc.v:172849.7-172849.32" - process $proc$libresoc.v:172849$10208 + attribute \src "libresoc.v:172848.7-172848.32" + process $proc$libresoc.v:172848$10208 assign { } { } assign $0\dive_abs_ov32$52[0:0]$10209 1'0 sync always sync init update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10209 end - attribute \src "libresoc.v:172857.7-172857.32" - process $proc$libresoc.v:172857$10210 + attribute \src "libresoc.v:172856.7-172856.32" + process $proc$libresoc.v:172856$10210 assign { } { } assign $0\dive_abs_ov64$53[0:0]$10211 1'0 sync always sync init update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10211 end - attribute \src "libresoc.v:172863.15-172863.68" - process $proc$libresoc.v:172863$10212 + attribute \src "libresoc.v:172862.15-172862.68" + process $proc$libresoc.v:172862$10212 assign { } { } assign $0\dividend$68[127:0]$10213 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dividend$68 $0\dividend$68[127:0]$10213 end - attribute \src "libresoc.v:172871.7-172871.31" - process $proc$libresoc.v:172871$10214 + attribute \src "libresoc.v:172870.7-172870.31" + process $proc$libresoc.v:172870$10214 assign { } { } assign $0\dividend_neg$51[0:0]$10215 1'0 sync always sync init update \dividend_neg$51 $0\dividend_neg$51[0:0]$10215 end - attribute \src "libresoc.v:172879.7-172879.30" - process $proc$libresoc.v:172879$10216 + attribute \src "libresoc.v:172878.7-172878.30" + process $proc$libresoc.v:172878$10216 assign { } { } assign $0\divisor_neg$50[0:0]$10217 1'0 sync always sync init update \divisor_neg$50 $0\divisor_neg$50[0:0]$10217 end - attribute \src "libresoc.v:172885.14-172885.58" - process $proc$libresoc.v:172885$10218 + attribute \src "libresoc.v:172884.14-172884.58" + process $proc$libresoc.v:172884$10218 assign { } { } assign $0\divisor_radicand$65[63:0]$10219 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10219 end - attribute \src "libresoc.v:172889.7-172889.19" - process $proc$libresoc.v:172889$10220 + attribute \src "libresoc.v:172888.7-172888.19" + process $proc$libresoc.v:172888$10220 assign { } { } assign $1\empty[0:0] 1'1 sync always sync init update \empty $1\empty[0:0] end - attribute \src "libresoc.v:172897.13-172897.45" - process $proc$libresoc.v:172897$10221 + attribute \src "libresoc.v:172896.13-172896.45" + process $proc$libresoc.v:172896$10221 assign { } { } assign $0\logical_op__data_len$45[3:0]$10222 4'0000 sync always sync init update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10222 end - attribute \src "libresoc.v:172950.14-172950.49" - process $proc$libresoc.v:172950$10223 + attribute \src "libresoc.v:172949.14-172949.49" + process $proc$libresoc.v:172949$10223 assign { } { } assign $0\logical_op__fn_unit$30[13:0]$10224 14'00000000000000 sync always sync init update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10224 end - attribute \src "libresoc.v:172956.14-172956.68" - process $proc$libresoc.v:172956$10225 + attribute \src "libresoc.v:172955.14-172955.68" + process $proc$libresoc.v:172955$10225 assign { } { } assign $0\logical_op__imm_data__data$31[63:0]$10226 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10226 end - attribute \src "libresoc.v:172964.7-172964.43" - process $proc$libresoc.v:172964$10227 + attribute \src "libresoc.v:172963.7-172963.43" + process $proc$libresoc.v:172963$10227 assign { } { } assign $0\logical_op__imm_data__ok$32[0:0]$10228 1'0 sync always sync init update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10228 end - attribute \src "libresoc.v:172986.13-172986.48" - process $proc$libresoc.v:172986$10229 + attribute \src "libresoc.v:172985.13-172985.48" + process $proc$libresoc.v:172985$10229 assign { } { } assign $0\logical_op__input_carry$39[1:0]$10230 2'00 sync always sync init update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10230 end - attribute \src "libresoc.v:172994.14-172994.43" - process $proc$libresoc.v:172994$10231 + attribute \src "libresoc.v:172993.14-172993.43" + process $proc$libresoc.v:172993$10231 assign { } { } assign $0\logical_op__insn$46[31:0]$10232 0 sync always sync init update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10232 end - attribute \src "libresoc.v:173227.13-173227.47" - process $proc$libresoc.v:173227$10233 + attribute \src "libresoc.v:173226.13-173226.47" + process $proc$libresoc.v:173226$10233 assign { } { } assign $0\logical_op__insn_type$29[6:0]$10234 7'0000000 sync always sync init update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10234 end - attribute \src "libresoc.v:173235.7-173235.40" - process $proc$libresoc.v:173235$10235 + attribute \src "libresoc.v:173234.7-173234.40" + process $proc$libresoc.v:173234$10235 assign { } { } assign $0\logical_op__invert_in$37[0:0]$10236 1'0 sync always sync init update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10236 end - attribute \src "libresoc.v:173243.7-173243.41" - process $proc$libresoc.v:173243$10237 + attribute \src "libresoc.v:173242.7-173242.41" + process $proc$libresoc.v:173242$10237 assign { } { } assign $0\logical_op__invert_out$40[0:0]$10238 1'0 sync always sync init update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10238 end - attribute \src "libresoc.v:173251.7-173251.39" - process $proc$libresoc.v:173251$10239 + attribute \src "libresoc.v:173250.7-173250.39" + process $proc$libresoc.v:173250$10239 assign { } { } assign $0\logical_op__is_32bit$43[0:0]$10240 1'0 sync always sync init update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10240 end - attribute \src "libresoc.v:173259.7-173259.40" - process $proc$libresoc.v:173259$10241 + attribute \src "libresoc.v:173258.7-173258.40" + process $proc$libresoc.v:173258$10241 assign { } { } assign $0\logical_op__is_signed$44[0:0]$10242 1'0 sync always sync init update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10242 end - attribute \src "libresoc.v:173265.7-173265.37" - process $proc$libresoc.v:173265$10243 + attribute \src "libresoc.v:173264.7-173264.37" + process $proc$libresoc.v:173264$10243 assign { } { } assign $0\logical_op__oe__oe$35[0:0]$10244 1'0 sync always sync init update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10244 end - attribute \src "libresoc.v:173273.7-173273.37" - process $proc$libresoc.v:173273$10245 + attribute \src "libresoc.v:173272.7-173272.37" + process $proc$libresoc.v:173272$10245 assign { } { } assign $0\logical_op__oe__ok$36[0:0]$10246 1'0 sync always sync init update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10246 end - attribute \src "libresoc.v:173283.7-173283.43" - process $proc$libresoc.v:173283$10247 + attribute \src "libresoc.v:173282.7-173282.43" + process $proc$libresoc.v:173282$10247 assign { } { } assign $0\logical_op__output_carry$42[0:0]$10248 1'0 sync always sync init update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10248 end - attribute \src "libresoc.v:173289.7-173289.37" - process $proc$libresoc.v:173289$10249 + attribute \src "libresoc.v:173288.7-173288.37" + process $proc$libresoc.v:173288$10249 assign { } { } assign $0\logical_op__rc__ok$34[0:0]$10250 1'0 sync always sync init update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10250 end - attribute \src "libresoc.v:173297.7-173297.37" - process $proc$libresoc.v:173297$10251 + attribute \src "libresoc.v:173296.7-173296.37" + process $proc$libresoc.v:173296$10251 assign { } { } assign $0\logical_op__rc__rc$33[0:0]$10252 1'0 sync always sync init update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10252 end - attribute \src "libresoc.v:173307.7-173307.40" - process $proc$libresoc.v:173307$10253 + attribute \src "libresoc.v:173306.7-173306.40" + process $proc$libresoc.v:173306$10253 assign { } { } assign $0\logical_op__write_cr0$41[0:0]$10254 1'0 sync always sync init update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10254 end - attribute \src "libresoc.v:173315.7-173315.37" - process $proc$libresoc.v:173315$10255 + attribute \src "libresoc.v:173314.7-173314.37" + process $proc$libresoc.v:173314$10255 assign { } { } assign $0\logical_op__zero_a$38[0:0]$10256 1'0 sync always sync init update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10256 end - attribute \src "libresoc.v:173323.13-173323.30" - process $proc$libresoc.v:173323$10257 + attribute \src "libresoc.v:173322.13-173322.30" + process $proc$libresoc.v:173322$10257 assign { } { } assign $0\muxid$28[1:0]$10258 2'00 sync always sync init update \muxid$28 $0\muxid$28[1:0]$10258 end - attribute \src "libresoc.v:173333.13-173333.34" - process $proc$libresoc.v:173333$10259 + attribute \src "libresoc.v:173332.13-173332.34" + process $proc$libresoc.v:173332$10259 assign { } { } assign $0\operation$69[1:0]$10260 2'00 sync always sync init update \operation$69 $0\operation$69[1:0]$10260 end - attribute \src "libresoc.v:173347.14-173347.44" - process $proc$libresoc.v:173347$10261 + attribute \src "libresoc.v:173346.14-173346.44" + process $proc$libresoc.v:173346$10261 assign { } { } assign $0\ra$47[63:0]$10262 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra$47 $0\ra$47[63:0]$10262 end - attribute \src "libresoc.v:173355.14-173355.44" - process $proc$libresoc.v:173355$10263 + attribute \src "libresoc.v:173354.14-173354.44" + process $proc$libresoc.v:173354$10263 assign { } { } assign $0\rb$48[63:0]$10264 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb$48 $0\rb$48[63:0]$10264 end - attribute \src "libresoc.v:173361.15-173361.84" - process $proc$libresoc.v:173361$10265 + attribute \src "libresoc.v:173360.15-173360.84" + process $proc$libresoc.v:173360$10265 assign { } { } assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] end - attribute \src "libresoc.v:173365.13-173365.45" - process $proc$libresoc.v:173365$10266 + attribute \src "libresoc.v:173364.13-173364.45" + process $proc$libresoc.v:173364$10266 assign { } { } assign $1\saved_state_q_bits_known[6:0] 7'0000000 sync always sync init update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] end - attribute \src "libresoc.v:173373.7-173373.25" - process $proc$libresoc.v:173373$10267 + attribute \src "libresoc.v:173372.7-173372.25" + process $proc$libresoc.v:173372$10267 assign { } { } assign $0\xer_so$49[0:0]$10268 1'0 sync always sync init update \xer_so$49 $0\xer_so$49[0:0]$10268 end - attribute \src "libresoc.v:173382.3-173383.43" - process $proc$libresoc.v:173382$10018 + attribute \src "libresoc.v:173381.3-173382.43" + process $proc$libresoc.v:173381$10018 assign { } { } assign $0\operation$69[1:0]$10019 \operation$69$next sync posedge \coresync_clk update \operation$69 $0\operation$69[1:0]$10019 end - attribute \src "libresoc.v:173384.3-173385.57" - process $proc$libresoc.v:173384$10020 + attribute \src "libresoc.v:173383.3-173384.57" + process $proc$libresoc.v:173383$10020 assign { } { } assign $0\divisor_radicand$65[63:0]$10021 \divisor_radicand$65$next sync posedge \coresync_clk update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10021 end - attribute \src "libresoc.v:173386.3-173387.41" - process $proc$libresoc.v:173386$10022 + attribute \src "libresoc.v:173385.3-173386.41" + process $proc$libresoc.v:173385$10022 assign { } { } assign $0\dividend$68[127:0]$10023 \dividend$68$next sync posedge \coresync_clk update \dividend$68 $0\dividend$68[127:0]$10023 end - attribute \src "libresoc.v:173388.3-173389.47" - process $proc$libresoc.v:173388$10024 + attribute \src "libresoc.v:173387.3-173388.47" + process $proc$libresoc.v:173387$10024 assign { } { } assign $0\div_by_zero$54[0:0]$10025 \div_by_zero$54$next sync posedge \coresync_clk update \div_by_zero$54 $0\div_by_zero$54[0:0]$10025 end - attribute \src "libresoc.v:173390.3-173391.51" - process $proc$libresoc.v:173390$10026 + attribute \src "libresoc.v:173389.3-173390.51" + process $proc$libresoc.v:173389$10026 assign { } { } assign $0\dive_abs_ov64$53[0:0]$10027 \dive_abs_ov64$53$next sync posedge \coresync_clk update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10027 end - attribute \src "libresoc.v:173392.3-173393.51" - process $proc$libresoc.v:173392$10028 + attribute \src "libresoc.v:173391.3-173392.51" + process $proc$libresoc.v:173391$10028 assign { } { } assign $0\dive_abs_ov32$52[0:0]$10029 \dive_abs_ov32$52$next sync posedge \coresync_clk update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10029 end - attribute \src "libresoc.v:173394.3-173395.49" - process $proc$libresoc.v:173394$10030 + attribute \src "libresoc.v:173393.3-173394.49" + process $proc$libresoc.v:173393$10030 assign { } { } assign $0\dividend_neg$51[0:0]$10031 \dividend_neg$51$next sync posedge \coresync_clk update \dividend_neg$51 $0\dividend_neg$51[0:0]$10031 end - attribute \src "libresoc.v:173396.3-173397.47" - process $proc$libresoc.v:173396$10032 + attribute \src "libresoc.v:173395.3-173396.47" + process $proc$libresoc.v:173395$10032 assign { } { } assign $0\divisor_neg$50[0:0]$10033 \divisor_neg$50$next sync posedge \coresync_clk update \divisor_neg$50 $0\divisor_neg$50[0:0]$10033 end - attribute \src "libresoc.v:173398.3-173399.37" - process $proc$libresoc.v:173398$10034 + attribute \src "libresoc.v:173397.3-173398.37" + process $proc$libresoc.v:173397$10034 assign { } { } assign $0\xer_so$49[0:0]$10035 \xer_so$49$next sync posedge \coresync_clk update \xer_so$49 $0\xer_so$49[0:0]$10035 end - attribute \src "libresoc.v:173400.3-173401.29" - process $proc$libresoc.v:173400$10036 + attribute \src "libresoc.v:173399.3-173400.29" + process $proc$libresoc.v:173399$10036 assign { } { } assign $0\rb$48[63:0]$10037 \rb$48$next sync posedge \coresync_clk update \rb$48 $0\rb$48[63:0]$10037 end - attribute \src "libresoc.v:173402.3-173403.29" - process $proc$libresoc.v:173402$10038 + attribute \src "libresoc.v:173401.3-173402.29" + process $proc$libresoc.v:173401$10038 assign { } { } assign $0\ra$47[63:0]$10039 \ra$47$next sync posedge \coresync_clk update \ra$47 $0\ra$47[63:0]$10039 end - attribute \src "libresoc.v:173404.3-173405.67" - process $proc$libresoc.v:173404$10040 + attribute \src "libresoc.v:173403.3-173404.67" + process $proc$libresoc.v:173403$10040 assign { } { } assign $0\logical_op__insn_type$29[6:0]$10041 \logical_op__insn_type$29$next sync posedge \coresync_clk update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10041 end - attribute \src "libresoc.v:173406.3-173407.63" - process $proc$libresoc.v:173406$10042 + attribute \src "libresoc.v:173405.3-173406.63" + process $proc$libresoc.v:173405$10042 assign { } { } assign $0\logical_op__fn_unit$30[13:0]$10043 \logical_op__fn_unit$30$next sync posedge \coresync_clk update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10043 end - attribute \src "libresoc.v:173408.3-173409.77" - process $proc$libresoc.v:173408$10044 + attribute \src "libresoc.v:173407.3-173408.77" + process $proc$libresoc.v:173407$10044 assign { } { } assign $0\logical_op__imm_data__data$31[63:0]$10045 \logical_op__imm_data__data$31$next sync posedge \coresync_clk update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10045 end - attribute \src "libresoc.v:173410.3-173411.73" - process $proc$libresoc.v:173410$10046 + attribute \src "libresoc.v:173409.3-173410.73" + process $proc$libresoc.v:173409$10046 assign { } { } assign $0\logical_op__imm_data__ok$32[0:0]$10047 \logical_op__imm_data__ok$32$next sync posedge \coresync_clk update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10047 end - attribute \src "libresoc.v:173412.3-173413.61" - process $proc$libresoc.v:173412$10048 + attribute \src "libresoc.v:173411.3-173412.61" + process $proc$libresoc.v:173411$10048 assign { } { } assign $0\logical_op__rc__rc$33[0:0]$10049 \logical_op__rc__rc$33$next sync posedge \coresync_clk update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10049 end - attribute \src "libresoc.v:173414.3-173415.61" - process $proc$libresoc.v:173414$10050 + attribute \src "libresoc.v:173413.3-173414.61" + process $proc$libresoc.v:173413$10050 assign { } { } assign $0\logical_op__rc__ok$34[0:0]$10051 \logical_op__rc__ok$34$next sync posedge \coresync_clk update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10051 end - attribute \src "libresoc.v:173416.3-173417.61" - process $proc$libresoc.v:173416$10052 + attribute \src "libresoc.v:173415.3-173416.61" + process $proc$libresoc.v:173415$10052 assign { } { } assign $0\logical_op__oe__oe$35[0:0]$10053 \logical_op__oe__oe$35$next sync posedge \coresync_clk update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10053 end - attribute \src "libresoc.v:173418.3-173419.61" - process $proc$libresoc.v:173418$10054 + attribute \src "libresoc.v:173417.3-173418.61" + process $proc$libresoc.v:173417$10054 assign { } { } assign $0\logical_op__oe__ok$36[0:0]$10055 \logical_op__oe__ok$36$next sync posedge \coresync_clk update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10055 end - attribute \src "libresoc.v:173420.3-173421.67" - process $proc$libresoc.v:173420$10056 + attribute \src "libresoc.v:173419.3-173420.67" + process $proc$libresoc.v:173419$10056 assign { } { } assign $0\logical_op__invert_in$37[0:0]$10057 \logical_op__invert_in$37$next sync posedge \coresync_clk update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10057 end - attribute \src "libresoc.v:173422.3-173423.61" - process $proc$libresoc.v:173422$10058 + attribute \src "libresoc.v:173421.3-173422.61" + process $proc$libresoc.v:173421$10058 assign { } { } assign $0\logical_op__zero_a$38[0:0]$10059 \logical_op__zero_a$38$next sync posedge \coresync_clk update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10059 end - attribute \src "libresoc.v:173424.3-173425.71" - process $proc$libresoc.v:173424$10060 + attribute \src "libresoc.v:173423.3-173424.71" + process $proc$libresoc.v:173423$10060 assign { } { } assign $0\logical_op__input_carry$39[1:0]$10061 \logical_op__input_carry$39$next sync posedge \coresync_clk update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10061 end - attribute \src "libresoc.v:173426.3-173427.69" - process $proc$libresoc.v:173426$10062 + attribute \src "libresoc.v:173425.3-173426.69" + process $proc$libresoc.v:173425$10062 assign { } { } assign $0\logical_op__invert_out$40[0:0]$10063 \logical_op__invert_out$40$next sync posedge \coresync_clk update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10063 end - attribute \src "libresoc.v:173428.3-173429.67" - process $proc$libresoc.v:173428$10064 + attribute \src "libresoc.v:173427.3-173428.67" + process $proc$libresoc.v:173427$10064 assign { } { } assign $0\logical_op__write_cr0$41[0:0]$10065 \logical_op__write_cr0$41$next sync posedge \coresync_clk update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10065 end - attribute \src "libresoc.v:173430.3-173431.73" - process $proc$libresoc.v:173430$10066 + attribute \src "libresoc.v:173429.3-173430.73" + process $proc$libresoc.v:173429$10066 assign { } { } assign $0\logical_op__output_carry$42[0:0]$10067 \logical_op__output_carry$42$next sync posedge \coresync_clk update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10067 end - attribute \src "libresoc.v:173432.3-173433.65" - process $proc$libresoc.v:173432$10068 + attribute \src "libresoc.v:173431.3-173432.65" + process $proc$libresoc.v:173431$10068 assign { } { } assign $0\logical_op__is_32bit$43[0:0]$10069 \logical_op__is_32bit$43$next sync posedge \coresync_clk update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10069 end - attribute \src "libresoc.v:173434.3-173435.67" - process $proc$libresoc.v:173434$10070 + attribute \src "libresoc.v:173433.3-173434.67" + process $proc$libresoc.v:173433$10070 assign { } { } assign $0\logical_op__is_signed$44[0:0]$10071 \logical_op__is_signed$44$next sync posedge \coresync_clk update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10071 end - attribute \src "libresoc.v:173436.3-173437.65" - process $proc$libresoc.v:173436$10072 + attribute \src "libresoc.v:173435.3-173436.65" + process $proc$libresoc.v:173435$10072 assign { } { } assign $0\logical_op__data_len$45[3:0]$10073 \logical_op__data_len$45$next sync posedge \coresync_clk update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10073 end - attribute \src "libresoc.v:173438.3-173439.57" - process $proc$libresoc.v:173438$10074 + attribute \src "libresoc.v:173437.3-173438.57" + process $proc$libresoc.v:173437$10074 assign { } { } assign $0\logical_op__insn$46[31:0]$10075 \logical_op__insn$46$next sync posedge \coresync_clk update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10075 end - attribute \src "libresoc.v:173440.3-173441.35" - process $proc$libresoc.v:173440$10076 + attribute \src "libresoc.v:173439.3-173440.35" + process $proc$libresoc.v:173439$10076 assign { } { } assign $0\muxid$28[1:0]$10077 \muxid$28$next sync posedge \coresync_clk update \muxid$28 $0\muxid$28[1:0]$10077 end - attribute \src "libresoc.v:173442.3-173443.27" - process $proc$libresoc.v:173442$10078 + attribute \src "libresoc.v:173441.3-173442.27" + process $proc$libresoc.v:173441$10078 assign { } { } assign $0\empty[0:0] \empty$next sync posedge \coresync_clk update \empty $0\empty[0:0] end - attribute \src "libresoc.v:173444.3-173445.75" - process $proc$libresoc.v:173444$10079 + attribute \src "libresoc.v:173443.3-173444.75" + process $proc$libresoc.v:173443$10079 assign { } { } assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next sync posedge \coresync_clk update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] end - attribute \src "libresoc.v:173446.3-173447.65" - process $proc$libresoc.v:173446$10080 + attribute \src "libresoc.v:173445.3-173446.65" + process $proc$libresoc.v:173445$10080 assign { } { } assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next sync posedge \coresync_clk update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] end - attribute \src "libresoc.v:173468.3-173476.6" - process $proc$libresoc.v:173468$10081 + attribute \src "libresoc.v:173467.3-173475.6" + process $proc$libresoc.v:173467$10081 assign { } { } assign { } { } assign $0\saved_state_q_bits_known$next[6:0]$10082 $1\saved_state_q_bits_known$next[6:0]$10083 - attribute \src "libresoc.v:173469.5-173469.29" + attribute \src "libresoc.v:173468.5-173468.29" switch \initial - attribute \src "libresoc.v:173469.9-173469.17" + attribute \src "libresoc.v:173468.9-173468.17" case 1'1 case end @@ -355801,14 +352611,14 @@ module \pipe_middle_0 sync always update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10082 end - attribute \src "libresoc.v:173477.3-173485.6" - process $proc$libresoc.v:173477$10084 + attribute \src "libresoc.v:173476.3-173484.6" + process $proc$libresoc.v:173476$10084 assign { } { } assign { } { } assign $0\saved_state_dividend_quotient$next[127:0]$10085 $1\saved_state_dividend_quotient$next[127:0]$10086 - attribute \src "libresoc.v:173478.5-173478.29" + attribute \src "libresoc.v:173477.5-173477.29" switch \initial - attribute \src "libresoc.v:173478.9-173478.17" + attribute \src "libresoc.v:173477.9-173477.17" case 1'1 case end @@ -355824,13 +352634,13 @@ module \pipe_middle_0 sync always update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10085 end - attribute \src "libresoc.v:173486.3-173497.6" - process $proc$libresoc.v:173486$10087 + attribute \src "libresoc.v:173485.3-173496.6" + process $proc$libresoc.v:173485$10087 assign { } { } assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:173487.5-173487.29" + attribute \src "libresoc.v:173486.5-173486.29" switch \initial - attribute \src "libresoc.v:173487.9-173487.17" + attribute \src "libresoc.v:173486.9-173486.17" case 1'1 case end @@ -355848,13 +352658,13 @@ module \pipe_middle_0 sync always update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] end - attribute \src "libresoc.v:173498.3-173509.6" - process $proc$libresoc.v:173498$10088 + attribute \src "libresoc.v:173497.3-173508.6" + process $proc$libresoc.v:173497$10088 assign { } { } assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:173499.5-173499.29" + attribute \src "libresoc.v:173498.5-173498.29" switch \initial - attribute \src "libresoc.v:173499.9-173499.17" + attribute \src "libresoc.v:173498.9-173498.17" case 1'1 case end @@ -355872,13 +352682,13 @@ module \pipe_middle_0 sync always update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] end - attribute \src "libresoc.v:173510.3-173521.6" - process $proc$libresoc.v:173510$10089 + attribute \src "libresoc.v:173509.3-173520.6" + process $proc$libresoc.v:173509$10089 assign { } { } assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:173511.5-173511.29" + attribute \src "libresoc.v:173510.5-173510.29" switch \initial - attribute \src "libresoc.v:173511.9-173511.17" + attribute \src "libresoc.v:173510.9-173510.17" case 1'1 case end @@ -355896,15 +352706,15 @@ module \pipe_middle_0 sync always update \div_state_next_divisor $0\div_state_next_divisor[63:0] end - attribute \src "libresoc.v:173522.3-173549.6" - process $proc$libresoc.v:173522$10090 + attribute \src "libresoc.v:173521.3-173548.6" + process $proc$libresoc.v:173521$10090 assign { } { } assign { } { } assign { } { } assign $0\empty$next[0:0]$10091 $4\empty$next[0:0]$10095 - attribute \src "libresoc.v:173523.5-173523.29" + attribute \src "libresoc.v:173522.5-173522.29" switch \initial - attribute \src "libresoc.v:173523.9-173523.17" + attribute \src "libresoc.v:173522.9-173522.17" case 1'1 case end @@ -355949,14 +352759,14 @@ module \pipe_middle_0 sync always update \empty$next $0\empty$next[0:0]$10091 end - attribute \src "libresoc.v:173550.3-173564.6" - process $proc$libresoc.v:173550$10096 + attribute \src "libresoc.v:173549.3-173563.6" + process $proc$libresoc.v:173549$10096 assign { } { } assign { } { } assign $0\muxid$28$next[1:0]$10097 $1\muxid$28$next[1:0]$10098 - attribute \src "libresoc.v:173551.5-173551.29" + attribute \src "libresoc.v:173550.5-173550.29" switch \initial - attribute \src "libresoc.v:173551.9-173551.17" + attribute \src "libresoc.v:173550.9-173550.17" case 1'1 case end @@ -355981,8 +352791,8 @@ module \pipe_middle_0 sync always update \muxid$28$next $0\muxid$28$next[1:0]$10097 end - attribute \src "libresoc.v:173565.3-173608.6" - process $proc$libresoc.v:173565$10100 + attribute \src "libresoc.v:173564.3-173607.6" + process $proc$libresoc.v:173564$10100 assign { } { } assign { } { } assign { } { } @@ -356043,9 +352853,9 @@ module \pipe_middle_0 assign $0\logical_op__oe__ok$36$next[0:0]$10113 $3\logical_op__oe__ok$36$next[0:0]$10158 assign $0\logical_op__rc__ok$34$next[0:0]$10115 $3\logical_op__rc__ok$34$next[0:0]$10159 assign $0\logical_op__rc__rc$33$next[0:0]$10116 $3\logical_op__rc__rc$33$next[0:0]$10160 - attribute \src "libresoc.v:173566.5-173566.29" + attribute \src "libresoc.v:173565.5-173565.29" switch \initial - attribute \src "libresoc.v:173566.9-173566.17" + attribute \src "libresoc.v:173565.9-173565.17" case 1'1 case end @@ -356196,14 +353006,14 @@ module \pipe_middle_0 update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10117 update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10118 end - attribute \src "libresoc.v:173609.3-173623.6" - process $proc$libresoc.v:173609$10161 + attribute \src "libresoc.v:173608.3-173622.6" + process $proc$libresoc.v:173608$10161 assign { } { } assign { } { } assign $0\ra$47$next[63:0]$10162 $1\ra$47$next[63:0]$10163 - attribute \src "libresoc.v:173610.5-173610.29" + attribute \src "libresoc.v:173609.5-173609.29" switch \initial - attribute \src "libresoc.v:173610.9-173610.17" + attribute \src "libresoc.v:173609.9-173609.17" case 1'1 case end @@ -356228,14 +353038,14 @@ module \pipe_middle_0 sync always update \ra$47$next $0\ra$47$next[63:0]$10162 end - attribute \src "libresoc.v:173624.3-173638.6" - process $proc$libresoc.v:173624$10165 + attribute \src "libresoc.v:173623.3-173637.6" + process $proc$libresoc.v:173623$10165 assign { } { } assign { } { } assign $0\rb$48$next[63:0]$10166 $1\rb$48$next[63:0]$10167 - attribute \src "libresoc.v:173625.5-173625.29" + attribute \src "libresoc.v:173624.5-173624.29" switch \initial - attribute \src "libresoc.v:173625.9-173625.17" + attribute \src "libresoc.v:173624.9-173624.17" case 1'1 case end @@ -356260,14 +353070,14 @@ module \pipe_middle_0 sync always update \rb$48$next $0\rb$48$next[63:0]$10166 end - attribute \src "libresoc.v:173639.3-173653.6" - process $proc$libresoc.v:173639$10169 + attribute \src "libresoc.v:173638.3-173652.6" + process $proc$libresoc.v:173638$10169 assign { } { } assign { } { } assign $0\xer_so$49$next[0:0]$10170 $1\xer_so$49$next[0:0]$10171 - attribute \src "libresoc.v:173640.5-173640.29" + attribute \src "libresoc.v:173639.5-173639.29" switch \initial - attribute \src "libresoc.v:173640.9-173640.17" + attribute \src "libresoc.v:173639.9-173639.17" case 1'1 case end @@ -356292,14 +353102,14 @@ module \pipe_middle_0 sync always update \xer_so$49$next $0\xer_so$49$next[0:0]$10170 end - attribute \src "libresoc.v:173654.3-173668.6" - process $proc$libresoc.v:173654$10173 + attribute \src "libresoc.v:173653.3-173667.6" + process $proc$libresoc.v:173653$10173 assign { } { } assign { } { } assign $0\divisor_neg$50$next[0:0]$10174 $1\divisor_neg$50$next[0:0]$10175 - attribute \src "libresoc.v:173655.5-173655.29" + attribute \src "libresoc.v:173654.5-173654.29" switch \initial - attribute \src "libresoc.v:173655.9-173655.17" + attribute \src "libresoc.v:173654.9-173654.17" case 1'1 case end @@ -356324,14 +353134,14 @@ module \pipe_middle_0 sync always update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10174 end - attribute \src "libresoc.v:173669.3-173683.6" - process $proc$libresoc.v:173669$10177 + attribute \src "libresoc.v:173668.3-173682.6" + process $proc$libresoc.v:173668$10177 assign { } { } assign { } { } assign $0\dividend_neg$51$next[0:0]$10178 $1\dividend_neg$51$next[0:0]$10179 - attribute \src "libresoc.v:173670.5-173670.29" + attribute \src "libresoc.v:173669.5-173669.29" switch \initial - attribute \src "libresoc.v:173670.9-173670.17" + attribute \src "libresoc.v:173669.9-173669.17" case 1'1 case end @@ -356356,14 +353166,14 @@ module \pipe_middle_0 sync always update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10178 end - attribute \src "libresoc.v:173684.3-173698.6" - process $proc$libresoc.v:173684$10181 + attribute \src "libresoc.v:173683.3-173697.6" + process $proc$libresoc.v:173683$10181 assign { } { } assign { } { } assign $0\dive_abs_ov32$52$next[0:0]$10182 $1\dive_abs_ov32$52$next[0:0]$10183 - attribute \src "libresoc.v:173685.5-173685.29" + attribute \src "libresoc.v:173684.5-173684.29" switch \initial - attribute \src "libresoc.v:173685.9-173685.17" + attribute \src "libresoc.v:173684.9-173684.17" case 1'1 case end @@ -356388,14 +353198,14 @@ module \pipe_middle_0 sync always update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10182 end - attribute \src "libresoc.v:173699.3-173713.6" - process $proc$libresoc.v:173699$10185 + attribute \src "libresoc.v:173698.3-173712.6" + process $proc$libresoc.v:173698$10185 assign { } { } assign { } { } assign $0\dive_abs_ov64$53$next[0:0]$10186 $1\dive_abs_ov64$53$next[0:0]$10187 - attribute \src "libresoc.v:173700.5-173700.29" + attribute \src "libresoc.v:173699.5-173699.29" switch \initial - attribute \src "libresoc.v:173700.9-173700.17" + attribute \src "libresoc.v:173699.9-173699.17" case 1'1 case end @@ -356420,14 +353230,14 @@ module \pipe_middle_0 sync always update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10186 end - attribute \src "libresoc.v:173714.3-173728.6" - process $proc$libresoc.v:173714$10189 + attribute \src "libresoc.v:173713.3-173727.6" + process $proc$libresoc.v:173713$10189 assign { } { } assign { } { } assign $0\div_by_zero$54$next[0:0]$10190 $1\div_by_zero$54$next[0:0]$10191 - attribute \src "libresoc.v:173715.5-173715.29" + attribute \src "libresoc.v:173714.5-173714.29" switch \initial - attribute \src "libresoc.v:173715.9-173715.17" + attribute \src "libresoc.v:173714.9-173714.17" case 1'1 case end @@ -356452,14 +353262,14 @@ module \pipe_middle_0 sync always update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10190 end - attribute \src "libresoc.v:173729.3-173743.6" - process $proc$libresoc.v:173729$10193 + attribute \src "libresoc.v:173728.3-173742.6" + process $proc$libresoc.v:173728$10193 assign { } { } assign { } { } assign $0\dividend$68$next[127:0]$10194 $1\dividend$68$next[127:0]$10195 - attribute \src "libresoc.v:173730.5-173730.29" + attribute \src "libresoc.v:173729.5-173729.29" switch \initial - attribute \src "libresoc.v:173730.9-173730.17" + attribute \src "libresoc.v:173729.9-173729.17" case 1'1 case end @@ -356484,14 +353294,14 @@ module \pipe_middle_0 sync always update \dividend$68$next $0\dividend$68$next[127:0]$10194 end - attribute \src "libresoc.v:173744.3-173758.6" - process $proc$libresoc.v:173744$10197 + attribute \src "libresoc.v:173743.3-173757.6" + process $proc$libresoc.v:173743$10197 assign { } { } assign { } { } assign $0\divisor_radicand$65$next[63:0]$10198 $1\divisor_radicand$65$next[63:0]$10199 - attribute \src "libresoc.v:173745.5-173745.29" + attribute \src "libresoc.v:173744.5-173744.29" switch \initial - attribute \src "libresoc.v:173745.9-173745.17" + attribute \src "libresoc.v:173744.9-173744.17" case 1'1 case end @@ -356516,14 +353326,14 @@ module \pipe_middle_0 sync always update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10198 end - attribute \src "libresoc.v:173759.3-173773.6" - process $proc$libresoc.v:173759$10201 + attribute \src "libresoc.v:173758.3-173772.6" + process $proc$libresoc.v:173758$10201 assign { } { } assign { } { } assign $0\operation$69$next[1:0]$10202 $1\operation$69$next[1:0]$10203 - attribute \src "libresoc.v:173760.5-173760.29" + attribute \src "libresoc.v:173759.5-173759.29" switch \initial - attribute \src "libresoc.v:173760.9-173760.17" + attribute \src "libresoc.v:173759.9-173759.17" case 1'1 case end @@ -356548,12 +353358,12 @@ module \pipe_middle_0 sync always update \operation$69$next $0\operation$69$next[1:0]$10202 end - connect \$56 $sshl$libresoc.v:173376$10011_Y - connect \$55 $pos$libresoc.v:173377$10013_Y - connect \$59 $not$libresoc.v:173378$10014_Y - connect \$61 $ge$libresoc.v:173379$10015_Y - connect \$63 $and$libresoc.v:173380$10016_Y - connect \$66 $and$libresoc.v:173381$10017_Y + connect \$56 $sshl$libresoc.v:173375$10011_Y + connect \$55 $pos$libresoc.v:173376$10013_Y + connect \$59 $not$libresoc.v:173377$10014_Y + connect \$61 $ge$libresoc.v:173378$10015_Y + connect \$63 $and$libresoc.v:173379$10016_Y + connect \$66 $and$libresoc.v:173380$10017_Y connect \p_ready_o \empty connect \n_valid_o \$63 connect \remainder \$55 @@ -356570,277 +353380,277 @@ module \pipe_middle_0 connect \muxid$1 \muxid$28 connect \div_state_init_dividend \dividend end -attribute \src "libresoc.v:173793.1-175338.10" +attribute \src "libresoc.v:173792.1-175337.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" attribute \generator "nMigen" module \pipe_start - attribute \src "libresoc.v:175144.3-175156.6" + attribute \src "libresoc.v:175143.3-175155.6" wire $0\div_by_zero$next[0:0]$10314 - attribute \src "libresoc.v:174930.3-174931.39" + attribute \src "libresoc.v:174929.3-174930.39" wire $0\div_by_zero[0:0] - attribute \src "libresoc.v:175118.3-175130.6" + attribute \src "libresoc.v:175117.3-175129.6" wire $0\dive_abs_ov32$next[0:0]$10308 - attribute \src "libresoc.v:174934.3-174935.43" + attribute \src "libresoc.v:174933.3-174934.43" wire $0\dive_abs_ov32[0:0] - attribute \src "libresoc.v:175131.3-175143.6" + attribute \src "libresoc.v:175130.3-175142.6" wire $0\dive_abs_ov64$next[0:0]$10311 - attribute \src "libresoc.v:174932.3-174933.43" + attribute \src "libresoc.v:174931.3-174932.43" wire $0\dive_abs_ov64[0:0] - attribute \src "libresoc.v:175157.3-175169.6" + attribute \src "libresoc.v:175156.3-175168.6" wire width 128 $0\dividend$next[127:0]$10317 - attribute \src "libresoc.v:174928.3-174929.33" + attribute \src "libresoc.v:174927.3-174928.33" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:175105.3-175117.6" + attribute \src "libresoc.v:175104.3-175116.6" wire $0\dividend_neg$next[0:0]$10305 - attribute \src "libresoc.v:174936.3-174937.41" + attribute \src "libresoc.v:174935.3-174936.41" wire $0\dividend_neg[0:0] - attribute \src "libresoc.v:175092.3-175104.6" + attribute \src "libresoc.v:175091.3-175103.6" wire $0\divisor_neg$next[0:0]$10302 - attribute \src "libresoc.v:174938.3-174939.39" + attribute \src "libresoc.v:174937.3-174938.39" wire $0\divisor_neg[0:0] - attribute \src "libresoc.v:175170.3-175182.6" + attribute \src "libresoc.v:175169.3-175181.6" wire width 64 $0\divisor_radicand$next[63:0]$10320 - attribute \src "libresoc.v:174926.3-174927.49" + attribute \src "libresoc.v:174925.3-174926.49" wire width 64 $0\divisor_radicand[63:0] - attribute \src "libresoc.v:173794.7-173794.20" + attribute \src "libresoc.v:173793.7-173793.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire width 4 $0\logical_op__data_len$next[3:0]$10333 - attribute \src "libresoc.v:174978.3-174979.57" + attribute \src "libresoc.v:174977.3-174978.57" wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire width 14 $0\logical_op__fn_unit$next[13:0]$10334 - attribute \src "libresoc.v:174948.3-174949.55" + attribute \src "libresoc.v:174947.3-174948.55" wire width 14 $0\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire width 64 $0\logical_op__imm_data__data$next[63:0]$10335 - attribute \src "libresoc.v:174950.3-174951.69" + attribute \src "libresoc.v:174949.3-174950.69" wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $0\logical_op__imm_data__ok$next[0:0]$10336 - attribute \src "libresoc.v:174952.3-174953.65" + attribute \src "libresoc.v:174951.3-174952.65" wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire width 2 $0\logical_op__input_carry$next[1:0]$10337 - attribute \src "libresoc.v:174966.3-174967.63" + attribute \src "libresoc.v:174965.3-174966.63" wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire width 32 $0\logical_op__insn$next[31:0]$10338 - attribute \src "libresoc.v:174980.3-174981.49" + attribute \src "libresoc.v:174979.3-174980.49" wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire width 7 $0\logical_op__insn_type$next[6:0]$10339 - attribute \src "libresoc.v:174946.3-174947.59" + attribute \src "libresoc.v:174945.3-174946.59" wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $0\logical_op__invert_in$next[0:0]$10340 - attribute \src "libresoc.v:174962.3-174963.59" + attribute \src "libresoc.v:174961.3-174962.59" wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $0\logical_op__invert_out$next[0:0]$10341 - attribute \src "libresoc.v:174968.3-174969.61" + attribute \src "libresoc.v:174967.3-174968.61" wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $0\logical_op__is_32bit$next[0:0]$10342 - attribute \src "libresoc.v:174974.3-174975.57" + attribute \src "libresoc.v:174973.3-174974.57" wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $0\logical_op__is_signed$next[0:0]$10343 - attribute \src "libresoc.v:174976.3-174977.59" + attribute \src "libresoc.v:174975.3-174976.59" wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $0\logical_op__oe__oe$next[0:0]$10344 - attribute \src "libresoc.v:174958.3-174959.53" + attribute \src "libresoc.v:174957.3-174958.53" wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $0\logical_op__oe__ok$next[0:0]$10345 - attribute \src "libresoc.v:174960.3-174961.53" + attribute \src "libresoc.v:174959.3-174960.53" wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $0\logical_op__output_carry$next[0:0]$10346 - attribute \src "libresoc.v:174972.3-174973.65" + attribute \src "libresoc.v:174971.3-174972.65" wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $0\logical_op__rc__ok$next[0:0]$10347 - attribute \src "libresoc.v:174956.3-174957.53" + attribute \src "libresoc.v:174955.3-174956.53" wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $0\logical_op__rc__rc$next[0:0]$10348 - attribute \src "libresoc.v:174954.3-174955.53" + attribute \src "libresoc.v:174953.3-174954.53" wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $0\logical_op__write_cr0$next[0:0]$10349 - attribute \src "libresoc.v:174970.3-174971.59" + attribute \src "libresoc.v:174969.3-174970.59" wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $0\logical_op__zero_a$next[0:0]$10350 - attribute \src "libresoc.v:174964.3-174965.53" + attribute \src "libresoc.v:174963.3-174964.53" wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:175214.3-175226.6" + attribute \src "libresoc.v:175213.3-175225.6" wire width 2 $0\muxid$next[1:0]$10330 - attribute \src "libresoc.v:174982.3-174983.27" + attribute \src "libresoc.v:174981.3-174982.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:175183.3-175195.6" + attribute \src "libresoc.v:175182.3-175194.6" wire width 2 $0\operation$next[1:0]$10323 - attribute \src "libresoc.v:174924.3-174925.35" + attribute \src "libresoc.v:174923.3-174924.35" wire width 2 $0\operation[1:0] - attribute \src "libresoc.v:175196.3-175213.6" + attribute \src "libresoc.v:175195.3-175212.6" wire $0\r_busy$next[0:0]$10326 - attribute \src "libresoc.v:174984.3-174985.29" + attribute \src "libresoc.v:174983.3-174984.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:175269.3-175281.6" + attribute \src "libresoc.v:175268.3-175280.6" wire width 64 $0\ra$next[63:0]$10376 - attribute \src "libresoc.v:174944.3-174945.21" + attribute \src "libresoc.v:174943.3-174944.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:175282.3-175294.6" + attribute \src "libresoc.v:175281.3-175293.6" wire width 64 $0\rb$next[63:0]$10379 - attribute \src "libresoc.v:174942.3-174943.21" + attribute \src "libresoc.v:174941.3-174942.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:175295.3-175307.6" + attribute \src "libresoc.v:175294.3-175306.6" wire $0\xer_so$next[0:0]$10382 - attribute \src "libresoc.v:174940.3-174941.29" + attribute \src "libresoc.v:174939.3-174940.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:175144.3-175156.6" + attribute \src "libresoc.v:175143.3-175155.6" wire $1\div_by_zero$next[0:0]$10315 - attribute \src "libresoc.v:173803.7-173803.25" + attribute \src "libresoc.v:173802.7-173802.25" wire $1\div_by_zero[0:0] - attribute \src "libresoc.v:175118.3-175130.6" + attribute \src "libresoc.v:175117.3-175129.6" wire $1\dive_abs_ov32$next[0:0]$10309 - attribute \src "libresoc.v:173810.7-173810.27" + attribute \src "libresoc.v:173809.7-173809.27" wire $1\dive_abs_ov32[0:0] - attribute \src "libresoc.v:175131.3-175143.6" + attribute \src "libresoc.v:175130.3-175142.6" wire $1\dive_abs_ov64$next[0:0]$10312 - attribute \src "libresoc.v:173817.7-173817.27" + attribute \src "libresoc.v:173816.7-173816.27" wire $1\dive_abs_ov64[0:0] - attribute \src "libresoc.v:175157.3-175169.6" + attribute \src "libresoc.v:175156.3-175168.6" wire width 128 $1\dividend$next[127:0]$10318 - attribute \src "libresoc.v:173824.15-173824.63" + attribute \src "libresoc.v:173823.15-173823.63" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:175105.3-175117.6" + attribute \src "libresoc.v:175104.3-175116.6" wire $1\dividend_neg$next[0:0]$10306 - attribute \src "libresoc.v:173831.7-173831.26" + attribute \src "libresoc.v:173830.7-173830.26" wire $1\dividend_neg[0:0] - attribute \src "libresoc.v:175092.3-175104.6" + attribute \src "libresoc.v:175091.3-175103.6" wire $1\divisor_neg$next[0:0]$10303 - attribute \src "libresoc.v:173838.7-173838.25" + attribute \src "libresoc.v:173837.7-173837.25" wire $1\divisor_neg[0:0] - attribute \src "libresoc.v:175170.3-175182.6" + attribute \src "libresoc.v:175169.3-175181.6" wire width 64 $1\divisor_radicand$next[63:0]$10321 - attribute \src "libresoc.v:173845.14-173845.53" + attribute \src "libresoc.v:173844.14-173844.53" wire width 64 $1\divisor_radicand[63:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire width 4 $1\logical_op__data_len$next[3:0]$10351 - attribute \src "libresoc.v:174128.13-174128.40" + attribute \src "libresoc.v:174127.13-174127.40" wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire width 14 $1\logical_op__fn_unit$next[13:0]$10352 - attribute \src "libresoc.v:174152.14-174152.44" + attribute \src "libresoc.v:174151.14-174151.44" wire width 14 $1\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire width 64 $1\logical_op__imm_data__data$next[63:0]$10353 - attribute \src "libresoc.v:174191.14-174191.63" + attribute \src "libresoc.v:174190.14-174190.63" wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $1\logical_op__imm_data__ok$next[0:0]$10354 - attribute \src "libresoc.v:174200.7-174200.38" + attribute \src "libresoc.v:174199.7-174199.38" wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire width 2 $1\logical_op__input_carry$next[1:0]$10355 - attribute \src "libresoc.v:174213.13-174213.43" + attribute \src "libresoc.v:174212.13-174212.43" wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire width 32 $1\logical_op__insn$next[31:0]$10356 - attribute \src "libresoc.v:174230.14-174230.38" + attribute \src "libresoc.v:174229.14-174229.38" wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire width 7 $1\logical_op__insn_type$next[6:0]$10357 - attribute \src "libresoc.v:174314.13-174314.42" + attribute \src "libresoc.v:174313.13-174313.42" wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $1\logical_op__invert_in$next[0:0]$10358 - attribute \src "libresoc.v:174473.7-174473.35" + attribute \src "libresoc.v:174472.7-174472.35" wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $1\logical_op__invert_out$next[0:0]$10359 - attribute \src "libresoc.v:174482.7-174482.36" + attribute \src "libresoc.v:174481.7-174481.36" wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $1\logical_op__is_32bit$next[0:0]$10360 - attribute \src "libresoc.v:174491.7-174491.34" + attribute \src "libresoc.v:174490.7-174490.34" wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $1\logical_op__is_signed$next[0:0]$10361 - attribute \src "libresoc.v:174500.7-174500.35" + attribute \src "libresoc.v:174499.7-174499.35" wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $1\logical_op__oe__oe$next[0:0]$10362 - attribute \src "libresoc.v:174509.7-174509.32" + attribute \src "libresoc.v:174508.7-174508.32" wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $1\logical_op__oe__ok$next[0:0]$10363 - attribute \src "libresoc.v:174518.7-174518.32" + attribute \src "libresoc.v:174517.7-174517.32" wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $1\logical_op__output_carry$next[0:0]$10364 - attribute \src "libresoc.v:174527.7-174527.38" + attribute \src "libresoc.v:174526.7-174526.38" wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $1\logical_op__rc__ok$next[0:0]$10365 - attribute \src "libresoc.v:174536.7-174536.32" + attribute \src "libresoc.v:174535.7-174535.32" wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $1\logical_op__rc__rc$next[0:0]$10366 - attribute \src "libresoc.v:174545.7-174545.32" + attribute \src "libresoc.v:174544.7-174544.32" wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $1\logical_op__write_cr0$next[0:0]$10367 - attribute \src "libresoc.v:174554.7-174554.35" + attribute \src "libresoc.v:174553.7-174553.35" wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $1\logical_op__zero_a$next[0:0]$10368 - attribute \src "libresoc.v:174563.7-174563.32" + attribute \src "libresoc.v:174562.7-174562.32" wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:175214.3-175226.6" + attribute \src "libresoc.v:175213.3-175225.6" wire width 2 $1\muxid$next[1:0]$10331 - attribute \src "libresoc.v:174572.13-174572.25" + attribute \src "libresoc.v:174571.13-174571.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:175183.3-175195.6" + attribute \src "libresoc.v:175182.3-175194.6" wire width 2 $1\operation$next[1:0]$10324 - attribute \src "libresoc.v:174587.13-174587.29" + attribute \src "libresoc.v:174586.13-174586.29" wire width 2 $1\operation[1:0] - attribute \src "libresoc.v:175196.3-175213.6" + attribute \src "libresoc.v:175195.3-175212.6" wire $1\r_busy$next[0:0]$10327 - attribute \src "libresoc.v:174601.7-174601.20" + attribute \src "libresoc.v:174600.7-174600.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:175269.3-175281.6" + attribute \src "libresoc.v:175268.3-175280.6" wire width 64 $1\ra$next[63:0]$10377 - attribute \src "libresoc.v:174606.14-174606.39" + attribute \src "libresoc.v:174605.14-174605.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:175282.3-175294.6" + attribute \src "libresoc.v:175281.3-175293.6" wire width 64 $1\rb$next[63:0]$10380 - attribute \src "libresoc.v:174617.14-174617.39" + attribute \src "libresoc.v:174616.14-174616.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:175295.3-175307.6" + attribute \src "libresoc.v:175294.3-175306.6" wire $1\xer_so$next[0:0]$10383 - attribute \src "libresoc.v:174916.7-174916.20" + attribute \src "libresoc.v:174915.7-174915.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire width 64 $2\logical_op__imm_data__data$next[63:0]$10369 - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $2\logical_op__imm_data__ok$next[0:0]$10370 - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $2\logical_op__oe__oe$next[0:0]$10371 - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $2\logical_op__oe__ok$next[0:0]$10372 - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $2\logical_op__rc__ok$next[0:0]$10373 - attribute \src "libresoc.v:175227.3-175268.6" + attribute \src "libresoc.v:175226.3-175267.6" wire $2\logical_op__rc__rc$next[0:0]$10374 - attribute \src "libresoc.v:175196.3-175213.6" + attribute \src "libresoc.v:175195.3-175212.6" wire $2\r_busy$next[0:0]$10328 - attribute \src "libresoc.v:174923.18-174923.118" - wire $and$libresoc.v:174923$10269_Y + attribute \src "libresoc.v:174922.18-174922.118" + wire $and$libresoc.v:174922$10269_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$66 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" @@ -356889,7 +353699,7 @@ module \pipe_start wire width 64 \divisor_radicand$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \divisor_radicand$next - attribute \src "libresoc.v:173794.7-173794.15" + attribute \src "libresoc.v:173793.7-173793.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len @@ -357942,7 +354752,7 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:174923$10269 + cell $and $and$libresoc.v:174922$10269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -357950,10 +354760,10 @@ module \pipe_start parameter \Y_WIDTH 1 connect \A \p_valid_i$65 connect \B \p_ready_o - connect \Y $and$libresoc.v:174923$10269_Y + connect \Y $and$libresoc.v:174922$10269_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:174986.14-175031.4" + attribute \src "libresoc.v:174985.14-175030.4" cell \input$78 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$40 @@ -358001,19 +354811,19 @@ module \pipe_start connect \xer_so$22 \input_xer_so$44 end attribute \module_not_derived 1 - attribute \src "libresoc.v:175032.10-175035.4" + attribute \src "libresoc.v:175031.10-175034.4" cell \n$77 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:175036.10-175039.4" + attribute \src "libresoc.v:175035.10-175038.4" cell \p$76 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:175040.15-175091.4" + attribute \src "libresoc.v:175039.15-175090.4" cell \setup_stage \setup_stage connect \div_by_zero \setup_stage_div_by_zero connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 @@ -358066,487 +354876,487 @@ module \pipe_start connect \xer_so \setup_stage_xer_so connect \xer_so$20 \setup_stage_xer_so$64 end - attribute \src "libresoc.v:173794.7-173794.20" - process $proc$libresoc.v:173794$10384 + attribute \src "libresoc.v:173793.7-173793.20" + process $proc$libresoc.v:173793$10384 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173803.7-173803.25" - process $proc$libresoc.v:173803$10385 + attribute \src "libresoc.v:173802.7-173802.25" + process $proc$libresoc.v:173802$10385 assign { } { } assign $1\div_by_zero[0:0] 1'0 sync always sync init update \div_by_zero $1\div_by_zero[0:0] end - attribute \src "libresoc.v:173810.7-173810.27" - process $proc$libresoc.v:173810$10386 + attribute \src "libresoc.v:173809.7-173809.27" + process $proc$libresoc.v:173809$10386 assign { } { } assign $1\dive_abs_ov32[0:0] 1'0 sync always sync init update \dive_abs_ov32 $1\dive_abs_ov32[0:0] end - attribute \src "libresoc.v:173817.7-173817.27" - process $proc$libresoc.v:173817$10387 + attribute \src "libresoc.v:173816.7-173816.27" + process $proc$libresoc.v:173816$10387 assign { } { } assign $1\dive_abs_ov64[0:0] 1'0 sync always sync init update \dive_abs_ov64 $1\dive_abs_ov64[0:0] end - attribute \src "libresoc.v:173824.15-173824.63" - process $proc$libresoc.v:173824$10388 + attribute \src "libresoc.v:173823.15-173823.63" + process $proc$libresoc.v:173823$10388 assign { } { } assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dividend $1\dividend[127:0] end - attribute \src "libresoc.v:173831.7-173831.26" - process $proc$libresoc.v:173831$10389 + attribute \src "libresoc.v:173830.7-173830.26" + process $proc$libresoc.v:173830$10389 assign { } { } assign $1\dividend_neg[0:0] 1'0 sync always sync init update \dividend_neg $1\dividend_neg[0:0] end - attribute \src "libresoc.v:173838.7-173838.25" - process $proc$libresoc.v:173838$10390 + attribute \src "libresoc.v:173837.7-173837.25" + process $proc$libresoc.v:173837$10390 assign { } { } assign $1\divisor_neg[0:0] 1'0 sync always sync init update \divisor_neg $1\divisor_neg[0:0] end - attribute \src "libresoc.v:173845.14-173845.53" - process $proc$libresoc.v:173845$10391 + attribute \src "libresoc.v:173844.14-173844.53" + process $proc$libresoc.v:173844$10391 assign { } { } assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \divisor_radicand $1\divisor_radicand[63:0] end - attribute \src "libresoc.v:174128.13-174128.40" - process $proc$libresoc.v:174128$10392 + attribute \src "libresoc.v:174127.13-174127.40" + process $proc$libresoc.v:174127$10392 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:174152.14-174152.44" - process $proc$libresoc.v:174152$10393 + attribute \src "libresoc.v:174151.14-174151.44" + process $proc$libresoc.v:174151$10393 assign { } { } assign $1\logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:174191.14-174191.63" - process $proc$libresoc.v:174191$10394 + attribute \src "libresoc.v:174190.14-174190.63" + process $proc$libresoc.v:174190$10394 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:174200.7-174200.38" - process $proc$libresoc.v:174200$10395 + attribute \src "libresoc.v:174199.7-174199.38" + process $proc$libresoc.v:174199$10395 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:174213.13-174213.43" - process $proc$libresoc.v:174213$10396 + attribute \src "libresoc.v:174212.13-174212.43" + process $proc$libresoc.v:174212$10396 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:174230.14-174230.38" - process $proc$libresoc.v:174230$10397 + attribute \src "libresoc.v:174229.14-174229.38" + process $proc$libresoc.v:174229$10397 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:174314.13-174314.42" - process $proc$libresoc.v:174314$10398 + attribute \src "libresoc.v:174313.13-174313.42" + process $proc$libresoc.v:174313$10398 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:174473.7-174473.35" - process $proc$libresoc.v:174473$10399 + attribute \src "libresoc.v:174472.7-174472.35" + process $proc$libresoc.v:174472$10399 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:174482.7-174482.36" - process $proc$libresoc.v:174482$10400 + attribute \src "libresoc.v:174481.7-174481.36" + process $proc$libresoc.v:174481$10400 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:174491.7-174491.34" - process $proc$libresoc.v:174491$10401 + attribute \src "libresoc.v:174490.7-174490.34" + process $proc$libresoc.v:174490$10401 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:174500.7-174500.35" - process $proc$libresoc.v:174500$10402 + attribute \src "libresoc.v:174499.7-174499.35" + process $proc$libresoc.v:174499$10402 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:174509.7-174509.32" - process $proc$libresoc.v:174509$10403 + attribute \src "libresoc.v:174508.7-174508.32" + process $proc$libresoc.v:174508$10403 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:174518.7-174518.32" - process $proc$libresoc.v:174518$10404 + attribute \src "libresoc.v:174517.7-174517.32" + process $proc$libresoc.v:174517$10404 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:174527.7-174527.38" - process $proc$libresoc.v:174527$10405 + attribute \src "libresoc.v:174526.7-174526.38" + process $proc$libresoc.v:174526$10405 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:174536.7-174536.32" - process $proc$libresoc.v:174536$10406 + attribute \src "libresoc.v:174535.7-174535.32" + process $proc$libresoc.v:174535$10406 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:174545.7-174545.32" - process $proc$libresoc.v:174545$10407 + attribute \src "libresoc.v:174544.7-174544.32" + process $proc$libresoc.v:174544$10407 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:174554.7-174554.35" - process $proc$libresoc.v:174554$10408 + attribute \src "libresoc.v:174553.7-174553.35" + process $proc$libresoc.v:174553$10408 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:174563.7-174563.32" - process $proc$libresoc.v:174563$10409 + attribute \src "libresoc.v:174562.7-174562.32" + process $proc$libresoc.v:174562$10409 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:174572.13-174572.25" - process $proc$libresoc.v:174572$10410 + attribute \src "libresoc.v:174571.13-174571.25" + process $proc$libresoc.v:174571$10410 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:174587.13-174587.29" - process $proc$libresoc.v:174587$10411 + attribute \src "libresoc.v:174586.13-174586.29" + process $proc$libresoc.v:174586$10411 assign { } { } assign $1\operation[1:0] 2'00 sync always sync init update \operation $1\operation[1:0] end - attribute \src "libresoc.v:174601.7-174601.20" - process $proc$libresoc.v:174601$10412 + attribute \src "libresoc.v:174600.7-174600.20" + process $proc$libresoc.v:174600$10412 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:174606.14-174606.39" - process $proc$libresoc.v:174606$10413 + attribute \src "libresoc.v:174605.14-174605.39" + process $proc$libresoc.v:174605$10413 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:174617.14-174617.39" - process $proc$libresoc.v:174617$10414 + attribute \src "libresoc.v:174616.14-174616.39" + process $proc$libresoc.v:174616$10414 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:174916.7-174916.20" - process $proc$libresoc.v:174916$10415 + attribute \src "libresoc.v:174915.7-174915.20" + process $proc$libresoc.v:174915$10415 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:174924.3-174925.35" - process $proc$libresoc.v:174924$10270 + attribute \src "libresoc.v:174923.3-174924.35" + process $proc$libresoc.v:174923$10270 assign { } { } assign $0\operation[1:0] \operation$next sync posedge \coresync_clk update \operation $0\operation[1:0] end - attribute \src "libresoc.v:174926.3-174927.49" - process $proc$libresoc.v:174926$10271 + attribute \src "libresoc.v:174925.3-174926.49" + process $proc$libresoc.v:174925$10271 assign { } { } assign $0\divisor_radicand[63:0] \divisor_radicand$next sync posedge \coresync_clk update \divisor_radicand $0\divisor_radicand[63:0] end - attribute \src "libresoc.v:174928.3-174929.33" - process $proc$libresoc.v:174928$10272 + attribute \src "libresoc.v:174927.3-174928.33" + process $proc$libresoc.v:174927$10272 assign { } { } assign $0\dividend[127:0] \dividend$next sync posedge \coresync_clk update \dividend $0\dividend[127:0] end - attribute \src "libresoc.v:174930.3-174931.39" - process $proc$libresoc.v:174930$10273 + attribute \src "libresoc.v:174929.3-174930.39" + process $proc$libresoc.v:174929$10273 assign { } { } assign $0\div_by_zero[0:0] \div_by_zero$next sync posedge \coresync_clk update \div_by_zero $0\div_by_zero[0:0] end - attribute \src "libresoc.v:174932.3-174933.43" - process $proc$libresoc.v:174932$10274 + attribute \src "libresoc.v:174931.3-174932.43" + process $proc$libresoc.v:174931$10274 assign { } { } assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next sync posedge \coresync_clk update \dive_abs_ov64 $0\dive_abs_ov64[0:0] end - attribute \src "libresoc.v:174934.3-174935.43" - process $proc$libresoc.v:174934$10275 + attribute \src "libresoc.v:174933.3-174934.43" + process $proc$libresoc.v:174933$10275 assign { } { } assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next sync posedge \coresync_clk update \dive_abs_ov32 $0\dive_abs_ov32[0:0] end - attribute \src "libresoc.v:174936.3-174937.41" - process $proc$libresoc.v:174936$10276 + attribute \src "libresoc.v:174935.3-174936.41" + process $proc$libresoc.v:174935$10276 assign { } { } assign $0\dividend_neg[0:0] \dividend_neg$next sync posedge \coresync_clk update \dividend_neg $0\dividend_neg[0:0] end - attribute \src "libresoc.v:174938.3-174939.39" - process $proc$libresoc.v:174938$10277 + attribute \src "libresoc.v:174937.3-174938.39" + process $proc$libresoc.v:174937$10277 assign { } { } assign $0\divisor_neg[0:0] \divisor_neg$next sync posedge \coresync_clk update \divisor_neg $0\divisor_neg[0:0] end - attribute \src "libresoc.v:174940.3-174941.29" - process $proc$libresoc.v:174940$10278 + attribute \src "libresoc.v:174939.3-174940.29" + process $proc$libresoc.v:174939$10278 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:174942.3-174943.21" - process $proc$libresoc.v:174942$10279 + attribute \src "libresoc.v:174941.3-174942.21" + process $proc$libresoc.v:174941$10279 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:174944.3-174945.21" - process $proc$libresoc.v:174944$10280 + attribute \src "libresoc.v:174943.3-174944.21" + process $proc$libresoc.v:174943$10280 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:174946.3-174947.59" - process $proc$libresoc.v:174946$10281 + attribute \src "libresoc.v:174945.3-174946.59" + process $proc$libresoc.v:174945$10281 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:174948.3-174949.55" - process $proc$libresoc.v:174948$10282 + attribute \src "libresoc.v:174947.3-174948.55" + process $proc$libresoc.v:174947$10282 assign { } { } assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next sync posedge \coresync_clk update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:174950.3-174951.69" - process $proc$libresoc.v:174950$10283 + attribute \src "libresoc.v:174949.3-174950.69" + process $proc$libresoc.v:174949$10283 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:174952.3-174953.65" - process $proc$libresoc.v:174952$10284 + attribute \src "libresoc.v:174951.3-174952.65" + process $proc$libresoc.v:174951$10284 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:174954.3-174955.53" - process $proc$libresoc.v:174954$10285 + attribute \src "libresoc.v:174953.3-174954.53" + process $proc$libresoc.v:174953$10285 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:174956.3-174957.53" - process $proc$libresoc.v:174956$10286 + attribute \src "libresoc.v:174955.3-174956.53" + process $proc$libresoc.v:174955$10286 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:174958.3-174959.53" - process $proc$libresoc.v:174958$10287 + attribute \src "libresoc.v:174957.3-174958.53" + process $proc$libresoc.v:174957$10287 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:174960.3-174961.53" - process $proc$libresoc.v:174960$10288 + attribute \src "libresoc.v:174959.3-174960.53" + process $proc$libresoc.v:174959$10288 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:174962.3-174963.59" - process $proc$libresoc.v:174962$10289 + attribute \src "libresoc.v:174961.3-174962.59" + process $proc$libresoc.v:174961$10289 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:174964.3-174965.53" - process $proc$libresoc.v:174964$10290 + attribute \src "libresoc.v:174963.3-174964.53" + process $proc$libresoc.v:174963$10290 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:174966.3-174967.63" - process $proc$libresoc.v:174966$10291 + attribute \src "libresoc.v:174965.3-174966.63" + process $proc$libresoc.v:174965$10291 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:174968.3-174969.61" - process $proc$libresoc.v:174968$10292 + attribute \src "libresoc.v:174967.3-174968.61" + process $proc$libresoc.v:174967$10292 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:174970.3-174971.59" - process $proc$libresoc.v:174970$10293 + attribute \src "libresoc.v:174969.3-174970.59" + process $proc$libresoc.v:174969$10293 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:174972.3-174973.65" - process $proc$libresoc.v:174972$10294 + attribute \src "libresoc.v:174971.3-174972.65" + process $proc$libresoc.v:174971$10294 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:174974.3-174975.57" - process $proc$libresoc.v:174974$10295 + attribute \src "libresoc.v:174973.3-174974.57" + process $proc$libresoc.v:174973$10295 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:174976.3-174977.59" - process $proc$libresoc.v:174976$10296 + attribute \src "libresoc.v:174975.3-174976.59" + process $proc$libresoc.v:174975$10296 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:174978.3-174979.57" - process $proc$libresoc.v:174978$10297 + attribute \src "libresoc.v:174977.3-174978.57" + process $proc$libresoc.v:174977$10297 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:174980.3-174981.49" - process $proc$libresoc.v:174980$10298 + attribute \src "libresoc.v:174979.3-174980.49" + process $proc$libresoc.v:174979$10298 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:174982.3-174983.27" - process $proc$libresoc.v:174982$10299 + attribute \src "libresoc.v:174981.3-174982.27" + process $proc$libresoc.v:174981$10299 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:174984.3-174985.29" - process $proc$libresoc.v:174984$10300 + attribute \src "libresoc.v:174983.3-174984.29" + process $proc$libresoc.v:174983$10300 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:175092.3-175104.6" - process $proc$libresoc.v:175092$10301 + attribute \src "libresoc.v:175091.3-175103.6" + process $proc$libresoc.v:175091$10301 assign { } { } assign { } { } assign $0\divisor_neg$next[0:0]$10302 $1\divisor_neg$next[0:0]$10303 - attribute \src "libresoc.v:175093.5-175093.29" + attribute \src "libresoc.v:175092.5-175092.29" switch \initial - attribute \src "libresoc.v:175093.9-175093.17" + attribute \src "libresoc.v:175092.9-175092.17" case 1'1 case end @@ -358566,14 +355376,14 @@ module \pipe_start sync always update \divisor_neg$next $0\divisor_neg$next[0:0]$10302 end - attribute \src "libresoc.v:175105.3-175117.6" - process $proc$libresoc.v:175105$10304 + attribute \src "libresoc.v:175104.3-175116.6" + process $proc$libresoc.v:175104$10304 assign { } { } assign { } { } assign $0\dividend_neg$next[0:0]$10305 $1\dividend_neg$next[0:0]$10306 - attribute \src "libresoc.v:175106.5-175106.29" + attribute \src "libresoc.v:175105.5-175105.29" switch \initial - attribute \src "libresoc.v:175106.9-175106.17" + attribute \src "libresoc.v:175105.9-175105.17" case 1'1 case end @@ -358593,14 +355403,14 @@ module \pipe_start sync always update \dividend_neg$next $0\dividend_neg$next[0:0]$10305 end - attribute \src "libresoc.v:175118.3-175130.6" - process $proc$libresoc.v:175118$10307 + attribute \src "libresoc.v:175117.3-175129.6" + process $proc$libresoc.v:175117$10307 assign { } { } assign { } { } assign $0\dive_abs_ov32$next[0:0]$10308 $1\dive_abs_ov32$next[0:0]$10309 - attribute \src "libresoc.v:175119.5-175119.29" + attribute \src "libresoc.v:175118.5-175118.29" switch \initial - attribute \src "libresoc.v:175119.9-175119.17" + attribute \src "libresoc.v:175118.9-175118.17" case 1'1 case end @@ -358620,14 +355430,14 @@ module \pipe_start sync always update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10308 end - attribute \src "libresoc.v:175131.3-175143.6" - process $proc$libresoc.v:175131$10310 + attribute \src "libresoc.v:175130.3-175142.6" + process $proc$libresoc.v:175130$10310 assign { } { } assign { } { } assign $0\dive_abs_ov64$next[0:0]$10311 $1\dive_abs_ov64$next[0:0]$10312 - attribute \src "libresoc.v:175132.5-175132.29" + attribute \src "libresoc.v:175131.5-175131.29" switch \initial - attribute \src "libresoc.v:175132.9-175132.17" + attribute \src "libresoc.v:175131.9-175131.17" case 1'1 case end @@ -358647,14 +355457,14 @@ module \pipe_start sync always update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10311 end - attribute \src "libresoc.v:175144.3-175156.6" - process $proc$libresoc.v:175144$10313 + attribute \src "libresoc.v:175143.3-175155.6" + process $proc$libresoc.v:175143$10313 assign { } { } assign { } { } assign $0\div_by_zero$next[0:0]$10314 $1\div_by_zero$next[0:0]$10315 - attribute \src "libresoc.v:175145.5-175145.29" + attribute \src "libresoc.v:175144.5-175144.29" switch \initial - attribute \src "libresoc.v:175145.9-175145.17" + attribute \src "libresoc.v:175144.9-175144.17" case 1'1 case end @@ -358674,14 +355484,14 @@ module \pipe_start sync always update \div_by_zero$next $0\div_by_zero$next[0:0]$10314 end - attribute \src "libresoc.v:175157.3-175169.6" - process $proc$libresoc.v:175157$10316 + attribute \src "libresoc.v:175156.3-175168.6" + process $proc$libresoc.v:175156$10316 assign { } { } assign { } { } assign $0\dividend$next[127:0]$10317 $1\dividend$next[127:0]$10318 - attribute \src "libresoc.v:175158.5-175158.29" + attribute \src "libresoc.v:175157.5-175157.29" switch \initial - attribute \src "libresoc.v:175158.9-175158.17" + attribute \src "libresoc.v:175157.9-175157.17" case 1'1 case end @@ -358701,14 +355511,14 @@ module \pipe_start sync always update \dividend$next $0\dividend$next[127:0]$10317 end - attribute \src "libresoc.v:175170.3-175182.6" - process $proc$libresoc.v:175170$10319 + attribute \src "libresoc.v:175169.3-175181.6" + process $proc$libresoc.v:175169$10319 assign { } { } assign { } { } assign $0\divisor_radicand$next[63:0]$10320 $1\divisor_radicand$next[63:0]$10321 - attribute \src "libresoc.v:175171.5-175171.29" + attribute \src "libresoc.v:175170.5-175170.29" switch \initial - attribute \src "libresoc.v:175171.9-175171.17" + attribute \src "libresoc.v:175170.9-175170.17" case 1'1 case end @@ -358728,14 +355538,14 @@ module \pipe_start sync always update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10320 end - attribute \src "libresoc.v:175183.3-175195.6" - process $proc$libresoc.v:175183$10322 + attribute \src "libresoc.v:175182.3-175194.6" + process $proc$libresoc.v:175182$10322 assign { } { } assign { } { } assign $0\operation$next[1:0]$10323 $1\operation$next[1:0]$10324 - attribute \src "libresoc.v:175184.5-175184.29" + attribute \src "libresoc.v:175183.5-175183.29" switch \initial - attribute \src "libresoc.v:175184.9-175184.17" + attribute \src "libresoc.v:175183.9-175183.17" case 1'1 case end @@ -358755,15 +355565,15 @@ module \pipe_start sync always update \operation$next $0\operation$next[1:0]$10323 end - attribute \src "libresoc.v:175196.3-175213.6" - process $proc$libresoc.v:175196$10325 + attribute \src "libresoc.v:175195.3-175212.6" + process $proc$libresoc.v:175195$10325 assign { } { } assign { } { } assign { } { } assign $0\r_busy$next[0:0]$10326 $2\r_busy$next[0:0]$10328 - attribute \src "libresoc.v:175197.5-175197.29" + attribute \src "libresoc.v:175196.5-175196.29" switch \initial - attribute \src "libresoc.v:175197.9-175197.17" + attribute \src "libresoc.v:175196.9-175196.17" case 1'1 case end @@ -358792,14 +355602,14 @@ module \pipe_start sync always update \r_busy$next $0\r_busy$next[0:0]$10326 end - attribute \src "libresoc.v:175214.3-175226.6" - process $proc$libresoc.v:175214$10329 + attribute \src "libresoc.v:175213.3-175225.6" + process $proc$libresoc.v:175213$10329 assign { } { } assign { } { } assign $0\muxid$next[1:0]$10330 $1\muxid$next[1:0]$10331 - attribute \src "libresoc.v:175215.5-175215.29" + attribute \src "libresoc.v:175214.5-175214.29" switch \initial - attribute \src "libresoc.v:175215.9-175215.17" + attribute \src "libresoc.v:175214.9-175214.17" case 1'1 case end @@ -358819,8 +355629,8 @@ module \pipe_start sync always update \muxid$next $0\muxid$next[1:0]$10330 end - attribute \src "libresoc.v:175227.3-175268.6" - process $proc$libresoc.v:175227$10332 + attribute \src "libresoc.v:175226.3-175267.6" + process $proc$libresoc.v:175226$10332 assign { } { } assign { } { } assign { } { } @@ -358881,9 +355691,9 @@ module \pipe_start assign $0\logical_op__oe__ok$next[0:0]$10345 $2\logical_op__oe__ok$next[0:0]$10372 assign $0\logical_op__rc__ok$next[0:0]$10347 $2\logical_op__rc__ok$next[0:0]$10373 assign $0\logical_op__rc__rc$next[0:0]$10348 $2\logical_op__rc__rc$next[0:0]$10374 - attribute \src "libresoc.v:175228.5-175228.29" + attribute \src "libresoc.v:175227.5-175227.29" switch \initial - attribute \src "libresoc.v:175228.9-175228.17" + attribute \src "libresoc.v:175227.9-175227.17" case 1'1 case end @@ -358995,14 +355805,14 @@ module \pipe_start update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10349 update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10350 end - attribute \src "libresoc.v:175269.3-175281.6" - process $proc$libresoc.v:175269$10375 + attribute \src "libresoc.v:175268.3-175280.6" + process $proc$libresoc.v:175268$10375 assign { } { } assign { } { } assign $0\ra$next[63:0]$10376 $1\ra$next[63:0]$10377 - attribute \src "libresoc.v:175270.5-175270.29" + attribute \src "libresoc.v:175269.5-175269.29" switch \initial - attribute \src "libresoc.v:175270.9-175270.17" + attribute \src "libresoc.v:175269.9-175269.17" case 1'1 case end @@ -359022,14 +355832,14 @@ module \pipe_start sync always update \ra$next $0\ra$next[63:0]$10376 end - attribute \src "libresoc.v:175282.3-175294.6" - process $proc$libresoc.v:175282$10378 + attribute \src "libresoc.v:175281.3-175293.6" + process $proc$libresoc.v:175281$10378 assign { } { } assign { } { } assign $0\rb$next[63:0]$10379 $1\rb$next[63:0]$10380 - attribute \src "libresoc.v:175283.5-175283.29" + attribute \src "libresoc.v:175282.5-175282.29" switch \initial - attribute \src "libresoc.v:175283.9-175283.17" + attribute \src "libresoc.v:175282.9-175282.17" case 1'1 case end @@ -359049,14 +355859,14 @@ module \pipe_start sync always update \rb$next $0\rb$next[63:0]$10379 end - attribute \src "libresoc.v:175295.3-175307.6" - process $proc$libresoc.v:175295$10381 + attribute \src "libresoc.v:175294.3-175306.6" + process $proc$libresoc.v:175294$10381 assign { } { } assign { } { } assign $0\xer_so$next[0:0]$10382 $1\xer_so$next[0:0]$10383 - attribute \src "libresoc.v:175296.5-175296.29" + attribute \src "libresoc.v:175295.5-175295.29" switch \initial - attribute \src "libresoc.v:175296.9-175296.17" + attribute \src "libresoc.v:175295.9-175295.17" case 1'1 case end @@ -359076,7 +355886,7 @@ module \pipe_start sync always update \xer_so$next $0\xer_so$next[0:0]$10382 end - connect \$66 $and$libresoc.v:174923$10269_Y + connect \$66 $and$libresoc.v:174922$10269_Y connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 connect \p_ready_o \n_i_rdy_data @@ -359108,27 +355918,27 @@ module \pipe_start connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:175342.1-175386.10" +attribute \src "libresoc.v:175341.1-175385.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.pll" attribute \generator "nMigen" module \pll - attribute \src "libresoc.v:175343.7-175343.20" + attribute \src "libresoc.v:175342.7-175342.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175375.3-175384.6" + attribute \src "libresoc.v:175374.3-175383.6" wire $0\pll_18_o[0:0] - attribute \src "libresoc.v:175365.3-175374.6" + attribute \src "libresoc.v:175364.3-175373.6" wire $0\pll_lck_o[0:0] - attribute \src "libresoc.v:175375.3-175384.6" + attribute \src "libresoc.v:175374.3-175383.6" wire $1\pll_18_o[0:0] - attribute \src "libresoc.v:175365.3-175374.6" + attribute \src "libresoc.v:175364.3-175373.6" wire $1\pll_lck_o[0:0] + attribute \src "libresoc.v:175361.17-175361.105" + wire $eq$libresoc.v:175361$10416_Y attribute \src "libresoc.v:175362.17-175362.105" - wire $eq$libresoc.v:175362$10416_Y - attribute \src "libresoc.v:175363.17-175363.105" - wire $eq$libresoc.v:175363$10417_Y - attribute \src "libresoc.v:175364.17-175364.98" - wire $not$libresoc.v:175364$10418_Y + wire $eq$libresoc.v:175362$10417_Y + attribute \src "libresoc.v:175363.17-175363.98" + wire $not$libresoc.v:175363$10418_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" @@ -359141,14 +355951,14 @@ module \pll wire output 5 \clk_pll_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" wire width 2 input 3 \clk_sel_i - attribute \src "libresoc.v:175343.7-175343.15" + attribute \src "libresoc.v:175342.7-175342.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" wire output 2 \pll_18_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" wire output 4 \pll_lck_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:175362$10416 + cell $eq $eq$libresoc.v:175361$10416 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -359156,10 +355966,10 @@ module \pll parameter \Y_WIDTH 1 connect \A \clk_sel_i connect \B 2'00 - connect \Y $eq$libresoc.v:175362$10416_Y + connect \Y $eq$libresoc.v:175361$10416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:175363$10417 + cell $eq $eq$libresoc.v:175362$10417 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -359167,32 +355977,32 @@ module \pll parameter \Y_WIDTH 1 connect \A \clk_sel_i connect \B 2'00 - connect \Y $eq$libresoc.v:175363$10417_Y + connect \Y $eq$libresoc.v:175362$10417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" - cell $not $not$libresoc.v:175364$10418 + cell $not $not$libresoc.v:175363$10418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clk_24_i - connect \Y $not$libresoc.v:175364$10418_Y + connect \Y $not$libresoc.v:175363$10418_Y end - attribute \src "libresoc.v:175343.7-175343.20" - process $proc$libresoc.v:175343$10421 + attribute \src "libresoc.v:175342.7-175342.20" + process $proc$libresoc.v:175342$10421 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175365.3-175374.6" - process $proc$libresoc.v:175365$10419 + attribute \src "libresoc.v:175364.3-175373.6" + process $proc$libresoc.v:175364$10419 assign { } { } assign { } { } assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0] - attribute \src "libresoc.v:175366.5-175366.29" + attribute \src "libresoc.v:175365.5-175365.29" switch \initial - attribute \src "libresoc.v:175366.9-175366.17" + attribute \src "libresoc.v:175365.9-175365.17" case 1'1 case end @@ -359208,14 +356018,14 @@ module \pll sync always update \pll_lck_o $0\pll_lck_o[0:0] end - attribute \src "libresoc.v:175375.3-175384.6" - process $proc$libresoc.v:175375$10420 + attribute \src "libresoc.v:175374.3-175383.6" + process $proc$libresoc.v:175374$10420 assign { } { } assign { } { } assign $0\pll_18_o[0:0] $1\pll_18_o[0:0] - attribute \src "libresoc.v:175376.5-175376.29" + attribute \src "libresoc.v:175375.5-175375.29" switch \initial - attribute \src "libresoc.v:175376.9-175376.17" + attribute \src "libresoc.v:175375.9-175375.17" case 1'1 case end @@ -359231,196 +356041,196 @@ module \pll sync always update \pll_18_o $0\pll_18_o[0:0] end - connect \$1 $eq$libresoc.v:175362$10416_Y - connect \$3 $eq$libresoc.v:175363$10417_Y - connect \$5 $not$libresoc.v:175364$10418_Y + connect \$1 $eq$libresoc.v:175361$10416_Y + connect \$3 $eq$libresoc.v:175362$10417_Y + connect \$5 $not$libresoc.v:175363$10418_Y connect \clk_pll_o \clk_24_i end -attribute \src "libresoc.v:175390.1-176032.10" +attribute \src "libresoc.v:175389.1-176031.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" attribute \generator "nMigen" module \popcount - attribute \src "libresoc.v:175391.7-175391.20" + attribute \src "libresoc.v:175390.7-175390.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175879.3-175905.6" + attribute \src "libresoc.v:175878.3-175904.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:175879.3-175905.6" + attribute \src "libresoc.v:175878.3-175904.6" wire width 64 $1\o[63:0] + attribute \src "libresoc.v:175802.19-175802.132" + wire width 4 $add$libresoc.v:175802$10422_Y attribute \src "libresoc.v:175803.19-175803.132" - wire width 4 $add$libresoc.v:175803$10422_Y + wire width 4 $add$libresoc.v:175803$10423_Y attribute \src "libresoc.v:175804.19-175804.132" - wire width 4 $add$libresoc.v:175804$10423_Y + wire width 4 $add$libresoc.v:175804$10424_Y attribute \src "libresoc.v:175805.19-175805.132" - wire width 4 $add$libresoc.v:175805$10424_Y - attribute \src "libresoc.v:175806.19-175806.132" - wire width 4 $add$libresoc.v:175806$10425_Y + wire width 4 $add$libresoc.v:175805$10425_Y + attribute \src "libresoc.v:175806.19-175806.134" + wire width 4 $add$libresoc.v:175806$10426_Y attribute \src "libresoc.v:175807.19-175807.134" - wire width 4 $add$libresoc.v:175807$10426_Y - attribute \src "libresoc.v:175808.19-175808.134" - wire width 4 $add$libresoc.v:175808$10427_Y - attribute \src "libresoc.v:175809.18-175809.125" - wire width 3 $add$libresoc.v:175809$10428_Y + wire width 4 $add$libresoc.v:175807$10427_Y + attribute \src "libresoc.v:175808.18-175808.125" + wire width 3 $add$libresoc.v:175808$10428_Y + attribute \src "libresoc.v:175809.19-175809.134" + wire width 4 $add$libresoc.v:175809$10429_Y attribute \src "libresoc.v:175810.19-175810.134" - wire width 4 $add$libresoc.v:175810$10429_Y + wire width 4 $add$libresoc.v:175810$10430_Y attribute \src "libresoc.v:175811.19-175811.134" - wire width 4 $add$libresoc.v:175811$10430_Y + wire width 4 $add$libresoc.v:175811$10431_Y attribute \src "libresoc.v:175812.19-175812.134" - wire width 4 $add$libresoc.v:175812$10431_Y + wire width 4 $add$libresoc.v:175812$10432_Y attribute \src "libresoc.v:175813.19-175813.134" - wire width 4 $add$libresoc.v:175813$10432_Y + wire width 4 $add$libresoc.v:175813$10433_Y attribute \src "libresoc.v:175814.19-175814.134" - wire width 4 $add$libresoc.v:175814$10433_Y + wire width 4 $add$libresoc.v:175814$10434_Y attribute \src "libresoc.v:175815.19-175815.134" - wire width 4 $add$libresoc.v:175815$10434_Y + wire width 4 $add$libresoc.v:175815$10435_Y attribute \src "libresoc.v:175816.19-175816.134" - wire width 4 $add$libresoc.v:175816$10435_Y + wire width 4 $add$libresoc.v:175816$10436_Y attribute \src "libresoc.v:175817.19-175817.134" - wire width 4 $add$libresoc.v:175817$10436_Y - attribute \src "libresoc.v:175818.19-175818.134" - wire width 4 $add$libresoc.v:175818$10437_Y - attribute \src "libresoc.v:175819.19-175819.132" - wire width 5 $add$libresoc.v:175819$10438_Y - attribute \src "libresoc.v:175820.18-175820.125" - wire width 3 $add$libresoc.v:175820$10439_Y + wire width 4 $add$libresoc.v:175817$10437_Y + attribute \src "libresoc.v:175818.19-175818.132" + wire width 5 $add$libresoc.v:175818$10438_Y + attribute \src "libresoc.v:175819.18-175819.125" + wire width 3 $add$libresoc.v:175819$10439_Y + attribute \src "libresoc.v:175820.19-175820.132" + wire width 5 $add$libresoc.v:175820$10440_Y attribute \src "libresoc.v:175821.19-175821.132" - wire width 5 $add$libresoc.v:175821$10440_Y + wire width 5 $add$libresoc.v:175821$10441_Y attribute \src "libresoc.v:175822.19-175822.132" - wire width 5 $add$libresoc.v:175822$10441_Y + wire width 5 $add$libresoc.v:175822$10442_Y attribute \src "libresoc.v:175823.19-175823.132" - wire width 5 $add$libresoc.v:175823$10442_Y - attribute \src "libresoc.v:175824.19-175824.132" - wire width 5 $add$libresoc.v:175824$10443_Y + wire width 5 $add$libresoc.v:175823$10443_Y + attribute \src "libresoc.v:175824.19-175824.134" + wire width 5 $add$libresoc.v:175824$10444_Y attribute \src "libresoc.v:175825.19-175825.134" - wire width 5 $add$libresoc.v:175825$10444_Y + wire width 5 $add$libresoc.v:175825$10445_Y attribute \src "libresoc.v:175826.19-175826.134" - wire width 5 $add$libresoc.v:175826$10445_Y - attribute \src "libresoc.v:175827.19-175827.134" - wire width 5 $add$libresoc.v:175827$10446_Y + wire width 5 $add$libresoc.v:175826$10446_Y + attribute \src "libresoc.v:175827.19-175827.132" + wire width 6 $add$libresoc.v:175827$10447_Y attribute \src "libresoc.v:175828.19-175828.132" - wire width 6 $add$libresoc.v:175828$10447_Y + wire width 6 $add$libresoc.v:175828$10448_Y attribute \src "libresoc.v:175829.19-175829.132" - wire width 6 $add$libresoc.v:175829$10448_Y - attribute \src "libresoc.v:175830.19-175830.132" - wire width 6 $add$libresoc.v:175830$10449_Y - attribute \src "libresoc.v:175831.18-175831.127" - wire width 3 $add$libresoc.v:175831$10450_Y + wire width 6 $add$libresoc.v:175829$10449_Y + attribute \src "libresoc.v:175830.18-175830.127" + wire width 3 $add$libresoc.v:175830$10450_Y + attribute \src "libresoc.v:175831.19-175831.132" + wire width 6 $add$libresoc.v:175831$10451_Y attribute \src "libresoc.v:175832.19-175832.132" - wire width 6 $add$libresoc.v:175832$10451_Y + wire width 7 $add$libresoc.v:175832$10452_Y attribute \src "libresoc.v:175833.19-175833.132" - wire width 7 $add$libresoc.v:175833$10452_Y + wire width 7 $add$libresoc.v:175833$10453_Y attribute \src "libresoc.v:175834.19-175834.132" - wire width 7 $add$libresoc.v:175834$10453_Y - attribute \src "libresoc.v:175835.19-175835.132" - wire width 8 $add$libresoc.v:175835$10454_Y - attribute \src "libresoc.v:175846.18-175846.127" - wire width 3 $add$libresoc.v:175846$10473_Y + wire width 8 $add$libresoc.v:175834$10454_Y + attribute \src "libresoc.v:175845.18-175845.127" + wire width 3 $add$libresoc.v:175845$10473_Y + attribute \src "libresoc.v:175849.18-175849.127" + wire width 3 $add$libresoc.v:175849$10480_Y attribute \src "libresoc.v:175850.18-175850.127" - wire width 3 $add$libresoc.v:175850$10480_Y - attribute \src "libresoc.v:175851.18-175851.127" - wire width 3 $add$libresoc.v:175851$10481_Y - attribute \src "libresoc.v:175852.17-175852.124" - wire width 3 $add$libresoc.v:175852$10482_Y + wire width 3 $add$libresoc.v:175850$10481_Y + attribute \src "libresoc.v:175851.17-175851.124" + wire width 3 $add$libresoc.v:175851$10482_Y + attribute \src "libresoc.v:175852.18-175852.127" + wire width 3 $add$libresoc.v:175852$10483_Y attribute \src "libresoc.v:175853.18-175853.127" - wire width 3 $add$libresoc.v:175853$10483_Y + wire width 3 $add$libresoc.v:175853$10484_Y attribute \src "libresoc.v:175854.18-175854.127" - wire width 3 $add$libresoc.v:175854$10484_Y + wire width 3 $add$libresoc.v:175854$10485_Y attribute \src "libresoc.v:175855.18-175855.127" - wire width 3 $add$libresoc.v:175855$10485_Y + wire width 3 $add$libresoc.v:175855$10486_Y attribute \src "libresoc.v:175856.18-175856.127" - wire width 3 $add$libresoc.v:175856$10486_Y + wire width 3 $add$libresoc.v:175856$10487_Y attribute \src "libresoc.v:175857.18-175857.127" - wire width 3 $add$libresoc.v:175857$10487_Y + wire width 3 $add$libresoc.v:175857$10488_Y attribute \src "libresoc.v:175858.18-175858.127" - wire width 3 $add$libresoc.v:175858$10488_Y + wire width 3 $add$libresoc.v:175858$10489_Y attribute \src "libresoc.v:175859.18-175859.127" - wire width 3 $add$libresoc.v:175859$10489_Y + wire width 3 $add$libresoc.v:175859$10490_Y attribute \src "libresoc.v:175860.18-175860.127" - wire width 3 $add$libresoc.v:175860$10490_Y + wire width 3 $add$libresoc.v:175860$10491_Y attribute \src "libresoc.v:175861.18-175861.127" - wire width 3 $add$libresoc.v:175861$10491_Y - attribute \src "libresoc.v:175862.18-175862.127" - wire width 3 $add$libresoc.v:175862$10492_Y - attribute \src "libresoc.v:175863.17-175863.124" - wire width 3 $add$libresoc.v:175863$10493_Y + wire width 3 $add$libresoc.v:175861$10492_Y + attribute \src "libresoc.v:175862.17-175862.124" + wire width 3 $add$libresoc.v:175862$10493_Y + attribute \src "libresoc.v:175863.18-175863.127" + wire width 3 $add$libresoc.v:175863$10494_Y attribute \src "libresoc.v:175864.18-175864.127" - wire width 3 $add$libresoc.v:175864$10494_Y + wire width 3 $add$libresoc.v:175864$10495_Y attribute \src "libresoc.v:175865.18-175865.127" - wire width 3 $add$libresoc.v:175865$10495_Y + wire width 3 $add$libresoc.v:175865$10496_Y attribute \src "libresoc.v:175866.18-175866.127" - wire width 3 $add$libresoc.v:175866$10496_Y + wire width 3 $add$libresoc.v:175866$10497_Y attribute \src "libresoc.v:175867.18-175867.127" - wire width 3 $add$libresoc.v:175867$10497_Y + wire width 3 $add$libresoc.v:175867$10498_Y attribute \src "libresoc.v:175868.18-175868.127" - wire width 3 $add$libresoc.v:175868$10498_Y + wire width 3 $add$libresoc.v:175868$10499_Y attribute \src "libresoc.v:175869.18-175869.127" - wire width 3 $add$libresoc.v:175869$10499_Y + wire width 3 $add$libresoc.v:175869$10500_Y attribute \src "libresoc.v:175870.18-175870.127" - wire width 3 $add$libresoc.v:175870$10500_Y + wire width 3 $add$libresoc.v:175870$10501_Y attribute \src "libresoc.v:175871.18-175871.127" - wire width 3 $add$libresoc.v:175871$10501_Y + wire width 3 $add$libresoc.v:175871$10502_Y attribute \src "libresoc.v:175872.18-175872.127" - wire width 3 $add$libresoc.v:175872$10502_Y - attribute \src "libresoc.v:175873.18-175873.127" - wire width 3 $add$libresoc.v:175873$10503_Y - attribute \src "libresoc.v:175874.17-175874.124" - wire width 3 $add$libresoc.v:175874$10504_Y + wire width 3 $add$libresoc.v:175872$10503_Y + attribute \src "libresoc.v:175873.17-175873.124" + wire width 3 $add$libresoc.v:175873$10504_Y + attribute \src "libresoc.v:175874.18-175874.127" + wire width 3 $add$libresoc.v:175874$10505_Y attribute \src "libresoc.v:175875.18-175875.127" - wire width 3 $add$libresoc.v:175875$10505_Y + wire width 3 $add$libresoc.v:175875$10506_Y attribute \src "libresoc.v:175876.18-175876.127" - wire width 3 $add$libresoc.v:175876$10506_Y - attribute \src "libresoc.v:175877.18-175877.127" - wire width 3 $add$libresoc.v:175877$10507_Y - attribute \src "libresoc.v:175878.18-175878.131" - wire width 4 $add$libresoc.v:175878$10508_Y + wire width 3 $add$libresoc.v:175876$10507_Y + attribute \src "libresoc.v:175877.18-175877.131" + wire width 4 $add$libresoc.v:175877$10508_Y + attribute \src "libresoc.v:175835.19-175835.111" + wire $eq$libresoc.v:175835$10455_Y attribute \src "libresoc.v:175836.19-175836.111" - wire $eq$libresoc.v:175836$10455_Y - attribute \src "libresoc.v:175837.19-175837.111" - wire $eq$libresoc.v:175837$10456_Y + wire $eq$libresoc.v:175836$10456_Y + attribute \src "libresoc.v:175837.19-175837.104" + wire width 8 $extend$libresoc.v:175837$10457_Y attribute \src "libresoc.v:175838.19-175838.104" - wire width 8 $extend$libresoc.v:175838$10457_Y + wire width 8 $extend$libresoc.v:175838$10459_Y attribute \src "libresoc.v:175839.19-175839.104" - wire width 8 $extend$libresoc.v:175839$10459_Y + wire width 8 $extend$libresoc.v:175839$10461_Y attribute \src "libresoc.v:175840.19-175840.104" - wire width 8 $extend$libresoc.v:175840$10461_Y + wire width 8 $extend$libresoc.v:175840$10463_Y attribute \src "libresoc.v:175841.19-175841.104" - wire width 8 $extend$libresoc.v:175841$10463_Y + wire width 8 $extend$libresoc.v:175841$10465_Y attribute \src "libresoc.v:175842.19-175842.104" - wire width 8 $extend$libresoc.v:175842$10465_Y + wire width 8 $extend$libresoc.v:175842$10467_Y attribute \src "libresoc.v:175843.19-175843.104" - wire width 8 $extend$libresoc.v:175843$10467_Y + wire width 8 $extend$libresoc.v:175843$10469_Y attribute \src "libresoc.v:175844.19-175844.104" - wire width 8 $extend$libresoc.v:175844$10469_Y - attribute \src "libresoc.v:175845.19-175845.104" - wire width 8 $extend$libresoc.v:175845$10471_Y + wire width 8 $extend$libresoc.v:175844$10471_Y + attribute \src "libresoc.v:175846.19-175846.104" + wire width 32 $extend$libresoc.v:175846$10474_Y attribute \src "libresoc.v:175847.19-175847.104" - wire width 32 $extend$libresoc.v:175847$10474_Y + wire width 32 $extend$libresoc.v:175847$10476_Y attribute \src "libresoc.v:175848.19-175848.104" - wire width 32 $extend$libresoc.v:175848$10476_Y - attribute \src "libresoc.v:175849.19-175849.104" - wire width 64 $extend$libresoc.v:175849$10478_Y + wire width 64 $extend$libresoc.v:175848$10478_Y + attribute \src "libresoc.v:175837.19-175837.104" + wire width 8 $pos$libresoc.v:175837$10458_Y attribute \src "libresoc.v:175838.19-175838.104" - wire width 8 $pos$libresoc.v:175838$10458_Y + wire width 8 $pos$libresoc.v:175838$10460_Y attribute \src "libresoc.v:175839.19-175839.104" - wire width 8 $pos$libresoc.v:175839$10460_Y + wire width 8 $pos$libresoc.v:175839$10462_Y attribute \src "libresoc.v:175840.19-175840.104" - wire width 8 $pos$libresoc.v:175840$10462_Y + wire width 8 $pos$libresoc.v:175840$10464_Y attribute \src "libresoc.v:175841.19-175841.104" - wire width 8 $pos$libresoc.v:175841$10464_Y + wire width 8 $pos$libresoc.v:175841$10466_Y attribute \src "libresoc.v:175842.19-175842.104" - wire width 8 $pos$libresoc.v:175842$10466_Y + wire width 8 $pos$libresoc.v:175842$10468_Y attribute \src "libresoc.v:175843.19-175843.104" - wire width 8 $pos$libresoc.v:175843$10468_Y + wire width 8 $pos$libresoc.v:175843$10470_Y attribute \src "libresoc.v:175844.19-175844.104" - wire width 8 $pos$libresoc.v:175844$10470_Y - attribute \src "libresoc.v:175845.19-175845.104" - wire width 8 $pos$libresoc.v:175845$10472_Y + wire width 8 $pos$libresoc.v:175844$10472_Y + attribute \src "libresoc.v:175846.19-175846.104" + wire width 32 $pos$libresoc.v:175846$10475_Y attribute \src "libresoc.v:175847.19-175847.104" - wire width 32 $pos$libresoc.v:175847$10475_Y + wire width 32 $pos$libresoc.v:175847$10477_Y attribute \src "libresoc.v:175848.19-175848.104" - wire width 32 $pos$libresoc.v:175848$10477_Y - attribute \src "libresoc.v:175849.19-175849.104" - wire width 64 $pos$libresoc.v:175849$10479_Y + wire width 64 $pos$libresoc.v:175848$10479_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" @@ -359703,7 +356513,7 @@ module \popcount wire width 64 input 3 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" wire width 64 input 1 \data_len - attribute \src "libresoc.v:175391.7-175391.15" + attribute \src "libresoc.v:175390.7-175390.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" wire width 64 output 2 \o @@ -359834,7 +356644,7 @@ module \popcount attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 7 \pop_7_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175803$10422 + cell $add $add$libresoc.v:175802$10422 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359842,10 +356652,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_2 } connect \B { 2'00 \pop_2_3 } - connect \Y $add$libresoc.v:175803$10422_Y + connect \Y $add$libresoc.v:175802$10422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175804$10423 + cell $add $add$libresoc.v:175803$10423 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359853,10 +356663,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_4 } connect \B { 2'00 \pop_2_5 } - connect \Y $add$libresoc.v:175804$10423_Y + connect \Y $add$libresoc.v:175803$10423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175805$10424 + cell $add $add$libresoc.v:175804$10424 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359864,10 +356674,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_6 } connect \B { 2'00 \pop_2_7 } - connect \Y $add$libresoc.v:175805$10424_Y + connect \Y $add$libresoc.v:175804$10424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175806$10425 + cell $add $add$libresoc.v:175805$10425 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359875,10 +356685,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_8 } connect \B { 2'00 \pop_2_9 } - connect \Y $add$libresoc.v:175806$10425_Y + connect \Y $add$libresoc.v:175805$10425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175807$10426 + cell $add $add$libresoc.v:175806$10426 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359886,10 +356696,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_10 } connect \B { 2'00 \pop_2_11 } - connect \Y $add$libresoc.v:175807$10426_Y + connect \Y $add$libresoc.v:175806$10426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175808$10427 + cell $add $add$libresoc.v:175807$10427 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359897,10 +356707,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_12 } connect \B { 2'00 \pop_2_13 } - connect \Y $add$libresoc.v:175808$10427_Y + connect \Y $add$libresoc.v:175807$10427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175809$10428 + cell $add $add$libresoc.v:175808$10428 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -359908,10 +356718,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [6] } connect \B { 2'00 \a [7] } - connect \Y $add$libresoc.v:175809$10428_Y + connect \Y $add$libresoc.v:175808$10428_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175810$10429 + cell $add $add$libresoc.v:175809$10429 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359919,10 +356729,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_14 } connect \B { 2'00 \pop_2_15 } - connect \Y $add$libresoc.v:175810$10429_Y + connect \Y $add$libresoc.v:175809$10429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175811$10430 + cell $add $add$libresoc.v:175810$10430 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359930,10 +356740,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_16 } connect \B { 2'00 \pop_2_17 } - connect \Y $add$libresoc.v:175811$10430_Y + connect \Y $add$libresoc.v:175810$10430_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175812$10431 + cell $add $add$libresoc.v:175811$10431 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359941,10 +356751,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_18 } connect \B { 2'00 \pop_2_19 } - connect \Y $add$libresoc.v:175812$10431_Y + connect \Y $add$libresoc.v:175811$10431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175813$10432 + cell $add $add$libresoc.v:175812$10432 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359952,10 +356762,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_20 } connect \B { 2'00 \pop_2_21 } - connect \Y $add$libresoc.v:175813$10432_Y + connect \Y $add$libresoc.v:175812$10432_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175814$10433 + cell $add $add$libresoc.v:175813$10433 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359963,10 +356773,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_22 } connect \B { 2'00 \pop_2_23 } - connect \Y $add$libresoc.v:175814$10433_Y + connect \Y $add$libresoc.v:175813$10433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175815$10434 + cell $add $add$libresoc.v:175814$10434 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359974,10 +356784,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_24 } connect \B { 2'00 \pop_2_25 } - connect \Y $add$libresoc.v:175815$10434_Y + connect \Y $add$libresoc.v:175814$10434_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175816$10435 + cell $add $add$libresoc.v:175815$10435 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359985,10 +356795,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_26 } connect \B { 2'00 \pop_2_27 } - connect \Y $add$libresoc.v:175816$10435_Y + connect \Y $add$libresoc.v:175815$10435_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175817$10436 + cell $add $add$libresoc.v:175816$10436 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -359996,10 +356806,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_28 } connect \B { 2'00 \pop_2_29 } - connect \Y $add$libresoc.v:175817$10436_Y + connect \Y $add$libresoc.v:175816$10436_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175818$10437 + cell $add $add$libresoc.v:175817$10437 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -360007,10 +356817,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_30 } connect \B { 2'00 \pop_2_31 } - connect \Y $add$libresoc.v:175818$10437_Y + connect \Y $add$libresoc.v:175817$10437_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175819$10438 + cell $add $add$libresoc.v:175818$10438 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360018,10 +356828,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_0 } connect \B { 2'00 \pop_3_1 } - connect \Y $add$libresoc.v:175819$10438_Y + connect \Y $add$libresoc.v:175818$10438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175820$10439 + cell $add $add$libresoc.v:175819$10439 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360029,10 +356839,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [8] } connect \B { 2'00 \a [9] } - connect \Y $add$libresoc.v:175820$10439_Y + connect \Y $add$libresoc.v:175819$10439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175821$10440 + cell $add $add$libresoc.v:175820$10440 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360040,10 +356850,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_2 } connect \B { 2'00 \pop_3_3 } - connect \Y $add$libresoc.v:175821$10440_Y + connect \Y $add$libresoc.v:175820$10440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175822$10441 + cell $add $add$libresoc.v:175821$10441 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360051,10 +356861,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_4 } connect \B { 2'00 \pop_3_5 } - connect \Y $add$libresoc.v:175822$10441_Y + connect \Y $add$libresoc.v:175821$10441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175823$10442 + cell $add $add$libresoc.v:175822$10442 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360062,10 +356872,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_6 } connect \B { 2'00 \pop_3_7 } - connect \Y $add$libresoc.v:175823$10442_Y + connect \Y $add$libresoc.v:175822$10442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175824$10443 + cell $add $add$libresoc.v:175823$10443 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360073,10 +356883,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_8 } connect \B { 2'00 \pop_3_9 } - connect \Y $add$libresoc.v:175824$10443_Y + connect \Y $add$libresoc.v:175823$10443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175825$10444 + cell $add $add$libresoc.v:175824$10444 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360084,10 +356894,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_10 } connect \B { 2'00 \pop_3_11 } - connect \Y $add$libresoc.v:175825$10444_Y + connect \Y $add$libresoc.v:175824$10444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175826$10445 + cell $add $add$libresoc.v:175825$10445 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360095,10 +356905,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_12 } connect \B { 2'00 \pop_3_13 } - connect \Y $add$libresoc.v:175826$10445_Y + connect \Y $add$libresoc.v:175825$10445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175827$10446 + cell $add $add$libresoc.v:175826$10446 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -360106,10 +356916,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_14 } connect \B { 2'00 \pop_3_15 } - connect \Y $add$libresoc.v:175827$10446_Y + connect \Y $add$libresoc.v:175826$10446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175828$10447 + cell $add $add$libresoc.v:175827$10447 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -360117,10 +356927,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_0 } connect \B { 2'00 \pop_4_1 } - connect \Y $add$libresoc.v:175828$10447_Y + connect \Y $add$libresoc.v:175827$10447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175829$10448 + cell $add $add$libresoc.v:175828$10448 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -360128,10 +356938,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_2 } connect \B { 2'00 \pop_4_3 } - connect \Y $add$libresoc.v:175829$10448_Y + connect \Y $add$libresoc.v:175828$10448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175830$10449 + cell $add $add$libresoc.v:175829$10449 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -360139,10 +356949,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_4 } connect \B { 2'00 \pop_4_5 } - connect \Y $add$libresoc.v:175830$10449_Y + connect \Y $add$libresoc.v:175829$10449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175831$10450 + cell $add $add$libresoc.v:175830$10450 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360150,10 +356960,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [10] } connect \B { 2'00 \a [11] } - connect \Y $add$libresoc.v:175831$10450_Y + connect \Y $add$libresoc.v:175830$10450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175832$10451 + cell $add $add$libresoc.v:175831$10451 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -360161,10 +356971,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_6 } connect \B { 2'00 \pop_4_7 } - connect \Y $add$libresoc.v:175832$10451_Y + connect \Y $add$libresoc.v:175831$10451_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175833$10452 + cell $add $add$libresoc.v:175832$10452 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -360172,10 +356982,10 @@ module \popcount parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_0 } connect \B { 2'00 \pop_5_1 } - connect \Y $add$libresoc.v:175833$10452_Y + connect \Y $add$libresoc.v:175832$10452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175834$10453 + cell $add $add$libresoc.v:175833$10453 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -360183,10 +356993,10 @@ module \popcount parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_2 } connect \B { 2'00 \pop_5_3 } - connect \Y $add$libresoc.v:175834$10453_Y + connect \Y $add$libresoc.v:175833$10453_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175835$10454 + cell $add $add$libresoc.v:175834$10454 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -360194,10 +357004,10 @@ module \popcount parameter \Y_WIDTH 8 connect \A { 2'00 \pop_6_0 } connect \B { 2'00 \pop_6_1 } - connect \Y $add$libresoc.v:175835$10454_Y + connect \Y $add$libresoc.v:175834$10454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175846$10473 + cell $add $add$libresoc.v:175845$10473 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360205,10 +357015,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [12] } connect \B { 2'00 \a [13] } - connect \Y $add$libresoc.v:175846$10473_Y + connect \Y $add$libresoc.v:175845$10473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175850$10480 + cell $add $add$libresoc.v:175849$10480 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360216,10 +357026,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [14] } connect \B { 2'00 \a [15] } - connect \Y $add$libresoc.v:175850$10480_Y + connect \Y $add$libresoc.v:175849$10480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175851$10481 + cell $add $add$libresoc.v:175850$10481 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360227,10 +357037,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [16] } connect \B { 2'00 \a [17] } - connect \Y $add$libresoc.v:175851$10481_Y + connect \Y $add$libresoc.v:175850$10481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175852$10482 + cell $add $add$libresoc.v:175851$10482 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360238,10 +357048,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [0] } connect \B { 2'00 \a [1] } - connect \Y $add$libresoc.v:175852$10482_Y + connect \Y $add$libresoc.v:175851$10482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175853$10483 + cell $add $add$libresoc.v:175852$10483 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360249,10 +357059,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [18] } connect \B { 2'00 \a [19] } - connect \Y $add$libresoc.v:175853$10483_Y + connect \Y $add$libresoc.v:175852$10483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175854$10484 + cell $add $add$libresoc.v:175853$10484 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360260,10 +357070,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [20] } connect \B { 2'00 \a [21] } - connect \Y $add$libresoc.v:175854$10484_Y + connect \Y $add$libresoc.v:175853$10484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175855$10485 + cell $add $add$libresoc.v:175854$10485 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360271,10 +357081,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [22] } connect \B { 2'00 \a [23] } - connect \Y $add$libresoc.v:175855$10485_Y + connect \Y $add$libresoc.v:175854$10485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175856$10486 + cell $add $add$libresoc.v:175855$10486 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360282,10 +357092,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [24] } connect \B { 2'00 \a [25] } - connect \Y $add$libresoc.v:175856$10486_Y + connect \Y $add$libresoc.v:175855$10486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175857$10487 + cell $add $add$libresoc.v:175856$10487 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360293,10 +357103,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [26] } connect \B { 2'00 \a [27] } - connect \Y $add$libresoc.v:175857$10487_Y + connect \Y $add$libresoc.v:175856$10487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175858$10488 + cell $add $add$libresoc.v:175857$10488 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360304,10 +357114,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [28] } connect \B { 2'00 \a [29] } - connect \Y $add$libresoc.v:175858$10488_Y + connect \Y $add$libresoc.v:175857$10488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175859$10489 + cell $add $add$libresoc.v:175858$10489 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360315,10 +357125,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [30] } connect \B { 2'00 \a [31] } - connect \Y $add$libresoc.v:175859$10489_Y + connect \Y $add$libresoc.v:175858$10489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175860$10490 + cell $add $add$libresoc.v:175859$10490 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360326,10 +357136,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [32] } connect \B { 2'00 \a [33] } - connect \Y $add$libresoc.v:175860$10490_Y + connect \Y $add$libresoc.v:175859$10490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175861$10491 + cell $add $add$libresoc.v:175860$10491 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360337,10 +357147,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [34] } connect \B { 2'00 \a [35] } - connect \Y $add$libresoc.v:175861$10491_Y + connect \Y $add$libresoc.v:175860$10491_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175862$10492 + cell $add $add$libresoc.v:175861$10492 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360348,10 +357158,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [36] } connect \B { 2'00 \a [37] } - connect \Y $add$libresoc.v:175862$10492_Y + connect \Y $add$libresoc.v:175861$10492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175863$10493 + cell $add $add$libresoc.v:175862$10493 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360359,10 +357169,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [2] } connect \B { 2'00 \a [3] } - connect \Y $add$libresoc.v:175863$10493_Y + connect \Y $add$libresoc.v:175862$10493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175864$10494 + cell $add $add$libresoc.v:175863$10494 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360370,10 +357180,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [38] } connect \B { 2'00 \a [39] } - connect \Y $add$libresoc.v:175864$10494_Y + connect \Y $add$libresoc.v:175863$10494_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175865$10495 + cell $add $add$libresoc.v:175864$10495 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360381,10 +357191,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [40] } connect \B { 2'00 \a [41] } - connect \Y $add$libresoc.v:175865$10495_Y + connect \Y $add$libresoc.v:175864$10495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175866$10496 + cell $add $add$libresoc.v:175865$10496 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360392,10 +357202,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [42] } connect \B { 2'00 \a [43] } - connect \Y $add$libresoc.v:175866$10496_Y + connect \Y $add$libresoc.v:175865$10496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175867$10497 + cell $add $add$libresoc.v:175866$10497 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360403,10 +357213,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [44] } connect \B { 2'00 \a [45] } - connect \Y $add$libresoc.v:175867$10497_Y + connect \Y $add$libresoc.v:175866$10497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175868$10498 + cell $add $add$libresoc.v:175867$10498 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360414,10 +357224,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [46] } connect \B { 2'00 \a [47] } - connect \Y $add$libresoc.v:175868$10498_Y + connect \Y $add$libresoc.v:175867$10498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175869$10499 + cell $add $add$libresoc.v:175868$10499 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360425,10 +357235,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [48] } connect \B { 2'00 \a [49] } - connect \Y $add$libresoc.v:175869$10499_Y + connect \Y $add$libresoc.v:175868$10499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175870$10500 + cell $add $add$libresoc.v:175869$10500 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360436,10 +357246,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [50] } connect \B { 2'00 \a [51] } - connect \Y $add$libresoc.v:175870$10500_Y + connect \Y $add$libresoc.v:175869$10500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175871$10501 + cell $add $add$libresoc.v:175870$10501 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360447,10 +357257,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [52] } connect \B { 2'00 \a [53] } - connect \Y $add$libresoc.v:175871$10501_Y + connect \Y $add$libresoc.v:175870$10501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175872$10502 + cell $add $add$libresoc.v:175871$10502 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360458,10 +357268,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [54] } connect \B { 2'00 \a [55] } - connect \Y $add$libresoc.v:175872$10502_Y + connect \Y $add$libresoc.v:175871$10502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175873$10503 + cell $add $add$libresoc.v:175872$10503 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360469,10 +357279,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [56] } connect \B { 2'00 \a [57] } - connect \Y $add$libresoc.v:175873$10503_Y + connect \Y $add$libresoc.v:175872$10503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175874$10504 + cell $add $add$libresoc.v:175873$10504 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360480,10 +357290,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [4] } connect \B { 2'00 \a [5] } - connect \Y $add$libresoc.v:175874$10504_Y + connect \Y $add$libresoc.v:175873$10504_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175875$10505 + cell $add $add$libresoc.v:175874$10505 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360491,10 +357301,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [58] } connect \B { 2'00 \a [59] } - connect \Y $add$libresoc.v:175875$10505_Y + connect \Y $add$libresoc.v:175874$10505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175876$10506 + cell $add $add$libresoc.v:175875$10506 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360502,10 +357312,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [60] } connect \B { 2'00 \a [61] } - connect \Y $add$libresoc.v:175876$10506_Y + connect \Y $add$libresoc.v:175875$10506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175877$10507 + cell $add $add$libresoc.v:175876$10507 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -360513,10 +357323,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [62] } connect \B { 2'00 \a [63] } - connect \Y $add$libresoc.v:175877$10507_Y + connect \Y $add$libresoc.v:175876$10507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175878$10508 + cell $add $add$libresoc.v:175877$10508 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -360524,10 +357334,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_0 } connect \B { 2'00 \pop_2_1 } - connect \Y $add$libresoc.v:175878$10508_Y + connect \Y $add$libresoc.v:175877$10508_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - cell $eq $eq$libresoc.v:175836$10455 + cell $eq $eq$libresoc.v:175835$10455 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -360535,10 +357345,10 @@ module \popcount parameter \Y_WIDTH 1 connect \A \data_len connect \B 1'1 - connect \Y $eq$libresoc.v:175836$10455_Y + connect \Y $eq$libresoc.v:175835$10455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" - cell $eq $eq$libresoc.v:175837$10456 + cell $eq $eq$libresoc.v:175836$10456 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -360546,199 +357356,199 @@ module \popcount parameter \Y_WIDTH 1 connect \A \data_len connect \B 3'100 - connect \Y $eq$libresoc.v:175837$10456_Y + connect \Y $eq$libresoc.v:175836$10456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175838$10457 + cell $pos $extend$libresoc.v:175837$10457 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_0 - connect \Y $extend$libresoc.v:175838$10457_Y + connect \Y $extend$libresoc.v:175837$10457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175839$10459 + cell $pos $extend$libresoc.v:175838$10459 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_1 - connect \Y $extend$libresoc.v:175839$10459_Y + connect \Y $extend$libresoc.v:175838$10459_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175840$10461 + cell $pos $extend$libresoc.v:175839$10461 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_2 - connect \Y $extend$libresoc.v:175840$10461_Y + connect \Y $extend$libresoc.v:175839$10461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175841$10463 + cell $pos $extend$libresoc.v:175840$10463 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_3 - connect \Y $extend$libresoc.v:175841$10463_Y + connect \Y $extend$libresoc.v:175840$10463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175842$10465 + cell $pos $extend$libresoc.v:175841$10465 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_4 - connect \Y $extend$libresoc.v:175842$10465_Y + connect \Y $extend$libresoc.v:175841$10465_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175843$10467 + cell $pos $extend$libresoc.v:175842$10467 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_5 - connect \Y $extend$libresoc.v:175843$10467_Y + connect \Y $extend$libresoc.v:175842$10467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175844$10469 + cell $pos $extend$libresoc.v:175843$10469 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_6 - connect \Y $extend$libresoc.v:175844$10469_Y + connect \Y $extend$libresoc.v:175843$10469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175845$10471 + cell $pos $extend$libresoc.v:175844$10471 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_7 - connect \Y $extend$libresoc.v:175845$10471_Y + connect \Y $extend$libresoc.v:175844$10471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175847$10474 + cell $pos $extend$libresoc.v:175846$10474 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_0 - connect \Y $extend$libresoc.v:175847$10474_Y + connect \Y $extend$libresoc.v:175846$10474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175848$10476 + cell $pos $extend$libresoc.v:175847$10476 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_1 - connect \Y $extend$libresoc.v:175848$10476_Y + connect \Y $extend$libresoc.v:175847$10476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175849$10478 + cell $pos $extend$libresoc.v:175848$10478 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 64 connect \A \pop_7_0 - connect \Y $extend$libresoc.v:175849$10478_Y + connect \Y $extend$libresoc.v:175848$10478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175838$10458 + cell $pos $pos$libresoc.v:175837$10458 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175838$10457_Y - connect \Y $pos$libresoc.v:175838$10458_Y + connect \A $extend$libresoc.v:175837$10457_Y + connect \Y $pos$libresoc.v:175837$10458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175839$10460 + cell $pos $pos$libresoc.v:175838$10460 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175839$10459_Y - connect \Y $pos$libresoc.v:175839$10460_Y + connect \A $extend$libresoc.v:175838$10459_Y + connect \Y $pos$libresoc.v:175838$10460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175840$10462 + cell $pos $pos$libresoc.v:175839$10462 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175840$10461_Y - connect \Y $pos$libresoc.v:175840$10462_Y + connect \A $extend$libresoc.v:175839$10461_Y + connect \Y $pos$libresoc.v:175839$10462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175841$10464 + cell $pos $pos$libresoc.v:175840$10464 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175841$10463_Y - connect \Y $pos$libresoc.v:175841$10464_Y + connect \A $extend$libresoc.v:175840$10463_Y + connect \Y $pos$libresoc.v:175840$10464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175842$10466 + cell $pos $pos$libresoc.v:175841$10466 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175842$10465_Y - connect \Y $pos$libresoc.v:175842$10466_Y + connect \A $extend$libresoc.v:175841$10465_Y + connect \Y $pos$libresoc.v:175841$10466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175843$10468 + cell $pos $pos$libresoc.v:175842$10468 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175843$10467_Y - connect \Y $pos$libresoc.v:175843$10468_Y + connect \A $extend$libresoc.v:175842$10467_Y + connect \Y $pos$libresoc.v:175842$10468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175844$10470 + cell $pos $pos$libresoc.v:175843$10470 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175844$10469_Y - connect \Y $pos$libresoc.v:175844$10470_Y + connect \A $extend$libresoc.v:175843$10469_Y + connect \Y $pos$libresoc.v:175843$10470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175845$10472 + cell $pos $pos$libresoc.v:175844$10472 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175845$10471_Y - connect \Y $pos$libresoc.v:175845$10472_Y + connect \A $extend$libresoc.v:175844$10471_Y + connect \Y $pos$libresoc.v:175844$10472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175847$10475 + cell $pos $pos$libresoc.v:175846$10475 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:175847$10474_Y - connect \Y $pos$libresoc.v:175847$10475_Y + connect \A $extend$libresoc.v:175846$10474_Y + connect \Y $pos$libresoc.v:175846$10475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175848$10477 + cell $pos $pos$libresoc.v:175847$10477 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:175848$10476_Y - connect \Y $pos$libresoc.v:175848$10477_Y + connect \A $extend$libresoc.v:175847$10476_Y + connect \Y $pos$libresoc.v:175847$10477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175849$10479 + cell $pos $pos$libresoc.v:175848$10479 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:175849$10478_Y - connect \Y $pos$libresoc.v:175849$10479_Y + connect \A $extend$libresoc.v:175848$10478_Y + connect \Y $pos$libresoc.v:175848$10479_Y end - attribute \src "libresoc.v:175391.7-175391.20" - process $proc$libresoc.v:175391$10510 + attribute \src "libresoc.v:175390.7-175390.20" + process $proc$libresoc.v:175390$10510 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175879.3-175905.6" - process $proc$libresoc.v:175879$10509 + attribute \src "libresoc.v:175878.3-175904.6" + process $proc$libresoc.v:175878$10509 assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:175880.5-175880.29" + attribute \src "libresoc.v:175879.5-175879.29" switch \initial - attribute \src "libresoc.v:175880.9-175880.17" + attribute \src "libresoc.v:175879.9-175879.17" case 1'1 case end @@ -360768,82 +357578,82 @@ module \popcount sync always update \o $0\o[63:0] end - connect \$101 $add$libresoc.v:175803$10422_Y - connect \$104 $add$libresoc.v:175804$10423_Y - connect \$107 $add$libresoc.v:175805$10424_Y - connect \$110 $add$libresoc.v:175806$10425_Y - connect \$113 $add$libresoc.v:175807$10426_Y - connect \$116 $add$libresoc.v:175808$10427_Y - connect \$11 $add$libresoc.v:175809$10428_Y - connect \$119 $add$libresoc.v:175810$10429_Y - connect \$122 $add$libresoc.v:175811$10430_Y - connect \$125 $add$libresoc.v:175812$10431_Y - connect \$128 $add$libresoc.v:175813$10432_Y - connect \$131 $add$libresoc.v:175814$10433_Y - connect \$134 $add$libresoc.v:175815$10434_Y - connect \$137 $add$libresoc.v:175816$10435_Y - connect \$140 $add$libresoc.v:175817$10436_Y - connect \$143 $add$libresoc.v:175818$10437_Y - connect \$146 $add$libresoc.v:175819$10438_Y - connect \$14 $add$libresoc.v:175820$10439_Y - connect \$149 $add$libresoc.v:175821$10440_Y - connect \$152 $add$libresoc.v:175822$10441_Y - connect \$155 $add$libresoc.v:175823$10442_Y - connect \$158 $add$libresoc.v:175824$10443_Y - connect \$161 $add$libresoc.v:175825$10444_Y - connect \$164 $add$libresoc.v:175826$10445_Y - connect \$167 $add$libresoc.v:175827$10446_Y - connect \$170 $add$libresoc.v:175828$10447_Y - connect \$173 $add$libresoc.v:175829$10448_Y - connect \$176 $add$libresoc.v:175830$10449_Y - connect \$17 $add$libresoc.v:175831$10450_Y - connect \$179 $add$libresoc.v:175832$10451_Y - connect \$182 $add$libresoc.v:175833$10452_Y - connect \$185 $add$libresoc.v:175834$10453_Y - connect \$188 $add$libresoc.v:175835$10454_Y - connect \$190 $eq$libresoc.v:175836$10455_Y - connect \$192 $eq$libresoc.v:175837$10456_Y - connect \$194 $pos$libresoc.v:175838$10458_Y - connect \$196 $pos$libresoc.v:175839$10460_Y - connect \$198 $pos$libresoc.v:175840$10462_Y - connect \$200 $pos$libresoc.v:175841$10464_Y - connect \$202 $pos$libresoc.v:175842$10466_Y - connect \$204 $pos$libresoc.v:175843$10468_Y - connect \$206 $pos$libresoc.v:175844$10470_Y - connect \$208 $pos$libresoc.v:175845$10472_Y - connect \$20 $add$libresoc.v:175846$10473_Y - connect \$210 $pos$libresoc.v:175847$10475_Y - connect \$212 $pos$libresoc.v:175848$10477_Y - connect \$214 $pos$libresoc.v:175849$10479_Y - connect \$23 $add$libresoc.v:175850$10480_Y - connect \$26 $add$libresoc.v:175851$10481_Y - connect \$2 $add$libresoc.v:175852$10482_Y - connect \$29 $add$libresoc.v:175853$10483_Y - connect \$32 $add$libresoc.v:175854$10484_Y - connect \$35 $add$libresoc.v:175855$10485_Y - connect \$38 $add$libresoc.v:175856$10486_Y - connect \$41 $add$libresoc.v:175857$10487_Y - connect \$44 $add$libresoc.v:175858$10488_Y - connect \$47 $add$libresoc.v:175859$10489_Y - connect \$50 $add$libresoc.v:175860$10490_Y - connect \$53 $add$libresoc.v:175861$10491_Y - connect \$56 $add$libresoc.v:175862$10492_Y - connect \$5 $add$libresoc.v:175863$10493_Y - connect \$59 $add$libresoc.v:175864$10494_Y - connect \$62 $add$libresoc.v:175865$10495_Y - connect \$65 $add$libresoc.v:175866$10496_Y - connect \$68 $add$libresoc.v:175867$10497_Y - connect \$71 $add$libresoc.v:175868$10498_Y - connect \$74 $add$libresoc.v:175869$10499_Y - connect \$77 $add$libresoc.v:175870$10500_Y - connect \$80 $add$libresoc.v:175871$10501_Y - connect \$83 $add$libresoc.v:175872$10502_Y - connect \$86 $add$libresoc.v:175873$10503_Y - connect \$8 $add$libresoc.v:175874$10504_Y - connect \$89 $add$libresoc.v:175875$10505_Y - connect \$92 $add$libresoc.v:175876$10506_Y - connect \$95 $add$libresoc.v:175877$10507_Y - connect \$98 $add$libresoc.v:175878$10508_Y + connect \$101 $add$libresoc.v:175802$10422_Y + connect \$104 $add$libresoc.v:175803$10423_Y + connect \$107 $add$libresoc.v:175804$10424_Y + connect \$110 $add$libresoc.v:175805$10425_Y + connect \$113 $add$libresoc.v:175806$10426_Y + connect \$116 $add$libresoc.v:175807$10427_Y + connect \$11 $add$libresoc.v:175808$10428_Y + connect \$119 $add$libresoc.v:175809$10429_Y + connect \$122 $add$libresoc.v:175810$10430_Y + connect \$125 $add$libresoc.v:175811$10431_Y + connect \$128 $add$libresoc.v:175812$10432_Y + connect \$131 $add$libresoc.v:175813$10433_Y + connect \$134 $add$libresoc.v:175814$10434_Y + connect \$137 $add$libresoc.v:175815$10435_Y + connect \$140 $add$libresoc.v:175816$10436_Y + connect \$143 $add$libresoc.v:175817$10437_Y + connect \$146 $add$libresoc.v:175818$10438_Y + connect \$14 $add$libresoc.v:175819$10439_Y + connect \$149 $add$libresoc.v:175820$10440_Y + connect \$152 $add$libresoc.v:175821$10441_Y + connect \$155 $add$libresoc.v:175822$10442_Y + connect \$158 $add$libresoc.v:175823$10443_Y + connect \$161 $add$libresoc.v:175824$10444_Y + connect \$164 $add$libresoc.v:175825$10445_Y + connect \$167 $add$libresoc.v:175826$10446_Y + connect \$170 $add$libresoc.v:175827$10447_Y + connect \$173 $add$libresoc.v:175828$10448_Y + connect \$176 $add$libresoc.v:175829$10449_Y + connect \$17 $add$libresoc.v:175830$10450_Y + connect \$179 $add$libresoc.v:175831$10451_Y + connect \$182 $add$libresoc.v:175832$10452_Y + connect \$185 $add$libresoc.v:175833$10453_Y + connect \$188 $add$libresoc.v:175834$10454_Y + connect \$190 $eq$libresoc.v:175835$10455_Y + connect \$192 $eq$libresoc.v:175836$10456_Y + connect \$194 $pos$libresoc.v:175837$10458_Y + connect \$196 $pos$libresoc.v:175838$10460_Y + connect \$198 $pos$libresoc.v:175839$10462_Y + connect \$200 $pos$libresoc.v:175840$10464_Y + connect \$202 $pos$libresoc.v:175841$10466_Y + connect \$204 $pos$libresoc.v:175842$10468_Y + connect \$206 $pos$libresoc.v:175843$10470_Y + connect \$208 $pos$libresoc.v:175844$10472_Y + connect \$20 $add$libresoc.v:175845$10473_Y + connect \$210 $pos$libresoc.v:175846$10475_Y + connect \$212 $pos$libresoc.v:175847$10477_Y + connect \$214 $pos$libresoc.v:175848$10479_Y + connect \$23 $add$libresoc.v:175849$10480_Y + connect \$26 $add$libresoc.v:175850$10481_Y + connect \$2 $add$libresoc.v:175851$10482_Y + connect \$29 $add$libresoc.v:175852$10483_Y + connect \$32 $add$libresoc.v:175853$10484_Y + connect \$35 $add$libresoc.v:175854$10485_Y + connect \$38 $add$libresoc.v:175855$10486_Y + connect \$41 $add$libresoc.v:175856$10487_Y + connect \$44 $add$libresoc.v:175857$10488_Y + connect \$47 $add$libresoc.v:175858$10489_Y + connect \$50 $add$libresoc.v:175859$10490_Y + connect \$53 $add$libresoc.v:175860$10491_Y + connect \$56 $add$libresoc.v:175861$10492_Y + connect \$5 $add$libresoc.v:175862$10493_Y + connect \$59 $add$libresoc.v:175863$10494_Y + connect \$62 $add$libresoc.v:175864$10495_Y + connect \$65 $add$libresoc.v:175865$10496_Y + connect \$68 $add$libresoc.v:175866$10497_Y + connect \$71 $add$libresoc.v:175867$10498_Y + connect \$74 $add$libresoc.v:175868$10499_Y + connect \$77 $add$libresoc.v:175869$10500_Y + connect \$80 $add$libresoc.v:175870$10501_Y + connect \$83 $add$libresoc.v:175871$10502_Y + connect \$86 $add$libresoc.v:175872$10503_Y + connect \$8 $add$libresoc.v:175873$10504_Y + connect \$89 $add$libresoc.v:175874$10505_Y + connect \$92 $add$libresoc.v:175875$10506_Y + connect \$95 $add$libresoc.v:175876$10507_Y + connect \$98 $add$libresoc.v:175877$10508_Y connect \$1 \$2 connect \$4 \$5 connect \$7 \$8 @@ -360971,43 +357781,43 @@ module \popcount connect \pop_2_1 \$5 [1:0] connect \pop_2_0 \$2 [1:0] end -attribute \src "libresoc.v:176036.1-176120.10" +attribute \src "libresoc.v:176035.1-176119.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" attribute \generator "nMigen" module \ppick - attribute \src "libresoc.v:176093.17-176093.91" - wire $not$libresoc.v:176093$10511_Y - attribute \src "libresoc.v:176095.18-176095.93" - wire $not$libresoc.v:176095$10513_Y - attribute \src "libresoc.v:176097.18-176097.93" - wire $not$libresoc.v:176097$10515_Y - attribute \src "libresoc.v:176098.17-176098.138" - wire width 8 $not$libresoc.v:176098$10516_Y - attribute \src "libresoc.v:176100.18-176100.93" - wire $not$libresoc.v:176100$10518_Y - attribute \src "libresoc.v:176102.18-176102.93" - wire $not$libresoc.v:176102$10520_Y - attribute \src "libresoc.v:176104.18-176104.93" - wire $not$libresoc.v:176104$10522_Y - attribute \src "libresoc.v:176107.17-176107.91" - wire $not$libresoc.v:176107$10525_Y - attribute \src "libresoc.v:176094.18-176094.116" - wire $reduce_or$libresoc.v:176094$10512_Y - attribute \src "libresoc.v:176096.18-176096.122" - wire $reduce_or$libresoc.v:176096$10514_Y - attribute \src "libresoc.v:176099.18-176099.128" - wire $reduce_or$libresoc.v:176099$10517_Y - attribute \src "libresoc.v:176101.18-176101.134" - wire $reduce_or$libresoc.v:176101$10519_Y - attribute \src "libresoc.v:176103.18-176103.140" - wire $reduce_or$libresoc.v:176103$10521_Y - attribute \src "libresoc.v:176105.18-176105.90" - wire $reduce_or$libresoc.v:176105$10523_Y - attribute \src "libresoc.v:176106.17-176106.103" - wire $reduce_or$libresoc.v:176106$10524_Y - attribute \src "libresoc.v:176108.17-176108.109" - wire $reduce_or$libresoc.v:176108$10526_Y + attribute \src "libresoc.v:176092.17-176092.91" + wire $not$libresoc.v:176092$10511_Y + attribute \src "libresoc.v:176094.18-176094.93" + wire $not$libresoc.v:176094$10513_Y + attribute \src "libresoc.v:176096.18-176096.93" + wire $not$libresoc.v:176096$10515_Y + attribute \src "libresoc.v:176097.17-176097.138" + wire width 8 $not$libresoc.v:176097$10516_Y + attribute \src "libresoc.v:176099.18-176099.93" + wire $not$libresoc.v:176099$10518_Y + attribute \src "libresoc.v:176101.18-176101.93" + wire $not$libresoc.v:176101$10520_Y + attribute \src "libresoc.v:176103.18-176103.93" + wire $not$libresoc.v:176103$10522_Y + attribute \src "libresoc.v:176106.17-176106.91" + wire $not$libresoc.v:176106$10525_Y + attribute \src "libresoc.v:176093.18-176093.116" + wire $reduce_or$libresoc.v:176093$10512_Y + attribute \src "libresoc.v:176095.18-176095.122" + wire $reduce_or$libresoc.v:176095$10514_Y + attribute \src "libresoc.v:176098.18-176098.128" + wire $reduce_or$libresoc.v:176098$10517_Y + attribute \src "libresoc.v:176100.18-176100.134" + wire $reduce_or$libresoc.v:176100$10519_Y + attribute \src "libresoc.v:176102.18-176102.140" + wire $reduce_or$libresoc.v:176102$10521_Y + attribute \src "libresoc.v:176104.18-176104.90" + wire $reduce_or$libresoc.v:176104$10523_Y + attribute \src "libresoc.v:176105.17-176105.103" + wire $reduce_or$libresoc.v:176105$10524_Y + attribute \src "libresoc.v:176107.17-176107.109" + wire $reduce_or$libresoc.v:176107$10526_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -361065,149 +357875,149 @@ module \ppick attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176093$10511 + cell $not $not$libresoc.v:176092$10511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176093$10511_Y + connect \Y $not$libresoc.v:176092$10511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176095$10513 + cell $not $not$libresoc.v:176094$10513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:176095$10513_Y + connect \Y $not$libresoc.v:176094$10513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176097$10515 + cell $not $not$libresoc.v:176096$10515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:176097$10515_Y + connect \Y $not$libresoc.v:176096$10515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176098$10516 + cell $not $not$libresoc.v:176097$10516 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:176098$10516_Y + connect \Y $not$libresoc.v:176097$10516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176100$10518 + cell $not $not$libresoc.v:176099$10518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:176100$10518_Y + connect \Y $not$libresoc.v:176099$10518_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176102$10520 + cell $not $not$libresoc.v:176101$10520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:176102$10520_Y + connect \Y $not$libresoc.v:176101$10520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176104$10522 + cell $not $not$libresoc.v:176103$10522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:176104$10522_Y + connect \Y $not$libresoc.v:176103$10522_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176107$10525 + cell $not $not$libresoc.v:176106$10525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176107$10525_Y + connect \Y $not$libresoc.v:176106$10525_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176094$10512 + cell $reduce_or $reduce_or$libresoc.v:176093$10512 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:176094$10512_Y + connect \Y $reduce_or$libresoc.v:176093$10512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176096$10514 + cell $reduce_or $reduce_or$libresoc.v:176095$10514 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:176096$10514_Y + connect \Y $reduce_or$libresoc.v:176095$10514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176099$10517 + cell $reduce_or $reduce_or$libresoc.v:176098$10517 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:176099$10517_Y + connect \Y $reduce_or$libresoc.v:176098$10517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176101$10519 + cell $reduce_or $reduce_or$libresoc.v:176100$10519 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:176101$10519_Y + connect \Y $reduce_or$libresoc.v:176100$10519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176103$10521 + cell $reduce_or $reduce_or$libresoc.v:176102$10521 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:176103$10521_Y + connect \Y $reduce_or$libresoc.v:176102$10521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176105$10523 + cell $reduce_or $reduce_or$libresoc.v:176104$10523 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176105$10523_Y + connect \Y $reduce_or$libresoc.v:176104$10523_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176106$10524 + cell $reduce_or $reduce_or$libresoc.v:176105$10524 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:176106$10524_Y + connect \Y $reduce_or$libresoc.v:176105$10524_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176108$10526 + cell $reduce_or $reduce_or$libresoc.v:176107$10526 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:176108$10526_Y - end - connect \$7 $not$libresoc.v:176093$10511_Y - connect \$12 $reduce_or$libresoc.v:176094$10512_Y - connect \$11 $not$libresoc.v:176095$10513_Y - connect \$16 $reduce_or$libresoc.v:176096$10514_Y - connect \$15 $not$libresoc.v:176097$10515_Y - connect \$1 $not$libresoc.v:176098$10516_Y - connect \$20 $reduce_or$libresoc.v:176099$10517_Y - connect \$19 $not$libresoc.v:176100$10518_Y - connect \$24 $reduce_or$libresoc.v:176101$10519_Y - connect \$23 $not$libresoc.v:176102$10520_Y - connect \$28 $reduce_or$libresoc.v:176103$10521_Y - connect \$27 $not$libresoc.v:176104$10522_Y - connect \$31 $reduce_or$libresoc.v:176105$10523_Y - connect \$4 $reduce_or$libresoc.v:176106$10524_Y - connect \$3 $not$libresoc.v:176107$10525_Y - connect \$8 $reduce_or$libresoc.v:176108$10526_Y + connect \Y $reduce_or$libresoc.v:176107$10526_Y + end + connect \$7 $not$libresoc.v:176092$10511_Y + connect \$12 $reduce_or$libresoc.v:176093$10512_Y + connect \$11 $not$libresoc.v:176094$10513_Y + connect \$16 $reduce_or$libresoc.v:176095$10514_Y + connect \$15 $not$libresoc.v:176096$10515_Y + connect \$1 $not$libresoc.v:176097$10516_Y + connect \$20 $reduce_or$libresoc.v:176098$10517_Y + connect \$19 $not$libresoc.v:176099$10518_Y + connect \$24 $reduce_or$libresoc.v:176100$10519_Y + connect \$23 $not$libresoc.v:176101$10520_Y + connect \$28 $reduce_or$libresoc.v:176102$10521_Y + connect \$27 $not$libresoc.v:176103$10522_Y + connect \$31 $reduce_or$libresoc.v:176104$10523_Y + connect \$4 $reduce_or$libresoc.v:176105$10524_Y + connect \$3 $not$libresoc.v:176106$10525_Y + connect \$8 $reduce_or$libresoc.v:176107$10526_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -361220,43 +358030,43 @@ module \ppick connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:176124.1-176208.10" +attribute \src "libresoc.v:176123.1-176207.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" attribute \generator "nMigen" module \ppick$175 - attribute \src "libresoc.v:176181.17-176181.91" - wire $not$libresoc.v:176181$10527_Y - attribute \src "libresoc.v:176183.18-176183.93" - wire $not$libresoc.v:176183$10529_Y - attribute \src "libresoc.v:176185.18-176185.93" - wire $not$libresoc.v:176185$10531_Y - attribute \src "libresoc.v:176186.17-176186.138" - wire width 8 $not$libresoc.v:176186$10532_Y - attribute \src "libresoc.v:176188.18-176188.93" - wire $not$libresoc.v:176188$10534_Y - attribute \src "libresoc.v:176190.18-176190.93" - wire $not$libresoc.v:176190$10536_Y - attribute \src "libresoc.v:176192.18-176192.93" - wire $not$libresoc.v:176192$10538_Y - attribute \src "libresoc.v:176195.17-176195.91" - wire $not$libresoc.v:176195$10541_Y - attribute \src "libresoc.v:176182.18-176182.116" - wire $reduce_or$libresoc.v:176182$10528_Y - attribute \src "libresoc.v:176184.18-176184.122" - wire $reduce_or$libresoc.v:176184$10530_Y - attribute \src "libresoc.v:176187.18-176187.128" - wire $reduce_or$libresoc.v:176187$10533_Y - attribute \src "libresoc.v:176189.18-176189.134" - wire $reduce_or$libresoc.v:176189$10535_Y - attribute \src "libresoc.v:176191.18-176191.140" - wire $reduce_or$libresoc.v:176191$10537_Y - attribute \src "libresoc.v:176193.18-176193.90" - wire $reduce_or$libresoc.v:176193$10539_Y - attribute \src "libresoc.v:176194.17-176194.103" - wire $reduce_or$libresoc.v:176194$10540_Y - attribute \src "libresoc.v:176196.17-176196.109" - wire $reduce_or$libresoc.v:176196$10542_Y + attribute \src "libresoc.v:176180.17-176180.91" + wire $not$libresoc.v:176180$10527_Y + attribute \src "libresoc.v:176182.18-176182.93" + wire $not$libresoc.v:176182$10529_Y + attribute \src "libresoc.v:176184.18-176184.93" + wire $not$libresoc.v:176184$10531_Y + attribute \src "libresoc.v:176185.17-176185.138" + wire width 8 $not$libresoc.v:176185$10532_Y + attribute \src "libresoc.v:176187.18-176187.93" + wire $not$libresoc.v:176187$10534_Y + attribute \src "libresoc.v:176189.18-176189.93" + wire $not$libresoc.v:176189$10536_Y + attribute \src "libresoc.v:176191.18-176191.93" + wire $not$libresoc.v:176191$10538_Y + attribute \src "libresoc.v:176194.17-176194.91" + wire $not$libresoc.v:176194$10541_Y + attribute \src "libresoc.v:176181.18-176181.116" + wire $reduce_or$libresoc.v:176181$10528_Y + attribute \src "libresoc.v:176183.18-176183.122" + wire $reduce_or$libresoc.v:176183$10530_Y + attribute \src "libresoc.v:176186.18-176186.128" + wire $reduce_or$libresoc.v:176186$10533_Y + attribute \src "libresoc.v:176188.18-176188.134" + wire $reduce_or$libresoc.v:176188$10535_Y + attribute \src "libresoc.v:176190.18-176190.140" + wire $reduce_or$libresoc.v:176190$10537_Y + attribute \src "libresoc.v:176192.18-176192.90" + wire $reduce_or$libresoc.v:176192$10539_Y + attribute \src "libresoc.v:176193.17-176193.103" + wire $reduce_or$libresoc.v:176193$10540_Y + attribute \src "libresoc.v:176195.17-176195.109" + wire $reduce_or$libresoc.v:176195$10542_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -361314,149 +358124,149 @@ module \ppick$175 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176181$10527 + cell $not $not$libresoc.v:176180$10527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176181$10527_Y + connect \Y $not$libresoc.v:176180$10527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176183$10529 + cell $not $not$libresoc.v:176182$10529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:176183$10529_Y + connect \Y $not$libresoc.v:176182$10529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176185$10531 + cell $not $not$libresoc.v:176184$10531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:176185$10531_Y + connect \Y $not$libresoc.v:176184$10531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176186$10532 + cell $not $not$libresoc.v:176185$10532 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:176186$10532_Y + connect \Y $not$libresoc.v:176185$10532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176188$10534 + cell $not $not$libresoc.v:176187$10534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:176188$10534_Y + connect \Y $not$libresoc.v:176187$10534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176190$10536 + cell $not $not$libresoc.v:176189$10536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:176190$10536_Y + connect \Y $not$libresoc.v:176189$10536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176192$10538 + cell $not $not$libresoc.v:176191$10538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:176192$10538_Y + connect \Y $not$libresoc.v:176191$10538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176195$10541 + cell $not $not$libresoc.v:176194$10541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176195$10541_Y + connect \Y $not$libresoc.v:176194$10541_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176182$10528 + cell $reduce_or $reduce_or$libresoc.v:176181$10528 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:176182$10528_Y + connect \Y $reduce_or$libresoc.v:176181$10528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176184$10530 + cell $reduce_or $reduce_or$libresoc.v:176183$10530 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:176184$10530_Y + connect \Y $reduce_or$libresoc.v:176183$10530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176187$10533 + cell $reduce_or $reduce_or$libresoc.v:176186$10533 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:176187$10533_Y + connect \Y $reduce_or$libresoc.v:176186$10533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176189$10535 + cell $reduce_or $reduce_or$libresoc.v:176188$10535 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:176189$10535_Y + connect \Y $reduce_or$libresoc.v:176188$10535_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176191$10537 + cell $reduce_or $reduce_or$libresoc.v:176190$10537 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:176191$10537_Y + connect \Y $reduce_or$libresoc.v:176190$10537_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176193$10539 + cell $reduce_or $reduce_or$libresoc.v:176192$10539 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176193$10539_Y + connect \Y $reduce_or$libresoc.v:176192$10539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176194$10540 + cell $reduce_or $reduce_or$libresoc.v:176193$10540 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:176194$10540_Y + connect \Y $reduce_or$libresoc.v:176193$10540_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176196$10542 + cell $reduce_or $reduce_or$libresoc.v:176195$10542 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:176196$10542_Y - end - connect \$7 $not$libresoc.v:176181$10527_Y - connect \$12 $reduce_or$libresoc.v:176182$10528_Y - connect \$11 $not$libresoc.v:176183$10529_Y - connect \$16 $reduce_or$libresoc.v:176184$10530_Y - connect \$15 $not$libresoc.v:176185$10531_Y - connect \$1 $not$libresoc.v:176186$10532_Y - connect \$20 $reduce_or$libresoc.v:176187$10533_Y - connect \$19 $not$libresoc.v:176188$10534_Y - connect \$24 $reduce_or$libresoc.v:176189$10535_Y - connect \$23 $not$libresoc.v:176190$10536_Y - connect \$28 $reduce_or$libresoc.v:176191$10537_Y - connect \$27 $not$libresoc.v:176192$10538_Y - connect \$31 $reduce_or$libresoc.v:176193$10539_Y - connect \$4 $reduce_or$libresoc.v:176194$10540_Y - connect \$3 $not$libresoc.v:176195$10541_Y - connect \$8 $reduce_or$libresoc.v:176196$10542_Y + connect \Y $reduce_or$libresoc.v:176195$10542_Y + end + connect \$7 $not$libresoc.v:176180$10527_Y + connect \$12 $reduce_or$libresoc.v:176181$10528_Y + connect \$11 $not$libresoc.v:176182$10529_Y + connect \$16 $reduce_or$libresoc.v:176183$10530_Y + connect \$15 $not$libresoc.v:176184$10531_Y + connect \$1 $not$libresoc.v:176185$10532_Y + connect \$20 $reduce_or$libresoc.v:176186$10533_Y + connect \$19 $not$libresoc.v:176187$10534_Y + connect \$24 $reduce_or$libresoc.v:176188$10535_Y + connect \$23 $not$libresoc.v:176189$10536_Y + connect \$28 $reduce_or$libresoc.v:176190$10537_Y + connect \$27 $not$libresoc.v:176191$10538_Y + connect \$31 $reduce_or$libresoc.v:176192$10539_Y + connect \$4 $reduce_or$libresoc.v:176193$10540_Y + connect \$3 $not$libresoc.v:176194$10541_Y + connect \$8 $reduce_or$libresoc.v:176195$10542_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -361469,19 +358279,19 @@ module \ppick$175 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:176212.1-176242.10" +attribute \src "libresoc.v:176211.1-176241.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_a" attribute \generator "nMigen" module \rdpick_CR_cr_a - attribute \src "libresoc.v:176233.17-176233.89" - wire width 2 $not$libresoc.v:176233$10543_Y - attribute \src "libresoc.v:176235.17-176235.91" - wire $not$libresoc.v:176235$10545_Y - attribute \src "libresoc.v:176234.17-176234.103" - wire $reduce_or$libresoc.v:176234$10544_Y - attribute \src "libresoc.v:176236.17-176236.89" - wire $reduce_or$libresoc.v:176236$10546_Y + attribute \src "libresoc.v:176232.17-176232.89" + wire width 2 $not$libresoc.v:176232$10543_Y + attribute \src "libresoc.v:176234.17-176234.91" + wire $not$libresoc.v:176234$10545_Y + attribute \src "libresoc.v:176233.17-176233.103" + wire $reduce_or$libresoc.v:176233$10544_Y + attribute \src "libresoc.v:176235.17-176235.89" + wire $reduce_or$libresoc.v:176235$10546_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -361503,56 +358313,56 @@ module \rdpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176233$10543 + cell $not $not$libresoc.v:176232$10543 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:176233$10543_Y + connect \Y $not$libresoc.v:176232$10543_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176235$10545 + cell $not $not$libresoc.v:176234$10545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176235$10545_Y + connect \Y $not$libresoc.v:176234$10545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176234$10544 + cell $reduce_or $reduce_or$libresoc.v:176233$10544 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176234$10544_Y + connect \Y $reduce_or$libresoc.v:176233$10544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176236$10546 + cell $reduce_or $reduce_or$libresoc.v:176235$10546 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176236$10546_Y + connect \Y $reduce_or$libresoc.v:176235$10546_Y end - connect \$1 $not$libresoc.v:176233$10543_Y - connect \$4 $reduce_or$libresoc.v:176234$10544_Y - connect \$3 $not$libresoc.v:176235$10545_Y - connect \$7 $reduce_or$libresoc.v:176236$10546_Y + connect \$1 $not$libresoc.v:176232$10543_Y + connect \$4 $reduce_or$libresoc.v:176233$10544_Y + connect \$3 $not$libresoc.v:176234$10545_Y + connect \$7 $reduce_or$libresoc.v:176235$10546_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176246.1-176267.10" +attribute \src "libresoc.v:176245.1-176266.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_b" attribute \generator "nMigen" module \rdpick_CR_cr_b + attribute \src "libresoc.v:176260.17-176260.89" + wire $not$libresoc.v:176260$10547_Y attribute \src "libresoc.v:176261.17-176261.89" - wire $not$libresoc.v:176261$10547_Y - attribute \src "libresoc.v:176262.17-176262.89" - wire $reduce_or$libresoc.v:176262$10548_Y + wire $reduce_or$libresoc.v:176261$10548_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -361568,37 +358378,37 @@ module \rdpick_CR_cr_b attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176261$10547 + cell $not $not$libresoc.v:176260$10547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:176261$10547_Y + connect \Y $not$libresoc.v:176260$10547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176262$10548 + cell $reduce_or $reduce_or$libresoc.v:176261$10548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176262$10548_Y + connect \Y $reduce_or$libresoc.v:176261$10548_Y end - connect \$1 $not$libresoc.v:176261$10547_Y - connect \$3 $reduce_or$libresoc.v:176262$10548_Y + connect \$1 $not$libresoc.v:176260$10547_Y + connect \$3 $reduce_or$libresoc.v:176261$10548_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:176271.1-176292.10" +attribute \src "libresoc.v:176270.1-176291.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_c" attribute \generator "nMigen" module \rdpick_CR_cr_c + attribute \src "libresoc.v:176285.17-176285.89" + wire $not$libresoc.v:176285$10549_Y attribute \src "libresoc.v:176286.17-176286.89" - wire $not$libresoc.v:176286$10549_Y - attribute \src "libresoc.v:176287.17-176287.89" - wire $reduce_or$libresoc.v:176287$10550_Y + wire $reduce_or$libresoc.v:176286$10550_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -361614,37 +358424,37 @@ module \rdpick_CR_cr_c attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176286$10549 + cell $not $not$libresoc.v:176285$10549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:176286$10549_Y + connect \Y $not$libresoc.v:176285$10549_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176287$10550 + cell $reduce_or $reduce_or$libresoc.v:176286$10550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176287$10550_Y + connect \Y $reduce_or$libresoc.v:176286$10550_Y end - connect \$1 $not$libresoc.v:176286$10549_Y - connect \$3 $reduce_or$libresoc.v:176287$10550_Y + connect \$1 $not$libresoc.v:176285$10549_Y + connect \$3 $reduce_or$libresoc.v:176286$10550_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:176296.1-176317.10" +attribute \src "libresoc.v:176295.1-176316.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_full_cr" attribute \generator "nMigen" module \rdpick_CR_full_cr + attribute \src "libresoc.v:176310.17-176310.89" + wire $not$libresoc.v:176310$10551_Y attribute \src "libresoc.v:176311.17-176311.89" - wire $not$libresoc.v:176311$10551_Y - attribute \src "libresoc.v:176312.17-176312.89" - wire $reduce_or$libresoc.v:176312$10552_Y + wire $reduce_or$libresoc.v:176311$10552_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -361660,45 +358470,45 @@ module \rdpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176311$10551 + cell $not $not$libresoc.v:176310$10551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:176311$10551_Y + connect \Y $not$libresoc.v:176310$10551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176312$10552 + cell $reduce_or $reduce_or$libresoc.v:176311$10552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176312$10552_Y + connect \Y $reduce_or$libresoc.v:176311$10552_Y end - connect \$1 $not$libresoc.v:176311$10551_Y - connect \$3 $reduce_or$libresoc.v:176312$10552_Y + connect \$1 $not$libresoc.v:176310$10551_Y + connect \$3 $reduce_or$libresoc.v:176311$10552_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:176321.1-176360.10" +attribute \src "libresoc.v:176320.1-176359.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast1" attribute \generator "nMigen" module \rdpick_FAST_fast1 - attribute \src "libresoc.v:176348.17-176348.91" - wire $not$libresoc.v:176348$10553_Y - attribute \src "libresoc.v:176350.17-176350.89" - wire width 3 $not$libresoc.v:176350$10555_Y - attribute \src "libresoc.v:176352.17-176352.91" - wire $not$libresoc.v:176352$10557_Y - attribute \src "libresoc.v:176349.18-176349.90" - wire $reduce_or$libresoc.v:176349$10554_Y - attribute \src "libresoc.v:176351.17-176351.103" - wire $reduce_or$libresoc.v:176351$10556_Y - attribute \src "libresoc.v:176353.17-176353.105" - wire $reduce_or$libresoc.v:176353$10558_Y + attribute \src "libresoc.v:176347.17-176347.91" + wire $not$libresoc.v:176347$10553_Y + attribute \src "libresoc.v:176349.17-176349.89" + wire width 3 $not$libresoc.v:176349$10555_Y + attribute \src "libresoc.v:176351.17-176351.91" + wire $not$libresoc.v:176351$10557_Y + attribute \src "libresoc.v:176348.18-176348.90" + wire $reduce_or$libresoc.v:176348$10554_Y + attribute \src "libresoc.v:176350.17-176350.103" + wire $reduce_or$libresoc.v:176350$10556_Y + attribute \src "libresoc.v:176352.17-176352.105" + wire $reduce_or$libresoc.v:176352$10558_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -361726,59 +358536,59 @@ module \rdpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176348$10553 + cell $not $not$libresoc.v:176347$10553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176348$10553_Y + connect \Y $not$libresoc.v:176347$10553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176350$10555 + cell $not $not$libresoc.v:176349$10555 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:176350$10555_Y + connect \Y $not$libresoc.v:176349$10555_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176352$10557 + cell $not $not$libresoc.v:176351$10557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176352$10557_Y + connect \Y $not$libresoc.v:176351$10557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176349$10554 + cell $reduce_or $reduce_or$libresoc.v:176348$10554 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176349$10554_Y + connect \Y $reduce_or$libresoc.v:176348$10554_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176351$10556 + cell $reduce_or $reduce_or$libresoc.v:176350$10556 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176351$10556_Y + connect \Y $reduce_or$libresoc.v:176350$10556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176353$10558 + cell $reduce_or $reduce_or$libresoc.v:176352$10558 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:176353$10558_Y - end - connect \$7 $not$libresoc.v:176348$10553_Y - connect \$11 $reduce_or$libresoc.v:176349$10554_Y - connect \$1 $not$libresoc.v:176350$10555_Y - connect \$4 $reduce_or$libresoc.v:176351$10556_Y - connect \$3 $not$libresoc.v:176352$10557_Y - connect \$8 $reduce_or$libresoc.v:176353$10558_Y + connect \Y $reduce_or$libresoc.v:176352$10558_Y + end + connect \$7 $not$libresoc.v:176347$10553_Y + connect \$11 $reduce_or$libresoc.v:176348$10554_Y + connect \$1 $not$libresoc.v:176349$10555_Y + connect \$4 $reduce_or$libresoc.v:176350$10556_Y + connect \$3 $not$libresoc.v:176351$10557_Y + connect \$8 $reduce_or$libresoc.v:176352$10558_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -361786,19 +358596,19 @@ module \rdpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176364.1-176394.10" +attribute \src "libresoc.v:176363.1-176393.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast2" attribute \generator "nMigen" module \rdpick_FAST_fast2 - attribute \src "libresoc.v:176385.17-176385.89" - wire width 2 $not$libresoc.v:176385$10559_Y - attribute \src "libresoc.v:176387.17-176387.91" - wire $not$libresoc.v:176387$10561_Y - attribute \src "libresoc.v:176386.17-176386.103" - wire $reduce_or$libresoc.v:176386$10560_Y - attribute \src "libresoc.v:176388.17-176388.89" - wire $reduce_or$libresoc.v:176388$10562_Y + attribute \src "libresoc.v:176384.17-176384.89" + wire width 2 $not$libresoc.v:176384$10559_Y + attribute \src "libresoc.v:176386.17-176386.91" + wire $not$libresoc.v:176386$10561_Y + attribute \src "libresoc.v:176385.17-176385.103" + wire $reduce_or$libresoc.v:176385$10560_Y + attribute \src "libresoc.v:176387.17-176387.89" + wire $reduce_or$libresoc.v:176387$10562_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -361820,88 +358630,88 @@ module \rdpick_FAST_fast2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176385$10559 + cell $not $not$libresoc.v:176384$10559 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:176385$10559_Y + connect \Y $not$libresoc.v:176384$10559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176387$10561 + cell $not $not$libresoc.v:176386$10561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176387$10561_Y + connect \Y $not$libresoc.v:176386$10561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176386$10560 + cell $reduce_or $reduce_or$libresoc.v:176385$10560 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176386$10560_Y + connect \Y $reduce_or$libresoc.v:176385$10560_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176388$10562 + cell $reduce_or $reduce_or$libresoc.v:176387$10562 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176388$10562_Y + connect \Y $reduce_or$libresoc.v:176387$10562_Y end - connect \$1 $not$libresoc.v:176385$10559_Y - connect \$4 $reduce_or$libresoc.v:176386$10560_Y - connect \$3 $not$libresoc.v:176387$10561_Y - connect \$7 $reduce_or$libresoc.v:176388$10562_Y + connect \$1 $not$libresoc.v:176384$10559_Y + connect \$4 $reduce_or$libresoc.v:176385$10560_Y + connect \$3 $not$libresoc.v:176386$10561_Y + connect \$7 $reduce_or$libresoc.v:176387$10562_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176398.1-176491.10" +attribute \src "libresoc.v:176397.1-176490.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_ra" attribute \generator "nMigen" module \rdpick_INT_ra - attribute \src "libresoc.v:176461.17-176461.91" - wire $not$libresoc.v:176461$10563_Y - attribute \src "libresoc.v:176463.18-176463.93" - wire $not$libresoc.v:176463$10565_Y - attribute \src "libresoc.v:176465.18-176465.93" - wire $not$libresoc.v:176465$10567_Y - attribute \src "libresoc.v:176466.17-176466.89" - wire width 9 $not$libresoc.v:176466$10568_Y - attribute \src "libresoc.v:176468.18-176468.93" - wire $not$libresoc.v:176468$10570_Y - attribute \src "libresoc.v:176470.18-176470.93" - wire $not$libresoc.v:176470$10572_Y - attribute \src "libresoc.v:176472.18-176472.93" - wire $not$libresoc.v:176472$10574_Y - attribute \src "libresoc.v:176474.18-176474.93" - wire $not$libresoc.v:176474$10576_Y - attribute \src "libresoc.v:176477.17-176477.91" - wire $not$libresoc.v:176477$10579_Y - attribute \src "libresoc.v:176462.18-176462.106" - wire $reduce_or$libresoc.v:176462$10564_Y - attribute \src "libresoc.v:176464.18-176464.106" - wire $reduce_or$libresoc.v:176464$10566_Y - attribute \src "libresoc.v:176467.18-176467.106" - wire $reduce_or$libresoc.v:176467$10569_Y - attribute \src "libresoc.v:176469.18-176469.106" - wire $reduce_or$libresoc.v:176469$10571_Y - attribute \src "libresoc.v:176471.18-176471.106" - wire $reduce_or$libresoc.v:176471$10573_Y - attribute \src "libresoc.v:176473.18-176473.106" - wire $reduce_or$libresoc.v:176473$10575_Y - attribute \src "libresoc.v:176475.18-176475.90" - wire $reduce_or$libresoc.v:176475$10577_Y - attribute \src "libresoc.v:176476.17-176476.103" - wire $reduce_or$libresoc.v:176476$10578_Y - attribute \src "libresoc.v:176478.17-176478.105" - wire $reduce_or$libresoc.v:176478$10580_Y + attribute \src "libresoc.v:176460.17-176460.91" + wire $not$libresoc.v:176460$10563_Y + attribute \src "libresoc.v:176462.18-176462.93" + wire $not$libresoc.v:176462$10565_Y + attribute \src "libresoc.v:176464.18-176464.93" + wire $not$libresoc.v:176464$10567_Y + attribute \src "libresoc.v:176465.17-176465.89" + wire width 9 $not$libresoc.v:176465$10568_Y + attribute \src "libresoc.v:176467.18-176467.93" + wire $not$libresoc.v:176467$10570_Y + attribute \src "libresoc.v:176469.18-176469.93" + wire $not$libresoc.v:176469$10572_Y + attribute \src "libresoc.v:176471.18-176471.93" + wire $not$libresoc.v:176471$10574_Y + attribute \src "libresoc.v:176473.18-176473.93" + wire $not$libresoc.v:176473$10576_Y + attribute \src "libresoc.v:176476.17-176476.91" + wire $not$libresoc.v:176476$10579_Y + attribute \src "libresoc.v:176461.18-176461.106" + wire $reduce_or$libresoc.v:176461$10564_Y + attribute \src "libresoc.v:176463.18-176463.106" + wire $reduce_or$libresoc.v:176463$10566_Y + attribute \src "libresoc.v:176466.18-176466.106" + wire $reduce_or$libresoc.v:176466$10569_Y + attribute \src "libresoc.v:176468.18-176468.106" + wire $reduce_or$libresoc.v:176468$10571_Y + attribute \src "libresoc.v:176470.18-176470.106" + wire $reduce_or$libresoc.v:176470$10573_Y + attribute \src "libresoc.v:176472.18-176472.106" + wire $reduce_or$libresoc.v:176472$10575_Y + attribute \src "libresoc.v:176474.18-176474.90" + wire $reduce_or$libresoc.v:176474$10577_Y + attribute \src "libresoc.v:176475.17-176475.103" + wire $reduce_or$libresoc.v:176475$10578_Y + attribute \src "libresoc.v:176477.17-176477.105" + wire $reduce_or$libresoc.v:176477$10580_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 9 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -361965,167 +358775,167 @@ module \rdpick_INT_ra attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176461$10563 + cell $not $not$libresoc.v:176460$10563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176461$10563_Y + connect \Y $not$libresoc.v:176460$10563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176463$10565 + cell $not $not$libresoc.v:176462$10565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:176463$10565_Y + connect \Y $not$libresoc.v:176462$10565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176465$10567 + cell $not $not$libresoc.v:176464$10567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:176465$10567_Y + connect \Y $not$libresoc.v:176464$10567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176466$10568 + cell $not $not$libresoc.v:176465$10568 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 9 connect \A \i - connect \Y $not$libresoc.v:176466$10568_Y + connect \Y $not$libresoc.v:176465$10568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176468$10570 + cell $not $not$libresoc.v:176467$10570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:176468$10570_Y + connect \Y $not$libresoc.v:176467$10570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176470$10572 + cell $not $not$libresoc.v:176469$10572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:176470$10572_Y + connect \Y $not$libresoc.v:176469$10572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176472$10574 + cell $not $not$libresoc.v:176471$10574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:176472$10574_Y + connect \Y $not$libresoc.v:176471$10574_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176474$10576 + cell $not $not$libresoc.v:176473$10576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:176474$10576_Y + connect \Y $not$libresoc.v:176473$10576_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176477$10579 + cell $not $not$libresoc.v:176476$10579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176477$10579_Y + connect \Y $not$libresoc.v:176476$10579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176462$10564 + cell $reduce_or $reduce_or$libresoc.v:176461$10564 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:176462$10564_Y + connect \Y $reduce_or$libresoc.v:176461$10564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176464$10566 + cell $reduce_or $reduce_or$libresoc.v:176463$10566 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:176464$10566_Y + connect \Y $reduce_or$libresoc.v:176463$10566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176467$10569 + cell $reduce_or $reduce_or$libresoc.v:176466$10569 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:176467$10569_Y + connect \Y $reduce_or$libresoc.v:176466$10569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176469$10571 + cell $reduce_or $reduce_or$libresoc.v:176468$10571 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:176469$10571_Y + connect \Y $reduce_or$libresoc.v:176468$10571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176471$10573 + cell $reduce_or $reduce_or$libresoc.v:176470$10573 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:176471$10573_Y + connect \Y $reduce_or$libresoc.v:176470$10573_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176473$10575 + cell $reduce_or $reduce_or$libresoc.v:176472$10575 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:176473$10575_Y + connect \Y $reduce_or$libresoc.v:176472$10575_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176475$10577 + cell $reduce_or $reduce_or$libresoc.v:176474$10577 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176475$10577_Y + connect \Y $reduce_or$libresoc.v:176474$10577_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176476$10578 + cell $reduce_or $reduce_or$libresoc.v:176475$10578 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176476$10578_Y + connect \Y $reduce_or$libresoc.v:176475$10578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176478$10580 + cell $reduce_or $reduce_or$libresoc.v:176477$10580 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:176478$10580_Y - end - connect \$7 $not$libresoc.v:176461$10563_Y - connect \$12 $reduce_or$libresoc.v:176462$10564_Y - connect \$11 $not$libresoc.v:176463$10565_Y - connect \$16 $reduce_or$libresoc.v:176464$10566_Y - connect \$15 $not$libresoc.v:176465$10567_Y - connect \$1 $not$libresoc.v:176466$10568_Y - connect \$20 $reduce_or$libresoc.v:176467$10569_Y - connect \$19 $not$libresoc.v:176468$10570_Y - connect \$24 $reduce_or$libresoc.v:176469$10571_Y - connect \$23 $not$libresoc.v:176470$10572_Y - connect \$28 $reduce_or$libresoc.v:176471$10573_Y - connect \$27 $not$libresoc.v:176472$10574_Y - connect \$32 $reduce_or$libresoc.v:176473$10575_Y - connect \$31 $not$libresoc.v:176474$10576_Y - connect \$35 $reduce_or$libresoc.v:176475$10577_Y - connect \$4 $reduce_or$libresoc.v:176476$10578_Y - connect \$3 $not$libresoc.v:176477$10579_Y - connect \$8 $reduce_or$libresoc.v:176478$10580_Y + connect \Y $reduce_or$libresoc.v:176477$10580_Y + end + connect \$7 $not$libresoc.v:176460$10563_Y + connect \$12 $reduce_or$libresoc.v:176461$10564_Y + connect \$11 $not$libresoc.v:176462$10565_Y + connect \$16 $reduce_or$libresoc.v:176463$10566_Y + connect \$15 $not$libresoc.v:176464$10567_Y + connect \$1 $not$libresoc.v:176465$10568_Y + connect \$20 $reduce_or$libresoc.v:176466$10569_Y + connect \$19 $not$libresoc.v:176467$10570_Y + connect \$24 $reduce_or$libresoc.v:176468$10571_Y + connect \$23 $not$libresoc.v:176469$10572_Y + connect \$28 $reduce_or$libresoc.v:176470$10573_Y + connect \$27 $not$libresoc.v:176471$10574_Y + connect \$32 $reduce_or$libresoc.v:176472$10575_Y + connect \$31 $not$libresoc.v:176473$10576_Y + connect \$35 $reduce_or$libresoc.v:176474$10577_Y + connect \$4 $reduce_or$libresoc.v:176475$10578_Y + connect \$3 $not$libresoc.v:176476$10579_Y + connect \$8 $reduce_or$libresoc.v:176477$10580_Y connect \en_o \$35 connect \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t8 \$31 @@ -362139,43 +358949,43 @@ module \rdpick_INT_ra connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176495.1-176579.10" +attribute \src "libresoc.v:176494.1-176578.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rb" attribute \generator "nMigen" module \rdpick_INT_rb - attribute \src "libresoc.v:176552.17-176552.91" - wire $not$libresoc.v:176552$10581_Y - attribute \src "libresoc.v:176554.18-176554.93" - wire $not$libresoc.v:176554$10583_Y - attribute \src "libresoc.v:176556.18-176556.93" - wire $not$libresoc.v:176556$10585_Y - attribute \src "libresoc.v:176557.17-176557.89" - wire width 8 $not$libresoc.v:176557$10586_Y - attribute \src "libresoc.v:176559.18-176559.93" - wire $not$libresoc.v:176559$10588_Y - attribute \src "libresoc.v:176561.18-176561.93" - wire $not$libresoc.v:176561$10590_Y - attribute \src "libresoc.v:176563.18-176563.93" - wire $not$libresoc.v:176563$10592_Y - attribute \src "libresoc.v:176566.17-176566.91" - wire $not$libresoc.v:176566$10595_Y - attribute \src "libresoc.v:176553.18-176553.106" - wire $reduce_or$libresoc.v:176553$10582_Y - attribute \src "libresoc.v:176555.18-176555.106" - wire $reduce_or$libresoc.v:176555$10584_Y - attribute \src "libresoc.v:176558.18-176558.106" - wire $reduce_or$libresoc.v:176558$10587_Y - attribute \src "libresoc.v:176560.18-176560.106" - wire $reduce_or$libresoc.v:176560$10589_Y - attribute \src "libresoc.v:176562.18-176562.106" - wire $reduce_or$libresoc.v:176562$10591_Y - attribute \src "libresoc.v:176564.18-176564.90" - wire $reduce_or$libresoc.v:176564$10593_Y - attribute \src "libresoc.v:176565.17-176565.103" - wire $reduce_or$libresoc.v:176565$10594_Y - attribute \src "libresoc.v:176567.17-176567.105" - wire $reduce_or$libresoc.v:176567$10596_Y + attribute \src "libresoc.v:176551.17-176551.91" + wire $not$libresoc.v:176551$10581_Y + attribute \src "libresoc.v:176553.18-176553.93" + wire $not$libresoc.v:176553$10583_Y + attribute \src "libresoc.v:176555.18-176555.93" + wire $not$libresoc.v:176555$10585_Y + attribute \src "libresoc.v:176556.17-176556.89" + wire width 8 $not$libresoc.v:176556$10586_Y + attribute \src "libresoc.v:176558.18-176558.93" + wire $not$libresoc.v:176558$10588_Y + attribute \src "libresoc.v:176560.18-176560.93" + wire $not$libresoc.v:176560$10590_Y + attribute \src "libresoc.v:176562.18-176562.93" + wire $not$libresoc.v:176562$10592_Y + attribute \src "libresoc.v:176565.17-176565.91" + wire $not$libresoc.v:176565$10595_Y + attribute \src "libresoc.v:176552.18-176552.106" + wire $reduce_or$libresoc.v:176552$10582_Y + attribute \src "libresoc.v:176554.18-176554.106" + wire $reduce_or$libresoc.v:176554$10584_Y + attribute \src "libresoc.v:176557.18-176557.106" + wire $reduce_or$libresoc.v:176557$10587_Y + attribute \src "libresoc.v:176559.18-176559.106" + wire $reduce_or$libresoc.v:176559$10589_Y + attribute \src "libresoc.v:176561.18-176561.106" + wire $reduce_or$libresoc.v:176561$10591_Y + attribute \src "libresoc.v:176563.18-176563.90" + wire $reduce_or$libresoc.v:176563$10593_Y + attribute \src "libresoc.v:176564.17-176564.103" + wire $reduce_or$libresoc.v:176564$10594_Y + attribute \src "libresoc.v:176566.17-176566.105" + wire $reduce_or$libresoc.v:176566$10596_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -362233,149 +359043,149 @@ module \rdpick_INT_rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176552$10581 + cell $not $not$libresoc.v:176551$10581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176552$10581_Y + connect \Y $not$libresoc.v:176551$10581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176554$10583 + cell $not $not$libresoc.v:176553$10583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:176554$10583_Y + connect \Y $not$libresoc.v:176553$10583_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176556$10585 + cell $not $not$libresoc.v:176555$10585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:176556$10585_Y + connect \Y $not$libresoc.v:176555$10585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176557$10586 + cell $not $not$libresoc.v:176556$10586 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A \i - connect \Y $not$libresoc.v:176557$10586_Y + connect \Y $not$libresoc.v:176556$10586_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176559$10588 + cell $not $not$libresoc.v:176558$10588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:176559$10588_Y + connect \Y $not$libresoc.v:176558$10588_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176561$10590 + cell $not $not$libresoc.v:176560$10590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:176561$10590_Y + connect \Y $not$libresoc.v:176560$10590_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176563$10592 + cell $not $not$libresoc.v:176562$10592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:176563$10592_Y + connect \Y $not$libresoc.v:176562$10592_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176566$10595 + cell $not $not$libresoc.v:176565$10595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176566$10595_Y + connect \Y $not$libresoc.v:176565$10595_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176553$10582 + cell $reduce_or $reduce_or$libresoc.v:176552$10582 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:176553$10582_Y + connect \Y $reduce_or$libresoc.v:176552$10582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176555$10584 + cell $reduce_or $reduce_or$libresoc.v:176554$10584 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:176555$10584_Y + connect \Y $reduce_or$libresoc.v:176554$10584_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176558$10587 + cell $reduce_or $reduce_or$libresoc.v:176557$10587 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:176558$10587_Y + connect \Y $reduce_or$libresoc.v:176557$10587_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176560$10589 + cell $reduce_or $reduce_or$libresoc.v:176559$10589 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:176560$10589_Y + connect \Y $reduce_or$libresoc.v:176559$10589_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176562$10591 + cell $reduce_or $reduce_or$libresoc.v:176561$10591 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:176562$10591_Y + connect \Y $reduce_or$libresoc.v:176561$10591_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176564$10593 + cell $reduce_or $reduce_or$libresoc.v:176563$10593 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176564$10593_Y + connect \Y $reduce_or$libresoc.v:176563$10593_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176565$10594 + cell $reduce_or $reduce_or$libresoc.v:176564$10594 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176565$10594_Y + connect \Y $reduce_or$libresoc.v:176564$10594_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176567$10596 + cell $reduce_or $reduce_or$libresoc.v:176566$10596 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:176567$10596_Y - end - connect \$7 $not$libresoc.v:176552$10581_Y - connect \$12 $reduce_or$libresoc.v:176553$10582_Y - connect \$11 $not$libresoc.v:176554$10583_Y - connect \$16 $reduce_or$libresoc.v:176555$10584_Y - connect \$15 $not$libresoc.v:176556$10585_Y - connect \$1 $not$libresoc.v:176557$10586_Y - connect \$20 $reduce_or$libresoc.v:176558$10587_Y - connect \$19 $not$libresoc.v:176559$10588_Y - connect \$24 $reduce_or$libresoc.v:176560$10589_Y - connect \$23 $not$libresoc.v:176561$10590_Y - connect \$28 $reduce_or$libresoc.v:176562$10591_Y - connect \$27 $not$libresoc.v:176563$10592_Y - connect \$31 $reduce_or$libresoc.v:176564$10593_Y - connect \$4 $reduce_or$libresoc.v:176565$10594_Y - connect \$3 $not$libresoc.v:176566$10595_Y - connect \$8 $reduce_or$libresoc.v:176567$10596_Y + connect \Y $reduce_or$libresoc.v:176566$10596_Y + end + connect \$7 $not$libresoc.v:176551$10581_Y + connect \$12 $reduce_or$libresoc.v:176552$10582_Y + connect \$11 $not$libresoc.v:176553$10583_Y + connect \$16 $reduce_or$libresoc.v:176554$10584_Y + connect \$15 $not$libresoc.v:176555$10585_Y + connect \$1 $not$libresoc.v:176556$10586_Y + connect \$20 $reduce_or$libresoc.v:176557$10587_Y + connect \$19 $not$libresoc.v:176558$10588_Y + connect \$24 $reduce_or$libresoc.v:176559$10589_Y + connect \$23 $not$libresoc.v:176560$10590_Y + connect \$28 $reduce_or$libresoc.v:176561$10591_Y + connect \$27 $not$libresoc.v:176562$10592_Y + connect \$31 $reduce_or$libresoc.v:176563$10593_Y + connect \$4 $reduce_or$libresoc.v:176564$10594_Y + connect \$3 $not$libresoc.v:176565$10595_Y + connect \$8 $reduce_or$libresoc.v:176566$10596_Y connect \en_o \$31 connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t7 \$27 @@ -362388,19 +359198,19 @@ module \rdpick_INT_rb connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176583.1-176613.10" +attribute \src "libresoc.v:176582.1-176612.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rc" attribute \generator "nMigen" module \rdpick_INT_rc - attribute \src "libresoc.v:176604.17-176604.89" - wire width 2 $not$libresoc.v:176604$10597_Y - attribute \src "libresoc.v:176606.17-176606.91" - wire $not$libresoc.v:176606$10599_Y - attribute \src "libresoc.v:176605.17-176605.103" - wire $reduce_or$libresoc.v:176605$10598_Y - attribute \src "libresoc.v:176607.17-176607.89" - wire $reduce_or$libresoc.v:176607$10600_Y + attribute \src "libresoc.v:176603.17-176603.89" + wire width 2 $not$libresoc.v:176603$10597_Y + attribute \src "libresoc.v:176605.17-176605.91" + wire $not$libresoc.v:176605$10599_Y + attribute \src "libresoc.v:176604.17-176604.103" + wire $reduce_or$libresoc.v:176604$10598_Y + attribute \src "libresoc.v:176606.17-176606.89" + wire $reduce_or$libresoc.v:176606$10600_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -362422,56 +359232,56 @@ module \rdpick_INT_rc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176604$10597 + cell $not $not$libresoc.v:176603$10597 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:176604$10597_Y + connect \Y $not$libresoc.v:176603$10597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176606$10599 + cell $not $not$libresoc.v:176605$10599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176606$10599_Y + connect \Y $not$libresoc.v:176605$10599_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176605$10598 + cell $reduce_or $reduce_or$libresoc.v:176604$10598 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176605$10598_Y + connect \Y $reduce_or$libresoc.v:176604$10598_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176607$10600 + cell $reduce_or $reduce_or$libresoc.v:176606$10600 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176607$10600_Y + connect \Y $reduce_or$libresoc.v:176606$10600_Y end - connect \$1 $not$libresoc.v:176604$10597_Y - connect \$4 $reduce_or$libresoc.v:176605$10598_Y - connect \$3 $not$libresoc.v:176606$10599_Y - connect \$7 $reduce_or$libresoc.v:176607$10600_Y + connect \$1 $not$libresoc.v:176603$10597_Y + connect \$4 $reduce_or$libresoc.v:176604$10598_Y + connect \$3 $not$libresoc.v:176605$10599_Y + connect \$7 $reduce_or$libresoc.v:176606$10600_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176617.1-176638.10" +attribute \src "libresoc.v:176616.1-176637.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_SPR_spr1" attribute \generator "nMigen" module \rdpick_SPR_spr1 + attribute \src "libresoc.v:176631.17-176631.89" + wire $not$libresoc.v:176631$10601_Y attribute \src "libresoc.v:176632.17-176632.89" - wire $not$libresoc.v:176632$10601_Y - attribute \src "libresoc.v:176633.17-176633.89" - wire $reduce_or$libresoc.v:176633$10602_Y + wire $reduce_or$libresoc.v:176632$10602_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -362487,45 +359297,45 @@ module \rdpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176632$10601 + cell $not $not$libresoc.v:176631$10601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:176632$10601_Y + connect \Y $not$libresoc.v:176631$10601_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176633$10602 + cell $reduce_or $reduce_or$libresoc.v:176632$10602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176633$10602_Y + connect \Y $reduce_or$libresoc.v:176632$10602_Y end - connect \$1 $not$libresoc.v:176632$10601_Y - connect \$3 $reduce_or$libresoc.v:176633$10602_Y + connect \$1 $not$libresoc.v:176631$10601_Y + connect \$3 $reduce_or$libresoc.v:176632$10602_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:176642.1-176681.10" +attribute \src "libresoc.v:176641.1-176680.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ca" attribute \generator "nMigen" module \rdpick_XER_xer_ca - attribute \src "libresoc.v:176669.17-176669.91" - wire $not$libresoc.v:176669$10603_Y - attribute \src "libresoc.v:176671.17-176671.89" - wire width 3 $not$libresoc.v:176671$10605_Y - attribute \src "libresoc.v:176673.17-176673.91" - wire $not$libresoc.v:176673$10607_Y - attribute \src "libresoc.v:176670.18-176670.90" - wire $reduce_or$libresoc.v:176670$10604_Y - attribute \src "libresoc.v:176672.17-176672.103" - wire $reduce_or$libresoc.v:176672$10606_Y - attribute \src "libresoc.v:176674.17-176674.105" - wire $reduce_or$libresoc.v:176674$10608_Y + attribute \src "libresoc.v:176668.17-176668.91" + wire $not$libresoc.v:176668$10603_Y + attribute \src "libresoc.v:176670.17-176670.89" + wire width 3 $not$libresoc.v:176670$10605_Y + attribute \src "libresoc.v:176672.17-176672.91" + wire $not$libresoc.v:176672$10607_Y + attribute \src "libresoc.v:176669.18-176669.90" + wire $reduce_or$libresoc.v:176669$10604_Y + attribute \src "libresoc.v:176671.17-176671.103" + wire $reduce_or$libresoc.v:176671$10606_Y + attribute \src "libresoc.v:176673.17-176673.105" + wire $reduce_or$libresoc.v:176673$10608_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -362553,59 +359363,59 @@ module \rdpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176669$10603 + cell $not $not$libresoc.v:176668$10603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176669$10603_Y + connect \Y $not$libresoc.v:176668$10603_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176671$10605 + cell $not $not$libresoc.v:176670$10605 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:176671$10605_Y + connect \Y $not$libresoc.v:176670$10605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176673$10607 + cell $not $not$libresoc.v:176672$10607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176673$10607_Y + connect \Y $not$libresoc.v:176672$10607_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176670$10604 + cell $reduce_or $reduce_or$libresoc.v:176669$10604 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176670$10604_Y + connect \Y $reduce_or$libresoc.v:176669$10604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176672$10606 + cell $reduce_or $reduce_or$libresoc.v:176671$10606 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176672$10606_Y + connect \Y $reduce_or$libresoc.v:176671$10606_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176674$10608 + cell $reduce_or $reduce_or$libresoc.v:176673$10608 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:176674$10608_Y - end - connect \$7 $not$libresoc.v:176669$10603_Y - connect \$11 $reduce_or$libresoc.v:176670$10604_Y - connect \$1 $not$libresoc.v:176671$10605_Y - connect \$4 $reduce_or$libresoc.v:176672$10606_Y - connect \$3 $not$libresoc.v:176673$10607_Y - connect \$8 $reduce_or$libresoc.v:176674$10608_Y + connect \Y $reduce_or$libresoc.v:176673$10608_Y + end + connect \$7 $not$libresoc.v:176668$10603_Y + connect \$11 $reduce_or$libresoc.v:176669$10604_Y + connect \$1 $not$libresoc.v:176670$10605_Y + connect \$4 $reduce_or$libresoc.v:176671$10606_Y + connect \$3 $not$libresoc.v:176672$10607_Y + connect \$8 $reduce_or$libresoc.v:176673$10608_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -362613,15 +359423,15 @@ module \rdpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176685.1-176706.10" +attribute \src "libresoc.v:176684.1-176705.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ov" attribute \generator "nMigen" module \rdpick_XER_xer_ov + attribute \src "libresoc.v:176699.17-176699.89" + wire $not$libresoc.v:176699$10609_Y attribute \src "libresoc.v:176700.17-176700.89" - wire $not$libresoc.v:176700$10609_Y - attribute \src "libresoc.v:176701.17-176701.89" - wire $reduce_or$libresoc.v:176701$10610_Y + wire $reduce_or$libresoc.v:176700$10610_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -362637,57 +359447,57 @@ module \rdpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176700$10609 + cell $not $not$libresoc.v:176699$10609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:176700$10609_Y + connect \Y $not$libresoc.v:176699$10609_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176701$10610 + cell $reduce_or $reduce_or$libresoc.v:176700$10610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176701$10610_Y + connect \Y $reduce_or$libresoc.v:176700$10610_Y end - connect \$1 $not$libresoc.v:176700$10609_Y - connect \$3 $reduce_or$libresoc.v:176701$10610_Y + connect \$1 $not$libresoc.v:176699$10609_Y + connect \$3 $reduce_or$libresoc.v:176700$10610_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:176710.1-176776.10" +attribute \src "libresoc.v:176709.1-176775.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_so" attribute \generator "nMigen" module \rdpick_XER_xer_so - attribute \src "libresoc.v:176755.17-176755.91" - wire $not$libresoc.v:176755$10611_Y - attribute \src "libresoc.v:176757.18-176757.93" - wire $not$libresoc.v:176757$10613_Y - attribute \src "libresoc.v:176759.18-176759.93" - wire $not$libresoc.v:176759$10615_Y - attribute \src "libresoc.v:176760.17-176760.89" - wire width 6 $not$libresoc.v:176760$10616_Y - attribute \src "libresoc.v:176762.18-176762.93" - wire $not$libresoc.v:176762$10618_Y - attribute \src "libresoc.v:176765.17-176765.91" - wire $not$libresoc.v:176765$10621_Y - attribute \src "libresoc.v:176756.18-176756.106" - wire $reduce_or$libresoc.v:176756$10612_Y - attribute \src "libresoc.v:176758.18-176758.106" - wire $reduce_or$libresoc.v:176758$10614_Y - attribute \src "libresoc.v:176761.18-176761.106" - wire $reduce_or$libresoc.v:176761$10617_Y - attribute \src "libresoc.v:176763.18-176763.90" - wire $reduce_or$libresoc.v:176763$10619_Y - attribute \src "libresoc.v:176764.17-176764.103" - wire $reduce_or$libresoc.v:176764$10620_Y - attribute \src "libresoc.v:176766.17-176766.105" - wire $reduce_or$libresoc.v:176766$10622_Y + attribute \src "libresoc.v:176754.17-176754.91" + wire $not$libresoc.v:176754$10611_Y + attribute \src "libresoc.v:176756.18-176756.93" + wire $not$libresoc.v:176756$10613_Y + attribute \src "libresoc.v:176758.18-176758.93" + wire $not$libresoc.v:176758$10615_Y + attribute \src "libresoc.v:176759.17-176759.89" + wire width 6 $not$libresoc.v:176759$10616_Y + attribute \src "libresoc.v:176761.18-176761.93" + wire $not$libresoc.v:176761$10618_Y + attribute \src "libresoc.v:176764.17-176764.91" + wire $not$libresoc.v:176764$10621_Y + attribute \src "libresoc.v:176755.18-176755.106" + wire $reduce_or$libresoc.v:176755$10612_Y + attribute \src "libresoc.v:176757.18-176757.106" + wire $reduce_or$libresoc.v:176757$10614_Y + attribute \src "libresoc.v:176760.18-176760.106" + wire $reduce_or$libresoc.v:176760$10617_Y + attribute \src "libresoc.v:176762.18-176762.90" + wire $reduce_or$libresoc.v:176762$10619_Y + attribute \src "libresoc.v:176763.17-176763.103" + wire $reduce_or$libresoc.v:176763$10620_Y + attribute \src "libresoc.v:176765.17-176765.105" + wire $reduce_or$libresoc.v:176765$10622_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -362733,113 +359543,113 @@ module \rdpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176755$10611 + cell $not $not$libresoc.v:176754$10611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176755$10611_Y + connect \Y $not$libresoc.v:176754$10611_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176757$10613 + cell $not $not$libresoc.v:176756$10613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:176757$10613_Y + connect \Y $not$libresoc.v:176756$10613_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176759$10615 + cell $not $not$libresoc.v:176758$10615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:176759$10615_Y + connect \Y $not$libresoc.v:176758$10615_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176760$10616 + cell $not $not$libresoc.v:176759$10616 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:176760$10616_Y + connect \Y $not$libresoc.v:176759$10616_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176762$10618 + cell $not $not$libresoc.v:176761$10618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:176762$10618_Y + connect \Y $not$libresoc.v:176761$10618_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176765$10621 + cell $not $not$libresoc.v:176764$10621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176765$10621_Y + connect \Y $not$libresoc.v:176764$10621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176756$10612 + cell $reduce_or $reduce_or$libresoc.v:176755$10612 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:176756$10612_Y + connect \Y $reduce_or$libresoc.v:176755$10612_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176758$10614 + cell $reduce_or $reduce_or$libresoc.v:176757$10614 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:176758$10614_Y + connect \Y $reduce_or$libresoc.v:176757$10614_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176761$10617 + cell $reduce_or $reduce_or$libresoc.v:176760$10617 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:176761$10617_Y + connect \Y $reduce_or$libresoc.v:176760$10617_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176763$10619 + cell $reduce_or $reduce_or$libresoc.v:176762$10619 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176763$10619_Y + connect \Y $reduce_or$libresoc.v:176762$10619_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176764$10620 + cell $reduce_or $reduce_or$libresoc.v:176763$10620 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176764$10620_Y + connect \Y $reduce_or$libresoc.v:176763$10620_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176766$10622 + cell $reduce_or $reduce_or$libresoc.v:176765$10622 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:176766$10622_Y - end - connect \$7 $not$libresoc.v:176755$10611_Y - connect \$12 $reduce_or$libresoc.v:176756$10612_Y - connect \$11 $not$libresoc.v:176757$10613_Y - connect \$16 $reduce_or$libresoc.v:176758$10614_Y - connect \$15 $not$libresoc.v:176759$10615_Y - connect \$1 $not$libresoc.v:176760$10616_Y - connect \$20 $reduce_or$libresoc.v:176761$10617_Y - connect \$19 $not$libresoc.v:176762$10618_Y - connect \$23 $reduce_or$libresoc.v:176763$10619_Y - connect \$4 $reduce_or$libresoc.v:176764$10620_Y - connect \$3 $not$libresoc.v:176765$10621_Y - connect \$8 $reduce_or$libresoc.v:176766$10622_Y + connect \Y $reduce_or$libresoc.v:176765$10622_Y + end + connect \$7 $not$libresoc.v:176754$10611_Y + connect \$12 $reduce_or$libresoc.v:176755$10612_Y + connect \$11 $not$libresoc.v:176756$10613_Y + connect \$16 $reduce_or$libresoc.v:176757$10614_Y + connect \$15 $not$libresoc.v:176758$10615_Y + connect \$1 $not$libresoc.v:176759$10616_Y + connect \$20 $reduce_or$libresoc.v:176760$10617_Y + connect \$19 $not$libresoc.v:176761$10618_Y + connect \$23 $reduce_or$libresoc.v:176762$10619_Y + connect \$4 $reduce_or$libresoc.v:176763$10620_Y + connect \$3 $not$libresoc.v:176764$10621_Y + connect \$8 $reduce_or$libresoc.v:176765$10622_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -362850,207 +359660,207 @@ module \rdpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176780.1-177335.10" +attribute \src "libresoc.v:176779.1-177334.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_0" attribute \generator "nMigen" module \reg_0 - attribute \src "libresoc.v:176888.3-176927.6" + attribute \src "libresoc.v:176887.3-176926.6" wire width 4 $0\cr_pred0__data_o$next[3:0]$10637 - attribute \src "libresoc.v:176886.3-176887.49" + attribute \src "libresoc.v:176885.3-176886.49" wire width 4 $0\cr_pred0__data_o[3:0] - attribute \src "libresoc.v:176781.7-176781.20" + attribute \src "libresoc.v:176780.7-176780.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177265.3-177304.6" + attribute \src "libresoc.v:177264.3-177303.6" wire width 4 $0\r0__data_o$next[3:0]$10708 - attribute \src "libresoc.v:176878.3-176879.37" + attribute \src "libresoc.v:176877.3-176878.37" wire width 4 $0\r0__data_o[3:0] - attribute \src "libresoc.v:176958.3-176997.6" + attribute \src "libresoc.v:176957.3-176996.6" wire width 4 $0\r20__data_o$next[3:0]$10646 - attribute \src "libresoc.v:176876.3-176877.39" + attribute \src "libresoc.v:176875.3-176876.39" wire width 4 $0\r20__data_o[3:0] - attribute \src "libresoc.v:177028.3-177054.6" + attribute \src "libresoc.v:177027.3-177053.6" wire width 4 $0\reg$next[3:0]$10660 - attribute \src "libresoc.v:176874.3-176875.25" + attribute \src "libresoc.v:176873.3-176874.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:177055.3-177094.6" + attribute \src "libresoc.v:177054.3-177093.6" wire width 4 $0\src10__data_o$next[3:0]$10666 - attribute \src "libresoc.v:176884.3-176885.43" + attribute \src "libresoc.v:176883.3-176884.43" wire width 4 $0\src10__data_o[3:0] - attribute \src "libresoc.v:177125.3-177164.6" + attribute \src "libresoc.v:177124.3-177163.6" wire width 4 $0\src20__data_o$next[3:0]$10680 - attribute \src "libresoc.v:176882.3-176883.43" + attribute \src "libresoc.v:176881.3-176882.43" wire width 4 $0\src20__data_o[3:0] - attribute \src "libresoc.v:177195.3-177234.6" + attribute \src "libresoc.v:177194.3-177233.6" wire width 4 $0\src30__data_o$next[3:0]$10694 - attribute \src "libresoc.v:176880.3-176881.43" + attribute \src "libresoc.v:176879.3-176880.43" wire width 4 $0\src30__data_o[3:0] - attribute \src "libresoc.v:177235.3-177264.6" + attribute \src "libresoc.v:177234.3-177263.6" wire $0\wr_detect$10[0:0]$10702 - attribute \src "libresoc.v:177305.3-177334.6" + attribute \src "libresoc.v:177304.3-177333.6" wire $0\wr_detect$13[0:0]$10716 - attribute \src "libresoc.v:176998.3-177027.6" + attribute \src "libresoc.v:176997.3-177026.6" wire $0\wr_detect$16[0:0]$10654 - attribute \src "libresoc.v:177095.3-177124.6" + attribute \src "libresoc.v:177094.3-177123.6" wire $0\wr_detect$4[0:0]$10674 - attribute \src "libresoc.v:177165.3-177194.6" + attribute \src "libresoc.v:177164.3-177193.6" wire $0\wr_detect$7[0:0]$10688 - attribute \src "libresoc.v:176928.3-176957.6" + attribute \src "libresoc.v:176927.3-176956.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:176888.3-176927.6" + attribute \src "libresoc.v:176887.3-176926.6" wire width 4 $1\cr_pred0__data_o$next[3:0]$10638 - attribute \src "libresoc.v:176800.13-176800.36" + attribute \src "libresoc.v:176799.13-176799.36" wire width 4 $1\cr_pred0__data_o[3:0] - attribute \src "libresoc.v:177265.3-177304.6" + attribute \src "libresoc.v:177264.3-177303.6" wire width 4 $1\r0__data_o$next[3:0]$10709 - attribute \src "libresoc.v:176815.13-176815.30" + attribute \src "libresoc.v:176814.13-176814.30" wire width 4 $1\r0__data_o[3:0] - attribute \src "libresoc.v:176958.3-176997.6" + attribute \src "libresoc.v:176957.3-176996.6" wire width 4 $1\r20__data_o$next[3:0]$10647 - attribute \src "libresoc.v:176822.13-176822.31" + attribute \src "libresoc.v:176821.13-176821.31" wire width 4 $1\r20__data_o[3:0] - attribute \src "libresoc.v:177028.3-177054.6" + attribute \src "libresoc.v:177027.3-177053.6" wire width 4 $1\reg$next[3:0]$10661 - attribute \src "libresoc.v:176828.13-176828.25" + attribute \src "libresoc.v:176827.13-176827.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:177055.3-177094.6" + attribute \src "libresoc.v:177054.3-177093.6" wire width 4 $1\src10__data_o$next[3:0]$10667 - attribute \src "libresoc.v:176833.13-176833.33" + attribute \src "libresoc.v:176832.13-176832.33" wire width 4 $1\src10__data_o[3:0] - attribute \src "libresoc.v:177125.3-177164.6" + attribute \src "libresoc.v:177124.3-177163.6" wire width 4 $1\src20__data_o$next[3:0]$10681 - attribute \src "libresoc.v:176840.13-176840.33" + attribute \src "libresoc.v:176839.13-176839.33" wire width 4 $1\src20__data_o[3:0] - attribute \src "libresoc.v:177195.3-177234.6" + attribute \src "libresoc.v:177194.3-177233.6" wire width 4 $1\src30__data_o$next[3:0]$10695 - attribute \src "libresoc.v:176847.13-176847.33" + attribute \src "libresoc.v:176846.13-176846.33" wire width 4 $1\src30__data_o[3:0] - attribute \src "libresoc.v:177235.3-177264.6" + attribute \src "libresoc.v:177234.3-177263.6" wire $1\wr_detect$10[0:0]$10703 - attribute \src "libresoc.v:177305.3-177334.6" + attribute \src "libresoc.v:177304.3-177333.6" wire $1\wr_detect$13[0:0]$10717 - attribute \src "libresoc.v:176998.3-177027.6" + attribute \src "libresoc.v:176997.3-177026.6" wire $1\wr_detect$16[0:0]$10655 - attribute \src "libresoc.v:177095.3-177124.6" + attribute \src "libresoc.v:177094.3-177123.6" wire $1\wr_detect$4[0:0]$10675 - attribute \src "libresoc.v:177165.3-177194.6" + attribute \src "libresoc.v:177164.3-177193.6" wire $1\wr_detect$7[0:0]$10689 - attribute \src "libresoc.v:176928.3-176957.6" + attribute \src "libresoc.v:176927.3-176956.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:176888.3-176927.6" + attribute \src "libresoc.v:176887.3-176926.6" wire width 4 $2\cr_pred0__data_o$next[3:0]$10639 - attribute \src "libresoc.v:177265.3-177304.6" + attribute \src "libresoc.v:177264.3-177303.6" wire width 4 $2\r0__data_o$next[3:0]$10710 - attribute \src "libresoc.v:176958.3-176997.6" + attribute \src "libresoc.v:176957.3-176996.6" wire width 4 $2\r20__data_o$next[3:0]$10648 - attribute \src "libresoc.v:177028.3-177054.6" + attribute \src "libresoc.v:177027.3-177053.6" wire width 4 $2\reg$next[3:0]$10662 - attribute \src "libresoc.v:177055.3-177094.6" + attribute \src "libresoc.v:177054.3-177093.6" wire width 4 $2\src10__data_o$next[3:0]$10668 - attribute \src "libresoc.v:177125.3-177164.6" + attribute \src "libresoc.v:177124.3-177163.6" wire width 4 $2\src20__data_o$next[3:0]$10682 - attribute \src "libresoc.v:177195.3-177234.6" + attribute \src "libresoc.v:177194.3-177233.6" wire width 4 $2\src30__data_o$next[3:0]$10696 - attribute \src "libresoc.v:177235.3-177264.6" + attribute \src "libresoc.v:177234.3-177263.6" wire $2\wr_detect$10[0:0]$10704 - attribute \src "libresoc.v:177305.3-177334.6" + attribute \src "libresoc.v:177304.3-177333.6" wire $2\wr_detect$13[0:0]$10718 - attribute \src "libresoc.v:176998.3-177027.6" + attribute \src "libresoc.v:176997.3-177026.6" wire $2\wr_detect$16[0:0]$10656 - attribute \src "libresoc.v:177095.3-177124.6" + attribute \src "libresoc.v:177094.3-177123.6" wire $2\wr_detect$4[0:0]$10676 - attribute \src "libresoc.v:177165.3-177194.6" + attribute \src "libresoc.v:177164.3-177193.6" wire $2\wr_detect$7[0:0]$10690 - attribute \src "libresoc.v:176928.3-176957.6" + attribute \src "libresoc.v:176927.3-176956.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:176888.3-176927.6" + attribute \src "libresoc.v:176887.3-176926.6" wire width 4 $3\cr_pred0__data_o$next[3:0]$10640 - attribute \src "libresoc.v:177265.3-177304.6" + attribute \src "libresoc.v:177264.3-177303.6" wire width 4 $3\r0__data_o$next[3:0]$10711 - attribute \src "libresoc.v:176958.3-176997.6" + attribute \src "libresoc.v:176957.3-176996.6" wire width 4 $3\r20__data_o$next[3:0]$10649 - attribute \src "libresoc.v:177028.3-177054.6" + attribute \src "libresoc.v:177027.3-177053.6" wire width 4 $3\reg$next[3:0]$10663 - attribute \src "libresoc.v:177055.3-177094.6" + attribute \src "libresoc.v:177054.3-177093.6" wire width 4 $3\src10__data_o$next[3:0]$10669 - attribute \src "libresoc.v:177125.3-177164.6" + attribute \src "libresoc.v:177124.3-177163.6" wire width 4 $3\src20__data_o$next[3:0]$10683 - attribute \src "libresoc.v:177195.3-177234.6" + attribute \src "libresoc.v:177194.3-177233.6" wire width 4 $3\src30__data_o$next[3:0]$10697 - attribute \src "libresoc.v:177235.3-177264.6" + attribute \src "libresoc.v:177234.3-177263.6" wire $3\wr_detect$10[0:0]$10705 - attribute \src "libresoc.v:177305.3-177334.6" + attribute \src "libresoc.v:177304.3-177333.6" wire $3\wr_detect$13[0:0]$10719 - attribute \src "libresoc.v:176998.3-177027.6" + attribute \src "libresoc.v:176997.3-177026.6" wire $3\wr_detect$16[0:0]$10657 - attribute \src "libresoc.v:177095.3-177124.6" + attribute \src "libresoc.v:177094.3-177123.6" wire $3\wr_detect$4[0:0]$10677 - attribute \src "libresoc.v:177165.3-177194.6" + attribute \src "libresoc.v:177164.3-177193.6" wire $3\wr_detect$7[0:0]$10691 - attribute \src "libresoc.v:176928.3-176957.6" + attribute \src "libresoc.v:176927.3-176956.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:176888.3-176927.6" + attribute \src "libresoc.v:176887.3-176926.6" wire width 4 $4\cr_pred0__data_o$next[3:0]$10641 - attribute \src "libresoc.v:177265.3-177304.6" + attribute \src "libresoc.v:177264.3-177303.6" wire width 4 $4\r0__data_o$next[3:0]$10712 - attribute \src "libresoc.v:176958.3-176997.6" + attribute \src "libresoc.v:176957.3-176996.6" wire width 4 $4\r20__data_o$next[3:0]$10650 - attribute \src "libresoc.v:177028.3-177054.6" + attribute \src "libresoc.v:177027.3-177053.6" wire width 4 $4\reg$next[3:0]$10664 - attribute \src "libresoc.v:177055.3-177094.6" + attribute \src "libresoc.v:177054.3-177093.6" wire width 4 $4\src10__data_o$next[3:0]$10670 - attribute \src "libresoc.v:177125.3-177164.6" + attribute \src "libresoc.v:177124.3-177163.6" wire width 4 $4\src20__data_o$next[3:0]$10684 - attribute \src "libresoc.v:177195.3-177234.6" + attribute \src "libresoc.v:177194.3-177233.6" wire width 4 $4\src30__data_o$next[3:0]$10698 - attribute \src "libresoc.v:177235.3-177264.6" + attribute \src "libresoc.v:177234.3-177263.6" wire $4\wr_detect$10[0:0]$10706 - attribute \src "libresoc.v:177305.3-177334.6" + attribute \src "libresoc.v:177304.3-177333.6" wire $4\wr_detect$13[0:0]$10720 - attribute \src "libresoc.v:176998.3-177027.6" + attribute \src "libresoc.v:176997.3-177026.6" wire $4\wr_detect$16[0:0]$10658 - attribute \src "libresoc.v:177095.3-177124.6" + attribute \src "libresoc.v:177094.3-177123.6" wire $4\wr_detect$4[0:0]$10678 - attribute \src "libresoc.v:177165.3-177194.6" + attribute \src "libresoc.v:177164.3-177193.6" wire $4\wr_detect$7[0:0]$10692 - attribute \src "libresoc.v:176928.3-176957.6" + attribute \src "libresoc.v:176927.3-176956.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:176888.3-176927.6" + attribute \src "libresoc.v:176887.3-176926.6" wire width 4 $5\cr_pred0__data_o$next[3:0]$10642 - attribute \src "libresoc.v:177265.3-177304.6" + attribute \src "libresoc.v:177264.3-177303.6" wire width 4 $5\r0__data_o$next[3:0]$10713 - attribute \src "libresoc.v:176958.3-176997.6" + attribute \src "libresoc.v:176957.3-176996.6" wire width 4 $5\r20__data_o$next[3:0]$10651 - attribute \src "libresoc.v:177055.3-177094.6" + attribute \src "libresoc.v:177054.3-177093.6" wire width 4 $5\src10__data_o$next[3:0]$10671 - attribute \src "libresoc.v:177125.3-177164.6" + attribute \src "libresoc.v:177124.3-177163.6" wire width 4 $5\src20__data_o$next[3:0]$10685 - attribute \src "libresoc.v:177195.3-177234.6" + attribute \src "libresoc.v:177194.3-177233.6" wire width 4 $5\src30__data_o$next[3:0]$10699 - attribute \src "libresoc.v:176888.3-176927.6" + attribute \src "libresoc.v:176887.3-176926.6" wire width 4 $6\cr_pred0__data_o$next[3:0]$10643 - attribute \src "libresoc.v:177265.3-177304.6" + attribute \src "libresoc.v:177264.3-177303.6" wire width 4 $6\r0__data_o$next[3:0]$10714 - attribute \src "libresoc.v:176958.3-176997.6" + attribute \src "libresoc.v:176957.3-176996.6" wire width 4 $6\r20__data_o$next[3:0]$10652 - attribute \src "libresoc.v:177055.3-177094.6" + attribute \src "libresoc.v:177054.3-177093.6" wire width 4 $6\src10__data_o$next[3:0]$10672 - attribute \src "libresoc.v:177125.3-177164.6" + attribute \src "libresoc.v:177124.3-177163.6" wire width 4 $6\src20__data_o$next[3:0]$10686 - attribute \src "libresoc.v:177195.3-177234.6" + attribute \src "libresoc.v:177194.3-177233.6" wire width 4 $6\src30__data_o$next[3:0]$10700 - attribute \src "libresoc.v:176868.17-176868.104" - wire $not$libresoc.v:176868$10623_Y + attribute \src "libresoc.v:176867.17-176867.104" + wire $not$libresoc.v:176867$10623_Y + attribute \src "libresoc.v:176868.18-176868.105" + wire $not$libresoc.v:176868$10624_Y attribute \src "libresoc.v:176869.18-176869.105" - wire $not$libresoc.v:176869$10624_Y - attribute \src "libresoc.v:176870.18-176870.105" - wire $not$libresoc.v:176870$10625_Y - attribute \src "libresoc.v:176871.17-176871.100" - wire $not$libresoc.v:176871$10626_Y + wire $not$libresoc.v:176869$10625_Y + attribute \src "libresoc.v:176870.17-176870.100" + wire $not$libresoc.v:176870$10626_Y + attribute \src "libresoc.v:176871.17-176871.103" + wire $not$libresoc.v:176871$10627_Y attribute \src "libresoc.v:176872.17-176872.103" - wire $not$libresoc.v:176872$10627_Y - attribute \src "libresoc.v:176873.17-176873.103" - wire $not$libresoc.v:176873$10628_Y + wire $not$libresoc.v:176872$10628_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -363081,7 +359891,7 @@ module \reg_0 wire width 4 input 13 \dest20__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest20__wen - attribute \src "libresoc.v:176781.7-176781.15" + attribute \src "libresoc.v:176780.7-176780.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r0__data_o @@ -363134,175 +359944,175 @@ module \reg_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176868$10623 + cell $not $not$libresoc.v:176867$10623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:176868$10623_Y + connect \Y $not$libresoc.v:176867$10623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176869$10624 + cell $not $not$libresoc.v:176868$10624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:176869$10624_Y + connect \Y $not$libresoc.v:176868$10624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176870$10625 + cell $not $not$libresoc.v:176869$10625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$16 - connect \Y $not$libresoc.v:176870$10625_Y + connect \Y $not$libresoc.v:176869$10625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176871$10626 + cell $not $not$libresoc.v:176870$10626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:176871$10626_Y + connect \Y $not$libresoc.v:176870$10626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176872$10627 + cell $not $not$libresoc.v:176871$10627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:176872$10627_Y + connect \Y $not$libresoc.v:176871$10627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176873$10628 + cell $not $not$libresoc.v:176872$10628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:176873$10628_Y + connect \Y $not$libresoc.v:176872$10628_Y end - attribute \src "libresoc.v:176781.7-176781.20" - process $proc$libresoc.v:176781$10721 + attribute \src "libresoc.v:176780.7-176780.20" + process $proc$libresoc.v:176780$10721 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:176800.13-176800.36" - process $proc$libresoc.v:176800$10722 + attribute \src "libresoc.v:176799.13-176799.36" + process $proc$libresoc.v:176799$10722 assign { } { } assign $1\cr_pred0__data_o[3:0] 4'0000 sync always sync init update \cr_pred0__data_o $1\cr_pred0__data_o[3:0] end - attribute \src "libresoc.v:176815.13-176815.30" - process $proc$libresoc.v:176815$10723 + attribute \src "libresoc.v:176814.13-176814.30" + process $proc$libresoc.v:176814$10723 assign { } { } assign $1\r0__data_o[3:0] 4'0000 sync always sync init update \r0__data_o $1\r0__data_o[3:0] end - attribute \src "libresoc.v:176822.13-176822.31" - process $proc$libresoc.v:176822$10724 + attribute \src "libresoc.v:176821.13-176821.31" + process $proc$libresoc.v:176821$10724 assign { } { } assign $1\r20__data_o[3:0] 4'0000 sync always sync init update \r20__data_o $1\r20__data_o[3:0] end - attribute \src "libresoc.v:176828.13-176828.25" - process $proc$libresoc.v:176828$10725 + attribute \src "libresoc.v:176827.13-176827.25" + process $proc$libresoc.v:176827$10725 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:176833.13-176833.33" - process $proc$libresoc.v:176833$10726 + attribute \src "libresoc.v:176832.13-176832.33" + process $proc$libresoc.v:176832$10726 assign { } { } assign $1\src10__data_o[3:0] 4'0000 sync always sync init update \src10__data_o $1\src10__data_o[3:0] end - attribute \src "libresoc.v:176840.13-176840.33" - process $proc$libresoc.v:176840$10727 + attribute \src "libresoc.v:176839.13-176839.33" + process $proc$libresoc.v:176839$10727 assign { } { } assign $1\src20__data_o[3:0] 4'0000 sync always sync init update \src20__data_o $1\src20__data_o[3:0] end - attribute \src "libresoc.v:176847.13-176847.33" - process $proc$libresoc.v:176847$10728 + attribute \src "libresoc.v:176846.13-176846.33" + process $proc$libresoc.v:176846$10728 assign { } { } assign $1\src30__data_o[3:0] 4'0000 sync always sync init update \src30__data_o $1\src30__data_o[3:0] end - attribute \src "libresoc.v:176874.3-176875.25" - process $proc$libresoc.v:176874$10629 + attribute \src "libresoc.v:176873.3-176874.25" + process $proc$libresoc.v:176873$10629 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:176876.3-176877.39" - process $proc$libresoc.v:176876$10630 + attribute \src "libresoc.v:176875.3-176876.39" + process $proc$libresoc.v:176875$10630 assign { } { } assign $0\r20__data_o[3:0] \r20__data_o$next sync posedge \coresync_clk update \r20__data_o $0\r20__data_o[3:0] end - attribute \src "libresoc.v:176878.3-176879.37" - process $proc$libresoc.v:176878$10631 + attribute \src "libresoc.v:176877.3-176878.37" + process $proc$libresoc.v:176877$10631 assign { } { } assign $0\r0__data_o[3:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[3:0] end - attribute \src "libresoc.v:176880.3-176881.43" - process $proc$libresoc.v:176880$10632 + attribute \src "libresoc.v:176879.3-176880.43" + process $proc$libresoc.v:176879$10632 assign { } { } assign $0\src30__data_o[3:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[3:0] end - attribute \src "libresoc.v:176882.3-176883.43" - process $proc$libresoc.v:176882$10633 + attribute \src "libresoc.v:176881.3-176882.43" + process $proc$libresoc.v:176881$10633 assign { } { } assign $0\src20__data_o[3:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[3:0] end - attribute \src "libresoc.v:176884.3-176885.43" - process $proc$libresoc.v:176884$10634 + attribute \src "libresoc.v:176883.3-176884.43" + process $proc$libresoc.v:176883$10634 assign { } { } assign $0\src10__data_o[3:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[3:0] end - attribute \src "libresoc.v:176886.3-176887.49" - process $proc$libresoc.v:176886$10635 + attribute \src "libresoc.v:176885.3-176886.49" + process $proc$libresoc.v:176885$10635 assign { } { } assign $0\cr_pred0__data_o[3:0] \cr_pred0__data_o$next sync posedge \coresync_clk update \cr_pred0__data_o $0\cr_pred0__data_o[3:0] end - attribute \src "libresoc.v:176888.3-176927.6" - process $proc$libresoc.v:176888$10636 + attribute \src "libresoc.v:176887.3-176926.6" + process $proc$libresoc.v:176887$10636 assign { } { } assign { } { } assign { } { } assign $0\cr_pred0__data_o$next[3:0]$10637 $6\cr_pred0__data_o$next[3:0]$10643 - attribute \src "libresoc.v:176889.5-176889.29" + attribute \src "libresoc.v:176888.5-176888.29" switch \initial - attribute \src "libresoc.v:176889.9-176889.17" + attribute \src "libresoc.v:176888.9-176888.17" case 1'1 case end @@ -363366,14 +360176,14 @@ module \reg_0 sync always update \cr_pred0__data_o$next $0\cr_pred0__data_o$next[3:0]$10637 end - attribute \src "libresoc.v:176928.3-176957.6" - process $proc$libresoc.v:176928$10644 + attribute \src "libresoc.v:176927.3-176956.6" + process $proc$libresoc.v:176927$10644 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:176929.5-176929.29" + attribute \src "libresoc.v:176928.5-176928.29" switch \initial - attribute \src "libresoc.v:176929.9-176929.17" + attribute \src "libresoc.v:176928.9-176928.17" case 1'1 case end @@ -363419,15 +360229,15 @@ module \reg_0 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:176958.3-176997.6" - process $proc$libresoc.v:176958$10645 + attribute \src "libresoc.v:176957.3-176996.6" + process $proc$libresoc.v:176957$10645 assign { } { } assign { } { } assign { } { } assign $0\r20__data_o$next[3:0]$10646 $6\r20__data_o$next[3:0]$10652 - attribute \src "libresoc.v:176959.5-176959.29" + attribute \src "libresoc.v:176958.5-176958.29" switch \initial - attribute \src "libresoc.v:176959.9-176959.17" + attribute \src "libresoc.v:176958.9-176958.17" case 1'1 case end @@ -363491,14 +360301,14 @@ module \reg_0 sync always update \r20__data_o$next $0\r20__data_o$next[3:0]$10646 end - attribute \src "libresoc.v:176998.3-177027.6" - process $proc$libresoc.v:176998$10653 + attribute \src "libresoc.v:176997.3-177026.6" + process $proc$libresoc.v:176997$10653 assign { } { } assign { } { } assign $0\wr_detect$16[0:0]$10654 $1\wr_detect$16[0:0]$10655 - attribute \src "libresoc.v:176999.5-176999.29" + attribute \src "libresoc.v:176998.5-176998.29" switch \initial - attribute \src "libresoc.v:176999.9-176999.17" + attribute \src "libresoc.v:176998.9-176998.17" case 1'1 case end @@ -363544,17 +360354,17 @@ module \reg_0 sync always update \wr_detect$16 $0\wr_detect$16[0:0]$10654 end - attribute \src "libresoc.v:177028.3-177054.6" - process $proc$libresoc.v:177028$10659 + attribute \src "libresoc.v:177027.3-177053.6" + process $proc$libresoc.v:177027$10659 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[3:0]$10660 $4\reg$next[3:0]$10664 - attribute \src "libresoc.v:177029.5-177029.29" + attribute \src "libresoc.v:177028.5-177028.29" switch \initial - attribute \src "libresoc.v:177029.9-177029.17" + attribute \src "libresoc.v:177028.9-177028.17" case 1'1 case end @@ -363597,15 +360407,15 @@ module \reg_0 sync always update \reg$next $0\reg$next[3:0]$10660 end - attribute \src "libresoc.v:177055.3-177094.6" - process $proc$libresoc.v:177055$10665 + attribute \src "libresoc.v:177054.3-177093.6" + process $proc$libresoc.v:177054$10665 assign { } { } assign { } { } assign { } { } assign $0\src10__data_o$next[3:0]$10666 $6\src10__data_o$next[3:0]$10672 - attribute \src "libresoc.v:177056.5-177056.29" + attribute \src "libresoc.v:177055.5-177055.29" switch \initial - attribute \src "libresoc.v:177056.9-177056.17" + attribute \src "libresoc.v:177055.9-177055.17" case 1'1 case end @@ -363669,14 +360479,14 @@ module \reg_0 sync always update \src10__data_o$next $0\src10__data_o$next[3:0]$10666 end - attribute \src "libresoc.v:177095.3-177124.6" - process $proc$libresoc.v:177095$10673 + attribute \src "libresoc.v:177094.3-177123.6" + process $proc$libresoc.v:177094$10673 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$10674 $1\wr_detect$4[0:0]$10675 - attribute \src "libresoc.v:177096.5-177096.29" + attribute \src "libresoc.v:177095.5-177095.29" switch \initial - attribute \src "libresoc.v:177096.9-177096.17" + attribute \src "libresoc.v:177095.9-177095.17" case 1'1 case end @@ -363722,15 +360532,15 @@ module \reg_0 sync always update \wr_detect$4 $0\wr_detect$4[0:0]$10674 end - attribute \src "libresoc.v:177125.3-177164.6" - process $proc$libresoc.v:177125$10679 + attribute \src "libresoc.v:177124.3-177163.6" + process $proc$libresoc.v:177124$10679 assign { } { } assign { } { } assign { } { } assign $0\src20__data_o$next[3:0]$10680 $6\src20__data_o$next[3:0]$10686 - attribute \src "libresoc.v:177126.5-177126.29" + attribute \src "libresoc.v:177125.5-177125.29" switch \initial - attribute \src "libresoc.v:177126.9-177126.17" + attribute \src "libresoc.v:177125.9-177125.17" case 1'1 case end @@ -363794,14 +360604,14 @@ module \reg_0 sync always update \src20__data_o$next $0\src20__data_o$next[3:0]$10680 end - attribute \src "libresoc.v:177165.3-177194.6" - process $proc$libresoc.v:177165$10687 + attribute \src "libresoc.v:177164.3-177193.6" + process $proc$libresoc.v:177164$10687 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$10688 $1\wr_detect$7[0:0]$10689 - attribute \src "libresoc.v:177166.5-177166.29" + attribute \src "libresoc.v:177165.5-177165.29" switch \initial - attribute \src "libresoc.v:177166.9-177166.17" + attribute \src "libresoc.v:177165.9-177165.17" case 1'1 case end @@ -363847,15 +360657,15 @@ module \reg_0 sync always update \wr_detect$7 $0\wr_detect$7[0:0]$10688 end - attribute \src "libresoc.v:177195.3-177234.6" - process $proc$libresoc.v:177195$10693 + attribute \src "libresoc.v:177194.3-177233.6" + process $proc$libresoc.v:177194$10693 assign { } { } assign { } { } assign { } { } assign $0\src30__data_o$next[3:0]$10694 $6\src30__data_o$next[3:0]$10700 - attribute \src "libresoc.v:177196.5-177196.29" + attribute \src "libresoc.v:177195.5-177195.29" switch \initial - attribute \src "libresoc.v:177196.9-177196.17" + attribute \src "libresoc.v:177195.9-177195.17" case 1'1 case end @@ -363919,14 +360729,14 @@ module \reg_0 sync always update \src30__data_o$next $0\src30__data_o$next[3:0]$10694 end - attribute \src "libresoc.v:177235.3-177264.6" - process $proc$libresoc.v:177235$10701 + attribute \src "libresoc.v:177234.3-177263.6" + process $proc$libresoc.v:177234$10701 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$10702 $1\wr_detect$10[0:0]$10703 - attribute \src "libresoc.v:177236.5-177236.29" + attribute \src "libresoc.v:177235.5-177235.29" switch \initial - attribute \src "libresoc.v:177236.9-177236.17" + attribute \src "libresoc.v:177235.9-177235.17" case 1'1 case end @@ -363972,15 +360782,15 @@ module \reg_0 sync always update \wr_detect$10 $0\wr_detect$10[0:0]$10702 end - attribute \src "libresoc.v:177265.3-177304.6" - process $proc$libresoc.v:177265$10707 + attribute \src "libresoc.v:177264.3-177303.6" + process $proc$libresoc.v:177264$10707 assign { } { } assign { } { } assign { } { } assign $0\r0__data_o$next[3:0]$10708 $6\r0__data_o$next[3:0]$10714 - attribute \src "libresoc.v:177266.5-177266.29" + attribute \src "libresoc.v:177265.5-177265.29" switch \initial - attribute \src "libresoc.v:177266.9-177266.17" + attribute \src "libresoc.v:177265.9-177265.17" case 1'1 case end @@ -364044,14 +360854,14 @@ module \reg_0 sync always update \r0__data_o$next $0\r0__data_o$next[3:0]$10708 end - attribute \src "libresoc.v:177305.3-177334.6" - process $proc$libresoc.v:177305$10715 + attribute \src "libresoc.v:177304.3-177333.6" + process $proc$libresoc.v:177304$10715 assign { } { } assign { } { } assign $0\wr_detect$13[0:0]$10716 $1\wr_detect$13[0:0]$10717 - attribute \src "libresoc.v:177306.5-177306.29" + attribute \src "libresoc.v:177305.5-177305.29" switch \initial - attribute \src "libresoc.v:177306.9-177306.17" + attribute \src "libresoc.v:177305.9-177305.17" case 1'1 case end @@ -364097,172 +360907,172 @@ module \reg_0 sync always update \wr_detect$13 $0\wr_detect$13[0:0]$10716 end - connect \$9 $not$libresoc.v:176868$10623_Y - connect \$12 $not$libresoc.v:176869$10624_Y - connect \$15 $not$libresoc.v:176870$10625_Y - connect \$1 $not$libresoc.v:176871$10626_Y - connect \$3 $not$libresoc.v:176872$10627_Y - connect \$6 $not$libresoc.v:176873$10628_Y + connect \$9 $not$libresoc.v:176867$10623_Y + connect \$12 $not$libresoc.v:176868$10624_Y + connect \$15 $not$libresoc.v:176869$10625_Y + connect \$1 $not$libresoc.v:176870$10626_Y + connect \$3 $not$libresoc.v:176871$10627_Y + connect \$6 $not$libresoc.v:176872$10628_Y end -attribute \src "libresoc.v:177339.1-177784.10" +attribute \src "libresoc.v:177338.1-177783.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_0" attribute \generator "nMigen" module \reg_0$132 - attribute \src "libresoc.v:177340.7-177340.20" + attribute \src "libresoc.v:177339.7-177339.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177669.3-177714.6" + attribute \src "libresoc.v:177668.3-177713.6" wire width 2 $0\r0__data_o$next[1:0]$10781 - attribute \src "libresoc.v:177415.3-177416.37" + attribute \src "libresoc.v:177414.3-177415.37" wire width 2 $0\r0__data_o[1:0] - attribute \src "libresoc.v:177751.3-177783.6" + attribute \src "libresoc.v:177750.3-177782.6" wire width 2 $0\reg$next[1:0]$10797 - attribute \src "libresoc.v:177413.3-177414.25" + attribute \src "libresoc.v:177412.3-177413.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:177423.3-177468.6" + attribute \src "libresoc.v:177422.3-177467.6" wire width 2 $0\src10__data_o$next[1:0]$10739 - attribute \src "libresoc.v:177421.3-177422.43" + attribute \src "libresoc.v:177420.3-177421.43" wire width 2 $0\src10__data_o[1:0] - attribute \src "libresoc.v:177505.3-177550.6" + attribute \src "libresoc.v:177504.3-177549.6" wire width 2 $0\src20__data_o$next[1:0]$10749 - attribute \src "libresoc.v:177419.3-177420.43" + attribute \src "libresoc.v:177418.3-177419.43" wire width 2 $0\src20__data_o[1:0] - attribute \src "libresoc.v:177587.3-177632.6" + attribute \src "libresoc.v:177586.3-177631.6" wire width 2 $0\src30__data_o$next[1:0]$10765 - attribute \src "libresoc.v:177417.3-177418.43" + attribute \src "libresoc.v:177416.3-177417.43" wire width 2 $0\src30__data_o[1:0] - attribute \src "libresoc.v:177715.3-177750.6" + attribute \src "libresoc.v:177714.3-177749.6" wire $0\wr_detect$10[0:0]$10790 - attribute \src "libresoc.v:177551.3-177586.6" + attribute \src "libresoc.v:177550.3-177585.6" wire $0\wr_detect$4[0:0]$10758 - attribute \src "libresoc.v:177633.3-177668.6" + attribute \src "libresoc.v:177632.3-177667.6" wire $0\wr_detect$7[0:0]$10774 - attribute \src "libresoc.v:177469.3-177504.6" + attribute \src "libresoc.v:177468.3-177503.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:177669.3-177714.6" + attribute \src "libresoc.v:177668.3-177713.6" wire width 2 $1\r0__data_o$next[1:0]$10782 - attribute \src "libresoc.v:177367.13-177367.30" + attribute \src "libresoc.v:177366.13-177366.30" wire width 2 $1\r0__data_o[1:0] - attribute \src "libresoc.v:177751.3-177783.6" + attribute \src "libresoc.v:177750.3-177782.6" wire width 2 $1\reg$next[1:0]$10798 - attribute \src "libresoc.v:177373.13-177373.25" + attribute \src "libresoc.v:177372.13-177372.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:177423.3-177468.6" + attribute \src "libresoc.v:177422.3-177467.6" wire width 2 $1\src10__data_o$next[1:0]$10740 - attribute \src "libresoc.v:177378.13-177378.33" + attribute \src "libresoc.v:177377.13-177377.33" wire width 2 $1\src10__data_o[1:0] - attribute \src "libresoc.v:177505.3-177550.6" + attribute \src "libresoc.v:177504.3-177549.6" wire width 2 $1\src20__data_o$next[1:0]$10750 - attribute \src "libresoc.v:177385.13-177385.33" + attribute \src "libresoc.v:177384.13-177384.33" wire width 2 $1\src20__data_o[1:0] - attribute \src "libresoc.v:177587.3-177632.6" + attribute \src "libresoc.v:177586.3-177631.6" wire width 2 $1\src30__data_o$next[1:0]$10766 - attribute \src "libresoc.v:177392.13-177392.33" + attribute \src "libresoc.v:177391.13-177391.33" wire width 2 $1\src30__data_o[1:0] - attribute \src "libresoc.v:177715.3-177750.6" + attribute \src "libresoc.v:177714.3-177749.6" wire $1\wr_detect$10[0:0]$10791 - attribute \src "libresoc.v:177551.3-177586.6" + attribute \src "libresoc.v:177550.3-177585.6" wire $1\wr_detect$4[0:0]$10759 - attribute \src "libresoc.v:177633.3-177668.6" + attribute \src "libresoc.v:177632.3-177667.6" wire $1\wr_detect$7[0:0]$10775 - attribute \src "libresoc.v:177469.3-177504.6" + attribute \src "libresoc.v:177468.3-177503.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:177669.3-177714.6" + attribute \src "libresoc.v:177668.3-177713.6" wire width 2 $2\r0__data_o$next[1:0]$10783 - attribute \src "libresoc.v:177751.3-177783.6" + attribute \src "libresoc.v:177750.3-177782.6" wire width 2 $2\reg$next[1:0]$10799 - attribute \src "libresoc.v:177423.3-177468.6" + attribute \src "libresoc.v:177422.3-177467.6" wire width 2 $2\src10__data_o$next[1:0]$10741 - attribute \src "libresoc.v:177505.3-177550.6" + attribute \src "libresoc.v:177504.3-177549.6" wire width 2 $2\src20__data_o$next[1:0]$10751 - attribute \src "libresoc.v:177587.3-177632.6" + attribute \src "libresoc.v:177586.3-177631.6" wire width 2 $2\src30__data_o$next[1:0]$10767 - attribute \src "libresoc.v:177715.3-177750.6" + attribute \src "libresoc.v:177714.3-177749.6" wire $2\wr_detect$10[0:0]$10792 - attribute \src "libresoc.v:177551.3-177586.6" + attribute \src "libresoc.v:177550.3-177585.6" wire $2\wr_detect$4[0:0]$10760 - attribute \src "libresoc.v:177633.3-177668.6" + attribute \src "libresoc.v:177632.3-177667.6" wire $2\wr_detect$7[0:0]$10776 - attribute \src "libresoc.v:177469.3-177504.6" + attribute \src "libresoc.v:177468.3-177503.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:177669.3-177714.6" + attribute \src "libresoc.v:177668.3-177713.6" wire width 2 $3\r0__data_o$next[1:0]$10784 - attribute \src "libresoc.v:177751.3-177783.6" + attribute \src "libresoc.v:177750.3-177782.6" wire width 2 $3\reg$next[1:0]$10800 - attribute \src "libresoc.v:177423.3-177468.6" + attribute \src "libresoc.v:177422.3-177467.6" wire width 2 $3\src10__data_o$next[1:0]$10742 - attribute \src "libresoc.v:177505.3-177550.6" + attribute \src "libresoc.v:177504.3-177549.6" wire width 2 $3\src20__data_o$next[1:0]$10752 - attribute \src "libresoc.v:177587.3-177632.6" + attribute \src "libresoc.v:177586.3-177631.6" wire width 2 $3\src30__data_o$next[1:0]$10768 - attribute \src "libresoc.v:177715.3-177750.6" + attribute \src "libresoc.v:177714.3-177749.6" wire $3\wr_detect$10[0:0]$10793 - attribute \src "libresoc.v:177551.3-177586.6" + attribute \src "libresoc.v:177550.3-177585.6" wire $3\wr_detect$4[0:0]$10761 - attribute \src "libresoc.v:177633.3-177668.6" + attribute \src "libresoc.v:177632.3-177667.6" wire $3\wr_detect$7[0:0]$10777 - attribute \src "libresoc.v:177469.3-177504.6" + attribute \src "libresoc.v:177468.3-177503.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:177669.3-177714.6" + attribute \src "libresoc.v:177668.3-177713.6" wire width 2 $4\r0__data_o$next[1:0]$10785 - attribute \src "libresoc.v:177751.3-177783.6" + attribute \src "libresoc.v:177750.3-177782.6" wire width 2 $4\reg$next[1:0]$10801 - attribute \src "libresoc.v:177423.3-177468.6" + attribute \src "libresoc.v:177422.3-177467.6" wire width 2 $4\src10__data_o$next[1:0]$10743 - attribute \src "libresoc.v:177505.3-177550.6" + attribute \src "libresoc.v:177504.3-177549.6" wire width 2 $4\src20__data_o$next[1:0]$10753 - attribute \src "libresoc.v:177587.3-177632.6" + attribute \src "libresoc.v:177586.3-177631.6" wire width 2 $4\src30__data_o$next[1:0]$10769 - attribute \src "libresoc.v:177715.3-177750.6" + attribute \src "libresoc.v:177714.3-177749.6" wire $4\wr_detect$10[0:0]$10794 - attribute \src "libresoc.v:177551.3-177586.6" + attribute \src "libresoc.v:177550.3-177585.6" wire $4\wr_detect$4[0:0]$10762 - attribute \src "libresoc.v:177633.3-177668.6" + attribute \src "libresoc.v:177632.3-177667.6" wire $4\wr_detect$7[0:0]$10778 - attribute \src "libresoc.v:177469.3-177504.6" + attribute \src "libresoc.v:177468.3-177503.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:177669.3-177714.6" + attribute \src "libresoc.v:177668.3-177713.6" wire width 2 $5\r0__data_o$next[1:0]$10786 - attribute \src "libresoc.v:177751.3-177783.6" + attribute \src "libresoc.v:177750.3-177782.6" wire width 2 $5\reg$next[1:0]$10802 - attribute \src "libresoc.v:177423.3-177468.6" + attribute \src "libresoc.v:177422.3-177467.6" wire width 2 $5\src10__data_o$next[1:0]$10744 - attribute \src "libresoc.v:177505.3-177550.6" + attribute \src "libresoc.v:177504.3-177549.6" wire width 2 $5\src20__data_o$next[1:0]$10754 - attribute \src "libresoc.v:177587.3-177632.6" + attribute \src "libresoc.v:177586.3-177631.6" wire width 2 $5\src30__data_o$next[1:0]$10770 - attribute \src "libresoc.v:177715.3-177750.6" + attribute \src "libresoc.v:177714.3-177749.6" wire $5\wr_detect$10[0:0]$10795 - attribute \src "libresoc.v:177551.3-177586.6" + attribute \src "libresoc.v:177550.3-177585.6" wire $5\wr_detect$4[0:0]$10763 - attribute \src "libresoc.v:177633.3-177668.6" + attribute \src "libresoc.v:177632.3-177667.6" wire $5\wr_detect$7[0:0]$10779 - attribute \src "libresoc.v:177469.3-177504.6" + attribute \src "libresoc.v:177468.3-177503.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:177669.3-177714.6" + attribute \src "libresoc.v:177668.3-177713.6" wire width 2 $6\r0__data_o$next[1:0]$10787 - attribute \src "libresoc.v:177423.3-177468.6" + attribute \src "libresoc.v:177422.3-177467.6" wire width 2 $6\src10__data_o$next[1:0]$10745 - attribute \src "libresoc.v:177505.3-177550.6" + attribute \src "libresoc.v:177504.3-177549.6" wire width 2 $6\src20__data_o$next[1:0]$10755 - attribute \src "libresoc.v:177587.3-177632.6" + attribute \src "libresoc.v:177586.3-177631.6" wire width 2 $6\src30__data_o$next[1:0]$10771 - attribute \src "libresoc.v:177669.3-177714.6" + attribute \src "libresoc.v:177668.3-177713.6" wire width 2 $7\r0__data_o$next[1:0]$10788 - attribute \src "libresoc.v:177423.3-177468.6" + attribute \src "libresoc.v:177422.3-177467.6" wire width 2 $7\src10__data_o$next[1:0]$10746 - attribute \src "libresoc.v:177505.3-177550.6" + attribute \src "libresoc.v:177504.3-177549.6" wire width 2 $7\src20__data_o$next[1:0]$10756 - attribute \src "libresoc.v:177587.3-177632.6" + attribute \src "libresoc.v:177586.3-177631.6" wire width 2 $7\src30__data_o$next[1:0]$10772 - attribute \src "libresoc.v:177409.17-177409.104" - wire $not$libresoc.v:177409$10729_Y - attribute \src "libresoc.v:177410.17-177410.100" - wire $not$libresoc.v:177410$10730_Y + attribute \src "libresoc.v:177408.17-177408.104" + wire $not$libresoc.v:177408$10729_Y + attribute \src "libresoc.v:177409.17-177409.100" + wire $not$libresoc.v:177409$10730_Y + attribute \src "libresoc.v:177410.17-177410.103" + wire $not$libresoc.v:177410$10731_Y attribute \src "libresoc.v:177411.17-177411.103" - wire $not$libresoc.v:177411$10731_Y - attribute \src "libresoc.v:177412.17-177412.103" - wire $not$libresoc.v:177412$10732_Y + wire $not$libresoc.v:177411$10732_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -364287,7 +361097,7 @@ module \reg_0$132 wire width 2 input 13 \dest30__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest30__wen - attribute \src "libresoc.v:177340.7-177340.15" + attribute \src "libresoc.v:177339.7-177339.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r0__data_o @@ -364330,129 +361140,129 @@ module \reg_0$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177409$10729 + cell $not $not$libresoc.v:177408$10729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:177409$10729_Y + connect \Y $not$libresoc.v:177408$10729_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177410$10730 + cell $not $not$libresoc.v:177409$10730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:177410$10730_Y + connect \Y $not$libresoc.v:177409$10730_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177411$10731 + cell $not $not$libresoc.v:177410$10731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:177411$10731_Y + connect \Y $not$libresoc.v:177410$10731_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177412$10732 + cell $not $not$libresoc.v:177411$10732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:177412$10732_Y + connect \Y $not$libresoc.v:177411$10732_Y end - attribute \src "libresoc.v:177340.7-177340.20" - process $proc$libresoc.v:177340$10803 + attribute \src "libresoc.v:177339.7-177339.20" + process $proc$libresoc.v:177339$10803 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177367.13-177367.30" - process $proc$libresoc.v:177367$10804 + attribute \src "libresoc.v:177366.13-177366.30" + process $proc$libresoc.v:177366$10804 assign { } { } assign $1\r0__data_o[1:0] 2'00 sync always sync init update \r0__data_o $1\r0__data_o[1:0] end - attribute \src "libresoc.v:177373.13-177373.25" - process $proc$libresoc.v:177373$10805 + attribute \src "libresoc.v:177372.13-177372.25" + process $proc$libresoc.v:177372$10805 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:177378.13-177378.33" - process $proc$libresoc.v:177378$10806 + attribute \src "libresoc.v:177377.13-177377.33" + process $proc$libresoc.v:177377$10806 assign { } { } assign $1\src10__data_o[1:0] 2'00 sync always sync init update \src10__data_o $1\src10__data_o[1:0] end - attribute \src "libresoc.v:177385.13-177385.33" - process $proc$libresoc.v:177385$10807 + attribute \src "libresoc.v:177384.13-177384.33" + process $proc$libresoc.v:177384$10807 assign { } { } assign $1\src20__data_o[1:0] 2'00 sync always sync init update \src20__data_o $1\src20__data_o[1:0] end - attribute \src "libresoc.v:177392.13-177392.33" - process $proc$libresoc.v:177392$10808 + attribute \src "libresoc.v:177391.13-177391.33" + process $proc$libresoc.v:177391$10808 assign { } { } assign $1\src30__data_o[1:0] 2'00 sync always sync init update \src30__data_o $1\src30__data_o[1:0] end - attribute \src "libresoc.v:177413.3-177414.25" - process $proc$libresoc.v:177413$10733 + attribute \src "libresoc.v:177412.3-177413.25" + process $proc$libresoc.v:177412$10733 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:177415.3-177416.37" - process $proc$libresoc.v:177415$10734 + attribute \src "libresoc.v:177414.3-177415.37" + process $proc$libresoc.v:177414$10734 assign { } { } assign $0\r0__data_o[1:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[1:0] end - attribute \src "libresoc.v:177417.3-177418.43" - process $proc$libresoc.v:177417$10735 + attribute \src "libresoc.v:177416.3-177417.43" + process $proc$libresoc.v:177416$10735 assign { } { } assign $0\src30__data_o[1:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[1:0] end - attribute \src "libresoc.v:177419.3-177420.43" - process $proc$libresoc.v:177419$10736 + attribute \src "libresoc.v:177418.3-177419.43" + process $proc$libresoc.v:177418$10736 assign { } { } assign $0\src20__data_o[1:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[1:0] end - attribute \src "libresoc.v:177421.3-177422.43" - process $proc$libresoc.v:177421$10737 + attribute \src "libresoc.v:177420.3-177421.43" + process $proc$libresoc.v:177420$10737 assign { } { } assign $0\src10__data_o[1:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[1:0] end - attribute \src "libresoc.v:177423.3-177468.6" - process $proc$libresoc.v:177423$10738 + attribute \src "libresoc.v:177422.3-177467.6" + process $proc$libresoc.v:177422$10738 assign { } { } assign { } { } assign { } { } assign $0\src10__data_o$next[1:0]$10739 $7\src10__data_o$next[1:0]$10746 - attribute \src "libresoc.v:177424.5-177424.29" + attribute \src "libresoc.v:177423.5-177423.29" switch \initial - attribute \src "libresoc.v:177424.9-177424.17" + attribute \src "libresoc.v:177423.9-177423.17" case 1'1 case end @@ -364526,14 +361336,14 @@ module \reg_0$132 sync always update \src10__data_o$next $0\src10__data_o$next[1:0]$10739 end - attribute \src "libresoc.v:177469.3-177504.6" - process $proc$libresoc.v:177469$10747 + attribute \src "libresoc.v:177468.3-177503.6" + process $proc$libresoc.v:177468$10747 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:177470.5-177470.29" + attribute \src "libresoc.v:177469.5-177469.29" switch \initial - attribute \src "libresoc.v:177470.9-177470.17" + attribute \src "libresoc.v:177469.9-177469.17" case 1'1 case end @@ -364589,15 +361399,15 @@ module \reg_0$132 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:177505.3-177550.6" - process $proc$libresoc.v:177505$10748 + attribute \src "libresoc.v:177504.3-177549.6" + process $proc$libresoc.v:177504$10748 assign { } { } assign { } { } assign { } { } assign $0\src20__data_o$next[1:0]$10749 $7\src20__data_o$next[1:0]$10756 - attribute \src "libresoc.v:177506.5-177506.29" + attribute \src "libresoc.v:177505.5-177505.29" switch \initial - attribute \src "libresoc.v:177506.9-177506.17" + attribute \src "libresoc.v:177505.9-177505.17" case 1'1 case end @@ -364671,14 +361481,14 @@ module \reg_0$132 sync always update \src20__data_o$next $0\src20__data_o$next[1:0]$10749 end - attribute \src "libresoc.v:177551.3-177586.6" - process $proc$libresoc.v:177551$10757 + attribute \src "libresoc.v:177550.3-177585.6" + process $proc$libresoc.v:177550$10757 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$10758 $1\wr_detect$4[0:0]$10759 - attribute \src "libresoc.v:177552.5-177552.29" + attribute \src "libresoc.v:177551.5-177551.29" switch \initial - attribute \src "libresoc.v:177552.9-177552.17" + attribute \src "libresoc.v:177551.9-177551.17" case 1'1 case end @@ -364734,15 +361544,15 @@ module \reg_0$132 sync always update \wr_detect$4 $0\wr_detect$4[0:0]$10758 end - attribute \src "libresoc.v:177587.3-177632.6" - process $proc$libresoc.v:177587$10764 + attribute \src "libresoc.v:177586.3-177631.6" + process $proc$libresoc.v:177586$10764 assign { } { } assign { } { } assign { } { } assign $0\src30__data_o$next[1:0]$10765 $7\src30__data_o$next[1:0]$10772 - attribute \src "libresoc.v:177588.5-177588.29" + attribute \src "libresoc.v:177587.5-177587.29" switch \initial - attribute \src "libresoc.v:177588.9-177588.17" + attribute \src "libresoc.v:177587.9-177587.17" case 1'1 case end @@ -364816,14 +361626,14 @@ module \reg_0$132 sync always update \src30__data_o$next $0\src30__data_o$next[1:0]$10765 end - attribute \src "libresoc.v:177633.3-177668.6" - process $proc$libresoc.v:177633$10773 + attribute \src "libresoc.v:177632.3-177667.6" + process $proc$libresoc.v:177632$10773 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$10774 $1\wr_detect$7[0:0]$10775 - attribute \src "libresoc.v:177634.5-177634.29" + attribute \src "libresoc.v:177633.5-177633.29" switch \initial - attribute \src "libresoc.v:177634.9-177634.17" + attribute \src "libresoc.v:177633.9-177633.17" case 1'1 case end @@ -364879,15 +361689,15 @@ module \reg_0$132 sync always update \wr_detect$7 $0\wr_detect$7[0:0]$10774 end - attribute \src "libresoc.v:177669.3-177714.6" - process $proc$libresoc.v:177669$10780 + attribute \src "libresoc.v:177668.3-177713.6" + process $proc$libresoc.v:177668$10780 assign { } { } assign { } { } assign { } { } assign $0\r0__data_o$next[1:0]$10781 $7\r0__data_o$next[1:0]$10788 - attribute \src "libresoc.v:177670.5-177670.29" + attribute \src "libresoc.v:177669.5-177669.29" switch \initial - attribute \src "libresoc.v:177670.9-177670.17" + attribute \src "libresoc.v:177669.9-177669.17" case 1'1 case end @@ -364961,14 +361771,14 @@ module \reg_0$132 sync always update \r0__data_o$next $0\r0__data_o$next[1:0]$10781 end - attribute \src "libresoc.v:177715.3-177750.6" - process $proc$libresoc.v:177715$10789 + attribute \src "libresoc.v:177714.3-177749.6" + process $proc$libresoc.v:177714$10789 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$10790 $1\wr_detect$10[0:0]$10791 - attribute \src "libresoc.v:177716.5-177716.29" + attribute \src "libresoc.v:177715.5-177715.29" switch \initial - attribute \src "libresoc.v:177716.9-177716.17" + attribute \src "libresoc.v:177715.9-177715.17" case 1'1 case end @@ -365024,8 +361834,8 @@ module \reg_0$132 sync always update \wr_detect$10 $0\wr_detect$10[0:0]$10790 end - attribute \src "libresoc.v:177751.3-177783.6" - process $proc$libresoc.v:177751$10796 + attribute \src "libresoc.v:177750.3-177782.6" + process $proc$libresoc.v:177750$10796 assign { } { } assign { } { } assign { } { } @@ -365033,9 +361843,9 @@ module \reg_0$132 assign { } { } assign { } { } assign $0\reg$next[1:0]$10797 $5\reg$next[1:0]$10802 - attribute \src "libresoc.v:177752.5-177752.29" + attribute \src "libresoc.v:177751.5-177751.29" switch \initial - attribute \src "libresoc.v:177752.9-177752.17" + attribute \src "libresoc.v:177751.9-177751.17" case 1'1 case end @@ -365087,136 +361897,136 @@ module \reg_0$132 sync always update \reg$next $0\reg$next[1:0]$10797 end - connect \$9 $not$libresoc.v:177409$10729_Y - connect \$1 $not$libresoc.v:177410$10730_Y - connect \$3 $not$libresoc.v:177411$10731_Y - connect \$6 $not$libresoc.v:177412$10732_Y + connect \$9 $not$libresoc.v:177408$10729_Y + connect \$1 $not$libresoc.v:177409$10730_Y + connect \$3 $not$libresoc.v:177410$10731_Y + connect \$6 $not$libresoc.v:177411$10732_Y end -attribute \src "libresoc.v:177788.1-178137.10" +attribute \src "libresoc.v:177787.1-178136.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_0" attribute \generator "nMigen" module \reg_0$135 - attribute \src "libresoc.v:177858.3-177903.6" + attribute \src "libresoc.v:177857.3-177902.6" wire width 64 $0\cia0__data_o$next[63:0]$10817 - attribute \src "libresoc.v:177856.3-177857.41" + attribute \src "libresoc.v:177855.3-177856.41" wire width 64 $0\cia0__data_o[63:0] - attribute \src "libresoc.v:177789.7-177789.20" + attribute \src "libresoc.v:177788.7-177788.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177940.3-177985.6" + attribute \src "libresoc.v:177939.3-177984.6" wire width 64 $0\msr0__data_o$next[63:0]$10827 - attribute \src "libresoc.v:177854.3-177855.41" + attribute \src "libresoc.v:177853.3-177854.41" wire width 64 $0\msr0__data_o[63:0] - attribute \src "libresoc.v:178104.3-178136.6" + attribute \src "libresoc.v:178103.3-178135.6" wire width 64 $0\reg$next[63:0]$10859 - attribute \src "libresoc.v:177850.3-177851.25" + attribute \src "libresoc.v:177849.3-177850.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:178022.3-178067.6" + attribute \src "libresoc.v:178021.3-178066.6" wire width 64 $0\sv0__data_o$next[63:0]$10843 - attribute \src "libresoc.v:177852.3-177853.39" + attribute \src "libresoc.v:177851.3-177852.39" wire width 64 $0\sv0__data_o[63:0] - attribute \src "libresoc.v:177986.3-178021.6" + attribute \src "libresoc.v:177985.3-178020.6" wire $0\wr_detect$4[0:0]$10836 - attribute \src "libresoc.v:178068.3-178103.6" + attribute \src "libresoc.v:178067.3-178102.6" wire $0\wr_detect$7[0:0]$10852 - attribute \src "libresoc.v:177904.3-177939.6" + attribute \src "libresoc.v:177903.3-177938.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:177858.3-177903.6" + attribute \src "libresoc.v:177857.3-177902.6" wire width 64 $1\cia0__data_o$next[63:0]$10818 - attribute \src "libresoc.v:177798.14-177798.49" + attribute \src "libresoc.v:177797.14-177797.49" wire width 64 $1\cia0__data_o[63:0] - attribute \src "libresoc.v:177940.3-177985.6" + attribute \src "libresoc.v:177939.3-177984.6" wire width 64 $1\msr0__data_o$next[63:0]$10828 - attribute \src "libresoc.v:177815.14-177815.49" + attribute \src "libresoc.v:177814.14-177814.49" wire width 64 $1\msr0__data_o[63:0] - attribute \src "libresoc.v:178104.3-178136.6" + attribute \src "libresoc.v:178103.3-178135.6" wire width 64 $1\reg$next[63:0]$10860 - attribute \src "libresoc.v:177827.14-177827.42" + attribute \src "libresoc.v:177826.14-177826.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:178022.3-178067.6" + attribute \src "libresoc.v:178021.3-178066.6" wire width 64 $1\sv0__data_o$next[63:0]$10844 - attribute \src "libresoc.v:177834.14-177834.48" + attribute \src "libresoc.v:177833.14-177833.48" wire width 64 $1\sv0__data_o[63:0] - attribute \src "libresoc.v:177986.3-178021.6" + attribute \src "libresoc.v:177985.3-178020.6" wire $1\wr_detect$4[0:0]$10837 - attribute \src "libresoc.v:178068.3-178103.6" + attribute \src "libresoc.v:178067.3-178102.6" wire $1\wr_detect$7[0:0]$10853 - attribute \src "libresoc.v:177904.3-177939.6" + attribute \src "libresoc.v:177903.3-177938.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:177858.3-177903.6" + attribute \src "libresoc.v:177857.3-177902.6" wire width 64 $2\cia0__data_o$next[63:0]$10819 - attribute \src "libresoc.v:177940.3-177985.6" + attribute \src "libresoc.v:177939.3-177984.6" wire width 64 $2\msr0__data_o$next[63:0]$10829 - attribute \src "libresoc.v:178104.3-178136.6" + attribute \src "libresoc.v:178103.3-178135.6" wire width 64 $2\reg$next[63:0]$10861 - attribute \src "libresoc.v:178022.3-178067.6" + attribute \src "libresoc.v:178021.3-178066.6" wire width 64 $2\sv0__data_o$next[63:0]$10845 - attribute \src "libresoc.v:177986.3-178021.6" + attribute \src "libresoc.v:177985.3-178020.6" wire $2\wr_detect$4[0:0]$10838 - attribute \src "libresoc.v:178068.3-178103.6" + attribute \src "libresoc.v:178067.3-178102.6" wire $2\wr_detect$7[0:0]$10854 - attribute \src "libresoc.v:177904.3-177939.6" + attribute \src "libresoc.v:177903.3-177938.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:177858.3-177903.6" + attribute \src "libresoc.v:177857.3-177902.6" wire width 64 $3\cia0__data_o$next[63:0]$10820 - attribute \src "libresoc.v:177940.3-177985.6" + attribute \src "libresoc.v:177939.3-177984.6" wire width 64 $3\msr0__data_o$next[63:0]$10830 - attribute \src "libresoc.v:178104.3-178136.6" + attribute \src "libresoc.v:178103.3-178135.6" wire width 64 $3\reg$next[63:0]$10862 - attribute \src "libresoc.v:178022.3-178067.6" + attribute \src "libresoc.v:178021.3-178066.6" wire width 64 $3\sv0__data_o$next[63:0]$10846 - attribute \src "libresoc.v:177986.3-178021.6" + attribute \src "libresoc.v:177985.3-178020.6" wire $3\wr_detect$4[0:0]$10839 - attribute \src "libresoc.v:178068.3-178103.6" + attribute \src "libresoc.v:178067.3-178102.6" wire $3\wr_detect$7[0:0]$10855 - attribute \src "libresoc.v:177904.3-177939.6" + attribute \src "libresoc.v:177903.3-177938.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:177858.3-177903.6" + attribute \src "libresoc.v:177857.3-177902.6" wire width 64 $4\cia0__data_o$next[63:0]$10821 - attribute \src "libresoc.v:177940.3-177985.6" + attribute \src "libresoc.v:177939.3-177984.6" wire width 64 $4\msr0__data_o$next[63:0]$10831 - attribute \src "libresoc.v:178104.3-178136.6" + attribute \src "libresoc.v:178103.3-178135.6" wire width 64 $4\reg$next[63:0]$10863 - attribute \src "libresoc.v:178022.3-178067.6" + attribute \src "libresoc.v:178021.3-178066.6" wire width 64 $4\sv0__data_o$next[63:0]$10847 - attribute \src "libresoc.v:177986.3-178021.6" + attribute \src "libresoc.v:177985.3-178020.6" wire $4\wr_detect$4[0:0]$10840 - attribute \src "libresoc.v:178068.3-178103.6" + attribute \src "libresoc.v:178067.3-178102.6" wire $4\wr_detect$7[0:0]$10856 - attribute \src "libresoc.v:177904.3-177939.6" + attribute \src "libresoc.v:177903.3-177938.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:177858.3-177903.6" + attribute \src "libresoc.v:177857.3-177902.6" wire width 64 $5\cia0__data_o$next[63:0]$10822 - attribute \src "libresoc.v:177940.3-177985.6" + attribute \src "libresoc.v:177939.3-177984.6" wire width 64 $5\msr0__data_o$next[63:0]$10832 - attribute \src "libresoc.v:178104.3-178136.6" + attribute \src "libresoc.v:178103.3-178135.6" wire width 64 $5\reg$next[63:0]$10864 - attribute \src "libresoc.v:178022.3-178067.6" + attribute \src "libresoc.v:178021.3-178066.6" wire width 64 $5\sv0__data_o$next[63:0]$10848 - attribute \src "libresoc.v:177986.3-178021.6" + attribute \src "libresoc.v:177985.3-178020.6" wire $5\wr_detect$4[0:0]$10841 - attribute \src "libresoc.v:178068.3-178103.6" + attribute \src "libresoc.v:178067.3-178102.6" wire $5\wr_detect$7[0:0]$10857 - attribute \src "libresoc.v:177904.3-177939.6" + attribute \src "libresoc.v:177903.3-177938.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:177858.3-177903.6" + attribute \src "libresoc.v:177857.3-177902.6" wire width 64 $6\cia0__data_o$next[63:0]$10823 - attribute \src "libresoc.v:177940.3-177985.6" + attribute \src "libresoc.v:177939.3-177984.6" wire width 64 $6\msr0__data_o$next[63:0]$10833 - attribute \src "libresoc.v:178022.3-178067.6" + attribute \src "libresoc.v:178021.3-178066.6" wire width 64 $6\sv0__data_o$next[63:0]$10849 - attribute \src "libresoc.v:177858.3-177903.6" + attribute \src "libresoc.v:177857.3-177902.6" wire width 64 $7\cia0__data_o$next[63:0]$10824 - attribute \src "libresoc.v:177940.3-177985.6" + attribute \src "libresoc.v:177939.3-177984.6" wire width 64 $7\msr0__data_o$next[63:0]$10834 - attribute \src "libresoc.v:178022.3-178067.6" + attribute \src "libresoc.v:178021.3-178066.6" wire width 64 $7\sv0__data_o$next[63:0]$10850 - attribute \src "libresoc.v:177847.17-177847.100" - wire $not$libresoc.v:177847$10809_Y + attribute \src "libresoc.v:177846.17-177846.100" + wire $not$libresoc.v:177846$10809_Y + attribute \src "libresoc.v:177847.17-177847.103" + wire $not$libresoc.v:177847$10810_Y attribute \src "libresoc.v:177848.17-177848.103" - wire $not$libresoc.v:177848$10810_Y - attribute \src "libresoc.v:177849.17-177849.103" - wire $not$libresoc.v:177849$10811_Y + wire $not$libresoc.v:177848$10811_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -365237,7 +362047,7 @@ module \reg_0$135 wire width 64 input 15 \d_wr10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr10__wen - attribute \src "libresoc.v:177789.7-177789.15" + attribute \src "libresoc.v:177788.7-177788.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr0__data_i @@ -365274,106 +362084,106 @@ module \reg_0$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177847$10809 + cell $not $not$libresoc.v:177846$10809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:177847$10809_Y + connect \Y $not$libresoc.v:177846$10809_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177848$10810 + cell $not $not$libresoc.v:177847$10810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:177848$10810_Y + connect \Y $not$libresoc.v:177847$10810_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177849$10811 + cell $not $not$libresoc.v:177848$10811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:177849$10811_Y + connect \Y $not$libresoc.v:177848$10811_Y end - attribute \src "libresoc.v:177789.7-177789.20" - process $proc$libresoc.v:177789$10865 + attribute \src "libresoc.v:177788.7-177788.20" + process $proc$libresoc.v:177788$10865 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177798.14-177798.49" - process $proc$libresoc.v:177798$10866 + attribute \src "libresoc.v:177797.14-177797.49" + process $proc$libresoc.v:177797$10866 assign { } { } assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia0__data_o $1\cia0__data_o[63:0] end - attribute \src "libresoc.v:177815.14-177815.49" - process $proc$libresoc.v:177815$10867 + attribute \src "libresoc.v:177814.14-177814.49" + process $proc$libresoc.v:177814$10867 assign { } { } assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr0__data_o $1\msr0__data_o[63:0] end - attribute \src "libresoc.v:177827.14-177827.42" - process $proc$libresoc.v:177827$10868 + attribute \src "libresoc.v:177826.14-177826.42" + process $proc$libresoc.v:177826$10868 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:177834.14-177834.48" - process $proc$libresoc.v:177834$10869 + attribute \src "libresoc.v:177833.14-177833.48" + process $proc$libresoc.v:177833$10869 assign { } { } assign $1\sv0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv0__data_o $1\sv0__data_o[63:0] end - attribute \src "libresoc.v:177850.3-177851.25" - process $proc$libresoc.v:177850$10812 + attribute \src "libresoc.v:177849.3-177850.25" + process $proc$libresoc.v:177849$10812 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:177852.3-177853.39" - process $proc$libresoc.v:177852$10813 + attribute \src "libresoc.v:177851.3-177852.39" + process $proc$libresoc.v:177851$10813 assign { } { } assign $0\sv0__data_o[63:0] \sv0__data_o$next sync posedge \coresync_clk update \sv0__data_o $0\sv0__data_o[63:0] end - attribute \src "libresoc.v:177854.3-177855.41" - process $proc$libresoc.v:177854$10814 + attribute \src "libresoc.v:177853.3-177854.41" + process $proc$libresoc.v:177853$10814 assign { } { } assign $0\msr0__data_o[63:0] \msr0__data_o$next sync posedge \coresync_clk update \msr0__data_o $0\msr0__data_o[63:0] end - attribute \src "libresoc.v:177856.3-177857.41" - process $proc$libresoc.v:177856$10815 + attribute \src "libresoc.v:177855.3-177856.41" + process $proc$libresoc.v:177855$10815 assign { } { } assign $0\cia0__data_o[63:0] \cia0__data_o$next sync posedge \coresync_clk update \cia0__data_o $0\cia0__data_o[63:0] end - attribute \src "libresoc.v:177858.3-177903.6" - process $proc$libresoc.v:177858$10816 + attribute \src "libresoc.v:177857.3-177902.6" + process $proc$libresoc.v:177857$10816 assign { } { } assign { } { } assign { } { } assign $0\cia0__data_o$next[63:0]$10817 $7\cia0__data_o$next[63:0]$10824 - attribute \src "libresoc.v:177859.5-177859.29" + attribute \src "libresoc.v:177858.5-177858.29" switch \initial - attribute \src "libresoc.v:177859.9-177859.17" + attribute \src "libresoc.v:177858.9-177858.17" case 1'1 case end @@ -365447,14 +362257,14 @@ module \reg_0$135 sync always update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10817 end - attribute \src "libresoc.v:177904.3-177939.6" - process $proc$libresoc.v:177904$10825 + attribute \src "libresoc.v:177903.3-177938.6" + process $proc$libresoc.v:177903$10825 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:177905.5-177905.29" + attribute \src "libresoc.v:177904.5-177904.29" switch \initial - attribute \src "libresoc.v:177905.9-177905.17" + attribute \src "libresoc.v:177904.9-177904.17" case 1'1 case end @@ -365510,15 +362320,15 @@ module \reg_0$135 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:177940.3-177985.6" - process $proc$libresoc.v:177940$10826 + attribute \src "libresoc.v:177939.3-177984.6" + process $proc$libresoc.v:177939$10826 assign { } { } assign { } { } assign { } { } assign $0\msr0__data_o$next[63:0]$10827 $7\msr0__data_o$next[63:0]$10834 - attribute \src "libresoc.v:177941.5-177941.29" + attribute \src "libresoc.v:177940.5-177940.29" switch \initial - attribute \src "libresoc.v:177941.9-177941.17" + attribute \src "libresoc.v:177940.9-177940.17" case 1'1 case end @@ -365592,14 +362402,14 @@ module \reg_0$135 sync always update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10827 end - attribute \src "libresoc.v:177986.3-178021.6" - process $proc$libresoc.v:177986$10835 + attribute \src "libresoc.v:177985.3-178020.6" + process $proc$libresoc.v:177985$10835 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$10836 $1\wr_detect$4[0:0]$10837 - attribute \src "libresoc.v:177987.5-177987.29" + attribute \src "libresoc.v:177986.5-177986.29" switch \initial - attribute \src "libresoc.v:177987.9-177987.17" + attribute \src "libresoc.v:177986.9-177986.17" case 1'1 case end @@ -365655,15 +362465,15 @@ module \reg_0$135 sync always update \wr_detect$4 $0\wr_detect$4[0:0]$10836 end - attribute \src "libresoc.v:178022.3-178067.6" - process $proc$libresoc.v:178022$10842 + attribute \src "libresoc.v:178021.3-178066.6" + process $proc$libresoc.v:178021$10842 assign { } { } assign { } { } assign { } { } assign $0\sv0__data_o$next[63:0]$10843 $7\sv0__data_o$next[63:0]$10850 - attribute \src "libresoc.v:178023.5-178023.29" + attribute \src "libresoc.v:178022.5-178022.29" switch \initial - attribute \src "libresoc.v:178023.9-178023.17" + attribute \src "libresoc.v:178022.9-178022.17" case 1'1 case end @@ -365737,14 +362547,14 @@ module \reg_0$135 sync always update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10843 end - attribute \src "libresoc.v:178068.3-178103.6" - process $proc$libresoc.v:178068$10851 + attribute \src "libresoc.v:178067.3-178102.6" + process $proc$libresoc.v:178067$10851 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$10852 $1\wr_detect$7[0:0]$10853 - attribute \src "libresoc.v:178069.5-178069.29" + attribute \src "libresoc.v:178068.5-178068.29" switch \initial - attribute \src "libresoc.v:178069.9-178069.17" + attribute \src "libresoc.v:178068.9-178068.17" case 1'1 case end @@ -365800,8 +362610,8 @@ module \reg_0$135 sync always update \wr_detect$7 $0\wr_detect$7[0:0]$10852 end - attribute \src "libresoc.v:178104.3-178136.6" - process $proc$libresoc.v:178104$10858 + attribute \src "libresoc.v:178103.3-178135.6" + process $proc$libresoc.v:178103$10858 assign { } { } assign { } { } assign { } { } @@ -365809,9 +362619,9 @@ module \reg_0$135 assign { } { } assign { } { } assign $0\reg$next[63:0]$10859 $5\reg$next[63:0]$10864 - attribute \src "libresoc.v:178105.5-178105.29" + attribute \src "libresoc.v:178104.5-178104.29" switch \initial - attribute \src "libresoc.v:178105.9-178105.17" + attribute \src "libresoc.v:178104.9-178104.17" case 1'1 case end @@ -365863,211 +362673,211 @@ module \reg_0$135 sync always update \reg$next $0\reg$next[63:0]$10859 end - connect \$1 $not$libresoc.v:177847$10809_Y - connect \$3 $not$libresoc.v:177848$10810_Y - connect \$6 $not$libresoc.v:177849$10811_Y + connect \$1 $not$libresoc.v:177846$10809_Y + connect \$3 $not$libresoc.v:177847$10810_Y + connect \$6 $not$libresoc.v:177848$10811_Y end -attribute \src "libresoc.v:178141.1-178696.10" +attribute \src "libresoc.v:178140.1-178695.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_1" attribute \generator "nMigen" module \reg_1 - attribute \src "libresoc.v:178249.3-178288.6" + attribute \src "libresoc.v:178248.3-178287.6" wire width 4 $0\cr_pred1__data_o$next[3:0]$10884 - attribute \src "libresoc.v:178247.3-178248.49" + attribute \src "libresoc.v:178246.3-178247.49" wire width 4 $0\cr_pred1__data_o[3:0] - attribute \src "libresoc.v:178142.7-178142.20" + attribute \src "libresoc.v:178141.7-178141.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178626.3-178665.6" + attribute \src "libresoc.v:178625.3-178664.6" wire width 4 $0\r1__data_o$next[3:0]$10955 - attribute \src "libresoc.v:178239.3-178240.37" + attribute \src "libresoc.v:178238.3-178239.37" wire width 4 $0\r1__data_o[3:0] - attribute \src "libresoc.v:178319.3-178358.6" + attribute \src "libresoc.v:178318.3-178357.6" wire width 4 $0\r21__data_o$next[3:0]$10893 - attribute \src "libresoc.v:178237.3-178238.39" + attribute \src "libresoc.v:178236.3-178237.39" wire width 4 $0\r21__data_o[3:0] - attribute \src "libresoc.v:178389.3-178415.6" + attribute \src "libresoc.v:178388.3-178414.6" wire width 4 $0\reg$next[3:0]$10907 - attribute \src "libresoc.v:178235.3-178236.25" + attribute \src "libresoc.v:178234.3-178235.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:178416.3-178455.6" + attribute \src "libresoc.v:178415.3-178454.6" wire width 4 $0\src11__data_o$next[3:0]$10913 - attribute \src "libresoc.v:178245.3-178246.43" + attribute \src "libresoc.v:178244.3-178245.43" wire width 4 $0\src11__data_o[3:0] - attribute \src "libresoc.v:178486.3-178525.6" + attribute \src "libresoc.v:178485.3-178524.6" wire width 4 $0\src21__data_o$next[3:0]$10927 - attribute \src "libresoc.v:178243.3-178244.43" + attribute \src "libresoc.v:178242.3-178243.43" wire width 4 $0\src21__data_o[3:0] - attribute \src "libresoc.v:178556.3-178595.6" + attribute \src "libresoc.v:178555.3-178594.6" wire width 4 $0\src31__data_o$next[3:0]$10941 - attribute \src "libresoc.v:178241.3-178242.43" + attribute \src "libresoc.v:178240.3-178241.43" wire width 4 $0\src31__data_o[3:0] - attribute \src "libresoc.v:178596.3-178625.6" + attribute \src "libresoc.v:178595.3-178624.6" wire $0\wr_detect$10[0:0]$10949 - attribute \src "libresoc.v:178666.3-178695.6" + attribute \src "libresoc.v:178665.3-178694.6" wire $0\wr_detect$13[0:0]$10963 - attribute \src "libresoc.v:178359.3-178388.6" + attribute \src "libresoc.v:178358.3-178387.6" wire $0\wr_detect$16[0:0]$10901 - attribute \src "libresoc.v:178456.3-178485.6" + attribute \src "libresoc.v:178455.3-178484.6" wire $0\wr_detect$4[0:0]$10921 - attribute \src "libresoc.v:178526.3-178555.6" + attribute \src "libresoc.v:178525.3-178554.6" wire $0\wr_detect$7[0:0]$10935 - attribute \src "libresoc.v:178289.3-178318.6" + attribute \src "libresoc.v:178288.3-178317.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:178249.3-178288.6" + attribute \src "libresoc.v:178248.3-178287.6" wire width 4 $1\cr_pred1__data_o$next[3:0]$10885 - attribute \src "libresoc.v:178161.13-178161.36" + attribute \src "libresoc.v:178160.13-178160.36" wire width 4 $1\cr_pred1__data_o[3:0] - attribute \src "libresoc.v:178626.3-178665.6" + attribute \src "libresoc.v:178625.3-178664.6" wire width 4 $1\r1__data_o$next[3:0]$10956 - attribute \src "libresoc.v:178176.13-178176.30" + attribute \src "libresoc.v:178175.13-178175.30" wire width 4 $1\r1__data_o[3:0] - attribute \src "libresoc.v:178319.3-178358.6" + attribute \src "libresoc.v:178318.3-178357.6" wire width 4 $1\r21__data_o$next[3:0]$10894 - attribute \src "libresoc.v:178183.13-178183.31" + attribute \src "libresoc.v:178182.13-178182.31" wire width 4 $1\r21__data_o[3:0] - attribute \src "libresoc.v:178389.3-178415.6" + attribute \src "libresoc.v:178388.3-178414.6" wire width 4 $1\reg$next[3:0]$10908 - attribute \src "libresoc.v:178189.13-178189.25" + attribute \src "libresoc.v:178188.13-178188.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:178416.3-178455.6" + attribute \src "libresoc.v:178415.3-178454.6" wire width 4 $1\src11__data_o$next[3:0]$10914 - attribute \src "libresoc.v:178194.13-178194.33" + attribute \src "libresoc.v:178193.13-178193.33" wire width 4 $1\src11__data_o[3:0] - attribute \src "libresoc.v:178486.3-178525.6" + attribute \src "libresoc.v:178485.3-178524.6" wire width 4 $1\src21__data_o$next[3:0]$10928 - attribute \src "libresoc.v:178201.13-178201.33" + attribute \src "libresoc.v:178200.13-178200.33" wire width 4 $1\src21__data_o[3:0] - attribute \src "libresoc.v:178556.3-178595.6" + attribute \src "libresoc.v:178555.3-178594.6" wire width 4 $1\src31__data_o$next[3:0]$10942 - attribute \src "libresoc.v:178208.13-178208.33" + attribute \src "libresoc.v:178207.13-178207.33" wire width 4 $1\src31__data_o[3:0] - attribute \src "libresoc.v:178596.3-178625.6" + attribute \src "libresoc.v:178595.3-178624.6" wire $1\wr_detect$10[0:0]$10950 - attribute \src "libresoc.v:178666.3-178695.6" + attribute \src "libresoc.v:178665.3-178694.6" wire $1\wr_detect$13[0:0]$10964 - attribute \src "libresoc.v:178359.3-178388.6" + attribute \src "libresoc.v:178358.3-178387.6" wire $1\wr_detect$16[0:0]$10902 - attribute \src "libresoc.v:178456.3-178485.6" + attribute \src "libresoc.v:178455.3-178484.6" wire $1\wr_detect$4[0:0]$10922 - attribute \src "libresoc.v:178526.3-178555.6" + attribute \src "libresoc.v:178525.3-178554.6" wire $1\wr_detect$7[0:0]$10936 - attribute \src "libresoc.v:178289.3-178318.6" + attribute \src "libresoc.v:178288.3-178317.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:178249.3-178288.6" + attribute \src "libresoc.v:178248.3-178287.6" wire width 4 $2\cr_pred1__data_o$next[3:0]$10886 - attribute \src "libresoc.v:178626.3-178665.6" + attribute \src "libresoc.v:178625.3-178664.6" wire width 4 $2\r1__data_o$next[3:0]$10957 - attribute \src "libresoc.v:178319.3-178358.6" + attribute \src "libresoc.v:178318.3-178357.6" wire width 4 $2\r21__data_o$next[3:0]$10895 - attribute \src "libresoc.v:178389.3-178415.6" + attribute \src "libresoc.v:178388.3-178414.6" wire width 4 $2\reg$next[3:0]$10909 - attribute \src "libresoc.v:178416.3-178455.6" + attribute \src "libresoc.v:178415.3-178454.6" wire width 4 $2\src11__data_o$next[3:0]$10915 - attribute \src "libresoc.v:178486.3-178525.6" + attribute \src "libresoc.v:178485.3-178524.6" wire width 4 $2\src21__data_o$next[3:0]$10929 - attribute \src "libresoc.v:178556.3-178595.6" + attribute \src "libresoc.v:178555.3-178594.6" wire width 4 $2\src31__data_o$next[3:0]$10943 - attribute \src "libresoc.v:178596.3-178625.6" + attribute \src "libresoc.v:178595.3-178624.6" wire $2\wr_detect$10[0:0]$10951 - attribute \src "libresoc.v:178666.3-178695.6" + attribute \src "libresoc.v:178665.3-178694.6" wire $2\wr_detect$13[0:0]$10965 - attribute \src "libresoc.v:178359.3-178388.6" + attribute \src "libresoc.v:178358.3-178387.6" wire $2\wr_detect$16[0:0]$10903 - attribute \src "libresoc.v:178456.3-178485.6" + attribute \src "libresoc.v:178455.3-178484.6" wire $2\wr_detect$4[0:0]$10923 - attribute \src "libresoc.v:178526.3-178555.6" + attribute \src "libresoc.v:178525.3-178554.6" wire $2\wr_detect$7[0:0]$10937 - attribute \src "libresoc.v:178289.3-178318.6" + attribute \src "libresoc.v:178288.3-178317.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:178249.3-178288.6" + attribute \src "libresoc.v:178248.3-178287.6" wire width 4 $3\cr_pred1__data_o$next[3:0]$10887 - attribute \src "libresoc.v:178626.3-178665.6" + attribute \src "libresoc.v:178625.3-178664.6" wire width 4 $3\r1__data_o$next[3:0]$10958 - attribute \src "libresoc.v:178319.3-178358.6" + attribute \src "libresoc.v:178318.3-178357.6" wire width 4 $3\r21__data_o$next[3:0]$10896 - attribute \src "libresoc.v:178389.3-178415.6" + attribute \src "libresoc.v:178388.3-178414.6" wire width 4 $3\reg$next[3:0]$10910 - attribute \src "libresoc.v:178416.3-178455.6" + attribute \src "libresoc.v:178415.3-178454.6" wire width 4 $3\src11__data_o$next[3:0]$10916 - attribute \src "libresoc.v:178486.3-178525.6" + attribute \src "libresoc.v:178485.3-178524.6" wire width 4 $3\src21__data_o$next[3:0]$10930 - attribute \src "libresoc.v:178556.3-178595.6" + attribute \src "libresoc.v:178555.3-178594.6" wire width 4 $3\src31__data_o$next[3:0]$10944 - attribute \src "libresoc.v:178596.3-178625.6" + attribute \src "libresoc.v:178595.3-178624.6" wire $3\wr_detect$10[0:0]$10952 - attribute \src "libresoc.v:178666.3-178695.6" + attribute \src "libresoc.v:178665.3-178694.6" wire $3\wr_detect$13[0:0]$10966 - attribute \src "libresoc.v:178359.3-178388.6" + attribute \src "libresoc.v:178358.3-178387.6" wire $3\wr_detect$16[0:0]$10904 - attribute \src "libresoc.v:178456.3-178485.6" + attribute \src "libresoc.v:178455.3-178484.6" wire $3\wr_detect$4[0:0]$10924 - attribute \src "libresoc.v:178526.3-178555.6" + attribute \src "libresoc.v:178525.3-178554.6" wire $3\wr_detect$7[0:0]$10938 - attribute \src "libresoc.v:178289.3-178318.6" + attribute \src "libresoc.v:178288.3-178317.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:178249.3-178288.6" + attribute \src "libresoc.v:178248.3-178287.6" wire width 4 $4\cr_pred1__data_o$next[3:0]$10888 - attribute \src "libresoc.v:178626.3-178665.6" + attribute \src "libresoc.v:178625.3-178664.6" wire width 4 $4\r1__data_o$next[3:0]$10959 - attribute \src "libresoc.v:178319.3-178358.6" + attribute \src "libresoc.v:178318.3-178357.6" wire width 4 $4\r21__data_o$next[3:0]$10897 - attribute \src "libresoc.v:178389.3-178415.6" + attribute \src "libresoc.v:178388.3-178414.6" wire width 4 $4\reg$next[3:0]$10911 - attribute \src "libresoc.v:178416.3-178455.6" + attribute \src "libresoc.v:178415.3-178454.6" wire width 4 $4\src11__data_o$next[3:0]$10917 - attribute \src "libresoc.v:178486.3-178525.6" + attribute \src "libresoc.v:178485.3-178524.6" wire width 4 $4\src21__data_o$next[3:0]$10931 - attribute \src "libresoc.v:178556.3-178595.6" + attribute \src "libresoc.v:178555.3-178594.6" wire width 4 $4\src31__data_o$next[3:0]$10945 - attribute \src "libresoc.v:178596.3-178625.6" + attribute \src "libresoc.v:178595.3-178624.6" wire $4\wr_detect$10[0:0]$10953 - attribute \src "libresoc.v:178666.3-178695.6" + attribute \src "libresoc.v:178665.3-178694.6" wire $4\wr_detect$13[0:0]$10967 - attribute \src "libresoc.v:178359.3-178388.6" + attribute \src "libresoc.v:178358.3-178387.6" wire $4\wr_detect$16[0:0]$10905 - attribute \src "libresoc.v:178456.3-178485.6" + attribute \src "libresoc.v:178455.3-178484.6" wire $4\wr_detect$4[0:0]$10925 - attribute \src "libresoc.v:178526.3-178555.6" + attribute \src "libresoc.v:178525.3-178554.6" wire $4\wr_detect$7[0:0]$10939 - attribute \src "libresoc.v:178289.3-178318.6" + attribute \src "libresoc.v:178288.3-178317.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:178249.3-178288.6" + attribute \src "libresoc.v:178248.3-178287.6" wire width 4 $5\cr_pred1__data_o$next[3:0]$10889 - attribute \src "libresoc.v:178626.3-178665.6" + attribute \src "libresoc.v:178625.3-178664.6" wire width 4 $5\r1__data_o$next[3:0]$10960 - attribute \src "libresoc.v:178319.3-178358.6" + attribute \src "libresoc.v:178318.3-178357.6" wire width 4 $5\r21__data_o$next[3:0]$10898 - attribute \src "libresoc.v:178416.3-178455.6" + attribute \src "libresoc.v:178415.3-178454.6" wire width 4 $5\src11__data_o$next[3:0]$10918 - attribute \src "libresoc.v:178486.3-178525.6" + attribute \src "libresoc.v:178485.3-178524.6" wire width 4 $5\src21__data_o$next[3:0]$10932 - attribute \src "libresoc.v:178556.3-178595.6" + attribute \src "libresoc.v:178555.3-178594.6" wire width 4 $5\src31__data_o$next[3:0]$10946 - attribute \src "libresoc.v:178249.3-178288.6" + attribute \src "libresoc.v:178248.3-178287.6" wire width 4 $6\cr_pred1__data_o$next[3:0]$10890 - attribute \src "libresoc.v:178626.3-178665.6" + attribute \src "libresoc.v:178625.3-178664.6" wire width 4 $6\r1__data_o$next[3:0]$10961 - attribute \src "libresoc.v:178319.3-178358.6" + attribute \src "libresoc.v:178318.3-178357.6" wire width 4 $6\r21__data_o$next[3:0]$10899 - attribute \src "libresoc.v:178416.3-178455.6" + attribute \src "libresoc.v:178415.3-178454.6" wire width 4 $6\src11__data_o$next[3:0]$10919 - attribute \src "libresoc.v:178486.3-178525.6" + attribute \src "libresoc.v:178485.3-178524.6" wire width 4 $6\src21__data_o$next[3:0]$10933 - attribute \src "libresoc.v:178556.3-178595.6" + attribute \src "libresoc.v:178555.3-178594.6" wire width 4 $6\src31__data_o$next[3:0]$10947 - attribute \src "libresoc.v:178229.17-178229.104" - wire $not$libresoc.v:178229$10870_Y + attribute \src "libresoc.v:178228.17-178228.104" + wire $not$libresoc.v:178228$10870_Y + attribute \src "libresoc.v:178229.18-178229.105" + wire $not$libresoc.v:178229$10871_Y attribute \src "libresoc.v:178230.18-178230.105" - wire $not$libresoc.v:178230$10871_Y - attribute \src "libresoc.v:178231.18-178231.105" - wire $not$libresoc.v:178231$10872_Y - attribute \src "libresoc.v:178232.17-178232.100" - wire $not$libresoc.v:178232$10873_Y + wire $not$libresoc.v:178230$10872_Y + attribute \src "libresoc.v:178231.17-178231.100" + wire $not$libresoc.v:178231$10873_Y + attribute \src "libresoc.v:178232.17-178232.103" + wire $not$libresoc.v:178232$10874_Y attribute \src "libresoc.v:178233.17-178233.103" - wire $not$libresoc.v:178233$10874_Y - attribute \src "libresoc.v:178234.17-178234.103" - wire $not$libresoc.v:178234$10875_Y + wire $not$libresoc.v:178233$10875_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -366098,7 +362908,7 @@ module \reg_1 wire width 4 input 13 \dest21__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest21__wen - attribute \src "libresoc.v:178142.7-178142.15" + attribute \src "libresoc.v:178141.7-178141.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r1__data_o @@ -366151,175 +362961,175 @@ module \reg_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178229$10870 + cell $not $not$libresoc.v:178228$10870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:178229$10870_Y + connect \Y $not$libresoc.v:178228$10870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178230$10871 + cell $not $not$libresoc.v:178229$10871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:178230$10871_Y + connect \Y $not$libresoc.v:178229$10871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178231$10872 + cell $not $not$libresoc.v:178230$10872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$16 - connect \Y $not$libresoc.v:178231$10872_Y + connect \Y $not$libresoc.v:178230$10872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178232$10873 + cell $not $not$libresoc.v:178231$10873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:178232$10873_Y + connect \Y $not$libresoc.v:178231$10873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178233$10874 + cell $not $not$libresoc.v:178232$10874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:178233$10874_Y + connect \Y $not$libresoc.v:178232$10874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178234$10875 + cell $not $not$libresoc.v:178233$10875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:178234$10875_Y + connect \Y $not$libresoc.v:178233$10875_Y end - attribute \src "libresoc.v:178142.7-178142.20" - process $proc$libresoc.v:178142$10968 + attribute \src "libresoc.v:178141.7-178141.20" + process $proc$libresoc.v:178141$10968 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178161.13-178161.36" - process $proc$libresoc.v:178161$10969 + attribute \src "libresoc.v:178160.13-178160.36" + process $proc$libresoc.v:178160$10969 assign { } { } assign $1\cr_pred1__data_o[3:0] 4'0000 sync always sync init update \cr_pred1__data_o $1\cr_pred1__data_o[3:0] end - attribute \src "libresoc.v:178176.13-178176.30" - process $proc$libresoc.v:178176$10970 + attribute \src "libresoc.v:178175.13-178175.30" + process $proc$libresoc.v:178175$10970 assign { } { } assign $1\r1__data_o[3:0] 4'0000 sync always sync init update \r1__data_o $1\r1__data_o[3:0] end - attribute \src "libresoc.v:178183.13-178183.31" - process $proc$libresoc.v:178183$10971 + attribute \src "libresoc.v:178182.13-178182.31" + process $proc$libresoc.v:178182$10971 assign { } { } assign $1\r21__data_o[3:0] 4'0000 sync always sync init update \r21__data_o $1\r21__data_o[3:0] end - attribute \src "libresoc.v:178189.13-178189.25" - process $proc$libresoc.v:178189$10972 + attribute \src "libresoc.v:178188.13-178188.25" + process $proc$libresoc.v:178188$10972 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:178194.13-178194.33" - process $proc$libresoc.v:178194$10973 + attribute \src "libresoc.v:178193.13-178193.33" + process $proc$libresoc.v:178193$10973 assign { } { } assign $1\src11__data_o[3:0] 4'0000 sync always sync init update \src11__data_o $1\src11__data_o[3:0] end - attribute \src "libresoc.v:178201.13-178201.33" - process $proc$libresoc.v:178201$10974 + attribute \src "libresoc.v:178200.13-178200.33" + process $proc$libresoc.v:178200$10974 assign { } { } assign $1\src21__data_o[3:0] 4'0000 sync always sync init update \src21__data_o $1\src21__data_o[3:0] end - attribute \src "libresoc.v:178208.13-178208.33" - process $proc$libresoc.v:178208$10975 + attribute \src "libresoc.v:178207.13-178207.33" + process $proc$libresoc.v:178207$10975 assign { } { } assign $1\src31__data_o[3:0] 4'0000 sync always sync init update \src31__data_o $1\src31__data_o[3:0] end - attribute \src "libresoc.v:178235.3-178236.25" - process $proc$libresoc.v:178235$10876 + attribute \src "libresoc.v:178234.3-178235.25" + process $proc$libresoc.v:178234$10876 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:178237.3-178238.39" - process $proc$libresoc.v:178237$10877 + attribute \src "libresoc.v:178236.3-178237.39" + process $proc$libresoc.v:178236$10877 assign { } { } assign $0\r21__data_o[3:0] \r21__data_o$next sync posedge \coresync_clk update \r21__data_o $0\r21__data_o[3:0] end - attribute \src "libresoc.v:178239.3-178240.37" - process $proc$libresoc.v:178239$10878 + attribute \src "libresoc.v:178238.3-178239.37" + process $proc$libresoc.v:178238$10878 assign { } { } assign $0\r1__data_o[3:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[3:0] end - attribute \src "libresoc.v:178241.3-178242.43" - process $proc$libresoc.v:178241$10879 + attribute \src "libresoc.v:178240.3-178241.43" + process $proc$libresoc.v:178240$10879 assign { } { } assign $0\src31__data_o[3:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[3:0] end - attribute \src "libresoc.v:178243.3-178244.43" - process $proc$libresoc.v:178243$10880 + attribute \src "libresoc.v:178242.3-178243.43" + process $proc$libresoc.v:178242$10880 assign { } { } assign $0\src21__data_o[3:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[3:0] end - attribute \src "libresoc.v:178245.3-178246.43" - process $proc$libresoc.v:178245$10881 + attribute \src "libresoc.v:178244.3-178245.43" + process $proc$libresoc.v:178244$10881 assign { } { } assign $0\src11__data_o[3:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[3:0] end - attribute \src "libresoc.v:178247.3-178248.49" - process $proc$libresoc.v:178247$10882 + attribute \src "libresoc.v:178246.3-178247.49" + process $proc$libresoc.v:178246$10882 assign { } { } assign $0\cr_pred1__data_o[3:0] \cr_pred1__data_o$next sync posedge \coresync_clk update \cr_pred1__data_o $0\cr_pred1__data_o[3:0] end - attribute \src "libresoc.v:178249.3-178288.6" - process $proc$libresoc.v:178249$10883 + attribute \src "libresoc.v:178248.3-178287.6" + process $proc$libresoc.v:178248$10883 assign { } { } assign { } { } assign { } { } assign $0\cr_pred1__data_o$next[3:0]$10884 $6\cr_pred1__data_o$next[3:0]$10890 - attribute \src "libresoc.v:178250.5-178250.29" + attribute \src "libresoc.v:178249.5-178249.29" switch \initial - attribute \src "libresoc.v:178250.9-178250.17" + attribute \src "libresoc.v:178249.9-178249.17" case 1'1 case end @@ -366383,14 +363193,14 @@ module \reg_1 sync always update \cr_pred1__data_o$next $0\cr_pred1__data_o$next[3:0]$10884 end - attribute \src "libresoc.v:178289.3-178318.6" - process $proc$libresoc.v:178289$10891 + attribute \src "libresoc.v:178288.3-178317.6" + process $proc$libresoc.v:178288$10891 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:178290.5-178290.29" + attribute \src "libresoc.v:178289.5-178289.29" switch \initial - attribute \src "libresoc.v:178290.9-178290.17" + attribute \src "libresoc.v:178289.9-178289.17" case 1'1 case end @@ -366436,15 +363246,15 @@ module \reg_1 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:178319.3-178358.6" - process $proc$libresoc.v:178319$10892 + attribute \src "libresoc.v:178318.3-178357.6" + process $proc$libresoc.v:178318$10892 assign { } { } assign { } { } assign { } { } assign $0\r21__data_o$next[3:0]$10893 $6\r21__data_o$next[3:0]$10899 - attribute \src "libresoc.v:178320.5-178320.29" + attribute \src "libresoc.v:178319.5-178319.29" switch \initial - attribute \src "libresoc.v:178320.9-178320.17" + attribute \src "libresoc.v:178319.9-178319.17" case 1'1 case end @@ -366508,14 +363318,14 @@ module \reg_1 sync always update \r21__data_o$next $0\r21__data_o$next[3:0]$10893 end - attribute \src "libresoc.v:178359.3-178388.6" - process $proc$libresoc.v:178359$10900 + attribute \src "libresoc.v:178358.3-178387.6" + process $proc$libresoc.v:178358$10900 assign { } { } assign { } { } assign $0\wr_detect$16[0:0]$10901 $1\wr_detect$16[0:0]$10902 - attribute \src "libresoc.v:178360.5-178360.29" + attribute \src "libresoc.v:178359.5-178359.29" switch \initial - attribute \src "libresoc.v:178360.9-178360.17" + attribute \src "libresoc.v:178359.9-178359.17" case 1'1 case end @@ -366561,17 +363371,17 @@ module \reg_1 sync always update \wr_detect$16 $0\wr_detect$16[0:0]$10901 end - attribute \src "libresoc.v:178389.3-178415.6" - process $proc$libresoc.v:178389$10906 + attribute \src "libresoc.v:178388.3-178414.6" + process $proc$libresoc.v:178388$10906 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[3:0]$10907 $4\reg$next[3:0]$10911 - attribute \src "libresoc.v:178390.5-178390.29" + attribute \src "libresoc.v:178389.5-178389.29" switch \initial - attribute \src "libresoc.v:178390.9-178390.17" + attribute \src "libresoc.v:178389.9-178389.17" case 1'1 case end @@ -366614,15 +363424,15 @@ module \reg_1 sync always update \reg$next $0\reg$next[3:0]$10907 end - attribute \src "libresoc.v:178416.3-178455.6" - process $proc$libresoc.v:178416$10912 + attribute \src "libresoc.v:178415.3-178454.6" + process $proc$libresoc.v:178415$10912 assign { } { } assign { } { } assign { } { } assign $0\src11__data_o$next[3:0]$10913 $6\src11__data_o$next[3:0]$10919 - attribute \src "libresoc.v:178417.5-178417.29" + attribute \src "libresoc.v:178416.5-178416.29" switch \initial - attribute \src "libresoc.v:178417.9-178417.17" + attribute \src "libresoc.v:178416.9-178416.17" case 1'1 case end @@ -366686,14 +363496,14 @@ module \reg_1 sync always update \src11__data_o$next $0\src11__data_o$next[3:0]$10913 end - attribute \src "libresoc.v:178456.3-178485.6" - process $proc$libresoc.v:178456$10920 + attribute \src "libresoc.v:178455.3-178484.6" + process $proc$libresoc.v:178455$10920 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$10921 $1\wr_detect$4[0:0]$10922 - attribute \src "libresoc.v:178457.5-178457.29" + attribute \src "libresoc.v:178456.5-178456.29" switch \initial - attribute \src "libresoc.v:178457.9-178457.17" + attribute \src "libresoc.v:178456.9-178456.17" case 1'1 case end @@ -366739,15 +363549,15 @@ module \reg_1 sync always update \wr_detect$4 $0\wr_detect$4[0:0]$10921 end - attribute \src "libresoc.v:178486.3-178525.6" - process $proc$libresoc.v:178486$10926 + attribute \src "libresoc.v:178485.3-178524.6" + process $proc$libresoc.v:178485$10926 assign { } { } assign { } { } assign { } { } assign $0\src21__data_o$next[3:0]$10927 $6\src21__data_o$next[3:0]$10933 - attribute \src "libresoc.v:178487.5-178487.29" + attribute \src "libresoc.v:178486.5-178486.29" switch \initial - attribute \src "libresoc.v:178487.9-178487.17" + attribute \src "libresoc.v:178486.9-178486.17" case 1'1 case end @@ -366811,14 +363621,14 @@ module \reg_1 sync always update \src21__data_o$next $0\src21__data_o$next[3:0]$10927 end - attribute \src "libresoc.v:178526.3-178555.6" - process $proc$libresoc.v:178526$10934 + attribute \src "libresoc.v:178525.3-178554.6" + process $proc$libresoc.v:178525$10934 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$10935 $1\wr_detect$7[0:0]$10936 - attribute \src "libresoc.v:178527.5-178527.29" + attribute \src "libresoc.v:178526.5-178526.29" switch \initial - attribute \src "libresoc.v:178527.9-178527.17" + attribute \src "libresoc.v:178526.9-178526.17" case 1'1 case end @@ -366864,15 +363674,15 @@ module \reg_1 sync always update \wr_detect$7 $0\wr_detect$7[0:0]$10935 end - attribute \src "libresoc.v:178556.3-178595.6" - process $proc$libresoc.v:178556$10940 + attribute \src "libresoc.v:178555.3-178594.6" + process $proc$libresoc.v:178555$10940 assign { } { } assign { } { } assign { } { } assign $0\src31__data_o$next[3:0]$10941 $6\src31__data_o$next[3:0]$10947 - attribute \src "libresoc.v:178557.5-178557.29" + attribute \src "libresoc.v:178556.5-178556.29" switch \initial - attribute \src "libresoc.v:178557.9-178557.17" + attribute \src "libresoc.v:178556.9-178556.17" case 1'1 case end @@ -366936,14 +363746,14 @@ module \reg_1 sync always update \src31__data_o$next $0\src31__data_o$next[3:0]$10941 end - attribute \src "libresoc.v:178596.3-178625.6" - process $proc$libresoc.v:178596$10948 + attribute \src "libresoc.v:178595.3-178624.6" + process $proc$libresoc.v:178595$10948 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$10949 $1\wr_detect$10[0:0]$10950 - attribute \src "libresoc.v:178597.5-178597.29" + attribute \src "libresoc.v:178596.5-178596.29" switch \initial - attribute \src "libresoc.v:178597.9-178597.17" + attribute \src "libresoc.v:178596.9-178596.17" case 1'1 case end @@ -366989,15 +363799,15 @@ module \reg_1 sync always update \wr_detect$10 $0\wr_detect$10[0:0]$10949 end - attribute \src "libresoc.v:178626.3-178665.6" - process $proc$libresoc.v:178626$10954 + attribute \src "libresoc.v:178625.3-178664.6" + process $proc$libresoc.v:178625$10954 assign { } { } assign { } { } assign { } { } assign $0\r1__data_o$next[3:0]$10955 $6\r1__data_o$next[3:0]$10961 - attribute \src "libresoc.v:178627.5-178627.29" + attribute \src "libresoc.v:178626.5-178626.29" switch \initial - attribute \src "libresoc.v:178627.9-178627.17" + attribute \src "libresoc.v:178626.9-178626.17" case 1'1 case end @@ -367061,14 +363871,14 @@ module \reg_1 sync always update \r1__data_o$next $0\r1__data_o$next[3:0]$10955 end - attribute \src "libresoc.v:178666.3-178695.6" - process $proc$libresoc.v:178666$10962 + attribute \src "libresoc.v:178665.3-178694.6" + process $proc$libresoc.v:178665$10962 assign { } { } assign { } { } assign $0\wr_detect$13[0:0]$10963 $1\wr_detect$13[0:0]$10964 - attribute \src "libresoc.v:178667.5-178667.29" + attribute \src "libresoc.v:178666.5-178666.29" switch \initial - attribute \src "libresoc.v:178667.9-178667.17" + attribute \src "libresoc.v:178666.9-178666.17" case 1'1 case end @@ -367114,172 +363924,172 @@ module \reg_1 sync always update \wr_detect$13 $0\wr_detect$13[0:0]$10963 end - connect \$9 $not$libresoc.v:178229$10870_Y - connect \$12 $not$libresoc.v:178230$10871_Y - connect \$15 $not$libresoc.v:178231$10872_Y - connect \$1 $not$libresoc.v:178232$10873_Y - connect \$3 $not$libresoc.v:178233$10874_Y - connect \$6 $not$libresoc.v:178234$10875_Y + connect \$9 $not$libresoc.v:178228$10870_Y + connect \$12 $not$libresoc.v:178229$10871_Y + connect \$15 $not$libresoc.v:178230$10872_Y + connect \$1 $not$libresoc.v:178231$10873_Y + connect \$3 $not$libresoc.v:178232$10874_Y + connect \$6 $not$libresoc.v:178233$10875_Y end -attribute \src "libresoc.v:178700.1-179145.10" +attribute \src "libresoc.v:178699.1-179144.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_1" attribute \generator "nMigen" module \reg_1$133 - attribute \src "libresoc.v:178701.7-178701.20" + attribute \src "libresoc.v:178700.7-178700.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179030.3-179075.6" + attribute \src "libresoc.v:179029.3-179074.6" wire width 2 $0\r1__data_o$next[1:0]$11028 - attribute \src "libresoc.v:178776.3-178777.37" + attribute \src "libresoc.v:178775.3-178776.37" wire width 2 $0\r1__data_o[1:0] - attribute \src "libresoc.v:179112.3-179144.6" + attribute \src "libresoc.v:179111.3-179143.6" wire width 2 $0\reg$next[1:0]$11044 - attribute \src "libresoc.v:178774.3-178775.25" + attribute \src "libresoc.v:178773.3-178774.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:178784.3-178829.6" + attribute \src "libresoc.v:178783.3-178828.6" wire width 2 $0\src11__data_o$next[1:0]$10986 - attribute \src "libresoc.v:178782.3-178783.43" + attribute \src "libresoc.v:178781.3-178782.43" wire width 2 $0\src11__data_o[1:0] - attribute \src "libresoc.v:178866.3-178911.6" + attribute \src "libresoc.v:178865.3-178910.6" wire width 2 $0\src21__data_o$next[1:0]$10996 - attribute \src "libresoc.v:178780.3-178781.43" + attribute \src "libresoc.v:178779.3-178780.43" wire width 2 $0\src21__data_o[1:0] - attribute \src "libresoc.v:178948.3-178993.6" + attribute \src "libresoc.v:178947.3-178992.6" wire width 2 $0\src31__data_o$next[1:0]$11012 - attribute \src "libresoc.v:178778.3-178779.43" + attribute \src "libresoc.v:178777.3-178778.43" wire width 2 $0\src31__data_o[1:0] - attribute \src "libresoc.v:179076.3-179111.6" + attribute \src "libresoc.v:179075.3-179110.6" wire $0\wr_detect$10[0:0]$11037 - attribute \src "libresoc.v:178912.3-178947.6" + attribute \src "libresoc.v:178911.3-178946.6" wire $0\wr_detect$4[0:0]$11005 - attribute \src "libresoc.v:178994.3-179029.6" + attribute \src "libresoc.v:178993.3-179028.6" wire $0\wr_detect$7[0:0]$11021 - attribute \src "libresoc.v:178830.3-178865.6" + attribute \src "libresoc.v:178829.3-178864.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:179030.3-179075.6" + attribute \src "libresoc.v:179029.3-179074.6" wire width 2 $1\r1__data_o$next[1:0]$11029 - attribute \src "libresoc.v:178728.13-178728.30" + attribute \src "libresoc.v:178727.13-178727.30" wire width 2 $1\r1__data_o[1:0] - attribute \src "libresoc.v:179112.3-179144.6" + attribute \src "libresoc.v:179111.3-179143.6" wire width 2 $1\reg$next[1:0]$11045 - attribute \src "libresoc.v:178734.13-178734.25" + attribute \src "libresoc.v:178733.13-178733.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:178784.3-178829.6" + attribute \src "libresoc.v:178783.3-178828.6" wire width 2 $1\src11__data_o$next[1:0]$10987 - attribute \src "libresoc.v:178739.13-178739.33" + attribute \src "libresoc.v:178738.13-178738.33" wire width 2 $1\src11__data_o[1:0] - attribute \src "libresoc.v:178866.3-178911.6" + attribute \src "libresoc.v:178865.3-178910.6" wire width 2 $1\src21__data_o$next[1:0]$10997 - attribute \src "libresoc.v:178746.13-178746.33" + attribute \src "libresoc.v:178745.13-178745.33" wire width 2 $1\src21__data_o[1:0] - attribute \src "libresoc.v:178948.3-178993.6" + attribute \src "libresoc.v:178947.3-178992.6" wire width 2 $1\src31__data_o$next[1:0]$11013 - attribute \src "libresoc.v:178753.13-178753.33" + attribute \src "libresoc.v:178752.13-178752.33" wire width 2 $1\src31__data_o[1:0] - attribute \src "libresoc.v:179076.3-179111.6" + attribute \src "libresoc.v:179075.3-179110.6" wire $1\wr_detect$10[0:0]$11038 - attribute \src "libresoc.v:178912.3-178947.6" + attribute \src "libresoc.v:178911.3-178946.6" wire $1\wr_detect$4[0:0]$11006 - attribute \src "libresoc.v:178994.3-179029.6" + attribute \src "libresoc.v:178993.3-179028.6" wire $1\wr_detect$7[0:0]$11022 - attribute \src "libresoc.v:178830.3-178865.6" + attribute \src "libresoc.v:178829.3-178864.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:179030.3-179075.6" + attribute \src "libresoc.v:179029.3-179074.6" wire width 2 $2\r1__data_o$next[1:0]$11030 - attribute \src "libresoc.v:179112.3-179144.6" + attribute \src "libresoc.v:179111.3-179143.6" wire width 2 $2\reg$next[1:0]$11046 - attribute \src "libresoc.v:178784.3-178829.6" + attribute \src "libresoc.v:178783.3-178828.6" wire width 2 $2\src11__data_o$next[1:0]$10988 - attribute \src "libresoc.v:178866.3-178911.6" + attribute \src "libresoc.v:178865.3-178910.6" wire width 2 $2\src21__data_o$next[1:0]$10998 - attribute \src "libresoc.v:178948.3-178993.6" + attribute \src "libresoc.v:178947.3-178992.6" wire width 2 $2\src31__data_o$next[1:0]$11014 - attribute \src "libresoc.v:179076.3-179111.6" + attribute \src "libresoc.v:179075.3-179110.6" wire $2\wr_detect$10[0:0]$11039 - attribute \src "libresoc.v:178912.3-178947.6" + attribute \src "libresoc.v:178911.3-178946.6" wire $2\wr_detect$4[0:0]$11007 - attribute \src "libresoc.v:178994.3-179029.6" + attribute \src "libresoc.v:178993.3-179028.6" wire $2\wr_detect$7[0:0]$11023 - attribute \src "libresoc.v:178830.3-178865.6" + attribute \src "libresoc.v:178829.3-178864.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:179030.3-179075.6" + attribute \src "libresoc.v:179029.3-179074.6" wire width 2 $3\r1__data_o$next[1:0]$11031 - attribute \src "libresoc.v:179112.3-179144.6" + attribute \src "libresoc.v:179111.3-179143.6" wire width 2 $3\reg$next[1:0]$11047 - attribute \src "libresoc.v:178784.3-178829.6" + attribute \src "libresoc.v:178783.3-178828.6" wire width 2 $3\src11__data_o$next[1:0]$10989 - attribute \src "libresoc.v:178866.3-178911.6" + attribute \src "libresoc.v:178865.3-178910.6" wire width 2 $3\src21__data_o$next[1:0]$10999 - attribute \src "libresoc.v:178948.3-178993.6" + attribute \src "libresoc.v:178947.3-178992.6" wire width 2 $3\src31__data_o$next[1:0]$11015 - attribute \src "libresoc.v:179076.3-179111.6" + attribute \src "libresoc.v:179075.3-179110.6" wire $3\wr_detect$10[0:0]$11040 - attribute \src "libresoc.v:178912.3-178947.6" + attribute \src "libresoc.v:178911.3-178946.6" wire $3\wr_detect$4[0:0]$11008 - attribute \src "libresoc.v:178994.3-179029.6" + attribute \src "libresoc.v:178993.3-179028.6" wire $3\wr_detect$7[0:0]$11024 - attribute \src "libresoc.v:178830.3-178865.6" + attribute \src "libresoc.v:178829.3-178864.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:179030.3-179075.6" + attribute \src "libresoc.v:179029.3-179074.6" wire width 2 $4\r1__data_o$next[1:0]$11032 - attribute \src "libresoc.v:179112.3-179144.6" + attribute \src "libresoc.v:179111.3-179143.6" wire width 2 $4\reg$next[1:0]$11048 - attribute \src "libresoc.v:178784.3-178829.6" + attribute \src "libresoc.v:178783.3-178828.6" wire width 2 $4\src11__data_o$next[1:0]$10990 - attribute \src "libresoc.v:178866.3-178911.6" + attribute \src "libresoc.v:178865.3-178910.6" wire width 2 $4\src21__data_o$next[1:0]$11000 - attribute \src "libresoc.v:178948.3-178993.6" + attribute \src "libresoc.v:178947.3-178992.6" wire width 2 $4\src31__data_o$next[1:0]$11016 - attribute \src "libresoc.v:179076.3-179111.6" + attribute \src "libresoc.v:179075.3-179110.6" wire $4\wr_detect$10[0:0]$11041 - attribute \src "libresoc.v:178912.3-178947.6" + attribute \src "libresoc.v:178911.3-178946.6" wire $4\wr_detect$4[0:0]$11009 - attribute \src "libresoc.v:178994.3-179029.6" + attribute \src "libresoc.v:178993.3-179028.6" wire $4\wr_detect$7[0:0]$11025 - attribute \src "libresoc.v:178830.3-178865.6" + attribute \src "libresoc.v:178829.3-178864.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:179030.3-179075.6" + attribute \src "libresoc.v:179029.3-179074.6" wire width 2 $5\r1__data_o$next[1:0]$11033 - attribute \src "libresoc.v:179112.3-179144.6" + attribute \src "libresoc.v:179111.3-179143.6" wire width 2 $5\reg$next[1:0]$11049 - attribute \src "libresoc.v:178784.3-178829.6" + attribute \src "libresoc.v:178783.3-178828.6" wire width 2 $5\src11__data_o$next[1:0]$10991 - attribute \src "libresoc.v:178866.3-178911.6" + attribute \src "libresoc.v:178865.3-178910.6" wire width 2 $5\src21__data_o$next[1:0]$11001 - attribute \src "libresoc.v:178948.3-178993.6" + attribute \src "libresoc.v:178947.3-178992.6" wire width 2 $5\src31__data_o$next[1:0]$11017 - attribute \src "libresoc.v:179076.3-179111.6" + attribute \src "libresoc.v:179075.3-179110.6" wire $5\wr_detect$10[0:0]$11042 - attribute \src "libresoc.v:178912.3-178947.6" + attribute \src "libresoc.v:178911.3-178946.6" wire $5\wr_detect$4[0:0]$11010 - attribute \src "libresoc.v:178994.3-179029.6" + attribute \src "libresoc.v:178993.3-179028.6" wire $5\wr_detect$7[0:0]$11026 - attribute \src "libresoc.v:178830.3-178865.6" + attribute \src "libresoc.v:178829.3-178864.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:179030.3-179075.6" + attribute \src "libresoc.v:179029.3-179074.6" wire width 2 $6\r1__data_o$next[1:0]$11034 - attribute \src "libresoc.v:178784.3-178829.6" + attribute \src "libresoc.v:178783.3-178828.6" wire width 2 $6\src11__data_o$next[1:0]$10992 - attribute \src "libresoc.v:178866.3-178911.6" + attribute \src "libresoc.v:178865.3-178910.6" wire width 2 $6\src21__data_o$next[1:0]$11002 - attribute \src "libresoc.v:178948.3-178993.6" + attribute \src "libresoc.v:178947.3-178992.6" wire width 2 $6\src31__data_o$next[1:0]$11018 - attribute \src "libresoc.v:179030.3-179075.6" + attribute \src "libresoc.v:179029.3-179074.6" wire width 2 $7\r1__data_o$next[1:0]$11035 - attribute \src "libresoc.v:178784.3-178829.6" + attribute \src "libresoc.v:178783.3-178828.6" wire width 2 $7\src11__data_o$next[1:0]$10993 - attribute \src "libresoc.v:178866.3-178911.6" + attribute \src "libresoc.v:178865.3-178910.6" wire width 2 $7\src21__data_o$next[1:0]$11003 - attribute \src "libresoc.v:178948.3-178993.6" + attribute \src "libresoc.v:178947.3-178992.6" wire width 2 $7\src31__data_o$next[1:0]$11019 - attribute \src "libresoc.v:178770.17-178770.104" - wire $not$libresoc.v:178770$10976_Y - attribute \src "libresoc.v:178771.17-178771.100" - wire $not$libresoc.v:178771$10977_Y + attribute \src "libresoc.v:178769.17-178769.104" + wire $not$libresoc.v:178769$10976_Y + attribute \src "libresoc.v:178770.17-178770.100" + wire $not$libresoc.v:178770$10977_Y + attribute \src "libresoc.v:178771.17-178771.103" + wire $not$libresoc.v:178771$10978_Y attribute \src "libresoc.v:178772.17-178772.103" - wire $not$libresoc.v:178772$10978_Y - attribute \src "libresoc.v:178773.17-178773.103" - wire $not$libresoc.v:178773$10979_Y + wire $not$libresoc.v:178772$10979_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -367304,7 +364114,7 @@ module \reg_1$133 wire width 2 input 13 \dest31__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest31__wen - attribute \src "libresoc.v:178701.7-178701.15" + attribute \src "libresoc.v:178700.7-178700.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r1__data_o @@ -367347,129 +364157,129 @@ module \reg_1$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178770$10976 + cell $not $not$libresoc.v:178769$10976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:178770$10976_Y + connect \Y $not$libresoc.v:178769$10976_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178771$10977 + cell $not $not$libresoc.v:178770$10977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:178771$10977_Y + connect \Y $not$libresoc.v:178770$10977_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178772$10978 + cell $not $not$libresoc.v:178771$10978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:178772$10978_Y + connect \Y $not$libresoc.v:178771$10978_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178773$10979 + cell $not $not$libresoc.v:178772$10979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:178773$10979_Y + connect \Y $not$libresoc.v:178772$10979_Y end - attribute \src "libresoc.v:178701.7-178701.20" - process $proc$libresoc.v:178701$11050 + attribute \src "libresoc.v:178700.7-178700.20" + process $proc$libresoc.v:178700$11050 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178728.13-178728.30" - process $proc$libresoc.v:178728$11051 + attribute \src "libresoc.v:178727.13-178727.30" + process $proc$libresoc.v:178727$11051 assign { } { } assign $1\r1__data_o[1:0] 2'00 sync always sync init update \r1__data_o $1\r1__data_o[1:0] end - attribute \src "libresoc.v:178734.13-178734.25" - process $proc$libresoc.v:178734$11052 + attribute \src "libresoc.v:178733.13-178733.25" + process $proc$libresoc.v:178733$11052 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:178739.13-178739.33" - process $proc$libresoc.v:178739$11053 + attribute \src "libresoc.v:178738.13-178738.33" + process $proc$libresoc.v:178738$11053 assign { } { } assign $1\src11__data_o[1:0] 2'00 sync always sync init update \src11__data_o $1\src11__data_o[1:0] end - attribute \src "libresoc.v:178746.13-178746.33" - process $proc$libresoc.v:178746$11054 + attribute \src "libresoc.v:178745.13-178745.33" + process $proc$libresoc.v:178745$11054 assign { } { } assign $1\src21__data_o[1:0] 2'00 sync always sync init update \src21__data_o $1\src21__data_o[1:0] end - attribute \src "libresoc.v:178753.13-178753.33" - process $proc$libresoc.v:178753$11055 + attribute \src "libresoc.v:178752.13-178752.33" + process $proc$libresoc.v:178752$11055 assign { } { } assign $1\src31__data_o[1:0] 2'00 sync always sync init update \src31__data_o $1\src31__data_o[1:0] end - attribute \src "libresoc.v:178774.3-178775.25" - process $proc$libresoc.v:178774$10980 + attribute \src "libresoc.v:178773.3-178774.25" + process $proc$libresoc.v:178773$10980 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:178776.3-178777.37" - process $proc$libresoc.v:178776$10981 + attribute \src "libresoc.v:178775.3-178776.37" + process $proc$libresoc.v:178775$10981 assign { } { } assign $0\r1__data_o[1:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[1:0] end - attribute \src "libresoc.v:178778.3-178779.43" - process $proc$libresoc.v:178778$10982 + attribute \src "libresoc.v:178777.3-178778.43" + process $proc$libresoc.v:178777$10982 assign { } { } assign $0\src31__data_o[1:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[1:0] end - attribute \src "libresoc.v:178780.3-178781.43" - process $proc$libresoc.v:178780$10983 + attribute \src "libresoc.v:178779.3-178780.43" + process $proc$libresoc.v:178779$10983 assign { } { } assign $0\src21__data_o[1:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[1:0] end - attribute \src "libresoc.v:178782.3-178783.43" - process $proc$libresoc.v:178782$10984 + attribute \src "libresoc.v:178781.3-178782.43" + process $proc$libresoc.v:178781$10984 assign { } { } assign $0\src11__data_o[1:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[1:0] end - attribute \src "libresoc.v:178784.3-178829.6" - process $proc$libresoc.v:178784$10985 + attribute \src "libresoc.v:178783.3-178828.6" + process $proc$libresoc.v:178783$10985 assign { } { } assign { } { } assign { } { } assign $0\src11__data_o$next[1:0]$10986 $7\src11__data_o$next[1:0]$10993 - attribute \src "libresoc.v:178785.5-178785.29" + attribute \src "libresoc.v:178784.5-178784.29" switch \initial - attribute \src "libresoc.v:178785.9-178785.17" + attribute \src "libresoc.v:178784.9-178784.17" case 1'1 case end @@ -367543,14 +364353,14 @@ module \reg_1$133 sync always update \src11__data_o$next $0\src11__data_o$next[1:0]$10986 end - attribute \src "libresoc.v:178830.3-178865.6" - process $proc$libresoc.v:178830$10994 + attribute \src "libresoc.v:178829.3-178864.6" + process $proc$libresoc.v:178829$10994 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:178831.5-178831.29" + attribute \src "libresoc.v:178830.5-178830.29" switch \initial - attribute \src "libresoc.v:178831.9-178831.17" + attribute \src "libresoc.v:178830.9-178830.17" case 1'1 case end @@ -367606,15 +364416,15 @@ module \reg_1$133 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:178866.3-178911.6" - process $proc$libresoc.v:178866$10995 + attribute \src "libresoc.v:178865.3-178910.6" + process $proc$libresoc.v:178865$10995 assign { } { } assign { } { } assign { } { } assign $0\src21__data_o$next[1:0]$10996 $7\src21__data_o$next[1:0]$11003 - attribute \src "libresoc.v:178867.5-178867.29" + attribute \src "libresoc.v:178866.5-178866.29" switch \initial - attribute \src "libresoc.v:178867.9-178867.17" + attribute \src "libresoc.v:178866.9-178866.17" case 1'1 case end @@ -367688,14 +364498,14 @@ module \reg_1$133 sync always update \src21__data_o$next $0\src21__data_o$next[1:0]$10996 end - attribute \src "libresoc.v:178912.3-178947.6" - process $proc$libresoc.v:178912$11004 + attribute \src "libresoc.v:178911.3-178946.6" + process $proc$libresoc.v:178911$11004 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11005 $1\wr_detect$4[0:0]$11006 - attribute \src "libresoc.v:178913.5-178913.29" + attribute \src "libresoc.v:178912.5-178912.29" switch \initial - attribute \src "libresoc.v:178913.9-178913.17" + attribute \src "libresoc.v:178912.9-178912.17" case 1'1 case end @@ -367751,15 +364561,15 @@ module \reg_1$133 sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11005 end - attribute \src "libresoc.v:178948.3-178993.6" - process $proc$libresoc.v:178948$11011 + attribute \src "libresoc.v:178947.3-178992.6" + process $proc$libresoc.v:178947$11011 assign { } { } assign { } { } assign { } { } assign $0\src31__data_o$next[1:0]$11012 $7\src31__data_o$next[1:0]$11019 - attribute \src "libresoc.v:178949.5-178949.29" + attribute \src "libresoc.v:178948.5-178948.29" switch \initial - attribute \src "libresoc.v:178949.9-178949.17" + attribute \src "libresoc.v:178948.9-178948.17" case 1'1 case end @@ -367833,14 +364643,14 @@ module \reg_1$133 sync always update \src31__data_o$next $0\src31__data_o$next[1:0]$11012 end - attribute \src "libresoc.v:178994.3-179029.6" - process $proc$libresoc.v:178994$11020 + attribute \src "libresoc.v:178993.3-179028.6" + process $proc$libresoc.v:178993$11020 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11021 $1\wr_detect$7[0:0]$11022 - attribute \src "libresoc.v:178995.5-178995.29" + attribute \src "libresoc.v:178994.5-178994.29" switch \initial - attribute \src "libresoc.v:178995.9-178995.17" + attribute \src "libresoc.v:178994.9-178994.17" case 1'1 case end @@ -367896,15 +364706,15 @@ module \reg_1$133 sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11021 end - attribute \src "libresoc.v:179030.3-179075.6" - process $proc$libresoc.v:179030$11027 + attribute \src "libresoc.v:179029.3-179074.6" + process $proc$libresoc.v:179029$11027 assign { } { } assign { } { } assign { } { } assign $0\r1__data_o$next[1:0]$11028 $7\r1__data_o$next[1:0]$11035 - attribute \src "libresoc.v:179031.5-179031.29" + attribute \src "libresoc.v:179030.5-179030.29" switch \initial - attribute \src "libresoc.v:179031.9-179031.17" + attribute \src "libresoc.v:179030.9-179030.17" case 1'1 case end @@ -367978,14 +364788,14 @@ module \reg_1$133 sync always update \r1__data_o$next $0\r1__data_o$next[1:0]$11028 end - attribute \src "libresoc.v:179076.3-179111.6" - process $proc$libresoc.v:179076$11036 + attribute \src "libresoc.v:179075.3-179110.6" + process $proc$libresoc.v:179075$11036 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$11037 $1\wr_detect$10[0:0]$11038 - attribute \src "libresoc.v:179077.5-179077.29" + attribute \src "libresoc.v:179076.5-179076.29" switch \initial - attribute \src "libresoc.v:179077.9-179077.17" + attribute \src "libresoc.v:179076.9-179076.17" case 1'1 case end @@ -368041,8 +364851,8 @@ module \reg_1$133 sync always update \wr_detect$10 $0\wr_detect$10[0:0]$11037 end - attribute \src "libresoc.v:179112.3-179144.6" - process $proc$libresoc.v:179112$11043 + attribute \src "libresoc.v:179111.3-179143.6" + process $proc$libresoc.v:179111$11043 assign { } { } assign { } { } assign { } { } @@ -368050,9 +364860,9 @@ module \reg_1$133 assign { } { } assign { } { } assign $0\reg$next[1:0]$11044 $5\reg$next[1:0]$11049 - attribute \src "libresoc.v:179113.5-179113.29" + attribute \src "libresoc.v:179112.5-179112.29" switch \initial - attribute \src "libresoc.v:179113.9-179113.17" + attribute \src "libresoc.v:179112.9-179112.17" case 1'1 case end @@ -368104,136 +364914,136 @@ module \reg_1$133 sync always update \reg$next $0\reg$next[1:0]$11044 end - connect \$9 $not$libresoc.v:178770$10976_Y - connect \$1 $not$libresoc.v:178771$10977_Y - connect \$3 $not$libresoc.v:178772$10978_Y - connect \$6 $not$libresoc.v:178773$10979_Y + connect \$9 $not$libresoc.v:178769$10976_Y + connect \$1 $not$libresoc.v:178770$10977_Y + connect \$3 $not$libresoc.v:178771$10978_Y + connect \$6 $not$libresoc.v:178772$10979_Y end -attribute \src "libresoc.v:179149.1-179498.10" +attribute \src "libresoc.v:179148.1-179497.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_1" attribute \generator "nMigen" module \reg_1$136 - attribute \src "libresoc.v:179219.3-179264.6" + attribute \src "libresoc.v:179218.3-179263.6" wire width 64 $0\cia1__data_o$next[63:0]$11064 - attribute \src "libresoc.v:179217.3-179218.41" + attribute \src "libresoc.v:179216.3-179217.41" wire width 64 $0\cia1__data_o[63:0] - attribute \src "libresoc.v:179150.7-179150.20" + attribute \src "libresoc.v:179149.7-179149.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179301.3-179346.6" + attribute \src "libresoc.v:179300.3-179345.6" wire width 64 $0\msr1__data_o$next[63:0]$11074 - attribute \src "libresoc.v:179215.3-179216.41" + attribute \src "libresoc.v:179214.3-179215.41" wire width 64 $0\msr1__data_o[63:0] - attribute \src "libresoc.v:179465.3-179497.6" + attribute \src "libresoc.v:179464.3-179496.6" wire width 64 $0\reg$next[63:0]$11106 - attribute \src "libresoc.v:179211.3-179212.25" + attribute \src "libresoc.v:179210.3-179211.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:179383.3-179428.6" + attribute \src "libresoc.v:179382.3-179427.6" wire width 64 $0\sv1__data_o$next[63:0]$11090 - attribute \src "libresoc.v:179213.3-179214.39" + attribute \src "libresoc.v:179212.3-179213.39" wire width 64 $0\sv1__data_o[63:0] - attribute \src "libresoc.v:179347.3-179382.6" + attribute \src "libresoc.v:179346.3-179381.6" wire $0\wr_detect$4[0:0]$11083 - attribute \src "libresoc.v:179429.3-179464.6" + attribute \src "libresoc.v:179428.3-179463.6" wire $0\wr_detect$7[0:0]$11099 - attribute \src "libresoc.v:179265.3-179300.6" + attribute \src "libresoc.v:179264.3-179299.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:179219.3-179264.6" + attribute \src "libresoc.v:179218.3-179263.6" wire width 64 $1\cia1__data_o$next[63:0]$11065 - attribute \src "libresoc.v:179159.14-179159.49" + attribute \src "libresoc.v:179158.14-179158.49" wire width 64 $1\cia1__data_o[63:0] - attribute \src "libresoc.v:179301.3-179346.6" + attribute \src "libresoc.v:179300.3-179345.6" wire width 64 $1\msr1__data_o$next[63:0]$11075 - attribute \src "libresoc.v:179176.14-179176.49" + attribute \src "libresoc.v:179175.14-179175.49" wire width 64 $1\msr1__data_o[63:0] - attribute \src "libresoc.v:179465.3-179497.6" + attribute \src "libresoc.v:179464.3-179496.6" wire width 64 $1\reg$next[63:0]$11107 - attribute \src "libresoc.v:179188.14-179188.42" + attribute \src "libresoc.v:179187.14-179187.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:179383.3-179428.6" + attribute \src "libresoc.v:179382.3-179427.6" wire width 64 $1\sv1__data_o$next[63:0]$11091 - attribute \src "libresoc.v:179195.14-179195.48" + attribute \src "libresoc.v:179194.14-179194.48" wire width 64 $1\sv1__data_o[63:0] - attribute \src "libresoc.v:179347.3-179382.6" + attribute \src "libresoc.v:179346.3-179381.6" wire $1\wr_detect$4[0:0]$11084 - attribute \src "libresoc.v:179429.3-179464.6" + attribute \src "libresoc.v:179428.3-179463.6" wire $1\wr_detect$7[0:0]$11100 - attribute \src "libresoc.v:179265.3-179300.6" + attribute \src "libresoc.v:179264.3-179299.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:179219.3-179264.6" + attribute \src "libresoc.v:179218.3-179263.6" wire width 64 $2\cia1__data_o$next[63:0]$11066 - attribute \src "libresoc.v:179301.3-179346.6" + attribute \src "libresoc.v:179300.3-179345.6" wire width 64 $2\msr1__data_o$next[63:0]$11076 - attribute \src "libresoc.v:179465.3-179497.6" + attribute \src "libresoc.v:179464.3-179496.6" wire width 64 $2\reg$next[63:0]$11108 - attribute \src "libresoc.v:179383.3-179428.6" + attribute \src "libresoc.v:179382.3-179427.6" wire width 64 $2\sv1__data_o$next[63:0]$11092 - attribute \src "libresoc.v:179347.3-179382.6" + attribute \src "libresoc.v:179346.3-179381.6" wire $2\wr_detect$4[0:0]$11085 - attribute \src "libresoc.v:179429.3-179464.6" + attribute \src "libresoc.v:179428.3-179463.6" wire $2\wr_detect$7[0:0]$11101 - attribute \src "libresoc.v:179265.3-179300.6" + attribute \src "libresoc.v:179264.3-179299.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:179219.3-179264.6" + attribute \src "libresoc.v:179218.3-179263.6" wire width 64 $3\cia1__data_o$next[63:0]$11067 - attribute \src "libresoc.v:179301.3-179346.6" + attribute \src "libresoc.v:179300.3-179345.6" wire width 64 $3\msr1__data_o$next[63:0]$11077 - attribute \src "libresoc.v:179465.3-179497.6" + attribute \src "libresoc.v:179464.3-179496.6" wire width 64 $3\reg$next[63:0]$11109 - attribute \src "libresoc.v:179383.3-179428.6" + attribute \src "libresoc.v:179382.3-179427.6" wire width 64 $3\sv1__data_o$next[63:0]$11093 - attribute \src "libresoc.v:179347.3-179382.6" + attribute \src "libresoc.v:179346.3-179381.6" wire $3\wr_detect$4[0:0]$11086 - attribute \src "libresoc.v:179429.3-179464.6" + attribute \src "libresoc.v:179428.3-179463.6" wire $3\wr_detect$7[0:0]$11102 - attribute \src "libresoc.v:179265.3-179300.6" + attribute \src "libresoc.v:179264.3-179299.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:179219.3-179264.6" + attribute \src "libresoc.v:179218.3-179263.6" wire width 64 $4\cia1__data_o$next[63:0]$11068 - attribute \src "libresoc.v:179301.3-179346.6" + attribute \src "libresoc.v:179300.3-179345.6" wire width 64 $4\msr1__data_o$next[63:0]$11078 - attribute \src "libresoc.v:179465.3-179497.6" + attribute \src "libresoc.v:179464.3-179496.6" wire width 64 $4\reg$next[63:0]$11110 - attribute \src "libresoc.v:179383.3-179428.6" + attribute \src "libresoc.v:179382.3-179427.6" wire width 64 $4\sv1__data_o$next[63:0]$11094 - attribute \src "libresoc.v:179347.3-179382.6" + attribute \src "libresoc.v:179346.3-179381.6" wire $4\wr_detect$4[0:0]$11087 - attribute \src "libresoc.v:179429.3-179464.6" + attribute \src "libresoc.v:179428.3-179463.6" wire $4\wr_detect$7[0:0]$11103 - attribute \src "libresoc.v:179265.3-179300.6" + attribute \src "libresoc.v:179264.3-179299.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:179219.3-179264.6" + attribute \src "libresoc.v:179218.3-179263.6" wire width 64 $5\cia1__data_o$next[63:0]$11069 - attribute \src "libresoc.v:179301.3-179346.6" + attribute \src "libresoc.v:179300.3-179345.6" wire width 64 $5\msr1__data_o$next[63:0]$11079 - attribute \src "libresoc.v:179465.3-179497.6" + attribute \src "libresoc.v:179464.3-179496.6" wire width 64 $5\reg$next[63:0]$11111 - attribute \src "libresoc.v:179383.3-179428.6" + attribute \src "libresoc.v:179382.3-179427.6" wire width 64 $5\sv1__data_o$next[63:0]$11095 - attribute \src "libresoc.v:179347.3-179382.6" + attribute \src "libresoc.v:179346.3-179381.6" wire $5\wr_detect$4[0:0]$11088 - attribute \src "libresoc.v:179429.3-179464.6" + attribute \src "libresoc.v:179428.3-179463.6" wire $5\wr_detect$7[0:0]$11104 - attribute \src "libresoc.v:179265.3-179300.6" + attribute \src "libresoc.v:179264.3-179299.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:179219.3-179264.6" + attribute \src "libresoc.v:179218.3-179263.6" wire width 64 $6\cia1__data_o$next[63:0]$11070 - attribute \src "libresoc.v:179301.3-179346.6" + attribute \src "libresoc.v:179300.3-179345.6" wire width 64 $6\msr1__data_o$next[63:0]$11080 - attribute \src "libresoc.v:179383.3-179428.6" + attribute \src "libresoc.v:179382.3-179427.6" wire width 64 $6\sv1__data_o$next[63:0]$11096 - attribute \src "libresoc.v:179219.3-179264.6" + attribute \src "libresoc.v:179218.3-179263.6" wire width 64 $7\cia1__data_o$next[63:0]$11071 - attribute \src "libresoc.v:179301.3-179346.6" + attribute \src "libresoc.v:179300.3-179345.6" wire width 64 $7\msr1__data_o$next[63:0]$11081 - attribute \src "libresoc.v:179383.3-179428.6" + attribute \src "libresoc.v:179382.3-179427.6" wire width 64 $7\sv1__data_o$next[63:0]$11097 - attribute \src "libresoc.v:179208.17-179208.100" - wire $not$libresoc.v:179208$11056_Y + attribute \src "libresoc.v:179207.17-179207.100" + wire $not$libresoc.v:179207$11056_Y + attribute \src "libresoc.v:179208.17-179208.103" + wire $not$libresoc.v:179208$11057_Y attribute \src "libresoc.v:179209.17-179209.103" - wire $not$libresoc.v:179209$11057_Y - attribute \src "libresoc.v:179210.17-179210.103" - wire $not$libresoc.v:179210$11058_Y + wire $not$libresoc.v:179209$11058_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -368254,7 +365064,7 @@ module \reg_1$136 wire width 64 input 15 \d_wr11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr11__wen - attribute \src "libresoc.v:179150.7-179150.15" + attribute \src "libresoc.v:179149.7-179149.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr1__data_i @@ -368291,106 +365101,106 @@ module \reg_1$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179208$11056 + cell $not $not$libresoc.v:179207$11056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:179208$11056_Y + connect \Y $not$libresoc.v:179207$11056_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179209$11057 + cell $not $not$libresoc.v:179208$11057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:179209$11057_Y + connect \Y $not$libresoc.v:179208$11057_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179210$11058 + cell $not $not$libresoc.v:179209$11058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:179210$11058_Y + connect \Y $not$libresoc.v:179209$11058_Y end - attribute \src "libresoc.v:179150.7-179150.20" - process $proc$libresoc.v:179150$11112 + attribute \src "libresoc.v:179149.7-179149.20" + process $proc$libresoc.v:179149$11112 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179159.14-179159.49" - process $proc$libresoc.v:179159$11113 + attribute \src "libresoc.v:179158.14-179158.49" + process $proc$libresoc.v:179158$11113 assign { } { } assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia1__data_o $1\cia1__data_o[63:0] end - attribute \src "libresoc.v:179176.14-179176.49" - process $proc$libresoc.v:179176$11114 + attribute \src "libresoc.v:179175.14-179175.49" + process $proc$libresoc.v:179175$11114 assign { } { } assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr1__data_o $1\msr1__data_o[63:0] end - attribute \src "libresoc.v:179188.14-179188.42" - process $proc$libresoc.v:179188$11115 + attribute \src "libresoc.v:179187.14-179187.42" + process $proc$libresoc.v:179187$11115 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:179195.14-179195.48" - process $proc$libresoc.v:179195$11116 + attribute \src "libresoc.v:179194.14-179194.48" + process $proc$libresoc.v:179194$11116 assign { } { } assign $1\sv1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv1__data_o $1\sv1__data_o[63:0] end - attribute \src "libresoc.v:179211.3-179212.25" - process $proc$libresoc.v:179211$11059 + attribute \src "libresoc.v:179210.3-179211.25" + process $proc$libresoc.v:179210$11059 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:179213.3-179214.39" - process $proc$libresoc.v:179213$11060 + attribute \src "libresoc.v:179212.3-179213.39" + process $proc$libresoc.v:179212$11060 assign { } { } assign $0\sv1__data_o[63:0] \sv1__data_o$next sync posedge \coresync_clk update \sv1__data_o $0\sv1__data_o[63:0] end - attribute \src "libresoc.v:179215.3-179216.41" - process $proc$libresoc.v:179215$11061 + attribute \src "libresoc.v:179214.3-179215.41" + process $proc$libresoc.v:179214$11061 assign { } { } assign $0\msr1__data_o[63:0] \msr1__data_o$next sync posedge \coresync_clk update \msr1__data_o $0\msr1__data_o[63:0] end - attribute \src "libresoc.v:179217.3-179218.41" - process $proc$libresoc.v:179217$11062 + attribute \src "libresoc.v:179216.3-179217.41" + process $proc$libresoc.v:179216$11062 assign { } { } assign $0\cia1__data_o[63:0] \cia1__data_o$next sync posedge \coresync_clk update \cia1__data_o $0\cia1__data_o[63:0] end - attribute \src "libresoc.v:179219.3-179264.6" - process $proc$libresoc.v:179219$11063 + attribute \src "libresoc.v:179218.3-179263.6" + process $proc$libresoc.v:179218$11063 assign { } { } assign { } { } assign { } { } assign $0\cia1__data_o$next[63:0]$11064 $7\cia1__data_o$next[63:0]$11071 - attribute \src "libresoc.v:179220.5-179220.29" + attribute \src "libresoc.v:179219.5-179219.29" switch \initial - attribute \src "libresoc.v:179220.9-179220.17" + attribute \src "libresoc.v:179219.9-179219.17" case 1'1 case end @@ -368464,14 +365274,14 @@ module \reg_1$136 sync always update \cia1__data_o$next $0\cia1__data_o$next[63:0]$11064 end - attribute \src "libresoc.v:179265.3-179300.6" - process $proc$libresoc.v:179265$11072 + attribute \src "libresoc.v:179264.3-179299.6" + process $proc$libresoc.v:179264$11072 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:179266.5-179266.29" + attribute \src "libresoc.v:179265.5-179265.29" switch \initial - attribute \src "libresoc.v:179266.9-179266.17" + attribute \src "libresoc.v:179265.9-179265.17" case 1'1 case end @@ -368527,15 +365337,15 @@ module \reg_1$136 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:179301.3-179346.6" - process $proc$libresoc.v:179301$11073 + attribute \src "libresoc.v:179300.3-179345.6" + process $proc$libresoc.v:179300$11073 assign { } { } assign { } { } assign { } { } assign $0\msr1__data_o$next[63:0]$11074 $7\msr1__data_o$next[63:0]$11081 - attribute \src "libresoc.v:179302.5-179302.29" + attribute \src "libresoc.v:179301.5-179301.29" switch \initial - attribute \src "libresoc.v:179302.9-179302.17" + attribute \src "libresoc.v:179301.9-179301.17" case 1'1 case end @@ -368609,14 +365419,14 @@ module \reg_1$136 sync always update \msr1__data_o$next $0\msr1__data_o$next[63:0]$11074 end - attribute \src "libresoc.v:179347.3-179382.6" - process $proc$libresoc.v:179347$11082 + attribute \src "libresoc.v:179346.3-179381.6" + process $proc$libresoc.v:179346$11082 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11083 $1\wr_detect$4[0:0]$11084 - attribute \src "libresoc.v:179348.5-179348.29" + attribute \src "libresoc.v:179347.5-179347.29" switch \initial - attribute \src "libresoc.v:179348.9-179348.17" + attribute \src "libresoc.v:179347.9-179347.17" case 1'1 case end @@ -368672,15 +365482,15 @@ module \reg_1$136 sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11083 end - attribute \src "libresoc.v:179383.3-179428.6" - process $proc$libresoc.v:179383$11089 + attribute \src "libresoc.v:179382.3-179427.6" + process $proc$libresoc.v:179382$11089 assign { } { } assign { } { } assign { } { } assign $0\sv1__data_o$next[63:0]$11090 $7\sv1__data_o$next[63:0]$11097 - attribute \src "libresoc.v:179384.5-179384.29" + attribute \src "libresoc.v:179383.5-179383.29" switch \initial - attribute \src "libresoc.v:179384.9-179384.17" + attribute \src "libresoc.v:179383.9-179383.17" case 1'1 case end @@ -368754,14 +365564,14 @@ module \reg_1$136 sync always update \sv1__data_o$next $0\sv1__data_o$next[63:0]$11090 end - attribute \src "libresoc.v:179429.3-179464.6" - process $proc$libresoc.v:179429$11098 + attribute \src "libresoc.v:179428.3-179463.6" + process $proc$libresoc.v:179428$11098 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11099 $1\wr_detect$7[0:0]$11100 - attribute \src "libresoc.v:179430.5-179430.29" + attribute \src "libresoc.v:179429.5-179429.29" switch \initial - attribute \src "libresoc.v:179430.9-179430.17" + attribute \src "libresoc.v:179429.9-179429.17" case 1'1 case end @@ -368817,8 +365627,8 @@ module \reg_1$136 sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11099 end - attribute \src "libresoc.v:179465.3-179497.6" - process $proc$libresoc.v:179465$11105 + attribute \src "libresoc.v:179464.3-179496.6" + process $proc$libresoc.v:179464$11105 assign { } { } assign { } { } assign { } { } @@ -368826,9 +365636,9 @@ module \reg_1$136 assign { } { } assign { } { } assign $0\reg$next[63:0]$11106 $5\reg$next[63:0]$11111 - attribute \src "libresoc.v:179466.5-179466.29" + attribute \src "libresoc.v:179465.5-179465.29" switch \initial - attribute \src "libresoc.v:179466.9-179466.17" + attribute \src "libresoc.v:179465.9-179465.17" case 1'1 case end @@ -368880,211 +365690,211 @@ module \reg_1$136 sync always update \reg$next $0\reg$next[63:0]$11106 end - connect \$1 $not$libresoc.v:179208$11056_Y - connect \$3 $not$libresoc.v:179209$11057_Y - connect \$6 $not$libresoc.v:179210$11058_Y + connect \$1 $not$libresoc.v:179207$11056_Y + connect \$3 $not$libresoc.v:179208$11057_Y + connect \$6 $not$libresoc.v:179209$11058_Y end -attribute \src "libresoc.v:179502.1-180057.10" +attribute \src "libresoc.v:179501.1-180056.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_2" attribute \generator "nMigen" module \reg_2 - attribute \src "libresoc.v:179610.3-179649.6" + attribute \src "libresoc.v:179609.3-179648.6" wire width 4 $0\cr_pred2__data_o$next[3:0]$11131 - attribute \src "libresoc.v:179608.3-179609.49" + attribute \src "libresoc.v:179607.3-179608.49" wire width 4 $0\cr_pred2__data_o[3:0] - attribute \src "libresoc.v:179503.7-179503.20" + attribute \src "libresoc.v:179502.7-179502.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179680.3-179719.6" + attribute \src "libresoc.v:179679.3-179718.6" wire width 4 $0\r22__data_o$next[3:0]$11140 - attribute \src "libresoc.v:179598.3-179599.39" + attribute \src "libresoc.v:179597.3-179598.39" wire width 4 $0\r22__data_o[3:0] - attribute \src "libresoc.v:179987.3-180026.6" + attribute \src "libresoc.v:179986.3-180025.6" wire width 4 $0\r2__data_o$next[3:0]$11202 - attribute \src "libresoc.v:179600.3-179601.37" + attribute \src "libresoc.v:179599.3-179600.37" wire width 4 $0\r2__data_o[3:0] - attribute \src "libresoc.v:179750.3-179776.6" + attribute \src "libresoc.v:179749.3-179775.6" wire width 4 $0\reg$next[3:0]$11154 - attribute \src "libresoc.v:179596.3-179597.25" + attribute \src "libresoc.v:179595.3-179596.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:179777.3-179816.6" + attribute \src "libresoc.v:179776.3-179815.6" wire width 4 $0\src12__data_o$next[3:0]$11160 - attribute \src "libresoc.v:179606.3-179607.43" + attribute \src "libresoc.v:179605.3-179606.43" wire width 4 $0\src12__data_o[3:0] - attribute \src "libresoc.v:179847.3-179886.6" + attribute \src "libresoc.v:179846.3-179885.6" wire width 4 $0\src22__data_o$next[3:0]$11174 - attribute \src "libresoc.v:179604.3-179605.43" + attribute \src "libresoc.v:179603.3-179604.43" wire width 4 $0\src22__data_o[3:0] - attribute \src "libresoc.v:179917.3-179956.6" + attribute \src "libresoc.v:179916.3-179955.6" wire width 4 $0\src32__data_o$next[3:0]$11188 - attribute \src "libresoc.v:179602.3-179603.43" + attribute \src "libresoc.v:179601.3-179602.43" wire width 4 $0\src32__data_o[3:0] - attribute \src "libresoc.v:179957.3-179986.6" + attribute \src "libresoc.v:179956.3-179985.6" wire $0\wr_detect$10[0:0]$11196 - attribute \src "libresoc.v:180027.3-180056.6" + attribute \src "libresoc.v:180026.3-180055.6" wire $0\wr_detect$13[0:0]$11210 - attribute \src "libresoc.v:179720.3-179749.6" + attribute \src "libresoc.v:179719.3-179748.6" wire $0\wr_detect$16[0:0]$11148 - attribute \src "libresoc.v:179817.3-179846.6" + attribute \src "libresoc.v:179816.3-179845.6" wire $0\wr_detect$4[0:0]$11168 - attribute \src "libresoc.v:179887.3-179916.6" + attribute \src "libresoc.v:179886.3-179915.6" wire $0\wr_detect$7[0:0]$11182 - attribute \src "libresoc.v:179650.3-179679.6" + attribute \src "libresoc.v:179649.3-179678.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:179610.3-179649.6" + attribute \src "libresoc.v:179609.3-179648.6" wire width 4 $1\cr_pred2__data_o$next[3:0]$11132 - attribute \src "libresoc.v:179522.13-179522.36" + attribute \src "libresoc.v:179521.13-179521.36" wire width 4 $1\cr_pred2__data_o[3:0] - attribute \src "libresoc.v:179680.3-179719.6" + attribute \src "libresoc.v:179679.3-179718.6" wire width 4 $1\r22__data_o$next[3:0]$11141 - attribute \src "libresoc.v:179537.13-179537.31" + attribute \src "libresoc.v:179536.13-179536.31" wire width 4 $1\r22__data_o[3:0] - attribute \src "libresoc.v:179987.3-180026.6" + attribute \src "libresoc.v:179986.3-180025.6" wire width 4 $1\r2__data_o$next[3:0]$11203 - attribute \src "libresoc.v:179544.13-179544.30" + attribute \src "libresoc.v:179543.13-179543.30" wire width 4 $1\r2__data_o[3:0] - attribute \src "libresoc.v:179750.3-179776.6" + attribute \src "libresoc.v:179749.3-179775.6" wire width 4 $1\reg$next[3:0]$11155 - attribute \src "libresoc.v:179550.13-179550.25" + attribute \src "libresoc.v:179549.13-179549.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:179777.3-179816.6" + attribute \src "libresoc.v:179776.3-179815.6" wire width 4 $1\src12__data_o$next[3:0]$11161 - attribute \src "libresoc.v:179555.13-179555.33" + attribute \src "libresoc.v:179554.13-179554.33" wire width 4 $1\src12__data_o[3:0] - attribute \src "libresoc.v:179847.3-179886.6" + attribute \src "libresoc.v:179846.3-179885.6" wire width 4 $1\src22__data_o$next[3:0]$11175 - attribute \src "libresoc.v:179562.13-179562.33" + attribute \src "libresoc.v:179561.13-179561.33" wire width 4 $1\src22__data_o[3:0] - attribute \src "libresoc.v:179917.3-179956.6" + attribute \src "libresoc.v:179916.3-179955.6" wire width 4 $1\src32__data_o$next[3:0]$11189 - attribute \src "libresoc.v:179569.13-179569.33" + attribute \src "libresoc.v:179568.13-179568.33" wire width 4 $1\src32__data_o[3:0] - attribute \src "libresoc.v:179957.3-179986.6" + attribute \src "libresoc.v:179956.3-179985.6" wire $1\wr_detect$10[0:0]$11197 - attribute \src "libresoc.v:180027.3-180056.6" + attribute \src "libresoc.v:180026.3-180055.6" wire $1\wr_detect$13[0:0]$11211 - attribute \src "libresoc.v:179720.3-179749.6" + attribute \src "libresoc.v:179719.3-179748.6" wire $1\wr_detect$16[0:0]$11149 - attribute \src "libresoc.v:179817.3-179846.6" + attribute \src "libresoc.v:179816.3-179845.6" wire $1\wr_detect$4[0:0]$11169 - attribute \src "libresoc.v:179887.3-179916.6" + attribute \src "libresoc.v:179886.3-179915.6" wire $1\wr_detect$7[0:0]$11183 - attribute \src "libresoc.v:179650.3-179679.6" + attribute \src "libresoc.v:179649.3-179678.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:179610.3-179649.6" + attribute \src "libresoc.v:179609.3-179648.6" wire width 4 $2\cr_pred2__data_o$next[3:0]$11133 - attribute \src "libresoc.v:179680.3-179719.6" + attribute \src "libresoc.v:179679.3-179718.6" wire width 4 $2\r22__data_o$next[3:0]$11142 - attribute \src "libresoc.v:179987.3-180026.6" + attribute \src "libresoc.v:179986.3-180025.6" wire width 4 $2\r2__data_o$next[3:0]$11204 - attribute \src "libresoc.v:179750.3-179776.6" + attribute \src "libresoc.v:179749.3-179775.6" wire width 4 $2\reg$next[3:0]$11156 - attribute \src "libresoc.v:179777.3-179816.6" + attribute \src "libresoc.v:179776.3-179815.6" wire width 4 $2\src12__data_o$next[3:0]$11162 - attribute \src "libresoc.v:179847.3-179886.6" + attribute \src "libresoc.v:179846.3-179885.6" wire width 4 $2\src22__data_o$next[3:0]$11176 - attribute \src "libresoc.v:179917.3-179956.6" + attribute \src "libresoc.v:179916.3-179955.6" wire width 4 $2\src32__data_o$next[3:0]$11190 - attribute \src "libresoc.v:179957.3-179986.6" + attribute \src "libresoc.v:179956.3-179985.6" wire $2\wr_detect$10[0:0]$11198 - attribute \src "libresoc.v:180027.3-180056.6" + attribute \src "libresoc.v:180026.3-180055.6" wire $2\wr_detect$13[0:0]$11212 - attribute \src "libresoc.v:179720.3-179749.6" + attribute \src "libresoc.v:179719.3-179748.6" wire $2\wr_detect$16[0:0]$11150 - attribute \src "libresoc.v:179817.3-179846.6" + attribute \src "libresoc.v:179816.3-179845.6" wire $2\wr_detect$4[0:0]$11170 - attribute \src "libresoc.v:179887.3-179916.6" + attribute \src "libresoc.v:179886.3-179915.6" wire $2\wr_detect$7[0:0]$11184 - attribute \src "libresoc.v:179650.3-179679.6" + attribute \src "libresoc.v:179649.3-179678.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:179610.3-179649.6" + attribute \src "libresoc.v:179609.3-179648.6" wire width 4 $3\cr_pred2__data_o$next[3:0]$11134 - attribute \src "libresoc.v:179680.3-179719.6" + attribute \src "libresoc.v:179679.3-179718.6" wire width 4 $3\r22__data_o$next[3:0]$11143 - attribute \src "libresoc.v:179987.3-180026.6" + attribute \src "libresoc.v:179986.3-180025.6" wire width 4 $3\r2__data_o$next[3:0]$11205 - attribute \src "libresoc.v:179750.3-179776.6" + attribute \src "libresoc.v:179749.3-179775.6" wire width 4 $3\reg$next[3:0]$11157 - attribute \src "libresoc.v:179777.3-179816.6" + attribute \src "libresoc.v:179776.3-179815.6" wire width 4 $3\src12__data_o$next[3:0]$11163 - attribute \src "libresoc.v:179847.3-179886.6" + attribute \src "libresoc.v:179846.3-179885.6" wire width 4 $3\src22__data_o$next[3:0]$11177 - attribute \src "libresoc.v:179917.3-179956.6" + attribute \src "libresoc.v:179916.3-179955.6" wire width 4 $3\src32__data_o$next[3:0]$11191 - attribute \src "libresoc.v:179957.3-179986.6" + attribute \src "libresoc.v:179956.3-179985.6" wire $3\wr_detect$10[0:0]$11199 - attribute \src "libresoc.v:180027.3-180056.6" + attribute \src "libresoc.v:180026.3-180055.6" wire $3\wr_detect$13[0:0]$11213 - attribute \src "libresoc.v:179720.3-179749.6" + attribute \src "libresoc.v:179719.3-179748.6" wire $3\wr_detect$16[0:0]$11151 - attribute \src "libresoc.v:179817.3-179846.6" + attribute \src "libresoc.v:179816.3-179845.6" wire $3\wr_detect$4[0:0]$11171 - attribute \src "libresoc.v:179887.3-179916.6" + attribute \src "libresoc.v:179886.3-179915.6" wire $3\wr_detect$7[0:0]$11185 - attribute \src "libresoc.v:179650.3-179679.6" + attribute \src "libresoc.v:179649.3-179678.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:179610.3-179649.6" + attribute \src "libresoc.v:179609.3-179648.6" wire width 4 $4\cr_pred2__data_o$next[3:0]$11135 - attribute \src "libresoc.v:179680.3-179719.6" + attribute \src "libresoc.v:179679.3-179718.6" wire width 4 $4\r22__data_o$next[3:0]$11144 - attribute \src "libresoc.v:179987.3-180026.6" + attribute \src "libresoc.v:179986.3-180025.6" wire width 4 $4\r2__data_o$next[3:0]$11206 - attribute \src "libresoc.v:179750.3-179776.6" + attribute \src "libresoc.v:179749.3-179775.6" wire width 4 $4\reg$next[3:0]$11158 - attribute \src "libresoc.v:179777.3-179816.6" + attribute \src "libresoc.v:179776.3-179815.6" wire width 4 $4\src12__data_o$next[3:0]$11164 - attribute \src "libresoc.v:179847.3-179886.6" + attribute \src "libresoc.v:179846.3-179885.6" wire width 4 $4\src22__data_o$next[3:0]$11178 - attribute \src "libresoc.v:179917.3-179956.6" + attribute \src "libresoc.v:179916.3-179955.6" wire width 4 $4\src32__data_o$next[3:0]$11192 - attribute \src "libresoc.v:179957.3-179986.6" + attribute \src "libresoc.v:179956.3-179985.6" wire $4\wr_detect$10[0:0]$11200 - attribute \src "libresoc.v:180027.3-180056.6" + attribute \src "libresoc.v:180026.3-180055.6" wire $4\wr_detect$13[0:0]$11214 - attribute \src "libresoc.v:179720.3-179749.6" + attribute \src "libresoc.v:179719.3-179748.6" wire $4\wr_detect$16[0:0]$11152 - attribute \src "libresoc.v:179817.3-179846.6" + attribute \src "libresoc.v:179816.3-179845.6" wire $4\wr_detect$4[0:0]$11172 - attribute \src "libresoc.v:179887.3-179916.6" + attribute \src "libresoc.v:179886.3-179915.6" wire $4\wr_detect$7[0:0]$11186 - attribute \src "libresoc.v:179650.3-179679.6" + attribute \src "libresoc.v:179649.3-179678.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:179610.3-179649.6" + attribute \src "libresoc.v:179609.3-179648.6" wire width 4 $5\cr_pred2__data_o$next[3:0]$11136 - attribute \src "libresoc.v:179680.3-179719.6" + attribute \src "libresoc.v:179679.3-179718.6" wire width 4 $5\r22__data_o$next[3:0]$11145 - attribute \src "libresoc.v:179987.3-180026.6" + attribute \src "libresoc.v:179986.3-180025.6" wire width 4 $5\r2__data_o$next[3:0]$11207 - attribute \src "libresoc.v:179777.3-179816.6" + attribute \src "libresoc.v:179776.3-179815.6" wire width 4 $5\src12__data_o$next[3:0]$11165 - attribute \src "libresoc.v:179847.3-179886.6" + attribute \src "libresoc.v:179846.3-179885.6" wire width 4 $5\src22__data_o$next[3:0]$11179 - attribute \src "libresoc.v:179917.3-179956.6" + attribute \src "libresoc.v:179916.3-179955.6" wire width 4 $5\src32__data_o$next[3:0]$11193 - attribute \src "libresoc.v:179610.3-179649.6" + attribute \src "libresoc.v:179609.3-179648.6" wire width 4 $6\cr_pred2__data_o$next[3:0]$11137 - attribute \src "libresoc.v:179680.3-179719.6" + attribute \src "libresoc.v:179679.3-179718.6" wire width 4 $6\r22__data_o$next[3:0]$11146 - attribute \src "libresoc.v:179987.3-180026.6" + attribute \src "libresoc.v:179986.3-180025.6" wire width 4 $6\r2__data_o$next[3:0]$11208 - attribute \src "libresoc.v:179777.3-179816.6" + attribute \src "libresoc.v:179776.3-179815.6" wire width 4 $6\src12__data_o$next[3:0]$11166 - attribute \src "libresoc.v:179847.3-179886.6" + attribute \src "libresoc.v:179846.3-179885.6" wire width 4 $6\src22__data_o$next[3:0]$11180 - attribute \src "libresoc.v:179917.3-179956.6" + attribute \src "libresoc.v:179916.3-179955.6" wire width 4 $6\src32__data_o$next[3:0]$11194 - attribute \src "libresoc.v:179590.17-179590.104" - wire $not$libresoc.v:179590$11117_Y + attribute \src "libresoc.v:179589.17-179589.104" + wire $not$libresoc.v:179589$11117_Y + attribute \src "libresoc.v:179590.18-179590.105" + wire $not$libresoc.v:179590$11118_Y attribute \src "libresoc.v:179591.18-179591.105" - wire $not$libresoc.v:179591$11118_Y - attribute \src "libresoc.v:179592.18-179592.105" - wire $not$libresoc.v:179592$11119_Y - attribute \src "libresoc.v:179593.17-179593.100" - wire $not$libresoc.v:179593$11120_Y + wire $not$libresoc.v:179591$11119_Y + attribute \src "libresoc.v:179592.17-179592.100" + wire $not$libresoc.v:179592$11120_Y + attribute \src "libresoc.v:179593.17-179593.103" + wire $not$libresoc.v:179593$11121_Y attribute \src "libresoc.v:179594.17-179594.103" - wire $not$libresoc.v:179594$11121_Y - attribute \src "libresoc.v:179595.17-179595.103" - wire $not$libresoc.v:179595$11122_Y + wire $not$libresoc.v:179594$11122_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -369115,7 +365925,7 @@ module \reg_2 wire width 4 input 13 \dest22__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest22__wen - attribute \src "libresoc.v:179503.7-179503.15" + attribute \src "libresoc.v:179502.7-179502.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 16 \r22__data_o @@ -369168,175 +365978,175 @@ module \reg_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179590$11117 + cell $not $not$libresoc.v:179589$11117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:179590$11117_Y + connect \Y $not$libresoc.v:179589$11117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179591$11118 + cell $not $not$libresoc.v:179590$11118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:179591$11118_Y + connect \Y $not$libresoc.v:179590$11118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179592$11119 + cell $not $not$libresoc.v:179591$11119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$16 - connect \Y $not$libresoc.v:179592$11119_Y + connect \Y $not$libresoc.v:179591$11119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179593$11120 + cell $not $not$libresoc.v:179592$11120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:179593$11120_Y + connect \Y $not$libresoc.v:179592$11120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179594$11121 + cell $not $not$libresoc.v:179593$11121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:179594$11121_Y + connect \Y $not$libresoc.v:179593$11121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179595$11122 + cell $not $not$libresoc.v:179594$11122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:179595$11122_Y + connect \Y $not$libresoc.v:179594$11122_Y end - attribute \src "libresoc.v:179503.7-179503.20" - process $proc$libresoc.v:179503$11215 + attribute \src "libresoc.v:179502.7-179502.20" + process $proc$libresoc.v:179502$11215 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179522.13-179522.36" - process $proc$libresoc.v:179522$11216 + attribute \src "libresoc.v:179521.13-179521.36" + process $proc$libresoc.v:179521$11216 assign { } { } assign $1\cr_pred2__data_o[3:0] 4'0000 sync always sync init update \cr_pred2__data_o $1\cr_pred2__data_o[3:0] end - attribute \src "libresoc.v:179537.13-179537.31" - process $proc$libresoc.v:179537$11217 + attribute \src "libresoc.v:179536.13-179536.31" + process $proc$libresoc.v:179536$11217 assign { } { } assign $1\r22__data_o[3:0] 4'0000 sync always sync init update \r22__data_o $1\r22__data_o[3:0] end - attribute \src "libresoc.v:179544.13-179544.30" - process $proc$libresoc.v:179544$11218 + attribute \src "libresoc.v:179543.13-179543.30" + process $proc$libresoc.v:179543$11218 assign { } { } assign $1\r2__data_o[3:0] 4'0000 sync always sync init update \r2__data_o $1\r2__data_o[3:0] end - attribute \src "libresoc.v:179550.13-179550.25" - process $proc$libresoc.v:179550$11219 + attribute \src "libresoc.v:179549.13-179549.25" + process $proc$libresoc.v:179549$11219 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:179555.13-179555.33" - process $proc$libresoc.v:179555$11220 + attribute \src "libresoc.v:179554.13-179554.33" + process $proc$libresoc.v:179554$11220 assign { } { } assign $1\src12__data_o[3:0] 4'0000 sync always sync init update \src12__data_o $1\src12__data_o[3:0] end - attribute \src "libresoc.v:179562.13-179562.33" - process $proc$libresoc.v:179562$11221 + attribute \src "libresoc.v:179561.13-179561.33" + process $proc$libresoc.v:179561$11221 assign { } { } assign $1\src22__data_o[3:0] 4'0000 sync always sync init update \src22__data_o $1\src22__data_o[3:0] end - attribute \src "libresoc.v:179569.13-179569.33" - process $proc$libresoc.v:179569$11222 + attribute \src "libresoc.v:179568.13-179568.33" + process $proc$libresoc.v:179568$11222 assign { } { } assign $1\src32__data_o[3:0] 4'0000 sync always sync init update \src32__data_o $1\src32__data_o[3:0] end - attribute \src "libresoc.v:179596.3-179597.25" - process $proc$libresoc.v:179596$11123 + attribute \src "libresoc.v:179595.3-179596.25" + process $proc$libresoc.v:179595$11123 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:179598.3-179599.39" - process $proc$libresoc.v:179598$11124 + attribute \src "libresoc.v:179597.3-179598.39" + process $proc$libresoc.v:179597$11124 assign { } { } assign $0\r22__data_o[3:0] \r22__data_o$next sync posedge \coresync_clk update \r22__data_o $0\r22__data_o[3:0] end - attribute \src "libresoc.v:179600.3-179601.37" - process $proc$libresoc.v:179600$11125 + attribute \src "libresoc.v:179599.3-179600.37" + process $proc$libresoc.v:179599$11125 assign { } { } assign $0\r2__data_o[3:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[3:0] end - attribute \src "libresoc.v:179602.3-179603.43" - process $proc$libresoc.v:179602$11126 + attribute \src "libresoc.v:179601.3-179602.43" + process $proc$libresoc.v:179601$11126 assign { } { } assign $0\src32__data_o[3:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[3:0] end - attribute \src "libresoc.v:179604.3-179605.43" - process $proc$libresoc.v:179604$11127 + attribute \src "libresoc.v:179603.3-179604.43" + process $proc$libresoc.v:179603$11127 assign { } { } assign $0\src22__data_o[3:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[3:0] end - attribute \src "libresoc.v:179606.3-179607.43" - process $proc$libresoc.v:179606$11128 + attribute \src "libresoc.v:179605.3-179606.43" + process $proc$libresoc.v:179605$11128 assign { } { } assign $0\src12__data_o[3:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[3:0] end - attribute \src "libresoc.v:179608.3-179609.49" - process $proc$libresoc.v:179608$11129 + attribute \src "libresoc.v:179607.3-179608.49" + process $proc$libresoc.v:179607$11129 assign { } { } assign $0\cr_pred2__data_o[3:0] \cr_pred2__data_o$next sync posedge \coresync_clk update \cr_pred2__data_o $0\cr_pred2__data_o[3:0] end - attribute \src "libresoc.v:179610.3-179649.6" - process $proc$libresoc.v:179610$11130 + attribute \src "libresoc.v:179609.3-179648.6" + process $proc$libresoc.v:179609$11130 assign { } { } assign { } { } assign { } { } assign $0\cr_pred2__data_o$next[3:0]$11131 $6\cr_pred2__data_o$next[3:0]$11137 - attribute \src "libresoc.v:179611.5-179611.29" + attribute \src "libresoc.v:179610.5-179610.29" switch \initial - attribute \src "libresoc.v:179611.9-179611.17" + attribute \src "libresoc.v:179610.9-179610.17" case 1'1 case end @@ -369400,14 +366210,14 @@ module \reg_2 sync always update \cr_pred2__data_o$next $0\cr_pred2__data_o$next[3:0]$11131 end - attribute \src "libresoc.v:179650.3-179679.6" - process $proc$libresoc.v:179650$11138 + attribute \src "libresoc.v:179649.3-179678.6" + process $proc$libresoc.v:179649$11138 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:179651.5-179651.29" + attribute \src "libresoc.v:179650.5-179650.29" switch \initial - attribute \src "libresoc.v:179651.9-179651.17" + attribute \src "libresoc.v:179650.9-179650.17" case 1'1 case end @@ -369453,15 +366263,15 @@ module \reg_2 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:179680.3-179719.6" - process $proc$libresoc.v:179680$11139 + attribute \src "libresoc.v:179679.3-179718.6" + process $proc$libresoc.v:179679$11139 assign { } { } assign { } { } assign { } { } assign $0\r22__data_o$next[3:0]$11140 $6\r22__data_o$next[3:0]$11146 - attribute \src "libresoc.v:179681.5-179681.29" + attribute \src "libresoc.v:179680.5-179680.29" switch \initial - attribute \src "libresoc.v:179681.9-179681.17" + attribute \src "libresoc.v:179680.9-179680.17" case 1'1 case end @@ -369525,14 +366335,14 @@ module \reg_2 sync always update \r22__data_o$next $0\r22__data_o$next[3:0]$11140 end - attribute \src "libresoc.v:179720.3-179749.6" - process $proc$libresoc.v:179720$11147 + attribute \src "libresoc.v:179719.3-179748.6" + process $proc$libresoc.v:179719$11147 assign { } { } assign { } { } assign $0\wr_detect$16[0:0]$11148 $1\wr_detect$16[0:0]$11149 - attribute \src "libresoc.v:179721.5-179721.29" + attribute \src "libresoc.v:179720.5-179720.29" switch \initial - attribute \src "libresoc.v:179721.9-179721.17" + attribute \src "libresoc.v:179720.9-179720.17" case 1'1 case end @@ -369578,17 +366388,17 @@ module \reg_2 sync always update \wr_detect$16 $0\wr_detect$16[0:0]$11148 end - attribute \src "libresoc.v:179750.3-179776.6" - process $proc$libresoc.v:179750$11153 + attribute \src "libresoc.v:179749.3-179775.6" + process $proc$libresoc.v:179749$11153 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[3:0]$11154 $4\reg$next[3:0]$11158 - attribute \src "libresoc.v:179751.5-179751.29" + attribute \src "libresoc.v:179750.5-179750.29" switch \initial - attribute \src "libresoc.v:179751.9-179751.17" + attribute \src "libresoc.v:179750.9-179750.17" case 1'1 case end @@ -369631,15 +366441,15 @@ module \reg_2 sync always update \reg$next $0\reg$next[3:0]$11154 end - attribute \src "libresoc.v:179777.3-179816.6" - process $proc$libresoc.v:179777$11159 + attribute \src "libresoc.v:179776.3-179815.6" + process $proc$libresoc.v:179776$11159 assign { } { } assign { } { } assign { } { } assign $0\src12__data_o$next[3:0]$11160 $6\src12__data_o$next[3:0]$11166 - attribute \src "libresoc.v:179778.5-179778.29" + attribute \src "libresoc.v:179777.5-179777.29" switch \initial - attribute \src "libresoc.v:179778.9-179778.17" + attribute \src "libresoc.v:179777.9-179777.17" case 1'1 case end @@ -369703,14 +366513,14 @@ module \reg_2 sync always update \src12__data_o$next $0\src12__data_o$next[3:0]$11160 end - attribute \src "libresoc.v:179817.3-179846.6" - process $proc$libresoc.v:179817$11167 + attribute \src "libresoc.v:179816.3-179845.6" + process $proc$libresoc.v:179816$11167 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11168 $1\wr_detect$4[0:0]$11169 - attribute \src "libresoc.v:179818.5-179818.29" + attribute \src "libresoc.v:179817.5-179817.29" switch \initial - attribute \src "libresoc.v:179818.9-179818.17" + attribute \src "libresoc.v:179817.9-179817.17" case 1'1 case end @@ -369756,15 +366566,15 @@ module \reg_2 sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11168 end - attribute \src "libresoc.v:179847.3-179886.6" - process $proc$libresoc.v:179847$11173 + attribute \src "libresoc.v:179846.3-179885.6" + process $proc$libresoc.v:179846$11173 assign { } { } assign { } { } assign { } { } assign $0\src22__data_o$next[3:0]$11174 $6\src22__data_o$next[3:0]$11180 - attribute \src "libresoc.v:179848.5-179848.29" + attribute \src "libresoc.v:179847.5-179847.29" switch \initial - attribute \src "libresoc.v:179848.9-179848.17" + attribute \src "libresoc.v:179847.9-179847.17" case 1'1 case end @@ -369828,14 +366638,14 @@ module \reg_2 sync always update \src22__data_o$next $0\src22__data_o$next[3:0]$11174 end - attribute \src "libresoc.v:179887.3-179916.6" - process $proc$libresoc.v:179887$11181 + attribute \src "libresoc.v:179886.3-179915.6" + process $proc$libresoc.v:179886$11181 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11182 $1\wr_detect$7[0:0]$11183 - attribute \src "libresoc.v:179888.5-179888.29" + attribute \src "libresoc.v:179887.5-179887.29" switch \initial - attribute \src "libresoc.v:179888.9-179888.17" + attribute \src "libresoc.v:179887.9-179887.17" case 1'1 case end @@ -369881,15 +366691,15 @@ module \reg_2 sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11182 end - attribute \src "libresoc.v:179917.3-179956.6" - process $proc$libresoc.v:179917$11187 + attribute \src "libresoc.v:179916.3-179955.6" + process $proc$libresoc.v:179916$11187 assign { } { } assign { } { } assign { } { } assign $0\src32__data_o$next[3:0]$11188 $6\src32__data_o$next[3:0]$11194 - attribute \src "libresoc.v:179918.5-179918.29" + attribute \src "libresoc.v:179917.5-179917.29" switch \initial - attribute \src "libresoc.v:179918.9-179918.17" + attribute \src "libresoc.v:179917.9-179917.17" case 1'1 case end @@ -369953,14 +366763,14 @@ module \reg_2 sync always update \src32__data_o$next $0\src32__data_o$next[3:0]$11188 end - attribute \src "libresoc.v:179957.3-179986.6" - process $proc$libresoc.v:179957$11195 + attribute \src "libresoc.v:179956.3-179985.6" + process $proc$libresoc.v:179956$11195 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$11196 $1\wr_detect$10[0:0]$11197 - attribute \src "libresoc.v:179958.5-179958.29" + attribute \src "libresoc.v:179957.5-179957.29" switch \initial - attribute \src "libresoc.v:179958.9-179958.17" + attribute \src "libresoc.v:179957.9-179957.17" case 1'1 case end @@ -370006,15 +366816,15 @@ module \reg_2 sync always update \wr_detect$10 $0\wr_detect$10[0:0]$11196 end - attribute \src "libresoc.v:179987.3-180026.6" - process $proc$libresoc.v:179987$11201 + attribute \src "libresoc.v:179986.3-180025.6" + process $proc$libresoc.v:179986$11201 assign { } { } assign { } { } assign { } { } assign $0\r2__data_o$next[3:0]$11202 $6\r2__data_o$next[3:0]$11208 - attribute \src "libresoc.v:179988.5-179988.29" + attribute \src "libresoc.v:179987.5-179987.29" switch \initial - attribute \src "libresoc.v:179988.9-179988.17" + attribute \src "libresoc.v:179987.9-179987.17" case 1'1 case end @@ -370078,14 +366888,14 @@ module \reg_2 sync always update \r2__data_o$next $0\r2__data_o$next[3:0]$11202 end - attribute \src "libresoc.v:180027.3-180056.6" - process $proc$libresoc.v:180027$11209 + attribute \src "libresoc.v:180026.3-180055.6" + process $proc$libresoc.v:180026$11209 assign { } { } assign { } { } assign $0\wr_detect$13[0:0]$11210 $1\wr_detect$13[0:0]$11211 - attribute \src "libresoc.v:180028.5-180028.29" + attribute \src "libresoc.v:180027.5-180027.29" switch \initial - attribute \src "libresoc.v:180028.9-180028.17" + attribute \src "libresoc.v:180027.9-180027.17" case 1'1 case end @@ -370131,172 +366941,172 @@ module \reg_2 sync always update \wr_detect$13 $0\wr_detect$13[0:0]$11210 end - connect \$9 $not$libresoc.v:179590$11117_Y - connect \$12 $not$libresoc.v:179591$11118_Y - connect \$15 $not$libresoc.v:179592$11119_Y - connect \$1 $not$libresoc.v:179593$11120_Y - connect \$3 $not$libresoc.v:179594$11121_Y - connect \$6 $not$libresoc.v:179595$11122_Y + connect \$9 $not$libresoc.v:179589$11117_Y + connect \$12 $not$libresoc.v:179590$11118_Y + connect \$15 $not$libresoc.v:179591$11119_Y + connect \$1 $not$libresoc.v:179592$11120_Y + connect \$3 $not$libresoc.v:179593$11121_Y + connect \$6 $not$libresoc.v:179594$11122_Y end -attribute \src "libresoc.v:180061.1-180506.10" +attribute \src "libresoc.v:180060.1-180505.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_2" attribute \generator "nMigen" module \reg_2$134 - attribute \src "libresoc.v:180062.7-180062.20" + attribute \src "libresoc.v:180061.7-180061.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180391.3-180436.6" + attribute \src "libresoc.v:180390.3-180435.6" wire width 2 $0\r2__data_o$next[1:0]$11275 - attribute \src "libresoc.v:180137.3-180138.37" + attribute \src "libresoc.v:180136.3-180137.37" wire width 2 $0\r2__data_o[1:0] - attribute \src "libresoc.v:180473.3-180505.6" + attribute \src "libresoc.v:180472.3-180504.6" wire width 2 $0\reg$next[1:0]$11291 - attribute \src "libresoc.v:180135.3-180136.25" + attribute \src "libresoc.v:180134.3-180135.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:180145.3-180190.6" + attribute \src "libresoc.v:180144.3-180189.6" wire width 2 $0\src12__data_o$next[1:0]$11233 - attribute \src "libresoc.v:180143.3-180144.43" + attribute \src "libresoc.v:180142.3-180143.43" wire width 2 $0\src12__data_o[1:0] - attribute \src "libresoc.v:180227.3-180272.6" + attribute \src "libresoc.v:180226.3-180271.6" wire width 2 $0\src22__data_o$next[1:0]$11243 - attribute \src "libresoc.v:180141.3-180142.43" + attribute \src "libresoc.v:180140.3-180141.43" wire width 2 $0\src22__data_o[1:0] - attribute \src "libresoc.v:180309.3-180354.6" + attribute \src "libresoc.v:180308.3-180353.6" wire width 2 $0\src32__data_o$next[1:0]$11259 - attribute \src "libresoc.v:180139.3-180140.43" + attribute \src "libresoc.v:180138.3-180139.43" wire width 2 $0\src32__data_o[1:0] - attribute \src "libresoc.v:180437.3-180472.6" + attribute \src "libresoc.v:180436.3-180471.6" wire $0\wr_detect$10[0:0]$11284 - attribute \src "libresoc.v:180273.3-180308.6" + attribute \src "libresoc.v:180272.3-180307.6" wire $0\wr_detect$4[0:0]$11252 - attribute \src "libresoc.v:180355.3-180390.6" + attribute \src "libresoc.v:180354.3-180389.6" wire $0\wr_detect$7[0:0]$11268 - attribute \src "libresoc.v:180191.3-180226.6" + attribute \src "libresoc.v:180190.3-180225.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:180391.3-180436.6" + attribute \src "libresoc.v:180390.3-180435.6" wire width 2 $1\r2__data_o$next[1:0]$11276 - attribute \src "libresoc.v:180089.13-180089.30" + attribute \src "libresoc.v:180088.13-180088.30" wire width 2 $1\r2__data_o[1:0] - attribute \src "libresoc.v:180473.3-180505.6" + attribute \src "libresoc.v:180472.3-180504.6" wire width 2 $1\reg$next[1:0]$11292 - attribute \src "libresoc.v:180095.13-180095.25" + attribute \src "libresoc.v:180094.13-180094.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:180145.3-180190.6" + attribute \src "libresoc.v:180144.3-180189.6" wire width 2 $1\src12__data_o$next[1:0]$11234 - attribute \src "libresoc.v:180100.13-180100.33" + attribute \src "libresoc.v:180099.13-180099.33" wire width 2 $1\src12__data_o[1:0] - attribute \src "libresoc.v:180227.3-180272.6" + attribute \src "libresoc.v:180226.3-180271.6" wire width 2 $1\src22__data_o$next[1:0]$11244 - attribute \src "libresoc.v:180107.13-180107.33" + attribute \src "libresoc.v:180106.13-180106.33" wire width 2 $1\src22__data_o[1:0] - attribute \src "libresoc.v:180309.3-180354.6" + attribute \src "libresoc.v:180308.3-180353.6" wire width 2 $1\src32__data_o$next[1:0]$11260 - attribute \src "libresoc.v:180114.13-180114.33" + attribute \src "libresoc.v:180113.13-180113.33" wire width 2 $1\src32__data_o[1:0] - attribute \src "libresoc.v:180437.3-180472.6" + attribute \src "libresoc.v:180436.3-180471.6" wire $1\wr_detect$10[0:0]$11285 - attribute \src "libresoc.v:180273.3-180308.6" + attribute \src "libresoc.v:180272.3-180307.6" wire $1\wr_detect$4[0:0]$11253 - attribute \src "libresoc.v:180355.3-180390.6" + attribute \src "libresoc.v:180354.3-180389.6" wire $1\wr_detect$7[0:0]$11269 - attribute \src "libresoc.v:180191.3-180226.6" + attribute \src "libresoc.v:180190.3-180225.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:180391.3-180436.6" + attribute \src "libresoc.v:180390.3-180435.6" wire width 2 $2\r2__data_o$next[1:0]$11277 - attribute \src "libresoc.v:180473.3-180505.6" + attribute \src "libresoc.v:180472.3-180504.6" wire width 2 $2\reg$next[1:0]$11293 - attribute \src "libresoc.v:180145.3-180190.6" + attribute \src "libresoc.v:180144.3-180189.6" wire width 2 $2\src12__data_o$next[1:0]$11235 - attribute \src "libresoc.v:180227.3-180272.6" + attribute \src "libresoc.v:180226.3-180271.6" wire width 2 $2\src22__data_o$next[1:0]$11245 - attribute \src "libresoc.v:180309.3-180354.6" + attribute \src "libresoc.v:180308.3-180353.6" wire width 2 $2\src32__data_o$next[1:0]$11261 - attribute \src "libresoc.v:180437.3-180472.6" + attribute \src "libresoc.v:180436.3-180471.6" wire $2\wr_detect$10[0:0]$11286 - attribute \src "libresoc.v:180273.3-180308.6" + attribute \src "libresoc.v:180272.3-180307.6" wire $2\wr_detect$4[0:0]$11254 - attribute \src "libresoc.v:180355.3-180390.6" + attribute \src "libresoc.v:180354.3-180389.6" wire $2\wr_detect$7[0:0]$11270 - attribute \src "libresoc.v:180191.3-180226.6" + attribute \src "libresoc.v:180190.3-180225.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:180391.3-180436.6" + attribute \src "libresoc.v:180390.3-180435.6" wire width 2 $3\r2__data_o$next[1:0]$11278 - attribute \src "libresoc.v:180473.3-180505.6" + attribute \src "libresoc.v:180472.3-180504.6" wire width 2 $3\reg$next[1:0]$11294 - attribute \src "libresoc.v:180145.3-180190.6" + attribute \src "libresoc.v:180144.3-180189.6" wire width 2 $3\src12__data_o$next[1:0]$11236 - attribute \src "libresoc.v:180227.3-180272.6" + attribute \src "libresoc.v:180226.3-180271.6" wire width 2 $3\src22__data_o$next[1:0]$11246 - attribute \src "libresoc.v:180309.3-180354.6" + attribute \src "libresoc.v:180308.3-180353.6" wire width 2 $3\src32__data_o$next[1:0]$11262 - attribute \src "libresoc.v:180437.3-180472.6" + attribute \src "libresoc.v:180436.3-180471.6" wire $3\wr_detect$10[0:0]$11287 - attribute \src "libresoc.v:180273.3-180308.6" + attribute \src "libresoc.v:180272.3-180307.6" wire $3\wr_detect$4[0:0]$11255 - attribute \src "libresoc.v:180355.3-180390.6" + attribute \src "libresoc.v:180354.3-180389.6" wire $3\wr_detect$7[0:0]$11271 - attribute \src "libresoc.v:180191.3-180226.6" + attribute \src "libresoc.v:180190.3-180225.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:180391.3-180436.6" + attribute \src "libresoc.v:180390.3-180435.6" wire width 2 $4\r2__data_o$next[1:0]$11279 - attribute \src "libresoc.v:180473.3-180505.6" + attribute \src "libresoc.v:180472.3-180504.6" wire width 2 $4\reg$next[1:0]$11295 - attribute \src "libresoc.v:180145.3-180190.6" + attribute \src "libresoc.v:180144.3-180189.6" wire width 2 $4\src12__data_o$next[1:0]$11237 - attribute \src "libresoc.v:180227.3-180272.6" + attribute \src "libresoc.v:180226.3-180271.6" wire width 2 $4\src22__data_o$next[1:0]$11247 - attribute \src "libresoc.v:180309.3-180354.6" + attribute \src "libresoc.v:180308.3-180353.6" wire width 2 $4\src32__data_o$next[1:0]$11263 - attribute \src "libresoc.v:180437.3-180472.6" + attribute \src "libresoc.v:180436.3-180471.6" wire $4\wr_detect$10[0:0]$11288 - attribute \src "libresoc.v:180273.3-180308.6" + attribute \src "libresoc.v:180272.3-180307.6" wire $4\wr_detect$4[0:0]$11256 - attribute \src "libresoc.v:180355.3-180390.6" + attribute \src "libresoc.v:180354.3-180389.6" wire $4\wr_detect$7[0:0]$11272 - attribute \src "libresoc.v:180191.3-180226.6" + attribute \src "libresoc.v:180190.3-180225.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:180391.3-180436.6" + attribute \src "libresoc.v:180390.3-180435.6" wire width 2 $5\r2__data_o$next[1:0]$11280 - attribute \src "libresoc.v:180473.3-180505.6" + attribute \src "libresoc.v:180472.3-180504.6" wire width 2 $5\reg$next[1:0]$11296 - attribute \src "libresoc.v:180145.3-180190.6" + attribute \src "libresoc.v:180144.3-180189.6" wire width 2 $5\src12__data_o$next[1:0]$11238 - attribute \src "libresoc.v:180227.3-180272.6" + attribute \src "libresoc.v:180226.3-180271.6" wire width 2 $5\src22__data_o$next[1:0]$11248 - attribute \src "libresoc.v:180309.3-180354.6" + attribute \src "libresoc.v:180308.3-180353.6" wire width 2 $5\src32__data_o$next[1:0]$11264 - attribute \src "libresoc.v:180437.3-180472.6" + attribute \src "libresoc.v:180436.3-180471.6" wire $5\wr_detect$10[0:0]$11289 - attribute \src "libresoc.v:180273.3-180308.6" + attribute \src "libresoc.v:180272.3-180307.6" wire $5\wr_detect$4[0:0]$11257 - attribute \src "libresoc.v:180355.3-180390.6" + attribute \src "libresoc.v:180354.3-180389.6" wire $5\wr_detect$7[0:0]$11273 - attribute \src "libresoc.v:180191.3-180226.6" + attribute \src "libresoc.v:180190.3-180225.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:180391.3-180436.6" + attribute \src "libresoc.v:180390.3-180435.6" wire width 2 $6\r2__data_o$next[1:0]$11281 - attribute \src "libresoc.v:180145.3-180190.6" + attribute \src "libresoc.v:180144.3-180189.6" wire width 2 $6\src12__data_o$next[1:0]$11239 - attribute \src "libresoc.v:180227.3-180272.6" + attribute \src "libresoc.v:180226.3-180271.6" wire width 2 $6\src22__data_o$next[1:0]$11249 - attribute \src "libresoc.v:180309.3-180354.6" + attribute \src "libresoc.v:180308.3-180353.6" wire width 2 $6\src32__data_o$next[1:0]$11265 - attribute \src "libresoc.v:180391.3-180436.6" + attribute \src "libresoc.v:180390.3-180435.6" wire width 2 $7\r2__data_o$next[1:0]$11282 - attribute \src "libresoc.v:180145.3-180190.6" + attribute \src "libresoc.v:180144.3-180189.6" wire width 2 $7\src12__data_o$next[1:0]$11240 - attribute \src "libresoc.v:180227.3-180272.6" + attribute \src "libresoc.v:180226.3-180271.6" wire width 2 $7\src22__data_o$next[1:0]$11250 - attribute \src "libresoc.v:180309.3-180354.6" + attribute \src "libresoc.v:180308.3-180353.6" wire width 2 $7\src32__data_o$next[1:0]$11266 - attribute \src "libresoc.v:180131.17-180131.104" - wire $not$libresoc.v:180131$11223_Y - attribute \src "libresoc.v:180132.17-180132.100" - wire $not$libresoc.v:180132$11224_Y + attribute \src "libresoc.v:180130.17-180130.104" + wire $not$libresoc.v:180130$11223_Y + attribute \src "libresoc.v:180131.17-180131.100" + wire $not$libresoc.v:180131$11224_Y + attribute \src "libresoc.v:180132.17-180132.103" + wire $not$libresoc.v:180132$11225_Y attribute \src "libresoc.v:180133.17-180133.103" - wire $not$libresoc.v:180133$11225_Y - attribute \src "libresoc.v:180134.17-180134.103" - wire $not$libresoc.v:180134$11226_Y + wire $not$libresoc.v:180133$11226_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -370321,7 +367131,7 @@ module \reg_2$134 wire width 2 input 13 \dest32__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest32__wen - attribute \src "libresoc.v:180062.7-180062.15" + attribute \src "libresoc.v:180061.7-180061.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r2__data_o @@ -370364,129 +367174,129 @@ module \reg_2$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180131$11223 + cell $not $not$libresoc.v:180130$11223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:180131$11223_Y + connect \Y $not$libresoc.v:180130$11223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180132$11224 + cell $not $not$libresoc.v:180131$11224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:180132$11224_Y + connect \Y $not$libresoc.v:180131$11224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180133$11225 + cell $not $not$libresoc.v:180132$11225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:180133$11225_Y + connect \Y $not$libresoc.v:180132$11225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180134$11226 + cell $not $not$libresoc.v:180133$11226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:180134$11226_Y + connect \Y $not$libresoc.v:180133$11226_Y end - attribute \src "libresoc.v:180062.7-180062.20" - process $proc$libresoc.v:180062$11297 + attribute \src "libresoc.v:180061.7-180061.20" + process $proc$libresoc.v:180061$11297 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180089.13-180089.30" - process $proc$libresoc.v:180089$11298 + attribute \src "libresoc.v:180088.13-180088.30" + process $proc$libresoc.v:180088$11298 assign { } { } assign $1\r2__data_o[1:0] 2'00 sync always sync init update \r2__data_o $1\r2__data_o[1:0] end - attribute \src "libresoc.v:180095.13-180095.25" - process $proc$libresoc.v:180095$11299 + attribute \src "libresoc.v:180094.13-180094.25" + process $proc$libresoc.v:180094$11299 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:180100.13-180100.33" - process $proc$libresoc.v:180100$11300 + attribute \src "libresoc.v:180099.13-180099.33" + process $proc$libresoc.v:180099$11300 assign { } { } assign $1\src12__data_o[1:0] 2'00 sync always sync init update \src12__data_o $1\src12__data_o[1:0] end - attribute \src "libresoc.v:180107.13-180107.33" - process $proc$libresoc.v:180107$11301 + attribute \src "libresoc.v:180106.13-180106.33" + process $proc$libresoc.v:180106$11301 assign { } { } assign $1\src22__data_o[1:0] 2'00 sync always sync init update \src22__data_o $1\src22__data_o[1:0] end - attribute \src "libresoc.v:180114.13-180114.33" - process $proc$libresoc.v:180114$11302 + attribute \src "libresoc.v:180113.13-180113.33" + process $proc$libresoc.v:180113$11302 assign { } { } assign $1\src32__data_o[1:0] 2'00 sync always sync init update \src32__data_o $1\src32__data_o[1:0] end - attribute \src "libresoc.v:180135.3-180136.25" - process $proc$libresoc.v:180135$11227 + attribute \src "libresoc.v:180134.3-180135.25" + process $proc$libresoc.v:180134$11227 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:180137.3-180138.37" - process $proc$libresoc.v:180137$11228 + attribute \src "libresoc.v:180136.3-180137.37" + process $proc$libresoc.v:180136$11228 assign { } { } assign $0\r2__data_o[1:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[1:0] end - attribute \src "libresoc.v:180139.3-180140.43" - process $proc$libresoc.v:180139$11229 + attribute \src "libresoc.v:180138.3-180139.43" + process $proc$libresoc.v:180138$11229 assign { } { } assign $0\src32__data_o[1:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[1:0] end - attribute \src "libresoc.v:180141.3-180142.43" - process $proc$libresoc.v:180141$11230 + attribute \src "libresoc.v:180140.3-180141.43" + process $proc$libresoc.v:180140$11230 assign { } { } assign $0\src22__data_o[1:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[1:0] end - attribute \src "libresoc.v:180143.3-180144.43" - process $proc$libresoc.v:180143$11231 + attribute \src "libresoc.v:180142.3-180143.43" + process $proc$libresoc.v:180142$11231 assign { } { } assign $0\src12__data_o[1:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[1:0] end - attribute \src "libresoc.v:180145.3-180190.6" - process $proc$libresoc.v:180145$11232 + attribute \src "libresoc.v:180144.3-180189.6" + process $proc$libresoc.v:180144$11232 assign { } { } assign { } { } assign { } { } assign $0\src12__data_o$next[1:0]$11233 $7\src12__data_o$next[1:0]$11240 - attribute \src "libresoc.v:180146.5-180146.29" + attribute \src "libresoc.v:180145.5-180145.29" switch \initial - attribute \src "libresoc.v:180146.9-180146.17" + attribute \src "libresoc.v:180145.9-180145.17" case 1'1 case end @@ -370560,14 +367370,14 @@ module \reg_2$134 sync always update \src12__data_o$next $0\src12__data_o$next[1:0]$11233 end - attribute \src "libresoc.v:180191.3-180226.6" - process $proc$libresoc.v:180191$11241 + attribute \src "libresoc.v:180190.3-180225.6" + process $proc$libresoc.v:180190$11241 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:180192.5-180192.29" + attribute \src "libresoc.v:180191.5-180191.29" switch \initial - attribute \src "libresoc.v:180192.9-180192.17" + attribute \src "libresoc.v:180191.9-180191.17" case 1'1 case end @@ -370623,15 +367433,15 @@ module \reg_2$134 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:180227.3-180272.6" - process $proc$libresoc.v:180227$11242 + attribute \src "libresoc.v:180226.3-180271.6" + process $proc$libresoc.v:180226$11242 assign { } { } assign { } { } assign { } { } assign $0\src22__data_o$next[1:0]$11243 $7\src22__data_o$next[1:0]$11250 - attribute \src "libresoc.v:180228.5-180228.29" + attribute \src "libresoc.v:180227.5-180227.29" switch \initial - attribute \src "libresoc.v:180228.9-180228.17" + attribute \src "libresoc.v:180227.9-180227.17" case 1'1 case end @@ -370705,14 +367515,14 @@ module \reg_2$134 sync always update \src22__data_o$next $0\src22__data_o$next[1:0]$11243 end - attribute \src "libresoc.v:180273.3-180308.6" - process $proc$libresoc.v:180273$11251 + attribute \src "libresoc.v:180272.3-180307.6" + process $proc$libresoc.v:180272$11251 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11252 $1\wr_detect$4[0:0]$11253 - attribute \src "libresoc.v:180274.5-180274.29" + attribute \src "libresoc.v:180273.5-180273.29" switch \initial - attribute \src "libresoc.v:180274.9-180274.17" + attribute \src "libresoc.v:180273.9-180273.17" case 1'1 case end @@ -370768,15 +367578,15 @@ module \reg_2$134 sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11252 end - attribute \src "libresoc.v:180309.3-180354.6" - process $proc$libresoc.v:180309$11258 + attribute \src "libresoc.v:180308.3-180353.6" + process $proc$libresoc.v:180308$11258 assign { } { } assign { } { } assign { } { } assign $0\src32__data_o$next[1:0]$11259 $7\src32__data_o$next[1:0]$11266 - attribute \src "libresoc.v:180310.5-180310.29" + attribute \src "libresoc.v:180309.5-180309.29" switch \initial - attribute \src "libresoc.v:180310.9-180310.17" + attribute \src "libresoc.v:180309.9-180309.17" case 1'1 case end @@ -370850,14 +367660,14 @@ module \reg_2$134 sync always update \src32__data_o$next $0\src32__data_o$next[1:0]$11259 end - attribute \src "libresoc.v:180355.3-180390.6" - process $proc$libresoc.v:180355$11267 + attribute \src "libresoc.v:180354.3-180389.6" + process $proc$libresoc.v:180354$11267 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11268 $1\wr_detect$7[0:0]$11269 - attribute \src "libresoc.v:180356.5-180356.29" + attribute \src "libresoc.v:180355.5-180355.29" switch \initial - attribute \src "libresoc.v:180356.9-180356.17" + attribute \src "libresoc.v:180355.9-180355.17" case 1'1 case end @@ -370913,15 +367723,15 @@ module \reg_2$134 sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11268 end - attribute \src "libresoc.v:180391.3-180436.6" - process $proc$libresoc.v:180391$11274 + attribute \src "libresoc.v:180390.3-180435.6" + process $proc$libresoc.v:180390$11274 assign { } { } assign { } { } assign { } { } assign $0\r2__data_o$next[1:0]$11275 $7\r2__data_o$next[1:0]$11282 - attribute \src "libresoc.v:180392.5-180392.29" + attribute \src "libresoc.v:180391.5-180391.29" switch \initial - attribute \src "libresoc.v:180392.9-180392.17" + attribute \src "libresoc.v:180391.9-180391.17" case 1'1 case end @@ -370995,14 +367805,14 @@ module \reg_2$134 sync always update \r2__data_o$next $0\r2__data_o$next[1:0]$11275 end - attribute \src "libresoc.v:180437.3-180472.6" - process $proc$libresoc.v:180437$11283 + attribute \src "libresoc.v:180436.3-180471.6" + process $proc$libresoc.v:180436$11283 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$11284 $1\wr_detect$10[0:0]$11285 - attribute \src "libresoc.v:180438.5-180438.29" + attribute \src "libresoc.v:180437.5-180437.29" switch \initial - attribute \src "libresoc.v:180438.9-180438.17" + attribute \src "libresoc.v:180437.9-180437.17" case 1'1 case end @@ -371058,8 +367868,8 @@ module \reg_2$134 sync always update \wr_detect$10 $0\wr_detect$10[0:0]$11284 end - attribute \src "libresoc.v:180473.3-180505.6" - process $proc$libresoc.v:180473$11290 + attribute \src "libresoc.v:180472.3-180504.6" + process $proc$libresoc.v:180472$11290 assign { } { } assign { } { } assign { } { } @@ -371067,9 +367877,9 @@ module \reg_2$134 assign { } { } assign { } { } assign $0\reg$next[1:0]$11291 $5\reg$next[1:0]$11296 - attribute \src "libresoc.v:180474.5-180474.29" + attribute \src "libresoc.v:180473.5-180473.29" switch \initial - attribute \src "libresoc.v:180474.9-180474.17" + attribute \src "libresoc.v:180473.9-180473.17" case 1'1 case end @@ -371121,136 +367931,136 @@ module \reg_2$134 sync always update \reg$next $0\reg$next[1:0]$11291 end - connect \$9 $not$libresoc.v:180131$11223_Y - connect \$1 $not$libresoc.v:180132$11224_Y - connect \$3 $not$libresoc.v:180133$11225_Y - connect \$6 $not$libresoc.v:180134$11226_Y + connect \$9 $not$libresoc.v:180130$11223_Y + connect \$1 $not$libresoc.v:180131$11224_Y + connect \$3 $not$libresoc.v:180132$11225_Y + connect \$6 $not$libresoc.v:180133$11226_Y end -attribute \src "libresoc.v:180510.1-180859.10" +attribute \src "libresoc.v:180509.1-180858.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2" attribute \generator "nMigen" module \reg_2$137 - attribute \src "libresoc.v:180580.3-180625.6" + attribute \src "libresoc.v:180579.3-180624.6" wire width 64 $0\cia2__data_o$next[63:0]$11311 - attribute \src "libresoc.v:180578.3-180579.41" + attribute \src "libresoc.v:180577.3-180578.41" wire width 64 $0\cia2__data_o[63:0] - attribute \src "libresoc.v:180511.7-180511.20" + attribute \src "libresoc.v:180510.7-180510.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180662.3-180707.6" + attribute \src "libresoc.v:180661.3-180706.6" wire width 64 $0\msr2__data_o$next[63:0]$11321 - attribute \src "libresoc.v:180576.3-180577.41" + attribute \src "libresoc.v:180575.3-180576.41" wire width 64 $0\msr2__data_o[63:0] - attribute \src "libresoc.v:180826.3-180858.6" + attribute \src "libresoc.v:180825.3-180857.6" wire width 64 $0\reg$next[63:0]$11353 - attribute \src "libresoc.v:180572.3-180573.25" + attribute \src "libresoc.v:180571.3-180572.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:180744.3-180789.6" + attribute \src "libresoc.v:180743.3-180788.6" wire width 64 $0\sv2__data_o$next[63:0]$11337 - attribute \src "libresoc.v:180574.3-180575.39" + attribute \src "libresoc.v:180573.3-180574.39" wire width 64 $0\sv2__data_o[63:0] - attribute \src "libresoc.v:180708.3-180743.6" + attribute \src "libresoc.v:180707.3-180742.6" wire $0\wr_detect$4[0:0]$11330 - attribute \src "libresoc.v:180790.3-180825.6" + attribute \src "libresoc.v:180789.3-180824.6" wire $0\wr_detect$7[0:0]$11346 - attribute \src "libresoc.v:180626.3-180661.6" + attribute \src "libresoc.v:180625.3-180660.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:180580.3-180625.6" + attribute \src "libresoc.v:180579.3-180624.6" wire width 64 $1\cia2__data_o$next[63:0]$11312 - attribute \src "libresoc.v:180520.14-180520.49" + attribute \src "libresoc.v:180519.14-180519.49" wire width 64 $1\cia2__data_o[63:0] - attribute \src "libresoc.v:180662.3-180707.6" + attribute \src "libresoc.v:180661.3-180706.6" wire width 64 $1\msr2__data_o$next[63:0]$11322 - attribute \src "libresoc.v:180537.14-180537.49" + attribute \src "libresoc.v:180536.14-180536.49" wire width 64 $1\msr2__data_o[63:0] - attribute \src "libresoc.v:180826.3-180858.6" + attribute \src "libresoc.v:180825.3-180857.6" wire width 64 $1\reg$next[63:0]$11354 - attribute \src "libresoc.v:180549.14-180549.42" + attribute \src "libresoc.v:180548.14-180548.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:180744.3-180789.6" + attribute \src "libresoc.v:180743.3-180788.6" wire width 64 $1\sv2__data_o$next[63:0]$11338 - attribute \src "libresoc.v:180556.14-180556.48" + attribute \src "libresoc.v:180555.14-180555.48" wire width 64 $1\sv2__data_o[63:0] - attribute \src "libresoc.v:180708.3-180743.6" + attribute \src "libresoc.v:180707.3-180742.6" wire $1\wr_detect$4[0:0]$11331 - attribute \src "libresoc.v:180790.3-180825.6" + attribute \src "libresoc.v:180789.3-180824.6" wire $1\wr_detect$7[0:0]$11347 - attribute \src "libresoc.v:180626.3-180661.6" + attribute \src "libresoc.v:180625.3-180660.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:180580.3-180625.6" + attribute \src "libresoc.v:180579.3-180624.6" wire width 64 $2\cia2__data_o$next[63:0]$11313 - attribute \src "libresoc.v:180662.3-180707.6" + attribute \src "libresoc.v:180661.3-180706.6" wire width 64 $2\msr2__data_o$next[63:0]$11323 - attribute \src "libresoc.v:180826.3-180858.6" + attribute \src "libresoc.v:180825.3-180857.6" wire width 64 $2\reg$next[63:0]$11355 - attribute \src "libresoc.v:180744.3-180789.6" + attribute \src "libresoc.v:180743.3-180788.6" wire width 64 $2\sv2__data_o$next[63:0]$11339 - attribute \src "libresoc.v:180708.3-180743.6" + attribute \src "libresoc.v:180707.3-180742.6" wire $2\wr_detect$4[0:0]$11332 - attribute \src "libresoc.v:180790.3-180825.6" + attribute \src "libresoc.v:180789.3-180824.6" wire $2\wr_detect$7[0:0]$11348 - attribute \src "libresoc.v:180626.3-180661.6" + attribute \src "libresoc.v:180625.3-180660.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:180580.3-180625.6" + attribute \src "libresoc.v:180579.3-180624.6" wire width 64 $3\cia2__data_o$next[63:0]$11314 - attribute \src "libresoc.v:180662.3-180707.6" + attribute \src "libresoc.v:180661.3-180706.6" wire width 64 $3\msr2__data_o$next[63:0]$11324 - attribute \src "libresoc.v:180826.3-180858.6" + attribute \src "libresoc.v:180825.3-180857.6" wire width 64 $3\reg$next[63:0]$11356 - attribute \src "libresoc.v:180744.3-180789.6" + attribute \src "libresoc.v:180743.3-180788.6" wire width 64 $3\sv2__data_o$next[63:0]$11340 - attribute \src "libresoc.v:180708.3-180743.6" + attribute \src "libresoc.v:180707.3-180742.6" wire $3\wr_detect$4[0:0]$11333 - attribute \src "libresoc.v:180790.3-180825.6" + attribute \src "libresoc.v:180789.3-180824.6" wire $3\wr_detect$7[0:0]$11349 - attribute \src "libresoc.v:180626.3-180661.6" + attribute \src "libresoc.v:180625.3-180660.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:180580.3-180625.6" + attribute \src "libresoc.v:180579.3-180624.6" wire width 64 $4\cia2__data_o$next[63:0]$11315 - attribute \src "libresoc.v:180662.3-180707.6" + attribute \src "libresoc.v:180661.3-180706.6" wire width 64 $4\msr2__data_o$next[63:0]$11325 - attribute \src "libresoc.v:180826.3-180858.6" + attribute \src "libresoc.v:180825.3-180857.6" wire width 64 $4\reg$next[63:0]$11357 - attribute \src "libresoc.v:180744.3-180789.6" + attribute \src "libresoc.v:180743.3-180788.6" wire width 64 $4\sv2__data_o$next[63:0]$11341 - attribute \src "libresoc.v:180708.3-180743.6" + attribute \src "libresoc.v:180707.3-180742.6" wire $4\wr_detect$4[0:0]$11334 - attribute \src "libresoc.v:180790.3-180825.6" + attribute \src "libresoc.v:180789.3-180824.6" wire $4\wr_detect$7[0:0]$11350 - attribute \src "libresoc.v:180626.3-180661.6" + attribute \src "libresoc.v:180625.3-180660.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:180580.3-180625.6" + attribute \src "libresoc.v:180579.3-180624.6" wire width 64 $5\cia2__data_o$next[63:0]$11316 - attribute \src "libresoc.v:180662.3-180707.6" + attribute \src "libresoc.v:180661.3-180706.6" wire width 64 $5\msr2__data_o$next[63:0]$11326 - attribute \src "libresoc.v:180826.3-180858.6" + attribute \src "libresoc.v:180825.3-180857.6" wire width 64 $5\reg$next[63:0]$11358 - attribute \src "libresoc.v:180744.3-180789.6" + attribute \src "libresoc.v:180743.3-180788.6" wire width 64 $5\sv2__data_o$next[63:0]$11342 - attribute \src "libresoc.v:180708.3-180743.6" + attribute \src "libresoc.v:180707.3-180742.6" wire $5\wr_detect$4[0:0]$11335 - attribute \src "libresoc.v:180790.3-180825.6" + attribute \src "libresoc.v:180789.3-180824.6" wire $5\wr_detect$7[0:0]$11351 - attribute \src "libresoc.v:180626.3-180661.6" + attribute \src "libresoc.v:180625.3-180660.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:180580.3-180625.6" + attribute \src "libresoc.v:180579.3-180624.6" wire width 64 $6\cia2__data_o$next[63:0]$11317 - attribute \src "libresoc.v:180662.3-180707.6" + attribute \src "libresoc.v:180661.3-180706.6" wire width 64 $6\msr2__data_o$next[63:0]$11327 - attribute \src "libresoc.v:180744.3-180789.6" + attribute \src "libresoc.v:180743.3-180788.6" wire width 64 $6\sv2__data_o$next[63:0]$11343 - attribute \src "libresoc.v:180580.3-180625.6" + attribute \src "libresoc.v:180579.3-180624.6" wire width 64 $7\cia2__data_o$next[63:0]$11318 - attribute \src "libresoc.v:180662.3-180707.6" + attribute \src "libresoc.v:180661.3-180706.6" wire width 64 $7\msr2__data_o$next[63:0]$11328 - attribute \src "libresoc.v:180744.3-180789.6" + attribute \src "libresoc.v:180743.3-180788.6" wire width 64 $7\sv2__data_o$next[63:0]$11344 - attribute \src "libresoc.v:180569.17-180569.100" - wire $not$libresoc.v:180569$11303_Y + attribute \src "libresoc.v:180568.17-180568.100" + wire $not$libresoc.v:180568$11303_Y + attribute \src "libresoc.v:180569.17-180569.103" + wire $not$libresoc.v:180569$11304_Y attribute \src "libresoc.v:180570.17-180570.103" - wire $not$libresoc.v:180570$11304_Y - attribute \src "libresoc.v:180571.17-180571.103" - wire $not$libresoc.v:180571$11305_Y + wire $not$libresoc.v:180570$11305_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -371271,7 +368081,7 @@ module \reg_2$137 wire width 64 input 15 \d_wr12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr12__wen - attribute \src "libresoc.v:180511.7-180511.15" + attribute \src "libresoc.v:180510.7-180510.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr2__data_i @@ -371308,106 +368118,106 @@ module \reg_2$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180569$11303 + cell $not $not$libresoc.v:180568$11303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:180569$11303_Y + connect \Y $not$libresoc.v:180568$11303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180570$11304 + cell $not $not$libresoc.v:180569$11304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:180570$11304_Y + connect \Y $not$libresoc.v:180569$11304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180571$11305 + cell $not $not$libresoc.v:180570$11305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:180571$11305_Y + connect \Y $not$libresoc.v:180570$11305_Y end - attribute \src "libresoc.v:180511.7-180511.20" - process $proc$libresoc.v:180511$11359 + attribute \src "libresoc.v:180510.7-180510.20" + process $proc$libresoc.v:180510$11359 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180520.14-180520.49" - process $proc$libresoc.v:180520$11360 + attribute \src "libresoc.v:180519.14-180519.49" + process $proc$libresoc.v:180519$11360 assign { } { } assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia2__data_o $1\cia2__data_o[63:0] end - attribute \src "libresoc.v:180537.14-180537.49" - process $proc$libresoc.v:180537$11361 + attribute \src "libresoc.v:180536.14-180536.49" + process $proc$libresoc.v:180536$11361 assign { } { } assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr2__data_o $1\msr2__data_o[63:0] end - attribute \src "libresoc.v:180549.14-180549.42" - process $proc$libresoc.v:180549$11362 + attribute \src "libresoc.v:180548.14-180548.42" + process $proc$libresoc.v:180548$11362 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:180556.14-180556.48" - process $proc$libresoc.v:180556$11363 + attribute \src "libresoc.v:180555.14-180555.48" + process $proc$libresoc.v:180555$11363 assign { } { } assign $1\sv2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv2__data_o $1\sv2__data_o[63:0] end - attribute \src "libresoc.v:180572.3-180573.25" - process $proc$libresoc.v:180572$11306 + attribute \src "libresoc.v:180571.3-180572.25" + process $proc$libresoc.v:180571$11306 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:180574.3-180575.39" - process $proc$libresoc.v:180574$11307 + attribute \src "libresoc.v:180573.3-180574.39" + process $proc$libresoc.v:180573$11307 assign { } { } assign $0\sv2__data_o[63:0] \sv2__data_o$next sync posedge \coresync_clk update \sv2__data_o $0\sv2__data_o[63:0] end - attribute \src "libresoc.v:180576.3-180577.41" - process $proc$libresoc.v:180576$11308 + attribute \src "libresoc.v:180575.3-180576.41" + process $proc$libresoc.v:180575$11308 assign { } { } assign $0\msr2__data_o[63:0] \msr2__data_o$next sync posedge \coresync_clk update \msr2__data_o $0\msr2__data_o[63:0] end - attribute \src "libresoc.v:180578.3-180579.41" - process $proc$libresoc.v:180578$11309 + attribute \src "libresoc.v:180577.3-180578.41" + process $proc$libresoc.v:180577$11309 assign { } { } assign $0\cia2__data_o[63:0] \cia2__data_o$next sync posedge \coresync_clk update \cia2__data_o $0\cia2__data_o[63:0] end - attribute \src "libresoc.v:180580.3-180625.6" - process $proc$libresoc.v:180580$11310 + attribute \src "libresoc.v:180579.3-180624.6" + process $proc$libresoc.v:180579$11310 assign { } { } assign { } { } assign { } { } assign $0\cia2__data_o$next[63:0]$11311 $7\cia2__data_o$next[63:0]$11318 - attribute \src "libresoc.v:180581.5-180581.29" + attribute \src "libresoc.v:180580.5-180580.29" switch \initial - attribute \src "libresoc.v:180581.9-180581.17" + attribute \src "libresoc.v:180580.9-180580.17" case 1'1 case end @@ -371481,14 +368291,14 @@ module \reg_2$137 sync always update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11311 end - attribute \src "libresoc.v:180626.3-180661.6" - process $proc$libresoc.v:180626$11319 + attribute \src "libresoc.v:180625.3-180660.6" + process $proc$libresoc.v:180625$11319 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:180627.5-180627.29" + attribute \src "libresoc.v:180626.5-180626.29" switch \initial - attribute \src "libresoc.v:180627.9-180627.17" + attribute \src "libresoc.v:180626.9-180626.17" case 1'1 case end @@ -371544,15 +368354,15 @@ module \reg_2$137 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:180662.3-180707.6" - process $proc$libresoc.v:180662$11320 + attribute \src "libresoc.v:180661.3-180706.6" + process $proc$libresoc.v:180661$11320 assign { } { } assign { } { } assign { } { } assign $0\msr2__data_o$next[63:0]$11321 $7\msr2__data_o$next[63:0]$11328 - attribute \src "libresoc.v:180663.5-180663.29" + attribute \src "libresoc.v:180662.5-180662.29" switch \initial - attribute \src "libresoc.v:180663.9-180663.17" + attribute \src "libresoc.v:180662.9-180662.17" case 1'1 case end @@ -371626,14 +368436,14 @@ module \reg_2$137 sync always update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11321 end - attribute \src "libresoc.v:180708.3-180743.6" - process $proc$libresoc.v:180708$11329 + attribute \src "libresoc.v:180707.3-180742.6" + process $proc$libresoc.v:180707$11329 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11330 $1\wr_detect$4[0:0]$11331 - attribute \src "libresoc.v:180709.5-180709.29" + attribute \src "libresoc.v:180708.5-180708.29" switch \initial - attribute \src "libresoc.v:180709.9-180709.17" + attribute \src "libresoc.v:180708.9-180708.17" case 1'1 case end @@ -371689,15 +368499,15 @@ module \reg_2$137 sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11330 end - attribute \src "libresoc.v:180744.3-180789.6" - process $proc$libresoc.v:180744$11336 + attribute \src "libresoc.v:180743.3-180788.6" + process $proc$libresoc.v:180743$11336 assign { } { } assign { } { } assign { } { } assign $0\sv2__data_o$next[63:0]$11337 $7\sv2__data_o$next[63:0]$11344 - attribute \src "libresoc.v:180745.5-180745.29" + attribute \src "libresoc.v:180744.5-180744.29" switch \initial - attribute \src "libresoc.v:180745.9-180745.17" + attribute \src "libresoc.v:180744.9-180744.17" case 1'1 case end @@ -371771,14 +368581,14 @@ module \reg_2$137 sync always update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11337 end - attribute \src "libresoc.v:180790.3-180825.6" - process $proc$libresoc.v:180790$11345 + attribute \src "libresoc.v:180789.3-180824.6" + process $proc$libresoc.v:180789$11345 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11346 $1\wr_detect$7[0:0]$11347 - attribute \src "libresoc.v:180791.5-180791.29" + attribute \src "libresoc.v:180790.5-180790.29" switch \initial - attribute \src "libresoc.v:180791.9-180791.17" + attribute \src "libresoc.v:180790.9-180790.17" case 1'1 case end @@ -371834,8 +368644,8 @@ module \reg_2$137 sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11346 end - attribute \src "libresoc.v:180826.3-180858.6" - process $proc$libresoc.v:180826$11352 + attribute \src "libresoc.v:180825.3-180857.6" + process $proc$libresoc.v:180825$11352 assign { } { } assign { } { } assign { } { } @@ -371843,9 +368653,9 @@ module \reg_2$137 assign { } { } assign { } { } assign $0\reg$next[63:0]$11353 $5\reg$next[63:0]$11358 - attribute \src "libresoc.v:180827.5-180827.29" + attribute \src "libresoc.v:180826.5-180826.29" switch \initial - attribute \src "libresoc.v:180827.9-180827.17" + attribute \src "libresoc.v:180826.9-180826.17" case 1'1 case end @@ -371897,211 +368707,211 @@ module \reg_2$137 sync always update \reg$next $0\reg$next[63:0]$11353 end - connect \$1 $not$libresoc.v:180569$11303_Y - connect \$3 $not$libresoc.v:180570$11304_Y - connect \$6 $not$libresoc.v:180571$11305_Y + connect \$1 $not$libresoc.v:180568$11303_Y + connect \$3 $not$libresoc.v:180569$11304_Y + connect \$6 $not$libresoc.v:180570$11305_Y end -attribute \src "libresoc.v:180863.1-181418.10" +attribute \src "libresoc.v:180862.1-181417.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_3" attribute \generator "nMigen" module \reg_3 - attribute \src "libresoc.v:180971.3-181010.6" + attribute \src "libresoc.v:180970.3-181009.6" wire width 4 $0\cr_pred3__data_o$next[3:0]$11378 - attribute \src "libresoc.v:180969.3-180970.49" + attribute \src "libresoc.v:180968.3-180969.49" wire width 4 $0\cr_pred3__data_o[3:0] - attribute \src "libresoc.v:180864.7-180864.20" + attribute \src "libresoc.v:180863.7-180863.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181041.3-181080.6" + attribute \src "libresoc.v:181040.3-181079.6" wire width 4 $0\r23__data_o$next[3:0]$11387 - attribute \src "libresoc.v:180959.3-180960.39" + attribute \src "libresoc.v:180958.3-180959.39" wire width 4 $0\r23__data_o[3:0] - attribute \src "libresoc.v:181348.3-181387.6" + attribute \src "libresoc.v:181347.3-181386.6" wire width 4 $0\r3__data_o$next[3:0]$11449 - attribute \src "libresoc.v:180961.3-180962.37" + attribute \src "libresoc.v:180960.3-180961.37" wire width 4 $0\r3__data_o[3:0] - attribute \src "libresoc.v:181111.3-181137.6" + attribute \src "libresoc.v:181110.3-181136.6" wire width 4 $0\reg$next[3:0]$11401 - attribute \src "libresoc.v:180957.3-180958.25" + attribute \src "libresoc.v:180956.3-180957.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:181138.3-181177.6" + attribute \src "libresoc.v:181137.3-181176.6" wire width 4 $0\src13__data_o$next[3:0]$11407 - attribute \src "libresoc.v:180967.3-180968.43" + attribute \src "libresoc.v:180966.3-180967.43" wire width 4 $0\src13__data_o[3:0] - attribute \src "libresoc.v:181208.3-181247.6" + attribute \src "libresoc.v:181207.3-181246.6" wire width 4 $0\src23__data_o$next[3:0]$11421 - attribute \src "libresoc.v:180965.3-180966.43" + attribute \src "libresoc.v:180964.3-180965.43" wire width 4 $0\src23__data_o[3:0] - attribute \src "libresoc.v:181278.3-181317.6" + attribute \src "libresoc.v:181277.3-181316.6" wire width 4 $0\src33__data_o$next[3:0]$11435 - attribute \src "libresoc.v:180963.3-180964.43" + attribute \src "libresoc.v:180962.3-180963.43" wire width 4 $0\src33__data_o[3:0] - attribute \src "libresoc.v:181318.3-181347.6" + attribute \src "libresoc.v:181317.3-181346.6" wire $0\wr_detect$10[0:0]$11443 - attribute \src "libresoc.v:181388.3-181417.6" + attribute \src "libresoc.v:181387.3-181416.6" wire $0\wr_detect$13[0:0]$11457 - attribute \src "libresoc.v:181081.3-181110.6" + attribute \src "libresoc.v:181080.3-181109.6" wire $0\wr_detect$16[0:0]$11395 - attribute \src "libresoc.v:181178.3-181207.6" + attribute \src "libresoc.v:181177.3-181206.6" wire $0\wr_detect$4[0:0]$11415 - attribute \src "libresoc.v:181248.3-181277.6" + attribute \src "libresoc.v:181247.3-181276.6" wire $0\wr_detect$7[0:0]$11429 - attribute \src "libresoc.v:181011.3-181040.6" + attribute \src "libresoc.v:181010.3-181039.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:180971.3-181010.6" + attribute \src "libresoc.v:180970.3-181009.6" wire width 4 $1\cr_pred3__data_o$next[3:0]$11379 - attribute \src "libresoc.v:180883.13-180883.36" + attribute \src "libresoc.v:180882.13-180882.36" wire width 4 $1\cr_pred3__data_o[3:0] - attribute \src "libresoc.v:181041.3-181080.6" + attribute \src "libresoc.v:181040.3-181079.6" wire width 4 $1\r23__data_o$next[3:0]$11388 - attribute \src "libresoc.v:180898.13-180898.31" + attribute \src "libresoc.v:180897.13-180897.31" wire width 4 $1\r23__data_o[3:0] - attribute \src "libresoc.v:181348.3-181387.6" + attribute \src "libresoc.v:181347.3-181386.6" wire width 4 $1\r3__data_o$next[3:0]$11450 - attribute \src "libresoc.v:180905.13-180905.30" + attribute \src "libresoc.v:180904.13-180904.30" wire width 4 $1\r3__data_o[3:0] - attribute \src "libresoc.v:181111.3-181137.6" + attribute \src "libresoc.v:181110.3-181136.6" wire width 4 $1\reg$next[3:0]$11402 - attribute \src "libresoc.v:180911.13-180911.25" + attribute \src "libresoc.v:180910.13-180910.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:181138.3-181177.6" + attribute \src "libresoc.v:181137.3-181176.6" wire width 4 $1\src13__data_o$next[3:0]$11408 - attribute \src "libresoc.v:180916.13-180916.33" + attribute \src "libresoc.v:180915.13-180915.33" wire width 4 $1\src13__data_o[3:0] - attribute \src "libresoc.v:181208.3-181247.6" + attribute \src "libresoc.v:181207.3-181246.6" wire width 4 $1\src23__data_o$next[3:0]$11422 - attribute \src "libresoc.v:180923.13-180923.33" + attribute \src "libresoc.v:180922.13-180922.33" wire width 4 $1\src23__data_o[3:0] - attribute \src "libresoc.v:181278.3-181317.6" + attribute \src "libresoc.v:181277.3-181316.6" wire width 4 $1\src33__data_o$next[3:0]$11436 - attribute \src "libresoc.v:180930.13-180930.33" + attribute \src "libresoc.v:180929.13-180929.33" wire width 4 $1\src33__data_o[3:0] - attribute \src "libresoc.v:181318.3-181347.6" + attribute \src "libresoc.v:181317.3-181346.6" wire $1\wr_detect$10[0:0]$11444 - attribute \src "libresoc.v:181388.3-181417.6" + attribute \src "libresoc.v:181387.3-181416.6" wire $1\wr_detect$13[0:0]$11458 - attribute \src "libresoc.v:181081.3-181110.6" + attribute \src "libresoc.v:181080.3-181109.6" wire $1\wr_detect$16[0:0]$11396 - attribute \src "libresoc.v:181178.3-181207.6" + attribute \src "libresoc.v:181177.3-181206.6" wire $1\wr_detect$4[0:0]$11416 - attribute \src "libresoc.v:181248.3-181277.6" + attribute \src "libresoc.v:181247.3-181276.6" wire $1\wr_detect$7[0:0]$11430 - attribute \src "libresoc.v:181011.3-181040.6" + attribute \src "libresoc.v:181010.3-181039.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:180971.3-181010.6" + attribute \src "libresoc.v:180970.3-181009.6" wire width 4 $2\cr_pred3__data_o$next[3:0]$11380 - attribute \src "libresoc.v:181041.3-181080.6" + attribute \src "libresoc.v:181040.3-181079.6" wire width 4 $2\r23__data_o$next[3:0]$11389 - attribute \src "libresoc.v:181348.3-181387.6" + attribute \src "libresoc.v:181347.3-181386.6" wire width 4 $2\r3__data_o$next[3:0]$11451 - attribute \src "libresoc.v:181111.3-181137.6" + attribute \src "libresoc.v:181110.3-181136.6" wire width 4 $2\reg$next[3:0]$11403 - attribute \src "libresoc.v:181138.3-181177.6" + attribute \src "libresoc.v:181137.3-181176.6" wire width 4 $2\src13__data_o$next[3:0]$11409 - attribute \src "libresoc.v:181208.3-181247.6" + attribute \src "libresoc.v:181207.3-181246.6" wire width 4 $2\src23__data_o$next[3:0]$11423 - attribute \src "libresoc.v:181278.3-181317.6" + attribute \src "libresoc.v:181277.3-181316.6" wire width 4 $2\src33__data_o$next[3:0]$11437 - attribute \src "libresoc.v:181318.3-181347.6" + attribute \src "libresoc.v:181317.3-181346.6" wire $2\wr_detect$10[0:0]$11445 - attribute \src "libresoc.v:181388.3-181417.6" + attribute \src "libresoc.v:181387.3-181416.6" wire $2\wr_detect$13[0:0]$11459 - attribute \src "libresoc.v:181081.3-181110.6" + attribute \src "libresoc.v:181080.3-181109.6" wire $2\wr_detect$16[0:0]$11397 - attribute \src "libresoc.v:181178.3-181207.6" + attribute \src "libresoc.v:181177.3-181206.6" wire $2\wr_detect$4[0:0]$11417 - attribute \src "libresoc.v:181248.3-181277.6" + attribute \src "libresoc.v:181247.3-181276.6" wire $2\wr_detect$7[0:0]$11431 - attribute \src "libresoc.v:181011.3-181040.6" + attribute \src "libresoc.v:181010.3-181039.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:180971.3-181010.6" + attribute \src "libresoc.v:180970.3-181009.6" wire width 4 $3\cr_pred3__data_o$next[3:0]$11381 - attribute \src "libresoc.v:181041.3-181080.6" + attribute \src "libresoc.v:181040.3-181079.6" wire width 4 $3\r23__data_o$next[3:0]$11390 - attribute \src "libresoc.v:181348.3-181387.6" + attribute \src "libresoc.v:181347.3-181386.6" wire width 4 $3\r3__data_o$next[3:0]$11452 - attribute \src "libresoc.v:181111.3-181137.6" + attribute \src "libresoc.v:181110.3-181136.6" wire width 4 $3\reg$next[3:0]$11404 - attribute \src "libresoc.v:181138.3-181177.6" + attribute \src "libresoc.v:181137.3-181176.6" wire width 4 $3\src13__data_o$next[3:0]$11410 - attribute \src "libresoc.v:181208.3-181247.6" + attribute \src "libresoc.v:181207.3-181246.6" wire width 4 $3\src23__data_o$next[3:0]$11424 - attribute \src "libresoc.v:181278.3-181317.6" + attribute \src "libresoc.v:181277.3-181316.6" wire width 4 $3\src33__data_o$next[3:0]$11438 - attribute \src "libresoc.v:181318.3-181347.6" + attribute \src "libresoc.v:181317.3-181346.6" wire $3\wr_detect$10[0:0]$11446 - attribute \src "libresoc.v:181388.3-181417.6" + attribute \src "libresoc.v:181387.3-181416.6" wire $3\wr_detect$13[0:0]$11460 - attribute \src "libresoc.v:181081.3-181110.6" + attribute \src "libresoc.v:181080.3-181109.6" wire $3\wr_detect$16[0:0]$11398 - attribute \src "libresoc.v:181178.3-181207.6" + attribute \src "libresoc.v:181177.3-181206.6" wire $3\wr_detect$4[0:0]$11418 - attribute \src "libresoc.v:181248.3-181277.6" + attribute \src "libresoc.v:181247.3-181276.6" wire $3\wr_detect$7[0:0]$11432 - attribute \src "libresoc.v:181011.3-181040.6" + attribute \src "libresoc.v:181010.3-181039.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:180971.3-181010.6" + attribute \src "libresoc.v:180970.3-181009.6" wire width 4 $4\cr_pred3__data_o$next[3:0]$11382 - attribute \src "libresoc.v:181041.3-181080.6" + attribute \src "libresoc.v:181040.3-181079.6" wire width 4 $4\r23__data_o$next[3:0]$11391 - attribute \src "libresoc.v:181348.3-181387.6" + attribute \src "libresoc.v:181347.3-181386.6" wire width 4 $4\r3__data_o$next[3:0]$11453 - attribute \src "libresoc.v:181111.3-181137.6" + attribute \src "libresoc.v:181110.3-181136.6" wire width 4 $4\reg$next[3:0]$11405 - attribute \src "libresoc.v:181138.3-181177.6" + attribute \src "libresoc.v:181137.3-181176.6" wire width 4 $4\src13__data_o$next[3:0]$11411 - attribute \src "libresoc.v:181208.3-181247.6" + attribute \src "libresoc.v:181207.3-181246.6" wire width 4 $4\src23__data_o$next[3:0]$11425 - attribute \src "libresoc.v:181278.3-181317.6" + attribute \src "libresoc.v:181277.3-181316.6" wire width 4 $4\src33__data_o$next[3:0]$11439 - attribute \src "libresoc.v:181318.3-181347.6" + attribute \src "libresoc.v:181317.3-181346.6" wire $4\wr_detect$10[0:0]$11447 - attribute \src "libresoc.v:181388.3-181417.6" + attribute \src "libresoc.v:181387.3-181416.6" wire $4\wr_detect$13[0:0]$11461 - attribute \src "libresoc.v:181081.3-181110.6" + attribute \src "libresoc.v:181080.3-181109.6" wire $4\wr_detect$16[0:0]$11399 - attribute \src "libresoc.v:181178.3-181207.6" + attribute \src "libresoc.v:181177.3-181206.6" wire $4\wr_detect$4[0:0]$11419 - attribute \src "libresoc.v:181248.3-181277.6" + attribute \src "libresoc.v:181247.3-181276.6" wire $4\wr_detect$7[0:0]$11433 - attribute \src "libresoc.v:181011.3-181040.6" + attribute \src "libresoc.v:181010.3-181039.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:180971.3-181010.6" + attribute \src "libresoc.v:180970.3-181009.6" wire width 4 $5\cr_pred3__data_o$next[3:0]$11383 - attribute \src "libresoc.v:181041.3-181080.6" + attribute \src "libresoc.v:181040.3-181079.6" wire width 4 $5\r23__data_o$next[3:0]$11392 - attribute \src "libresoc.v:181348.3-181387.6" + attribute \src "libresoc.v:181347.3-181386.6" wire width 4 $5\r3__data_o$next[3:0]$11454 - attribute \src "libresoc.v:181138.3-181177.6" + attribute \src "libresoc.v:181137.3-181176.6" wire width 4 $5\src13__data_o$next[3:0]$11412 - attribute \src "libresoc.v:181208.3-181247.6" + attribute \src "libresoc.v:181207.3-181246.6" wire width 4 $5\src23__data_o$next[3:0]$11426 - attribute \src "libresoc.v:181278.3-181317.6" + attribute \src "libresoc.v:181277.3-181316.6" wire width 4 $5\src33__data_o$next[3:0]$11440 - attribute \src "libresoc.v:180971.3-181010.6" + attribute \src "libresoc.v:180970.3-181009.6" wire width 4 $6\cr_pred3__data_o$next[3:0]$11384 - attribute \src "libresoc.v:181041.3-181080.6" + attribute \src "libresoc.v:181040.3-181079.6" wire width 4 $6\r23__data_o$next[3:0]$11393 - attribute \src "libresoc.v:181348.3-181387.6" + attribute \src "libresoc.v:181347.3-181386.6" wire width 4 $6\r3__data_o$next[3:0]$11455 - attribute \src "libresoc.v:181138.3-181177.6" + attribute \src "libresoc.v:181137.3-181176.6" wire width 4 $6\src13__data_o$next[3:0]$11413 - attribute \src "libresoc.v:181208.3-181247.6" + attribute \src "libresoc.v:181207.3-181246.6" wire width 4 $6\src23__data_o$next[3:0]$11427 - attribute \src "libresoc.v:181278.3-181317.6" + attribute \src "libresoc.v:181277.3-181316.6" wire width 4 $6\src33__data_o$next[3:0]$11441 - attribute \src "libresoc.v:180951.17-180951.104" - wire $not$libresoc.v:180951$11364_Y + attribute \src "libresoc.v:180950.17-180950.104" + wire $not$libresoc.v:180950$11364_Y + attribute \src "libresoc.v:180951.18-180951.105" + wire $not$libresoc.v:180951$11365_Y attribute \src "libresoc.v:180952.18-180952.105" - wire $not$libresoc.v:180952$11365_Y - attribute \src "libresoc.v:180953.18-180953.105" - wire $not$libresoc.v:180953$11366_Y - attribute \src "libresoc.v:180954.17-180954.100" - wire $not$libresoc.v:180954$11367_Y + wire $not$libresoc.v:180952$11366_Y + attribute \src "libresoc.v:180953.17-180953.100" + wire $not$libresoc.v:180953$11367_Y + attribute \src "libresoc.v:180954.17-180954.103" + wire $not$libresoc.v:180954$11368_Y attribute \src "libresoc.v:180955.17-180955.103" - wire $not$libresoc.v:180955$11368_Y - attribute \src "libresoc.v:180956.17-180956.103" - wire $not$libresoc.v:180956$11369_Y + wire $not$libresoc.v:180955$11369_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -372132,7 +368942,7 @@ module \reg_3 wire width 4 input 13 \dest23__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest23__wen - attribute \src "libresoc.v:180864.7-180864.15" + attribute \src "libresoc.v:180863.7-180863.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 16 \r23__data_o @@ -372185,175 +368995,175 @@ module \reg_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180951$11364 + cell $not $not$libresoc.v:180950$11364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:180951$11364_Y + connect \Y $not$libresoc.v:180950$11364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180952$11365 + cell $not $not$libresoc.v:180951$11365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:180952$11365_Y + connect \Y $not$libresoc.v:180951$11365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180953$11366 + cell $not $not$libresoc.v:180952$11366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$16 - connect \Y $not$libresoc.v:180953$11366_Y + connect \Y $not$libresoc.v:180952$11366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180954$11367 + cell $not $not$libresoc.v:180953$11367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:180954$11367_Y + connect \Y $not$libresoc.v:180953$11367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180955$11368 + cell $not $not$libresoc.v:180954$11368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:180955$11368_Y + connect \Y $not$libresoc.v:180954$11368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180956$11369 + cell $not $not$libresoc.v:180955$11369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:180956$11369_Y + connect \Y $not$libresoc.v:180955$11369_Y end - attribute \src "libresoc.v:180864.7-180864.20" - process $proc$libresoc.v:180864$11462 + attribute \src "libresoc.v:180863.7-180863.20" + process $proc$libresoc.v:180863$11462 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180883.13-180883.36" - process $proc$libresoc.v:180883$11463 + attribute \src "libresoc.v:180882.13-180882.36" + process $proc$libresoc.v:180882$11463 assign { } { } assign $1\cr_pred3__data_o[3:0] 4'0000 sync always sync init update \cr_pred3__data_o $1\cr_pred3__data_o[3:0] end - attribute \src "libresoc.v:180898.13-180898.31" - process $proc$libresoc.v:180898$11464 + attribute \src "libresoc.v:180897.13-180897.31" + process $proc$libresoc.v:180897$11464 assign { } { } assign $1\r23__data_o[3:0] 4'0000 sync always sync init update \r23__data_o $1\r23__data_o[3:0] end - attribute \src "libresoc.v:180905.13-180905.30" - process $proc$libresoc.v:180905$11465 + attribute \src "libresoc.v:180904.13-180904.30" + process $proc$libresoc.v:180904$11465 assign { } { } assign $1\r3__data_o[3:0] 4'0000 sync always sync init update \r3__data_o $1\r3__data_o[3:0] end - attribute \src "libresoc.v:180911.13-180911.25" - process $proc$libresoc.v:180911$11466 + attribute \src "libresoc.v:180910.13-180910.25" + process $proc$libresoc.v:180910$11466 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:180916.13-180916.33" - process $proc$libresoc.v:180916$11467 + attribute \src "libresoc.v:180915.13-180915.33" + process $proc$libresoc.v:180915$11467 assign { } { } assign $1\src13__data_o[3:0] 4'0000 sync always sync init update \src13__data_o $1\src13__data_o[3:0] end - attribute \src "libresoc.v:180923.13-180923.33" - process $proc$libresoc.v:180923$11468 + attribute \src "libresoc.v:180922.13-180922.33" + process $proc$libresoc.v:180922$11468 assign { } { } assign $1\src23__data_o[3:0] 4'0000 sync always sync init update \src23__data_o $1\src23__data_o[3:0] end - attribute \src "libresoc.v:180930.13-180930.33" - process $proc$libresoc.v:180930$11469 + attribute \src "libresoc.v:180929.13-180929.33" + process $proc$libresoc.v:180929$11469 assign { } { } assign $1\src33__data_o[3:0] 4'0000 sync always sync init update \src33__data_o $1\src33__data_o[3:0] end - attribute \src "libresoc.v:180957.3-180958.25" - process $proc$libresoc.v:180957$11370 + attribute \src "libresoc.v:180956.3-180957.25" + process $proc$libresoc.v:180956$11370 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:180959.3-180960.39" - process $proc$libresoc.v:180959$11371 + attribute \src "libresoc.v:180958.3-180959.39" + process $proc$libresoc.v:180958$11371 assign { } { } assign $0\r23__data_o[3:0] \r23__data_o$next sync posedge \coresync_clk update \r23__data_o $0\r23__data_o[3:0] end - attribute \src "libresoc.v:180961.3-180962.37" - process $proc$libresoc.v:180961$11372 + attribute \src "libresoc.v:180960.3-180961.37" + process $proc$libresoc.v:180960$11372 assign { } { } assign $0\r3__data_o[3:0] \r3__data_o$next sync posedge \coresync_clk update \r3__data_o $0\r3__data_o[3:0] end - attribute \src "libresoc.v:180963.3-180964.43" - process $proc$libresoc.v:180963$11373 + attribute \src "libresoc.v:180962.3-180963.43" + process $proc$libresoc.v:180962$11373 assign { } { } assign $0\src33__data_o[3:0] \src33__data_o$next sync posedge \coresync_clk update \src33__data_o $0\src33__data_o[3:0] end - attribute \src "libresoc.v:180965.3-180966.43" - process $proc$libresoc.v:180965$11374 + attribute \src "libresoc.v:180964.3-180965.43" + process $proc$libresoc.v:180964$11374 assign { } { } assign $0\src23__data_o[3:0] \src23__data_o$next sync posedge \coresync_clk update \src23__data_o $0\src23__data_o[3:0] end - attribute \src "libresoc.v:180967.3-180968.43" - process $proc$libresoc.v:180967$11375 + attribute \src "libresoc.v:180966.3-180967.43" + process $proc$libresoc.v:180966$11375 assign { } { } assign $0\src13__data_o[3:0] \src13__data_o$next sync posedge \coresync_clk update \src13__data_o $0\src13__data_o[3:0] end - attribute \src "libresoc.v:180969.3-180970.49" - process $proc$libresoc.v:180969$11376 + attribute \src "libresoc.v:180968.3-180969.49" + process $proc$libresoc.v:180968$11376 assign { } { } assign $0\cr_pred3__data_o[3:0] \cr_pred3__data_o$next sync posedge \coresync_clk update \cr_pred3__data_o $0\cr_pred3__data_o[3:0] end - attribute \src "libresoc.v:180971.3-181010.6" - process $proc$libresoc.v:180971$11377 + attribute \src "libresoc.v:180970.3-181009.6" + process $proc$libresoc.v:180970$11377 assign { } { } assign { } { } assign { } { } assign $0\cr_pred3__data_o$next[3:0]$11378 $6\cr_pred3__data_o$next[3:0]$11384 - attribute \src "libresoc.v:180972.5-180972.29" + attribute \src "libresoc.v:180971.5-180971.29" switch \initial - attribute \src "libresoc.v:180972.9-180972.17" + attribute \src "libresoc.v:180971.9-180971.17" case 1'1 case end @@ -372417,14 +369227,14 @@ module \reg_3 sync always update \cr_pred3__data_o$next $0\cr_pred3__data_o$next[3:0]$11378 end - attribute \src "libresoc.v:181011.3-181040.6" - process $proc$libresoc.v:181011$11385 + attribute \src "libresoc.v:181010.3-181039.6" + process $proc$libresoc.v:181010$11385 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:181012.5-181012.29" + attribute \src "libresoc.v:181011.5-181011.29" switch \initial - attribute \src "libresoc.v:181012.9-181012.17" + attribute \src "libresoc.v:181011.9-181011.17" case 1'1 case end @@ -372470,15 +369280,15 @@ module \reg_3 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:181041.3-181080.6" - process $proc$libresoc.v:181041$11386 + attribute \src "libresoc.v:181040.3-181079.6" + process $proc$libresoc.v:181040$11386 assign { } { } assign { } { } assign { } { } assign $0\r23__data_o$next[3:0]$11387 $6\r23__data_o$next[3:0]$11393 - attribute \src "libresoc.v:181042.5-181042.29" + attribute \src "libresoc.v:181041.5-181041.29" switch \initial - attribute \src "libresoc.v:181042.9-181042.17" + attribute \src "libresoc.v:181041.9-181041.17" case 1'1 case end @@ -372542,14 +369352,14 @@ module \reg_3 sync always update \r23__data_o$next $0\r23__data_o$next[3:0]$11387 end - attribute \src "libresoc.v:181081.3-181110.6" - process $proc$libresoc.v:181081$11394 + attribute \src "libresoc.v:181080.3-181109.6" + process $proc$libresoc.v:181080$11394 assign { } { } assign { } { } assign $0\wr_detect$16[0:0]$11395 $1\wr_detect$16[0:0]$11396 - attribute \src "libresoc.v:181082.5-181082.29" + attribute \src "libresoc.v:181081.5-181081.29" switch \initial - attribute \src "libresoc.v:181082.9-181082.17" + attribute \src "libresoc.v:181081.9-181081.17" case 1'1 case end @@ -372595,17 +369405,17 @@ module \reg_3 sync always update \wr_detect$16 $0\wr_detect$16[0:0]$11395 end - attribute \src "libresoc.v:181111.3-181137.6" - process $proc$libresoc.v:181111$11400 + attribute \src "libresoc.v:181110.3-181136.6" + process $proc$libresoc.v:181110$11400 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[3:0]$11401 $4\reg$next[3:0]$11405 - attribute \src "libresoc.v:181112.5-181112.29" + attribute \src "libresoc.v:181111.5-181111.29" switch \initial - attribute \src "libresoc.v:181112.9-181112.17" + attribute \src "libresoc.v:181111.9-181111.17" case 1'1 case end @@ -372648,15 +369458,15 @@ module \reg_3 sync always update \reg$next $0\reg$next[3:0]$11401 end - attribute \src "libresoc.v:181138.3-181177.6" - process $proc$libresoc.v:181138$11406 + attribute \src "libresoc.v:181137.3-181176.6" + process $proc$libresoc.v:181137$11406 assign { } { } assign { } { } assign { } { } assign $0\src13__data_o$next[3:0]$11407 $6\src13__data_o$next[3:0]$11413 - attribute \src "libresoc.v:181139.5-181139.29" + attribute \src "libresoc.v:181138.5-181138.29" switch \initial - attribute \src "libresoc.v:181139.9-181139.17" + attribute \src "libresoc.v:181138.9-181138.17" case 1'1 case end @@ -372720,14 +369530,14 @@ module \reg_3 sync always update \src13__data_o$next $0\src13__data_o$next[3:0]$11407 end - attribute \src "libresoc.v:181178.3-181207.6" - process $proc$libresoc.v:181178$11414 + attribute \src "libresoc.v:181177.3-181206.6" + process $proc$libresoc.v:181177$11414 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11415 $1\wr_detect$4[0:0]$11416 - attribute \src "libresoc.v:181179.5-181179.29" + attribute \src "libresoc.v:181178.5-181178.29" switch \initial - attribute \src "libresoc.v:181179.9-181179.17" + attribute \src "libresoc.v:181178.9-181178.17" case 1'1 case end @@ -372773,15 +369583,15 @@ module \reg_3 sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11415 end - attribute \src "libresoc.v:181208.3-181247.6" - process $proc$libresoc.v:181208$11420 + attribute \src "libresoc.v:181207.3-181246.6" + process $proc$libresoc.v:181207$11420 assign { } { } assign { } { } assign { } { } assign $0\src23__data_o$next[3:0]$11421 $6\src23__data_o$next[3:0]$11427 - attribute \src "libresoc.v:181209.5-181209.29" + attribute \src "libresoc.v:181208.5-181208.29" switch \initial - attribute \src "libresoc.v:181209.9-181209.17" + attribute \src "libresoc.v:181208.9-181208.17" case 1'1 case end @@ -372845,14 +369655,14 @@ module \reg_3 sync always update \src23__data_o$next $0\src23__data_o$next[3:0]$11421 end - attribute \src "libresoc.v:181248.3-181277.6" - process $proc$libresoc.v:181248$11428 + attribute \src "libresoc.v:181247.3-181276.6" + process $proc$libresoc.v:181247$11428 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11429 $1\wr_detect$7[0:0]$11430 - attribute \src "libresoc.v:181249.5-181249.29" + attribute \src "libresoc.v:181248.5-181248.29" switch \initial - attribute \src "libresoc.v:181249.9-181249.17" + attribute \src "libresoc.v:181248.9-181248.17" case 1'1 case end @@ -372898,15 +369708,15 @@ module \reg_3 sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11429 end - attribute \src "libresoc.v:181278.3-181317.6" - process $proc$libresoc.v:181278$11434 + attribute \src "libresoc.v:181277.3-181316.6" + process $proc$libresoc.v:181277$11434 assign { } { } assign { } { } assign { } { } assign $0\src33__data_o$next[3:0]$11435 $6\src33__data_o$next[3:0]$11441 - attribute \src "libresoc.v:181279.5-181279.29" + attribute \src "libresoc.v:181278.5-181278.29" switch \initial - attribute \src "libresoc.v:181279.9-181279.17" + attribute \src "libresoc.v:181278.9-181278.17" case 1'1 case end @@ -372970,14 +369780,14 @@ module \reg_3 sync always update \src33__data_o$next $0\src33__data_o$next[3:0]$11435 end - attribute \src "libresoc.v:181318.3-181347.6" - process $proc$libresoc.v:181318$11442 + attribute \src "libresoc.v:181317.3-181346.6" + process $proc$libresoc.v:181317$11442 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$11443 $1\wr_detect$10[0:0]$11444 - attribute \src "libresoc.v:181319.5-181319.29" + attribute \src "libresoc.v:181318.5-181318.29" switch \initial - attribute \src "libresoc.v:181319.9-181319.17" + attribute \src "libresoc.v:181318.9-181318.17" case 1'1 case end @@ -373023,15 +369833,15 @@ module \reg_3 sync always update \wr_detect$10 $0\wr_detect$10[0:0]$11443 end - attribute \src "libresoc.v:181348.3-181387.6" - process $proc$libresoc.v:181348$11448 + attribute \src "libresoc.v:181347.3-181386.6" + process $proc$libresoc.v:181347$11448 assign { } { } assign { } { } assign { } { } assign $0\r3__data_o$next[3:0]$11449 $6\r3__data_o$next[3:0]$11455 - attribute \src "libresoc.v:181349.5-181349.29" + attribute \src "libresoc.v:181348.5-181348.29" switch \initial - attribute \src "libresoc.v:181349.9-181349.17" + attribute \src "libresoc.v:181348.9-181348.17" case 1'1 case end @@ -373095,14 +369905,14 @@ module \reg_3 sync always update \r3__data_o$next $0\r3__data_o$next[3:0]$11449 end - attribute \src "libresoc.v:181388.3-181417.6" - process $proc$libresoc.v:181388$11456 + attribute \src "libresoc.v:181387.3-181416.6" + process $proc$libresoc.v:181387$11456 assign { } { } assign { } { } assign $0\wr_detect$13[0:0]$11457 $1\wr_detect$13[0:0]$11458 - attribute \src "libresoc.v:181389.5-181389.29" + attribute \src "libresoc.v:181388.5-181388.29" switch \initial - attribute \src "libresoc.v:181389.9-181389.17" + attribute \src "libresoc.v:181388.9-181388.17" case 1'1 case end @@ -373148,214 +369958,214 @@ module \reg_3 sync always update \wr_detect$13 $0\wr_detect$13[0:0]$11457 end - connect \$9 $not$libresoc.v:180951$11364_Y - connect \$12 $not$libresoc.v:180952$11365_Y - connect \$15 $not$libresoc.v:180953$11366_Y - connect \$1 $not$libresoc.v:180954$11367_Y - connect \$3 $not$libresoc.v:180955$11368_Y - connect \$6 $not$libresoc.v:180956$11369_Y + connect \$9 $not$libresoc.v:180950$11364_Y + connect \$12 $not$libresoc.v:180951$11365_Y + connect \$15 $not$libresoc.v:180952$11366_Y + connect \$1 $not$libresoc.v:180953$11367_Y + connect \$3 $not$libresoc.v:180954$11368_Y + connect \$6 $not$libresoc.v:180955$11369_Y end -attribute \src "libresoc.v:181422.1-181977.10" +attribute \src "libresoc.v:181421.1-181976.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_4" attribute \generator "nMigen" module \reg_4 - attribute \src "libresoc.v:181530.3-181569.6" + attribute \src "libresoc.v:181529.3-181568.6" wire width 4 $0\cr_pred4__data_o$next[3:0]$11484 - attribute \src "libresoc.v:181528.3-181529.49" + attribute \src "libresoc.v:181527.3-181528.49" wire width 4 $0\cr_pred4__data_o[3:0] - attribute \src "libresoc.v:181423.7-181423.20" + attribute \src "libresoc.v:181422.7-181422.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181600.3-181639.6" + attribute \src "libresoc.v:181599.3-181638.6" wire width 4 $0\r24__data_o$next[3:0]$11493 - attribute \src "libresoc.v:181518.3-181519.39" + attribute \src "libresoc.v:181517.3-181518.39" wire width 4 $0\r24__data_o[3:0] - attribute \src "libresoc.v:181907.3-181946.6" + attribute \src "libresoc.v:181906.3-181945.6" wire width 4 $0\r4__data_o$next[3:0]$11555 - attribute \src "libresoc.v:181520.3-181521.37" + attribute \src "libresoc.v:181519.3-181520.37" wire width 4 $0\r4__data_o[3:0] - attribute \src "libresoc.v:181670.3-181696.6" + attribute \src "libresoc.v:181669.3-181695.6" wire width 4 $0\reg$next[3:0]$11507 - attribute \src "libresoc.v:181516.3-181517.25" + attribute \src "libresoc.v:181515.3-181516.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:181697.3-181736.6" + attribute \src "libresoc.v:181696.3-181735.6" wire width 4 $0\src14__data_o$next[3:0]$11513 - attribute \src "libresoc.v:181526.3-181527.43" + attribute \src "libresoc.v:181525.3-181526.43" wire width 4 $0\src14__data_o[3:0] - attribute \src "libresoc.v:181767.3-181806.6" + attribute \src "libresoc.v:181766.3-181805.6" wire width 4 $0\src24__data_o$next[3:0]$11527 - attribute \src "libresoc.v:181524.3-181525.43" + attribute \src "libresoc.v:181523.3-181524.43" wire width 4 $0\src24__data_o[3:0] - attribute \src "libresoc.v:181837.3-181876.6" + attribute \src "libresoc.v:181836.3-181875.6" wire width 4 $0\src34__data_o$next[3:0]$11541 - attribute \src "libresoc.v:181522.3-181523.43" + attribute \src "libresoc.v:181521.3-181522.43" wire width 4 $0\src34__data_o[3:0] - attribute \src "libresoc.v:181877.3-181906.6" + attribute \src "libresoc.v:181876.3-181905.6" wire $0\wr_detect$10[0:0]$11549 - attribute \src "libresoc.v:181947.3-181976.6" + attribute \src "libresoc.v:181946.3-181975.6" wire $0\wr_detect$13[0:0]$11563 - attribute \src "libresoc.v:181640.3-181669.6" + attribute \src "libresoc.v:181639.3-181668.6" wire $0\wr_detect$16[0:0]$11501 - attribute \src "libresoc.v:181737.3-181766.6" + attribute \src "libresoc.v:181736.3-181765.6" wire $0\wr_detect$4[0:0]$11521 - attribute \src "libresoc.v:181807.3-181836.6" + attribute \src "libresoc.v:181806.3-181835.6" wire $0\wr_detect$7[0:0]$11535 - attribute \src "libresoc.v:181570.3-181599.6" + attribute \src "libresoc.v:181569.3-181598.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:181530.3-181569.6" + attribute \src "libresoc.v:181529.3-181568.6" wire width 4 $1\cr_pred4__data_o$next[3:0]$11485 - attribute \src "libresoc.v:181442.13-181442.36" + attribute \src "libresoc.v:181441.13-181441.36" wire width 4 $1\cr_pred4__data_o[3:0] - attribute \src "libresoc.v:181600.3-181639.6" + attribute \src "libresoc.v:181599.3-181638.6" wire width 4 $1\r24__data_o$next[3:0]$11494 - attribute \src "libresoc.v:181457.13-181457.31" + attribute \src "libresoc.v:181456.13-181456.31" wire width 4 $1\r24__data_o[3:0] - attribute \src "libresoc.v:181907.3-181946.6" + attribute \src "libresoc.v:181906.3-181945.6" wire width 4 $1\r4__data_o$next[3:0]$11556 - attribute \src "libresoc.v:181464.13-181464.30" + attribute \src "libresoc.v:181463.13-181463.30" wire width 4 $1\r4__data_o[3:0] - attribute \src "libresoc.v:181670.3-181696.6" + attribute \src "libresoc.v:181669.3-181695.6" wire width 4 $1\reg$next[3:0]$11508 - attribute \src "libresoc.v:181470.13-181470.25" + attribute \src "libresoc.v:181469.13-181469.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:181697.3-181736.6" + attribute \src "libresoc.v:181696.3-181735.6" wire width 4 $1\src14__data_o$next[3:0]$11514 - attribute \src "libresoc.v:181475.13-181475.33" + attribute \src "libresoc.v:181474.13-181474.33" wire width 4 $1\src14__data_o[3:0] - attribute \src "libresoc.v:181767.3-181806.6" + attribute \src "libresoc.v:181766.3-181805.6" wire width 4 $1\src24__data_o$next[3:0]$11528 - attribute \src "libresoc.v:181482.13-181482.33" + attribute \src "libresoc.v:181481.13-181481.33" wire width 4 $1\src24__data_o[3:0] - attribute \src "libresoc.v:181837.3-181876.6" + attribute \src "libresoc.v:181836.3-181875.6" wire width 4 $1\src34__data_o$next[3:0]$11542 - attribute \src "libresoc.v:181489.13-181489.33" + attribute \src "libresoc.v:181488.13-181488.33" wire width 4 $1\src34__data_o[3:0] - attribute \src "libresoc.v:181877.3-181906.6" + attribute \src "libresoc.v:181876.3-181905.6" wire $1\wr_detect$10[0:0]$11550 - attribute \src "libresoc.v:181947.3-181976.6" + attribute \src "libresoc.v:181946.3-181975.6" wire $1\wr_detect$13[0:0]$11564 - attribute \src "libresoc.v:181640.3-181669.6" + attribute \src "libresoc.v:181639.3-181668.6" wire $1\wr_detect$16[0:0]$11502 - attribute \src "libresoc.v:181737.3-181766.6" + attribute \src "libresoc.v:181736.3-181765.6" wire $1\wr_detect$4[0:0]$11522 - attribute \src "libresoc.v:181807.3-181836.6" + attribute \src "libresoc.v:181806.3-181835.6" wire $1\wr_detect$7[0:0]$11536 - attribute \src "libresoc.v:181570.3-181599.6" + attribute \src "libresoc.v:181569.3-181598.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:181530.3-181569.6" + attribute \src "libresoc.v:181529.3-181568.6" wire width 4 $2\cr_pred4__data_o$next[3:0]$11486 - attribute \src "libresoc.v:181600.3-181639.6" + attribute \src "libresoc.v:181599.3-181638.6" wire width 4 $2\r24__data_o$next[3:0]$11495 - attribute \src "libresoc.v:181907.3-181946.6" + attribute \src "libresoc.v:181906.3-181945.6" wire width 4 $2\r4__data_o$next[3:0]$11557 - attribute \src "libresoc.v:181670.3-181696.6" + attribute \src "libresoc.v:181669.3-181695.6" wire width 4 $2\reg$next[3:0]$11509 - attribute \src "libresoc.v:181697.3-181736.6" + attribute \src "libresoc.v:181696.3-181735.6" wire width 4 $2\src14__data_o$next[3:0]$11515 - attribute \src "libresoc.v:181767.3-181806.6" + attribute \src "libresoc.v:181766.3-181805.6" wire width 4 $2\src24__data_o$next[3:0]$11529 - attribute \src "libresoc.v:181837.3-181876.6" + attribute \src "libresoc.v:181836.3-181875.6" wire width 4 $2\src34__data_o$next[3:0]$11543 - attribute \src "libresoc.v:181877.3-181906.6" + attribute \src "libresoc.v:181876.3-181905.6" wire $2\wr_detect$10[0:0]$11551 - attribute \src "libresoc.v:181947.3-181976.6" + attribute \src "libresoc.v:181946.3-181975.6" wire $2\wr_detect$13[0:0]$11565 - attribute \src "libresoc.v:181640.3-181669.6" + attribute \src "libresoc.v:181639.3-181668.6" wire $2\wr_detect$16[0:0]$11503 - attribute \src "libresoc.v:181737.3-181766.6" + attribute \src "libresoc.v:181736.3-181765.6" wire $2\wr_detect$4[0:0]$11523 - attribute \src "libresoc.v:181807.3-181836.6" + attribute \src "libresoc.v:181806.3-181835.6" wire $2\wr_detect$7[0:0]$11537 - attribute \src "libresoc.v:181570.3-181599.6" + attribute \src "libresoc.v:181569.3-181598.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:181530.3-181569.6" + attribute \src "libresoc.v:181529.3-181568.6" wire width 4 $3\cr_pred4__data_o$next[3:0]$11487 - attribute \src "libresoc.v:181600.3-181639.6" + attribute \src "libresoc.v:181599.3-181638.6" wire width 4 $3\r24__data_o$next[3:0]$11496 - attribute \src "libresoc.v:181907.3-181946.6" + attribute \src "libresoc.v:181906.3-181945.6" wire width 4 $3\r4__data_o$next[3:0]$11558 - attribute \src "libresoc.v:181670.3-181696.6" + attribute \src "libresoc.v:181669.3-181695.6" wire width 4 $3\reg$next[3:0]$11510 - attribute \src "libresoc.v:181697.3-181736.6" + attribute \src "libresoc.v:181696.3-181735.6" wire width 4 $3\src14__data_o$next[3:0]$11516 - attribute \src "libresoc.v:181767.3-181806.6" + attribute \src "libresoc.v:181766.3-181805.6" wire width 4 $3\src24__data_o$next[3:0]$11530 - attribute \src "libresoc.v:181837.3-181876.6" + attribute \src "libresoc.v:181836.3-181875.6" wire width 4 $3\src34__data_o$next[3:0]$11544 - attribute \src "libresoc.v:181877.3-181906.6" + attribute \src "libresoc.v:181876.3-181905.6" wire $3\wr_detect$10[0:0]$11552 - attribute \src "libresoc.v:181947.3-181976.6" + attribute \src "libresoc.v:181946.3-181975.6" wire $3\wr_detect$13[0:0]$11566 - attribute \src "libresoc.v:181640.3-181669.6" + attribute \src "libresoc.v:181639.3-181668.6" wire $3\wr_detect$16[0:0]$11504 - attribute \src "libresoc.v:181737.3-181766.6" + attribute \src "libresoc.v:181736.3-181765.6" wire $3\wr_detect$4[0:0]$11524 - attribute \src "libresoc.v:181807.3-181836.6" + attribute \src "libresoc.v:181806.3-181835.6" wire $3\wr_detect$7[0:0]$11538 - attribute \src "libresoc.v:181570.3-181599.6" + attribute \src "libresoc.v:181569.3-181598.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:181530.3-181569.6" + attribute \src "libresoc.v:181529.3-181568.6" wire width 4 $4\cr_pred4__data_o$next[3:0]$11488 - attribute \src "libresoc.v:181600.3-181639.6" + attribute \src "libresoc.v:181599.3-181638.6" wire width 4 $4\r24__data_o$next[3:0]$11497 - attribute \src "libresoc.v:181907.3-181946.6" + attribute \src "libresoc.v:181906.3-181945.6" wire width 4 $4\r4__data_o$next[3:0]$11559 - attribute \src "libresoc.v:181670.3-181696.6" + attribute \src "libresoc.v:181669.3-181695.6" wire width 4 $4\reg$next[3:0]$11511 - attribute \src "libresoc.v:181697.3-181736.6" + attribute \src "libresoc.v:181696.3-181735.6" wire width 4 $4\src14__data_o$next[3:0]$11517 - attribute \src "libresoc.v:181767.3-181806.6" + attribute \src "libresoc.v:181766.3-181805.6" wire width 4 $4\src24__data_o$next[3:0]$11531 - attribute \src "libresoc.v:181837.3-181876.6" + attribute \src "libresoc.v:181836.3-181875.6" wire width 4 $4\src34__data_o$next[3:0]$11545 - attribute \src "libresoc.v:181877.3-181906.6" + attribute \src "libresoc.v:181876.3-181905.6" wire $4\wr_detect$10[0:0]$11553 - attribute \src "libresoc.v:181947.3-181976.6" + attribute \src "libresoc.v:181946.3-181975.6" wire $4\wr_detect$13[0:0]$11567 - attribute \src "libresoc.v:181640.3-181669.6" + attribute \src "libresoc.v:181639.3-181668.6" wire $4\wr_detect$16[0:0]$11505 - attribute \src "libresoc.v:181737.3-181766.6" + attribute \src "libresoc.v:181736.3-181765.6" wire $4\wr_detect$4[0:0]$11525 - attribute \src "libresoc.v:181807.3-181836.6" + attribute \src "libresoc.v:181806.3-181835.6" wire $4\wr_detect$7[0:0]$11539 - attribute \src "libresoc.v:181570.3-181599.6" + attribute \src "libresoc.v:181569.3-181598.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:181530.3-181569.6" + attribute \src "libresoc.v:181529.3-181568.6" wire width 4 $5\cr_pred4__data_o$next[3:0]$11489 - attribute \src "libresoc.v:181600.3-181639.6" + attribute \src "libresoc.v:181599.3-181638.6" wire width 4 $5\r24__data_o$next[3:0]$11498 - attribute \src "libresoc.v:181907.3-181946.6" + attribute \src "libresoc.v:181906.3-181945.6" wire width 4 $5\r4__data_o$next[3:0]$11560 - attribute \src "libresoc.v:181697.3-181736.6" + attribute \src "libresoc.v:181696.3-181735.6" wire width 4 $5\src14__data_o$next[3:0]$11518 - attribute \src "libresoc.v:181767.3-181806.6" + attribute \src "libresoc.v:181766.3-181805.6" wire width 4 $5\src24__data_o$next[3:0]$11532 - attribute \src "libresoc.v:181837.3-181876.6" + attribute \src "libresoc.v:181836.3-181875.6" wire width 4 $5\src34__data_o$next[3:0]$11546 - attribute \src "libresoc.v:181530.3-181569.6" + attribute \src "libresoc.v:181529.3-181568.6" wire width 4 $6\cr_pred4__data_o$next[3:0]$11490 - attribute \src "libresoc.v:181600.3-181639.6" + attribute \src "libresoc.v:181599.3-181638.6" wire width 4 $6\r24__data_o$next[3:0]$11499 - attribute \src "libresoc.v:181907.3-181946.6" + attribute \src "libresoc.v:181906.3-181945.6" wire width 4 $6\r4__data_o$next[3:0]$11561 - attribute \src "libresoc.v:181697.3-181736.6" + attribute \src "libresoc.v:181696.3-181735.6" wire width 4 $6\src14__data_o$next[3:0]$11519 - attribute \src "libresoc.v:181767.3-181806.6" + attribute \src "libresoc.v:181766.3-181805.6" wire width 4 $6\src24__data_o$next[3:0]$11533 - attribute \src "libresoc.v:181837.3-181876.6" + attribute \src "libresoc.v:181836.3-181875.6" wire width 4 $6\src34__data_o$next[3:0]$11547 - attribute \src "libresoc.v:181510.17-181510.104" - wire $not$libresoc.v:181510$11470_Y + attribute \src "libresoc.v:181509.17-181509.104" + wire $not$libresoc.v:181509$11470_Y + attribute \src "libresoc.v:181510.18-181510.105" + wire $not$libresoc.v:181510$11471_Y attribute \src "libresoc.v:181511.18-181511.105" - wire $not$libresoc.v:181511$11471_Y - attribute \src "libresoc.v:181512.18-181512.105" - wire $not$libresoc.v:181512$11472_Y - attribute \src "libresoc.v:181513.17-181513.100" - wire $not$libresoc.v:181513$11473_Y + wire $not$libresoc.v:181511$11472_Y + attribute \src "libresoc.v:181512.17-181512.100" + wire $not$libresoc.v:181512$11473_Y + attribute \src "libresoc.v:181513.17-181513.103" + wire $not$libresoc.v:181513$11474_Y attribute \src "libresoc.v:181514.17-181514.103" - wire $not$libresoc.v:181514$11474_Y - attribute \src "libresoc.v:181515.17-181515.103" - wire $not$libresoc.v:181515$11475_Y + wire $not$libresoc.v:181514$11475_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -373386,7 +370196,7 @@ module \reg_4 wire width 4 input 13 \dest24__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest24__wen - attribute \src "libresoc.v:181423.7-181423.15" + attribute \src "libresoc.v:181422.7-181422.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 16 \r24__data_o @@ -373439,175 +370249,175 @@ module \reg_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181510$11470 + cell $not $not$libresoc.v:181509$11470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:181510$11470_Y + connect \Y $not$libresoc.v:181509$11470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181511$11471 + cell $not $not$libresoc.v:181510$11471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:181511$11471_Y + connect \Y $not$libresoc.v:181510$11471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181512$11472 + cell $not $not$libresoc.v:181511$11472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$16 - connect \Y $not$libresoc.v:181512$11472_Y + connect \Y $not$libresoc.v:181511$11472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181513$11473 + cell $not $not$libresoc.v:181512$11473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:181513$11473_Y + connect \Y $not$libresoc.v:181512$11473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181514$11474 + cell $not $not$libresoc.v:181513$11474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:181514$11474_Y + connect \Y $not$libresoc.v:181513$11474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181515$11475 + cell $not $not$libresoc.v:181514$11475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:181515$11475_Y + connect \Y $not$libresoc.v:181514$11475_Y end - attribute \src "libresoc.v:181423.7-181423.20" - process $proc$libresoc.v:181423$11568 + attribute \src "libresoc.v:181422.7-181422.20" + process $proc$libresoc.v:181422$11568 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181442.13-181442.36" - process $proc$libresoc.v:181442$11569 + attribute \src "libresoc.v:181441.13-181441.36" + process $proc$libresoc.v:181441$11569 assign { } { } assign $1\cr_pred4__data_o[3:0] 4'0000 sync always sync init update \cr_pred4__data_o $1\cr_pred4__data_o[3:0] end - attribute \src "libresoc.v:181457.13-181457.31" - process $proc$libresoc.v:181457$11570 + attribute \src "libresoc.v:181456.13-181456.31" + process $proc$libresoc.v:181456$11570 assign { } { } assign $1\r24__data_o[3:0] 4'0000 sync always sync init update \r24__data_o $1\r24__data_o[3:0] end - attribute \src "libresoc.v:181464.13-181464.30" - process $proc$libresoc.v:181464$11571 + attribute \src "libresoc.v:181463.13-181463.30" + process $proc$libresoc.v:181463$11571 assign { } { } assign $1\r4__data_o[3:0] 4'0000 sync always sync init update \r4__data_o $1\r4__data_o[3:0] end - attribute \src "libresoc.v:181470.13-181470.25" - process $proc$libresoc.v:181470$11572 + attribute \src "libresoc.v:181469.13-181469.25" + process $proc$libresoc.v:181469$11572 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:181475.13-181475.33" - process $proc$libresoc.v:181475$11573 + attribute \src "libresoc.v:181474.13-181474.33" + process $proc$libresoc.v:181474$11573 assign { } { } assign $1\src14__data_o[3:0] 4'0000 sync always sync init update \src14__data_o $1\src14__data_o[3:0] end - attribute \src "libresoc.v:181482.13-181482.33" - process $proc$libresoc.v:181482$11574 + attribute \src "libresoc.v:181481.13-181481.33" + process $proc$libresoc.v:181481$11574 assign { } { } assign $1\src24__data_o[3:0] 4'0000 sync always sync init update \src24__data_o $1\src24__data_o[3:0] end - attribute \src "libresoc.v:181489.13-181489.33" - process $proc$libresoc.v:181489$11575 + attribute \src "libresoc.v:181488.13-181488.33" + process $proc$libresoc.v:181488$11575 assign { } { } assign $1\src34__data_o[3:0] 4'0000 sync always sync init update \src34__data_o $1\src34__data_o[3:0] end - attribute \src "libresoc.v:181516.3-181517.25" - process $proc$libresoc.v:181516$11476 + attribute \src "libresoc.v:181515.3-181516.25" + process $proc$libresoc.v:181515$11476 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:181518.3-181519.39" - process $proc$libresoc.v:181518$11477 + attribute \src "libresoc.v:181517.3-181518.39" + process $proc$libresoc.v:181517$11477 assign { } { } assign $0\r24__data_o[3:0] \r24__data_o$next sync posedge \coresync_clk update \r24__data_o $0\r24__data_o[3:0] end - attribute \src "libresoc.v:181520.3-181521.37" - process $proc$libresoc.v:181520$11478 + attribute \src "libresoc.v:181519.3-181520.37" + process $proc$libresoc.v:181519$11478 assign { } { } assign $0\r4__data_o[3:0] \r4__data_o$next sync posedge \coresync_clk update \r4__data_o $0\r4__data_o[3:0] end - attribute \src "libresoc.v:181522.3-181523.43" - process $proc$libresoc.v:181522$11479 + attribute \src "libresoc.v:181521.3-181522.43" + process $proc$libresoc.v:181521$11479 assign { } { } assign $0\src34__data_o[3:0] \src34__data_o$next sync posedge \coresync_clk update \src34__data_o $0\src34__data_o[3:0] end - attribute \src "libresoc.v:181524.3-181525.43" - process $proc$libresoc.v:181524$11480 + attribute \src "libresoc.v:181523.3-181524.43" + process $proc$libresoc.v:181523$11480 assign { } { } assign $0\src24__data_o[3:0] \src24__data_o$next sync posedge \coresync_clk update \src24__data_o $0\src24__data_o[3:0] end - attribute \src "libresoc.v:181526.3-181527.43" - process $proc$libresoc.v:181526$11481 + attribute \src "libresoc.v:181525.3-181526.43" + process $proc$libresoc.v:181525$11481 assign { } { } assign $0\src14__data_o[3:0] \src14__data_o$next sync posedge \coresync_clk update \src14__data_o $0\src14__data_o[3:0] end - attribute \src "libresoc.v:181528.3-181529.49" - process $proc$libresoc.v:181528$11482 + attribute \src "libresoc.v:181527.3-181528.49" + process $proc$libresoc.v:181527$11482 assign { } { } assign $0\cr_pred4__data_o[3:0] \cr_pred4__data_o$next sync posedge \coresync_clk update \cr_pred4__data_o $0\cr_pred4__data_o[3:0] end - attribute \src "libresoc.v:181530.3-181569.6" - process $proc$libresoc.v:181530$11483 + attribute \src "libresoc.v:181529.3-181568.6" + process $proc$libresoc.v:181529$11483 assign { } { } assign { } { } assign { } { } assign $0\cr_pred4__data_o$next[3:0]$11484 $6\cr_pred4__data_o$next[3:0]$11490 - attribute \src "libresoc.v:181531.5-181531.29" + attribute \src "libresoc.v:181530.5-181530.29" switch \initial - attribute \src "libresoc.v:181531.9-181531.17" + attribute \src "libresoc.v:181530.9-181530.17" case 1'1 case end @@ -373671,14 +370481,14 @@ module \reg_4 sync always update \cr_pred4__data_o$next $0\cr_pred4__data_o$next[3:0]$11484 end - attribute \src "libresoc.v:181570.3-181599.6" - process $proc$libresoc.v:181570$11491 + attribute \src "libresoc.v:181569.3-181598.6" + process $proc$libresoc.v:181569$11491 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:181571.5-181571.29" + attribute \src "libresoc.v:181570.5-181570.29" switch \initial - attribute \src "libresoc.v:181571.9-181571.17" + attribute \src "libresoc.v:181570.9-181570.17" case 1'1 case end @@ -373724,15 +370534,15 @@ module \reg_4 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:181600.3-181639.6" - process $proc$libresoc.v:181600$11492 + attribute \src "libresoc.v:181599.3-181638.6" + process $proc$libresoc.v:181599$11492 assign { } { } assign { } { } assign { } { } assign $0\r24__data_o$next[3:0]$11493 $6\r24__data_o$next[3:0]$11499 - attribute \src "libresoc.v:181601.5-181601.29" + attribute \src "libresoc.v:181600.5-181600.29" switch \initial - attribute \src "libresoc.v:181601.9-181601.17" + attribute \src "libresoc.v:181600.9-181600.17" case 1'1 case end @@ -373796,14 +370606,14 @@ module \reg_4 sync always update \r24__data_o$next $0\r24__data_o$next[3:0]$11493 end - attribute \src "libresoc.v:181640.3-181669.6" - process $proc$libresoc.v:181640$11500 + attribute \src "libresoc.v:181639.3-181668.6" + process $proc$libresoc.v:181639$11500 assign { } { } assign { } { } assign $0\wr_detect$16[0:0]$11501 $1\wr_detect$16[0:0]$11502 - attribute \src "libresoc.v:181641.5-181641.29" + attribute \src "libresoc.v:181640.5-181640.29" switch \initial - attribute \src "libresoc.v:181641.9-181641.17" + attribute \src "libresoc.v:181640.9-181640.17" case 1'1 case end @@ -373849,17 +370659,17 @@ module \reg_4 sync always update \wr_detect$16 $0\wr_detect$16[0:0]$11501 end - attribute \src "libresoc.v:181670.3-181696.6" - process $proc$libresoc.v:181670$11506 + attribute \src "libresoc.v:181669.3-181695.6" + process $proc$libresoc.v:181669$11506 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[3:0]$11507 $4\reg$next[3:0]$11511 - attribute \src "libresoc.v:181671.5-181671.29" + attribute \src "libresoc.v:181670.5-181670.29" switch \initial - attribute \src "libresoc.v:181671.9-181671.17" + attribute \src "libresoc.v:181670.9-181670.17" case 1'1 case end @@ -373902,15 +370712,15 @@ module \reg_4 sync always update \reg$next $0\reg$next[3:0]$11507 end - attribute \src "libresoc.v:181697.3-181736.6" - process $proc$libresoc.v:181697$11512 + attribute \src "libresoc.v:181696.3-181735.6" + process $proc$libresoc.v:181696$11512 assign { } { } assign { } { } assign { } { } assign $0\src14__data_o$next[3:0]$11513 $6\src14__data_o$next[3:0]$11519 - attribute \src "libresoc.v:181698.5-181698.29" + attribute \src "libresoc.v:181697.5-181697.29" switch \initial - attribute \src "libresoc.v:181698.9-181698.17" + attribute \src "libresoc.v:181697.9-181697.17" case 1'1 case end @@ -373974,14 +370784,14 @@ module \reg_4 sync always update \src14__data_o$next $0\src14__data_o$next[3:0]$11513 end - attribute \src "libresoc.v:181737.3-181766.6" - process $proc$libresoc.v:181737$11520 + attribute \src "libresoc.v:181736.3-181765.6" + process $proc$libresoc.v:181736$11520 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11521 $1\wr_detect$4[0:0]$11522 - attribute \src "libresoc.v:181738.5-181738.29" + attribute \src "libresoc.v:181737.5-181737.29" switch \initial - attribute \src "libresoc.v:181738.9-181738.17" + attribute \src "libresoc.v:181737.9-181737.17" case 1'1 case end @@ -374027,15 +370837,15 @@ module \reg_4 sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11521 end - attribute \src "libresoc.v:181767.3-181806.6" - process $proc$libresoc.v:181767$11526 + attribute \src "libresoc.v:181766.3-181805.6" + process $proc$libresoc.v:181766$11526 assign { } { } assign { } { } assign { } { } assign $0\src24__data_o$next[3:0]$11527 $6\src24__data_o$next[3:0]$11533 - attribute \src "libresoc.v:181768.5-181768.29" + attribute \src "libresoc.v:181767.5-181767.29" switch \initial - attribute \src "libresoc.v:181768.9-181768.17" + attribute \src "libresoc.v:181767.9-181767.17" case 1'1 case end @@ -374099,14 +370909,14 @@ module \reg_4 sync always update \src24__data_o$next $0\src24__data_o$next[3:0]$11527 end - attribute \src "libresoc.v:181807.3-181836.6" - process $proc$libresoc.v:181807$11534 + attribute \src "libresoc.v:181806.3-181835.6" + process $proc$libresoc.v:181806$11534 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11535 $1\wr_detect$7[0:0]$11536 - attribute \src "libresoc.v:181808.5-181808.29" + attribute \src "libresoc.v:181807.5-181807.29" switch \initial - attribute \src "libresoc.v:181808.9-181808.17" + attribute \src "libresoc.v:181807.9-181807.17" case 1'1 case end @@ -374152,15 +370962,15 @@ module \reg_4 sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11535 end - attribute \src "libresoc.v:181837.3-181876.6" - process $proc$libresoc.v:181837$11540 + attribute \src "libresoc.v:181836.3-181875.6" + process $proc$libresoc.v:181836$11540 assign { } { } assign { } { } assign { } { } assign $0\src34__data_o$next[3:0]$11541 $6\src34__data_o$next[3:0]$11547 - attribute \src "libresoc.v:181838.5-181838.29" + attribute \src "libresoc.v:181837.5-181837.29" switch \initial - attribute \src "libresoc.v:181838.9-181838.17" + attribute \src "libresoc.v:181837.9-181837.17" case 1'1 case end @@ -374224,14 +371034,14 @@ module \reg_4 sync always update \src34__data_o$next $0\src34__data_o$next[3:0]$11541 end - attribute \src "libresoc.v:181877.3-181906.6" - process $proc$libresoc.v:181877$11548 + attribute \src "libresoc.v:181876.3-181905.6" + process $proc$libresoc.v:181876$11548 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$11549 $1\wr_detect$10[0:0]$11550 - attribute \src "libresoc.v:181878.5-181878.29" + attribute \src "libresoc.v:181877.5-181877.29" switch \initial - attribute \src "libresoc.v:181878.9-181878.17" + attribute \src "libresoc.v:181877.9-181877.17" case 1'1 case end @@ -374277,15 +371087,15 @@ module \reg_4 sync always update \wr_detect$10 $0\wr_detect$10[0:0]$11549 end - attribute \src "libresoc.v:181907.3-181946.6" - process $proc$libresoc.v:181907$11554 + attribute \src "libresoc.v:181906.3-181945.6" + process $proc$libresoc.v:181906$11554 assign { } { } assign { } { } assign { } { } assign $0\r4__data_o$next[3:0]$11555 $6\r4__data_o$next[3:0]$11561 - attribute \src "libresoc.v:181908.5-181908.29" + attribute \src "libresoc.v:181907.5-181907.29" switch \initial - attribute \src "libresoc.v:181908.9-181908.17" + attribute \src "libresoc.v:181907.9-181907.17" case 1'1 case end @@ -374349,14 +371159,14 @@ module \reg_4 sync always update \r4__data_o$next $0\r4__data_o$next[3:0]$11555 end - attribute \src "libresoc.v:181947.3-181976.6" - process $proc$libresoc.v:181947$11562 + attribute \src "libresoc.v:181946.3-181975.6" + process $proc$libresoc.v:181946$11562 assign { } { } assign { } { } assign $0\wr_detect$13[0:0]$11563 $1\wr_detect$13[0:0]$11564 - attribute \src "libresoc.v:181948.5-181948.29" + attribute \src "libresoc.v:181947.5-181947.29" switch \initial - attribute \src "libresoc.v:181948.9-181948.17" + attribute \src "libresoc.v:181947.9-181947.17" case 1'1 case end @@ -374402,214 +371212,214 @@ module \reg_4 sync always update \wr_detect$13 $0\wr_detect$13[0:0]$11563 end - connect \$9 $not$libresoc.v:181510$11470_Y - connect \$12 $not$libresoc.v:181511$11471_Y - connect \$15 $not$libresoc.v:181512$11472_Y - connect \$1 $not$libresoc.v:181513$11473_Y - connect \$3 $not$libresoc.v:181514$11474_Y - connect \$6 $not$libresoc.v:181515$11475_Y + connect \$9 $not$libresoc.v:181509$11470_Y + connect \$12 $not$libresoc.v:181510$11471_Y + connect \$15 $not$libresoc.v:181511$11472_Y + connect \$1 $not$libresoc.v:181512$11473_Y + connect \$3 $not$libresoc.v:181513$11474_Y + connect \$6 $not$libresoc.v:181514$11475_Y end -attribute \src "libresoc.v:181981.1-182536.10" +attribute \src "libresoc.v:181980.1-182535.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_5" attribute \generator "nMigen" module \reg_5 - attribute \src "libresoc.v:182089.3-182128.6" + attribute \src "libresoc.v:182088.3-182127.6" wire width 4 $0\cr_pred5__data_o$next[3:0]$11590 - attribute \src "libresoc.v:182087.3-182088.49" + attribute \src "libresoc.v:182086.3-182087.49" wire width 4 $0\cr_pred5__data_o[3:0] - attribute \src "libresoc.v:181982.7-181982.20" + attribute \src "libresoc.v:181981.7-181981.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182159.3-182198.6" + attribute \src "libresoc.v:182158.3-182197.6" wire width 4 $0\r25__data_o$next[3:0]$11599 - attribute \src "libresoc.v:182077.3-182078.39" + attribute \src "libresoc.v:182076.3-182077.39" wire width 4 $0\r25__data_o[3:0] - attribute \src "libresoc.v:182466.3-182505.6" + attribute \src "libresoc.v:182465.3-182504.6" wire width 4 $0\r5__data_o$next[3:0]$11661 - attribute \src "libresoc.v:182079.3-182080.37" + attribute \src "libresoc.v:182078.3-182079.37" wire width 4 $0\r5__data_o[3:0] - attribute \src "libresoc.v:182229.3-182255.6" + attribute \src "libresoc.v:182228.3-182254.6" wire width 4 $0\reg$next[3:0]$11613 - attribute \src "libresoc.v:182075.3-182076.25" + attribute \src "libresoc.v:182074.3-182075.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:182256.3-182295.6" + attribute \src "libresoc.v:182255.3-182294.6" wire width 4 $0\src15__data_o$next[3:0]$11619 - attribute \src "libresoc.v:182085.3-182086.43" + attribute \src "libresoc.v:182084.3-182085.43" wire width 4 $0\src15__data_o[3:0] - attribute \src "libresoc.v:182326.3-182365.6" + attribute \src "libresoc.v:182325.3-182364.6" wire width 4 $0\src25__data_o$next[3:0]$11633 - attribute \src "libresoc.v:182083.3-182084.43" + attribute \src "libresoc.v:182082.3-182083.43" wire width 4 $0\src25__data_o[3:0] - attribute \src "libresoc.v:182396.3-182435.6" + attribute \src "libresoc.v:182395.3-182434.6" wire width 4 $0\src35__data_o$next[3:0]$11647 - attribute \src "libresoc.v:182081.3-182082.43" + attribute \src "libresoc.v:182080.3-182081.43" wire width 4 $0\src35__data_o[3:0] - attribute \src "libresoc.v:182436.3-182465.6" + attribute \src "libresoc.v:182435.3-182464.6" wire $0\wr_detect$10[0:0]$11655 - attribute \src "libresoc.v:182506.3-182535.6" + attribute \src "libresoc.v:182505.3-182534.6" wire $0\wr_detect$13[0:0]$11669 - attribute \src "libresoc.v:182199.3-182228.6" + attribute \src "libresoc.v:182198.3-182227.6" wire $0\wr_detect$16[0:0]$11607 - attribute \src "libresoc.v:182296.3-182325.6" + attribute \src "libresoc.v:182295.3-182324.6" wire $0\wr_detect$4[0:0]$11627 - attribute \src "libresoc.v:182366.3-182395.6" + attribute \src "libresoc.v:182365.3-182394.6" wire $0\wr_detect$7[0:0]$11641 - attribute \src "libresoc.v:182129.3-182158.6" + attribute \src "libresoc.v:182128.3-182157.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:182089.3-182128.6" + attribute \src "libresoc.v:182088.3-182127.6" wire width 4 $1\cr_pred5__data_o$next[3:0]$11591 - attribute \src "libresoc.v:182001.13-182001.36" + attribute \src "libresoc.v:182000.13-182000.36" wire width 4 $1\cr_pred5__data_o[3:0] - attribute \src "libresoc.v:182159.3-182198.6" + attribute \src "libresoc.v:182158.3-182197.6" wire width 4 $1\r25__data_o$next[3:0]$11600 - attribute \src "libresoc.v:182016.13-182016.31" + attribute \src "libresoc.v:182015.13-182015.31" wire width 4 $1\r25__data_o[3:0] - attribute \src "libresoc.v:182466.3-182505.6" + attribute \src "libresoc.v:182465.3-182504.6" wire width 4 $1\r5__data_o$next[3:0]$11662 - attribute \src "libresoc.v:182023.13-182023.30" + attribute \src "libresoc.v:182022.13-182022.30" wire width 4 $1\r5__data_o[3:0] - attribute \src "libresoc.v:182229.3-182255.6" + attribute \src "libresoc.v:182228.3-182254.6" wire width 4 $1\reg$next[3:0]$11614 - attribute \src "libresoc.v:182029.13-182029.25" + attribute \src "libresoc.v:182028.13-182028.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:182256.3-182295.6" + attribute \src "libresoc.v:182255.3-182294.6" wire width 4 $1\src15__data_o$next[3:0]$11620 - attribute \src "libresoc.v:182034.13-182034.33" + attribute \src "libresoc.v:182033.13-182033.33" wire width 4 $1\src15__data_o[3:0] - attribute \src "libresoc.v:182326.3-182365.6" + attribute \src "libresoc.v:182325.3-182364.6" wire width 4 $1\src25__data_o$next[3:0]$11634 - attribute \src "libresoc.v:182041.13-182041.33" + attribute \src "libresoc.v:182040.13-182040.33" wire width 4 $1\src25__data_o[3:0] - attribute \src "libresoc.v:182396.3-182435.6" + attribute \src "libresoc.v:182395.3-182434.6" wire width 4 $1\src35__data_o$next[3:0]$11648 - attribute \src "libresoc.v:182048.13-182048.33" + attribute \src "libresoc.v:182047.13-182047.33" wire width 4 $1\src35__data_o[3:0] - attribute \src "libresoc.v:182436.3-182465.6" + attribute \src "libresoc.v:182435.3-182464.6" wire $1\wr_detect$10[0:0]$11656 - attribute \src "libresoc.v:182506.3-182535.6" + attribute \src "libresoc.v:182505.3-182534.6" wire $1\wr_detect$13[0:0]$11670 - attribute \src "libresoc.v:182199.3-182228.6" + attribute \src "libresoc.v:182198.3-182227.6" wire $1\wr_detect$16[0:0]$11608 - attribute \src "libresoc.v:182296.3-182325.6" + attribute \src "libresoc.v:182295.3-182324.6" wire $1\wr_detect$4[0:0]$11628 - attribute \src "libresoc.v:182366.3-182395.6" + attribute \src "libresoc.v:182365.3-182394.6" wire $1\wr_detect$7[0:0]$11642 - attribute \src "libresoc.v:182129.3-182158.6" + attribute \src "libresoc.v:182128.3-182157.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:182089.3-182128.6" + attribute \src "libresoc.v:182088.3-182127.6" wire width 4 $2\cr_pred5__data_o$next[3:0]$11592 - attribute \src "libresoc.v:182159.3-182198.6" + attribute \src "libresoc.v:182158.3-182197.6" wire width 4 $2\r25__data_o$next[3:0]$11601 - attribute \src "libresoc.v:182466.3-182505.6" + attribute \src "libresoc.v:182465.3-182504.6" wire width 4 $2\r5__data_o$next[3:0]$11663 - attribute \src "libresoc.v:182229.3-182255.6" + attribute \src "libresoc.v:182228.3-182254.6" wire width 4 $2\reg$next[3:0]$11615 - attribute \src "libresoc.v:182256.3-182295.6" + attribute \src "libresoc.v:182255.3-182294.6" wire width 4 $2\src15__data_o$next[3:0]$11621 - attribute \src "libresoc.v:182326.3-182365.6" + attribute \src "libresoc.v:182325.3-182364.6" wire width 4 $2\src25__data_o$next[3:0]$11635 - attribute \src "libresoc.v:182396.3-182435.6" + attribute \src "libresoc.v:182395.3-182434.6" wire width 4 $2\src35__data_o$next[3:0]$11649 - attribute \src "libresoc.v:182436.3-182465.6" + attribute \src "libresoc.v:182435.3-182464.6" wire $2\wr_detect$10[0:0]$11657 - attribute \src "libresoc.v:182506.3-182535.6" + attribute \src "libresoc.v:182505.3-182534.6" wire $2\wr_detect$13[0:0]$11671 - attribute \src "libresoc.v:182199.3-182228.6" + attribute \src "libresoc.v:182198.3-182227.6" wire $2\wr_detect$16[0:0]$11609 - attribute \src "libresoc.v:182296.3-182325.6" + attribute \src "libresoc.v:182295.3-182324.6" wire $2\wr_detect$4[0:0]$11629 - attribute \src "libresoc.v:182366.3-182395.6" + attribute \src "libresoc.v:182365.3-182394.6" wire $2\wr_detect$7[0:0]$11643 - attribute \src "libresoc.v:182129.3-182158.6" + attribute \src "libresoc.v:182128.3-182157.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:182089.3-182128.6" + attribute \src "libresoc.v:182088.3-182127.6" wire width 4 $3\cr_pred5__data_o$next[3:0]$11593 - attribute \src "libresoc.v:182159.3-182198.6" + attribute \src "libresoc.v:182158.3-182197.6" wire width 4 $3\r25__data_o$next[3:0]$11602 - attribute \src "libresoc.v:182466.3-182505.6" + attribute \src "libresoc.v:182465.3-182504.6" wire width 4 $3\r5__data_o$next[3:0]$11664 - attribute \src "libresoc.v:182229.3-182255.6" + attribute \src "libresoc.v:182228.3-182254.6" wire width 4 $3\reg$next[3:0]$11616 - attribute \src "libresoc.v:182256.3-182295.6" + attribute \src "libresoc.v:182255.3-182294.6" wire width 4 $3\src15__data_o$next[3:0]$11622 - attribute \src "libresoc.v:182326.3-182365.6" + attribute \src "libresoc.v:182325.3-182364.6" wire width 4 $3\src25__data_o$next[3:0]$11636 - attribute \src "libresoc.v:182396.3-182435.6" + attribute \src "libresoc.v:182395.3-182434.6" wire width 4 $3\src35__data_o$next[3:0]$11650 - attribute \src "libresoc.v:182436.3-182465.6" + attribute \src "libresoc.v:182435.3-182464.6" wire $3\wr_detect$10[0:0]$11658 - attribute \src "libresoc.v:182506.3-182535.6" + attribute \src "libresoc.v:182505.3-182534.6" wire $3\wr_detect$13[0:0]$11672 - attribute \src "libresoc.v:182199.3-182228.6" + attribute \src "libresoc.v:182198.3-182227.6" wire $3\wr_detect$16[0:0]$11610 - attribute \src "libresoc.v:182296.3-182325.6" + attribute \src "libresoc.v:182295.3-182324.6" wire $3\wr_detect$4[0:0]$11630 - attribute \src "libresoc.v:182366.3-182395.6" + attribute \src "libresoc.v:182365.3-182394.6" wire $3\wr_detect$7[0:0]$11644 - attribute \src "libresoc.v:182129.3-182158.6" + attribute \src "libresoc.v:182128.3-182157.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:182089.3-182128.6" + attribute \src "libresoc.v:182088.3-182127.6" wire width 4 $4\cr_pred5__data_o$next[3:0]$11594 - attribute \src "libresoc.v:182159.3-182198.6" + attribute \src "libresoc.v:182158.3-182197.6" wire width 4 $4\r25__data_o$next[3:0]$11603 - attribute \src "libresoc.v:182466.3-182505.6" + attribute \src "libresoc.v:182465.3-182504.6" wire width 4 $4\r5__data_o$next[3:0]$11665 - attribute \src "libresoc.v:182229.3-182255.6" + attribute \src "libresoc.v:182228.3-182254.6" wire width 4 $4\reg$next[3:0]$11617 - attribute \src "libresoc.v:182256.3-182295.6" + attribute \src "libresoc.v:182255.3-182294.6" wire width 4 $4\src15__data_o$next[3:0]$11623 - attribute \src "libresoc.v:182326.3-182365.6" + attribute \src "libresoc.v:182325.3-182364.6" wire width 4 $4\src25__data_o$next[3:0]$11637 - attribute \src "libresoc.v:182396.3-182435.6" + attribute \src "libresoc.v:182395.3-182434.6" wire width 4 $4\src35__data_o$next[3:0]$11651 - attribute \src "libresoc.v:182436.3-182465.6" + attribute \src "libresoc.v:182435.3-182464.6" wire $4\wr_detect$10[0:0]$11659 - attribute \src "libresoc.v:182506.3-182535.6" + attribute \src "libresoc.v:182505.3-182534.6" wire $4\wr_detect$13[0:0]$11673 - attribute \src "libresoc.v:182199.3-182228.6" + attribute \src "libresoc.v:182198.3-182227.6" wire $4\wr_detect$16[0:0]$11611 - attribute \src "libresoc.v:182296.3-182325.6" + attribute \src "libresoc.v:182295.3-182324.6" wire $4\wr_detect$4[0:0]$11631 - attribute \src "libresoc.v:182366.3-182395.6" + attribute \src "libresoc.v:182365.3-182394.6" wire $4\wr_detect$7[0:0]$11645 - attribute \src "libresoc.v:182129.3-182158.6" + attribute \src "libresoc.v:182128.3-182157.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:182089.3-182128.6" + attribute \src "libresoc.v:182088.3-182127.6" wire width 4 $5\cr_pred5__data_o$next[3:0]$11595 - attribute \src "libresoc.v:182159.3-182198.6" + attribute \src "libresoc.v:182158.3-182197.6" wire width 4 $5\r25__data_o$next[3:0]$11604 - attribute \src "libresoc.v:182466.3-182505.6" + attribute \src "libresoc.v:182465.3-182504.6" wire width 4 $5\r5__data_o$next[3:0]$11666 - attribute \src "libresoc.v:182256.3-182295.6" + attribute \src "libresoc.v:182255.3-182294.6" wire width 4 $5\src15__data_o$next[3:0]$11624 - attribute \src "libresoc.v:182326.3-182365.6" + attribute \src "libresoc.v:182325.3-182364.6" wire width 4 $5\src25__data_o$next[3:0]$11638 - attribute \src "libresoc.v:182396.3-182435.6" + attribute \src "libresoc.v:182395.3-182434.6" wire width 4 $5\src35__data_o$next[3:0]$11652 - attribute \src "libresoc.v:182089.3-182128.6" + attribute \src "libresoc.v:182088.3-182127.6" wire width 4 $6\cr_pred5__data_o$next[3:0]$11596 - attribute \src "libresoc.v:182159.3-182198.6" + attribute \src "libresoc.v:182158.3-182197.6" wire width 4 $6\r25__data_o$next[3:0]$11605 - attribute \src "libresoc.v:182466.3-182505.6" + attribute \src "libresoc.v:182465.3-182504.6" wire width 4 $6\r5__data_o$next[3:0]$11667 - attribute \src "libresoc.v:182256.3-182295.6" + attribute \src "libresoc.v:182255.3-182294.6" wire width 4 $6\src15__data_o$next[3:0]$11625 - attribute \src "libresoc.v:182326.3-182365.6" + attribute \src "libresoc.v:182325.3-182364.6" wire width 4 $6\src25__data_o$next[3:0]$11639 - attribute \src "libresoc.v:182396.3-182435.6" + attribute \src "libresoc.v:182395.3-182434.6" wire width 4 $6\src35__data_o$next[3:0]$11653 - attribute \src "libresoc.v:182069.17-182069.104" - wire $not$libresoc.v:182069$11576_Y + attribute \src "libresoc.v:182068.17-182068.104" + wire $not$libresoc.v:182068$11576_Y + attribute \src "libresoc.v:182069.18-182069.105" + wire $not$libresoc.v:182069$11577_Y attribute \src "libresoc.v:182070.18-182070.105" - wire $not$libresoc.v:182070$11577_Y - attribute \src "libresoc.v:182071.18-182071.105" - wire $not$libresoc.v:182071$11578_Y - attribute \src "libresoc.v:182072.17-182072.100" - wire $not$libresoc.v:182072$11579_Y + wire $not$libresoc.v:182070$11578_Y + attribute \src "libresoc.v:182071.17-182071.100" + wire $not$libresoc.v:182071$11579_Y + attribute \src "libresoc.v:182072.17-182072.103" + wire $not$libresoc.v:182072$11580_Y attribute \src "libresoc.v:182073.17-182073.103" - wire $not$libresoc.v:182073$11580_Y - attribute \src "libresoc.v:182074.17-182074.103" - wire $not$libresoc.v:182074$11581_Y + wire $not$libresoc.v:182073$11581_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -374640,7 +371450,7 @@ module \reg_5 wire width 4 input 13 \dest25__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest25__wen - attribute \src "libresoc.v:181982.7-181982.15" + attribute \src "libresoc.v:181981.7-181981.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 16 \r25__data_o @@ -374693,175 +371503,175 @@ module \reg_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182069$11576 + cell $not $not$libresoc.v:182068$11576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:182069$11576_Y + connect \Y $not$libresoc.v:182068$11576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182070$11577 + cell $not $not$libresoc.v:182069$11577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:182070$11577_Y + connect \Y $not$libresoc.v:182069$11577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182071$11578 + cell $not $not$libresoc.v:182070$11578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$16 - connect \Y $not$libresoc.v:182071$11578_Y + connect \Y $not$libresoc.v:182070$11578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182072$11579 + cell $not $not$libresoc.v:182071$11579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:182072$11579_Y + connect \Y $not$libresoc.v:182071$11579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182073$11580 + cell $not $not$libresoc.v:182072$11580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:182073$11580_Y + connect \Y $not$libresoc.v:182072$11580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182074$11581 + cell $not $not$libresoc.v:182073$11581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:182074$11581_Y + connect \Y $not$libresoc.v:182073$11581_Y end - attribute \src "libresoc.v:181982.7-181982.20" - process $proc$libresoc.v:181982$11674 + attribute \src "libresoc.v:181981.7-181981.20" + process $proc$libresoc.v:181981$11674 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182001.13-182001.36" - process $proc$libresoc.v:182001$11675 + attribute \src "libresoc.v:182000.13-182000.36" + process $proc$libresoc.v:182000$11675 assign { } { } assign $1\cr_pred5__data_o[3:0] 4'0000 sync always sync init update \cr_pred5__data_o $1\cr_pred5__data_o[3:0] end - attribute \src "libresoc.v:182016.13-182016.31" - process $proc$libresoc.v:182016$11676 + attribute \src "libresoc.v:182015.13-182015.31" + process $proc$libresoc.v:182015$11676 assign { } { } assign $1\r25__data_o[3:0] 4'0000 sync always sync init update \r25__data_o $1\r25__data_o[3:0] end - attribute \src "libresoc.v:182023.13-182023.30" - process $proc$libresoc.v:182023$11677 + attribute \src "libresoc.v:182022.13-182022.30" + process $proc$libresoc.v:182022$11677 assign { } { } assign $1\r5__data_o[3:0] 4'0000 sync always sync init update \r5__data_o $1\r5__data_o[3:0] end - attribute \src "libresoc.v:182029.13-182029.25" - process $proc$libresoc.v:182029$11678 + attribute \src "libresoc.v:182028.13-182028.25" + process $proc$libresoc.v:182028$11678 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:182034.13-182034.33" - process $proc$libresoc.v:182034$11679 + attribute \src "libresoc.v:182033.13-182033.33" + process $proc$libresoc.v:182033$11679 assign { } { } assign $1\src15__data_o[3:0] 4'0000 sync always sync init update \src15__data_o $1\src15__data_o[3:0] end - attribute \src "libresoc.v:182041.13-182041.33" - process $proc$libresoc.v:182041$11680 + attribute \src "libresoc.v:182040.13-182040.33" + process $proc$libresoc.v:182040$11680 assign { } { } assign $1\src25__data_o[3:0] 4'0000 sync always sync init update \src25__data_o $1\src25__data_o[3:0] end - attribute \src "libresoc.v:182048.13-182048.33" - process $proc$libresoc.v:182048$11681 + attribute \src "libresoc.v:182047.13-182047.33" + process $proc$libresoc.v:182047$11681 assign { } { } assign $1\src35__data_o[3:0] 4'0000 sync always sync init update \src35__data_o $1\src35__data_o[3:0] end - attribute \src "libresoc.v:182075.3-182076.25" - process $proc$libresoc.v:182075$11582 + attribute \src "libresoc.v:182074.3-182075.25" + process $proc$libresoc.v:182074$11582 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:182077.3-182078.39" - process $proc$libresoc.v:182077$11583 + attribute \src "libresoc.v:182076.3-182077.39" + process $proc$libresoc.v:182076$11583 assign { } { } assign $0\r25__data_o[3:0] \r25__data_o$next sync posedge \coresync_clk update \r25__data_o $0\r25__data_o[3:0] end - attribute \src "libresoc.v:182079.3-182080.37" - process $proc$libresoc.v:182079$11584 + attribute \src "libresoc.v:182078.3-182079.37" + process $proc$libresoc.v:182078$11584 assign { } { } assign $0\r5__data_o[3:0] \r5__data_o$next sync posedge \coresync_clk update \r5__data_o $0\r5__data_o[3:0] end - attribute \src "libresoc.v:182081.3-182082.43" - process $proc$libresoc.v:182081$11585 + attribute \src "libresoc.v:182080.3-182081.43" + process $proc$libresoc.v:182080$11585 assign { } { } assign $0\src35__data_o[3:0] \src35__data_o$next sync posedge \coresync_clk update \src35__data_o $0\src35__data_o[3:0] end - attribute \src "libresoc.v:182083.3-182084.43" - process $proc$libresoc.v:182083$11586 + attribute \src "libresoc.v:182082.3-182083.43" + process $proc$libresoc.v:182082$11586 assign { } { } assign $0\src25__data_o[3:0] \src25__data_o$next sync posedge \coresync_clk update \src25__data_o $0\src25__data_o[3:0] end - attribute \src "libresoc.v:182085.3-182086.43" - process $proc$libresoc.v:182085$11587 + attribute \src "libresoc.v:182084.3-182085.43" + process $proc$libresoc.v:182084$11587 assign { } { } assign $0\src15__data_o[3:0] \src15__data_o$next sync posedge \coresync_clk update \src15__data_o $0\src15__data_o[3:0] end - attribute \src "libresoc.v:182087.3-182088.49" - process $proc$libresoc.v:182087$11588 + attribute \src "libresoc.v:182086.3-182087.49" + process $proc$libresoc.v:182086$11588 assign { } { } assign $0\cr_pred5__data_o[3:0] \cr_pred5__data_o$next sync posedge \coresync_clk update \cr_pred5__data_o $0\cr_pred5__data_o[3:0] end - attribute \src "libresoc.v:182089.3-182128.6" - process $proc$libresoc.v:182089$11589 + attribute \src "libresoc.v:182088.3-182127.6" + process $proc$libresoc.v:182088$11589 assign { } { } assign { } { } assign { } { } assign $0\cr_pred5__data_o$next[3:0]$11590 $6\cr_pred5__data_o$next[3:0]$11596 - attribute \src "libresoc.v:182090.5-182090.29" + attribute \src "libresoc.v:182089.5-182089.29" switch \initial - attribute \src "libresoc.v:182090.9-182090.17" + attribute \src "libresoc.v:182089.9-182089.17" case 1'1 case end @@ -374925,14 +371735,14 @@ module \reg_5 sync always update \cr_pred5__data_o$next $0\cr_pred5__data_o$next[3:0]$11590 end - attribute \src "libresoc.v:182129.3-182158.6" - process $proc$libresoc.v:182129$11597 + attribute \src "libresoc.v:182128.3-182157.6" + process $proc$libresoc.v:182128$11597 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:182130.5-182130.29" + attribute \src "libresoc.v:182129.5-182129.29" switch \initial - attribute \src "libresoc.v:182130.9-182130.17" + attribute \src "libresoc.v:182129.9-182129.17" case 1'1 case end @@ -374978,15 +371788,15 @@ module \reg_5 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:182159.3-182198.6" - process $proc$libresoc.v:182159$11598 + attribute \src "libresoc.v:182158.3-182197.6" + process $proc$libresoc.v:182158$11598 assign { } { } assign { } { } assign { } { } assign $0\r25__data_o$next[3:0]$11599 $6\r25__data_o$next[3:0]$11605 - attribute \src "libresoc.v:182160.5-182160.29" + attribute \src "libresoc.v:182159.5-182159.29" switch \initial - attribute \src "libresoc.v:182160.9-182160.17" + attribute \src "libresoc.v:182159.9-182159.17" case 1'1 case end @@ -375050,14 +371860,14 @@ module \reg_5 sync always update \r25__data_o$next $0\r25__data_o$next[3:0]$11599 end - attribute \src "libresoc.v:182199.3-182228.6" - process $proc$libresoc.v:182199$11606 + attribute \src "libresoc.v:182198.3-182227.6" + process $proc$libresoc.v:182198$11606 assign { } { } assign { } { } assign $0\wr_detect$16[0:0]$11607 $1\wr_detect$16[0:0]$11608 - attribute \src "libresoc.v:182200.5-182200.29" + attribute \src "libresoc.v:182199.5-182199.29" switch \initial - attribute \src "libresoc.v:182200.9-182200.17" + attribute \src "libresoc.v:182199.9-182199.17" case 1'1 case end @@ -375103,17 +371913,17 @@ module \reg_5 sync always update \wr_detect$16 $0\wr_detect$16[0:0]$11607 end - attribute \src "libresoc.v:182229.3-182255.6" - process $proc$libresoc.v:182229$11612 + attribute \src "libresoc.v:182228.3-182254.6" + process $proc$libresoc.v:182228$11612 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[3:0]$11613 $4\reg$next[3:0]$11617 - attribute \src "libresoc.v:182230.5-182230.29" + attribute \src "libresoc.v:182229.5-182229.29" switch \initial - attribute \src "libresoc.v:182230.9-182230.17" + attribute \src "libresoc.v:182229.9-182229.17" case 1'1 case end @@ -375156,15 +371966,15 @@ module \reg_5 sync always update \reg$next $0\reg$next[3:0]$11613 end - attribute \src "libresoc.v:182256.3-182295.6" - process $proc$libresoc.v:182256$11618 + attribute \src "libresoc.v:182255.3-182294.6" + process $proc$libresoc.v:182255$11618 assign { } { } assign { } { } assign { } { } assign $0\src15__data_o$next[3:0]$11619 $6\src15__data_o$next[3:0]$11625 - attribute \src "libresoc.v:182257.5-182257.29" + attribute \src "libresoc.v:182256.5-182256.29" switch \initial - attribute \src "libresoc.v:182257.9-182257.17" + attribute \src "libresoc.v:182256.9-182256.17" case 1'1 case end @@ -375228,14 +372038,14 @@ module \reg_5 sync always update \src15__data_o$next $0\src15__data_o$next[3:0]$11619 end - attribute \src "libresoc.v:182296.3-182325.6" - process $proc$libresoc.v:182296$11626 + attribute \src "libresoc.v:182295.3-182324.6" + process $proc$libresoc.v:182295$11626 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11627 $1\wr_detect$4[0:0]$11628 - attribute \src "libresoc.v:182297.5-182297.29" + attribute \src "libresoc.v:182296.5-182296.29" switch \initial - attribute \src "libresoc.v:182297.9-182297.17" + attribute \src "libresoc.v:182296.9-182296.17" case 1'1 case end @@ -375281,15 +372091,15 @@ module \reg_5 sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11627 end - attribute \src "libresoc.v:182326.3-182365.6" - process $proc$libresoc.v:182326$11632 + attribute \src "libresoc.v:182325.3-182364.6" + process $proc$libresoc.v:182325$11632 assign { } { } assign { } { } assign { } { } assign $0\src25__data_o$next[3:0]$11633 $6\src25__data_o$next[3:0]$11639 - attribute \src "libresoc.v:182327.5-182327.29" + attribute \src "libresoc.v:182326.5-182326.29" switch \initial - attribute \src "libresoc.v:182327.9-182327.17" + attribute \src "libresoc.v:182326.9-182326.17" case 1'1 case end @@ -375353,14 +372163,14 @@ module \reg_5 sync always update \src25__data_o$next $0\src25__data_o$next[3:0]$11633 end - attribute \src "libresoc.v:182366.3-182395.6" - process $proc$libresoc.v:182366$11640 + attribute \src "libresoc.v:182365.3-182394.6" + process $proc$libresoc.v:182365$11640 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11641 $1\wr_detect$7[0:0]$11642 - attribute \src "libresoc.v:182367.5-182367.29" + attribute \src "libresoc.v:182366.5-182366.29" switch \initial - attribute \src "libresoc.v:182367.9-182367.17" + attribute \src "libresoc.v:182366.9-182366.17" case 1'1 case end @@ -375406,15 +372216,15 @@ module \reg_5 sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11641 end - attribute \src "libresoc.v:182396.3-182435.6" - process $proc$libresoc.v:182396$11646 + attribute \src "libresoc.v:182395.3-182434.6" + process $proc$libresoc.v:182395$11646 assign { } { } assign { } { } assign { } { } assign $0\src35__data_o$next[3:0]$11647 $6\src35__data_o$next[3:0]$11653 - attribute \src "libresoc.v:182397.5-182397.29" + attribute \src "libresoc.v:182396.5-182396.29" switch \initial - attribute \src "libresoc.v:182397.9-182397.17" + attribute \src "libresoc.v:182396.9-182396.17" case 1'1 case end @@ -375478,14 +372288,14 @@ module \reg_5 sync always update \src35__data_o$next $0\src35__data_o$next[3:0]$11647 end - attribute \src "libresoc.v:182436.3-182465.6" - process $proc$libresoc.v:182436$11654 + attribute \src "libresoc.v:182435.3-182464.6" + process $proc$libresoc.v:182435$11654 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$11655 $1\wr_detect$10[0:0]$11656 - attribute \src "libresoc.v:182437.5-182437.29" + attribute \src "libresoc.v:182436.5-182436.29" switch \initial - attribute \src "libresoc.v:182437.9-182437.17" + attribute \src "libresoc.v:182436.9-182436.17" case 1'1 case end @@ -375531,15 +372341,15 @@ module \reg_5 sync always update \wr_detect$10 $0\wr_detect$10[0:0]$11655 end - attribute \src "libresoc.v:182466.3-182505.6" - process $proc$libresoc.v:182466$11660 + attribute \src "libresoc.v:182465.3-182504.6" + process $proc$libresoc.v:182465$11660 assign { } { } assign { } { } assign { } { } assign $0\r5__data_o$next[3:0]$11661 $6\r5__data_o$next[3:0]$11667 - attribute \src "libresoc.v:182467.5-182467.29" + attribute \src "libresoc.v:182466.5-182466.29" switch \initial - attribute \src "libresoc.v:182467.9-182467.17" + attribute \src "libresoc.v:182466.9-182466.17" case 1'1 case end @@ -375603,14 +372413,14 @@ module \reg_5 sync always update \r5__data_o$next $0\r5__data_o$next[3:0]$11661 end - attribute \src "libresoc.v:182506.3-182535.6" - process $proc$libresoc.v:182506$11668 + attribute \src "libresoc.v:182505.3-182534.6" + process $proc$libresoc.v:182505$11668 assign { } { } assign { } { } assign $0\wr_detect$13[0:0]$11669 $1\wr_detect$13[0:0]$11670 - attribute \src "libresoc.v:182507.5-182507.29" + attribute \src "libresoc.v:182506.5-182506.29" switch \initial - attribute \src "libresoc.v:182507.9-182507.17" + attribute \src "libresoc.v:182506.9-182506.17" case 1'1 case end @@ -375656,214 +372466,214 @@ module \reg_5 sync always update \wr_detect$13 $0\wr_detect$13[0:0]$11669 end - connect \$9 $not$libresoc.v:182069$11576_Y - connect \$12 $not$libresoc.v:182070$11577_Y - connect \$15 $not$libresoc.v:182071$11578_Y - connect \$1 $not$libresoc.v:182072$11579_Y - connect \$3 $not$libresoc.v:182073$11580_Y - connect \$6 $not$libresoc.v:182074$11581_Y + connect \$9 $not$libresoc.v:182068$11576_Y + connect \$12 $not$libresoc.v:182069$11577_Y + connect \$15 $not$libresoc.v:182070$11578_Y + connect \$1 $not$libresoc.v:182071$11579_Y + connect \$3 $not$libresoc.v:182072$11580_Y + connect \$6 $not$libresoc.v:182073$11581_Y end -attribute \src "libresoc.v:182540.1-183095.10" +attribute \src "libresoc.v:182539.1-183094.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_6" attribute \generator "nMigen" module \reg_6 - attribute \src "libresoc.v:182648.3-182687.6" + attribute \src "libresoc.v:182647.3-182686.6" wire width 4 $0\cr_pred6__data_o$next[3:0]$11696 - attribute \src "libresoc.v:182646.3-182647.49" + attribute \src "libresoc.v:182645.3-182646.49" wire width 4 $0\cr_pred6__data_o[3:0] - attribute \src "libresoc.v:182541.7-182541.20" + attribute \src "libresoc.v:182540.7-182540.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182718.3-182757.6" + attribute \src "libresoc.v:182717.3-182756.6" wire width 4 $0\r26__data_o$next[3:0]$11705 - attribute \src "libresoc.v:182636.3-182637.39" + attribute \src "libresoc.v:182635.3-182636.39" wire width 4 $0\r26__data_o[3:0] - attribute \src "libresoc.v:183025.3-183064.6" + attribute \src "libresoc.v:183024.3-183063.6" wire width 4 $0\r6__data_o$next[3:0]$11767 - attribute \src "libresoc.v:182638.3-182639.37" + attribute \src "libresoc.v:182637.3-182638.37" wire width 4 $0\r6__data_o[3:0] - attribute \src "libresoc.v:182788.3-182814.6" + attribute \src "libresoc.v:182787.3-182813.6" wire width 4 $0\reg$next[3:0]$11719 - attribute \src "libresoc.v:182634.3-182635.25" + attribute \src "libresoc.v:182633.3-182634.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:182815.3-182854.6" + attribute \src "libresoc.v:182814.3-182853.6" wire width 4 $0\src16__data_o$next[3:0]$11725 - attribute \src "libresoc.v:182644.3-182645.43" + attribute \src "libresoc.v:182643.3-182644.43" wire width 4 $0\src16__data_o[3:0] - attribute \src "libresoc.v:182885.3-182924.6" + attribute \src "libresoc.v:182884.3-182923.6" wire width 4 $0\src26__data_o$next[3:0]$11739 - attribute \src "libresoc.v:182642.3-182643.43" + attribute \src "libresoc.v:182641.3-182642.43" wire width 4 $0\src26__data_o[3:0] - attribute \src "libresoc.v:182955.3-182994.6" + attribute \src "libresoc.v:182954.3-182993.6" wire width 4 $0\src36__data_o$next[3:0]$11753 - attribute \src "libresoc.v:182640.3-182641.43" + attribute \src "libresoc.v:182639.3-182640.43" wire width 4 $0\src36__data_o[3:0] - attribute \src "libresoc.v:182995.3-183024.6" + attribute \src "libresoc.v:182994.3-183023.6" wire $0\wr_detect$10[0:0]$11761 - attribute \src "libresoc.v:183065.3-183094.6" + attribute \src "libresoc.v:183064.3-183093.6" wire $0\wr_detect$13[0:0]$11775 - attribute \src "libresoc.v:182758.3-182787.6" + attribute \src "libresoc.v:182757.3-182786.6" wire $0\wr_detect$16[0:0]$11713 - attribute \src "libresoc.v:182855.3-182884.6" + attribute \src "libresoc.v:182854.3-182883.6" wire $0\wr_detect$4[0:0]$11733 - attribute \src "libresoc.v:182925.3-182954.6" + attribute \src "libresoc.v:182924.3-182953.6" wire $0\wr_detect$7[0:0]$11747 - attribute \src "libresoc.v:182688.3-182717.6" + attribute \src "libresoc.v:182687.3-182716.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:182648.3-182687.6" + attribute \src "libresoc.v:182647.3-182686.6" wire width 4 $1\cr_pred6__data_o$next[3:0]$11697 - attribute \src "libresoc.v:182560.13-182560.36" + attribute \src "libresoc.v:182559.13-182559.36" wire width 4 $1\cr_pred6__data_o[3:0] - attribute \src "libresoc.v:182718.3-182757.6" + attribute \src "libresoc.v:182717.3-182756.6" wire width 4 $1\r26__data_o$next[3:0]$11706 - attribute \src "libresoc.v:182575.13-182575.31" + attribute \src "libresoc.v:182574.13-182574.31" wire width 4 $1\r26__data_o[3:0] - attribute \src "libresoc.v:183025.3-183064.6" + attribute \src "libresoc.v:183024.3-183063.6" wire width 4 $1\r6__data_o$next[3:0]$11768 - attribute \src "libresoc.v:182582.13-182582.30" + attribute \src "libresoc.v:182581.13-182581.30" wire width 4 $1\r6__data_o[3:0] - attribute \src "libresoc.v:182788.3-182814.6" + attribute \src "libresoc.v:182787.3-182813.6" wire width 4 $1\reg$next[3:0]$11720 - attribute \src "libresoc.v:182588.13-182588.25" + attribute \src "libresoc.v:182587.13-182587.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:182815.3-182854.6" + attribute \src "libresoc.v:182814.3-182853.6" wire width 4 $1\src16__data_o$next[3:0]$11726 - attribute \src "libresoc.v:182593.13-182593.33" + attribute \src "libresoc.v:182592.13-182592.33" wire width 4 $1\src16__data_o[3:0] - attribute \src "libresoc.v:182885.3-182924.6" + attribute \src "libresoc.v:182884.3-182923.6" wire width 4 $1\src26__data_o$next[3:0]$11740 - attribute \src "libresoc.v:182600.13-182600.33" + attribute \src "libresoc.v:182599.13-182599.33" wire width 4 $1\src26__data_o[3:0] - attribute \src "libresoc.v:182955.3-182994.6" + attribute \src "libresoc.v:182954.3-182993.6" wire width 4 $1\src36__data_o$next[3:0]$11754 - attribute \src "libresoc.v:182607.13-182607.33" + attribute \src "libresoc.v:182606.13-182606.33" wire width 4 $1\src36__data_o[3:0] - attribute \src "libresoc.v:182995.3-183024.6" + attribute \src "libresoc.v:182994.3-183023.6" wire $1\wr_detect$10[0:0]$11762 - attribute \src "libresoc.v:183065.3-183094.6" + attribute \src "libresoc.v:183064.3-183093.6" wire $1\wr_detect$13[0:0]$11776 - attribute \src "libresoc.v:182758.3-182787.6" + attribute \src "libresoc.v:182757.3-182786.6" wire $1\wr_detect$16[0:0]$11714 - attribute \src "libresoc.v:182855.3-182884.6" + attribute \src "libresoc.v:182854.3-182883.6" wire $1\wr_detect$4[0:0]$11734 - attribute \src "libresoc.v:182925.3-182954.6" + attribute \src "libresoc.v:182924.3-182953.6" wire $1\wr_detect$7[0:0]$11748 - attribute \src "libresoc.v:182688.3-182717.6" + attribute \src "libresoc.v:182687.3-182716.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:182648.3-182687.6" + attribute \src "libresoc.v:182647.3-182686.6" wire width 4 $2\cr_pred6__data_o$next[3:0]$11698 - attribute \src "libresoc.v:182718.3-182757.6" + attribute \src "libresoc.v:182717.3-182756.6" wire width 4 $2\r26__data_o$next[3:0]$11707 - attribute \src "libresoc.v:183025.3-183064.6" + attribute \src "libresoc.v:183024.3-183063.6" wire width 4 $2\r6__data_o$next[3:0]$11769 - attribute \src "libresoc.v:182788.3-182814.6" + attribute \src "libresoc.v:182787.3-182813.6" wire width 4 $2\reg$next[3:0]$11721 - attribute \src "libresoc.v:182815.3-182854.6" + attribute \src "libresoc.v:182814.3-182853.6" wire width 4 $2\src16__data_o$next[3:0]$11727 - attribute \src "libresoc.v:182885.3-182924.6" + attribute \src "libresoc.v:182884.3-182923.6" wire width 4 $2\src26__data_o$next[3:0]$11741 - attribute \src "libresoc.v:182955.3-182994.6" + attribute \src "libresoc.v:182954.3-182993.6" wire width 4 $2\src36__data_o$next[3:0]$11755 - attribute \src "libresoc.v:182995.3-183024.6" + attribute \src "libresoc.v:182994.3-183023.6" wire $2\wr_detect$10[0:0]$11763 - attribute \src "libresoc.v:183065.3-183094.6" + attribute \src "libresoc.v:183064.3-183093.6" wire $2\wr_detect$13[0:0]$11777 - attribute \src "libresoc.v:182758.3-182787.6" + attribute \src "libresoc.v:182757.3-182786.6" wire $2\wr_detect$16[0:0]$11715 - attribute \src "libresoc.v:182855.3-182884.6" + attribute \src "libresoc.v:182854.3-182883.6" wire $2\wr_detect$4[0:0]$11735 - attribute \src "libresoc.v:182925.3-182954.6" + attribute \src "libresoc.v:182924.3-182953.6" wire $2\wr_detect$7[0:0]$11749 - attribute \src "libresoc.v:182688.3-182717.6" + attribute \src "libresoc.v:182687.3-182716.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:182648.3-182687.6" + attribute \src "libresoc.v:182647.3-182686.6" wire width 4 $3\cr_pred6__data_o$next[3:0]$11699 - attribute \src "libresoc.v:182718.3-182757.6" + attribute \src "libresoc.v:182717.3-182756.6" wire width 4 $3\r26__data_o$next[3:0]$11708 - attribute \src "libresoc.v:183025.3-183064.6" + attribute \src "libresoc.v:183024.3-183063.6" wire width 4 $3\r6__data_o$next[3:0]$11770 - attribute \src "libresoc.v:182788.3-182814.6" + attribute \src "libresoc.v:182787.3-182813.6" wire width 4 $3\reg$next[3:0]$11722 - attribute \src "libresoc.v:182815.3-182854.6" + attribute \src "libresoc.v:182814.3-182853.6" wire width 4 $3\src16__data_o$next[3:0]$11728 - attribute \src "libresoc.v:182885.3-182924.6" + attribute \src "libresoc.v:182884.3-182923.6" wire width 4 $3\src26__data_o$next[3:0]$11742 - attribute \src "libresoc.v:182955.3-182994.6" + attribute \src "libresoc.v:182954.3-182993.6" wire width 4 $3\src36__data_o$next[3:0]$11756 - attribute \src "libresoc.v:182995.3-183024.6" + attribute \src "libresoc.v:182994.3-183023.6" wire $3\wr_detect$10[0:0]$11764 - attribute \src "libresoc.v:183065.3-183094.6" + attribute \src "libresoc.v:183064.3-183093.6" wire $3\wr_detect$13[0:0]$11778 - attribute \src "libresoc.v:182758.3-182787.6" + attribute \src "libresoc.v:182757.3-182786.6" wire $3\wr_detect$16[0:0]$11716 - attribute \src "libresoc.v:182855.3-182884.6" + attribute \src "libresoc.v:182854.3-182883.6" wire $3\wr_detect$4[0:0]$11736 - attribute \src "libresoc.v:182925.3-182954.6" + attribute \src "libresoc.v:182924.3-182953.6" wire $3\wr_detect$7[0:0]$11750 - attribute \src "libresoc.v:182688.3-182717.6" + attribute \src "libresoc.v:182687.3-182716.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:182648.3-182687.6" + attribute \src "libresoc.v:182647.3-182686.6" wire width 4 $4\cr_pred6__data_o$next[3:0]$11700 - attribute \src "libresoc.v:182718.3-182757.6" + attribute \src "libresoc.v:182717.3-182756.6" wire width 4 $4\r26__data_o$next[3:0]$11709 - attribute \src "libresoc.v:183025.3-183064.6" + attribute \src "libresoc.v:183024.3-183063.6" wire width 4 $4\r6__data_o$next[3:0]$11771 - attribute \src "libresoc.v:182788.3-182814.6" + attribute \src "libresoc.v:182787.3-182813.6" wire width 4 $4\reg$next[3:0]$11723 - attribute \src "libresoc.v:182815.3-182854.6" + attribute \src "libresoc.v:182814.3-182853.6" wire width 4 $4\src16__data_o$next[3:0]$11729 - attribute \src "libresoc.v:182885.3-182924.6" + attribute \src "libresoc.v:182884.3-182923.6" wire width 4 $4\src26__data_o$next[3:0]$11743 - attribute \src "libresoc.v:182955.3-182994.6" + attribute \src "libresoc.v:182954.3-182993.6" wire width 4 $4\src36__data_o$next[3:0]$11757 - attribute \src "libresoc.v:182995.3-183024.6" + attribute \src "libresoc.v:182994.3-183023.6" wire $4\wr_detect$10[0:0]$11765 - attribute \src "libresoc.v:183065.3-183094.6" + attribute \src "libresoc.v:183064.3-183093.6" wire $4\wr_detect$13[0:0]$11779 - attribute \src "libresoc.v:182758.3-182787.6" + attribute \src "libresoc.v:182757.3-182786.6" wire $4\wr_detect$16[0:0]$11717 - attribute \src "libresoc.v:182855.3-182884.6" + attribute \src "libresoc.v:182854.3-182883.6" wire $4\wr_detect$4[0:0]$11737 - attribute \src "libresoc.v:182925.3-182954.6" + attribute \src "libresoc.v:182924.3-182953.6" wire $4\wr_detect$7[0:0]$11751 - attribute \src "libresoc.v:182688.3-182717.6" + attribute \src "libresoc.v:182687.3-182716.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:182648.3-182687.6" + attribute \src "libresoc.v:182647.3-182686.6" wire width 4 $5\cr_pred6__data_o$next[3:0]$11701 - attribute \src "libresoc.v:182718.3-182757.6" + attribute \src "libresoc.v:182717.3-182756.6" wire width 4 $5\r26__data_o$next[3:0]$11710 - attribute \src "libresoc.v:183025.3-183064.6" + attribute \src "libresoc.v:183024.3-183063.6" wire width 4 $5\r6__data_o$next[3:0]$11772 - attribute \src "libresoc.v:182815.3-182854.6" + attribute \src "libresoc.v:182814.3-182853.6" wire width 4 $5\src16__data_o$next[3:0]$11730 - attribute \src "libresoc.v:182885.3-182924.6" + attribute \src "libresoc.v:182884.3-182923.6" wire width 4 $5\src26__data_o$next[3:0]$11744 - attribute \src "libresoc.v:182955.3-182994.6" + attribute \src "libresoc.v:182954.3-182993.6" wire width 4 $5\src36__data_o$next[3:0]$11758 - attribute \src "libresoc.v:182648.3-182687.6" + attribute \src "libresoc.v:182647.3-182686.6" wire width 4 $6\cr_pred6__data_o$next[3:0]$11702 - attribute \src "libresoc.v:182718.3-182757.6" + attribute \src "libresoc.v:182717.3-182756.6" wire width 4 $6\r26__data_o$next[3:0]$11711 - attribute \src "libresoc.v:183025.3-183064.6" + attribute \src "libresoc.v:183024.3-183063.6" wire width 4 $6\r6__data_o$next[3:0]$11773 - attribute \src "libresoc.v:182815.3-182854.6" + attribute \src "libresoc.v:182814.3-182853.6" wire width 4 $6\src16__data_o$next[3:0]$11731 - attribute \src "libresoc.v:182885.3-182924.6" + attribute \src "libresoc.v:182884.3-182923.6" wire width 4 $6\src26__data_o$next[3:0]$11745 - attribute \src "libresoc.v:182955.3-182994.6" + attribute \src "libresoc.v:182954.3-182993.6" wire width 4 $6\src36__data_o$next[3:0]$11759 - attribute \src "libresoc.v:182628.17-182628.104" - wire $not$libresoc.v:182628$11682_Y + attribute \src "libresoc.v:182627.17-182627.104" + wire $not$libresoc.v:182627$11682_Y + attribute \src "libresoc.v:182628.18-182628.105" + wire $not$libresoc.v:182628$11683_Y attribute \src "libresoc.v:182629.18-182629.105" - wire $not$libresoc.v:182629$11683_Y - attribute \src "libresoc.v:182630.18-182630.105" - wire $not$libresoc.v:182630$11684_Y - attribute \src "libresoc.v:182631.17-182631.100" - wire $not$libresoc.v:182631$11685_Y + wire $not$libresoc.v:182629$11684_Y + attribute \src "libresoc.v:182630.17-182630.100" + wire $not$libresoc.v:182630$11685_Y + attribute \src "libresoc.v:182631.17-182631.103" + wire $not$libresoc.v:182631$11686_Y attribute \src "libresoc.v:182632.17-182632.103" - wire $not$libresoc.v:182632$11686_Y - attribute \src "libresoc.v:182633.17-182633.103" - wire $not$libresoc.v:182633$11687_Y + wire $not$libresoc.v:182632$11687_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -375894,7 +372704,7 @@ module \reg_6 wire width 4 input 13 \dest26__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest26__wen - attribute \src "libresoc.v:182541.7-182541.15" + attribute \src "libresoc.v:182540.7-182540.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 16 \r26__data_o @@ -375947,175 +372757,175 @@ module \reg_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182628$11682 + cell $not $not$libresoc.v:182627$11682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:182628$11682_Y + connect \Y $not$libresoc.v:182627$11682_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182629$11683 + cell $not $not$libresoc.v:182628$11683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:182629$11683_Y + connect \Y $not$libresoc.v:182628$11683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182630$11684 + cell $not $not$libresoc.v:182629$11684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$16 - connect \Y $not$libresoc.v:182630$11684_Y + connect \Y $not$libresoc.v:182629$11684_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182631$11685 + cell $not $not$libresoc.v:182630$11685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:182631$11685_Y + connect \Y $not$libresoc.v:182630$11685_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182632$11686 + cell $not $not$libresoc.v:182631$11686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:182632$11686_Y + connect \Y $not$libresoc.v:182631$11686_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182633$11687 + cell $not $not$libresoc.v:182632$11687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:182633$11687_Y + connect \Y $not$libresoc.v:182632$11687_Y end - attribute \src "libresoc.v:182541.7-182541.20" - process $proc$libresoc.v:182541$11780 + attribute \src "libresoc.v:182540.7-182540.20" + process $proc$libresoc.v:182540$11780 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182560.13-182560.36" - process $proc$libresoc.v:182560$11781 + attribute \src "libresoc.v:182559.13-182559.36" + process $proc$libresoc.v:182559$11781 assign { } { } assign $1\cr_pred6__data_o[3:0] 4'0000 sync always sync init update \cr_pred6__data_o $1\cr_pred6__data_o[3:0] end - attribute \src "libresoc.v:182575.13-182575.31" - process $proc$libresoc.v:182575$11782 + attribute \src "libresoc.v:182574.13-182574.31" + process $proc$libresoc.v:182574$11782 assign { } { } assign $1\r26__data_o[3:0] 4'0000 sync always sync init update \r26__data_o $1\r26__data_o[3:0] end - attribute \src "libresoc.v:182582.13-182582.30" - process $proc$libresoc.v:182582$11783 + attribute \src "libresoc.v:182581.13-182581.30" + process $proc$libresoc.v:182581$11783 assign { } { } assign $1\r6__data_o[3:0] 4'0000 sync always sync init update \r6__data_o $1\r6__data_o[3:0] end - attribute \src "libresoc.v:182588.13-182588.25" - process $proc$libresoc.v:182588$11784 + attribute \src "libresoc.v:182587.13-182587.25" + process $proc$libresoc.v:182587$11784 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:182593.13-182593.33" - process $proc$libresoc.v:182593$11785 + attribute \src "libresoc.v:182592.13-182592.33" + process $proc$libresoc.v:182592$11785 assign { } { } assign $1\src16__data_o[3:0] 4'0000 sync always sync init update \src16__data_o $1\src16__data_o[3:0] end - attribute \src "libresoc.v:182600.13-182600.33" - process $proc$libresoc.v:182600$11786 + attribute \src "libresoc.v:182599.13-182599.33" + process $proc$libresoc.v:182599$11786 assign { } { } assign $1\src26__data_o[3:0] 4'0000 sync always sync init update \src26__data_o $1\src26__data_o[3:0] end - attribute \src "libresoc.v:182607.13-182607.33" - process $proc$libresoc.v:182607$11787 + attribute \src "libresoc.v:182606.13-182606.33" + process $proc$libresoc.v:182606$11787 assign { } { } assign $1\src36__data_o[3:0] 4'0000 sync always sync init update \src36__data_o $1\src36__data_o[3:0] end - attribute \src "libresoc.v:182634.3-182635.25" - process $proc$libresoc.v:182634$11688 + attribute \src "libresoc.v:182633.3-182634.25" + process $proc$libresoc.v:182633$11688 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:182636.3-182637.39" - process $proc$libresoc.v:182636$11689 + attribute \src "libresoc.v:182635.3-182636.39" + process $proc$libresoc.v:182635$11689 assign { } { } assign $0\r26__data_o[3:0] \r26__data_o$next sync posedge \coresync_clk update \r26__data_o $0\r26__data_o[3:0] end - attribute \src "libresoc.v:182638.3-182639.37" - process $proc$libresoc.v:182638$11690 + attribute \src "libresoc.v:182637.3-182638.37" + process $proc$libresoc.v:182637$11690 assign { } { } assign $0\r6__data_o[3:0] \r6__data_o$next sync posedge \coresync_clk update \r6__data_o $0\r6__data_o[3:0] end - attribute \src "libresoc.v:182640.3-182641.43" - process $proc$libresoc.v:182640$11691 + attribute \src "libresoc.v:182639.3-182640.43" + process $proc$libresoc.v:182639$11691 assign { } { } assign $0\src36__data_o[3:0] \src36__data_o$next sync posedge \coresync_clk update \src36__data_o $0\src36__data_o[3:0] end - attribute \src "libresoc.v:182642.3-182643.43" - process $proc$libresoc.v:182642$11692 + attribute \src "libresoc.v:182641.3-182642.43" + process $proc$libresoc.v:182641$11692 assign { } { } assign $0\src26__data_o[3:0] \src26__data_o$next sync posedge \coresync_clk update \src26__data_o $0\src26__data_o[3:0] end - attribute \src "libresoc.v:182644.3-182645.43" - process $proc$libresoc.v:182644$11693 + attribute \src "libresoc.v:182643.3-182644.43" + process $proc$libresoc.v:182643$11693 assign { } { } assign $0\src16__data_o[3:0] \src16__data_o$next sync posedge \coresync_clk update \src16__data_o $0\src16__data_o[3:0] end - attribute \src "libresoc.v:182646.3-182647.49" - process $proc$libresoc.v:182646$11694 + attribute \src "libresoc.v:182645.3-182646.49" + process $proc$libresoc.v:182645$11694 assign { } { } assign $0\cr_pred6__data_o[3:0] \cr_pred6__data_o$next sync posedge \coresync_clk update \cr_pred6__data_o $0\cr_pred6__data_o[3:0] end - attribute \src "libresoc.v:182648.3-182687.6" - process $proc$libresoc.v:182648$11695 + attribute \src "libresoc.v:182647.3-182686.6" + process $proc$libresoc.v:182647$11695 assign { } { } assign { } { } assign { } { } assign $0\cr_pred6__data_o$next[3:0]$11696 $6\cr_pred6__data_o$next[3:0]$11702 - attribute \src "libresoc.v:182649.5-182649.29" + attribute \src "libresoc.v:182648.5-182648.29" switch \initial - attribute \src "libresoc.v:182649.9-182649.17" + attribute \src "libresoc.v:182648.9-182648.17" case 1'1 case end @@ -376179,14 +372989,14 @@ module \reg_6 sync always update \cr_pred6__data_o$next $0\cr_pred6__data_o$next[3:0]$11696 end - attribute \src "libresoc.v:182688.3-182717.6" - process $proc$libresoc.v:182688$11703 + attribute \src "libresoc.v:182687.3-182716.6" + process $proc$libresoc.v:182687$11703 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:182689.5-182689.29" + attribute \src "libresoc.v:182688.5-182688.29" switch \initial - attribute \src "libresoc.v:182689.9-182689.17" + attribute \src "libresoc.v:182688.9-182688.17" case 1'1 case end @@ -376232,15 +373042,15 @@ module \reg_6 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:182718.3-182757.6" - process $proc$libresoc.v:182718$11704 + attribute \src "libresoc.v:182717.3-182756.6" + process $proc$libresoc.v:182717$11704 assign { } { } assign { } { } assign { } { } assign $0\r26__data_o$next[3:0]$11705 $6\r26__data_o$next[3:0]$11711 - attribute \src "libresoc.v:182719.5-182719.29" + attribute \src "libresoc.v:182718.5-182718.29" switch \initial - attribute \src "libresoc.v:182719.9-182719.17" + attribute \src "libresoc.v:182718.9-182718.17" case 1'1 case end @@ -376304,14 +373114,14 @@ module \reg_6 sync always update \r26__data_o$next $0\r26__data_o$next[3:0]$11705 end - attribute \src "libresoc.v:182758.3-182787.6" - process $proc$libresoc.v:182758$11712 + attribute \src "libresoc.v:182757.3-182786.6" + process $proc$libresoc.v:182757$11712 assign { } { } assign { } { } assign $0\wr_detect$16[0:0]$11713 $1\wr_detect$16[0:0]$11714 - attribute \src "libresoc.v:182759.5-182759.29" + attribute \src "libresoc.v:182758.5-182758.29" switch \initial - attribute \src "libresoc.v:182759.9-182759.17" + attribute \src "libresoc.v:182758.9-182758.17" case 1'1 case end @@ -376357,17 +373167,17 @@ module \reg_6 sync always update \wr_detect$16 $0\wr_detect$16[0:0]$11713 end - attribute \src "libresoc.v:182788.3-182814.6" - process $proc$libresoc.v:182788$11718 + attribute \src "libresoc.v:182787.3-182813.6" + process $proc$libresoc.v:182787$11718 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[3:0]$11719 $4\reg$next[3:0]$11723 - attribute \src "libresoc.v:182789.5-182789.29" + attribute \src "libresoc.v:182788.5-182788.29" switch \initial - attribute \src "libresoc.v:182789.9-182789.17" + attribute \src "libresoc.v:182788.9-182788.17" case 1'1 case end @@ -376410,15 +373220,15 @@ module \reg_6 sync always update \reg$next $0\reg$next[3:0]$11719 end - attribute \src "libresoc.v:182815.3-182854.6" - process $proc$libresoc.v:182815$11724 + attribute \src "libresoc.v:182814.3-182853.6" + process $proc$libresoc.v:182814$11724 assign { } { } assign { } { } assign { } { } assign $0\src16__data_o$next[3:0]$11725 $6\src16__data_o$next[3:0]$11731 - attribute \src "libresoc.v:182816.5-182816.29" + attribute \src "libresoc.v:182815.5-182815.29" switch \initial - attribute \src "libresoc.v:182816.9-182816.17" + attribute \src "libresoc.v:182815.9-182815.17" case 1'1 case end @@ -376482,14 +373292,14 @@ module \reg_6 sync always update \src16__data_o$next $0\src16__data_o$next[3:0]$11725 end - attribute \src "libresoc.v:182855.3-182884.6" - process $proc$libresoc.v:182855$11732 + attribute \src "libresoc.v:182854.3-182883.6" + process $proc$libresoc.v:182854$11732 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11733 $1\wr_detect$4[0:0]$11734 - attribute \src "libresoc.v:182856.5-182856.29" + attribute \src "libresoc.v:182855.5-182855.29" switch \initial - attribute \src "libresoc.v:182856.9-182856.17" + attribute \src "libresoc.v:182855.9-182855.17" case 1'1 case end @@ -376535,15 +373345,15 @@ module \reg_6 sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11733 end - attribute \src "libresoc.v:182885.3-182924.6" - process $proc$libresoc.v:182885$11738 + attribute \src "libresoc.v:182884.3-182923.6" + process $proc$libresoc.v:182884$11738 assign { } { } assign { } { } assign { } { } assign $0\src26__data_o$next[3:0]$11739 $6\src26__data_o$next[3:0]$11745 - attribute \src "libresoc.v:182886.5-182886.29" + attribute \src "libresoc.v:182885.5-182885.29" switch \initial - attribute \src "libresoc.v:182886.9-182886.17" + attribute \src "libresoc.v:182885.9-182885.17" case 1'1 case end @@ -376607,14 +373417,14 @@ module \reg_6 sync always update \src26__data_o$next $0\src26__data_o$next[3:0]$11739 end - attribute \src "libresoc.v:182925.3-182954.6" - process $proc$libresoc.v:182925$11746 + attribute \src "libresoc.v:182924.3-182953.6" + process $proc$libresoc.v:182924$11746 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11747 $1\wr_detect$7[0:0]$11748 - attribute \src "libresoc.v:182926.5-182926.29" + attribute \src "libresoc.v:182925.5-182925.29" switch \initial - attribute \src "libresoc.v:182926.9-182926.17" + attribute \src "libresoc.v:182925.9-182925.17" case 1'1 case end @@ -376660,15 +373470,15 @@ module \reg_6 sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11747 end - attribute \src "libresoc.v:182955.3-182994.6" - process $proc$libresoc.v:182955$11752 + attribute \src "libresoc.v:182954.3-182993.6" + process $proc$libresoc.v:182954$11752 assign { } { } assign { } { } assign { } { } assign $0\src36__data_o$next[3:0]$11753 $6\src36__data_o$next[3:0]$11759 - attribute \src "libresoc.v:182956.5-182956.29" + attribute \src "libresoc.v:182955.5-182955.29" switch \initial - attribute \src "libresoc.v:182956.9-182956.17" + attribute \src "libresoc.v:182955.9-182955.17" case 1'1 case end @@ -376732,14 +373542,14 @@ module \reg_6 sync always update \src36__data_o$next $0\src36__data_o$next[3:0]$11753 end - attribute \src "libresoc.v:182995.3-183024.6" - process $proc$libresoc.v:182995$11760 + attribute \src "libresoc.v:182994.3-183023.6" + process $proc$libresoc.v:182994$11760 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$11761 $1\wr_detect$10[0:0]$11762 - attribute \src "libresoc.v:182996.5-182996.29" + attribute \src "libresoc.v:182995.5-182995.29" switch \initial - attribute \src "libresoc.v:182996.9-182996.17" + attribute \src "libresoc.v:182995.9-182995.17" case 1'1 case end @@ -376785,15 +373595,15 @@ module \reg_6 sync always update \wr_detect$10 $0\wr_detect$10[0:0]$11761 end - attribute \src "libresoc.v:183025.3-183064.6" - process $proc$libresoc.v:183025$11766 + attribute \src "libresoc.v:183024.3-183063.6" + process $proc$libresoc.v:183024$11766 assign { } { } assign { } { } assign { } { } assign $0\r6__data_o$next[3:0]$11767 $6\r6__data_o$next[3:0]$11773 - attribute \src "libresoc.v:183026.5-183026.29" + attribute \src "libresoc.v:183025.5-183025.29" switch \initial - attribute \src "libresoc.v:183026.9-183026.17" + attribute \src "libresoc.v:183025.9-183025.17" case 1'1 case end @@ -376857,14 +373667,14 @@ module \reg_6 sync always update \r6__data_o$next $0\r6__data_o$next[3:0]$11767 end - attribute \src "libresoc.v:183065.3-183094.6" - process $proc$libresoc.v:183065$11774 + attribute \src "libresoc.v:183064.3-183093.6" + process $proc$libresoc.v:183064$11774 assign { } { } assign { } { } assign $0\wr_detect$13[0:0]$11775 $1\wr_detect$13[0:0]$11776 - attribute \src "libresoc.v:183066.5-183066.29" + attribute \src "libresoc.v:183065.5-183065.29" switch \initial - attribute \src "libresoc.v:183066.9-183066.17" + attribute \src "libresoc.v:183065.9-183065.17" case 1'1 case end @@ -376910,214 +373720,214 @@ module \reg_6 sync always update \wr_detect$13 $0\wr_detect$13[0:0]$11775 end - connect \$9 $not$libresoc.v:182628$11682_Y - connect \$12 $not$libresoc.v:182629$11683_Y - connect \$15 $not$libresoc.v:182630$11684_Y - connect \$1 $not$libresoc.v:182631$11685_Y - connect \$3 $not$libresoc.v:182632$11686_Y - connect \$6 $not$libresoc.v:182633$11687_Y + connect \$9 $not$libresoc.v:182627$11682_Y + connect \$12 $not$libresoc.v:182628$11683_Y + connect \$15 $not$libresoc.v:182629$11684_Y + connect \$1 $not$libresoc.v:182630$11685_Y + connect \$3 $not$libresoc.v:182631$11686_Y + connect \$6 $not$libresoc.v:182632$11687_Y end -attribute \src "libresoc.v:183099.1-183654.10" +attribute \src "libresoc.v:183098.1-183653.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_7" attribute \generator "nMigen" module \reg_7 - attribute \src "libresoc.v:183207.3-183246.6" + attribute \src "libresoc.v:183206.3-183245.6" wire width 4 $0\cr_pred7__data_o$next[3:0]$11802 - attribute \src "libresoc.v:183205.3-183206.49" + attribute \src "libresoc.v:183204.3-183205.49" wire width 4 $0\cr_pred7__data_o[3:0] - attribute \src "libresoc.v:183100.7-183100.20" + attribute \src "libresoc.v:183099.7-183099.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183277.3-183316.6" + attribute \src "libresoc.v:183276.3-183315.6" wire width 4 $0\r27__data_o$next[3:0]$11811 - attribute \src "libresoc.v:183195.3-183196.39" + attribute \src "libresoc.v:183194.3-183195.39" wire width 4 $0\r27__data_o[3:0] - attribute \src "libresoc.v:183584.3-183623.6" + attribute \src "libresoc.v:183583.3-183622.6" wire width 4 $0\r7__data_o$next[3:0]$11873 - attribute \src "libresoc.v:183197.3-183198.37" + attribute \src "libresoc.v:183196.3-183197.37" wire width 4 $0\r7__data_o[3:0] - attribute \src "libresoc.v:183347.3-183373.6" + attribute \src "libresoc.v:183346.3-183372.6" wire width 4 $0\reg$next[3:0]$11825 - attribute \src "libresoc.v:183193.3-183194.25" + attribute \src "libresoc.v:183192.3-183193.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:183374.3-183413.6" + attribute \src "libresoc.v:183373.3-183412.6" wire width 4 $0\src17__data_o$next[3:0]$11831 - attribute \src "libresoc.v:183203.3-183204.43" + attribute \src "libresoc.v:183202.3-183203.43" wire width 4 $0\src17__data_o[3:0] - attribute \src "libresoc.v:183444.3-183483.6" + attribute \src "libresoc.v:183443.3-183482.6" wire width 4 $0\src27__data_o$next[3:0]$11845 - attribute \src "libresoc.v:183201.3-183202.43" + attribute \src "libresoc.v:183200.3-183201.43" wire width 4 $0\src27__data_o[3:0] - attribute \src "libresoc.v:183514.3-183553.6" + attribute \src "libresoc.v:183513.3-183552.6" wire width 4 $0\src37__data_o$next[3:0]$11859 - attribute \src "libresoc.v:183199.3-183200.43" + attribute \src "libresoc.v:183198.3-183199.43" wire width 4 $0\src37__data_o[3:0] - attribute \src "libresoc.v:183554.3-183583.6" + attribute \src "libresoc.v:183553.3-183582.6" wire $0\wr_detect$10[0:0]$11867 - attribute \src "libresoc.v:183624.3-183653.6" + attribute \src "libresoc.v:183623.3-183652.6" wire $0\wr_detect$13[0:0]$11881 - attribute \src "libresoc.v:183317.3-183346.6" + attribute \src "libresoc.v:183316.3-183345.6" wire $0\wr_detect$16[0:0]$11819 - attribute \src "libresoc.v:183414.3-183443.6" + attribute \src "libresoc.v:183413.3-183442.6" wire $0\wr_detect$4[0:0]$11839 - attribute \src "libresoc.v:183484.3-183513.6" + attribute \src "libresoc.v:183483.3-183512.6" wire $0\wr_detect$7[0:0]$11853 - attribute \src "libresoc.v:183247.3-183276.6" + attribute \src "libresoc.v:183246.3-183275.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:183207.3-183246.6" + attribute \src "libresoc.v:183206.3-183245.6" wire width 4 $1\cr_pred7__data_o$next[3:0]$11803 - attribute \src "libresoc.v:183119.13-183119.36" + attribute \src "libresoc.v:183118.13-183118.36" wire width 4 $1\cr_pred7__data_o[3:0] - attribute \src "libresoc.v:183277.3-183316.6" + attribute \src "libresoc.v:183276.3-183315.6" wire width 4 $1\r27__data_o$next[3:0]$11812 - attribute \src "libresoc.v:183134.13-183134.31" + attribute \src "libresoc.v:183133.13-183133.31" wire width 4 $1\r27__data_o[3:0] - attribute \src "libresoc.v:183584.3-183623.6" + attribute \src "libresoc.v:183583.3-183622.6" wire width 4 $1\r7__data_o$next[3:0]$11874 - attribute \src "libresoc.v:183141.13-183141.30" + attribute \src "libresoc.v:183140.13-183140.30" wire width 4 $1\r7__data_o[3:0] - attribute \src "libresoc.v:183347.3-183373.6" + attribute \src "libresoc.v:183346.3-183372.6" wire width 4 $1\reg$next[3:0]$11826 - attribute \src "libresoc.v:183147.13-183147.25" + attribute \src "libresoc.v:183146.13-183146.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:183374.3-183413.6" + attribute \src "libresoc.v:183373.3-183412.6" wire width 4 $1\src17__data_o$next[3:0]$11832 - attribute \src "libresoc.v:183152.13-183152.33" + attribute \src "libresoc.v:183151.13-183151.33" wire width 4 $1\src17__data_o[3:0] - attribute \src "libresoc.v:183444.3-183483.6" + attribute \src "libresoc.v:183443.3-183482.6" wire width 4 $1\src27__data_o$next[3:0]$11846 - attribute \src "libresoc.v:183159.13-183159.33" + attribute \src "libresoc.v:183158.13-183158.33" wire width 4 $1\src27__data_o[3:0] - attribute \src "libresoc.v:183514.3-183553.6" + attribute \src "libresoc.v:183513.3-183552.6" wire width 4 $1\src37__data_o$next[3:0]$11860 - attribute \src "libresoc.v:183166.13-183166.33" + attribute \src "libresoc.v:183165.13-183165.33" wire width 4 $1\src37__data_o[3:0] - attribute \src "libresoc.v:183554.3-183583.6" + attribute \src "libresoc.v:183553.3-183582.6" wire $1\wr_detect$10[0:0]$11868 - attribute \src "libresoc.v:183624.3-183653.6" + attribute \src "libresoc.v:183623.3-183652.6" wire $1\wr_detect$13[0:0]$11882 - attribute \src "libresoc.v:183317.3-183346.6" + attribute \src "libresoc.v:183316.3-183345.6" wire $1\wr_detect$16[0:0]$11820 - attribute \src "libresoc.v:183414.3-183443.6" + attribute \src "libresoc.v:183413.3-183442.6" wire $1\wr_detect$4[0:0]$11840 - attribute \src "libresoc.v:183484.3-183513.6" + attribute \src "libresoc.v:183483.3-183512.6" wire $1\wr_detect$7[0:0]$11854 - attribute \src "libresoc.v:183247.3-183276.6" + attribute \src "libresoc.v:183246.3-183275.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:183207.3-183246.6" + attribute \src "libresoc.v:183206.3-183245.6" wire width 4 $2\cr_pred7__data_o$next[3:0]$11804 - attribute \src "libresoc.v:183277.3-183316.6" + attribute \src "libresoc.v:183276.3-183315.6" wire width 4 $2\r27__data_o$next[3:0]$11813 - attribute \src "libresoc.v:183584.3-183623.6" + attribute \src "libresoc.v:183583.3-183622.6" wire width 4 $2\r7__data_o$next[3:0]$11875 - attribute \src "libresoc.v:183347.3-183373.6" + attribute \src "libresoc.v:183346.3-183372.6" wire width 4 $2\reg$next[3:0]$11827 - attribute \src "libresoc.v:183374.3-183413.6" + attribute \src "libresoc.v:183373.3-183412.6" wire width 4 $2\src17__data_o$next[3:0]$11833 - attribute \src "libresoc.v:183444.3-183483.6" + attribute \src "libresoc.v:183443.3-183482.6" wire width 4 $2\src27__data_o$next[3:0]$11847 - attribute \src "libresoc.v:183514.3-183553.6" + attribute \src "libresoc.v:183513.3-183552.6" wire width 4 $2\src37__data_o$next[3:0]$11861 - attribute \src "libresoc.v:183554.3-183583.6" + attribute \src "libresoc.v:183553.3-183582.6" wire $2\wr_detect$10[0:0]$11869 - attribute \src "libresoc.v:183624.3-183653.6" + attribute \src "libresoc.v:183623.3-183652.6" wire $2\wr_detect$13[0:0]$11883 - attribute \src "libresoc.v:183317.3-183346.6" + attribute \src "libresoc.v:183316.3-183345.6" wire $2\wr_detect$16[0:0]$11821 - attribute \src "libresoc.v:183414.3-183443.6" + attribute \src "libresoc.v:183413.3-183442.6" wire $2\wr_detect$4[0:0]$11841 - attribute \src "libresoc.v:183484.3-183513.6" + attribute \src "libresoc.v:183483.3-183512.6" wire $2\wr_detect$7[0:0]$11855 - attribute \src "libresoc.v:183247.3-183276.6" + attribute \src "libresoc.v:183246.3-183275.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:183207.3-183246.6" + attribute \src "libresoc.v:183206.3-183245.6" wire width 4 $3\cr_pred7__data_o$next[3:0]$11805 - attribute \src "libresoc.v:183277.3-183316.6" + attribute \src "libresoc.v:183276.3-183315.6" wire width 4 $3\r27__data_o$next[3:0]$11814 - attribute \src "libresoc.v:183584.3-183623.6" + attribute \src "libresoc.v:183583.3-183622.6" wire width 4 $3\r7__data_o$next[3:0]$11876 - attribute \src "libresoc.v:183347.3-183373.6" + attribute \src "libresoc.v:183346.3-183372.6" wire width 4 $3\reg$next[3:0]$11828 - attribute \src "libresoc.v:183374.3-183413.6" + attribute \src "libresoc.v:183373.3-183412.6" wire width 4 $3\src17__data_o$next[3:0]$11834 - attribute \src "libresoc.v:183444.3-183483.6" + attribute \src "libresoc.v:183443.3-183482.6" wire width 4 $3\src27__data_o$next[3:0]$11848 - attribute \src "libresoc.v:183514.3-183553.6" + attribute \src "libresoc.v:183513.3-183552.6" wire width 4 $3\src37__data_o$next[3:0]$11862 - attribute \src "libresoc.v:183554.3-183583.6" + attribute \src "libresoc.v:183553.3-183582.6" wire $3\wr_detect$10[0:0]$11870 - attribute \src "libresoc.v:183624.3-183653.6" + attribute \src "libresoc.v:183623.3-183652.6" wire $3\wr_detect$13[0:0]$11884 - attribute \src "libresoc.v:183317.3-183346.6" + attribute \src "libresoc.v:183316.3-183345.6" wire $3\wr_detect$16[0:0]$11822 - attribute \src "libresoc.v:183414.3-183443.6" + attribute \src "libresoc.v:183413.3-183442.6" wire $3\wr_detect$4[0:0]$11842 - attribute \src "libresoc.v:183484.3-183513.6" + attribute \src "libresoc.v:183483.3-183512.6" wire $3\wr_detect$7[0:0]$11856 - attribute \src "libresoc.v:183247.3-183276.6" + attribute \src "libresoc.v:183246.3-183275.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:183207.3-183246.6" + attribute \src "libresoc.v:183206.3-183245.6" wire width 4 $4\cr_pred7__data_o$next[3:0]$11806 - attribute \src "libresoc.v:183277.3-183316.6" + attribute \src "libresoc.v:183276.3-183315.6" wire width 4 $4\r27__data_o$next[3:0]$11815 - attribute \src "libresoc.v:183584.3-183623.6" + attribute \src "libresoc.v:183583.3-183622.6" wire width 4 $4\r7__data_o$next[3:0]$11877 - attribute \src "libresoc.v:183347.3-183373.6" + attribute \src "libresoc.v:183346.3-183372.6" wire width 4 $4\reg$next[3:0]$11829 - attribute \src "libresoc.v:183374.3-183413.6" + attribute \src "libresoc.v:183373.3-183412.6" wire width 4 $4\src17__data_o$next[3:0]$11835 - attribute \src "libresoc.v:183444.3-183483.6" + attribute \src "libresoc.v:183443.3-183482.6" wire width 4 $4\src27__data_o$next[3:0]$11849 - attribute \src "libresoc.v:183514.3-183553.6" + attribute \src "libresoc.v:183513.3-183552.6" wire width 4 $4\src37__data_o$next[3:0]$11863 - attribute \src "libresoc.v:183554.3-183583.6" + attribute \src "libresoc.v:183553.3-183582.6" wire $4\wr_detect$10[0:0]$11871 - attribute \src "libresoc.v:183624.3-183653.6" + attribute \src "libresoc.v:183623.3-183652.6" wire $4\wr_detect$13[0:0]$11885 - attribute \src "libresoc.v:183317.3-183346.6" + attribute \src "libresoc.v:183316.3-183345.6" wire $4\wr_detect$16[0:0]$11823 - attribute \src "libresoc.v:183414.3-183443.6" + attribute \src "libresoc.v:183413.3-183442.6" wire $4\wr_detect$4[0:0]$11843 - attribute \src "libresoc.v:183484.3-183513.6" + attribute \src "libresoc.v:183483.3-183512.6" wire $4\wr_detect$7[0:0]$11857 - attribute \src "libresoc.v:183247.3-183276.6" + attribute \src "libresoc.v:183246.3-183275.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:183207.3-183246.6" + attribute \src "libresoc.v:183206.3-183245.6" wire width 4 $5\cr_pred7__data_o$next[3:0]$11807 - attribute \src "libresoc.v:183277.3-183316.6" + attribute \src "libresoc.v:183276.3-183315.6" wire width 4 $5\r27__data_o$next[3:0]$11816 - attribute \src "libresoc.v:183584.3-183623.6" + attribute \src "libresoc.v:183583.3-183622.6" wire width 4 $5\r7__data_o$next[3:0]$11878 - attribute \src "libresoc.v:183374.3-183413.6" + attribute \src "libresoc.v:183373.3-183412.6" wire width 4 $5\src17__data_o$next[3:0]$11836 - attribute \src "libresoc.v:183444.3-183483.6" + attribute \src "libresoc.v:183443.3-183482.6" wire width 4 $5\src27__data_o$next[3:0]$11850 - attribute \src "libresoc.v:183514.3-183553.6" + attribute \src "libresoc.v:183513.3-183552.6" wire width 4 $5\src37__data_o$next[3:0]$11864 - attribute \src "libresoc.v:183207.3-183246.6" + attribute \src "libresoc.v:183206.3-183245.6" wire width 4 $6\cr_pred7__data_o$next[3:0]$11808 - attribute \src "libresoc.v:183277.3-183316.6" + attribute \src "libresoc.v:183276.3-183315.6" wire width 4 $6\r27__data_o$next[3:0]$11817 - attribute \src "libresoc.v:183584.3-183623.6" + attribute \src "libresoc.v:183583.3-183622.6" wire width 4 $6\r7__data_o$next[3:0]$11879 - attribute \src "libresoc.v:183374.3-183413.6" + attribute \src "libresoc.v:183373.3-183412.6" wire width 4 $6\src17__data_o$next[3:0]$11837 - attribute \src "libresoc.v:183444.3-183483.6" + attribute \src "libresoc.v:183443.3-183482.6" wire width 4 $6\src27__data_o$next[3:0]$11851 - attribute \src "libresoc.v:183514.3-183553.6" + attribute \src "libresoc.v:183513.3-183552.6" wire width 4 $6\src37__data_o$next[3:0]$11865 - attribute \src "libresoc.v:183187.17-183187.104" - wire $not$libresoc.v:183187$11788_Y + attribute \src "libresoc.v:183186.17-183186.104" + wire $not$libresoc.v:183186$11788_Y + attribute \src "libresoc.v:183187.18-183187.105" + wire $not$libresoc.v:183187$11789_Y attribute \src "libresoc.v:183188.18-183188.105" - wire $not$libresoc.v:183188$11789_Y - attribute \src "libresoc.v:183189.18-183189.105" - wire $not$libresoc.v:183189$11790_Y - attribute \src "libresoc.v:183190.17-183190.100" - wire $not$libresoc.v:183190$11791_Y + wire $not$libresoc.v:183188$11790_Y + attribute \src "libresoc.v:183189.17-183189.100" + wire $not$libresoc.v:183189$11791_Y + attribute \src "libresoc.v:183190.17-183190.103" + wire $not$libresoc.v:183190$11792_Y attribute \src "libresoc.v:183191.17-183191.103" - wire $not$libresoc.v:183191$11792_Y - attribute \src "libresoc.v:183192.17-183192.103" - wire $not$libresoc.v:183192$11793_Y + wire $not$libresoc.v:183191$11793_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -377148,7 +373958,7 @@ module \reg_7 wire width 4 input 13 \dest27__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest27__wen - attribute \src "libresoc.v:183100.7-183100.15" + attribute \src "libresoc.v:183099.7-183099.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 16 \r27__data_o @@ -377201,175 +374011,175 @@ module \reg_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183187$11788 + cell $not $not$libresoc.v:183186$11788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:183187$11788_Y + connect \Y $not$libresoc.v:183186$11788_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183188$11789 + cell $not $not$libresoc.v:183187$11789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:183188$11789_Y + connect \Y $not$libresoc.v:183187$11789_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183189$11790 + cell $not $not$libresoc.v:183188$11790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$16 - connect \Y $not$libresoc.v:183189$11790_Y + connect \Y $not$libresoc.v:183188$11790_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183190$11791 + cell $not $not$libresoc.v:183189$11791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:183190$11791_Y + connect \Y $not$libresoc.v:183189$11791_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183191$11792 + cell $not $not$libresoc.v:183190$11792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:183191$11792_Y + connect \Y $not$libresoc.v:183190$11792_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183192$11793 + cell $not $not$libresoc.v:183191$11793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:183192$11793_Y + connect \Y $not$libresoc.v:183191$11793_Y end - attribute \src "libresoc.v:183100.7-183100.20" - process $proc$libresoc.v:183100$11886 + attribute \src "libresoc.v:183099.7-183099.20" + process $proc$libresoc.v:183099$11886 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183119.13-183119.36" - process $proc$libresoc.v:183119$11887 + attribute \src "libresoc.v:183118.13-183118.36" + process $proc$libresoc.v:183118$11887 assign { } { } assign $1\cr_pred7__data_o[3:0] 4'0000 sync always sync init update \cr_pred7__data_o $1\cr_pred7__data_o[3:0] end - attribute \src "libresoc.v:183134.13-183134.31" - process $proc$libresoc.v:183134$11888 + attribute \src "libresoc.v:183133.13-183133.31" + process $proc$libresoc.v:183133$11888 assign { } { } assign $1\r27__data_o[3:0] 4'0000 sync always sync init update \r27__data_o $1\r27__data_o[3:0] end - attribute \src "libresoc.v:183141.13-183141.30" - process $proc$libresoc.v:183141$11889 + attribute \src "libresoc.v:183140.13-183140.30" + process $proc$libresoc.v:183140$11889 assign { } { } assign $1\r7__data_o[3:0] 4'0000 sync always sync init update \r7__data_o $1\r7__data_o[3:0] end - attribute \src "libresoc.v:183147.13-183147.25" - process $proc$libresoc.v:183147$11890 + attribute \src "libresoc.v:183146.13-183146.25" + process $proc$libresoc.v:183146$11890 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:183152.13-183152.33" - process $proc$libresoc.v:183152$11891 + attribute \src "libresoc.v:183151.13-183151.33" + process $proc$libresoc.v:183151$11891 assign { } { } assign $1\src17__data_o[3:0] 4'0000 sync always sync init update \src17__data_o $1\src17__data_o[3:0] end - attribute \src "libresoc.v:183159.13-183159.33" - process $proc$libresoc.v:183159$11892 + attribute \src "libresoc.v:183158.13-183158.33" + process $proc$libresoc.v:183158$11892 assign { } { } assign $1\src27__data_o[3:0] 4'0000 sync always sync init update \src27__data_o $1\src27__data_o[3:0] end - attribute \src "libresoc.v:183166.13-183166.33" - process $proc$libresoc.v:183166$11893 + attribute \src "libresoc.v:183165.13-183165.33" + process $proc$libresoc.v:183165$11893 assign { } { } assign $1\src37__data_o[3:0] 4'0000 sync always sync init update \src37__data_o $1\src37__data_o[3:0] end - attribute \src "libresoc.v:183193.3-183194.25" - process $proc$libresoc.v:183193$11794 + attribute \src "libresoc.v:183192.3-183193.25" + process $proc$libresoc.v:183192$11794 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:183195.3-183196.39" - process $proc$libresoc.v:183195$11795 + attribute \src "libresoc.v:183194.3-183195.39" + process $proc$libresoc.v:183194$11795 assign { } { } assign $0\r27__data_o[3:0] \r27__data_o$next sync posedge \coresync_clk update \r27__data_o $0\r27__data_o[3:0] end - attribute \src "libresoc.v:183197.3-183198.37" - process $proc$libresoc.v:183197$11796 + attribute \src "libresoc.v:183196.3-183197.37" + process $proc$libresoc.v:183196$11796 assign { } { } assign $0\r7__data_o[3:0] \r7__data_o$next sync posedge \coresync_clk update \r7__data_o $0\r7__data_o[3:0] end - attribute \src "libresoc.v:183199.3-183200.43" - process $proc$libresoc.v:183199$11797 + attribute \src "libresoc.v:183198.3-183199.43" + process $proc$libresoc.v:183198$11797 assign { } { } assign $0\src37__data_o[3:0] \src37__data_o$next sync posedge \coresync_clk update \src37__data_o $0\src37__data_o[3:0] end - attribute \src "libresoc.v:183201.3-183202.43" - process $proc$libresoc.v:183201$11798 + attribute \src "libresoc.v:183200.3-183201.43" + process $proc$libresoc.v:183200$11798 assign { } { } assign $0\src27__data_o[3:0] \src27__data_o$next sync posedge \coresync_clk update \src27__data_o $0\src27__data_o[3:0] end - attribute \src "libresoc.v:183203.3-183204.43" - process $proc$libresoc.v:183203$11799 + attribute \src "libresoc.v:183202.3-183203.43" + process $proc$libresoc.v:183202$11799 assign { } { } assign $0\src17__data_o[3:0] \src17__data_o$next sync posedge \coresync_clk update \src17__data_o $0\src17__data_o[3:0] end - attribute \src "libresoc.v:183205.3-183206.49" - process $proc$libresoc.v:183205$11800 + attribute \src "libresoc.v:183204.3-183205.49" + process $proc$libresoc.v:183204$11800 assign { } { } assign $0\cr_pred7__data_o[3:0] \cr_pred7__data_o$next sync posedge \coresync_clk update \cr_pred7__data_o $0\cr_pred7__data_o[3:0] end - attribute \src "libresoc.v:183207.3-183246.6" - process $proc$libresoc.v:183207$11801 + attribute \src "libresoc.v:183206.3-183245.6" + process $proc$libresoc.v:183206$11801 assign { } { } assign { } { } assign { } { } assign $0\cr_pred7__data_o$next[3:0]$11802 $6\cr_pred7__data_o$next[3:0]$11808 - attribute \src "libresoc.v:183208.5-183208.29" + attribute \src "libresoc.v:183207.5-183207.29" switch \initial - attribute \src "libresoc.v:183208.9-183208.17" + attribute \src "libresoc.v:183207.9-183207.17" case 1'1 case end @@ -377433,14 +374243,14 @@ module \reg_7 sync always update \cr_pred7__data_o$next $0\cr_pred7__data_o$next[3:0]$11802 end - attribute \src "libresoc.v:183247.3-183276.6" - process $proc$libresoc.v:183247$11809 + attribute \src "libresoc.v:183246.3-183275.6" + process $proc$libresoc.v:183246$11809 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:183248.5-183248.29" + attribute \src "libresoc.v:183247.5-183247.29" switch \initial - attribute \src "libresoc.v:183248.9-183248.17" + attribute \src "libresoc.v:183247.9-183247.17" case 1'1 case end @@ -377486,15 +374296,15 @@ module \reg_7 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:183277.3-183316.6" - process $proc$libresoc.v:183277$11810 + attribute \src "libresoc.v:183276.3-183315.6" + process $proc$libresoc.v:183276$11810 assign { } { } assign { } { } assign { } { } assign $0\r27__data_o$next[3:0]$11811 $6\r27__data_o$next[3:0]$11817 - attribute \src "libresoc.v:183278.5-183278.29" + attribute \src "libresoc.v:183277.5-183277.29" switch \initial - attribute \src "libresoc.v:183278.9-183278.17" + attribute \src "libresoc.v:183277.9-183277.17" case 1'1 case end @@ -377558,14 +374368,14 @@ module \reg_7 sync always update \r27__data_o$next $0\r27__data_o$next[3:0]$11811 end - attribute \src "libresoc.v:183317.3-183346.6" - process $proc$libresoc.v:183317$11818 + attribute \src "libresoc.v:183316.3-183345.6" + process $proc$libresoc.v:183316$11818 assign { } { } assign { } { } assign $0\wr_detect$16[0:0]$11819 $1\wr_detect$16[0:0]$11820 - attribute \src "libresoc.v:183318.5-183318.29" + attribute \src "libresoc.v:183317.5-183317.29" switch \initial - attribute \src "libresoc.v:183318.9-183318.17" + attribute \src "libresoc.v:183317.9-183317.17" case 1'1 case end @@ -377611,17 +374421,17 @@ module \reg_7 sync always update \wr_detect$16 $0\wr_detect$16[0:0]$11819 end - attribute \src "libresoc.v:183347.3-183373.6" - process $proc$libresoc.v:183347$11824 + attribute \src "libresoc.v:183346.3-183372.6" + process $proc$libresoc.v:183346$11824 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign $0\reg$next[3:0]$11825 $4\reg$next[3:0]$11829 - attribute \src "libresoc.v:183348.5-183348.29" + attribute \src "libresoc.v:183347.5-183347.29" switch \initial - attribute \src "libresoc.v:183348.9-183348.17" + attribute \src "libresoc.v:183347.9-183347.17" case 1'1 case end @@ -377664,15 +374474,15 @@ module \reg_7 sync always update \reg$next $0\reg$next[3:0]$11825 end - attribute \src "libresoc.v:183374.3-183413.6" - process $proc$libresoc.v:183374$11830 + attribute \src "libresoc.v:183373.3-183412.6" + process $proc$libresoc.v:183373$11830 assign { } { } assign { } { } assign { } { } assign $0\src17__data_o$next[3:0]$11831 $6\src17__data_o$next[3:0]$11837 - attribute \src "libresoc.v:183375.5-183375.29" + attribute \src "libresoc.v:183374.5-183374.29" switch \initial - attribute \src "libresoc.v:183375.9-183375.17" + attribute \src "libresoc.v:183374.9-183374.17" case 1'1 case end @@ -377736,14 +374546,14 @@ module \reg_7 sync always update \src17__data_o$next $0\src17__data_o$next[3:0]$11831 end - attribute \src "libresoc.v:183414.3-183443.6" - process $proc$libresoc.v:183414$11838 + attribute \src "libresoc.v:183413.3-183442.6" + process $proc$libresoc.v:183413$11838 assign { } { } assign { } { } assign $0\wr_detect$4[0:0]$11839 $1\wr_detect$4[0:0]$11840 - attribute \src "libresoc.v:183415.5-183415.29" + attribute \src "libresoc.v:183414.5-183414.29" switch \initial - attribute \src "libresoc.v:183415.9-183415.17" + attribute \src "libresoc.v:183414.9-183414.17" case 1'1 case end @@ -377789,15 +374599,15 @@ module \reg_7 sync always update \wr_detect$4 $0\wr_detect$4[0:0]$11839 end - attribute \src "libresoc.v:183444.3-183483.6" - process $proc$libresoc.v:183444$11844 + attribute \src "libresoc.v:183443.3-183482.6" + process $proc$libresoc.v:183443$11844 assign { } { } assign { } { } assign { } { } assign $0\src27__data_o$next[3:0]$11845 $6\src27__data_o$next[3:0]$11851 - attribute \src "libresoc.v:183445.5-183445.29" + attribute \src "libresoc.v:183444.5-183444.29" switch \initial - attribute \src "libresoc.v:183445.9-183445.17" + attribute \src "libresoc.v:183444.9-183444.17" case 1'1 case end @@ -377861,14 +374671,14 @@ module \reg_7 sync always update \src27__data_o$next $0\src27__data_o$next[3:0]$11845 end - attribute \src "libresoc.v:183484.3-183513.6" - process $proc$libresoc.v:183484$11852 + attribute \src "libresoc.v:183483.3-183512.6" + process $proc$libresoc.v:183483$11852 assign { } { } assign { } { } assign $0\wr_detect$7[0:0]$11853 $1\wr_detect$7[0:0]$11854 - attribute \src "libresoc.v:183485.5-183485.29" + attribute \src "libresoc.v:183484.5-183484.29" switch \initial - attribute \src "libresoc.v:183485.9-183485.17" + attribute \src "libresoc.v:183484.9-183484.17" case 1'1 case end @@ -377914,15 +374724,15 @@ module \reg_7 sync always update \wr_detect$7 $0\wr_detect$7[0:0]$11853 end - attribute \src "libresoc.v:183514.3-183553.6" - process $proc$libresoc.v:183514$11858 + attribute \src "libresoc.v:183513.3-183552.6" + process $proc$libresoc.v:183513$11858 assign { } { } assign { } { } assign { } { } assign $0\src37__data_o$next[3:0]$11859 $6\src37__data_o$next[3:0]$11865 - attribute \src "libresoc.v:183515.5-183515.29" + attribute \src "libresoc.v:183514.5-183514.29" switch \initial - attribute \src "libresoc.v:183515.9-183515.17" + attribute \src "libresoc.v:183514.9-183514.17" case 1'1 case end @@ -377986,14 +374796,14 @@ module \reg_7 sync always update \src37__data_o$next $0\src37__data_o$next[3:0]$11859 end - attribute \src "libresoc.v:183554.3-183583.6" - process $proc$libresoc.v:183554$11866 + attribute \src "libresoc.v:183553.3-183582.6" + process $proc$libresoc.v:183553$11866 assign { } { } assign { } { } assign $0\wr_detect$10[0:0]$11867 $1\wr_detect$10[0:0]$11868 - attribute \src "libresoc.v:183555.5-183555.29" + attribute \src "libresoc.v:183554.5-183554.29" switch \initial - attribute \src "libresoc.v:183555.9-183555.17" + attribute \src "libresoc.v:183554.9-183554.17" case 1'1 case end @@ -378039,15 +374849,15 @@ module \reg_7 sync always update \wr_detect$10 $0\wr_detect$10[0:0]$11867 end - attribute \src "libresoc.v:183584.3-183623.6" - process $proc$libresoc.v:183584$11872 + attribute \src "libresoc.v:183583.3-183622.6" + process $proc$libresoc.v:183583$11872 assign { } { } assign { } { } assign { } { } assign $0\r7__data_o$next[3:0]$11873 $6\r7__data_o$next[3:0]$11879 - attribute \src "libresoc.v:183585.5-183585.29" + attribute \src "libresoc.v:183584.5-183584.29" switch \initial - attribute \src "libresoc.v:183585.9-183585.17" + attribute \src "libresoc.v:183584.9-183584.17" case 1'1 case end @@ -378111,14 +374921,14 @@ module \reg_7 sync always update \r7__data_o$next $0\r7__data_o$next[3:0]$11873 end - attribute \src "libresoc.v:183624.3-183653.6" - process $proc$libresoc.v:183624$11880 + attribute \src "libresoc.v:183623.3-183652.6" + process $proc$libresoc.v:183623$11880 assign { } { } assign { } { } assign $0\wr_detect$13[0:0]$11881 $1\wr_detect$13[0:0]$11882 - attribute \src "libresoc.v:183625.5-183625.29" + attribute \src "libresoc.v:183624.5-183624.29" switch \initial - attribute \src "libresoc.v:183625.9-183625.17" + attribute \src "libresoc.v:183624.9-183624.17" case 1'1 case end @@ -378164,44 +374974,44 @@ module \reg_7 sync always update \wr_detect$13 $0\wr_detect$13[0:0]$11881 end - connect \$9 $not$libresoc.v:183187$11788_Y - connect \$12 $not$libresoc.v:183188$11789_Y - connect \$15 $not$libresoc.v:183189$11790_Y - connect \$1 $not$libresoc.v:183190$11791_Y - connect \$3 $not$libresoc.v:183191$11792_Y - connect \$6 $not$libresoc.v:183192$11793_Y + connect \$9 $not$libresoc.v:183186$11788_Y + connect \$12 $not$libresoc.v:183187$11789_Y + connect \$15 $not$libresoc.v:183188$11790_Y + connect \$1 $not$libresoc.v:183189$11791_Y + connect \$3 $not$libresoc.v:183190$11792_Y + connect \$6 $not$libresoc.v:183191$11793_Y end -attribute \src "libresoc.v:183658.1-183716.10" +attribute \src "libresoc.v:183657.1-183715.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.req_l" attribute \generator "nMigen" module \req_l - attribute \src "libresoc.v:183659.7-183659.20" + attribute \src "libresoc.v:183658.7-183658.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183704.3-183712.6" + attribute \src "libresoc.v:183703.3-183711.6" wire width 5 $0\q_int$next[4:0]$11904 - attribute \src "libresoc.v:183702.3-183703.27" + attribute \src "libresoc.v:183701.3-183702.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:183704.3-183712.6" + attribute \src "libresoc.v:183703.3-183711.6" wire width 5 $1\q_int$next[4:0]$11905 - attribute \src "libresoc.v:183681.13-183681.26" + attribute \src "libresoc.v:183680.13-183680.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:183694.17-183694.96" - wire width 5 $and$libresoc.v:183694$11894_Y - attribute \src "libresoc.v:183699.17-183699.96" - wire width 5 $and$libresoc.v:183699$11899_Y - attribute \src "libresoc.v:183696.18-183696.93" - wire width 5 $not$libresoc.v:183696$11896_Y - attribute \src "libresoc.v:183698.17-183698.92" - wire width 5 $not$libresoc.v:183698$11898_Y - attribute \src "libresoc.v:183701.17-183701.92" - wire width 5 $not$libresoc.v:183701$11901_Y - attribute \src "libresoc.v:183695.18-183695.98" - wire width 5 $or$libresoc.v:183695$11895_Y - attribute \src "libresoc.v:183697.18-183697.99" - wire width 5 $or$libresoc.v:183697$11897_Y - attribute \src "libresoc.v:183700.17-183700.97" - wire width 5 $or$libresoc.v:183700$11900_Y + attribute \src "libresoc.v:183693.17-183693.96" + wire width 5 $and$libresoc.v:183693$11894_Y + attribute \src "libresoc.v:183698.17-183698.96" + wire width 5 $and$libresoc.v:183698$11899_Y + attribute \src "libresoc.v:183695.18-183695.93" + wire width 5 $not$libresoc.v:183695$11896_Y + attribute \src "libresoc.v:183697.17-183697.92" + wire width 5 $not$libresoc.v:183697$11898_Y + attribute \src "libresoc.v:183700.17-183700.92" + wire width 5 $not$libresoc.v:183700$11901_Y + attribute \src "libresoc.v:183694.18-183694.98" + wire width 5 $or$libresoc.v:183694$11895_Y + attribute \src "libresoc.v:183696.18-183696.99" + wire width 5 $or$libresoc.v:183696$11897_Y + attribute \src "libresoc.v:183699.17-183699.97" + wire width 5 $or$libresoc.v:183699$11900_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378222,7 +375032,7 @@ module \req_l wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183659.7-183659.15" + attribute \src "libresoc.v:183658.7-183658.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -378239,7 +375049,7 @@ module \req_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183694$11894 + cell $and $and$libresoc.v:183693$11894 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -378247,10 +375057,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183694$11894_Y + connect \Y $and$libresoc.v:183693$11894_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183699$11899 + cell $and $and$libresoc.v:183698$11899 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -378258,34 +375068,34 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183699$11899_Y + connect \Y $and$libresoc.v:183698$11899_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183696$11896 + cell $not $not$libresoc.v:183695$11896 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:183696$11896_Y + connect \Y $not$libresoc.v:183695$11896_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183698$11898 + cell $not $not$libresoc.v:183697$11898 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:183698$11898_Y + connect \Y $not$libresoc.v:183697$11898_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183701$11901 + cell $not $not$libresoc.v:183700$11901 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:183701$11901_Y + connect \Y $not$libresoc.v:183700$11901_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183695$11895 + cell $or $or$libresoc.v:183694$11895 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -378293,10 +375103,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:183695$11895_Y + connect \Y $or$libresoc.v:183694$11895_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183697$11897 + cell $or $or$libresoc.v:183696$11897 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -378304,10 +375114,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:183697$11897_Y + connect \Y $or$libresoc.v:183696$11897_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183700$11900 + cell $or $or$libresoc.v:183699$11900 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -378315,39 +375125,39 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:183700$11900_Y + connect \Y $or$libresoc.v:183699$11900_Y end - attribute \src "libresoc.v:183659.7-183659.20" - process $proc$libresoc.v:183659$11906 + attribute \src "libresoc.v:183658.7-183658.20" + process $proc$libresoc.v:183658$11906 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183681.13-183681.26" - process $proc$libresoc.v:183681$11907 + attribute \src "libresoc.v:183680.13-183680.26" + process $proc$libresoc.v:183680$11907 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:183702.3-183703.27" - process $proc$libresoc.v:183702$11902 + attribute \src "libresoc.v:183701.3-183702.27" + process $proc$libresoc.v:183701$11902 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:183704.3-183712.6" - process $proc$libresoc.v:183704$11903 + attribute \src "libresoc.v:183703.3-183711.6" + process $proc$libresoc.v:183703$11903 assign { } { } assign { } { } assign $0\q_int$next[4:0]$11904 $1\q_int$next[4:0]$11905 - attribute \src "libresoc.v:183705.5-183705.29" + attribute \src "libresoc.v:183704.5-183704.29" switch \initial - attribute \src "libresoc.v:183705.9-183705.17" + attribute \src "libresoc.v:183704.9-183704.17" case 1'1 case end @@ -378363,49 +375173,49 @@ module \req_l sync always update \q_int$next $0\q_int$next[4:0]$11904 end - connect \$9 $and$libresoc.v:183694$11894_Y - connect \$11 $or$libresoc.v:183695$11895_Y - connect \$13 $not$libresoc.v:183696$11896_Y - connect \$15 $or$libresoc.v:183697$11897_Y - connect \$1 $not$libresoc.v:183698$11898_Y - connect \$3 $and$libresoc.v:183699$11899_Y - connect \$5 $or$libresoc.v:183700$11900_Y - connect \$7 $not$libresoc.v:183701$11901_Y + connect \$9 $and$libresoc.v:183693$11894_Y + connect \$11 $or$libresoc.v:183694$11895_Y + connect \$13 $not$libresoc.v:183695$11896_Y + connect \$15 $or$libresoc.v:183696$11897_Y + connect \$1 $not$libresoc.v:183697$11898_Y + connect \$3 $and$libresoc.v:183698$11899_Y + connect \$5 $or$libresoc.v:183699$11900_Y + connect \$7 $not$libresoc.v:183700$11901_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:183720.1-183778.10" +attribute \src "libresoc.v:183719.1-183777.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.req_l" attribute \generator "nMigen" module \req_l$103 - attribute \src "libresoc.v:183721.7-183721.20" + attribute \src "libresoc.v:183720.7-183720.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183766.3-183774.6" + attribute \src "libresoc.v:183765.3-183773.6" wire width 4 $0\q_int$next[3:0]$11918 - attribute \src "libresoc.v:183764.3-183765.27" + attribute \src "libresoc.v:183763.3-183764.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:183766.3-183774.6" + attribute \src "libresoc.v:183765.3-183773.6" wire width 4 $1\q_int$next[3:0]$11919 - attribute \src "libresoc.v:183743.13-183743.25" + attribute \src "libresoc.v:183742.13-183742.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:183756.17-183756.96" - wire width 4 $and$libresoc.v:183756$11908_Y - attribute \src "libresoc.v:183761.17-183761.96" - wire width 4 $and$libresoc.v:183761$11913_Y - attribute \src "libresoc.v:183758.18-183758.93" - wire width 4 $not$libresoc.v:183758$11910_Y - attribute \src "libresoc.v:183760.17-183760.92" - wire width 4 $not$libresoc.v:183760$11912_Y - attribute \src "libresoc.v:183763.17-183763.92" - wire width 4 $not$libresoc.v:183763$11915_Y - attribute \src "libresoc.v:183757.18-183757.98" - wire width 4 $or$libresoc.v:183757$11909_Y - attribute \src "libresoc.v:183759.18-183759.99" - wire width 4 $or$libresoc.v:183759$11911_Y - attribute \src "libresoc.v:183762.17-183762.97" - wire width 4 $or$libresoc.v:183762$11914_Y + attribute \src "libresoc.v:183755.17-183755.96" + wire width 4 $and$libresoc.v:183755$11908_Y + attribute \src "libresoc.v:183760.17-183760.96" + wire width 4 $and$libresoc.v:183760$11913_Y + attribute \src "libresoc.v:183757.18-183757.93" + wire width 4 $not$libresoc.v:183757$11910_Y + attribute \src "libresoc.v:183759.17-183759.92" + wire width 4 $not$libresoc.v:183759$11912_Y + attribute \src "libresoc.v:183762.17-183762.92" + wire width 4 $not$libresoc.v:183762$11915_Y + attribute \src "libresoc.v:183756.18-183756.98" + wire width 4 $or$libresoc.v:183756$11909_Y + attribute \src "libresoc.v:183758.18-183758.99" + wire width 4 $or$libresoc.v:183758$11911_Y + attribute \src "libresoc.v:183761.17-183761.97" + wire width 4 $or$libresoc.v:183761$11914_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378426,7 +375236,7 @@ module \req_l$103 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183721.7-183721.15" + attribute \src "libresoc.v:183720.7-183720.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -378443,7 +375253,7 @@ module \req_l$103 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183756$11908 + cell $and $and$libresoc.v:183755$11908 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -378451,10 +375261,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183756$11908_Y + connect \Y $and$libresoc.v:183755$11908_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183761$11913 + cell $and $and$libresoc.v:183760$11913 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -378462,34 +375272,34 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183761$11913_Y + connect \Y $and$libresoc.v:183760$11913_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183758$11910 + cell $not $not$libresoc.v:183757$11910 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:183758$11910_Y + connect \Y $not$libresoc.v:183757$11910_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183760$11912 + cell $not $not$libresoc.v:183759$11912 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:183760$11912_Y + connect \Y $not$libresoc.v:183759$11912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183763$11915 + cell $not $not$libresoc.v:183762$11915 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:183763$11915_Y + connect \Y $not$libresoc.v:183762$11915_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183757$11909 + cell $or $or$libresoc.v:183756$11909 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -378497,10 +375307,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:183757$11909_Y + connect \Y $or$libresoc.v:183756$11909_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183759$11911 + cell $or $or$libresoc.v:183758$11911 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -378508,10 +375318,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:183759$11911_Y + connect \Y $or$libresoc.v:183758$11911_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183762$11914 + cell $or $or$libresoc.v:183761$11914 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -378519,39 +375329,39 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:183762$11914_Y + connect \Y $or$libresoc.v:183761$11914_Y end - attribute \src "libresoc.v:183721.7-183721.20" - process $proc$libresoc.v:183721$11920 + attribute \src "libresoc.v:183720.7-183720.20" + process $proc$libresoc.v:183720$11920 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183743.13-183743.25" - process $proc$libresoc.v:183743$11921 + attribute \src "libresoc.v:183742.13-183742.25" + process $proc$libresoc.v:183742$11921 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:183764.3-183765.27" - process $proc$libresoc.v:183764$11916 + attribute \src "libresoc.v:183763.3-183764.27" + process $proc$libresoc.v:183763$11916 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:183766.3-183774.6" - process $proc$libresoc.v:183766$11917 + attribute \src "libresoc.v:183765.3-183773.6" + process $proc$libresoc.v:183765$11917 assign { } { } assign { } { } assign $0\q_int$next[3:0]$11918 $1\q_int$next[3:0]$11919 - attribute \src "libresoc.v:183767.5-183767.29" + attribute \src "libresoc.v:183766.5-183766.29" switch \initial - attribute \src "libresoc.v:183767.9-183767.17" + attribute \src "libresoc.v:183766.9-183766.17" case 1'1 case end @@ -378567,49 +375377,49 @@ module \req_l$103 sync always update \q_int$next $0\q_int$next[3:0]$11918 end - connect \$9 $and$libresoc.v:183756$11908_Y - connect \$11 $or$libresoc.v:183757$11909_Y - connect \$13 $not$libresoc.v:183758$11910_Y - connect \$15 $or$libresoc.v:183759$11911_Y - connect \$1 $not$libresoc.v:183760$11912_Y - connect \$3 $and$libresoc.v:183761$11913_Y - connect \$5 $or$libresoc.v:183762$11914_Y - connect \$7 $not$libresoc.v:183763$11915_Y + connect \$9 $and$libresoc.v:183755$11908_Y + connect \$11 $or$libresoc.v:183756$11909_Y + connect \$13 $not$libresoc.v:183757$11910_Y + connect \$15 $or$libresoc.v:183758$11911_Y + connect \$1 $not$libresoc.v:183759$11912_Y + connect \$3 $and$libresoc.v:183760$11913_Y + connect \$5 $or$libresoc.v:183761$11914_Y + connect \$7 $not$libresoc.v:183762$11915_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:183782.1-183840.10" +attribute \src "libresoc.v:183781.1-183839.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.req_l" attribute \generator "nMigen" module \req_l$12 - attribute \src "libresoc.v:183783.7-183783.20" + attribute \src "libresoc.v:183782.7-183782.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183828.3-183836.6" + attribute \src "libresoc.v:183827.3-183835.6" wire width 3 $0\q_int$next[2:0]$11932 - attribute \src "libresoc.v:183826.3-183827.27" + attribute \src "libresoc.v:183825.3-183826.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:183828.3-183836.6" + attribute \src "libresoc.v:183827.3-183835.6" wire width 3 $1\q_int$next[2:0]$11933 - attribute \src "libresoc.v:183805.13-183805.25" + attribute \src "libresoc.v:183804.13-183804.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:183818.17-183818.96" - wire width 3 $and$libresoc.v:183818$11922_Y - attribute \src "libresoc.v:183823.17-183823.96" - wire width 3 $and$libresoc.v:183823$11927_Y - attribute \src "libresoc.v:183820.18-183820.93" - wire width 3 $not$libresoc.v:183820$11924_Y - attribute \src "libresoc.v:183822.17-183822.92" - wire width 3 $not$libresoc.v:183822$11926_Y - attribute \src "libresoc.v:183825.17-183825.92" - wire width 3 $not$libresoc.v:183825$11929_Y - attribute \src "libresoc.v:183819.18-183819.98" - wire width 3 $or$libresoc.v:183819$11923_Y - attribute \src "libresoc.v:183821.18-183821.99" - wire width 3 $or$libresoc.v:183821$11925_Y - attribute \src "libresoc.v:183824.17-183824.97" - wire width 3 $or$libresoc.v:183824$11928_Y + attribute \src "libresoc.v:183817.17-183817.96" + wire width 3 $and$libresoc.v:183817$11922_Y + attribute \src "libresoc.v:183822.17-183822.96" + wire width 3 $and$libresoc.v:183822$11927_Y + attribute \src "libresoc.v:183819.18-183819.93" + wire width 3 $not$libresoc.v:183819$11924_Y + attribute \src "libresoc.v:183821.17-183821.92" + wire width 3 $not$libresoc.v:183821$11926_Y + attribute \src "libresoc.v:183824.17-183824.92" + wire width 3 $not$libresoc.v:183824$11929_Y + attribute \src "libresoc.v:183818.18-183818.98" + wire width 3 $or$libresoc.v:183818$11923_Y + attribute \src "libresoc.v:183820.18-183820.99" + wire width 3 $or$libresoc.v:183820$11925_Y + attribute \src "libresoc.v:183823.17-183823.97" + wire width 3 $or$libresoc.v:183823$11928_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378630,7 +375440,7 @@ module \req_l$12 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183783.7-183783.15" + attribute \src "libresoc.v:183782.7-183782.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -378647,7 +375457,7 @@ module \req_l$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183818$11922 + cell $and $and$libresoc.v:183817$11922 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378655,10 +375465,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183818$11922_Y + connect \Y $and$libresoc.v:183817$11922_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183823$11927 + cell $and $and$libresoc.v:183822$11927 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378666,34 +375476,34 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183823$11927_Y + connect \Y $and$libresoc.v:183822$11927_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183820$11924 + cell $not $not$libresoc.v:183819$11924 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:183820$11924_Y + connect \Y $not$libresoc.v:183819$11924_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183822$11926 + cell $not $not$libresoc.v:183821$11926 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183822$11926_Y + connect \Y $not$libresoc.v:183821$11926_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183825$11929 + cell $not $not$libresoc.v:183824$11929 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183825$11929_Y + connect \Y $not$libresoc.v:183824$11929_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183819$11923 + cell $or $or$libresoc.v:183818$11923 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378701,10 +375511,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:183819$11923_Y + connect \Y $or$libresoc.v:183818$11923_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183821$11925 + cell $or $or$libresoc.v:183820$11925 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378712,10 +375522,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:183821$11925_Y + connect \Y $or$libresoc.v:183820$11925_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183824$11928 + cell $or $or$libresoc.v:183823$11928 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378723,39 +375533,39 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:183824$11928_Y + connect \Y $or$libresoc.v:183823$11928_Y end - attribute \src "libresoc.v:183783.7-183783.20" - process $proc$libresoc.v:183783$11934 + attribute \src "libresoc.v:183782.7-183782.20" + process $proc$libresoc.v:183782$11934 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183805.13-183805.25" - process $proc$libresoc.v:183805$11935 + attribute \src "libresoc.v:183804.13-183804.25" + process $proc$libresoc.v:183804$11935 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:183826.3-183827.27" - process $proc$libresoc.v:183826$11930 + attribute \src "libresoc.v:183825.3-183826.27" + process $proc$libresoc.v:183825$11930 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:183828.3-183836.6" - process $proc$libresoc.v:183828$11931 + attribute \src "libresoc.v:183827.3-183835.6" + process $proc$libresoc.v:183827$11931 assign { } { } assign { } { } assign $0\q_int$next[2:0]$11932 $1\q_int$next[2:0]$11933 - attribute \src "libresoc.v:183829.5-183829.29" + attribute \src "libresoc.v:183828.5-183828.29" switch \initial - attribute \src "libresoc.v:183829.9-183829.17" + attribute \src "libresoc.v:183828.9-183828.17" case 1'1 case end @@ -378771,49 +375581,49 @@ module \req_l$12 sync always update \q_int$next $0\q_int$next[2:0]$11932 end - connect \$9 $and$libresoc.v:183818$11922_Y - connect \$11 $or$libresoc.v:183819$11923_Y - connect \$13 $not$libresoc.v:183820$11924_Y - connect \$15 $or$libresoc.v:183821$11925_Y - connect \$1 $not$libresoc.v:183822$11926_Y - connect \$3 $and$libresoc.v:183823$11927_Y - connect \$5 $or$libresoc.v:183824$11928_Y - connect \$7 $not$libresoc.v:183825$11929_Y + connect \$9 $and$libresoc.v:183817$11922_Y + connect \$11 $or$libresoc.v:183818$11923_Y + connect \$13 $not$libresoc.v:183819$11924_Y + connect \$15 $or$libresoc.v:183820$11925_Y + connect \$1 $not$libresoc.v:183821$11926_Y + connect \$3 $and$libresoc.v:183822$11927_Y + connect \$5 $or$libresoc.v:183823$11928_Y + connect \$7 $not$libresoc.v:183824$11929_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:183844.1-183902.10" +attribute \src "libresoc.v:183843.1-183901.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.req_l" attribute \generator "nMigen" module \req_l$121 - attribute \src "libresoc.v:183845.7-183845.20" + attribute \src "libresoc.v:183844.7-183844.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183890.3-183898.6" + attribute \src "libresoc.v:183889.3-183897.6" wire width 3 $0\q_int$next[2:0]$11946 - attribute \src "libresoc.v:183888.3-183889.27" + attribute \src "libresoc.v:183887.3-183888.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:183890.3-183898.6" + attribute \src "libresoc.v:183889.3-183897.6" wire width 3 $1\q_int$next[2:0]$11947 - attribute \src "libresoc.v:183867.13-183867.25" + attribute \src "libresoc.v:183866.13-183866.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:183880.17-183880.96" - wire width 3 $and$libresoc.v:183880$11936_Y - attribute \src "libresoc.v:183885.17-183885.96" - wire width 3 $and$libresoc.v:183885$11941_Y - attribute \src "libresoc.v:183882.18-183882.93" - wire width 3 $not$libresoc.v:183882$11938_Y - attribute \src "libresoc.v:183884.17-183884.92" - wire width 3 $not$libresoc.v:183884$11940_Y - attribute \src "libresoc.v:183887.17-183887.92" - wire width 3 $not$libresoc.v:183887$11943_Y - attribute \src "libresoc.v:183881.18-183881.98" - wire width 3 $or$libresoc.v:183881$11937_Y - attribute \src "libresoc.v:183883.18-183883.99" - wire width 3 $or$libresoc.v:183883$11939_Y - attribute \src "libresoc.v:183886.17-183886.97" - wire width 3 $or$libresoc.v:183886$11942_Y + attribute \src "libresoc.v:183879.17-183879.96" + wire width 3 $and$libresoc.v:183879$11936_Y + attribute \src "libresoc.v:183884.17-183884.96" + wire width 3 $and$libresoc.v:183884$11941_Y + attribute \src "libresoc.v:183881.18-183881.93" + wire width 3 $not$libresoc.v:183881$11938_Y + attribute \src "libresoc.v:183883.17-183883.92" + wire width 3 $not$libresoc.v:183883$11940_Y + attribute \src "libresoc.v:183886.17-183886.92" + wire width 3 $not$libresoc.v:183886$11943_Y + attribute \src "libresoc.v:183880.18-183880.98" + wire width 3 $or$libresoc.v:183880$11937_Y + attribute \src "libresoc.v:183882.18-183882.99" + wire width 3 $or$libresoc.v:183882$11939_Y + attribute \src "libresoc.v:183885.17-183885.97" + wire width 3 $or$libresoc.v:183885$11942_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -378834,7 +375644,7 @@ module \req_l$121 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183845.7-183845.15" + attribute \src "libresoc.v:183844.7-183844.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -378851,7 +375661,7 @@ module \req_l$121 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183880$11936 + cell $and $and$libresoc.v:183879$11936 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378859,10 +375669,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183880$11936_Y + connect \Y $and$libresoc.v:183879$11936_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183885$11941 + cell $and $and$libresoc.v:183884$11941 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378870,34 +375680,34 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183885$11941_Y + connect \Y $and$libresoc.v:183884$11941_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183882$11938 + cell $not $not$libresoc.v:183881$11938 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:183882$11938_Y + connect \Y $not$libresoc.v:183881$11938_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183884$11940 + cell $not $not$libresoc.v:183883$11940 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183884$11940_Y + connect \Y $not$libresoc.v:183883$11940_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183887$11943 + cell $not $not$libresoc.v:183886$11943 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183887$11943_Y + connect \Y $not$libresoc.v:183886$11943_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183881$11937 + cell $or $or$libresoc.v:183880$11937 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378905,10 +375715,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:183881$11937_Y + connect \Y $or$libresoc.v:183880$11937_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183883$11939 + cell $or $or$libresoc.v:183882$11939 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378916,10 +375726,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:183883$11939_Y + connect \Y $or$libresoc.v:183882$11939_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183886$11942 + cell $or $or$libresoc.v:183885$11942 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -378927,39 +375737,39 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:183886$11942_Y + connect \Y $or$libresoc.v:183885$11942_Y end - attribute \src "libresoc.v:183845.7-183845.20" - process $proc$libresoc.v:183845$11948 + attribute \src "libresoc.v:183844.7-183844.20" + process $proc$libresoc.v:183844$11948 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183867.13-183867.25" - process $proc$libresoc.v:183867$11949 + attribute \src "libresoc.v:183866.13-183866.25" + process $proc$libresoc.v:183866$11949 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:183888.3-183889.27" - process $proc$libresoc.v:183888$11944 + attribute \src "libresoc.v:183887.3-183888.27" + process $proc$libresoc.v:183887$11944 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:183890.3-183898.6" - process $proc$libresoc.v:183890$11945 + attribute \src "libresoc.v:183889.3-183897.6" + process $proc$libresoc.v:183889$11945 assign { } { } assign { } { } assign $0\q_int$next[2:0]$11946 $1\q_int$next[2:0]$11947 - attribute \src "libresoc.v:183891.5-183891.29" + attribute \src "libresoc.v:183890.5-183890.29" switch \initial - attribute \src "libresoc.v:183891.9-183891.17" + attribute \src "libresoc.v:183890.9-183890.17" case 1'1 case end @@ -378975,49 +375785,49 @@ module \req_l$121 sync always update \q_int$next $0\q_int$next[2:0]$11946 end - connect \$9 $and$libresoc.v:183880$11936_Y - connect \$11 $or$libresoc.v:183881$11937_Y - connect \$13 $not$libresoc.v:183882$11938_Y - connect \$15 $or$libresoc.v:183883$11939_Y - connect \$1 $not$libresoc.v:183884$11940_Y - connect \$3 $and$libresoc.v:183885$11941_Y - connect \$5 $or$libresoc.v:183886$11942_Y - connect \$7 $not$libresoc.v:183887$11943_Y + connect \$9 $and$libresoc.v:183879$11936_Y + connect \$11 $or$libresoc.v:183880$11937_Y + connect \$13 $not$libresoc.v:183881$11938_Y + connect \$15 $or$libresoc.v:183882$11939_Y + connect \$1 $not$libresoc.v:183883$11940_Y + connect \$3 $and$libresoc.v:183884$11941_Y + connect \$5 $or$libresoc.v:183885$11942_Y + connect \$7 $not$libresoc.v:183886$11943_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:183906.1-183964.10" +attribute \src "libresoc.v:183905.1-183963.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.req_l" attribute \generator "nMigen" module \req_l$25 - attribute \src "libresoc.v:183907.7-183907.20" + attribute \src "libresoc.v:183906.7-183906.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183952.3-183960.6" + attribute \src "libresoc.v:183951.3-183959.6" wire width 3 $0\q_int$next[2:0]$11960 - attribute \src "libresoc.v:183950.3-183951.27" + attribute \src "libresoc.v:183949.3-183950.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:183952.3-183960.6" + attribute \src "libresoc.v:183951.3-183959.6" wire width 3 $1\q_int$next[2:0]$11961 - attribute \src "libresoc.v:183929.13-183929.25" + attribute \src "libresoc.v:183928.13-183928.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:183942.17-183942.96" - wire width 3 $and$libresoc.v:183942$11950_Y - attribute \src "libresoc.v:183947.17-183947.96" - wire width 3 $and$libresoc.v:183947$11955_Y - attribute \src "libresoc.v:183944.18-183944.93" - wire width 3 $not$libresoc.v:183944$11952_Y - attribute \src "libresoc.v:183946.17-183946.92" - wire width 3 $not$libresoc.v:183946$11954_Y - attribute \src "libresoc.v:183949.17-183949.92" - wire width 3 $not$libresoc.v:183949$11957_Y - attribute \src "libresoc.v:183943.18-183943.98" - wire width 3 $or$libresoc.v:183943$11951_Y - attribute \src "libresoc.v:183945.18-183945.99" - wire width 3 $or$libresoc.v:183945$11953_Y - attribute \src "libresoc.v:183948.17-183948.97" - wire width 3 $or$libresoc.v:183948$11956_Y + attribute \src "libresoc.v:183941.17-183941.96" + wire width 3 $and$libresoc.v:183941$11950_Y + attribute \src "libresoc.v:183946.17-183946.96" + wire width 3 $and$libresoc.v:183946$11955_Y + attribute \src "libresoc.v:183943.18-183943.93" + wire width 3 $not$libresoc.v:183943$11952_Y + attribute \src "libresoc.v:183945.17-183945.92" + wire width 3 $not$libresoc.v:183945$11954_Y + attribute \src "libresoc.v:183948.17-183948.92" + wire width 3 $not$libresoc.v:183948$11957_Y + attribute \src "libresoc.v:183942.18-183942.98" + wire width 3 $or$libresoc.v:183942$11951_Y + attribute \src "libresoc.v:183944.18-183944.99" + wire width 3 $or$libresoc.v:183944$11953_Y + attribute \src "libresoc.v:183947.17-183947.97" + wire width 3 $or$libresoc.v:183947$11956_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379038,7 +375848,7 @@ module \req_l$25 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183907.7-183907.15" + attribute \src "libresoc.v:183906.7-183906.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -379055,7 +375865,7 @@ module \req_l$25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183942$11950 + cell $and $and$libresoc.v:183941$11950 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -379063,10 +375873,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183942$11950_Y + connect \Y $and$libresoc.v:183941$11950_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183947$11955 + cell $and $and$libresoc.v:183946$11955 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -379074,34 +375884,34 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183947$11955_Y + connect \Y $and$libresoc.v:183946$11955_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183944$11952 + cell $not $not$libresoc.v:183943$11952 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:183944$11952_Y + connect \Y $not$libresoc.v:183943$11952_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183946$11954 + cell $not $not$libresoc.v:183945$11954 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183946$11954_Y + connect \Y $not$libresoc.v:183945$11954_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183949$11957 + cell $not $not$libresoc.v:183948$11957 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183949$11957_Y + connect \Y $not$libresoc.v:183948$11957_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183943$11951 + cell $or $or$libresoc.v:183942$11951 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -379109,10 +375919,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:183943$11951_Y + connect \Y $or$libresoc.v:183942$11951_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183945$11953 + cell $or $or$libresoc.v:183944$11953 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -379120,10 +375930,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:183945$11953_Y + connect \Y $or$libresoc.v:183944$11953_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183948$11956 + cell $or $or$libresoc.v:183947$11956 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -379131,39 +375941,39 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:183948$11956_Y + connect \Y $or$libresoc.v:183947$11956_Y end - attribute \src "libresoc.v:183907.7-183907.20" - process $proc$libresoc.v:183907$11962 + attribute \src "libresoc.v:183906.7-183906.20" + process $proc$libresoc.v:183906$11962 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183929.13-183929.25" - process $proc$libresoc.v:183929$11963 + attribute \src "libresoc.v:183928.13-183928.25" + process $proc$libresoc.v:183928$11963 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:183950.3-183951.27" - process $proc$libresoc.v:183950$11958 + attribute \src "libresoc.v:183949.3-183950.27" + process $proc$libresoc.v:183949$11958 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:183952.3-183960.6" - process $proc$libresoc.v:183952$11959 + attribute \src "libresoc.v:183951.3-183959.6" + process $proc$libresoc.v:183951$11959 assign { } { } assign { } { } assign $0\q_int$next[2:0]$11960 $1\q_int$next[2:0]$11961 - attribute \src "libresoc.v:183953.5-183953.29" + attribute \src "libresoc.v:183952.5-183952.29" switch \initial - attribute \src "libresoc.v:183953.9-183953.17" + attribute \src "libresoc.v:183952.9-183952.17" case 1'1 case end @@ -379179,49 +375989,49 @@ module \req_l$25 sync always update \q_int$next $0\q_int$next[2:0]$11960 end - connect \$9 $and$libresoc.v:183942$11950_Y - connect \$11 $or$libresoc.v:183943$11951_Y - connect \$13 $not$libresoc.v:183944$11952_Y - connect \$15 $or$libresoc.v:183945$11953_Y - connect \$1 $not$libresoc.v:183946$11954_Y - connect \$3 $and$libresoc.v:183947$11955_Y - connect \$5 $or$libresoc.v:183948$11956_Y - connect \$7 $not$libresoc.v:183949$11957_Y + connect \$9 $and$libresoc.v:183941$11950_Y + connect \$11 $or$libresoc.v:183942$11951_Y + connect \$13 $not$libresoc.v:183943$11952_Y + connect \$15 $or$libresoc.v:183944$11953_Y + connect \$1 $not$libresoc.v:183945$11954_Y + connect \$3 $and$libresoc.v:183946$11955_Y + connect \$5 $or$libresoc.v:183947$11956_Y + connect \$7 $not$libresoc.v:183948$11957_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:183968.1-184026.10" +attribute \src "libresoc.v:183967.1-184025.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.req_l" attribute \generator "nMigen" module \req_l$41 - attribute \src "libresoc.v:183969.7-183969.20" + attribute \src "libresoc.v:183968.7-183968.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184014.3-184022.6" + attribute \src "libresoc.v:184013.3-184021.6" wire width 5 $0\q_int$next[4:0]$11974 - attribute \src "libresoc.v:184012.3-184013.27" + attribute \src "libresoc.v:184011.3-184012.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:184014.3-184022.6" + attribute \src "libresoc.v:184013.3-184021.6" wire width 5 $1\q_int$next[4:0]$11975 - attribute \src "libresoc.v:183991.13-183991.26" + attribute \src "libresoc.v:183990.13-183990.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:184004.17-184004.96" - wire width 5 $and$libresoc.v:184004$11964_Y - attribute \src "libresoc.v:184009.17-184009.96" - wire width 5 $and$libresoc.v:184009$11969_Y - attribute \src "libresoc.v:184006.18-184006.93" - wire width 5 $not$libresoc.v:184006$11966_Y - attribute \src "libresoc.v:184008.17-184008.92" - wire width 5 $not$libresoc.v:184008$11968_Y - attribute \src "libresoc.v:184011.17-184011.92" - wire width 5 $not$libresoc.v:184011$11971_Y - attribute \src "libresoc.v:184005.18-184005.98" - wire width 5 $or$libresoc.v:184005$11965_Y - attribute \src "libresoc.v:184007.18-184007.99" - wire width 5 $or$libresoc.v:184007$11967_Y - attribute \src "libresoc.v:184010.17-184010.97" - wire width 5 $or$libresoc.v:184010$11970_Y + attribute \src "libresoc.v:184003.17-184003.96" + wire width 5 $and$libresoc.v:184003$11964_Y + attribute \src "libresoc.v:184008.17-184008.96" + wire width 5 $and$libresoc.v:184008$11969_Y + attribute \src "libresoc.v:184005.18-184005.93" + wire width 5 $not$libresoc.v:184005$11966_Y + attribute \src "libresoc.v:184007.17-184007.92" + wire width 5 $not$libresoc.v:184007$11968_Y + attribute \src "libresoc.v:184010.17-184010.92" + wire width 5 $not$libresoc.v:184010$11971_Y + attribute \src "libresoc.v:184004.18-184004.98" + wire width 5 $or$libresoc.v:184004$11965_Y + attribute \src "libresoc.v:184006.18-184006.99" + wire width 5 $or$libresoc.v:184006$11967_Y + attribute \src "libresoc.v:184009.17-184009.97" + wire width 5 $or$libresoc.v:184009$11970_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379242,7 +376052,7 @@ module \req_l$41 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:183969.7-183969.15" + attribute \src "libresoc.v:183968.7-183968.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -379259,7 +376069,7 @@ module \req_l$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184004$11964 + cell $and $and$libresoc.v:184003$11964 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -379267,10 +376077,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184004$11964_Y + connect \Y $and$libresoc.v:184003$11964_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184009$11969 + cell $and $and$libresoc.v:184008$11969 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -379278,34 +376088,34 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184009$11969_Y + connect \Y $and$libresoc.v:184008$11969_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184006$11966 + cell $not $not$libresoc.v:184005$11966 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:184006$11966_Y + connect \Y $not$libresoc.v:184005$11966_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184008$11968 + cell $not $not$libresoc.v:184007$11968 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:184008$11968_Y + connect \Y $not$libresoc.v:184007$11968_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184011$11971 + cell $not $not$libresoc.v:184010$11971 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:184011$11971_Y + connect \Y $not$libresoc.v:184010$11971_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184005$11965 + cell $or $or$libresoc.v:184004$11965 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -379313,10 +376123,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184005$11965_Y + connect \Y $or$libresoc.v:184004$11965_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184007$11967 + cell $or $or$libresoc.v:184006$11967 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -379324,10 +376134,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184007$11967_Y + connect \Y $or$libresoc.v:184006$11967_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184010$11970 + cell $or $or$libresoc.v:184009$11970 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -379335,39 +376145,39 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184010$11970_Y + connect \Y $or$libresoc.v:184009$11970_Y end - attribute \src "libresoc.v:183969.7-183969.20" - process $proc$libresoc.v:183969$11976 + attribute \src "libresoc.v:183968.7-183968.20" + process $proc$libresoc.v:183968$11976 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183991.13-183991.26" - process $proc$libresoc.v:183991$11977 + attribute \src "libresoc.v:183990.13-183990.26" + process $proc$libresoc.v:183990$11977 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:184012.3-184013.27" - process $proc$libresoc.v:184012$11972 + attribute \src "libresoc.v:184011.3-184012.27" + process $proc$libresoc.v:184011$11972 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:184014.3-184022.6" - process $proc$libresoc.v:184014$11973 + attribute \src "libresoc.v:184013.3-184021.6" + process $proc$libresoc.v:184013$11973 assign { } { } assign { } { } assign $0\q_int$next[4:0]$11974 $1\q_int$next[4:0]$11975 - attribute \src "libresoc.v:184015.5-184015.29" + attribute \src "libresoc.v:184014.5-184014.29" switch \initial - attribute \src "libresoc.v:184015.9-184015.17" + attribute \src "libresoc.v:184014.9-184014.17" case 1'1 case end @@ -379383,49 +376193,49 @@ module \req_l$41 sync always update \q_int$next $0\q_int$next[4:0]$11974 end - connect \$9 $and$libresoc.v:184004$11964_Y - connect \$11 $or$libresoc.v:184005$11965_Y - connect \$13 $not$libresoc.v:184006$11966_Y - connect \$15 $or$libresoc.v:184007$11967_Y - connect \$1 $not$libresoc.v:184008$11968_Y - connect \$3 $and$libresoc.v:184009$11969_Y - connect \$5 $or$libresoc.v:184010$11970_Y - connect \$7 $not$libresoc.v:184011$11971_Y + connect \$9 $and$libresoc.v:184003$11964_Y + connect \$11 $or$libresoc.v:184004$11965_Y + connect \$13 $not$libresoc.v:184005$11966_Y + connect \$15 $or$libresoc.v:184006$11967_Y + connect \$1 $not$libresoc.v:184007$11968_Y + connect \$3 $and$libresoc.v:184008$11969_Y + connect \$5 $or$libresoc.v:184009$11970_Y + connect \$7 $not$libresoc.v:184010$11971_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184030.1-184088.10" +attribute \src "libresoc.v:184029.1-184087.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.req_l" attribute \generator "nMigen" module \req_l$57 - attribute \src "libresoc.v:184031.7-184031.20" + attribute \src "libresoc.v:184030.7-184030.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184076.3-184084.6" + attribute \src "libresoc.v:184075.3-184083.6" wire width 2 $0\q_int$next[1:0]$11988 - attribute \src "libresoc.v:184074.3-184075.27" + attribute \src "libresoc.v:184073.3-184074.27" wire width 2 $0\q_int[1:0] - attribute \src "libresoc.v:184076.3-184084.6" + attribute \src "libresoc.v:184075.3-184083.6" wire width 2 $1\q_int$next[1:0]$11989 - attribute \src "libresoc.v:184053.13-184053.25" + attribute \src "libresoc.v:184052.13-184052.25" wire width 2 $1\q_int[1:0] - attribute \src "libresoc.v:184066.17-184066.96" - wire width 2 $and$libresoc.v:184066$11978_Y - attribute \src "libresoc.v:184071.17-184071.96" - wire width 2 $and$libresoc.v:184071$11983_Y - attribute \src "libresoc.v:184068.18-184068.93" - wire width 2 $not$libresoc.v:184068$11980_Y - attribute \src "libresoc.v:184070.17-184070.92" - wire width 2 $not$libresoc.v:184070$11982_Y - attribute \src "libresoc.v:184073.17-184073.92" - wire width 2 $not$libresoc.v:184073$11985_Y - attribute \src "libresoc.v:184067.18-184067.98" - wire width 2 $or$libresoc.v:184067$11979_Y - attribute \src "libresoc.v:184069.18-184069.99" - wire width 2 $or$libresoc.v:184069$11981_Y - attribute \src "libresoc.v:184072.17-184072.97" - wire width 2 $or$libresoc.v:184072$11984_Y + attribute \src "libresoc.v:184065.17-184065.96" + wire width 2 $and$libresoc.v:184065$11978_Y + attribute \src "libresoc.v:184070.17-184070.96" + wire width 2 $and$libresoc.v:184070$11983_Y + attribute \src "libresoc.v:184067.18-184067.93" + wire width 2 $not$libresoc.v:184067$11980_Y + attribute \src "libresoc.v:184069.17-184069.92" + wire width 2 $not$libresoc.v:184069$11982_Y + attribute \src "libresoc.v:184072.17-184072.92" + wire width 2 $not$libresoc.v:184072$11985_Y + attribute \src "libresoc.v:184066.18-184066.98" + wire width 2 $or$libresoc.v:184066$11979_Y + attribute \src "libresoc.v:184068.18-184068.99" + wire width 2 $or$libresoc.v:184068$11981_Y + attribute \src "libresoc.v:184071.17-184071.97" + wire width 2 $or$libresoc.v:184071$11984_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379446,7 +376256,7 @@ module \req_l$57 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:184031.7-184031.15" + attribute \src "libresoc.v:184030.7-184030.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 2 \q_int @@ -379463,7 +376273,7 @@ module \req_l$57 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 2 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184066$11978 + cell $and $and$libresoc.v:184065$11978 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -379471,10 +376281,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184066$11978_Y + connect \Y $and$libresoc.v:184065$11978_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184071$11983 + cell $and $and$libresoc.v:184070$11983 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -379482,34 +376292,34 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184071$11983_Y + connect \Y $and$libresoc.v:184070$11983_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184068$11980 + cell $not $not$libresoc.v:184067$11980 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \q_req - connect \Y $not$libresoc.v:184068$11980_Y + connect \Y $not$libresoc.v:184067$11980_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184070$11982 + cell $not $not$libresoc.v:184069$11982 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:184070$11982_Y + connect \Y $not$libresoc.v:184069$11982_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184073$11985 + cell $not $not$libresoc.v:184072$11985 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:184073$11985_Y + connect \Y $not$libresoc.v:184072$11985_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184067$11979 + cell $or $or$libresoc.v:184066$11979 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -379517,10 +376327,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184067$11979_Y + connect \Y $or$libresoc.v:184066$11979_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184069$11981 + cell $or $or$libresoc.v:184068$11981 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -379528,10 +376338,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184069$11981_Y + connect \Y $or$libresoc.v:184068$11981_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184072$11984 + cell $or $or$libresoc.v:184071$11984 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -379539,39 +376349,39 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184072$11984_Y + connect \Y $or$libresoc.v:184071$11984_Y end - attribute \src "libresoc.v:184031.7-184031.20" - process $proc$libresoc.v:184031$11990 + attribute \src "libresoc.v:184030.7-184030.20" + process $proc$libresoc.v:184030$11990 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184053.13-184053.25" - process $proc$libresoc.v:184053$11991 + attribute \src "libresoc.v:184052.13-184052.25" + process $proc$libresoc.v:184052$11991 assign { } { } assign $1\q_int[1:0] 2'00 sync always sync init update \q_int $1\q_int[1:0] end - attribute \src "libresoc.v:184074.3-184075.27" - process $proc$libresoc.v:184074$11986 + attribute \src "libresoc.v:184073.3-184074.27" + process $proc$libresoc.v:184073$11986 assign { } { } assign $0\q_int[1:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[1:0] end - attribute \src "libresoc.v:184076.3-184084.6" - process $proc$libresoc.v:184076$11987 + attribute \src "libresoc.v:184075.3-184083.6" + process $proc$libresoc.v:184075$11987 assign { } { } assign { } { } assign $0\q_int$next[1:0]$11988 $1\q_int$next[1:0]$11989 - attribute \src "libresoc.v:184077.5-184077.29" + attribute \src "libresoc.v:184076.5-184076.29" switch \initial - attribute \src "libresoc.v:184077.9-184077.17" + attribute \src "libresoc.v:184076.9-184076.17" case 1'1 case end @@ -379587,49 +376397,49 @@ module \req_l$57 sync always update \q_int$next $0\q_int$next[1:0]$11988 end - connect \$9 $and$libresoc.v:184066$11978_Y - connect \$11 $or$libresoc.v:184067$11979_Y - connect \$13 $not$libresoc.v:184068$11980_Y - connect \$15 $or$libresoc.v:184069$11981_Y - connect \$1 $not$libresoc.v:184070$11982_Y - connect \$3 $and$libresoc.v:184071$11983_Y - connect \$5 $or$libresoc.v:184072$11984_Y - connect \$7 $not$libresoc.v:184073$11985_Y + connect \$9 $and$libresoc.v:184065$11978_Y + connect \$11 $or$libresoc.v:184066$11979_Y + connect \$13 $not$libresoc.v:184067$11980_Y + connect \$15 $or$libresoc.v:184068$11981_Y + connect \$1 $not$libresoc.v:184069$11982_Y + connect \$3 $and$libresoc.v:184070$11983_Y + connect \$5 $or$libresoc.v:184071$11984_Y + connect \$7 $not$libresoc.v:184072$11985_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184092.1-184150.10" +attribute \src "libresoc.v:184091.1-184149.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.req_l" attribute \generator "nMigen" module \req_l$69 - attribute \src "libresoc.v:184093.7-184093.20" + attribute \src "libresoc.v:184092.7-184092.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184138.3-184146.6" + attribute \src "libresoc.v:184137.3-184145.6" wire width 6 $0\q_int$next[5:0]$12002 - attribute \src "libresoc.v:184136.3-184137.27" + attribute \src "libresoc.v:184135.3-184136.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:184138.3-184146.6" + attribute \src "libresoc.v:184137.3-184145.6" wire width 6 $1\q_int$next[5:0]$12003 - attribute \src "libresoc.v:184115.13-184115.26" + attribute \src "libresoc.v:184114.13-184114.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:184128.17-184128.96" - wire width 6 $and$libresoc.v:184128$11992_Y - attribute \src "libresoc.v:184133.17-184133.96" - wire width 6 $and$libresoc.v:184133$11997_Y - attribute \src "libresoc.v:184130.18-184130.93" - wire width 6 $not$libresoc.v:184130$11994_Y - attribute \src "libresoc.v:184132.17-184132.92" - wire width 6 $not$libresoc.v:184132$11996_Y - attribute \src "libresoc.v:184135.17-184135.92" - wire width 6 $not$libresoc.v:184135$11999_Y - attribute \src "libresoc.v:184129.18-184129.98" - wire width 6 $or$libresoc.v:184129$11993_Y - attribute \src "libresoc.v:184131.18-184131.99" - wire width 6 $or$libresoc.v:184131$11995_Y - attribute \src "libresoc.v:184134.17-184134.97" - wire width 6 $or$libresoc.v:184134$11998_Y + attribute \src "libresoc.v:184127.17-184127.96" + wire width 6 $and$libresoc.v:184127$11992_Y + attribute \src "libresoc.v:184132.17-184132.96" + wire width 6 $and$libresoc.v:184132$11997_Y + attribute \src "libresoc.v:184129.18-184129.93" + wire width 6 $not$libresoc.v:184129$11994_Y + attribute \src "libresoc.v:184131.17-184131.92" + wire width 6 $not$libresoc.v:184131$11996_Y + attribute \src "libresoc.v:184134.17-184134.92" + wire width 6 $not$libresoc.v:184134$11999_Y + attribute \src "libresoc.v:184128.18-184128.98" + wire width 6 $or$libresoc.v:184128$11993_Y + attribute \src "libresoc.v:184130.18-184130.99" + wire width 6 $or$libresoc.v:184130$11995_Y + attribute \src "libresoc.v:184133.17-184133.97" + wire width 6 $or$libresoc.v:184133$11998_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379650,7 +376460,7 @@ module \req_l$69 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:184093.7-184093.15" + attribute \src "libresoc.v:184092.7-184092.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -379667,7 +376477,7 @@ module \req_l$69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184128$11992 + cell $and $and$libresoc.v:184127$11992 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -379675,10 +376485,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184128$11992_Y + connect \Y $and$libresoc.v:184127$11992_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184133$11997 + cell $and $and$libresoc.v:184132$11997 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -379686,34 +376496,34 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184133$11997_Y + connect \Y $and$libresoc.v:184132$11997_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184130$11994 + cell $not $not$libresoc.v:184129$11994 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_req - connect \Y $not$libresoc.v:184130$11994_Y + connect \Y $not$libresoc.v:184129$11994_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184132$11996 + cell $not $not$libresoc.v:184131$11996 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:184132$11996_Y + connect \Y $not$libresoc.v:184131$11996_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184135$11999 + cell $not $not$libresoc.v:184134$11999 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:184135$11999_Y + connect \Y $not$libresoc.v:184134$11999_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184129$11993 + cell $or $or$libresoc.v:184128$11993 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -379721,10 +376531,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184129$11993_Y + connect \Y $or$libresoc.v:184128$11993_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184131$11995 + cell $or $or$libresoc.v:184130$11995 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -379732,10 +376542,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184131$11995_Y + connect \Y $or$libresoc.v:184130$11995_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184134$11998 + cell $or $or$libresoc.v:184133$11998 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -379743,39 +376553,39 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184134$11998_Y + connect \Y $or$libresoc.v:184133$11998_Y end - attribute \src "libresoc.v:184093.7-184093.20" - process $proc$libresoc.v:184093$12004 + attribute \src "libresoc.v:184092.7-184092.20" + process $proc$libresoc.v:184092$12004 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184115.13-184115.26" - process $proc$libresoc.v:184115$12005 + attribute \src "libresoc.v:184114.13-184114.26" + process $proc$libresoc.v:184114$12005 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:184136.3-184137.27" - process $proc$libresoc.v:184136$12000 + attribute \src "libresoc.v:184135.3-184136.27" + process $proc$libresoc.v:184135$12000 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:184138.3-184146.6" - process $proc$libresoc.v:184138$12001 + attribute \src "libresoc.v:184137.3-184145.6" + process $proc$libresoc.v:184137$12001 assign { } { } assign { } { } assign $0\q_int$next[5:0]$12002 $1\q_int$next[5:0]$12003 - attribute \src "libresoc.v:184139.5-184139.29" + attribute \src "libresoc.v:184138.5-184138.29" switch \initial - attribute \src "libresoc.v:184139.9-184139.17" + attribute \src "libresoc.v:184138.9-184138.17" case 1'1 case end @@ -379791,49 +376601,49 @@ module \req_l$69 sync always update \q_int$next $0\q_int$next[5:0]$12002 end - connect \$9 $and$libresoc.v:184128$11992_Y - connect \$11 $or$libresoc.v:184129$11993_Y - connect \$13 $not$libresoc.v:184130$11994_Y - connect \$15 $or$libresoc.v:184131$11995_Y - connect \$1 $not$libresoc.v:184132$11996_Y - connect \$3 $and$libresoc.v:184133$11997_Y - connect \$5 $or$libresoc.v:184134$11998_Y - connect \$7 $not$libresoc.v:184135$11999_Y + connect \$9 $and$libresoc.v:184127$11992_Y + connect \$11 $or$libresoc.v:184128$11993_Y + connect \$13 $not$libresoc.v:184129$11994_Y + connect \$15 $or$libresoc.v:184130$11995_Y + connect \$1 $not$libresoc.v:184131$11996_Y + connect \$3 $and$libresoc.v:184132$11997_Y + connect \$5 $or$libresoc.v:184133$11998_Y + connect \$7 $not$libresoc.v:184134$11999_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184154.1-184212.10" +attribute \src "libresoc.v:184153.1-184211.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.req_l" attribute \generator "nMigen" module \req_l$86 - attribute \src "libresoc.v:184155.7-184155.20" + attribute \src "libresoc.v:184154.7-184154.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184200.3-184208.6" + attribute \src "libresoc.v:184199.3-184207.6" wire width 4 $0\q_int$next[3:0]$12016 - attribute \src "libresoc.v:184198.3-184199.27" + attribute \src "libresoc.v:184197.3-184198.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:184200.3-184208.6" + attribute \src "libresoc.v:184199.3-184207.6" wire width 4 $1\q_int$next[3:0]$12017 - attribute \src "libresoc.v:184177.13-184177.25" + attribute \src "libresoc.v:184176.13-184176.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:184190.17-184190.96" - wire width 4 $and$libresoc.v:184190$12006_Y - attribute \src "libresoc.v:184195.17-184195.96" - wire width 4 $and$libresoc.v:184195$12011_Y - attribute \src "libresoc.v:184192.18-184192.93" - wire width 4 $not$libresoc.v:184192$12008_Y - attribute \src "libresoc.v:184194.17-184194.92" - wire width 4 $not$libresoc.v:184194$12010_Y - attribute \src "libresoc.v:184197.17-184197.92" - wire width 4 $not$libresoc.v:184197$12013_Y - attribute \src "libresoc.v:184191.18-184191.98" - wire width 4 $or$libresoc.v:184191$12007_Y - attribute \src "libresoc.v:184193.18-184193.99" - wire width 4 $or$libresoc.v:184193$12009_Y - attribute \src "libresoc.v:184196.17-184196.97" - wire width 4 $or$libresoc.v:184196$12012_Y + attribute \src "libresoc.v:184189.17-184189.96" + wire width 4 $and$libresoc.v:184189$12006_Y + attribute \src "libresoc.v:184194.17-184194.96" + wire width 4 $and$libresoc.v:184194$12011_Y + attribute \src "libresoc.v:184191.18-184191.93" + wire width 4 $not$libresoc.v:184191$12008_Y + attribute \src "libresoc.v:184193.17-184193.92" + wire width 4 $not$libresoc.v:184193$12010_Y + attribute \src "libresoc.v:184196.17-184196.92" + wire width 4 $not$libresoc.v:184196$12013_Y + attribute \src "libresoc.v:184190.18-184190.98" + wire width 4 $or$libresoc.v:184190$12007_Y + attribute \src "libresoc.v:184192.18-184192.99" + wire width 4 $or$libresoc.v:184192$12009_Y + attribute \src "libresoc.v:184195.17-184195.97" + wire width 4 $or$libresoc.v:184195$12012_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379854,7 +376664,7 @@ module \req_l$86 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:184155.7-184155.15" + attribute \src "libresoc.v:184154.7-184154.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -379871,7 +376681,7 @@ module \req_l$86 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184190$12006 + cell $and $and$libresoc.v:184189$12006 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -379879,10 +376689,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184190$12006_Y + connect \Y $and$libresoc.v:184189$12006_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184195$12011 + cell $and $and$libresoc.v:184194$12011 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -379890,34 +376700,34 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184195$12011_Y + connect \Y $and$libresoc.v:184194$12011_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184192$12008 + cell $not $not$libresoc.v:184191$12008 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:184192$12008_Y + connect \Y $not$libresoc.v:184191$12008_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184194$12010 + cell $not $not$libresoc.v:184193$12010 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:184194$12010_Y + connect \Y $not$libresoc.v:184193$12010_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184197$12013 + cell $not $not$libresoc.v:184196$12013 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:184197$12013_Y + connect \Y $not$libresoc.v:184196$12013_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184191$12007 + cell $or $or$libresoc.v:184190$12007 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -379925,10 +376735,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184191$12007_Y + connect \Y $or$libresoc.v:184190$12007_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184193$12009 + cell $or $or$libresoc.v:184192$12009 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -379936,10 +376746,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184193$12009_Y + connect \Y $or$libresoc.v:184192$12009_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184196$12012 + cell $or $or$libresoc.v:184195$12012 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -379947,39 +376757,39 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184196$12012_Y + connect \Y $or$libresoc.v:184195$12012_Y end - attribute \src "libresoc.v:184155.7-184155.20" - process $proc$libresoc.v:184155$12018 + attribute \src "libresoc.v:184154.7-184154.20" + process $proc$libresoc.v:184154$12018 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184177.13-184177.25" - process $proc$libresoc.v:184177$12019 + attribute \src "libresoc.v:184176.13-184176.25" + process $proc$libresoc.v:184176$12019 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:184198.3-184199.27" - process $proc$libresoc.v:184198$12014 + attribute \src "libresoc.v:184197.3-184198.27" + process $proc$libresoc.v:184197$12014 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:184200.3-184208.6" - process $proc$libresoc.v:184200$12015 + attribute \src "libresoc.v:184199.3-184207.6" + process $proc$libresoc.v:184199$12015 assign { } { } assign { } { } assign $0\q_int$next[3:0]$12016 $1\q_int$next[3:0]$12017 - attribute \src "libresoc.v:184201.5-184201.29" + attribute \src "libresoc.v:184200.5-184200.29" switch \initial - attribute \src "libresoc.v:184201.9-184201.17" + attribute \src "libresoc.v:184200.9-184200.17" case 1'1 case end @@ -379995,43 +376805,43 @@ module \req_l$86 sync always update \q_int$next $0\q_int$next[3:0]$12016 end - connect \$9 $and$libresoc.v:184190$12006_Y - connect \$11 $or$libresoc.v:184191$12007_Y - connect \$13 $not$libresoc.v:184192$12008_Y - connect \$15 $or$libresoc.v:184193$12009_Y - connect \$1 $not$libresoc.v:184194$12010_Y - connect \$3 $and$libresoc.v:184195$12011_Y - connect \$5 $or$libresoc.v:184196$12012_Y - connect \$7 $not$libresoc.v:184197$12013_Y + connect \$9 $and$libresoc.v:184189$12006_Y + connect \$11 $or$libresoc.v:184190$12007_Y + connect \$13 $not$libresoc.v:184191$12008_Y + connect \$15 $or$libresoc.v:184192$12009_Y + connect \$1 $not$libresoc.v:184193$12010_Y + connect \$3 $and$libresoc.v:184194$12011_Y + connect \$5 $or$libresoc.v:184195$12012_Y + connect \$7 $not$libresoc.v:184196$12013_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184216.1-184265.10" +attribute \src "libresoc.v:184215.1-184264.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.reset_l" attribute \generator "nMigen" module \reset_l - attribute \src "libresoc.v:184217.7-184217.20" + attribute \src "libresoc.v:184216.7-184216.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184253.3-184261.6" + attribute \src "libresoc.v:184252.3-184260.6" wire $0\q_int$next[0:0]$12027 - attribute \src "libresoc.v:184251.3-184252.27" + attribute \src "libresoc.v:184250.3-184251.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:184253.3-184261.6" + attribute \src "libresoc.v:184252.3-184260.6" wire $1\q_int$next[0:0]$12028 - attribute \src "libresoc.v:184233.7-184233.19" + attribute \src "libresoc.v:184232.7-184232.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:184248.17-184248.96" - wire $and$libresoc.v:184248$12022_Y - attribute \src "libresoc.v:184247.17-184247.94" - wire $not$libresoc.v:184247$12021_Y - attribute \src "libresoc.v:184250.17-184250.94" - wire $not$libresoc.v:184250$12024_Y - attribute \src "libresoc.v:184246.17-184246.100" - wire $or$libresoc.v:184246$12020_Y - attribute \src "libresoc.v:184249.17-184249.99" - wire $or$libresoc.v:184249$12023_Y + attribute \src "libresoc.v:184247.17-184247.96" + wire $and$libresoc.v:184247$12022_Y + attribute \src "libresoc.v:184246.17-184246.94" + wire $not$libresoc.v:184246$12021_Y + attribute \src "libresoc.v:184249.17-184249.94" + wire $not$libresoc.v:184249$12024_Y + attribute \src "libresoc.v:184245.17-184245.100" + wire $or$libresoc.v:184245$12020_Y + attribute \src "libresoc.v:184248.17-184248.99" + wire $or$libresoc.v:184248$12023_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -380046,7 +376856,7 @@ module \reset_l wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:184217.7-184217.15" + attribute \src "libresoc.v:184216.7-184216.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -380063,7 +376873,7 @@ module \reset_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184248$12022 + cell $and $and$libresoc.v:184247$12022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380071,26 +376881,26 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184248$12022_Y + connect \Y $and$libresoc.v:184247$12022_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184247$12021 + cell $not $not$libresoc.v:184246$12021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:184247$12021_Y + connect \Y $not$libresoc.v:184246$12021_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184250$12024 + cell $not $not$libresoc.v:184249$12024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:184250$12024_Y + connect \Y $not$libresoc.v:184249$12024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184246$12020 + cell $or $or$libresoc.v:184245$12020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380098,10 +376908,10 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:184246$12020_Y + connect \Y $or$libresoc.v:184245$12020_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184249$12023 + cell $or $or$libresoc.v:184248$12023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380109,39 +376919,39 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:184249$12023_Y + connect \Y $or$libresoc.v:184248$12023_Y end - attribute \src "libresoc.v:184217.7-184217.20" - process $proc$libresoc.v:184217$12029 + attribute \src "libresoc.v:184216.7-184216.20" + process $proc$libresoc.v:184216$12029 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184233.7-184233.19" - process $proc$libresoc.v:184233$12030 + attribute \src "libresoc.v:184232.7-184232.19" + process $proc$libresoc.v:184232$12030 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:184251.3-184252.27" - process $proc$libresoc.v:184251$12025 + attribute \src "libresoc.v:184250.3-184251.27" + process $proc$libresoc.v:184250$12025 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:184253.3-184261.6" - process $proc$libresoc.v:184253$12026 + attribute \src "libresoc.v:184252.3-184260.6" + process $proc$libresoc.v:184252$12026 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12027 $1\q_int$next[0:0]$12028 - attribute \src "libresoc.v:184254.5-184254.29" + attribute \src "libresoc.v:184253.5-184253.29" switch \initial - attribute \src "libresoc.v:184254.9-184254.17" + attribute \src "libresoc.v:184253.9-184253.17" case 1'1 case end @@ -380157,40 +376967,40 @@ module \reset_l sync always update \q_int$next $0\q_int$next[0:0]$12027 end - connect \$9 $or$libresoc.v:184246$12020_Y - connect \$1 $not$libresoc.v:184247$12021_Y - connect \$3 $and$libresoc.v:184248$12022_Y - connect \$5 $or$libresoc.v:184249$12023_Y - connect \$7 $not$libresoc.v:184250$12024_Y + connect \$9 $or$libresoc.v:184245$12020_Y + connect \$1 $not$libresoc.v:184246$12021_Y + connect \$3 $and$libresoc.v:184247$12022_Y + connect \$5 $or$libresoc.v:184248$12023_Y + connect \$7 $not$libresoc.v:184249$12024_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:184269.1-184318.10" +attribute \src "libresoc.v:184268.1-184317.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.reset_l" attribute \generator "nMigen" module \reset_l$131 - attribute \src "libresoc.v:184270.7-184270.20" + attribute \src "libresoc.v:184269.7-184269.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184306.3-184314.6" + attribute \src "libresoc.v:184305.3-184313.6" wire $0\q_int$next[0:0]$12038 - attribute \src "libresoc.v:184304.3-184305.27" + attribute \src "libresoc.v:184303.3-184304.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:184306.3-184314.6" + attribute \src "libresoc.v:184305.3-184313.6" wire $1\q_int$next[0:0]$12039 - attribute \src "libresoc.v:184286.7-184286.19" + attribute \src "libresoc.v:184285.7-184285.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:184301.17-184301.96" - wire $and$libresoc.v:184301$12033_Y - attribute \src "libresoc.v:184300.17-184300.94" - wire $not$libresoc.v:184300$12032_Y - attribute \src "libresoc.v:184303.17-184303.94" - wire $not$libresoc.v:184303$12035_Y - attribute \src "libresoc.v:184299.17-184299.100" - wire $or$libresoc.v:184299$12031_Y - attribute \src "libresoc.v:184302.17-184302.99" - wire $or$libresoc.v:184302$12034_Y + attribute \src "libresoc.v:184300.17-184300.96" + wire $and$libresoc.v:184300$12033_Y + attribute \src "libresoc.v:184299.17-184299.94" + wire $not$libresoc.v:184299$12032_Y + attribute \src "libresoc.v:184302.17-184302.94" + wire $not$libresoc.v:184302$12035_Y + attribute \src "libresoc.v:184298.17-184298.100" + wire $or$libresoc.v:184298$12031_Y + attribute \src "libresoc.v:184301.17-184301.99" + wire $or$libresoc.v:184301$12034_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -380205,7 +377015,7 @@ module \reset_l$131 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:184270.7-184270.15" + attribute \src "libresoc.v:184269.7-184269.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -380222,7 +377032,7 @@ module \reset_l$131 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184301$12033 + cell $and $and$libresoc.v:184300$12033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380230,26 +377040,26 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184301$12033_Y + connect \Y $and$libresoc.v:184300$12033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184300$12032 + cell $not $not$libresoc.v:184299$12032 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:184300$12032_Y + connect \Y $not$libresoc.v:184299$12032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184303$12035 + cell $not $not$libresoc.v:184302$12035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:184303$12035_Y + connect \Y $not$libresoc.v:184302$12035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184299$12031 + cell $or $or$libresoc.v:184298$12031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380257,10 +377067,10 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:184299$12031_Y + connect \Y $or$libresoc.v:184298$12031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184302$12034 + cell $or $or$libresoc.v:184301$12034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380268,39 +377078,39 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:184302$12034_Y + connect \Y $or$libresoc.v:184301$12034_Y end - attribute \src "libresoc.v:184270.7-184270.20" - process $proc$libresoc.v:184270$12040 + attribute \src "libresoc.v:184269.7-184269.20" + process $proc$libresoc.v:184269$12040 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184286.7-184286.19" - process $proc$libresoc.v:184286$12041 + attribute \src "libresoc.v:184285.7-184285.19" + process $proc$libresoc.v:184285$12041 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:184304.3-184305.27" - process $proc$libresoc.v:184304$12036 + attribute \src "libresoc.v:184303.3-184304.27" + process $proc$libresoc.v:184303$12036 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:184306.3-184314.6" - process $proc$libresoc.v:184306$12037 + attribute \src "libresoc.v:184305.3-184313.6" + process $proc$libresoc.v:184305$12037 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12038 $1\q_int$next[0:0]$12039 - attribute \src "libresoc.v:184307.5-184307.29" + attribute \src "libresoc.v:184306.5-184306.29" switch \initial - attribute \src "libresoc.v:184307.9-184307.17" + attribute \src "libresoc.v:184306.9-184306.17" case 1'1 case end @@ -380316,280 +377126,280 @@ module \reset_l$131 sync always update \q_int$next $0\q_int$next[0:0]$12038 end - connect \$9 $or$libresoc.v:184299$12031_Y - connect \$1 $not$libresoc.v:184300$12032_Y - connect \$3 $and$libresoc.v:184301$12033_Y - connect \$5 $or$libresoc.v:184302$12034_Y - connect \$7 $not$libresoc.v:184303$12035_Y + connect \$9 $or$libresoc.v:184298$12031_Y + connect \$1 $not$libresoc.v:184299$12032_Y + connect \$3 $and$libresoc.v:184300$12033_Y + connect \$5 $or$libresoc.v:184301$12034_Y + connect \$7 $not$libresoc.v:184302$12035_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:184322.1-184909.10" +attribute \src "libresoc.v:184321.1-184908.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" attribute \generator "nMigen" module \right_mask - attribute \src "libresoc.v:184323.7-184323.20" + attribute \src "libresoc.v:184322.7-184322.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $10\mask[9:9] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $11\mask[10:10] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $12\mask[11:11] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $13\mask[12:12] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $14\mask[13:13] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $15\mask[14:14] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $16\mask[15:15] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $17\mask[16:16] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $18\mask[17:17] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $19\mask[18:18] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $1\mask[0:0] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $20\mask[19:19] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $21\mask[20:20] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $22\mask[21:21] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $23\mask[22:22] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $24\mask[23:23] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $25\mask[24:24] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $26\mask[25:25] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $27\mask[26:26] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $28\mask[27:27] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $29\mask[28:28] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $2\mask[1:1] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $30\mask[29:29] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $31\mask[30:30] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $32\mask[31:31] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $33\mask[32:32] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $34\mask[33:33] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $35\mask[34:34] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $36\mask[35:35] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $37\mask[36:36] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $38\mask[37:37] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $39\mask[38:38] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $3\mask[2:2] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $40\mask[39:39] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $41\mask[40:40] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $42\mask[41:41] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $43\mask[42:42] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $44\mask[43:43] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $45\mask[44:44] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $46\mask[45:45] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $47\mask[46:46] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $48\mask[47:47] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $49\mask[48:48] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $4\mask[3:3] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $50\mask[49:49] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $51\mask[50:50] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $52\mask[51:51] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $53\mask[52:52] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $54\mask[53:53] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $55\mask[54:54] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $56\mask[55:55] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $57\mask[56:56] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $58\mask[57:57] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $59\mask[58:58] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $5\mask[4:4] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $60\mask[59:59] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $61\mask[60:60] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $62\mask[61:61] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $63\mask[62:62] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $64\mask[63:63] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $6\mask[5:5] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $7\mask[6:6] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $8\mask[7:7] - attribute \src "libresoc.v:184521.3-184908.6" + attribute \src "libresoc.v:184520.3-184907.6" wire $9\mask[8:8] - attribute \src "libresoc.v:184457.17-184457.96" - wire $gt$libresoc.v:184457$12042_Y - attribute \src "libresoc.v:184458.18-184458.98" - wire $gt$libresoc.v:184458$12043_Y + attribute \src "libresoc.v:184456.17-184456.96" + wire $gt$libresoc.v:184456$12042_Y + attribute \src "libresoc.v:184457.18-184457.98" + wire $gt$libresoc.v:184457$12043_Y + attribute \src "libresoc.v:184458.19-184458.99" + wire $gt$libresoc.v:184458$12044_Y attribute \src "libresoc.v:184459.19-184459.99" - wire $gt$libresoc.v:184459$12044_Y + wire $gt$libresoc.v:184459$12045_Y attribute \src "libresoc.v:184460.19-184460.99" - wire $gt$libresoc.v:184460$12045_Y + wire $gt$libresoc.v:184460$12046_Y attribute \src "libresoc.v:184461.19-184461.99" - wire $gt$libresoc.v:184461$12046_Y + wire $gt$libresoc.v:184461$12047_Y attribute \src "libresoc.v:184462.19-184462.99" - wire $gt$libresoc.v:184462$12047_Y + wire $gt$libresoc.v:184462$12048_Y attribute \src "libresoc.v:184463.19-184463.99" - wire $gt$libresoc.v:184463$12048_Y + wire $gt$libresoc.v:184463$12049_Y attribute \src "libresoc.v:184464.19-184464.99" - wire $gt$libresoc.v:184464$12049_Y + wire $gt$libresoc.v:184464$12050_Y attribute \src "libresoc.v:184465.19-184465.99" - wire $gt$libresoc.v:184465$12050_Y + wire $gt$libresoc.v:184465$12051_Y attribute \src "libresoc.v:184466.19-184466.99" - wire $gt$libresoc.v:184466$12051_Y - attribute \src "libresoc.v:184467.19-184467.99" - wire $gt$libresoc.v:184467$12052_Y - attribute \src "libresoc.v:184468.18-184468.97" - wire $gt$libresoc.v:184468$12053_Y + wire $gt$libresoc.v:184466$12052_Y + attribute \src "libresoc.v:184467.18-184467.97" + wire $gt$libresoc.v:184467$12053_Y + attribute \src "libresoc.v:184468.19-184468.99" + wire $gt$libresoc.v:184468$12054_Y attribute \src "libresoc.v:184469.19-184469.99" - wire $gt$libresoc.v:184469$12054_Y + wire $gt$libresoc.v:184469$12055_Y attribute \src "libresoc.v:184470.19-184470.99" - wire $gt$libresoc.v:184470$12055_Y + wire $gt$libresoc.v:184470$12056_Y attribute \src "libresoc.v:184471.19-184471.99" - wire $gt$libresoc.v:184471$12056_Y + wire $gt$libresoc.v:184471$12057_Y attribute \src "libresoc.v:184472.19-184472.99" - wire $gt$libresoc.v:184472$12057_Y - attribute \src "libresoc.v:184473.19-184473.99" - wire $gt$libresoc.v:184473$12058_Y + wire $gt$libresoc.v:184472$12058_Y + attribute \src "libresoc.v:184473.18-184473.97" + wire $gt$libresoc.v:184473$12059_Y attribute \src "libresoc.v:184474.18-184474.97" - wire $gt$libresoc.v:184474$12059_Y + wire $gt$libresoc.v:184474$12060_Y attribute \src "libresoc.v:184475.18-184475.97" - wire $gt$libresoc.v:184475$12060_Y - attribute \src "libresoc.v:184476.18-184476.97" - wire $gt$libresoc.v:184476$12061_Y - attribute \src "libresoc.v:184477.17-184477.96" - wire $gt$libresoc.v:184477$12062_Y + wire $gt$libresoc.v:184475$12061_Y + attribute \src "libresoc.v:184476.17-184476.96" + wire $gt$libresoc.v:184476$12062_Y + attribute \src "libresoc.v:184477.18-184477.97" + wire $gt$libresoc.v:184477$12063_Y attribute \src "libresoc.v:184478.18-184478.97" - wire $gt$libresoc.v:184478$12063_Y + wire $gt$libresoc.v:184478$12064_Y attribute \src "libresoc.v:184479.18-184479.97" - wire $gt$libresoc.v:184479$12064_Y + wire $gt$libresoc.v:184479$12065_Y attribute \src "libresoc.v:184480.18-184480.97" - wire $gt$libresoc.v:184480$12065_Y + wire $gt$libresoc.v:184480$12066_Y attribute \src "libresoc.v:184481.18-184481.97" - wire $gt$libresoc.v:184481$12066_Y + wire $gt$libresoc.v:184481$12067_Y attribute \src "libresoc.v:184482.18-184482.97" - wire $gt$libresoc.v:184482$12067_Y + wire $gt$libresoc.v:184482$12068_Y attribute \src "libresoc.v:184483.18-184483.97" - wire $gt$libresoc.v:184483$12068_Y - attribute \src "libresoc.v:184484.18-184484.97" - wire $gt$libresoc.v:184484$12069_Y + wire $gt$libresoc.v:184483$12069_Y + attribute \src "libresoc.v:184484.18-184484.98" + wire $gt$libresoc.v:184484$12070_Y attribute \src "libresoc.v:184485.18-184485.98" - wire $gt$libresoc.v:184485$12070_Y + wire $gt$libresoc.v:184485$12071_Y attribute \src "libresoc.v:184486.18-184486.98" - wire $gt$libresoc.v:184486$12071_Y - attribute \src "libresoc.v:184487.18-184487.98" - wire $gt$libresoc.v:184487$12072_Y - attribute \src "libresoc.v:184488.17-184488.96" - wire $gt$libresoc.v:184488$12073_Y + wire $gt$libresoc.v:184486$12072_Y + attribute \src "libresoc.v:184487.17-184487.96" + wire $gt$libresoc.v:184487$12073_Y + attribute \src "libresoc.v:184488.18-184488.98" + wire $gt$libresoc.v:184488$12074_Y attribute \src "libresoc.v:184489.18-184489.98" - wire $gt$libresoc.v:184489$12074_Y + wire $gt$libresoc.v:184489$12075_Y attribute \src "libresoc.v:184490.18-184490.98" - wire $gt$libresoc.v:184490$12075_Y + wire $gt$libresoc.v:184490$12076_Y attribute \src "libresoc.v:184491.18-184491.98" - wire $gt$libresoc.v:184491$12076_Y + wire $gt$libresoc.v:184491$12077_Y attribute \src "libresoc.v:184492.18-184492.98" - wire $gt$libresoc.v:184492$12077_Y + wire $gt$libresoc.v:184492$12078_Y attribute \src "libresoc.v:184493.18-184493.98" - wire $gt$libresoc.v:184493$12078_Y + wire $gt$libresoc.v:184493$12079_Y attribute \src "libresoc.v:184494.18-184494.98" - wire $gt$libresoc.v:184494$12079_Y + wire $gt$libresoc.v:184494$12080_Y attribute \src "libresoc.v:184495.18-184495.98" - wire $gt$libresoc.v:184495$12080_Y + wire $gt$libresoc.v:184495$12081_Y attribute \src "libresoc.v:184496.18-184496.98" - wire $gt$libresoc.v:184496$12081_Y + wire $gt$libresoc.v:184496$12082_Y attribute \src "libresoc.v:184497.18-184497.98" - wire $gt$libresoc.v:184497$12082_Y - attribute \src "libresoc.v:184498.18-184498.98" - wire $gt$libresoc.v:184498$12083_Y - attribute \src "libresoc.v:184499.17-184499.96" - wire $gt$libresoc.v:184499$12084_Y + wire $gt$libresoc.v:184497$12083_Y + attribute \src "libresoc.v:184498.17-184498.96" + wire $gt$libresoc.v:184498$12084_Y + attribute \src "libresoc.v:184499.18-184499.98" + wire $gt$libresoc.v:184499$12085_Y attribute \src "libresoc.v:184500.18-184500.98" - wire $gt$libresoc.v:184500$12085_Y + wire $gt$libresoc.v:184500$12086_Y attribute \src "libresoc.v:184501.18-184501.98" - wire $gt$libresoc.v:184501$12086_Y + wire $gt$libresoc.v:184501$12087_Y attribute \src "libresoc.v:184502.18-184502.98" - wire $gt$libresoc.v:184502$12087_Y + wire $gt$libresoc.v:184502$12088_Y attribute \src "libresoc.v:184503.18-184503.98" - wire $gt$libresoc.v:184503$12088_Y + wire $gt$libresoc.v:184503$12089_Y attribute \src "libresoc.v:184504.18-184504.98" - wire $gt$libresoc.v:184504$12089_Y + wire $gt$libresoc.v:184504$12090_Y attribute \src "libresoc.v:184505.18-184505.98" - wire $gt$libresoc.v:184505$12090_Y + wire $gt$libresoc.v:184505$12091_Y attribute \src "libresoc.v:184506.18-184506.98" - wire $gt$libresoc.v:184506$12091_Y + wire $gt$libresoc.v:184506$12092_Y attribute \src "libresoc.v:184507.18-184507.98" - wire $gt$libresoc.v:184507$12092_Y + wire $gt$libresoc.v:184507$12093_Y attribute \src "libresoc.v:184508.18-184508.98" - wire $gt$libresoc.v:184508$12093_Y - attribute \src "libresoc.v:184509.18-184509.98" - wire $gt$libresoc.v:184509$12094_Y - attribute \src "libresoc.v:184510.17-184510.96" - wire $gt$libresoc.v:184510$12095_Y + wire $gt$libresoc.v:184508$12094_Y + attribute \src "libresoc.v:184509.17-184509.96" + wire $gt$libresoc.v:184509$12095_Y + attribute \src "libresoc.v:184510.18-184510.98" + wire $gt$libresoc.v:184510$12096_Y attribute \src "libresoc.v:184511.18-184511.98" - wire $gt$libresoc.v:184511$12096_Y + wire $gt$libresoc.v:184511$12097_Y attribute \src "libresoc.v:184512.18-184512.98" - wire $gt$libresoc.v:184512$12097_Y + wire $gt$libresoc.v:184512$12098_Y attribute \src "libresoc.v:184513.18-184513.98" - wire $gt$libresoc.v:184513$12098_Y + wire $gt$libresoc.v:184513$12099_Y attribute \src "libresoc.v:184514.18-184514.98" - wire $gt$libresoc.v:184514$12099_Y + wire $gt$libresoc.v:184514$12100_Y attribute \src "libresoc.v:184515.18-184515.98" - wire $gt$libresoc.v:184515$12100_Y + wire $gt$libresoc.v:184515$12101_Y attribute \src "libresoc.v:184516.18-184516.98" - wire $gt$libresoc.v:184516$12101_Y + wire $gt$libresoc.v:184516$12102_Y attribute \src "libresoc.v:184517.18-184517.98" - wire $gt$libresoc.v:184517$12102_Y + wire $gt$libresoc.v:184517$12103_Y attribute \src "libresoc.v:184518.18-184518.98" - wire $gt$libresoc.v:184518$12103_Y + wire $gt$libresoc.v:184518$12104_Y attribute \src "libresoc.v:184519.18-184519.98" - wire $gt$libresoc.v:184519$12104_Y - attribute \src "libresoc.v:184520.18-184520.98" - wire $gt$libresoc.v:184520$12105_Y + wire $gt$libresoc.v:184519$12105_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" @@ -380718,14 +377528,14 @@ module \right_mask wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 - attribute \src "libresoc.v:184323.7-184323.15" + attribute \src "libresoc.v:184322.7-184322.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184457$12042 + cell $gt $gt$libresoc.v:184456$12042 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380733,10 +377543,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:184457$12042_Y + connect \Y $gt$libresoc.v:184456$12042_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184458$12043 + cell $gt $gt$libresoc.v:184457$12043 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380744,10 +377554,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:184458$12043_Y + connect \Y $gt$libresoc.v:184457$12043_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184459$12044 + cell $gt $gt$libresoc.v:184458$12044 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380755,10 +377565,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:184459$12044_Y + connect \Y $gt$libresoc.v:184458$12044_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184460$12045 + cell $gt $gt$libresoc.v:184459$12045 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380766,10 +377576,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:184460$12045_Y + connect \Y $gt$libresoc.v:184459$12045_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184461$12046 + cell $gt $gt$libresoc.v:184460$12046 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380777,10 +377587,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:184461$12046_Y + connect \Y $gt$libresoc.v:184460$12046_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184462$12047 + cell $gt $gt$libresoc.v:184461$12047 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380788,10 +377598,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:184462$12047_Y + connect \Y $gt$libresoc.v:184461$12047_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184463$12048 + cell $gt $gt$libresoc.v:184462$12048 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380799,10 +377609,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:184463$12048_Y + connect \Y $gt$libresoc.v:184462$12048_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184464$12049 + cell $gt $gt$libresoc.v:184463$12049 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380810,10 +377620,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:184464$12049_Y + connect \Y $gt$libresoc.v:184463$12049_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184465$12050 + cell $gt $gt$libresoc.v:184464$12050 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380821,10 +377631,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:184465$12050_Y + connect \Y $gt$libresoc.v:184464$12050_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184466$12051 + cell $gt $gt$libresoc.v:184465$12051 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380832,10 +377642,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:184466$12051_Y + connect \Y $gt$libresoc.v:184465$12051_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184467$12052 + cell $gt $gt$libresoc.v:184466$12052 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380843,10 +377653,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:184467$12052_Y + connect \Y $gt$libresoc.v:184466$12052_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184468$12053 + cell $gt $gt$libresoc.v:184467$12053 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380854,10 +377664,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:184468$12053_Y + connect \Y $gt$libresoc.v:184467$12053_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184469$12054 + cell $gt $gt$libresoc.v:184468$12054 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380865,10 +377675,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:184469$12054_Y + connect \Y $gt$libresoc.v:184468$12054_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184470$12055 + cell $gt $gt$libresoc.v:184469$12055 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380876,10 +377686,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:184470$12055_Y + connect \Y $gt$libresoc.v:184469$12055_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184471$12056 + cell $gt $gt$libresoc.v:184470$12056 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380887,10 +377697,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:184471$12056_Y + connect \Y $gt$libresoc.v:184470$12056_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184472$12057 + cell $gt $gt$libresoc.v:184471$12057 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380898,10 +377708,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:184472$12057_Y + connect \Y $gt$libresoc.v:184471$12057_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184473$12058 + cell $gt $gt$libresoc.v:184472$12058 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380909,10 +377719,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:184473$12058_Y + connect \Y $gt$libresoc.v:184472$12058_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184474$12059 + cell $gt $gt$libresoc.v:184473$12059 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380920,10 +377730,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:184474$12059_Y + connect \Y $gt$libresoc.v:184473$12059_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184475$12060 + cell $gt $gt$libresoc.v:184474$12060 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380931,10 +377741,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:184475$12060_Y + connect \Y $gt$libresoc.v:184474$12060_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184476$12061 + cell $gt $gt$libresoc.v:184475$12061 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380942,10 +377752,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:184476$12061_Y + connect \Y $gt$libresoc.v:184475$12061_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184477$12062 + cell $gt $gt$libresoc.v:184476$12062 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380953,10 +377763,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:184477$12062_Y + connect \Y $gt$libresoc.v:184476$12062_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184478$12063 + cell $gt $gt$libresoc.v:184477$12063 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380964,10 +377774,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:184478$12063_Y + connect \Y $gt$libresoc.v:184477$12063_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184479$12064 + cell $gt $gt$libresoc.v:184478$12064 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380975,10 +377785,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:184479$12064_Y + connect \Y $gt$libresoc.v:184478$12064_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184480$12065 + cell $gt $gt$libresoc.v:184479$12065 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380986,10 +377796,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:184480$12065_Y + connect \Y $gt$libresoc.v:184479$12065_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184481$12066 + cell $gt $gt$libresoc.v:184480$12066 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -380997,10 +377807,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:184481$12066_Y + connect \Y $gt$libresoc.v:184480$12066_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184482$12067 + cell $gt $gt$libresoc.v:184481$12067 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381008,10 +377818,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:184482$12067_Y + connect \Y $gt$libresoc.v:184481$12067_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184483$12068 + cell $gt $gt$libresoc.v:184482$12068 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381019,10 +377829,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:184483$12068_Y + connect \Y $gt$libresoc.v:184482$12068_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184484$12069 + cell $gt $gt$libresoc.v:184483$12069 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381030,10 +377840,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:184484$12069_Y + connect \Y $gt$libresoc.v:184483$12069_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184485$12070 + cell $gt $gt$libresoc.v:184484$12070 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381041,10 +377851,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:184485$12070_Y + connect \Y $gt$libresoc.v:184484$12070_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184486$12071 + cell $gt $gt$libresoc.v:184485$12071 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381052,10 +377862,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:184486$12071_Y + connect \Y $gt$libresoc.v:184485$12071_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184487$12072 + cell $gt $gt$libresoc.v:184486$12072 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381063,10 +377873,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:184487$12072_Y + connect \Y $gt$libresoc.v:184486$12072_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184488$12073 + cell $gt $gt$libresoc.v:184487$12073 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381074,10 +377884,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:184488$12073_Y + connect \Y $gt$libresoc.v:184487$12073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184489$12074 + cell $gt $gt$libresoc.v:184488$12074 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381085,10 +377895,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:184489$12074_Y + connect \Y $gt$libresoc.v:184488$12074_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184490$12075 + cell $gt $gt$libresoc.v:184489$12075 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381096,10 +377906,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:184490$12075_Y + connect \Y $gt$libresoc.v:184489$12075_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184491$12076 + cell $gt $gt$libresoc.v:184490$12076 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381107,10 +377917,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:184491$12076_Y + connect \Y $gt$libresoc.v:184490$12076_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184492$12077 + cell $gt $gt$libresoc.v:184491$12077 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381118,10 +377928,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:184492$12077_Y + connect \Y $gt$libresoc.v:184491$12077_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184493$12078 + cell $gt $gt$libresoc.v:184492$12078 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381129,10 +377939,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:184493$12078_Y + connect \Y $gt$libresoc.v:184492$12078_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184494$12079 + cell $gt $gt$libresoc.v:184493$12079 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381140,10 +377950,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:184494$12079_Y + connect \Y $gt$libresoc.v:184493$12079_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184495$12080 + cell $gt $gt$libresoc.v:184494$12080 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381151,10 +377961,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:184495$12080_Y + connect \Y $gt$libresoc.v:184494$12080_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184496$12081 + cell $gt $gt$libresoc.v:184495$12081 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381162,10 +377972,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:184496$12081_Y + connect \Y $gt$libresoc.v:184495$12081_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184497$12082 + cell $gt $gt$libresoc.v:184496$12082 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381173,10 +377983,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:184497$12082_Y + connect \Y $gt$libresoc.v:184496$12082_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184498$12083 + cell $gt $gt$libresoc.v:184497$12083 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381184,10 +377994,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:184498$12083_Y + connect \Y $gt$libresoc.v:184497$12083_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184499$12084 + cell $gt $gt$libresoc.v:184498$12084 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381195,10 +378005,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:184499$12084_Y + connect \Y $gt$libresoc.v:184498$12084_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184500$12085 + cell $gt $gt$libresoc.v:184499$12085 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381206,10 +378016,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:184500$12085_Y + connect \Y $gt$libresoc.v:184499$12085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184501$12086 + cell $gt $gt$libresoc.v:184500$12086 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381217,10 +378027,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:184501$12086_Y + connect \Y $gt$libresoc.v:184500$12086_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184502$12087 + cell $gt $gt$libresoc.v:184501$12087 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381228,10 +378038,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:184502$12087_Y + connect \Y $gt$libresoc.v:184501$12087_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184503$12088 + cell $gt $gt$libresoc.v:184502$12088 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381239,10 +378049,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:184503$12088_Y + connect \Y $gt$libresoc.v:184502$12088_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184504$12089 + cell $gt $gt$libresoc.v:184503$12089 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381250,10 +378060,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:184504$12089_Y + connect \Y $gt$libresoc.v:184503$12089_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184505$12090 + cell $gt $gt$libresoc.v:184504$12090 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381261,10 +378071,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:184505$12090_Y + connect \Y $gt$libresoc.v:184504$12090_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184506$12091 + cell $gt $gt$libresoc.v:184505$12091 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381272,10 +378082,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:184506$12091_Y + connect \Y $gt$libresoc.v:184505$12091_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184507$12092 + cell $gt $gt$libresoc.v:184506$12092 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381283,10 +378093,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:184507$12092_Y + connect \Y $gt$libresoc.v:184506$12092_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184508$12093 + cell $gt $gt$libresoc.v:184507$12093 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381294,10 +378104,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:184508$12093_Y + connect \Y $gt$libresoc.v:184507$12093_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184509$12094 + cell $gt $gt$libresoc.v:184508$12094 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381305,10 +378115,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:184509$12094_Y + connect \Y $gt$libresoc.v:184508$12094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184510$12095 + cell $gt $gt$libresoc.v:184509$12095 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381316,10 +378126,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:184510$12095_Y + connect \Y $gt$libresoc.v:184509$12095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184511$12096 + cell $gt $gt$libresoc.v:184510$12096 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381327,10 +378137,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:184511$12096_Y + connect \Y $gt$libresoc.v:184510$12096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184512$12097 + cell $gt $gt$libresoc.v:184511$12097 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381338,10 +378148,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:184512$12097_Y + connect \Y $gt$libresoc.v:184511$12097_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184513$12098 + cell $gt $gt$libresoc.v:184512$12098 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381349,10 +378159,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:184513$12098_Y + connect \Y $gt$libresoc.v:184512$12098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184514$12099 + cell $gt $gt$libresoc.v:184513$12099 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381360,10 +378170,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:184514$12099_Y + connect \Y $gt$libresoc.v:184513$12099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184515$12100 + cell $gt $gt$libresoc.v:184514$12100 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381371,10 +378181,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:184515$12100_Y + connect \Y $gt$libresoc.v:184514$12100_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184516$12101 + cell $gt $gt$libresoc.v:184515$12101 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381382,10 +378192,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:184516$12101_Y + connect \Y $gt$libresoc.v:184515$12101_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184517$12102 + cell $gt $gt$libresoc.v:184516$12102 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381393,10 +378203,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:184517$12102_Y + connect \Y $gt$libresoc.v:184516$12102_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184518$12103 + cell $gt $gt$libresoc.v:184517$12103 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381404,10 +378214,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:184518$12103_Y + connect \Y $gt$libresoc.v:184517$12103_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184519$12104 + cell $gt $gt$libresoc.v:184518$12104 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381415,10 +378225,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:184519$12104_Y + connect \Y $gt$libresoc.v:184518$12104_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184520$12105 + cell $gt $gt$libresoc.v:184519$12105 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381426,18 +378236,18 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:184520$12105_Y + connect \Y $gt$libresoc.v:184519$12105_Y end - attribute \src "libresoc.v:184323.7-184323.20" - process $proc$libresoc.v:184323$12107 + attribute \src "libresoc.v:184322.7-184322.20" + process $proc$libresoc.v:184322$12107 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184521.3-184908.6" - process $proc$libresoc.v:184521$12106 + attribute \src "libresoc.v:184520.3-184907.6" + process $proc$libresoc.v:184520$12106 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -381504,9 +378314,9 @@ module \right_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:184522.5-184522.29" + attribute \src "libresoc.v:184521.5-184521.29" switch \initial - attribute \src "libresoc.v:184522.9-184522.17" + attribute \src "libresoc.v:184521.9-184521.17" case 1'1 case end @@ -382089,102 +378899,102 @@ module \right_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:184457$12042_Y - connect \$99 $gt$libresoc.v:184458$12043_Y - connect \$101 $gt$libresoc.v:184459$12044_Y - connect \$103 $gt$libresoc.v:184460$12045_Y - connect \$105 $gt$libresoc.v:184461$12046_Y - connect \$107 $gt$libresoc.v:184462$12047_Y - connect \$109 $gt$libresoc.v:184463$12048_Y - connect \$111 $gt$libresoc.v:184464$12049_Y - connect \$113 $gt$libresoc.v:184465$12050_Y - connect \$115 $gt$libresoc.v:184466$12051_Y - connect \$117 $gt$libresoc.v:184467$12052_Y - connect \$11 $gt$libresoc.v:184468$12053_Y - connect \$119 $gt$libresoc.v:184469$12054_Y - connect \$121 $gt$libresoc.v:184470$12055_Y - connect \$123 $gt$libresoc.v:184471$12056_Y - connect \$125 $gt$libresoc.v:184472$12057_Y - connect \$127 $gt$libresoc.v:184473$12058_Y - connect \$13 $gt$libresoc.v:184474$12059_Y - connect \$15 $gt$libresoc.v:184475$12060_Y - connect \$17 $gt$libresoc.v:184476$12061_Y - connect \$1 $gt$libresoc.v:184477$12062_Y - connect \$19 $gt$libresoc.v:184478$12063_Y - connect \$21 $gt$libresoc.v:184479$12064_Y - connect \$23 $gt$libresoc.v:184480$12065_Y - connect \$25 $gt$libresoc.v:184481$12066_Y - connect \$27 $gt$libresoc.v:184482$12067_Y - connect \$29 $gt$libresoc.v:184483$12068_Y - connect \$31 $gt$libresoc.v:184484$12069_Y - connect \$33 $gt$libresoc.v:184485$12070_Y - connect \$35 $gt$libresoc.v:184486$12071_Y - connect \$37 $gt$libresoc.v:184487$12072_Y - connect \$3 $gt$libresoc.v:184488$12073_Y - connect \$39 $gt$libresoc.v:184489$12074_Y - connect \$41 $gt$libresoc.v:184490$12075_Y - connect \$43 $gt$libresoc.v:184491$12076_Y - connect \$45 $gt$libresoc.v:184492$12077_Y - connect \$47 $gt$libresoc.v:184493$12078_Y - connect \$49 $gt$libresoc.v:184494$12079_Y - connect \$51 $gt$libresoc.v:184495$12080_Y - connect \$53 $gt$libresoc.v:184496$12081_Y - connect \$55 $gt$libresoc.v:184497$12082_Y - connect \$57 $gt$libresoc.v:184498$12083_Y - connect \$5 $gt$libresoc.v:184499$12084_Y - connect \$59 $gt$libresoc.v:184500$12085_Y - connect \$61 $gt$libresoc.v:184501$12086_Y - connect \$63 $gt$libresoc.v:184502$12087_Y - connect \$65 $gt$libresoc.v:184503$12088_Y - connect \$67 $gt$libresoc.v:184504$12089_Y - connect \$69 $gt$libresoc.v:184505$12090_Y - connect \$71 $gt$libresoc.v:184506$12091_Y - connect \$73 $gt$libresoc.v:184507$12092_Y - connect \$75 $gt$libresoc.v:184508$12093_Y - connect \$77 $gt$libresoc.v:184509$12094_Y - connect \$7 $gt$libresoc.v:184510$12095_Y - connect \$79 $gt$libresoc.v:184511$12096_Y - connect \$81 $gt$libresoc.v:184512$12097_Y - connect \$83 $gt$libresoc.v:184513$12098_Y - connect \$85 $gt$libresoc.v:184514$12099_Y - connect \$87 $gt$libresoc.v:184515$12100_Y - connect \$89 $gt$libresoc.v:184516$12101_Y - connect \$91 $gt$libresoc.v:184517$12102_Y - connect \$93 $gt$libresoc.v:184518$12103_Y - connect \$95 $gt$libresoc.v:184519$12104_Y - connect \$97 $gt$libresoc.v:184520$12105_Y + connect \$9 $gt$libresoc.v:184456$12042_Y + connect \$99 $gt$libresoc.v:184457$12043_Y + connect \$101 $gt$libresoc.v:184458$12044_Y + connect \$103 $gt$libresoc.v:184459$12045_Y + connect \$105 $gt$libresoc.v:184460$12046_Y + connect \$107 $gt$libresoc.v:184461$12047_Y + connect \$109 $gt$libresoc.v:184462$12048_Y + connect \$111 $gt$libresoc.v:184463$12049_Y + connect \$113 $gt$libresoc.v:184464$12050_Y + connect \$115 $gt$libresoc.v:184465$12051_Y + connect \$117 $gt$libresoc.v:184466$12052_Y + connect \$11 $gt$libresoc.v:184467$12053_Y + connect \$119 $gt$libresoc.v:184468$12054_Y + connect \$121 $gt$libresoc.v:184469$12055_Y + connect \$123 $gt$libresoc.v:184470$12056_Y + connect \$125 $gt$libresoc.v:184471$12057_Y + connect \$127 $gt$libresoc.v:184472$12058_Y + connect \$13 $gt$libresoc.v:184473$12059_Y + connect \$15 $gt$libresoc.v:184474$12060_Y + connect \$17 $gt$libresoc.v:184475$12061_Y + connect \$1 $gt$libresoc.v:184476$12062_Y + connect \$19 $gt$libresoc.v:184477$12063_Y + connect \$21 $gt$libresoc.v:184478$12064_Y + connect \$23 $gt$libresoc.v:184479$12065_Y + connect \$25 $gt$libresoc.v:184480$12066_Y + connect \$27 $gt$libresoc.v:184481$12067_Y + connect \$29 $gt$libresoc.v:184482$12068_Y + connect \$31 $gt$libresoc.v:184483$12069_Y + connect \$33 $gt$libresoc.v:184484$12070_Y + connect \$35 $gt$libresoc.v:184485$12071_Y + connect \$37 $gt$libresoc.v:184486$12072_Y + connect \$3 $gt$libresoc.v:184487$12073_Y + connect \$39 $gt$libresoc.v:184488$12074_Y + connect \$41 $gt$libresoc.v:184489$12075_Y + connect \$43 $gt$libresoc.v:184490$12076_Y + connect \$45 $gt$libresoc.v:184491$12077_Y + connect \$47 $gt$libresoc.v:184492$12078_Y + connect \$49 $gt$libresoc.v:184493$12079_Y + connect \$51 $gt$libresoc.v:184494$12080_Y + connect \$53 $gt$libresoc.v:184495$12081_Y + connect \$55 $gt$libresoc.v:184496$12082_Y + connect \$57 $gt$libresoc.v:184497$12083_Y + connect \$5 $gt$libresoc.v:184498$12084_Y + connect \$59 $gt$libresoc.v:184499$12085_Y + connect \$61 $gt$libresoc.v:184500$12086_Y + connect \$63 $gt$libresoc.v:184501$12087_Y + connect \$65 $gt$libresoc.v:184502$12088_Y + connect \$67 $gt$libresoc.v:184503$12089_Y + connect \$69 $gt$libresoc.v:184504$12090_Y + connect \$71 $gt$libresoc.v:184505$12091_Y + connect \$73 $gt$libresoc.v:184506$12092_Y + connect \$75 $gt$libresoc.v:184507$12093_Y + connect \$77 $gt$libresoc.v:184508$12094_Y + connect \$7 $gt$libresoc.v:184509$12095_Y + connect \$79 $gt$libresoc.v:184510$12096_Y + connect \$81 $gt$libresoc.v:184511$12097_Y + connect \$83 $gt$libresoc.v:184512$12098_Y + connect \$85 $gt$libresoc.v:184513$12099_Y + connect \$87 $gt$libresoc.v:184514$12100_Y + connect \$89 $gt$libresoc.v:184515$12101_Y + connect \$91 $gt$libresoc.v:184516$12102_Y + connect \$93 $gt$libresoc.v:184517$12103_Y + connect \$95 $gt$libresoc.v:184518$12104_Y + connect \$97 $gt$libresoc.v:184519$12105_Y end -attribute \src "libresoc.v:184913.1-184971.10" +attribute \src "libresoc.v:184912.1-184970.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rok_l" attribute \generator "nMigen" module \rok_l - attribute \src "libresoc.v:184914.7-184914.20" + attribute \src "libresoc.v:184913.7-184913.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184959.3-184967.6" + attribute \src "libresoc.v:184958.3-184966.6" wire $0\q_int$next[0:0]$12118 - attribute \src "libresoc.v:184957.3-184958.27" + attribute \src "libresoc.v:184956.3-184957.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:184959.3-184967.6" + attribute \src "libresoc.v:184958.3-184966.6" wire $1\q_int$next[0:0]$12119 - attribute \src "libresoc.v:184936.7-184936.19" + attribute \src "libresoc.v:184935.7-184935.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:184949.17-184949.96" - wire $and$libresoc.v:184949$12108_Y - attribute \src "libresoc.v:184954.17-184954.96" - wire $and$libresoc.v:184954$12113_Y - attribute \src "libresoc.v:184951.18-184951.94" - wire $not$libresoc.v:184951$12110_Y - attribute \src "libresoc.v:184953.17-184953.93" - wire $not$libresoc.v:184953$12112_Y - attribute \src "libresoc.v:184956.17-184956.93" - wire $not$libresoc.v:184956$12115_Y - attribute \src "libresoc.v:184950.18-184950.99" - wire $or$libresoc.v:184950$12109_Y - attribute \src "libresoc.v:184952.18-184952.100" - wire $or$libresoc.v:184952$12111_Y - attribute \src "libresoc.v:184955.17-184955.98" - wire $or$libresoc.v:184955$12114_Y + attribute \src "libresoc.v:184948.17-184948.96" + wire $and$libresoc.v:184948$12108_Y + attribute \src "libresoc.v:184953.17-184953.96" + wire $and$libresoc.v:184953$12113_Y + attribute \src "libresoc.v:184950.18-184950.94" + wire $not$libresoc.v:184950$12110_Y + attribute \src "libresoc.v:184952.17-184952.93" + wire $not$libresoc.v:184952$12112_Y + attribute \src "libresoc.v:184955.17-184955.93" + wire $not$libresoc.v:184955$12115_Y + attribute \src "libresoc.v:184949.18-184949.99" + wire $or$libresoc.v:184949$12109_Y + attribute \src "libresoc.v:184951.18-184951.100" + wire $or$libresoc.v:184951$12111_Y + attribute \src "libresoc.v:184954.17-184954.98" + wire $or$libresoc.v:184954$12114_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382205,7 +379015,7 @@ module \rok_l wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:184914.7-184914.15" + attribute \src "libresoc.v:184913.7-184913.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382222,7 +379032,7 @@ module \rok_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184949$12108 + cell $and $and$libresoc.v:184948$12108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382230,10 +379040,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184949$12108_Y + connect \Y $and$libresoc.v:184948$12108_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184954$12113 + cell $and $and$libresoc.v:184953$12113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382241,34 +379051,34 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184954$12113_Y + connect \Y $and$libresoc.v:184953$12113_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184951$12110 + cell $not $not$libresoc.v:184950$12110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:184951$12110_Y + connect \Y $not$libresoc.v:184950$12110_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184953$12112 + cell $not $not$libresoc.v:184952$12112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:184953$12112_Y + connect \Y $not$libresoc.v:184952$12112_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184956$12115 + cell $not $not$libresoc.v:184955$12115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:184956$12115_Y + connect \Y $not$libresoc.v:184955$12115_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184950$12109 + cell $or $or$libresoc.v:184949$12109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382276,10 +379086,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:184950$12109_Y + connect \Y $or$libresoc.v:184949$12109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184952$12111 + cell $or $or$libresoc.v:184951$12111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382287,10 +379097,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:184952$12111_Y + connect \Y $or$libresoc.v:184951$12111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184955$12114 + cell $or $or$libresoc.v:184954$12114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382298,39 +379108,39 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:184955$12114_Y + connect \Y $or$libresoc.v:184954$12114_Y end - attribute \src "libresoc.v:184914.7-184914.20" - process $proc$libresoc.v:184914$12120 + attribute \src "libresoc.v:184913.7-184913.20" + process $proc$libresoc.v:184913$12120 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184936.7-184936.19" - process $proc$libresoc.v:184936$12121 + attribute \src "libresoc.v:184935.7-184935.19" + process $proc$libresoc.v:184935$12121 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:184957.3-184958.27" - process $proc$libresoc.v:184957$12116 + attribute \src "libresoc.v:184956.3-184957.27" + process $proc$libresoc.v:184956$12116 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:184959.3-184967.6" - process $proc$libresoc.v:184959$12117 + attribute \src "libresoc.v:184958.3-184966.6" + process $proc$libresoc.v:184958$12117 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12118 $1\q_int$next[0:0]$12119 - attribute \src "libresoc.v:184960.5-184960.29" + attribute \src "libresoc.v:184959.5-184959.29" switch \initial - attribute \src "libresoc.v:184960.9-184960.17" + attribute \src "libresoc.v:184959.9-184959.17" case 1'1 case end @@ -382346,49 +379156,49 @@ module \rok_l sync always update \q_int$next $0\q_int$next[0:0]$12118 end - connect \$9 $and$libresoc.v:184949$12108_Y - connect \$11 $or$libresoc.v:184950$12109_Y - connect \$13 $not$libresoc.v:184951$12110_Y - connect \$15 $or$libresoc.v:184952$12111_Y - connect \$1 $not$libresoc.v:184953$12112_Y - connect \$3 $and$libresoc.v:184954$12113_Y - connect \$5 $or$libresoc.v:184955$12114_Y - connect \$7 $not$libresoc.v:184956$12115_Y + connect \$9 $and$libresoc.v:184948$12108_Y + connect \$11 $or$libresoc.v:184949$12109_Y + connect \$13 $not$libresoc.v:184950$12110_Y + connect \$15 $or$libresoc.v:184951$12111_Y + connect \$1 $not$libresoc.v:184952$12112_Y + connect \$3 $and$libresoc.v:184953$12113_Y + connect \$5 $or$libresoc.v:184954$12114_Y + connect \$7 $not$libresoc.v:184955$12115_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:184975.1-185033.10" +attribute \src "libresoc.v:184974.1-185032.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rok_l" attribute \generator "nMigen" module \rok_l$105 - attribute \src "libresoc.v:184976.7-184976.20" + attribute \src "libresoc.v:184975.7-184975.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185021.3-185029.6" + attribute \src "libresoc.v:185020.3-185028.6" wire $0\q_int$next[0:0]$12132 - attribute \src "libresoc.v:185019.3-185020.27" + attribute \src "libresoc.v:185018.3-185019.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185021.3-185029.6" + attribute \src "libresoc.v:185020.3-185028.6" wire $1\q_int$next[0:0]$12133 - attribute \src "libresoc.v:184998.7-184998.19" + attribute \src "libresoc.v:184997.7-184997.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185011.17-185011.96" - wire $and$libresoc.v:185011$12122_Y - attribute \src "libresoc.v:185016.17-185016.96" - wire $and$libresoc.v:185016$12127_Y - attribute \src "libresoc.v:185013.18-185013.94" - wire $not$libresoc.v:185013$12124_Y - attribute \src "libresoc.v:185015.17-185015.93" - wire $not$libresoc.v:185015$12126_Y - attribute \src "libresoc.v:185018.17-185018.93" - wire $not$libresoc.v:185018$12129_Y - attribute \src "libresoc.v:185012.18-185012.99" - wire $or$libresoc.v:185012$12123_Y - attribute \src "libresoc.v:185014.18-185014.100" - wire $or$libresoc.v:185014$12125_Y - attribute \src "libresoc.v:185017.17-185017.98" - wire $or$libresoc.v:185017$12128_Y + attribute \src "libresoc.v:185010.17-185010.96" + wire $and$libresoc.v:185010$12122_Y + attribute \src "libresoc.v:185015.17-185015.96" + wire $and$libresoc.v:185015$12127_Y + attribute \src "libresoc.v:185012.18-185012.94" + wire $not$libresoc.v:185012$12124_Y + attribute \src "libresoc.v:185014.17-185014.93" + wire $not$libresoc.v:185014$12126_Y + attribute \src "libresoc.v:185017.17-185017.93" + wire $not$libresoc.v:185017$12129_Y + attribute \src "libresoc.v:185011.18-185011.99" + wire $or$libresoc.v:185011$12123_Y + attribute \src "libresoc.v:185013.18-185013.100" + wire $or$libresoc.v:185013$12125_Y + attribute \src "libresoc.v:185016.17-185016.98" + wire $or$libresoc.v:185016$12128_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382409,7 +379219,7 @@ module \rok_l$105 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:184976.7-184976.15" + attribute \src "libresoc.v:184975.7-184975.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382426,7 +379236,7 @@ module \rok_l$105 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185011$12122 + cell $and $and$libresoc.v:185010$12122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382434,10 +379244,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185011$12122_Y + connect \Y $and$libresoc.v:185010$12122_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185016$12127 + cell $and $and$libresoc.v:185015$12127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382445,34 +379255,34 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185016$12127_Y + connect \Y $and$libresoc.v:185015$12127_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185013$12124 + cell $not $not$libresoc.v:185012$12124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185013$12124_Y + connect \Y $not$libresoc.v:185012$12124_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185015$12126 + cell $not $not$libresoc.v:185014$12126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185015$12126_Y + connect \Y $not$libresoc.v:185014$12126_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185018$12129 + cell $not $not$libresoc.v:185017$12129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185018$12129_Y + connect \Y $not$libresoc.v:185017$12129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185012$12123 + cell $or $or$libresoc.v:185011$12123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382480,10 +379290,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185012$12123_Y + connect \Y $or$libresoc.v:185011$12123_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185014$12125 + cell $or $or$libresoc.v:185013$12125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382491,10 +379301,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185014$12125_Y + connect \Y $or$libresoc.v:185013$12125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185017$12128 + cell $or $or$libresoc.v:185016$12128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382502,39 +379312,39 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185017$12128_Y + connect \Y $or$libresoc.v:185016$12128_Y end - attribute \src "libresoc.v:184976.7-184976.20" - process $proc$libresoc.v:184976$12134 + attribute \src "libresoc.v:184975.7-184975.20" + process $proc$libresoc.v:184975$12134 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184998.7-184998.19" - process $proc$libresoc.v:184998$12135 + attribute \src "libresoc.v:184997.7-184997.19" + process $proc$libresoc.v:184997$12135 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185019.3-185020.27" - process $proc$libresoc.v:185019$12130 + attribute \src "libresoc.v:185018.3-185019.27" + process $proc$libresoc.v:185018$12130 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185021.3-185029.6" - process $proc$libresoc.v:185021$12131 + attribute \src "libresoc.v:185020.3-185028.6" + process $proc$libresoc.v:185020$12131 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12132 $1\q_int$next[0:0]$12133 - attribute \src "libresoc.v:185022.5-185022.29" + attribute \src "libresoc.v:185021.5-185021.29" switch \initial - attribute \src "libresoc.v:185022.9-185022.17" + attribute \src "libresoc.v:185021.9-185021.17" case 1'1 case end @@ -382550,49 +379360,49 @@ module \rok_l$105 sync always update \q_int$next $0\q_int$next[0:0]$12132 end - connect \$9 $and$libresoc.v:185011$12122_Y - connect \$11 $or$libresoc.v:185012$12123_Y - connect \$13 $not$libresoc.v:185013$12124_Y - connect \$15 $or$libresoc.v:185014$12125_Y - connect \$1 $not$libresoc.v:185015$12126_Y - connect \$3 $and$libresoc.v:185016$12127_Y - connect \$5 $or$libresoc.v:185017$12128_Y - connect \$7 $not$libresoc.v:185018$12129_Y + connect \$9 $and$libresoc.v:185010$12122_Y + connect \$11 $or$libresoc.v:185011$12123_Y + connect \$13 $not$libresoc.v:185012$12124_Y + connect \$15 $or$libresoc.v:185013$12125_Y + connect \$1 $not$libresoc.v:185014$12126_Y + connect \$3 $and$libresoc.v:185015$12127_Y + connect \$5 $or$libresoc.v:185016$12128_Y + connect \$7 $not$libresoc.v:185017$12129_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185037.1-185095.10" +attribute \src "libresoc.v:185036.1-185094.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rok_l" attribute \generator "nMigen" module \rok_l$123 - attribute \src "libresoc.v:185038.7-185038.20" + attribute \src "libresoc.v:185037.7-185037.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185083.3-185091.6" + attribute \src "libresoc.v:185082.3-185090.6" wire $0\q_int$next[0:0]$12146 - attribute \src "libresoc.v:185081.3-185082.27" + attribute \src "libresoc.v:185080.3-185081.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185083.3-185091.6" + attribute \src "libresoc.v:185082.3-185090.6" wire $1\q_int$next[0:0]$12147 - attribute \src "libresoc.v:185060.7-185060.19" + attribute \src "libresoc.v:185059.7-185059.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185073.17-185073.96" - wire $and$libresoc.v:185073$12136_Y - attribute \src "libresoc.v:185078.17-185078.96" - wire $and$libresoc.v:185078$12141_Y - attribute \src "libresoc.v:185075.18-185075.94" - wire $not$libresoc.v:185075$12138_Y - attribute \src "libresoc.v:185077.17-185077.93" - wire $not$libresoc.v:185077$12140_Y - attribute \src "libresoc.v:185080.17-185080.93" - wire $not$libresoc.v:185080$12143_Y - attribute \src "libresoc.v:185074.18-185074.99" - wire $or$libresoc.v:185074$12137_Y - attribute \src "libresoc.v:185076.18-185076.100" - wire $or$libresoc.v:185076$12139_Y - attribute \src "libresoc.v:185079.17-185079.98" - wire $or$libresoc.v:185079$12142_Y + attribute \src "libresoc.v:185072.17-185072.96" + wire $and$libresoc.v:185072$12136_Y + attribute \src "libresoc.v:185077.17-185077.96" + wire $and$libresoc.v:185077$12141_Y + attribute \src "libresoc.v:185074.18-185074.94" + wire $not$libresoc.v:185074$12138_Y + attribute \src "libresoc.v:185076.17-185076.93" + wire $not$libresoc.v:185076$12140_Y + attribute \src "libresoc.v:185079.17-185079.93" + wire $not$libresoc.v:185079$12143_Y + attribute \src "libresoc.v:185073.18-185073.99" + wire $or$libresoc.v:185073$12137_Y + attribute \src "libresoc.v:185075.18-185075.100" + wire $or$libresoc.v:185075$12139_Y + attribute \src "libresoc.v:185078.17-185078.98" + wire $or$libresoc.v:185078$12142_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382613,7 +379423,7 @@ module \rok_l$123 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:185038.7-185038.15" + attribute \src "libresoc.v:185037.7-185037.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382630,7 +379440,7 @@ module \rok_l$123 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185073$12136 + cell $and $and$libresoc.v:185072$12136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382638,10 +379448,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185073$12136_Y + connect \Y $and$libresoc.v:185072$12136_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185078$12141 + cell $and $and$libresoc.v:185077$12141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382649,34 +379459,34 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185078$12141_Y + connect \Y $and$libresoc.v:185077$12141_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185075$12138 + cell $not $not$libresoc.v:185074$12138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185075$12138_Y + connect \Y $not$libresoc.v:185074$12138_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185077$12140 + cell $not $not$libresoc.v:185076$12140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185077$12140_Y + connect \Y $not$libresoc.v:185076$12140_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185080$12143 + cell $not $not$libresoc.v:185079$12143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185080$12143_Y + connect \Y $not$libresoc.v:185079$12143_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185074$12137 + cell $or $or$libresoc.v:185073$12137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382684,10 +379494,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185074$12137_Y + connect \Y $or$libresoc.v:185073$12137_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185076$12139 + cell $or $or$libresoc.v:185075$12139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382695,10 +379505,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185076$12139_Y + connect \Y $or$libresoc.v:185075$12139_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185079$12142 + cell $or $or$libresoc.v:185078$12142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382706,39 +379516,39 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185079$12142_Y + connect \Y $or$libresoc.v:185078$12142_Y end - attribute \src "libresoc.v:185038.7-185038.20" - process $proc$libresoc.v:185038$12148 + attribute \src "libresoc.v:185037.7-185037.20" + process $proc$libresoc.v:185037$12148 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185060.7-185060.19" - process $proc$libresoc.v:185060$12149 + attribute \src "libresoc.v:185059.7-185059.19" + process $proc$libresoc.v:185059$12149 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185081.3-185082.27" - process $proc$libresoc.v:185081$12144 + attribute \src "libresoc.v:185080.3-185081.27" + process $proc$libresoc.v:185080$12144 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185083.3-185091.6" - process $proc$libresoc.v:185083$12145 + attribute \src "libresoc.v:185082.3-185090.6" + process $proc$libresoc.v:185082$12145 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12146 $1\q_int$next[0:0]$12147 - attribute \src "libresoc.v:185084.5-185084.29" + attribute \src "libresoc.v:185083.5-185083.29" switch \initial - attribute \src "libresoc.v:185084.9-185084.17" + attribute \src "libresoc.v:185083.9-185083.17" case 1'1 case end @@ -382754,49 +379564,49 @@ module \rok_l$123 sync always update \q_int$next $0\q_int$next[0:0]$12146 end - connect \$9 $and$libresoc.v:185073$12136_Y - connect \$11 $or$libresoc.v:185074$12137_Y - connect \$13 $not$libresoc.v:185075$12138_Y - connect \$15 $or$libresoc.v:185076$12139_Y - connect \$1 $not$libresoc.v:185077$12140_Y - connect \$3 $and$libresoc.v:185078$12141_Y - connect \$5 $or$libresoc.v:185079$12142_Y - connect \$7 $not$libresoc.v:185080$12143_Y + connect \$9 $and$libresoc.v:185072$12136_Y + connect \$11 $or$libresoc.v:185073$12137_Y + connect \$13 $not$libresoc.v:185074$12138_Y + connect \$15 $or$libresoc.v:185075$12139_Y + connect \$1 $not$libresoc.v:185076$12140_Y + connect \$3 $and$libresoc.v:185077$12141_Y + connect \$5 $or$libresoc.v:185078$12142_Y + connect \$7 $not$libresoc.v:185079$12143_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185099.1-185157.10" +attribute \src "libresoc.v:185098.1-185156.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rok_l" attribute \generator "nMigen" module \rok_l$14 - attribute \src "libresoc.v:185100.7-185100.20" + attribute \src "libresoc.v:185099.7-185099.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185145.3-185153.6" + attribute \src "libresoc.v:185144.3-185152.6" wire $0\q_int$next[0:0]$12160 - attribute \src "libresoc.v:185143.3-185144.27" + attribute \src "libresoc.v:185142.3-185143.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185145.3-185153.6" + attribute \src "libresoc.v:185144.3-185152.6" wire $1\q_int$next[0:0]$12161 - attribute \src "libresoc.v:185122.7-185122.19" + attribute \src "libresoc.v:185121.7-185121.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185135.17-185135.96" - wire $and$libresoc.v:185135$12150_Y - attribute \src "libresoc.v:185140.17-185140.96" - wire $and$libresoc.v:185140$12155_Y - attribute \src "libresoc.v:185137.18-185137.94" - wire $not$libresoc.v:185137$12152_Y - attribute \src "libresoc.v:185139.17-185139.93" - wire $not$libresoc.v:185139$12154_Y - attribute \src "libresoc.v:185142.17-185142.93" - wire $not$libresoc.v:185142$12157_Y - attribute \src "libresoc.v:185136.18-185136.99" - wire $or$libresoc.v:185136$12151_Y - attribute \src "libresoc.v:185138.18-185138.100" - wire $or$libresoc.v:185138$12153_Y - attribute \src "libresoc.v:185141.17-185141.98" - wire $or$libresoc.v:185141$12156_Y + attribute \src "libresoc.v:185134.17-185134.96" + wire $and$libresoc.v:185134$12150_Y + attribute \src "libresoc.v:185139.17-185139.96" + wire $and$libresoc.v:185139$12155_Y + attribute \src "libresoc.v:185136.18-185136.94" + wire $not$libresoc.v:185136$12152_Y + attribute \src "libresoc.v:185138.17-185138.93" + wire $not$libresoc.v:185138$12154_Y + attribute \src "libresoc.v:185141.17-185141.93" + wire $not$libresoc.v:185141$12157_Y + attribute \src "libresoc.v:185135.18-185135.99" + wire $or$libresoc.v:185135$12151_Y + attribute \src "libresoc.v:185137.18-185137.100" + wire $or$libresoc.v:185137$12153_Y + attribute \src "libresoc.v:185140.17-185140.98" + wire $or$libresoc.v:185140$12156_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382817,7 +379627,7 @@ module \rok_l$14 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:185100.7-185100.15" + attribute \src "libresoc.v:185099.7-185099.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382834,7 +379644,7 @@ module \rok_l$14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185135$12150 + cell $and $and$libresoc.v:185134$12150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382842,10 +379652,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185135$12150_Y + connect \Y $and$libresoc.v:185134$12150_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185140$12155 + cell $and $and$libresoc.v:185139$12155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382853,34 +379663,34 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185140$12155_Y + connect \Y $and$libresoc.v:185139$12155_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185137$12152 + cell $not $not$libresoc.v:185136$12152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185137$12152_Y + connect \Y $not$libresoc.v:185136$12152_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185139$12154 + cell $not $not$libresoc.v:185138$12154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185139$12154_Y + connect \Y $not$libresoc.v:185138$12154_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185142$12157 + cell $not $not$libresoc.v:185141$12157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185142$12157_Y + connect \Y $not$libresoc.v:185141$12157_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185136$12151 + cell $or $or$libresoc.v:185135$12151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382888,10 +379698,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185136$12151_Y + connect \Y $or$libresoc.v:185135$12151_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185138$12153 + cell $or $or$libresoc.v:185137$12153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382899,10 +379709,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185138$12153_Y + connect \Y $or$libresoc.v:185137$12153_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185141$12156 + cell $or $or$libresoc.v:185140$12156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382910,39 +379720,39 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185141$12156_Y + connect \Y $or$libresoc.v:185140$12156_Y end - attribute \src "libresoc.v:185100.7-185100.20" - process $proc$libresoc.v:185100$12162 + attribute \src "libresoc.v:185099.7-185099.20" + process $proc$libresoc.v:185099$12162 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185122.7-185122.19" - process $proc$libresoc.v:185122$12163 + attribute \src "libresoc.v:185121.7-185121.19" + process $proc$libresoc.v:185121$12163 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185143.3-185144.27" - process $proc$libresoc.v:185143$12158 + attribute \src "libresoc.v:185142.3-185143.27" + process $proc$libresoc.v:185142$12158 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185145.3-185153.6" - process $proc$libresoc.v:185145$12159 + attribute \src "libresoc.v:185144.3-185152.6" + process $proc$libresoc.v:185144$12159 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12160 $1\q_int$next[0:0]$12161 - attribute \src "libresoc.v:185146.5-185146.29" + attribute \src "libresoc.v:185145.5-185145.29" switch \initial - attribute \src "libresoc.v:185146.9-185146.17" + attribute \src "libresoc.v:185145.9-185145.17" case 1'1 case end @@ -382958,49 +379768,49 @@ module \rok_l$14 sync always update \q_int$next $0\q_int$next[0:0]$12160 end - connect \$9 $and$libresoc.v:185135$12150_Y - connect \$11 $or$libresoc.v:185136$12151_Y - connect \$13 $not$libresoc.v:185137$12152_Y - connect \$15 $or$libresoc.v:185138$12153_Y - connect \$1 $not$libresoc.v:185139$12154_Y - connect \$3 $and$libresoc.v:185140$12155_Y - connect \$5 $or$libresoc.v:185141$12156_Y - connect \$7 $not$libresoc.v:185142$12157_Y + connect \$9 $and$libresoc.v:185134$12150_Y + connect \$11 $or$libresoc.v:185135$12151_Y + connect \$13 $not$libresoc.v:185136$12152_Y + connect \$15 $or$libresoc.v:185137$12153_Y + connect \$1 $not$libresoc.v:185138$12154_Y + connect \$3 $and$libresoc.v:185139$12155_Y + connect \$5 $or$libresoc.v:185140$12156_Y + connect \$7 $not$libresoc.v:185141$12157_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185161.1-185219.10" +attribute \src "libresoc.v:185160.1-185218.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rok_l" attribute \generator "nMigen" module \rok_l$27 - attribute \src "libresoc.v:185162.7-185162.20" + attribute \src "libresoc.v:185161.7-185161.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185207.3-185215.6" + attribute \src "libresoc.v:185206.3-185214.6" wire $0\q_int$next[0:0]$12174 - attribute \src "libresoc.v:185205.3-185206.27" + attribute \src "libresoc.v:185204.3-185205.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185207.3-185215.6" + attribute \src "libresoc.v:185206.3-185214.6" wire $1\q_int$next[0:0]$12175 - attribute \src "libresoc.v:185184.7-185184.19" + attribute \src "libresoc.v:185183.7-185183.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185197.17-185197.96" - wire $and$libresoc.v:185197$12164_Y - attribute \src "libresoc.v:185202.17-185202.96" - wire $and$libresoc.v:185202$12169_Y - attribute \src "libresoc.v:185199.18-185199.94" - wire $not$libresoc.v:185199$12166_Y - attribute \src "libresoc.v:185201.17-185201.93" - wire $not$libresoc.v:185201$12168_Y - attribute \src "libresoc.v:185204.17-185204.93" - wire $not$libresoc.v:185204$12171_Y - attribute \src "libresoc.v:185198.18-185198.99" - wire $or$libresoc.v:185198$12165_Y - attribute \src "libresoc.v:185200.18-185200.100" - wire $or$libresoc.v:185200$12167_Y - attribute \src "libresoc.v:185203.17-185203.98" - wire $or$libresoc.v:185203$12170_Y + attribute \src "libresoc.v:185196.17-185196.96" + wire $and$libresoc.v:185196$12164_Y + attribute \src "libresoc.v:185201.17-185201.96" + wire $and$libresoc.v:185201$12169_Y + attribute \src "libresoc.v:185198.18-185198.94" + wire $not$libresoc.v:185198$12166_Y + attribute \src "libresoc.v:185200.17-185200.93" + wire $not$libresoc.v:185200$12168_Y + attribute \src "libresoc.v:185203.17-185203.93" + wire $not$libresoc.v:185203$12171_Y + attribute \src "libresoc.v:185197.18-185197.99" + wire $or$libresoc.v:185197$12165_Y + attribute \src "libresoc.v:185199.18-185199.100" + wire $or$libresoc.v:185199$12167_Y + attribute \src "libresoc.v:185202.17-185202.98" + wire $or$libresoc.v:185202$12170_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -383021,7 +379831,7 @@ module \rok_l$27 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:185162.7-185162.15" + attribute \src "libresoc.v:185161.7-185161.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -383038,7 +379848,7 @@ module \rok_l$27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185197$12164 + cell $and $and$libresoc.v:185196$12164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383046,10 +379856,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185197$12164_Y + connect \Y $and$libresoc.v:185196$12164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185202$12169 + cell $and $and$libresoc.v:185201$12169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383057,34 +379867,34 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185202$12169_Y + connect \Y $and$libresoc.v:185201$12169_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185199$12166 + cell $not $not$libresoc.v:185198$12166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185199$12166_Y + connect \Y $not$libresoc.v:185198$12166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185201$12168 + cell $not $not$libresoc.v:185200$12168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185201$12168_Y + connect \Y $not$libresoc.v:185200$12168_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185204$12171 + cell $not $not$libresoc.v:185203$12171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185204$12171_Y + connect \Y $not$libresoc.v:185203$12171_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185198$12165 + cell $or $or$libresoc.v:185197$12165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383092,10 +379902,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185198$12165_Y + connect \Y $or$libresoc.v:185197$12165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185200$12167 + cell $or $or$libresoc.v:185199$12167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383103,10 +379913,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185200$12167_Y + connect \Y $or$libresoc.v:185199$12167_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185203$12170 + cell $or $or$libresoc.v:185202$12170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383114,39 +379924,39 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185203$12170_Y + connect \Y $or$libresoc.v:185202$12170_Y end - attribute \src "libresoc.v:185162.7-185162.20" - process $proc$libresoc.v:185162$12176 + attribute \src "libresoc.v:185161.7-185161.20" + process $proc$libresoc.v:185161$12176 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185184.7-185184.19" - process $proc$libresoc.v:185184$12177 + attribute \src "libresoc.v:185183.7-185183.19" + process $proc$libresoc.v:185183$12177 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185205.3-185206.27" - process $proc$libresoc.v:185205$12172 + attribute \src "libresoc.v:185204.3-185205.27" + process $proc$libresoc.v:185204$12172 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185207.3-185215.6" - process $proc$libresoc.v:185207$12173 + attribute \src "libresoc.v:185206.3-185214.6" + process $proc$libresoc.v:185206$12173 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12174 $1\q_int$next[0:0]$12175 - attribute \src "libresoc.v:185208.5-185208.29" + attribute \src "libresoc.v:185207.5-185207.29" switch \initial - attribute \src "libresoc.v:185208.9-185208.17" + attribute \src "libresoc.v:185207.9-185207.17" case 1'1 case end @@ -383162,49 +379972,49 @@ module \rok_l$27 sync always update \q_int$next $0\q_int$next[0:0]$12174 end - connect \$9 $and$libresoc.v:185197$12164_Y - connect \$11 $or$libresoc.v:185198$12165_Y - connect \$13 $not$libresoc.v:185199$12166_Y - connect \$15 $or$libresoc.v:185200$12167_Y - connect \$1 $not$libresoc.v:185201$12168_Y - connect \$3 $and$libresoc.v:185202$12169_Y - connect \$5 $or$libresoc.v:185203$12170_Y - connect \$7 $not$libresoc.v:185204$12171_Y + connect \$9 $and$libresoc.v:185196$12164_Y + connect \$11 $or$libresoc.v:185197$12165_Y + connect \$13 $not$libresoc.v:185198$12166_Y + connect \$15 $or$libresoc.v:185199$12167_Y + connect \$1 $not$libresoc.v:185200$12168_Y + connect \$3 $and$libresoc.v:185201$12169_Y + connect \$5 $or$libresoc.v:185202$12170_Y + connect \$7 $not$libresoc.v:185203$12171_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185223.1-185281.10" +attribute \src "libresoc.v:185222.1-185280.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rok_l" attribute \generator "nMigen" module \rok_l$43 - attribute \src "libresoc.v:185224.7-185224.20" + attribute \src "libresoc.v:185223.7-185223.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185269.3-185277.6" + attribute \src "libresoc.v:185268.3-185276.6" wire $0\q_int$next[0:0]$12188 - attribute \src "libresoc.v:185267.3-185268.27" + attribute \src "libresoc.v:185266.3-185267.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185269.3-185277.6" + attribute \src "libresoc.v:185268.3-185276.6" wire $1\q_int$next[0:0]$12189 - attribute \src "libresoc.v:185246.7-185246.19" + attribute \src "libresoc.v:185245.7-185245.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185259.17-185259.96" - wire $and$libresoc.v:185259$12178_Y - attribute \src "libresoc.v:185264.17-185264.96" - wire $and$libresoc.v:185264$12183_Y - attribute \src "libresoc.v:185261.18-185261.94" - wire $not$libresoc.v:185261$12180_Y - attribute \src "libresoc.v:185263.17-185263.93" - wire $not$libresoc.v:185263$12182_Y - attribute \src "libresoc.v:185266.17-185266.93" - wire $not$libresoc.v:185266$12185_Y - attribute \src "libresoc.v:185260.18-185260.99" - wire $or$libresoc.v:185260$12179_Y - attribute \src "libresoc.v:185262.18-185262.100" - wire $or$libresoc.v:185262$12181_Y - attribute \src "libresoc.v:185265.17-185265.98" - wire $or$libresoc.v:185265$12184_Y + attribute \src "libresoc.v:185258.17-185258.96" + wire $and$libresoc.v:185258$12178_Y + attribute \src "libresoc.v:185263.17-185263.96" + wire $and$libresoc.v:185263$12183_Y + attribute \src "libresoc.v:185260.18-185260.94" + wire $not$libresoc.v:185260$12180_Y + attribute \src "libresoc.v:185262.17-185262.93" + wire $not$libresoc.v:185262$12182_Y + attribute \src "libresoc.v:185265.17-185265.93" + wire $not$libresoc.v:185265$12185_Y + attribute \src "libresoc.v:185259.18-185259.99" + wire $or$libresoc.v:185259$12179_Y + attribute \src "libresoc.v:185261.18-185261.100" + wire $or$libresoc.v:185261$12181_Y + attribute \src "libresoc.v:185264.17-185264.98" + wire $or$libresoc.v:185264$12184_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -383225,7 +380035,7 @@ module \rok_l$43 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:185224.7-185224.15" + attribute \src "libresoc.v:185223.7-185223.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -383242,7 +380052,7 @@ module \rok_l$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185259$12178 + cell $and $and$libresoc.v:185258$12178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383250,10 +380060,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185259$12178_Y + connect \Y $and$libresoc.v:185258$12178_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185264$12183 + cell $and $and$libresoc.v:185263$12183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383261,34 +380071,34 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185264$12183_Y + connect \Y $and$libresoc.v:185263$12183_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185261$12180 + cell $not $not$libresoc.v:185260$12180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185261$12180_Y + connect \Y $not$libresoc.v:185260$12180_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185263$12182 + cell $not $not$libresoc.v:185262$12182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185263$12182_Y + connect \Y $not$libresoc.v:185262$12182_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185266$12185 + cell $not $not$libresoc.v:185265$12185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185266$12185_Y + connect \Y $not$libresoc.v:185265$12185_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185260$12179 + cell $or $or$libresoc.v:185259$12179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383296,10 +380106,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185260$12179_Y + connect \Y $or$libresoc.v:185259$12179_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185262$12181 + cell $or $or$libresoc.v:185261$12181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383307,10 +380117,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185262$12181_Y + connect \Y $or$libresoc.v:185261$12181_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185265$12184 + cell $or $or$libresoc.v:185264$12184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383318,39 +380128,39 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185265$12184_Y + connect \Y $or$libresoc.v:185264$12184_Y end - attribute \src "libresoc.v:185224.7-185224.20" - process $proc$libresoc.v:185224$12190 + attribute \src "libresoc.v:185223.7-185223.20" + process $proc$libresoc.v:185223$12190 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185246.7-185246.19" - process $proc$libresoc.v:185246$12191 + attribute \src "libresoc.v:185245.7-185245.19" + process $proc$libresoc.v:185245$12191 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185267.3-185268.27" - process $proc$libresoc.v:185267$12186 + attribute \src "libresoc.v:185266.3-185267.27" + process $proc$libresoc.v:185266$12186 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185269.3-185277.6" - process $proc$libresoc.v:185269$12187 + attribute \src "libresoc.v:185268.3-185276.6" + process $proc$libresoc.v:185268$12187 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12188 $1\q_int$next[0:0]$12189 - attribute \src "libresoc.v:185270.5-185270.29" + attribute \src "libresoc.v:185269.5-185269.29" switch \initial - attribute \src "libresoc.v:185270.9-185270.17" + attribute \src "libresoc.v:185269.9-185269.17" case 1'1 case end @@ -383366,49 +380176,49 @@ module \rok_l$43 sync always update \q_int$next $0\q_int$next[0:0]$12188 end - connect \$9 $and$libresoc.v:185259$12178_Y - connect \$11 $or$libresoc.v:185260$12179_Y - connect \$13 $not$libresoc.v:185261$12180_Y - connect \$15 $or$libresoc.v:185262$12181_Y - connect \$1 $not$libresoc.v:185263$12182_Y - connect \$3 $and$libresoc.v:185264$12183_Y - connect \$5 $or$libresoc.v:185265$12184_Y - connect \$7 $not$libresoc.v:185266$12185_Y + connect \$9 $and$libresoc.v:185258$12178_Y + connect \$11 $or$libresoc.v:185259$12179_Y + connect \$13 $not$libresoc.v:185260$12180_Y + connect \$15 $or$libresoc.v:185261$12181_Y + connect \$1 $not$libresoc.v:185262$12182_Y + connect \$3 $and$libresoc.v:185263$12183_Y + connect \$5 $or$libresoc.v:185264$12184_Y + connect \$7 $not$libresoc.v:185265$12185_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185285.1-185343.10" +attribute \src "libresoc.v:185284.1-185342.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rok_l" attribute \generator "nMigen" module \rok_l$59 - attribute \src "libresoc.v:185286.7-185286.20" + attribute \src "libresoc.v:185285.7-185285.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185331.3-185339.6" + attribute \src "libresoc.v:185330.3-185338.6" wire $0\q_int$next[0:0]$12202 - attribute \src "libresoc.v:185329.3-185330.27" + attribute \src "libresoc.v:185328.3-185329.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185331.3-185339.6" + attribute \src "libresoc.v:185330.3-185338.6" wire $1\q_int$next[0:0]$12203 - attribute \src "libresoc.v:185308.7-185308.19" + attribute \src "libresoc.v:185307.7-185307.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185321.17-185321.96" - wire $and$libresoc.v:185321$12192_Y - attribute \src "libresoc.v:185326.17-185326.96" - wire $and$libresoc.v:185326$12197_Y - attribute \src "libresoc.v:185323.18-185323.94" - wire $not$libresoc.v:185323$12194_Y - attribute \src "libresoc.v:185325.17-185325.93" - wire $not$libresoc.v:185325$12196_Y - attribute \src "libresoc.v:185328.17-185328.93" - wire $not$libresoc.v:185328$12199_Y - attribute \src "libresoc.v:185322.18-185322.99" - wire $or$libresoc.v:185322$12193_Y - attribute \src "libresoc.v:185324.18-185324.100" - wire $or$libresoc.v:185324$12195_Y - attribute \src "libresoc.v:185327.17-185327.98" - wire $or$libresoc.v:185327$12198_Y + attribute \src "libresoc.v:185320.17-185320.96" + wire $and$libresoc.v:185320$12192_Y + attribute \src "libresoc.v:185325.17-185325.96" + wire $and$libresoc.v:185325$12197_Y + attribute \src "libresoc.v:185322.18-185322.94" + wire $not$libresoc.v:185322$12194_Y + attribute \src "libresoc.v:185324.17-185324.93" + wire $not$libresoc.v:185324$12196_Y + attribute \src "libresoc.v:185327.17-185327.93" + wire $not$libresoc.v:185327$12199_Y + attribute \src "libresoc.v:185321.18-185321.99" + wire $or$libresoc.v:185321$12193_Y + attribute \src "libresoc.v:185323.18-185323.100" + wire $or$libresoc.v:185323$12195_Y + attribute \src "libresoc.v:185326.17-185326.98" + wire $or$libresoc.v:185326$12198_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -383429,7 +380239,7 @@ module \rok_l$59 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:185286.7-185286.15" + attribute \src "libresoc.v:185285.7-185285.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -383446,7 +380256,7 @@ module \rok_l$59 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185321$12192 + cell $and $and$libresoc.v:185320$12192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383454,10 +380264,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185321$12192_Y + connect \Y $and$libresoc.v:185320$12192_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185326$12197 + cell $and $and$libresoc.v:185325$12197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383465,34 +380275,34 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185326$12197_Y + connect \Y $and$libresoc.v:185325$12197_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185323$12194 + cell $not $not$libresoc.v:185322$12194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185323$12194_Y + connect \Y $not$libresoc.v:185322$12194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185325$12196 + cell $not $not$libresoc.v:185324$12196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185325$12196_Y + connect \Y $not$libresoc.v:185324$12196_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185328$12199 + cell $not $not$libresoc.v:185327$12199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185328$12199_Y + connect \Y $not$libresoc.v:185327$12199_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185322$12193 + cell $or $or$libresoc.v:185321$12193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383500,10 +380310,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185322$12193_Y + connect \Y $or$libresoc.v:185321$12193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185324$12195 + cell $or $or$libresoc.v:185323$12195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383511,10 +380321,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185324$12195_Y + connect \Y $or$libresoc.v:185323$12195_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185327$12198 + cell $or $or$libresoc.v:185326$12198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383522,39 +380332,39 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185327$12198_Y + connect \Y $or$libresoc.v:185326$12198_Y end - attribute \src "libresoc.v:185286.7-185286.20" - process $proc$libresoc.v:185286$12204 + attribute \src "libresoc.v:185285.7-185285.20" + process $proc$libresoc.v:185285$12204 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185308.7-185308.19" - process $proc$libresoc.v:185308$12205 + attribute \src "libresoc.v:185307.7-185307.19" + process $proc$libresoc.v:185307$12205 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185329.3-185330.27" - process $proc$libresoc.v:185329$12200 + attribute \src "libresoc.v:185328.3-185329.27" + process $proc$libresoc.v:185328$12200 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185331.3-185339.6" - process $proc$libresoc.v:185331$12201 + attribute \src "libresoc.v:185330.3-185338.6" + process $proc$libresoc.v:185330$12201 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12202 $1\q_int$next[0:0]$12203 - attribute \src "libresoc.v:185332.5-185332.29" + attribute \src "libresoc.v:185331.5-185331.29" switch \initial - attribute \src "libresoc.v:185332.9-185332.17" + attribute \src "libresoc.v:185331.9-185331.17" case 1'1 case end @@ -383570,49 +380380,49 @@ module \rok_l$59 sync always update \q_int$next $0\q_int$next[0:0]$12202 end - connect \$9 $and$libresoc.v:185321$12192_Y - connect \$11 $or$libresoc.v:185322$12193_Y - connect \$13 $not$libresoc.v:185323$12194_Y - connect \$15 $or$libresoc.v:185324$12195_Y - connect \$1 $not$libresoc.v:185325$12196_Y - connect \$3 $and$libresoc.v:185326$12197_Y - connect \$5 $or$libresoc.v:185327$12198_Y - connect \$7 $not$libresoc.v:185328$12199_Y + connect \$9 $and$libresoc.v:185320$12192_Y + connect \$11 $or$libresoc.v:185321$12193_Y + connect \$13 $not$libresoc.v:185322$12194_Y + connect \$15 $or$libresoc.v:185323$12195_Y + connect \$1 $not$libresoc.v:185324$12196_Y + connect \$3 $and$libresoc.v:185325$12197_Y + connect \$5 $or$libresoc.v:185326$12198_Y + connect \$7 $not$libresoc.v:185327$12199_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185347.1-185405.10" +attribute \src "libresoc.v:185346.1-185404.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rok_l" attribute \generator "nMigen" module \rok_l$71 - attribute \src "libresoc.v:185348.7-185348.20" + attribute \src "libresoc.v:185347.7-185347.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185393.3-185401.6" + attribute \src "libresoc.v:185392.3-185400.6" wire $0\q_int$next[0:0]$12216 - attribute \src "libresoc.v:185391.3-185392.27" + attribute \src "libresoc.v:185390.3-185391.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185393.3-185401.6" + attribute \src "libresoc.v:185392.3-185400.6" wire $1\q_int$next[0:0]$12217 - attribute \src "libresoc.v:185370.7-185370.19" + attribute \src "libresoc.v:185369.7-185369.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185383.17-185383.96" - wire $and$libresoc.v:185383$12206_Y - attribute \src "libresoc.v:185388.17-185388.96" - wire $and$libresoc.v:185388$12211_Y - attribute \src "libresoc.v:185385.18-185385.94" - wire $not$libresoc.v:185385$12208_Y - attribute \src "libresoc.v:185387.17-185387.93" - wire $not$libresoc.v:185387$12210_Y - attribute \src "libresoc.v:185390.17-185390.93" - wire $not$libresoc.v:185390$12213_Y - attribute \src "libresoc.v:185384.18-185384.99" - wire $or$libresoc.v:185384$12207_Y - attribute \src "libresoc.v:185386.18-185386.100" - wire $or$libresoc.v:185386$12209_Y - attribute \src "libresoc.v:185389.17-185389.98" - wire $or$libresoc.v:185389$12212_Y + attribute \src "libresoc.v:185382.17-185382.96" + wire $and$libresoc.v:185382$12206_Y + attribute \src "libresoc.v:185387.17-185387.96" + wire $and$libresoc.v:185387$12211_Y + attribute \src "libresoc.v:185384.18-185384.94" + wire $not$libresoc.v:185384$12208_Y + attribute \src "libresoc.v:185386.17-185386.93" + wire $not$libresoc.v:185386$12210_Y + attribute \src "libresoc.v:185389.17-185389.93" + wire $not$libresoc.v:185389$12213_Y + attribute \src "libresoc.v:185383.18-185383.99" + wire $or$libresoc.v:185383$12207_Y + attribute \src "libresoc.v:185385.18-185385.100" + wire $or$libresoc.v:185385$12209_Y + attribute \src "libresoc.v:185388.17-185388.98" + wire $or$libresoc.v:185388$12212_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -383633,7 +380443,7 @@ module \rok_l$71 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:185348.7-185348.15" + attribute \src "libresoc.v:185347.7-185347.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -383650,7 +380460,7 @@ module \rok_l$71 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185383$12206 + cell $and $and$libresoc.v:185382$12206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383658,10 +380468,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185383$12206_Y + connect \Y $and$libresoc.v:185382$12206_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185388$12211 + cell $and $and$libresoc.v:185387$12211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383669,34 +380479,34 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185388$12211_Y + connect \Y $and$libresoc.v:185387$12211_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185385$12208 + cell $not $not$libresoc.v:185384$12208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185385$12208_Y + connect \Y $not$libresoc.v:185384$12208_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185387$12210 + cell $not $not$libresoc.v:185386$12210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185387$12210_Y + connect \Y $not$libresoc.v:185386$12210_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185390$12213 + cell $not $not$libresoc.v:185389$12213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185390$12213_Y + connect \Y $not$libresoc.v:185389$12213_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185384$12207 + cell $or $or$libresoc.v:185383$12207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383704,10 +380514,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185384$12207_Y + connect \Y $or$libresoc.v:185383$12207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185386$12209 + cell $or $or$libresoc.v:185385$12209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383715,10 +380525,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185386$12209_Y + connect \Y $or$libresoc.v:185385$12209_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185389$12212 + cell $or $or$libresoc.v:185388$12212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383726,39 +380536,39 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185389$12212_Y + connect \Y $or$libresoc.v:185388$12212_Y end - attribute \src "libresoc.v:185348.7-185348.20" - process $proc$libresoc.v:185348$12218 + attribute \src "libresoc.v:185347.7-185347.20" + process $proc$libresoc.v:185347$12218 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185370.7-185370.19" - process $proc$libresoc.v:185370$12219 + attribute \src "libresoc.v:185369.7-185369.19" + process $proc$libresoc.v:185369$12219 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185391.3-185392.27" - process $proc$libresoc.v:185391$12214 + attribute \src "libresoc.v:185390.3-185391.27" + process $proc$libresoc.v:185390$12214 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185393.3-185401.6" - process $proc$libresoc.v:185393$12215 + attribute \src "libresoc.v:185392.3-185400.6" + process $proc$libresoc.v:185392$12215 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12216 $1\q_int$next[0:0]$12217 - attribute \src "libresoc.v:185394.5-185394.29" + attribute \src "libresoc.v:185393.5-185393.29" switch \initial - attribute \src "libresoc.v:185394.9-185394.17" + attribute \src "libresoc.v:185393.9-185393.17" case 1'1 case end @@ -383774,49 +380584,49 @@ module \rok_l$71 sync always update \q_int$next $0\q_int$next[0:0]$12216 end - connect \$9 $and$libresoc.v:185383$12206_Y - connect \$11 $or$libresoc.v:185384$12207_Y - connect \$13 $not$libresoc.v:185385$12208_Y - connect \$15 $or$libresoc.v:185386$12209_Y - connect \$1 $not$libresoc.v:185387$12210_Y - connect \$3 $and$libresoc.v:185388$12211_Y - connect \$5 $or$libresoc.v:185389$12212_Y - connect \$7 $not$libresoc.v:185390$12213_Y + connect \$9 $and$libresoc.v:185382$12206_Y + connect \$11 $or$libresoc.v:185383$12207_Y + connect \$13 $not$libresoc.v:185384$12208_Y + connect \$15 $or$libresoc.v:185385$12209_Y + connect \$1 $not$libresoc.v:185386$12210_Y + connect \$3 $and$libresoc.v:185387$12211_Y + connect \$5 $or$libresoc.v:185388$12212_Y + connect \$7 $not$libresoc.v:185389$12213_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185409.1-185467.10" +attribute \src "libresoc.v:185408.1-185466.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rok_l" attribute \generator "nMigen" module \rok_l$88 - attribute \src "libresoc.v:185410.7-185410.20" + attribute \src "libresoc.v:185409.7-185409.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185455.3-185463.6" + attribute \src "libresoc.v:185454.3-185462.6" wire $0\q_int$next[0:0]$12230 - attribute \src "libresoc.v:185453.3-185454.27" + attribute \src "libresoc.v:185452.3-185453.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185455.3-185463.6" + attribute \src "libresoc.v:185454.3-185462.6" wire $1\q_int$next[0:0]$12231 - attribute \src "libresoc.v:185432.7-185432.19" + attribute \src "libresoc.v:185431.7-185431.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185445.17-185445.96" - wire $and$libresoc.v:185445$12220_Y - attribute \src "libresoc.v:185450.17-185450.96" - wire $and$libresoc.v:185450$12225_Y - attribute \src "libresoc.v:185447.18-185447.94" - wire $not$libresoc.v:185447$12222_Y - attribute \src "libresoc.v:185449.17-185449.93" - wire $not$libresoc.v:185449$12224_Y - attribute \src "libresoc.v:185452.17-185452.93" - wire $not$libresoc.v:185452$12227_Y - attribute \src "libresoc.v:185446.18-185446.99" - wire $or$libresoc.v:185446$12221_Y - attribute \src "libresoc.v:185448.18-185448.100" - wire $or$libresoc.v:185448$12223_Y - attribute \src "libresoc.v:185451.17-185451.98" - wire $or$libresoc.v:185451$12226_Y + attribute \src "libresoc.v:185444.17-185444.96" + wire $and$libresoc.v:185444$12220_Y + attribute \src "libresoc.v:185449.17-185449.96" + wire $and$libresoc.v:185449$12225_Y + attribute \src "libresoc.v:185446.18-185446.94" + wire $not$libresoc.v:185446$12222_Y + attribute \src "libresoc.v:185448.17-185448.93" + wire $not$libresoc.v:185448$12224_Y + attribute \src "libresoc.v:185451.17-185451.93" + wire $not$libresoc.v:185451$12227_Y + attribute \src "libresoc.v:185445.18-185445.99" + wire $or$libresoc.v:185445$12221_Y + attribute \src "libresoc.v:185447.18-185447.100" + wire $or$libresoc.v:185447$12223_Y + attribute \src "libresoc.v:185450.17-185450.98" + wire $or$libresoc.v:185450$12226_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -383837,7 +380647,7 @@ module \rok_l$88 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:185410.7-185410.15" + attribute \src "libresoc.v:185409.7-185409.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -383854,7 +380664,7 @@ module \rok_l$88 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185445$12220 + cell $and $and$libresoc.v:185444$12220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383862,10 +380672,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185445$12220_Y + connect \Y $and$libresoc.v:185444$12220_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185450$12225 + cell $and $and$libresoc.v:185449$12225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383873,34 +380683,34 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185450$12225_Y + connect \Y $and$libresoc.v:185449$12225_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185447$12222 + cell $not $not$libresoc.v:185446$12222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185447$12222_Y + connect \Y $not$libresoc.v:185446$12222_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185449$12224 + cell $not $not$libresoc.v:185448$12224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185449$12224_Y + connect \Y $not$libresoc.v:185448$12224_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185452$12227 + cell $not $not$libresoc.v:185451$12227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185452$12227_Y + connect \Y $not$libresoc.v:185451$12227_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185446$12221 + cell $or $or$libresoc.v:185445$12221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383908,10 +380718,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185446$12221_Y + connect \Y $or$libresoc.v:185445$12221_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185448$12223 + cell $or $or$libresoc.v:185447$12223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383919,10 +380729,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185448$12223_Y + connect \Y $or$libresoc.v:185447$12223_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185451$12226 + cell $or $or$libresoc.v:185450$12226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383930,39 +380740,39 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185451$12226_Y + connect \Y $or$libresoc.v:185450$12226_Y end - attribute \src "libresoc.v:185410.7-185410.20" - process $proc$libresoc.v:185410$12232 + attribute \src "libresoc.v:185409.7-185409.20" + process $proc$libresoc.v:185409$12232 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185432.7-185432.19" - process $proc$libresoc.v:185432$12233 + attribute \src "libresoc.v:185431.7-185431.19" + process $proc$libresoc.v:185431$12233 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185453.3-185454.27" - process $proc$libresoc.v:185453$12228 + attribute \src "libresoc.v:185452.3-185453.27" + process $proc$libresoc.v:185452$12228 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185455.3-185463.6" - process $proc$libresoc.v:185455$12229 + attribute \src "libresoc.v:185454.3-185462.6" + process $proc$libresoc.v:185454$12229 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12230 $1\q_int$next[0:0]$12231 - attribute \src "libresoc.v:185456.5-185456.29" + attribute \src "libresoc.v:185455.5-185455.29" switch \initial - attribute \src "libresoc.v:185456.9-185456.17" + attribute \src "libresoc.v:185455.9-185455.17" case 1'1 case end @@ -383978,143 +380788,143 @@ module \rok_l$88 sync always update \q_int$next $0\q_int$next[0:0]$12230 end - connect \$9 $and$libresoc.v:185445$12220_Y - connect \$11 $or$libresoc.v:185446$12221_Y - connect \$13 $not$libresoc.v:185447$12222_Y - connect \$15 $or$libresoc.v:185448$12223_Y - connect \$1 $not$libresoc.v:185449$12224_Y - connect \$3 $and$libresoc.v:185450$12225_Y - connect \$5 $or$libresoc.v:185451$12226_Y - connect \$7 $not$libresoc.v:185452$12227_Y + connect \$9 $and$libresoc.v:185444$12220_Y + connect \$11 $or$libresoc.v:185445$12221_Y + connect \$13 $not$libresoc.v:185446$12222_Y + connect \$15 $or$libresoc.v:185447$12223_Y + connect \$1 $not$libresoc.v:185448$12224_Y + connect \$3 $and$libresoc.v:185449$12225_Y + connect \$5 $or$libresoc.v:185450$12226_Y + connect \$7 $not$libresoc.v:185451$12227_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185471.1-185822.10" +attribute \src "libresoc.v:185470.1-185821.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" attribute \generator "nMigen" module \rotator - attribute \src "libresoc.v:185740.3-185749.6" + attribute \src "libresoc.v:185739.3-185748.6" wire $0\carry_out_o[0:0] - attribute \src "libresoc.v:185672.3-185686.6" + attribute \src "libresoc.v:185671.3-185685.6" wire width 32 $0\hi32[31:0] - attribute \src "libresoc.v:185472.7-185472.20" + attribute \src "libresoc.v:185471.7-185471.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185762.3-185795.6" + attribute \src "libresoc.v:185761.3-185794.6" wire width 7 $0\mb$8[6:0]$12281 - attribute \src "libresoc.v:185796.3-185810.6" + attribute \src "libresoc.v:185795.3-185809.6" wire width 7 $0\me$13[6:0]$12286 - attribute \src "libresoc.v:185697.3-185708.6" + attribute \src "libresoc.v:185696.3-185707.6" wire width 64 $0\mr[63:0] - attribute \src "libresoc.v:185709.3-185720.6" + attribute \src "libresoc.v:185708.3-185719.6" wire width 2 $0\output_mode[1:0] - attribute \src "libresoc.v:185721.3-185739.6" + attribute \src "libresoc.v:185720.3-185738.6" wire width 64 $0\result_o[63:0] - attribute \src "libresoc.v:185687.3-185696.6" + attribute \src "libresoc.v:185686.3-185695.6" wire width 7 $0\right_mask_shift[6:0] - attribute \src "libresoc.v:185750.3-185761.6" + attribute \src "libresoc.v:185749.3-185760.6" wire width 6 $0\rot_count[5:0] - attribute \src "libresoc.v:185740.3-185749.6" + attribute \src "libresoc.v:185739.3-185748.6" wire $1\carry_out_o[0:0] - attribute \src "libresoc.v:185672.3-185686.6" + attribute \src "libresoc.v:185671.3-185685.6" wire width 32 $1\hi32[31:0] - attribute \src "libresoc.v:185762.3-185795.6" + attribute \src "libresoc.v:185761.3-185794.6" wire width 7 $1\mb$8[6:0]$12282 - attribute \src "libresoc.v:185796.3-185810.6" + attribute \src "libresoc.v:185795.3-185809.6" wire width 7 $1\me$13[6:0]$12287 - attribute \src "libresoc.v:185697.3-185708.6" + attribute \src "libresoc.v:185696.3-185707.6" wire width 64 $1\mr[63:0] - attribute \src "libresoc.v:185709.3-185720.6" + attribute \src "libresoc.v:185708.3-185719.6" wire width 2 $1\output_mode[1:0] - attribute \src "libresoc.v:185721.3-185739.6" + attribute \src "libresoc.v:185720.3-185738.6" wire width 64 $1\result_o[63:0] - attribute \src "libresoc.v:185687.3-185696.6" + attribute \src "libresoc.v:185686.3-185695.6" wire width 7 $1\right_mask_shift[6:0] - attribute \src "libresoc.v:185750.3-185761.6" + attribute \src "libresoc.v:185749.3-185760.6" wire width 6 $1\rot_count[5:0] - attribute \src "libresoc.v:185762.3-185795.6" + attribute \src "libresoc.v:185761.3-185794.6" wire width 2 $2\mb$8[6:5]$12283 - attribute \src "libresoc.v:185762.3-185795.6" + attribute \src "libresoc.v:185761.3-185794.6" wire width 2 $3\mb$8[6:5]$12284 - attribute \src "libresoc.v:185623.18-185623.118" - wire $and$libresoc.v:185623$12237_Y - attribute \src "libresoc.v:185625.18-185625.114" - wire $and$libresoc.v:185625$12239_Y - attribute \src "libresoc.v:185634.18-185634.113" - wire $and$libresoc.v:185634$12248_Y - attribute \src "libresoc.v:185636.18-185636.114" - wire $and$libresoc.v:185636$12250_Y - attribute \src "libresoc.v:185638.18-185638.114" - wire $and$libresoc.v:185638$12252_Y - attribute \src "libresoc.v:185639.18-185639.103" - wire width 64 $and$libresoc.v:185639$12253_Y - attribute \src "libresoc.v:185640.18-185640.106" - wire width 64 $and$libresoc.v:185640$12254_Y - attribute \src "libresoc.v:185642.18-185642.103" - wire width 64 $and$libresoc.v:185642$12256_Y - attribute \src "libresoc.v:185644.18-185644.105" - wire width 64 $and$libresoc.v:185644$12258_Y - attribute \src "libresoc.v:185647.18-185647.106" - wire width 64 $and$libresoc.v:185647$12261_Y - attribute \src "libresoc.v:185650.18-185650.105" - wire width 64 $and$libresoc.v:185650$12264_Y - attribute \src "libresoc.v:185652.17-185652.109" - wire $and$libresoc.v:185652$12266_Y - attribute \src "libresoc.v:185653.18-185653.104" - wire width 64 $and$libresoc.v:185653$12267_Y - attribute \src "libresoc.v:185657.18-185657.105" - wire width 64 $and$libresoc.v:185657$12271_Y - attribute \src "libresoc.v:185621.17-185621.98" - wire width 7 $extend$libresoc.v:185621$12234_Y - attribute \src "libresoc.v:185637.18-185637.122" - wire $gt$libresoc.v:185637$12251_Y - attribute \src "libresoc.v:185627.18-185627.111" - wire $le$libresoc.v:185627$12241_Y - attribute \src "libresoc.v:185629.18-185629.111" - wire $le$libresoc.v:185629$12243_Y - attribute \src "libresoc.v:185630.17-185630.117" - wire width 7 $neg$libresoc.v:185630$12244_Y - attribute \src "libresoc.v:185622.18-185622.103" - wire $not$libresoc.v:185622$12236_Y - attribute \src "libresoc.v:185624.18-185624.108" - wire $not$libresoc.v:185624$12238_Y - attribute \src "libresoc.v:185626.18-185626.105" - wire width 6 $not$libresoc.v:185626$12240_Y - attribute \src "libresoc.v:185632.18-185632.112" - wire width 64 $not$libresoc.v:185632$12246_Y - attribute \src "libresoc.v:185633.18-185633.109" - wire $not$libresoc.v:185633$12247_Y - attribute \src "libresoc.v:185641.17-185641.105" - wire $not$libresoc.v:185641$12255_Y - attribute \src "libresoc.v:185643.18-185643.102" - wire width 64 $not$libresoc.v:185643$12257_Y - attribute \src "libresoc.v:185649.18-185649.102" - wire width 64 $not$libresoc.v:185649$12263_Y - attribute \src "libresoc.v:185654.18-185654.100" - wire width 64 $not$libresoc.v:185654$12268_Y - attribute \src "libresoc.v:185656.18-185656.100" - wire width 64 $not$libresoc.v:185656$12270_Y - attribute \src "libresoc.v:185635.18-185635.115" - wire $or$libresoc.v:185635$12249_Y - attribute \src "libresoc.v:185645.18-185645.108" - wire width 64 $or$libresoc.v:185645$12259_Y - attribute \src "libresoc.v:185646.18-185646.103" - wire width 64 $or$libresoc.v:185646$12260_Y - attribute \src "libresoc.v:185648.18-185648.103" - wire width 64 $or$libresoc.v:185648$12262_Y - attribute \src "libresoc.v:185651.18-185651.108" - wire width 64 $or$libresoc.v:185651$12265_Y - attribute \src "libresoc.v:185655.18-185655.106" - wire width 64 $or$libresoc.v:185655$12269_Y - attribute \src "libresoc.v:185621.17-185621.98" - wire width 7 $pos$libresoc.v:185621$12235_Y - attribute \src "libresoc.v:185658.18-185658.102" - wire $reduce_or$libresoc.v:185658$12272_Y - attribute \src "libresoc.v:185628.18-185628.109" - wire width 8 $sub$libresoc.v:185628$12242_Y - attribute \src "libresoc.v:185631.18-185631.110" - wire width 8 $sub$libresoc.v:185631$12245_Y + attribute \src "libresoc.v:185622.18-185622.118" + wire $and$libresoc.v:185622$12237_Y + attribute \src "libresoc.v:185624.18-185624.114" + wire $and$libresoc.v:185624$12239_Y + attribute \src "libresoc.v:185633.18-185633.113" + wire $and$libresoc.v:185633$12248_Y + attribute \src "libresoc.v:185635.18-185635.114" + wire $and$libresoc.v:185635$12250_Y + attribute \src "libresoc.v:185637.18-185637.114" + wire $and$libresoc.v:185637$12252_Y + attribute \src "libresoc.v:185638.18-185638.103" + wire width 64 $and$libresoc.v:185638$12253_Y + attribute \src "libresoc.v:185639.18-185639.106" + wire width 64 $and$libresoc.v:185639$12254_Y + attribute \src "libresoc.v:185641.18-185641.103" + wire width 64 $and$libresoc.v:185641$12256_Y + attribute \src "libresoc.v:185643.18-185643.105" + wire width 64 $and$libresoc.v:185643$12258_Y + attribute \src "libresoc.v:185646.18-185646.106" + wire width 64 $and$libresoc.v:185646$12261_Y + attribute \src "libresoc.v:185649.18-185649.105" + wire width 64 $and$libresoc.v:185649$12264_Y + attribute \src "libresoc.v:185651.17-185651.109" + wire $and$libresoc.v:185651$12266_Y + attribute \src "libresoc.v:185652.18-185652.104" + wire width 64 $and$libresoc.v:185652$12267_Y + attribute \src "libresoc.v:185656.18-185656.105" + wire width 64 $and$libresoc.v:185656$12271_Y + attribute \src "libresoc.v:185620.17-185620.98" + wire width 7 $extend$libresoc.v:185620$12234_Y + attribute \src "libresoc.v:185636.18-185636.122" + wire $gt$libresoc.v:185636$12251_Y + attribute \src "libresoc.v:185626.18-185626.111" + wire $le$libresoc.v:185626$12241_Y + attribute \src "libresoc.v:185628.18-185628.111" + wire $le$libresoc.v:185628$12243_Y + attribute \src "libresoc.v:185629.17-185629.117" + wire width 7 $neg$libresoc.v:185629$12244_Y + attribute \src "libresoc.v:185621.18-185621.103" + wire $not$libresoc.v:185621$12236_Y + attribute \src "libresoc.v:185623.18-185623.108" + wire $not$libresoc.v:185623$12238_Y + attribute \src "libresoc.v:185625.18-185625.105" + wire width 6 $not$libresoc.v:185625$12240_Y + attribute \src "libresoc.v:185631.18-185631.112" + wire width 64 $not$libresoc.v:185631$12246_Y + attribute \src "libresoc.v:185632.18-185632.109" + wire $not$libresoc.v:185632$12247_Y + attribute \src "libresoc.v:185640.17-185640.105" + wire $not$libresoc.v:185640$12255_Y + attribute \src "libresoc.v:185642.18-185642.102" + wire width 64 $not$libresoc.v:185642$12257_Y + attribute \src "libresoc.v:185648.18-185648.102" + wire width 64 $not$libresoc.v:185648$12263_Y + attribute \src "libresoc.v:185653.18-185653.100" + wire width 64 $not$libresoc.v:185653$12268_Y + attribute \src "libresoc.v:185655.18-185655.100" + wire width 64 $not$libresoc.v:185655$12270_Y + attribute \src "libresoc.v:185634.18-185634.115" + wire $or$libresoc.v:185634$12249_Y + attribute \src "libresoc.v:185644.18-185644.108" + wire width 64 $or$libresoc.v:185644$12259_Y + attribute \src "libresoc.v:185645.18-185645.103" + wire width 64 $or$libresoc.v:185645$12260_Y + attribute \src "libresoc.v:185647.18-185647.103" + wire width 64 $or$libresoc.v:185647$12262_Y + attribute \src "libresoc.v:185650.18-185650.108" + wire width 64 $or$libresoc.v:185650$12265_Y + attribute \src "libresoc.v:185654.18-185654.106" + wire width 64 $or$libresoc.v:185654$12269_Y + attribute \src "libresoc.v:185620.17-185620.98" + wire width 7 $pos$libresoc.v:185620$12235_Y + attribute \src "libresoc.v:185657.18-185657.102" + wire $reduce_or$libresoc.v:185657$12272_Y + attribute \src "libresoc.v:185627.18-185627.109" + wire width 8 $sub$libresoc.v:185627$12242_Y + attribute \src "libresoc.v:185630.18-185630.110" + wire width 8 $sub$libresoc.v:185630$12245_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" wire width 7 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" @@ -384207,7 +381017,7 @@ module \rotator wire input 10 \clear_right attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81" wire width 32 \hi32 - attribute \src "libresoc.v:185472.7-185472.15" + attribute \src "libresoc.v:185471.7-185471.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" wire input 6 \is_32bit @@ -384264,7 +381074,7 @@ module \rotator attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" wire input 11 \sign_ext_rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - cell $and $and$libresoc.v:185623$12237 + cell $and $and$libresoc.v:185622$12237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384272,10 +381082,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \is_32bit - connect \Y $and$libresoc.v:185623$12237_Y + connect \Y $and$libresoc.v:185622$12237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $and $and$libresoc.v:185625$12239 + cell $and $and$libresoc.v:185624$12239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384283,10 +381093,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$16 - connect \Y $and$libresoc.v:185625$12239_Y + connect \Y $and$libresoc.v:185624$12239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $and $and$libresoc.v:185634$12248 + cell $and $and$libresoc.v:185633$12248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384294,10 +381104,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_left connect \B \$34 - connect \Y $and$libresoc.v:185634$12248_Y + connect \Y $and$libresoc.v:185633$12248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" - cell $and $and$libresoc.v:185636$12250 + cell $and $and$libresoc.v:185635$12250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384305,10 +381115,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \arith connect \B \repl32 [63] - connect \Y $and$libresoc.v:185636$12250_Y + connect \Y $and$libresoc.v:185635$12250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $and $and$libresoc.v:185638$12252 + cell $and $and$libresoc.v:185637$12252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384316,10 +381126,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$42 - connect \Y $and$libresoc.v:185638$12252_Y + connect \Y $and$libresoc.v:185637$12252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:185639$12253 + cell $and $and$libresoc.v:185638$12253 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384327,10 +381137,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:185639$12253_Y + connect \Y $and$libresoc.v:185638$12253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:185640$12254 + cell $and $and$libresoc.v:185639$12254 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384338,10 +381148,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$46 - connect \Y $and$libresoc.v:185640$12254_Y + connect \Y $and$libresoc.v:185639$12254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:185642$12256 + cell $and $and$libresoc.v:185641$12256 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384349,10 +381159,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:185642$12256_Y + connect \Y $and$libresoc.v:185641$12256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:185644$12258 + cell $and $and$libresoc.v:185643$12258 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384360,10 +381170,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$50 - connect \Y $and$libresoc.v:185644$12258_Y + connect \Y $and$libresoc.v:185643$12258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:185647$12261 + cell $and $and$libresoc.v:185646$12261 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384371,10 +381181,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$58 - connect \Y $and$libresoc.v:185647$12261_Y + connect \Y $and$libresoc.v:185646$12261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:185650$12264 + cell $and $and$libresoc.v:185649$12264 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384382,10 +381192,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$62 - connect \Y $and$libresoc.v:185650$12264_Y + connect \Y $and$libresoc.v:185649$12264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $and $and$libresoc.v:185652$12266 + cell $and $and$libresoc.v:185651$12266 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384393,10 +381203,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \shift [6] connect \B \$4 - connect \Y $and$libresoc.v:185652$12266_Y + connect \Y $and$libresoc.v:185651$12266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" - cell $and $and$libresoc.v:185653$12267 + cell $and $and$libresoc.v:185652$12267 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384404,10 +381214,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \mr - connect \Y $and$libresoc.v:185653$12267_Y + connect \Y $and$libresoc.v:185652$12267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $and $and$libresoc.v:185657$12271 + cell $and $and$libresoc.v:185656$12271 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384415,18 +381225,18 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rs connect \B \$77 - connect \Y $and$libresoc.v:185657$12271_Y + connect \Y $and$libresoc.v:185656$12271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $extend$libresoc.v:185621$12234 + cell $pos $extend$libresoc.v:185620$12234 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \mb - connect \Y $extend$libresoc.v:185621$12234_Y + connect \Y $extend$libresoc.v:185620$12234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $gt $gt$libresoc.v:185637$12251 + cell $gt $gt$libresoc.v:185636$12251 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -384434,10 +381244,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 [5:0] connect \B \me$13 [5:0] - connect \Y $gt$libresoc.v:185637$12251_Y + connect \Y $gt$libresoc.v:185636$12251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:185627$12241 + cell $le $le$libresoc.v:185626$12241 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -384445,10 +381255,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:185627$12241_Y + connect \Y $le$libresoc.v:185626$12241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:185629$12243 + cell $le $le$libresoc.v:185628$12243 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -384456,98 +381266,98 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:185629$12243_Y + connect \Y $le$libresoc.v:185628$12243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" - cell $neg $neg$libresoc.v:185630$12244 + cell $neg $neg$libresoc.v:185629$12244 parameter \A_SIGNED 1 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A { \shift_signed [5] \shift_signed } - connect \Y $neg$libresoc.v:185630$12244_Y + connect \Y $neg$libresoc.v:185629$12244_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" - cell $not $not$libresoc.v:185622$12236 + cell $not $not$libresoc.v:185621$12236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sh [5] - connect \Y $not$libresoc.v:185622$12236_Y + connect \Y $not$libresoc.v:185621$12236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $not $not$libresoc.v:185624$12238 + cell $not $not$libresoc.v:185623$12238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_left - connect \Y $not$libresoc.v:185624$12238_Y + connect \Y $not$libresoc.v:185623$12238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" - cell $not $not$libresoc.v:185626$12240 + cell $not $not$libresoc.v:185625$12240 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \sh [5:0] - connect \Y $not$libresoc.v:185626$12240_Y + connect \Y $not$libresoc.v:185625$12240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" - cell $not $not$libresoc.v:185632$12246 + cell $not $not$libresoc.v:185631$12246 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \left_mask_mask - connect \Y $not$libresoc.v:185632$12246_Y + connect \Y $not$libresoc.v:185631$12246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $not $not$libresoc.v:185633$12247 + cell $not $not$libresoc.v:185632$12247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_right - connect \Y $not$libresoc.v:185633$12247_Y + connect \Y $not$libresoc.v:185632$12247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $not $not$libresoc.v:185641$12255 + cell $not $not$libresoc.v:185640$12255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_32bit - connect \Y $not$libresoc.v:185641$12255_Y + connect \Y $not$libresoc.v:185640$12255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $not $not$libresoc.v:185643$12257 + cell $not $not$libresoc.v:185642$12257 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$51 - connect \Y $not$libresoc.v:185643$12257_Y + connect \Y $not$libresoc.v:185642$12257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $not $not$libresoc.v:185649$12263 + cell $not $not$libresoc.v:185648$12263 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$63 - connect \Y $not$libresoc.v:185649$12263_Y + connect \Y $not$libresoc.v:185648$12263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $not $not$libresoc.v:185654$12268 + cell $not $not$libresoc.v:185653$12268 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \mr - connect \Y $not$libresoc.v:185654$12268_Y + connect \Y $not$libresoc.v:185653$12268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $not $not$libresoc.v:185656$12270 + cell $not $not$libresoc.v:185655$12270 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ml - connect \Y $not$libresoc.v:185656$12270_Y + connect \Y $not$libresoc.v:185655$12270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $or $or$libresoc.v:185635$12249 + cell $or $or$libresoc.v:185634$12249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384555,10 +381365,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \$36 connect \B \right_shift - connect \Y $or$libresoc.v:185635$12249_Y + connect \Y $or$libresoc.v:185634$12249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $or $or$libresoc.v:185645$12259 + cell $or $or$libresoc.v:185644$12259 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384566,10 +381376,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$48 connect \B \$54 - connect \Y $or$libresoc.v:185645$12259_Y + connect \Y $or$libresoc.v:185644$12259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:185646$12260 + cell $or $or$libresoc.v:185645$12260 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384577,10 +381387,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:185646$12260_Y + connect \Y $or$libresoc.v:185645$12260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:185648$12262 + cell $or $or$libresoc.v:185647$12262 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384588,10 +381398,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:185648$12262_Y + connect \Y $or$libresoc.v:185647$12262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:185651$12265 + cell $or $or$libresoc.v:185650$12265 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384599,10 +381409,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$60 connect \B \$66 - connect \Y $or$libresoc.v:185651$12265_Y + connect \Y $or$libresoc.v:185650$12265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $or $or$libresoc.v:185655$12269 + cell $or $or$libresoc.v:185654$12269 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384610,26 +381420,26 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$72 - connect \Y $or$libresoc.v:185655$12269_Y + connect \Y $or$libresoc.v:185654$12269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $pos$libresoc.v:185621$12235 + cell $pos $pos$libresoc.v:185620$12235 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:185621$12234_Y - connect \Y $pos$libresoc.v:185621$12235_Y + connect \A $extend$libresoc.v:185620$12234_Y + connect \Y $pos$libresoc.v:185620$12235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $reduce_or $reduce_or$libresoc.v:185658$12272 + cell $reduce_or $reduce_or$libresoc.v:185657$12272 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \$79 - connect \Y $reduce_or$libresoc.v:185658$12272_Y + connect \Y $reduce_or$libresoc.v:185657$12272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" - cell $sub $sub$libresoc.v:185628$12242 + cell $sub $sub$libresoc.v:185627$12242 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -384637,10 +381447,10 @@ module \rotator parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \mb$8 - connect \Y $sub$libresoc.v:185628$12242_Y + connect \Y $sub$libresoc.v:185627$12242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" - cell $sub $sub$libresoc.v:185631$12245 + cell $sub $sub$libresoc.v:185630$12245 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -384648,42 +381458,42 @@ module \rotator parameter \Y_WIDTH 8 connect \A 6'111111 connect \B \me$13 - connect \Y $sub$libresoc.v:185631$12245_Y + connect \Y $sub$libresoc.v:185630$12245_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:185659.13-185662.4" + attribute \src "libresoc.v:185658.13-185661.4" cell \left_mask \left_mask connect \mask \left_mask_mask connect \shift \left_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:185663.14-185666.4" + attribute \src "libresoc.v:185662.14-185665.4" cell \right_mask \right_mask connect \mask \right_mask_mask connect \shift \right_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:185667.8-185671.4" + attribute \src "libresoc.v:185666.8-185670.4" cell \rotl \rotl connect \a \rotl_a connect \b \rotl_b connect \o \rotl_o end - attribute \src "libresoc.v:185472.7-185472.20" - process $proc$libresoc.v:185472$12288 + attribute \src "libresoc.v:185471.7-185471.20" + process $proc$libresoc.v:185471$12288 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185672.3-185686.6" - process $proc$libresoc.v:185672$12273 + attribute \src "libresoc.v:185671.3-185685.6" + process $proc$libresoc.v:185671$12273 assign { } { } assign $0\hi32[31:0] $1\hi32[31:0] - attribute \src "libresoc.v:185673.5-185673.29" + attribute \src "libresoc.v:185672.5-185672.29" switch \initial - attribute \src "libresoc.v:185673.9-185673.17" + attribute \src "libresoc.v:185672.9-185672.17" case 1'1 case end @@ -384705,14 +381515,14 @@ module \rotator sync always update \hi32 $0\hi32[31:0] end - attribute \src "libresoc.v:185687.3-185696.6" - process $proc$libresoc.v:185687$12274 + attribute \src "libresoc.v:185686.3-185695.6" + process $proc$libresoc.v:185686$12274 assign { } { } assign { } { } assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] - attribute \src "libresoc.v:185688.5-185688.29" + attribute \src "libresoc.v:185687.5-185687.29" switch \initial - attribute \src "libresoc.v:185688.9-185688.17" + attribute \src "libresoc.v:185687.9-185687.17" case 1'1 case end @@ -384728,13 +381538,13 @@ module \rotator sync always update \right_mask_shift $0\right_mask_shift[6:0] end - attribute \src "libresoc.v:185697.3-185708.6" - process $proc$libresoc.v:185697$12275 + attribute \src "libresoc.v:185696.3-185707.6" + process $proc$libresoc.v:185696$12275 assign { } { } assign $0\mr[63:0] $1\mr[63:0] - attribute \src "libresoc.v:185698.5-185698.29" + attribute \src "libresoc.v:185697.5-185697.29" switch \initial - attribute \src "libresoc.v:185698.9-185698.17" + attribute \src "libresoc.v:185697.9-185697.17" case 1'1 case end @@ -384752,13 +381562,13 @@ module \rotator sync always update \mr $0\mr[63:0] end - attribute \src "libresoc.v:185709.3-185720.6" - process $proc$libresoc.v:185709$12276 + attribute \src "libresoc.v:185708.3-185719.6" + process $proc$libresoc.v:185708$12276 assign { } { } assign $0\output_mode[1:0] $1\output_mode[1:0] - attribute \src "libresoc.v:185710.5-185710.29" + attribute \src "libresoc.v:185709.5-185709.29" switch \initial - attribute \src "libresoc.v:185710.9-185710.17" + attribute \src "libresoc.v:185709.9-185709.17" case 1'1 case end @@ -384776,14 +381586,14 @@ module \rotator sync always update \output_mode $0\output_mode[1:0] end - attribute \src "libresoc.v:185721.3-185739.6" - process $proc$libresoc.v:185721$12277 + attribute \src "libresoc.v:185720.3-185738.6" + process $proc$libresoc.v:185720$12277 assign { } { } assign { } { } assign $0\result_o[63:0] $1\result_o[63:0] - attribute \src "libresoc.v:185722.5-185722.29" + attribute \src "libresoc.v:185721.5-185721.29" switch \initial - attribute \src "libresoc.v:185722.9-185722.17" + attribute \src "libresoc.v:185721.9-185721.17" case 1'1 case end @@ -384811,14 +381621,14 @@ module \rotator sync always update \result_o $0\result_o[63:0] end - attribute \src "libresoc.v:185740.3-185749.6" - process $proc$libresoc.v:185740$12278 + attribute \src "libresoc.v:185739.3-185748.6" + process $proc$libresoc.v:185739$12278 assign { } { } assign { } { } assign $0\carry_out_o[0:0] $1\carry_out_o[0:0] - attribute \src "libresoc.v:185741.5-185741.29" + attribute \src "libresoc.v:185740.5-185740.29" switch \initial - attribute \src "libresoc.v:185741.9-185741.17" + attribute \src "libresoc.v:185740.9-185740.17" case 1'1 case end @@ -384834,13 +381644,13 @@ module \rotator sync always update \carry_out_o $0\carry_out_o[0:0] end - attribute \src "libresoc.v:185750.3-185761.6" - process $proc$libresoc.v:185750$12279 + attribute \src "libresoc.v:185749.3-185760.6" + process $proc$libresoc.v:185749$12279 assign { } { } assign $0\rot_count[5:0] $1\rot_count[5:0] - attribute \src "libresoc.v:185751.5-185751.29" + attribute \src "libresoc.v:185750.5-185750.29" switch \initial - attribute \src "libresoc.v:185751.9-185751.17" + attribute \src "libresoc.v:185750.9-185750.17" case 1'1 case end @@ -384858,13 +381668,13 @@ module \rotator sync always update \rot_count $0\rot_count[5:0] end - attribute \src "libresoc.v:185762.3-185795.6" - process $proc$libresoc.v:185762$12280 + attribute \src "libresoc.v:185761.3-185794.6" + process $proc$libresoc.v:185761$12280 assign { } { } assign $0\mb$8[6:0]$12281 $1\mb$8[6:0]$12282 - attribute \src "libresoc.v:185763.5-185763.29" + attribute \src "libresoc.v:185762.5-185762.29" switch \initial - attribute \src "libresoc.v:185763.9-185763.17" + attribute \src "libresoc.v:185762.9-185762.17" case 1'1 case end @@ -384908,13 +381718,13 @@ module \rotator sync always update \mb$8 $0\mb$8[6:0]$12281 end - attribute \src "libresoc.v:185796.3-185810.6" - process $proc$libresoc.v:185796$12285 + attribute \src "libresoc.v:185795.3-185809.6" + process $proc$libresoc.v:185795$12285 assign { } { } assign $0\me$13[6:0]$12286 $1\me$13[6:0]$12287 - attribute \src "libresoc.v:185797.5-185797.29" + attribute \src "libresoc.v:185796.5-185796.29" switch \initial - attribute \src "libresoc.v:185797.9-185797.17" + attribute \src "libresoc.v:185796.9-185796.17" case 1'1 case end @@ -384936,44 +381746,44 @@ module \rotator sync always update \me$13 $0\me$13[6:0]$12286 end - connect \$9 $pos$libresoc.v:185621$12235_Y - connect \$11 $not$libresoc.v:185622$12236_Y - connect \$14 $and$libresoc.v:185623$12237_Y - connect \$16 $not$libresoc.v:185624$12238_Y - connect \$18 $and$libresoc.v:185625$12239_Y - connect \$20 $not$libresoc.v:185626$12240_Y - connect \$22 $le$libresoc.v:185627$12241_Y - connect \$25 $sub$libresoc.v:185628$12242_Y - connect \$27 $le$libresoc.v:185629$12243_Y - connect \$2 $neg$libresoc.v:185630$12244_Y - connect \$30 $sub$libresoc.v:185631$12245_Y - connect \$32 $not$libresoc.v:185632$12246_Y - connect \$34 $not$libresoc.v:185633$12247_Y - connect \$36 $and$libresoc.v:185634$12248_Y - connect \$38 $or$libresoc.v:185635$12249_Y - connect \$40 $and$libresoc.v:185636$12250_Y - connect \$42 $gt$libresoc.v:185637$12251_Y - connect \$44 $and$libresoc.v:185638$12252_Y - connect \$46 $and$libresoc.v:185639$12253_Y - connect \$48 $and$libresoc.v:185640$12254_Y - connect \$4 $not$libresoc.v:185641$12255_Y - connect \$51 $and$libresoc.v:185642$12256_Y - connect \$50 $not$libresoc.v:185643$12257_Y - connect \$54 $and$libresoc.v:185644$12258_Y - connect \$56 $or$libresoc.v:185645$12259_Y - connect \$58 $or$libresoc.v:185646$12260_Y - connect \$60 $and$libresoc.v:185647$12261_Y - connect \$63 $or$libresoc.v:185648$12262_Y - connect \$62 $not$libresoc.v:185649$12263_Y - connect \$66 $and$libresoc.v:185650$12264_Y - connect \$68 $or$libresoc.v:185651$12265_Y - connect \$6 $and$libresoc.v:185652$12266_Y - connect \$70 $and$libresoc.v:185653$12267_Y - connect \$72 $not$libresoc.v:185654$12268_Y - connect \$74 $or$libresoc.v:185655$12269_Y - connect \$77 $not$libresoc.v:185656$12270_Y - connect \$79 $and$libresoc.v:185657$12271_Y - connect \$76 $reduce_or$libresoc.v:185658$12272_Y + connect \$9 $pos$libresoc.v:185620$12235_Y + connect \$11 $not$libresoc.v:185621$12236_Y + connect \$14 $and$libresoc.v:185622$12237_Y + connect \$16 $not$libresoc.v:185623$12238_Y + connect \$18 $and$libresoc.v:185624$12239_Y + connect \$20 $not$libresoc.v:185625$12240_Y + connect \$22 $le$libresoc.v:185626$12241_Y + connect \$25 $sub$libresoc.v:185627$12242_Y + connect \$27 $le$libresoc.v:185628$12243_Y + connect \$2 $neg$libresoc.v:185629$12244_Y + connect \$30 $sub$libresoc.v:185630$12245_Y + connect \$32 $not$libresoc.v:185631$12246_Y + connect \$34 $not$libresoc.v:185632$12247_Y + connect \$36 $and$libresoc.v:185633$12248_Y + connect \$38 $or$libresoc.v:185634$12249_Y + connect \$40 $and$libresoc.v:185635$12250_Y + connect \$42 $gt$libresoc.v:185636$12251_Y + connect \$44 $and$libresoc.v:185637$12252_Y + connect \$46 $and$libresoc.v:185638$12253_Y + connect \$48 $and$libresoc.v:185639$12254_Y + connect \$4 $not$libresoc.v:185640$12255_Y + connect \$51 $and$libresoc.v:185641$12256_Y + connect \$50 $not$libresoc.v:185642$12257_Y + connect \$54 $and$libresoc.v:185643$12258_Y + connect \$56 $or$libresoc.v:185644$12259_Y + connect \$58 $or$libresoc.v:185645$12260_Y + connect \$60 $and$libresoc.v:185646$12261_Y + connect \$63 $or$libresoc.v:185647$12262_Y + connect \$62 $not$libresoc.v:185648$12263_Y + connect \$66 $and$libresoc.v:185649$12264_Y + connect \$68 $or$libresoc.v:185650$12265_Y + connect \$6 $and$libresoc.v:185651$12266_Y + connect \$70 $and$libresoc.v:185652$12267_Y + connect \$72 $not$libresoc.v:185653$12268_Y + connect \$74 $or$libresoc.v:185654$12269_Y + connect \$77 $not$libresoc.v:185655$12270_Y + connect \$79 $and$libresoc.v:185656$12271_Y + connect \$76 $reduce_or$libresoc.v:185657$12272_Y connect \$1 \$2 connect \$24 \$25 connect \$29 \$30 @@ -384986,15 +381796,15 @@ module \rotator connect \shift_signed \shift [5:0] connect \repl32 { \hi32 \rs [31:0] } end -attribute \src "libresoc.v:185826.1-185840.10" +attribute \src "libresoc.v:185825.1-185839.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" attribute \generator "nMigen" module \rotl - attribute \src "libresoc.v:185838.17-185838.32" - wire width 128 $shr$libresoc.v:185838$12290_Y - attribute \src "libresoc.v:185837.17-185837.100" - wire width 8 $sub$libresoc.v:185837$12289_Y + attribute \src "libresoc.v:185837.17-185837.32" + wire width 128 $shr$libresoc.v:185837$12290_Y + attribute \src "libresoc.v:185836.17-185836.100" + wire width 8 $sub$libresoc.v:185836$12289_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" @@ -385005,8 +381815,8 @@ module \rotl wire width 6 input 1 \b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" wire width 64 output 2 \o - attribute \src "libresoc.v:185838.17-185838.32" - cell $shr $shr$libresoc.v:185838$12290 + attribute \src "libresoc.v:185837.17-185837.32" + cell $shr $shr$libresoc.v:185837$12290 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -385014,10 +381824,10 @@ module \rotl parameter \Y_WIDTH 128 connect \A { \a \a } connect \B \$2 - connect \Y $shr$libresoc.v:185838$12290_Y + connect \Y $shr$libresoc.v:185837$12290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - cell $sub $sub$libresoc.v:185837$12289 + cell $sub $sub$libresoc.v:185836$12289 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -385025,43 +381835,43 @@ module \rotl parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \b - connect \Y $sub$libresoc.v:185837$12289_Y + connect \Y $sub$libresoc.v:185836$12289_Y end - connect \$2 $sub$libresoc.v:185837$12289_Y - connect \$1 $shr$libresoc.v:185838$12290_Y [63:0] + connect \$2 $sub$libresoc.v:185836$12289_Y + connect \$1 $shr$libresoc.v:185837$12290_Y [63:0] connect \o \$1 end -attribute \src "libresoc.v:185844.1-185902.10" +attribute \src "libresoc.v:185843.1-185901.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rst_l" attribute \generator "nMigen" module \rst_l - attribute \src "libresoc.v:185845.7-185845.20" + attribute \src "libresoc.v:185844.7-185844.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185890.3-185898.6" + attribute \src "libresoc.v:185889.3-185897.6" wire $0\q_int$next[0:0]$12301 - attribute \src "libresoc.v:185888.3-185889.27" + attribute \src "libresoc.v:185887.3-185888.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185890.3-185898.6" + attribute \src "libresoc.v:185889.3-185897.6" wire $1\q_int$next[0:0]$12302 - attribute \src "libresoc.v:185867.7-185867.19" + attribute \src "libresoc.v:185866.7-185866.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185880.17-185880.96" - wire $and$libresoc.v:185880$12291_Y - attribute \src "libresoc.v:185885.17-185885.96" - wire $and$libresoc.v:185885$12296_Y - attribute \src "libresoc.v:185882.18-185882.93" - wire $not$libresoc.v:185882$12293_Y - attribute \src "libresoc.v:185884.17-185884.92" - wire $not$libresoc.v:185884$12295_Y - attribute \src "libresoc.v:185887.17-185887.92" - wire $not$libresoc.v:185887$12298_Y - attribute \src "libresoc.v:185881.18-185881.98" - wire $or$libresoc.v:185881$12292_Y - attribute \src "libresoc.v:185883.18-185883.99" - wire $or$libresoc.v:185883$12294_Y - attribute \src "libresoc.v:185886.17-185886.97" - wire $or$libresoc.v:185886$12297_Y + attribute \src "libresoc.v:185879.17-185879.96" + wire $and$libresoc.v:185879$12291_Y + attribute \src "libresoc.v:185884.17-185884.96" + wire $and$libresoc.v:185884$12296_Y + attribute \src "libresoc.v:185881.18-185881.93" + wire $not$libresoc.v:185881$12293_Y + attribute \src "libresoc.v:185883.17-185883.92" + wire $not$libresoc.v:185883$12295_Y + attribute \src "libresoc.v:185886.17-185886.92" + wire $not$libresoc.v:185886$12298_Y + attribute \src "libresoc.v:185880.18-185880.98" + wire $or$libresoc.v:185880$12292_Y + attribute \src "libresoc.v:185882.18-185882.99" + wire $or$libresoc.v:185882$12294_Y + attribute \src "libresoc.v:185885.17-185885.97" + wire $or$libresoc.v:185885$12297_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -385082,7 +381892,7 @@ module \rst_l wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:185845.7-185845.15" + attribute \src "libresoc.v:185844.7-185844.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -385099,7 +381909,7 @@ module \rst_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185880$12291 + cell $and $and$libresoc.v:185879$12291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385107,10 +381917,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185880$12291_Y + connect \Y $and$libresoc.v:185879$12291_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185885$12296 + cell $and $and$libresoc.v:185884$12296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385118,34 +381928,34 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185885$12296_Y + connect \Y $and$libresoc.v:185884$12296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185882$12293 + cell $not $not$libresoc.v:185881$12293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:185882$12293_Y + connect \Y $not$libresoc.v:185881$12293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185884$12295 + cell $not $not$libresoc.v:185883$12295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:185884$12295_Y + connect \Y $not$libresoc.v:185883$12295_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185887$12298 + cell $not $not$libresoc.v:185886$12298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:185887$12298_Y + connect \Y $not$libresoc.v:185886$12298_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185881$12292 + cell $or $or$libresoc.v:185880$12292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385153,10 +381963,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:185881$12292_Y + connect \Y $or$libresoc.v:185880$12292_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185883$12294 + cell $or $or$libresoc.v:185882$12294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385164,10 +381974,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:185883$12294_Y + connect \Y $or$libresoc.v:185882$12294_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185886$12297 + cell $or $or$libresoc.v:185885$12297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385175,39 +381985,39 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:185886$12297_Y + connect \Y $or$libresoc.v:185885$12297_Y end - attribute \src "libresoc.v:185845.7-185845.20" - process $proc$libresoc.v:185845$12303 + attribute \src "libresoc.v:185844.7-185844.20" + process $proc$libresoc.v:185844$12303 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185867.7-185867.19" - process $proc$libresoc.v:185867$12304 + attribute \src "libresoc.v:185866.7-185866.19" + process $proc$libresoc.v:185866$12304 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185888.3-185889.27" - process $proc$libresoc.v:185888$12299 + attribute \src "libresoc.v:185887.3-185888.27" + process $proc$libresoc.v:185887$12299 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185890.3-185898.6" - process $proc$libresoc.v:185890$12300 + attribute \src "libresoc.v:185889.3-185897.6" + process $proc$libresoc.v:185889$12300 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12301 $1\q_int$next[0:0]$12302 - attribute \src "libresoc.v:185891.5-185891.29" + attribute \src "libresoc.v:185890.5-185890.29" switch \initial - attribute \src "libresoc.v:185891.9-185891.17" + attribute \src "libresoc.v:185890.9-185890.17" case 1'1 case end @@ -385223,49 +382033,49 @@ module \rst_l sync always update \q_int$next $0\q_int$next[0:0]$12301 end - connect \$9 $and$libresoc.v:185880$12291_Y - connect \$11 $or$libresoc.v:185881$12292_Y - connect \$13 $not$libresoc.v:185882$12293_Y - connect \$15 $or$libresoc.v:185883$12294_Y - connect \$1 $not$libresoc.v:185884$12295_Y - connect \$3 $and$libresoc.v:185885$12296_Y - connect \$5 $or$libresoc.v:185886$12297_Y - connect \$7 $not$libresoc.v:185887$12298_Y + connect \$9 $and$libresoc.v:185879$12291_Y + connect \$11 $or$libresoc.v:185880$12292_Y + connect \$13 $not$libresoc.v:185881$12293_Y + connect \$15 $or$libresoc.v:185882$12294_Y + connect \$1 $not$libresoc.v:185883$12295_Y + connect \$3 $and$libresoc.v:185884$12296_Y + connect \$5 $or$libresoc.v:185885$12297_Y + connect \$7 $not$libresoc.v:185886$12298_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:185906.1-185964.10" +attribute \src "libresoc.v:185905.1-185963.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rst_l" attribute \generator "nMigen" module \rst_l$104 - attribute \src "libresoc.v:185907.7-185907.20" + attribute \src "libresoc.v:185906.7-185906.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185952.3-185960.6" + attribute \src "libresoc.v:185951.3-185959.6" wire $0\q_int$next[0:0]$12315 - attribute \src "libresoc.v:185950.3-185951.27" + attribute \src "libresoc.v:185949.3-185950.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185952.3-185960.6" + attribute \src "libresoc.v:185951.3-185959.6" wire $1\q_int$next[0:0]$12316 - attribute \src "libresoc.v:185929.7-185929.19" + attribute \src "libresoc.v:185928.7-185928.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185942.17-185942.96" - wire $and$libresoc.v:185942$12305_Y - attribute \src "libresoc.v:185947.17-185947.96" - wire $and$libresoc.v:185947$12310_Y - attribute \src "libresoc.v:185944.18-185944.93" - wire $not$libresoc.v:185944$12307_Y - attribute \src "libresoc.v:185946.17-185946.92" - wire $not$libresoc.v:185946$12309_Y - attribute \src "libresoc.v:185949.17-185949.92" - wire $not$libresoc.v:185949$12312_Y - attribute \src "libresoc.v:185943.18-185943.98" - wire $or$libresoc.v:185943$12306_Y - attribute \src "libresoc.v:185945.18-185945.99" - wire $or$libresoc.v:185945$12308_Y - attribute \src "libresoc.v:185948.17-185948.97" - wire $or$libresoc.v:185948$12311_Y + attribute \src "libresoc.v:185941.17-185941.96" + wire $and$libresoc.v:185941$12305_Y + attribute \src "libresoc.v:185946.17-185946.96" + wire $and$libresoc.v:185946$12310_Y + attribute \src "libresoc.v:185943.18-185943.93" + wire $not$libresoc.v:185943$12307_Y + attribute \src "libresoc.v:185945.17-185945.92" + wire $not$libresoc.v:185945$12309_Y + attribute \src "libresoc.v:185948.17-185948.92" + wire $not$libresoc.v:185948$12312_Y + attribute \src "libresoc.v:185942.18-185942.98" + wire $or$libresoc.v:185942$12306_Y + attribute \src "libresoc.v:185944.18-185944.99" + wire $or$libresoc.v:185944$12308_Y + attribute \src "libresoc.v:185947.17-185947.97" + wire $or$libresoc.v:185947$12311_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -385286,7 +382096,7 @@ module \rst_l$104 wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:185907.7-185907.15" + attribute \src "libresoc.v:185906.7-185906.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -385303,7 +382113,7 @@ module \rst_l$104 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185942$12305 + cell $and $and$libresoc.v:185941$12305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385311,10 +382121,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185942$12305_Y + connect \Y $and$libresoc.v:185941$12305_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185947$12310 + cell $and $and$libresoc.v:185946$12310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385322,34 +382132,34 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185947$12310_Y + connect \Y $and$libresoc.v:185946$12310_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185944$12307 + cell $not $not$libresoc.v:185943$12307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:185944$12307_Y + connect \Y $not$libresoc.v:185943$12307_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185946$12309 + cell $not $not$libresoc.v:185945$12309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:185946$12309_Y + connect \Y $not$libresoc.v:185945$12309_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185949$12312 + cell $not $not$libresoc.v:185948$12312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:185949$12312_Y + connect \Y $not$libresoc.v:185948$12312_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185943$12306 + cell $or $or$libresoc.v:185942$12306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385357,10 +382167,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:185943$12306_Y + connect \Y $or$libresoc.v:185942$12306_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185945$12308 + cell $or $or$libresoc.v:185944$12308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385368,10 +382178,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:185945$12308_Y + connect \Y $or$libresoc.v:185944$12308_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185948$12311 + cell $or $or$libresoc.v:185947$12311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385379,39 +382189,39 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:185948$12311_Y + connect \Y $or$libresoc.v:185947$12311_Y end - attribute \src "libresoc.v:185907.7-185907.20" - process $proc$libresoc.v:185907$12317 + attribute \src "libresoc.v:185906.7-185906.20" + process $proc$libresoc.v:185906$12317 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185929.7-185929.19" - process $proc$libresoc.v:185929$12318 + attribute \src "libresoc.v:185928.7-185928.19" + process $proc$libresoc.v:185928$12318 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185950.3-185951.27" - process $proc$libresoc.v:185950$12313 + attribute \src "libresoc.v:185949.3-185950.27" + process $proc$libresoc.v:185949$12313 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185952.3-185960.6" - process $proc$libresoc.v:185952$12314 + attribute \src "libresoc.v:185951.3-185959.6" + process $proc$libresoc.v:185951$12314 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12315 $1\q_int$next[0:0]$12316 - attribute \src "libresoc.v:185953.5-185953.29" + attribute \src "libresoc.v:185952.5-185952.29" switch \initial - attribute \src "libresoc.v:185953.9-185953.17" + attribute \src "libresoc.v:185952.9-185952.17" case 1'1 case end @@ -385427,49 +382237,49 @@ module \rst_l$104 sync always update \q_int$next $0\q_int$next[0:0]$12315 end - connect \$9 $and$libresoc.v:185942$12305_Y - connect \$11 $or$libresoc.v:185943$12306_Y - connect \$13 $not$libresoc.v:185944$12307_Y - connect \$15 $or$libresoc.v:185945$12308_Y - connect \$1 $not$libresoc.v:185946$12309_Y - connect \$3 $and$libresoc.v:185947$12310_Y - connect \$5 $or$libresoc.v:185948$12311_Y - connect \$7 $not$libresoc.v:185949$12312_Y + connect \$9 $and$libresoc.v:185941$12305_Y + connect \$11 $or$libresoc.v:185942$12306_Y + connect \$13 $not$libresoc.v:185943$12307_Y + connect \$15 $or$libresoc.v:185944$12308_Y + connect \$1 $not$libresoc.v:185945$12309_Y + connect \$3 $and$libresoc.v:185946$12310_Y + connect \$5 $or$libresoc.v:185947$12311_Y + connect \$7 $not$libresoc.v:185948$12312_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:185968.1-186026.10" +attribute \src "libresoc.v:185967.1-186025.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rst_l" attribute \generator "nMigen" module \rst_l$122 - attribute \src "libresoc.v:185969.7-185969.20" + attribute \src "libresoc.v:185968.7-185968.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186014.3-186022.6" + attribute \src "libresoc.v:186013.3-186021.6" wire $0\q_int$next[0:0]$12329 - attribute \src "libresoc.v:186012.3-186013.27" + attribute \src "libresoc.v:186011.3-186012.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186014.3-186022.6" + attribute \src "libresoc.v:186013.3-186021.6" wire $1\q_int$next[0:0]$12330 - attribute \src "libresoc.v:185991.7-185991.19" + attribute \src "libresoc.v:185990.7-185990.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186004.17-186004.96" - wire $and$libresoc.v:186004$12319_Y - attribute \src "libresoc.v:186009.17-186009.96" - wire $and$libresoc.v:186009$12324_Y - attribute \src "libresoc.v:186006.18-186006.93" - wire $not$libresoc.v:186006$12321_Y - attribute \src "libresoc.v:186008.17-186008.92" - wire $not$libresoc.v:186008$12323_Y - attribute \src "libresoc.v:186011.17-186011.92" - wire $not$libresoc.v:186011$12326_Y - attribute \src "libresoc.v:186005.18-186005.98" - wire $or$libresoc.v:186005$12320_Y - attribute \src "libresoc.v:186007.18-186007.99" - wire $or$libresoc.v:186007$12322_Y - attribute \src "libresoc.v:186010.17-186010.97" - wire $or$libresoc.v:186010$12325_Y + attribute \src "libresoc.v:186003.17-186003.96" + wire $and$libresoc.v:186003$12319_Y + attribute \src "libresoc.v:186008.17-186008.96" + wire $and$libresoc.v:186008$12324_Y + attribute \src "libresoc.v:186005.18-186005.93" + wire $not$libresoc.v:186005$12321_Y + attribute \src "libresoc.v:186007.17-186007.92" + wire $not$libresoc.v:186007$12323_Y + attribute \src "libresoc.v:186010.17-186010.92" + wire $not$libresoc.v:186010$12326_Y + attribute \src "libresoc.v:186004.18-186004.98" + wire $or$libresoc.v:186004$12320_Y + attribute \src "libresoc.v:186006.18-186006.99" + wire $or$libresoc.v:186006$12322_Y + attribute \src "libresoc.v:186009.17-186009.97" + wire $or$libresoc.v:186009$12325_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -385490,7 +382300,7 @@ module \rst_l$122 wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:185969.7-185969.15" + attribute \src "libresoc.v:185968.7-185968.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -385507,7 +382317,7 @@ module \rst_l$122 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186004$12319 + cell $and $and$libresoc.v:186003$12319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385515,10 +382325,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186004$12319_Y + connect \Y $and$libresoc.v:186003$12319_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186009$12324 + cell $and $and$libresoc.v:186008$12324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385526,34 +382336,34 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186009$12324_Y + connect \Y $and$libresoc.v:186008$12324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186006$12321 + cell $not $not$libresoc.v:186005$12321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186006$12321_Y + connect \Y $not$libresoc.v:186005$12321_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186008$12323 + cell $not $not$libresoc.v:186007$12323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186008$12323_Y + connect \Y $not$libresoc.v:186007$12323_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186011$12326 + cell $not $not$libresoc.v:186010$12326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186011$12326_Y + connect \Y $not$libresoc.v:186010$12326_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186005$12320 + cell $or $or$libresoc.v:186004$12320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385561,10 +382371,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186005$12320_Y + connect \Y $or$libresoc.v:186004$12320_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186007$12322 + cell $or $or$libresoc.v:186006$12322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385572,10 +382382,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186007$12322_Y + connect \Y $or$libresoc.v:186006$12322_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186010$12325 + cell $or $or$libresoc.v:186009$12325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385583,39 +382393,39 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186010$12325_Y + connect \Y $or$libresoc.v:186009$12325_Y end - attribute \src "libresoc.v:185969.7-185969.20" - process $proc$libresoc.v:185969$12331 + attribute \src "libresoc.v:185968.7-185968.20" + process $proc$libresoc.v:185968$12331 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185991.7-185991.19" - process $proc$libresoc.v:185991$12332 + attribute \src "libresoc.v:185990.7-185990.19" + process $proc$libresoc.v:185990$12332 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186012.3-186013.27" - process $proc$libresoc.v:186012$12327 + attribute \src "libresoc.v:186011.3-186012.27" + process $proc$libresoc.v:186011$12327 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186014.3-186022.6" - process $proc$libresoc.v:186014$12328 + attribute \src "libresoc.v:186013.3-186021.6" + process $proc$libresoc.v:186013$12328 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12329 $1\q_int$next[0:0]$12330 - attribute \src "libresoc.v:186015.5-186015.29" + attribute \src "libresoc.v:186014.5-186014.29" switch \initial - attribute \src "libresoc.v:186015.9-186015.17" + attribute \src "libresoc.v:186014.9-186014.17" case 1'1 case end @@ -385631,49 +382441,49 @@ module \rst_l$122 sync always update \q_int$next $0\q_int$next[0:0]$12329 end - connect \$9 $and$libresoc.v:186004$12319_Y - connect \$11 $or$libresoc.v:186005$12320_Y - connect \$13 $not$libresoc.v:186006$12321_Y - connect \$15 $or$libresoc.v:186007$12322_Y - connect \$1 $not$libresoc.v:186008$12323_Y - connect \$3 $and$libresoc.v:186009$12324_Y - connect \$5 $or$libresoc.v:186010$12325_Y - connect \$7 $not$libresoc.v:186011$12326_Y + connect \$9 $and$libresoc.v:186003$12319_Y + connect \$11 $or$libresoc.v:186004$12320_Y + connect \$13 $not$libresoc.v:186005$12321_Y + connect \$15 $or$libresoc.v:186006$12322_Y + connect \$1 $not$libresoc.v:186007$12323_Y + connect \$3 $and$libresoc.v:186008$12324_Y + connect \$5 $or$libresoc.v:186009$12325_Y + connect \$7 $not$libresoc.v:186010$12326_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186030.1-186088.10" +attribute \src "libresoc.v:186029.1-186087.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.rst_l" attribute \generator "nMigen" module \rst_l$129 - attribute \src "libresoc.v:186031.7-186031.20" + attribute \src "libresoc.v:186030.7-186030.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186076.3-186084.6" + attribute \src "libresoc.v:186075.3-186083.6" wire $0\q_int$next[0:0]$12343 - attribute \src "libresoc.v:186074.3-186075.27" + attribute \src "libresoc.v:186073.3-186074.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186076.3-186084.6" + attribute \src "libresoc.v:186075.3-186083.6" wire $1\q_int$next[0:0]$12344 - attribute \src "libresoc.v:186053.7-186053.19" + attribute \src "libresoc.v:186052.7-186052.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186066.17-186066.96" - wire $and$libresoc.v:186066$12333_Y - attribute \src "libresoc.v:186071.17-186071.96" - wire $and$libresoc.v:186071$12338_Y - attribute \src "libresoc.v:186068.18-186068.93" - wire $not$libresoc.v:186068$12335_Y - attribute \src "libresoc.v:186070.17-186070.92" - wire $not$libresoc.v:186070$12337_Y - attribute \src "libresoc.v:186073.17-186073.92" - wire $not$libresoc.v:186073$12340_Y - attribute \src "libresoc.v:186067.18-186067.98" - wire $or$libresoc.v:186067$12334_Y - attribute \src "libresoc.v:186069.18-186069.99" - wire $or$libresoc.v:186069$12336_Y - attribute \src "libresoc.v:186072.17-186072.97" - wire $or$libresoc.v:186072$12339_Y + attribute \src "libresoc.v:186065.17-186065.96" + wire $and$libresoc.v:186065$12333_Y + attribute \src "libresoc.v:186070.17-186070.96" + wire $and$libresoc.v:186070$12338_Y + attribute \src "libresoc.v:186067.18-186067.93" + wire $not$libresoc.v:186067$12335_Y + attribute \src "libresoc.v:186069.17-186069.92" + wire $not$libresoc.v:186069$12337_Y + attribute \src "libresoc.v:186072.17-186072.92" + wire $not$libresoc.v:186072$12340_Y + attribute \src "libresoc.v:186066.18-186066.98" + wire $or$libresoc.v:186066$12334_Y + attribute \src "libresoc.v:186068.18-186068.99" + wire $or$libresoc.v:186068$12336_Y + attribute \src "libresoc.v:186071.17-186071.97" + wire $or$libresoc.v:186071$12339_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -385694,7 +382504,7 @@ module \rst_l$129 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:186031.7-186031.15" + attribute \src "libresoc.v:186030.7-186030.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -385711,7 +382521,7 @@ module \rst_l$129 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186066$12333 + cell $and $and$libresoc.v:186065$12333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385719,10 +382529,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186066$12333_Y + connect \Y $and$libresoc.v:186065$12333_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186071$12338 + cell $and $and$libresoc.v:186070$12338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385730,34 +382540,34 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186071$12338_Y + connect \Y $and$libresoc.v:186070$12338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186068$12335 + cell $not $not$libresoc.v:186067$12335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186068$12335_Y + connect \Y $not$libresoc.v:186067$12335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186070$12337 + cell $not $not$libresoc.v:186069$12337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186070$12337_Y + connect \Y $not$libresoc.v:186069$12337_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186073$12340 + cell $not $not$libresoc.v:186072$12340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186073$12340_Y + connect \Y $not$libresoc.v:186072$12340_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186067$12334 + cell $or $or$libresoc.v:186066$12334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385765,10 +382575,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186067$12334_Y + connect \Y $or$libresoc.v:186066$12334_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186069$12336 + cell $or $or$libresoc.v:186068$12336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385776,10 +382586,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186069$12336_Y + connect \Y $or$libresoc.v:186068$12336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186072$12339 + cell $or $or$libresoc.v:186071$12339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385787,39 +382597,39 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186072$12339_Y + connect \Y $or$libresoc.v:186071$12339_Y end - attribute \src "libresoc.v:186031.7-186031.20" - process $proc$libresoc.v:186031$12345 + attribute \src "libresoc.v:186030.7-186030.20" + process $proc$libresoc.v:186030$12345 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186053.7-186053.19" - process $proc$libresoc.v:186053$12346 + attribute \src "libresoc.v:186052.7-186052.19" + process $proc$libresoc.v:186052$12346 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186074.3-186075.27" - process $proc$libresoc.v:186074$12341 + attribute \src "libresoc.v:186073.3-186074.27" + process $proc$libresoc.v:186073$12341 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186076.3-186084.6" - process $proc$libresoc.v:186076$12342 + attribute \src "libresoc.v:186075.3-186083.6" + process $proc$libresoc.v:186075$12342 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12343 $1\q_int$next[0:0]$12344 - attribute \src "libresoc.v:186077.5-186077.29" + attribute \src "libresoc.v:186076.5-186076.29" switch \initial - attribute \src "libresoc.v:186077.9-186077.17" + attribute \src "libresoc.v:186076.9-186076.17" case 1'1 case end @@ -385835,49 +382645,49 @@ module \rst_l$129 sync always update \q_int$next $0\q_int$next[0:0]$12343 end - connect \$9 $and$libresoc.v:186066$12333_Y - connect \$11 $or$libresoc.v:186067$12334_Y - connect \$13 $not$libresoc.v:186068$12335_Y - connect \$15 $or$libresoc.v:186069$12336_Y - connect \$1 $not$libresoc.v:186070$12337_Y - connect \$3 $and$libresoc.v:186071$12338_Y - connect \$5 $or$libresoc.v:186072$12339_Y - connect \$7 $not$libresoc.v:186073$12340_Y + connect \$9 $and$libresoc.v:186065$12333_Y + connect \$11 $or$libresoc.v:186066$12334_Y + connect \$13 $not$libresoc.v:186067$12335_Y + connect \$15 $or$libresoc.v:186068$12336_Y + connect \$1 $not$libresoc.v:186069$12337_Y + connect \$3 $and$libresoc.v:186070$12338_Y + connect \$5 $or$libresoc.v:186071$12339_Y + connect \$7 $not$libresoc.v:186072$12340_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186092.1-186150.10" +attribute \src "libresoc.v:186091.1-186149.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rst_l" attribute \generator "nMigen" module \rst_l$13 - attribute \src "libresoc.v:186093.7-186093.20" + attribute \src "libresoc.v:186092.7-186092.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186138.3-186146.6" + attribute \src "libresoc.v:186137.3-186145.6" wire $0\q_int$next[0:0]$12357 - attribute \src "libresoc.v:186136.3-186137.27" + attribute \src "libresoc.v:186135.3-186136.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186138.3-186146.6" + attribute \src "libresoc.v:186137.3-186145.6" wire $1\q_int$next[0:0]$12358 - attribute \src "libresoc.v:186115.7-186115.19" + attribute \src "libresoc.v:186114.7-186114.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186128.17-186128.96" - wire $and$libresoc.v:186128$12347_Y - attribute \src "libresoc.v:186133.17-186133.96" - wire $and$libresoc.v:186133$12352_Y - attribute \src "libresoc.v:186130.18-186130.93" - wire $not$libresoc.v:186130$12349_Y - attribute \src "libresoc.v:186132.17-186132.92" - wire $not$libresoc.v:186132$12351_Y - attribute \src "libresoc.v:186135.17-186135.92" - wire $not$libresoc.v:186135$12354_Y - attribute \src "libresoc.v:186129.18-186129.98" - wire $or$libresoc.v:186129$12348_Y - attribute \src "libresoc.v:186131.18-186131.99" - wire $or$libresoc.v:186131$12350_Y - attribute \src "libresoc.v:186134.17-186134.97" - wire $or$libresoc.v:186134$12353_Y + attribute \src "libresoc.v:186127.17-186127.96" + wire $and$libresoc.v:186127$12347_Y + attribute \src "libresoc.v:186132.17-186132.96" + wire $and$libresoc.v:186132$12352_Y + attribute \src "libresoc.v:186129.18-186129.93" + wire $not$libresoc.v:186129$12349_Y + attribute \src "libresoc.v:186131.17-186131.92" + wire $not$libresoc.v:186131$12351_Y + attribute \src "libresoc.v:186134.17-186134.92" + wire $not$libresoc.v:186134$12354_Y + attribute \src "libresoc.v:186128.18-186128.98" + wire $or$libresoc.v:186128$12348_Y + attribute \src "libresoc.v:186130.18-186130.99" + wire $or$libresoc.v:186130$12350_Y + attribute \src "libresoc.v:186133.17-186133.97" + wire $or$libresoc.v:186133$12353_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -385898,7 +382708,7 @@ module \rst_l$13 wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:186093.7-186093.15" + attribute \src "libresoc.v:186092.7-186092.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -385915,7 +382725,7 @@ module \rst_l$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186128$12347 + cell $and $and$libresoc.v:186127$12347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385923,10 +382733,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186128$12347_Y + connect \Y $and$libresoc.v:186127$12347_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186133$12352 + cell $and $and$libresoc.v:186132$12352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385934,34 +382744,34 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186133$12352_Y + connect \Y $and$libresoc.v:186132$12352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186130$12349 + cell $not $not$libresoc.v:186129$12349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186130$12349_Y + connect \Y $not$libresoc.v:186129$12349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186132$12351 + cell $not $not$libresoc.v:186131$12351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186132$12351_Y + connect \Y $not$libresoc.v:186131$12351_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186135$12354 + cell $not $not$libresoc.v:186134$12354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186135$12354_Y + connect \Y $not$libresoc.v:186134$12354_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186129$12348 + cell $or $or$libresoc.v:186128$12348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385969,10 +382779,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186129$12348_Y + connect \Y $or$libresoc.v:186128$12348_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186131$12350 + cell $or $or$libresoc.v:186130$12350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385980,10 +382790,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186131$12350_Y + connect \Y $or$libresoc.v:186130$12350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186134$12353 + cell $or $or$libresoc.v:186133$12353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385991,39 +382801,39 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186134$12353_Y + connect \Y $or$libresoc.v:186133$12353_Y end - attribute \src "libresoc.v:186093.7-186093.20" - process $proc$libresoc.v:186093$12359 + attribute \src "libresoc.v:186092.7-186092.20" + process $proc$libresoc.v:186092$12359 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186115.7-186115.19" - process $proc$libresoc.v:186115$12360 + attribute \src "libresoc.v:186114.7-186114.19" + process $proc$libresoc.v:186114$12360 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186136.3-186137.27" - process $proc$libresoc.v:186136$12355 + attribute \src "libresoc.v:186135.3-186136.27" + process $proc$libresoc.v:186135$12355 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186138.3-186146.6" - process $proc$libresoc.v:186138$12356 + attribute \src "libresoc.v:186137.3-186145.6" + process $proc$libresoc.v:186137$12356 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12357 $1\q_int$next[0:0]$12358 - attribute \src "libresoc.v:186139.5-186139.29" + attribute \src "libresoc.v:186138.5-186138.29" switch \initial - attribute \src "libresoc.v:186139.9-186139.17" + attribute \src "libresoc.v:186138.9-186138.17" case 1'1 case end @@ -386039,49 +382849,49 @@ module \rst_l$13 sync always update \q_int$next $0\q_int$next[0:0]$12357 end - connect \$9 $and$libresoc.v:186128$12347_Y - connect \$11 $or$libresoc.v:186129$12348_Y - connect \$13 $not$libresoc.v:186130$12349_Y - connect \$15 $or$libresoc.v:186131$12350_Y - connect \$1 $not$libresoc.v:186132$12351_Y - connect \$3 $and$libresoc.v:186133$12352_Y - connect \$5 $or$libresoc.v:186134$12353_Y - connect \$7 $not$libresoc.v:186135$12354_Y + connect \$9 $and$libresoc.v:186127$12347_Y + connect \$11 $or$libresoc.v:186128$12348_Y + connect \$13 $not$libresoc.v:186129$12349_Y + connect \$15 $or$libresoc.v:186130$12350_Y + connect \$1 $not$libresoc.v:186131$12351_Y + connect \$3 $and$libresoc.v:186132$12352_Y + connect \$5 $or$libresoc.v:186133$12353_Y + connect \$7 $not$libresoc.v:186134$12354_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186154.1-186212.10" +attribute \src "libresoc.v:186153.1-186211.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rst_l" attribute \generator "nMigen" module \rst_l$26 - attribute \src "libresoc.v:186155.7-186155.20" + attribute \src "libresoc.v:186154.7-186154.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186200.3-186208.6" + attribute \src "libresoc.v:186199.3-186207.6" wire $0\q_int$next[0:0]$12371 - attribute \src "libresoc.v:186198.3-186199.27" + attribute \src "libresoc.v:186197.3-186198.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186200.3-186208.6" + attribute \src "libresoc.v:186199.3-186207.6" wire $1\q_int$next[0:0]$12372 - attribute \src "libresoc.v:186177.7-186177.19" + attribute \src "libresoc.v:186176.7-186176.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186190.17-186190.96" - wire $and$libresoc.v:186190$12361_Y - attribute \src "libresoc.v:186195.17-186195.96" - wire $and$libresoc.v:186195$12366_Y - attribute \src "libresoc.v:186192.18-186192.93" - wire $not$libresoc.v:186192$12363_Y - attribute \src "libresoc.v:186194.17-186194.92" - wire $not$libresoc.v:186194$12365_Y - attribute \src "libresoc.v:186197.17-186197.92" - wire $not$libresoc.v:186197$12368_Y - attribute \src "libresoc.v:186191.18-186191.98" - wire $or$libresoc.v:186191$12362_Y - attribute \src "libresoc.v:186193.18-186193.99" - wire $or$libresoc.v:186193$12364_Y - attribute \src "libresoc.v:186196.17-186196.97" - wire $or$libresoc.v:186196$12367_Y + attribute \src "libresoc.v:186189.17-186189.96" + wire $and$libresoc.v:186189$12361_Y + attribute \src "libresoc.v:186194.17-186194.96" + wire $and$libresoc.v:186194$12366_Y + attribute \src "libresoc.v:186191.18-186191.93" + wire $not$libresoc.v:186191$12363_Y + attribute \src "libresoc.v:186193.17-186193.92" + wire $not$libresoc.v:186193$12365_Y + attribute \src "libresoc.v:186196.17-186196.92" + wire $not$libresoc.v:186196$12368_Y + attribute \src "libresoc.v:186190.18-186190.98" + wire $or$libresoc.v:186190$12362_Y + attribute \src "libresoc.v:186192.18-186192.99" + wire $or$libresoc.v:186192$12364_Y + attribute \src "libresoc.v:186195.17-186195.97" + wire $or$libresoc.v:186195$12367_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -386102,7 +382912,7 @@ module \rst_l$26 wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:186155.7-186155.15" + attribute \src "libresoc.v:186154.7-186154.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -386119,7 +382929,7 @@ module \rst_l$26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186190$12361 + cell $and $and$libresoc.v:186189$12361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386127,10 +382937,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186190$12361_Y + connect \Y $and$libresoc.v:186189$12361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186195$12366 + cell $and $and$libresoc.v:186194$12366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386138,34 +382948,34 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186195$12366_Y + connect \Y $and$libresoc.v:186194$12366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186192$12363 + cell $not $not$libresoc.v:186191$12363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186192$12363_Y + connect \Y $not$libresoc.v:186191$12363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186194$12365 + cell $not $not$libresoc.v:186193$12365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186194$12365_Y + connect \Y $not$libresoc.v:186193$12365_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186197$12368 + cell $not $not$libresoc.v:186196$12368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186197$12368_Y + connect \Y $not$libresoc.v:186196$12368_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186191$12362 + cell $or $or$libresoc.v:186190$12362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386173,10 +382983,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186191$12362_Y + connect \Y $or$libresoc.v:186190$12362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186193$12364 + cell $or $or$libresoc.v:186192$12364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386184,10 +382994,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186193$12364_Y + connect \Y $or$libresoc.v:186192$12364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186196$12367 + cell $or $or$libresoc.v:186195$12367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386195,39 +383005,39 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186196$12367_Y + connect \Y $or$libresoc.v:186195$12367_Y end - attribute \src "libresoc.v:186155.7-186155.20" - process $proc$libresoc.v:186155$12373 + attribute \src "libresoc.v:186154.7-186154.20" + process $proc$libresoc.v:186154$12373 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186177.7-186177.19" - process $proc$libresoc.v:186177$12374 + attribute \src "libresoc.v:186176.7-186176.19" + process $proc$libresoc.v:186176$12374 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186198.3-186199.27" - process $proc$libresoc.v:186198$12369 + attribute \src "libresoc.v:186197.3-186198.27" + process $proc$libresoc.v:186197$12369 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186200.3-186208.6" - process $proc$libresoc.v:186200$12370 + attribute \src "libresoc.v:186199.3-186207.6" + process $proc$libresoc.v:186199$12370 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12371 $1\q_int$next[0:0]$12372 - attribute \src "libresoc.v:186201.5-186201.29" + attribute \src "libresoc.v:186200.5-186200.29" switch \initial - attribute \src "libresoc.v:186201.9-186201.17" + attribute \src "libresoc.v:186200.9-186200.17" case 1'1 case end @@ -386243,49 +383053,49 @@ module \rst_l$26 sync always update \q_int$next $0\q_int$next[0:0]$12371 end - connect \$9 $and$libresoc.v:186190$12361_Y - connect \$11 $or$libresoc.v:186191$12362_Y - connect \$13 $not$libresoc.v:186192$12363_Y - connect \$15 $or$libresoc.v:186193$12364_Y - connect \$1 $not$libresoc.v:186194$12365_Y - connect \$3 $and$libresoc.v:186195$12366_Y - connect \$5 $or$libresoc.v:186196$12367_Y - connect \$7 $not$libresoc.v:186197$12368_Y + connect \$9 $and$libresoc.v:186189$12361_Y + connect \$11 $or$libresoc.v:186190$12362_Y + connect \$13 $not$libresoc.v:186191$12363_Y + connect \$15 $or$libresoc.v:186192$12364_Y + connect \$1 $not$libresoc.v:186193$12365_Y + connect \$3 $and$libresoc.v:186194$12366_Y + connect \$5 $or$libresoc.v:186195$12367_Y + connect \$7 $not$libresoc.v:186196$12368_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186216.1-186274.10" +attribute \src "libresoc.v:186215.1-186273.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rst_l" attribute \generator "nMigen" module \rst_l$42 - attribute \src "libresoc.v:186217.7-186217.20" + attribute \src "libresoc.v:186216.7-186216.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186262.3-186270.6" + attribute \src "libresoc.v:186261.3-186269.6" wire $0\q_int$next[0:0]$12385 - attribute \src "libresoc.v:186260.3-186261.27" + attribute \src "libresoc.v:186259.3-186260.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186262.3-186270.6" + attribute \src "libresoc.v:186261.3-186269.6" wire $1\q_int$next[0:0]$12386 - attribute \src "libresoc.v:186239.7-186239.19" + attribute \src "libresoc.v:186238.7-186238.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186252.17-186252.96" - wire $and$libresoc.v:186252$12375_Y - attribute \src "libresoc.v:186257.17-186257.96" - wire $and$libresoc.v:186257$12380_Y - attribute \src "libresoc.v:186254.18-186254.93" - wire $not$libresoc.v:186254$12377_Y - attribute \src "libresoc.v:186256.17-186256.92" - wire $not$libresoc.v:186256$12379_Y - attribute \src "libresoc.v:186259.17-186259.92" - wire $not$libresoc.v:186259$12382_Y - attribute \src "libresoc.v:186253.18-186253.98" - wire $or$libresoc.v:186253$12376_Y - attribute \src "libresoc.v:186255.18-186255.99" - wire $or$libresoc.v:186255$12378_Y - attribute \src "libresoc.v:186258.17-186258.97" - wire $or$libresoc.v:186258$12381_Y + attribute \src "libresoc.v:186251.17-186251.96" + wire $and$libresoc.v:186251$12375_Y + attribute \src "libresoc.v:186256.17-186256.96" + wire $and$libresoc.v:186256$12380_Y + attribute \src "libresoc.v:186253.18-186253.93" + wire $not$libresoc.v:186253$12377_Y + attribute \src "libresoc.v:186255.17-186255.92" + wire $not$libresoc.v:186255$12379_Y + attribute \src "libresoc.v:186258.17-186258.92" + wire $not$libresoc.v:186258$12382_Y + attribute \src "libresoc.v:186252.18-186252.98" + wire $or$libresoc.v:186252$12376_Y + attribute \src "libresoc.v:186254.18-186254.99" + wire $or$libresoc.v:186254$12378_Y + attribute \src "libresoc.v:186257.17-186257.97" + wire $or$libresoc.v:186257$12381_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -386306,7 +383116,7 @@ module \rst_l$42 wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:186217.7-186217.15" + attribute \src "libresoc.v:186216.7-186216.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -386323,7 +383133,7 @@ module \rst_l$42 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186252$12375 + cell $and $and$libresoc.v:186251$12375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386331,10 +383141,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186252$12375_Y + connect \Y $and$libresoc.v:186251$12375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186257$12380 + cell $and $and$libresoc.v:186256$12380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386342,34 +383152,34 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186257$12380_Y + connect \Y $and$libresoc.v:186256$12380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186254$12377 + cell $not $not$libresoc.v:186253$12377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186254$12377_Y + connect \Y $not$libresoc.v:186253$12377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186256$12379 + cell $not $not$libresoc.v:186255$12379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186256$12379_Y + connect \Y $not$libresoc.v:186255$12379_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186259$12382 + cell $not $not$libresoc.v:186258$12382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186259$12382_Y + connect \Y $not$libresoc.v:186258$12382_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186253$12376 + cell $or $or$libresoc.v:186252$12376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386377,10 +383187,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186253$12376_Y + connect \Y $or$libresoc.v:186252$12376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186255$12378 + cell $or $or$libresoc.v:186254$12378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386388,10 +383198,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186255$12378_Y + connect \Y $or$libresoc.v:186254$12378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186258$12381 + cell $or $or$libresoc.v:186257$12381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386399,39 +383209,39 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186258$12381_Y + connect \Y $or$libresoc.v:186257$12381_Y end - attribute \src "libresoc.v:186217.7-186217.20" - process $proc$libresoc.v:186217$12387 + attribute \src "libresoc.v:186216.7-186216.20" + process $proc$libresoc.v:186216$12387 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186239.7-186239.19" - process $proc$libresoc.v:186239$12388 + attribute \src "libresoc.v:186238.7-186238.19" + process $proc$libresoc.v:186238$12388 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186260.3-186261.27" - process $proc$libresoc.v:186260$12383 + attribute \src "libresoc.v:186259.3-186260.27" + process $proc$libresoc.v:186259$12383 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186262.3-186270.6" - process $proc$libresoc.v:186262$12384 + attribute \src "libresoc.v:186261.3-186269.6" + process $proc$libresoc.v:186261$12384 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12385 $1\q_int$next[0:0]$12386 - attribute \src "libresoc.v:186263.5-186263.29" + attribute \src "libresoc.v:186262.5-186262.29" switch \initial - attribute \src "libresoc.v:186263.9-186263.17" + attribute \src "libresoc.v:186262.9-186262.17" case 1'1 case end @@ -386447,49 +383257,49 @@ module \rst_l$42 sync always update \q_int$next $0\q_int$next[0:0]$12385 end - connect \$9 $and$libresoc.v:186252$12375_Y - connect \$11 $or$libresoc.v:186253$12376_Y - connect \$13 $not$libresoc.v:186254$12377_Y - connect \$15 $or$libresoc.v:186255$12378_Y - connect \$1 $not$libresoc.v:186256$12379_Y - connect \$3 $and$libresoc.v:186257$12380_Y - connect \$5 $or$libresoc.v:186258$12381_Y - connect \$7 $not$libresoc.v:186259$12382_Y + connect \$9 $and$libresoc.v:186251$12375_Y + connect \$11 $or$libresoc.v:186252$12376_Y + connect \$13 $not$libresoc.v:186253$12377_Y + connect \$15 $or$libresoc.v:186254$12378_Y + connect \$1 $not$libresoc.v:186255$12379_Y + connect \$3 $and$libresoc.v:186256$12380_Y + connect \$5 $or$libresoc.v:186257$12381_Y + connect \$7 $not$libresoc.v:186258$12382_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186278.1-186336.10" +attribute \src "libresoc.v:186277.1-186335.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rst_l" attribute \generator "nMigen" module \rst_l$58 - attribute \src "libresoc.v:186279.7-186279.20" + attribute \src "libresoc.v:186278.7-186278.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186324.3-186332.6" + attribute \src "libresoc.v:186323.3-186331.6" wire $0\q_int$next[0:0]$12399 - attribute \src "libresoc.v:186322.3-186323.27" + attribute \src "libresoc.v:186321.3-186322.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186324.3-186332.6" + attribute \src "libresoc.v:186323.3-186331.6" wire $1\q_int$next[0:0]$12400 - attribute \src "libresoc.v:186301.7-186301.19" + attribute \src "libresoc.v:186300.7-186300.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186314.17-186314.96" - wire $and$libresoc.v:186314$12389_Y - attribute \src "libresoc.v:186319.17-186319.96" - wire $and$libresoc.v:186319$12394_Y - attribute \src "libresoc.v:186316.18-186316.93" - wire $not$libresoc.v:186316$12391_Y - attribute \src "libresoc.v:186318.17-186318.92" - wire $not$libresoc.v:186318$12393_Y - attribute \src "libresoc.v:186321.17-186321.92" - wire $not$libresoc.v:186321$12396_Y - attribute \src "libresoc.v:186315.18-186315.98" - wire $or$libresoc.v:186315$12390_Y - attribute \src "libresoc.v:186317.18-186317.99" - wire $or$libresoc.v:186317$12392_Y - attribute \src "libresoc.v:186320.17-186320.97" - wire $or$libresoc.v:186320$12395_Y + attribute \src "libresoc.v:186313.17-186313.96" + wire $and$libresoc.v:186313$12389_Y + attribute \src "libresoc.v:186318.17-186318.96" + wire $and$libresoc.v:186318$12394_Y + attribute \src "libresoc.v:186315.18-186315.93" + wire $not$libresoc.v:186315$12391_Y + attribute \src "libresoc.v:186317.17-186317.92" + wire $not$libresoc.v:186317$12393_Y + attribute \src "libresoc.v:186320.17-186320.92" + wire $not$libresoc.v:186320$12396_Y + attribute \src "libresoc.v:186314.18-186314.98" + wire $or$libresoc.v:186314$12390_Y + attribute \src "libresoc.v:186316.18-186316.99" + wire $or$libresoc.v:186316$12392_Y + attribute \src "libresoc.v:186319.17-186319.97" + wire $or$libresoc.v:186319$12395_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -386510,7 +383320,7 @@ module \rst_l$58 wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:186279.7-186279.15" + attribute \src "libresoc.v:186278.7-186278.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -386527,7 +383337,7 @@ module \rst_l$58 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186314$12389 + cell $and $and$libresoc.v:186313$12389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386535,10 +383345,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186314$12389_Y + connect \Y $and$libresoc.v:186313$12389_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186319$12394 + cell $and $and$libresoc.v:186318$12394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386546,34 +383356,34 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186319$12394_Y + connect \Y $and$libresoc.v:186318$12394_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186316$12391 + cell $not $not$libresoc.v:186315$12391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186316$12391_Y + connect \Y $not$libresoc.v:186315$12391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186318$12393 + cell $not $not$libresoc.v:186317$12393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186318$12393_Y + connect \Y $not$libresoc.v:186317$12393_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186321$12396 + cell $not $not$libresoc.v:186320$12396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186321$12396_Y + connect \Y $not$libresoc.v:186320$12396_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186315$12390 + cell $or $or$libresoc.v:186314$12390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386581,10 +383391,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186315$12390_Y + connect \Y $or$libresoc.v:186314$12390_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186317$12392 + cell $or $or$libresoc.v:186316$12392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386592,10 +383402,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186317$12392_Y + connect \Y $or$libresoc.v:186316$12392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186320$12395 + cell $or $or$libresoc.v:186319$12395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386603,39 +383413,39 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186320$12395_Y + connect \Y $or$libresoc.v:186319$12395_Y end - attribute \src "libresoc.v:186279.7-186279.20" - process $proc$libresoc.v:186279$12401 + attribute \src "libresoc.v:186278.7-186278.20" + process $proc$libresoc.v:186278$12401 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186301.7-186301.19" - process $proc$libresoc.v:186301$12402 + attribute \src "libresoc.v:186300.7-186300.19" + process $proc$libresoc.v:186300$12402 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186322.3-186323.27" - process $proc$libresoc.v:186322$12397 + attribute \src "libresoc.v:186321.3-186322.27" + process $proc$libresoc.v:186321$12397 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186324.3-186332.6" - process $proc$libresoc.v:186324$12398 + attribute \src "libresoc.v:186323.3-186331.6" + process $proc$libresoc.v:186323$12398 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12399 $1\q_int$next[0:0]$12400 - attribute \src "libresoc.v:186325.5-186325.29" + attribute \src "libresoc.v:186324.5-186324.29" switch \initial - attribute \src "libresoc.v:186325.9-186325.17" + attribute \src "libresoc.v:186324.9-186324.17" case 1'1 case end @@ -386651,49 +383461,49 @@ module \rst_l$58 sync always update \q_int$next $0\q_int$next[0:0]$12399 end - connect \$9 $and$libresoc.v:186314$12389_Y - connect \$11 $or$libresoc.v:186315$12390_Y - connect \$13 $not$libresoc.v:186316$12391_Y - connect \$15 $or$libresoc.v:186317$12392_Y - connect \$1 $not$libresoc.v:186318$12393_Y - connect \$3 $and$libresoc.v:186319$12394_Y - connect \$5 $or$libresoc.v:186320$12395_Y - connect \$7 $not$libresoc.v:186321$12396_Y + connect \$9 $and$libresoc.v:186313$12389_Y + connect \$11 $or$libresoc.v:186314$12390_Y + connect \$13 $not$libresoc.v:186315$12391_Y + connect \$15 $or$libresoc.v:186316$12392_Y + connect \$1 $not$libresoc.v:186317$12393_Y + connect \$3 $and$libresoc.v:186318$12394_Y + connect \$5 $or$libresoc.v:186319$12395_Y + connect \$7 $not$libresoc.v:186320$12396_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186340.1-186398.10" +attribute \src "libresoc.v:186339.1-186397.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rst_l" attribute \generator "nMigen" module \rst_l$70 - attribute \src "libresoc.v:186341.7-186341.20" + attribute \src "libresoc.v:186340.7-186340.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186386.3-186394.6" + attribute \src "libresoc.v:186385.3-186393.6" wire $0\q_int$next[0:0]$12413 - attribute \src "libresoc.v:186384.3-186385.27" + attribute \src "libresoc.v:186383.3-186384.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186386.3-186394.6" + attribute \src "libresoc.v:186385.3-186393.6" wire $1\q_int$next[0:0]$12414 - attribute \src "libresoc.v:186363.7-186363.19" + attribute \src "libresoc.v:186362.7-186362.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186376.17-186376.96" - wire $and$libresoc.v:186376$12403_Y - attribute \src "libresoc.v:186381.17-186381.96" - wire $and$libresoc.v:186381$12408_Y - attribute \src "libresoc.v:186378.18-186378.93" - wire $not$libresoc.v:186378$12405_Y - attribute \src "libresoc.v:186380.17-186380.92" - wire $not$libresoc.v:186380$12407_Y - attribute \src "libresoc.v:186383.17-186383.92" - wire $not$libresoc.v:186383$12410_Y - attribute \src "libresoc.v:186377.18-186377.98" - wire $or$libresoc.v:186377$12404_Y - attribute \src "libresoc.v:186379.18-186379.99" - wire $or$libresoc.v:186379$12406_Y - attribute \src "libresoc.v:186382.17-186382.97" - wire $or$libresoc.v:186382$12409_Y + attribute \src "libresoc.v:186375.17-186375.96" + wire $and$libresoc.v:186375$12403_Y + attribute \src "libresoc.v:186380.17-186380.96" + wire $and$libresoc.v:186380$12408_Y + attribute \src "libresoc.v:186377.18-186377.93" + wire $not$libresoc.v:186377$12405_Y + attribute \src "libresoc.v:186379.17-186379.92" + wire $not$libresoc.v:186379$12407_Y + attribute \src "libresoc.v:186382.17-186382.92" + wire $not$libresoc.v:186382$12410_Y + attribute \src "libresoc.v:186376.18-186376.98" + wire $or$libresoc.v:186376$12404_Y + attribute \src "libresoc.v:186378.18-186378.99" + wire $or$libresoc.v:186378$12406_Y + attribute \src "libresoc.v:186381.17-186381.97" + wire $or$libresoc.v:186381$12409_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -386714,7 +383524,7 @@ module \rst_l$70 wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:186341.7-186341.15" + attribute \src "libresoc.v:186340.7-186340.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -386731,7 +383541,7 @@ module \rst_l$70 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186376$12403 + cell $and $and$libresoc.v:186375$12403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386739,10 +383549,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186376$12403_Y + connect \Y $and$libresoc.v:186375$12403_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186381$12408 + cell $and $and$libresoc.v:186380$12408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386750,34 +383560,34 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186381$12408_Y + connect \Y $and$libresoc.v:186380$12408_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186378$12405 + cell $not $not$libresoc.v:186377$12405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186378$12405_Y + connect \Y $not$libresoc.v:186377$12405_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186380$12407 + cell $not $not$libresoc.v:186379$12407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186380$12407_Y + connect \Y $not$libresoc.v:186379$12407_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186383$12410 + cell $not $not$libresoc.v:186382$12410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186383$12410_Y + connect \Y $not$libresoc.v:186382$12410_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186377$12404 + cell $or $or$libresoc.v:186376$12404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386785,10 +383595,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186377$12404_Y + connect \Y $or$libresoc.v:186376$12404_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186379$12406 + cell $or $or$libresoc.v:186378$12406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386796,10 +383606,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186379$12406_Y + connect \Y $or$libresoc.v:186378$12406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186382$12409 + cell $or $or$libresoc.v:186381$12409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386807,39 +383617,39 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186382$12409_Y + connect \Y $or$libresoc.v:186381$12409_Y end - attribute \src "libresoc.v:186341.7-186341.20" - process $proc$libresoc.v:186341$12415 + attribute \src "libresoc.v:186340.7-186340.20" + process $proc$libresoc.v:186340$12415 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186363.7-186363.19" - process $proc$libresoc.v:186363$12416 + attribute \src "libresoc.v:186362.7-186362.19" + process $proc$libresoc.v:186362$12416 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186384.3-186385.27" - process $proc$libresoc.v:186384$12411 + attribute \src "libresoc.v:186383.3-186384.27" + process $proc$libresoc.v:186383$12411 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186386.3-186394.6" - process $proc$libresoc.v:186386$12412 + attribute \src "libresoc.v:186385.3-186393.6" + process $proc$libresoc.v:186385$12412 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12413 $1\q_int$next[0:0]$12414 - attribute \src "libresoc.v:186387.5-186387.29" + attribute \src "libresoc.v:186386.5-186386.29" switch \initial - attribute \src "libresoc.v:186387.9-186387.17" + attribute \src "libresoc.v:186386.9-186386.17" case 1'1 case end @@ -386855,49 +383665,49 @@ module \rst_l$70 sync always update \q_int$next $0\q_int$next[0:0]$12413 end - connect \$9 $and$libresoc.v:186376$12403_Y - connect \$11 $or$libresoc.v:186377$12404_Y - connect \$13 $not$libresoc.v:186378$12405_Y - connect \$15 $or$libresoc.v:186379$12406_Y - connect \$1 $not$libresoc.v:186380$12407_Y - connect \$3 $and$libresoc.v:186381$12408_Y - connect \$5 $or$libresoc.v:186382$12409_Y - connect \$7 $not$libresoc.v:186383$12410_Y + connect \$9 $and$libresoc.v:186375$12403_Y + connect \$11 $or$libresoc.v:186376$12404_Y + connect \$13 $not$libresoc.v:186377$12405_Y + connect \$15 $or$libresoc.v:186378$12406_Y + connect \$1 $not$libresoc.v:186379$12407_Y + connect \$3 $and$libresoc.v:186380$12408_Y + connect \$5 $or$libresoc.v:186381$12409_Y + connect \$7 $not$libresoc.v:186382$12410_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186402.1-186460.10" +attribute \src "libresoc.v:186401.1-186459.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rst_l" attribute \generator "nMigen" module \rst_l$87 - attribute \src "libresoc.v:186403.7-186403.20" + attribute \src "libresoc.v:186402.7-186402.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186448.3-186456.6" + attribute \src "libresoc.v:186447.3-186455.6" wire $0\q_int$next[0:0]$12427 - attribute \src "libresoc.v:186446.3-186447.27" + attribute \src "libresoc.v:186445.3-186446.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186448.3-186456.6" + attribute \src "libresoc.v:186447.3-186455.6" wire $1\q_int$next[0:0]$12428 - attribute \src "libresoc.v:186425.7-186425.19" + attribute \src "libresoc.v:186424.7-186424.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186438.17-186438.96" - wire $and$libresoc.v:186438$12417_Y - attribute \src "libresoc.v:186443.17-186443.96" - wire $and$libresoc.v:186443$12422_Y - attribute \src "libresoc.v:186440.18-186440.93" - wire $not$libresoc.v:186440$12419_Y - attribute \src "libresoc.v:186442.17-186442.92" - wire $not$libresoc.v:186442$12421_Y - attribute \src "libresoc.v:186445.17-186445.92" - wire $not$libresoc.v:186445$12424_Y - attribute \src "libresoc.v:186439.18-186439.98" - wire $or$libresoc.v:186439$12418_Y - attribute \src "libresoc.v:186441.18-186441.99" - wire $or$libresoc.v:186441$12420_Y - attribute \src "libresoc.v:186444.17-186444.97" - wire $or$libresoc.v:186444$12423_Y + attribute \src "libresoc.v:186437.17-186437.96" + wire $and$libresoc.v:186437$12417_Y + attribute \src "libresoc.v:186442.17-186442.96" + wire $and$libresoc.v:186442$12422_Y + attribute \src "libresoc.v:186439.18-186439.93" + wire $not$libresoc.v:186439$12419_Y + attribute \src "libresoc.v:186441.17-186441.92" + wire $not$libresoc.v:186441$12421_Y + attribute \src "libresoc.v:186444.17-186444.92" + wire $not$libresoc.v:186444$12424_Y + attribute \src "libresoc.v:186438.18-186438.98" + wire $or$libresoc.v:186438$12418_Y + attribute \src "libresoc.v:186440.18-186440.99" + wire $or$libresoc.v:186440$12420_Y + attribute \src "libresoc.v:186443.17-186443.97" + wire $or$libresoc.v:186443$12423_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -386918,7 +383728,7 @@ module \rst_l$87 wire input 4 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:186403.7-186403.15" + attribute \src "libresoc.v:186402.7-186402.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -386935,7 +383745,7 @@ module \rst_l$87 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186438$12417 + cell $and $and$libresoc.v:186437$12417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386943,10 +383753,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186438$12417_Y + connect \Y $and$libresoc.v:186437$12417_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186443$12422 + cell $and $and$libresoc.v:186442$12422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386954,34 +383764,34 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186443$12422_Y + connect \Y $and$libresoc.v:186442$12422_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186440$12419 + cell $not $not$libresoc.v:186439$12419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186440$12419_Y + connect \Y $not$libresoc.v:186439$12419_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186442$12421 + cell $not $not$libresoc.v:186441$12421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186442$12421_Y + connect \Y $not$libresoc.v:186441$12421_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186445$12424 + cell $not $not$libresoc.v:186444$12424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186445$12424_Y + connect \Y $not$libresoc.v:186444$12424_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186439$12418 + cell $or $or$libresoc.v:186438$12418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386989,10 +383799,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186439$12418_Y + connect \Y $or$libresoc.v:186438$12418_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186441$12420 + cell $or $or$libresoc.v:186440$12420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387000,10 +383810,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186441$12420_Y + connect \Y $or$libresoc.v:186440$12420_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186444$12423 + cell $or $or$libresoc.v:186443$12423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387011,39 +383821,39 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186444$12423_Y + connect \Y $or$libresoc.v:186443$12423_Y end - attribute \src "libresoc.v:186403.7-186403.20" - process $proc$libresoc.v:186403$12429 + attribute \src "libresoc.v:186402.7-186402.20" + process $proc$libresoc.v:186402$12429 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186425.7-186425.19" - process $proc$libresoc.v:186425$12430 + attribute \src "libresoc.v:186424.7-186424.19" + process $proc$libresoc.v:186424$12430 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186446.3-186447.27" - process $proc$libresoc.v:186446$12425 + attribute \src "libresoc.v:186445.3-186446.27" + process $proc$libresoc.v:186445$12425 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186448.3-186456.6" - process $proc$libresoc.v:186448$12426 + attribute \src "libresoc.v:186447.3-186455.6" + process $proc$libresoc.v:186447$12426 assign { } { } assign { } { } assign $0\q_int$next[0:0]$12427 $1\q_int$next[0:0]$12428 - attribute \src "libresoc.v:186449.5-186449.29" + attribute \src "libresoc.v:186448.5-186448.29" switch \initial - attribute \src "libresoc.v:186449.9-186449.17" + attribute \src "libresoc.v:186448.9-186448.17" case 1'1 case end @@ -387059,85 +383869,85 @@ module \rst_l$87 sync always update \q_int$next $0\q_int$next[0:0]$12427 end - connect \$9 $and$libresoc.v:186438$12417_Y - connect \$11 $or$libresoc.v:186439$12418_Y - connect \$13 $not$libresoc.v:186440$12419_Y - connect \$15 $or$libresoc.v:186441$12420_Y - connect \$1 $not$libresoc.v:186442$12421_Y - connect \$3 $and$libresoc.v:186443$12422_Y - connect \$5 $or$libresoc.v:186444$12423_Y - connect \$7 $not$libresoc.v:186445$12424_Y + connect \$9 $and$libresoc.v:186437$12417_Y + connect \$11 $or$libresoc.v:186438$12418_Y + connect \$13 $not$libresoc.v:186439$12419_Y + connect \$15 $or$libresoc.v:186440$12420_Y + connect \$1 $not$libresoc.v:186441$12421_Y + connect \$3 $and$libresoc.v:186442$12422_Y + connect \$5 $or$libresoc.v:186443$12423_Y + connect \$7 $not$libresoc.v:186444$12424_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186464.1-186873.10" +attribute \src "libresoc.v:186463.1-186872.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage" attribute \generator "nMigen" module \setup_stage - attribute \src "libresoc.v:186831.3-186856.6" + attribute \src "libresoc.v:186830.3-186855.6" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:186465.7-186465.20" + attribute \src "libresoc.v:186464.7-186464.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186831.3-186856.6" + attribute \src "libresoc.v:186830.3-186855.6" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:186831.3-186856.6" + attribute \src "libresoc.v:186830.3-186855.6" wire width 128 $2\dividend[127:0] - attribute \src "libresoc.v:186810.18-186810.122" - wire $and$libresoc.v:186810$12432_Y - attribute \src "libresoc.v:186812.18-186812.122" - wire $and$libresoc.v:186812$12434_Y - attribute \src "libresoc.v:186821.18-186821.105" - wire $and$libresoc.v:186821$12447_Y - attribute \src "libresoc.v:186824.18-186824.105" - wire $and$libresoc.v:186824$12450_Y - attribute \src "libresoc.v:186820.18-186820.123" - wire $eq$libresoc.v:186820$12446_Y - attribute \src "libresoc.v:186823.18-186823.123" - wire $eq$libresoc.v:186823$12449_Y - attribute \src "libresoc.v:186826.18-186826.117" - wire $eq$libresoc.v:186826$12452_Y - attribute \src "libresoc.v:186813.18-186813.97" - wire width 65 $extend$libresoc.v:186813$12435_Y - attribute \src "libresoc.v:186814.18-186814.91" - wire width 65 $extend$libresoc.v:186814$12437_Y - attribute \src "libresoc.v:186816.18-186816.97" - wire width 65 $extend$libresoc.v:186816$12440_Y - attribute \src "libresoc.v:186817.18-186817.91" - wire width 65 $extend$libresoc.v:186817$12442_Y - attribute \src "libresoc.v:186829.18-186829.99" - wire width 128 $extend$libresoc.v:186829$12455_Y - attribute \src "libresoc.v:186819.18-186819.112" - wire $ge$libresoc.v:186819$12445_Y - attribute \src "libresoc.v:186822.18-186822.124" - wire $ge$libresoc.v:186822$12448_Y - attribute \src "libresoc.v:186813.18-186813.97" - wire width 65 $neg$libresoc.v:186813$12436_Y - attribute \src "libresoc.v:186816.18-186816.97" - wire width 65 $neg$libresoc.v:186816$12441_Y - attribute \src "libresoc.v:186814.18-186814.91" - wire width 65 $pos$libresoc.v:186814$12438_Y - attribute \src "libresoc.v:186817.18-186817.91" - wire width 65 $pos$libresoc.v:186817$12443_Y - attribute \src "libresoc.v:186829.18-186829.99" - wire width 128 $pos$libresoc.v:186829$12456_Y - attribute \src "libresoc.v:186828.18-186828.117" - wire width 95 $sshl$libresoc.v:186828$12454_Y - attribute \src "libresoc.v:186830.18-186830.111" - wire width 191 $sshl$libresoc.v:186830$12457_Y - attribute \src "libresoc.v:186809.18-186809.131" - wire $ternary$libresoc.v:186809$12431_Y - attribute \src "libresoc.v:186811.18-186811.131" - wire $ternary$libresoc.v:186811$12433_Y - attribute \src "libresoc.v:186815.18-186815.119" - wire width 65 $ternary$libresoc.v:186815$12439_Y - attribute \src "libresoc.v:186818.18-186818.120" - wire width 65 $ternary$libresoc.v:186818$12444_Y - attribute \src "libresoc.v:186825.18-186825.130" - wire width 32 $ternary$libresoc.v:186825$12451_Y - attribute \src "libresoc.v:186827.18-186827.131" - wire width 32 $ternary$libresoc.v:186827$12453_Y + attribute \src "libresoc.v:186809.18-186809.122" + wire $and$libresoc.v:186809$12432_Y + attribute \src "libresoc.v:186811.18-186811.122" + wire $and$libresoc.v:186811$12434_Y + attribute \src "libresoc.v:186820.18-186820.105" + wire $and$libresoc.v:186820$12447_Y + attribute \src "libresoc.v:186823.18-186823.105" + wire $and$libresoc.v:186823$12450_Y + attribute \src "libresoc.v:186819.18-186819.123" + wire $eq$libresoc.v:186819$12446_Y + attribute \src "libresoc.v:186822.18-186822.123" + wire $eq$libresoc.v:186822$12449_Y + attribute \src "libresoc.v:186825.18-186825.117" + wire $eq$libresoc.v:186825$12452_Y + attribute \src "libresoc.v:186812.18-186812.97" + wire width 65 $extend$libresoc.v:186812$12435_Y + attribute \src "libresoc.v:186813.18-186813.91" + wire width 65 $extend$libresoc.v:186813$12437_Y + attribute \src "libresoc.v:186815.18-186815.97" + wire width 65 $extend$libresoc.v:186815$12440_Y + attribute \src "libresoc.v:186816.18-186816.91" + wire width 65 $extend$libresoc.v:186816$12442_Y + attribute \src "libresoc.v:186828.18-186828.99" + wire width 128 $extend$libresoc.v:186828$12455_Y + attribute \src "libresoc.v:186818.18-186818.112" + wire $ge$libresoc.v:186818$12445_Y + attribute \src "libresoc.v:186821.18-186821.124" + wire $ge$libresoc.v:186821$12448_Y + attribute \src "libresoc.v:186812.18-186812.97" + wire width 65 $neg$libresoc.v:186812$12436_Y + attribute \src "libresoc.v:186815.18-186815.97" + wire width 65 $neg$libresoc.v:186815$12441_Y + attribute \src "libresoc.v:186813.18-186813.91" + wire width 65 $pos$libresoc.v:186813$12438_Y + attribute \src "libresoc.v:186816.18-186816.91" + wire width 65 $pos$libresoc.v:186816$12443_Y + attribute \src "libresoc.v:186828.18-186828.99" + wire width 128 $pos$libresoc.v:186828$12456_Y + attribute \src "libresoc.v:186827.18-186827.117" + wire width 95 $sshl$libresoc.v:186827$12454_Y + attribute \src "libresoc.v:186829.18-186829.111" + wire width 191 $sshl$libresoc.v:186829$12457_Y + attribute \src "libresoc.v:186808.18-186808.131" + wire $ternary$libresoc.v:186808$12431_Y + attribute \src "libresoc.v:186810.18-186810.131" + wire $ternary$libresoc.v:186810$12433_Y + attribute \src "libresoc.v:186814.18-186814.119" + wire width 65 $ternary$libresoc.v:186814$12439_Y + attribute \src "libresoc.v:186817.18-186817.120" + wire width 65 $ternary$libresoc.v:186817$12444_Y + attribute \src "libresoc.v:186824.18-186824.130" + wire width 32 $ternary$libresoc.v:186824$12451_Y + attribute \src "libresoc.v:186826.18-186826.131" + wire width 32 $ternary$libresoc.v:186826$12453_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" @@ -387206,7 +384016,7 @@ module \setup_stage wire output 42 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 output 48 \divisor_radicand - attribute \src "libresoc.v:186465.7-186465.15" + attribute \src "libresoc.v:186464.7-186464.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -387483,7 +384293,7 @@ module \setup_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 41 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $and $and$libresoc.v:186810$12432 + cell $and $and$libresoc.v:186809$12432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387491,10 +384301,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$21 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:186810$12432_Y + connect \Y $and$libresoc.v:186809$12432_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $and $and$libresoc.v:186812$12434 + cell $and $and$libresoc.v:186811$12434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387502,10 +384312,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$25 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:186812$12434_Y + connect \Y $and$libresoc.v:186811$12434_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $and $and$libresoc.v:186821$12447 + cell $and $and$libresoc.v:186820$12447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387513,10 +384323,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$43 connect \B \$45 - connect \Y $and$libresoc.v:186821$12447_Y + connect \Y $and$libresoc.v:186820$12447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $and $and$libresoc.v:186824$12450 + cell $and $and$libresoc.v:186823$12450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -387524,10 +384334,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$49 connect \B \$51 - connect \Y $and$libresoc.v:186824$12450_Y + connect \Y $and$libresoc.v:186823$12450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $eq $eq$libresoc.v:186820$12446 + cell $eq $eq$libresoc.v:186819$12446 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387535,10 +384345,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:186820$12446_Y + connect \Y $eq$libresoc.v:186819$12446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $eq $eq$libresoc.v:186823$12449 + cell $eq $eq$libresoc.v:186822$12449 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -387546,10 +384356,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:186823$12449_Y + connect \Y $eq$libresoc.v:186822$12449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - cell $eq $eq$libresoc.v:186826$12452 + cell $eq $eq$libresoc.v:186825$12452 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -387557,50 +384367,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \divisor_radicand connect \B 1'0 - connect \Y $eq$libresoc.v:186826$12452_Y + connect \Y $eq$libresoc.v:186825$12452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $pos $extend$libresoc.v:186813$12435 + cell $pos $extend$libresoc.v:186812$12435 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:186813$12435_Y + connect \Y $extend$libresoc.v:186812$12435_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:186814$12437 + cell $pos $extend$libresoc.v:186813$12437 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:186814$12437_Y + connect \Y $extend$libresoc.v:186813$12437_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $pos $extend$libresoc.v:186816$12440 + cell $pos $extend$libresoc.v:186815$12440 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:186816$12440_Y + connect \Y $extend$libresoc.v:186815$12440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:186817$12442 + cell $pos $extend$libresoc.v:186816$12442 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:186817$12442_Y + connect \Y $extend$libresoc.v:186816$12442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $extend$libresoc.v:186829$12455 + cell $pos $extend$libresoc.v:186828$12455 parameter \A_SIGNED 0 parameter \A_WIDTH 95 parameter \Y_WIDTH 128 connect \A \$62 - connect \Y $extend$libresoc.v:186829$12455_Y + connect \Y $extend$libresoc.v:186828$12455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - cell $ge $ge$libresoc.v:186819$12445 + cell $ge $ge$libresoc.v:186818$12445 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -387608,10 +384418,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend connect \B \abs_dor - connect \Y $ge$libresoc.v:186819$12445_Y + connect \Y $ge$libresoc.v:186818$12445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - cell $ge $ge$libresoc.v:186822$12448 + cell $ge $ge$libresoc.v:186821$12448 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -387619,50 +384429,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend [31:0] connect \B \abs_dor [31:0] - connect \Y $ge$libresoc.v:186822$12448_Y + connect \Y $ge$libresoc.v:186821$12448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $neg $neg$libresoc.v:186813$12436 + cell $neg $neg$libresoc.v:186812$12436 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:186813$12435_Y - connect \Y $neg$libresoc.v:186813$12436_Y + connect \A $extend$libresoc.v:186812$12435_Y + connect \Y $neg$libresoc.v:186812$12436_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $neg $neg$libresoc.v:186816$12441 + cell $neg $neg$libresoc.v:186815$12441 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:186816$12440_Y - connect \Y $neg$libresoc.v:186816$12441_Y + connect \A $extend$libresoc.v:186815$12440_Y + connect \Y $neg$libresoc.v:186815$12441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:186814$12438 + cell $pos $pos$libresoc.v:186813$12438 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:186814$12437_Y - connect \Y $pos$libresoc.v:186814$12438_Y + connect \A $extend$libresoc.v:186813$12437_Y + connect \Y $pos$libresoc.v:186813$12438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:186817$12443 + cell $pos $pos$libresoc.v:186816$12443 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:186817$12442_Y - connect \Y $pos$libresoc.v:186817$12443_Y + connect \A $extend$libresoc.v:186816$12442_Y + connect \Y $pos$libresoc.v:186816$12443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $pos$libresoc.v:186829$12456 + cell $pos $pos$libresoc.v:186828$12456 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 128 - connect \A $extend$libresoc.v:186829$12455_Y - connect \Y $pos$libresoc.v:186829$12456_Y + connect \A $extend$libresoc.v:186828$12455_Y + connect \Y $pos$libresoc.v:186828$12456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $sshl $sshl$libresoc.v:186828$12454 + cell $sshl $sshl$libresoc.v:186827$12454 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -387670,10 +384480,10 @@ module \setup_stage parameter \Y_WIDTH 95 connect \A \abs_dend [31:0] connect \B 6'100000 - connect \Y $sshl$libresoc.v:186828$12454_Y + connect \Y $sshl$libresoc.v:186827$12454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - cell $sshl $sshl$libresoc.v:186830$12457 + cell $sshl $sshl$libresoc.v:186829$12457 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -387681,72 +384491,72 @@ module \setup_stage parameter \Y_WIDTH 191 connect \A \abs_dend connect \B 7'1000000 - connect \Y $sshl$libresoc.v:186830$12457_Y + connect \Y $sshl$libresoc.v:186829$12457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $mux $ternary$libresoc.v:186809$12431 + cell $mux $ternary$libresoc.v:186808$12431 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:186809$12431_Y + connect \Y $ternary$libresoc.v:186808$12431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $mux $ternary$libresoc.v:186811$12433 + cell $mux $ternary$libresoc.v:186810$12433 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:186811$12433_Y + connect \Y $ternary$libresoc.v:186810$12433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $mux $ternary$libresoc.v:186815$12439 + cell $mux $ternary$libresoc.v:186814$12439 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \divisor_neg - connect \Y $ternary$libresoc.v:186815$12439_Y + connect \Y $ternary$libresoc.v:186814$12439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $mux $ternary$libresoc.v:186818$12444 + cell $mux $ternary$libresoc.v:186817$12444 parameter \WIDTH 65 connect \A \$39 connect \B \$37 connect \S \dividend_neg - connect \Y $ternary$libresoc.v:186818$12444_Y + connect \Y $ternary$libresoc.v:186817$12444_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:186825$12451 + cell $mux $ternary$libresoc.v:186824$12451 parameter \WIDTH 32 connect \A \abs_dor [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:186825$12451_Y + connect \Y $ternary$libresoc.v:186824$12451_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:186827$12453 + cell $mux $ternary$libresoc.v:186826$12453 parameter \WIDTH 32 connect \A \abs_dend [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:186827$12453_Y + connect \Y $ternary$libresoc.v:186826$12453_Y end - attribute \src "libresoc.v:186465.7-186465.20" - process $proc$libresoc.v:186465$12459 + attribute \src "libresoc.v:186464.7-186464.20" + process $proc$libresoc.v:186464$12459 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186831.3-186856.6" - process $proc$libresoc.v:186831$12458 + attribute \src "libresoc.v:186830.3-186855.6" + process $proc$libresoc.v:186830$12458 assign { } { } assign { } { } assign $0\dividend[127:0] $1\dividend[127:0] - attribute \src "libresoc.v:186832.5-186832.29" + attribute \src "libresoc.v:186831.5-186831.29" switch \initial - attribute \src "libresoc.v:186832.9-186832.17" + attribute \src "libresoc.v:186831.9-186831.17" case 1'1 case end @@ -387778,28 +384588,28 @@ module \setup_stage sync always update \dividend $0\dividend[127:0] end - connect \$21 $ternary$libresoc.v:186809$12431_Y - connect \$23 $and$libresoc.v:186810$12432_Y - connect \$25 $ternary$libresoc.v:186811$12433_Y - connect \$27 $and$libresoc.v:186812$12434_Y - connect \$30 $neg$libresoc.v:186813$12436_Y - connect \$32 $pos$libresoc.v:186814$12438_Y - connect \$34 $ternary$libresoc.v:186815$12439_Y - connect \$37 $neg$libresoc.v:186816$12441_Y - connect \$39 $pos$libresoc.v:186817$12443_Y - connect \$41 $ternary$libresoc.v:186818$12444_Y - connect \$43 $ge$libresoc.v:186819$12445_Y - connect \$45 $eq$libresoc.v:186820$12446_Y - connect \$47 $and$libresoc.v:186821$12447_Y - connect \$49 $ge$libresoc.v:186822$12448_Y - connect \$51 $eq$libresoc.v:186823$12449_Y - connect \$53 $and$libresoc.v:186824$12450_Y - connect \$55 $ternary$libresoc.v:186825$12451_Y - connect \$57 $eq$libresoc.v:186826$12452_Y - connect \$59 $ternary$libresoc.v:186827$12453_Y - connect \$62 $sshl$libresoc.v:186828$12454_Y - connect \$61 $pos$libresoc.v:186829$12456_Y - connect \$66 $sshl$libresoc.v:186830$12457_Y + connect \$21 $ternary$libresoc.v:186808$12431_Y + connect \$23 $and$libresoc.v:186809$12432_Y + connect \$25 $ternary$libresoc.v:186810$12433_Y + connect \$27 $and$libresoc.v:186811$12434_Y + connect \$30 $neg$libresoc.v:186812$12436_Y + connect \$32 $pos$libresoc.v:186813$12438_Y + connect \$34 $ternary$libresoc.v:186814$12439_Y + connect \$37 $neg$libresoc.v:186815$12441_Y + connect \$39 $pos$libresoc.v:186816$12443_Y + connect \$41 $ternary$libresoc.v:186817$12444_Y + connect \$43 $ge$libresoc.v:186818$12445_Y + connect \$45 $eq$libresoc.v:186819$12446_Y + connect \$47 $and$libresoc.v:186820$12447_Y + connect \$49 $ge$libresoc.v:186821$12448_Y + connect \$51 $eq$libresoc.v:186822$12449_Y + connect \$53 $and$libresoc.v:186823$12450_Y + connect \$55 $ternary$libresoc.v:186824$12451_Y + connect \$57 $eq$libresoc.v:186825$12452_Y + connect \$59 $ternary$libresoc.v:186826$12453_Y + connect \$62 $sshl$libresoc.v:186827$12454_Y + connect \$61 $pos$libresoc.v:186828$12456_Y + connect \$66 $sshl$libresoc.v:186829$12457_Y connect \$29 \$34 connect \$36 \$41 connect \$65 \$66 @@ -387817,513 +384627,513 @@ module \setup_stage connect \dividend_neg \$23 connect \operation 2'01 end -attribute \src "libresoc.v:186877.1-188084.10" +attribute \src "libresoc.v:186876.1-188083.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0" attribute \generator "nMigen" module \shiftrot0 - attribute \src "libresoc.v:187655.3-187656.25" + attribute \src "libresoc.v:187654.3-187655.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:187653.3-187654.46" + attribute \src "libresoc.v:187652.3-187653.46" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:188004.3-188012.6" + attribute \src "libresoc.v:188003.3-188011.6" wire $0\alu_l_r_alu$next[0:0]$12677 - attribute \src "libresoc.v:187571.3-187572.39" + attribute \src "libresoc.v:187570.3-187571.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire width 14 $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12594 - attribute \src "libresoc.v:187599.3-187600.75" + attribute \src "libresoc.v:187598.3-187599.75" wire width 14 $0\alu_shift_rot0_sr_op__fn_unit[13:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12595 - attribute \src "libresoc.v:187601.3-187602.89" + attribute \src "libresoc.v:187600.3-187601.89" wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12596 - attribute \src "libresoc.v:187603.3-187604.85" + attribute \src "libresoc.v:187602.3-187603.85" wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12597 - attribute \src "libresoc.v:187617.3-187618.83" + attribute \src "libresoc.v:187616.3-187617.83" wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12598 - attribute \src "libresoc.v:187621.3-187622.77" + attribute \src "libresoc.v:187620.3-187621.77" wire $0\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12599 - attribute \src "libresoc.v:187629.3-187630.69" + attribute \src "libresoc.v:187628.3-187629.69" wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12600 - attribute \src "libresoc.v:187597.3-187598.79" + attribute \src "libresoc.v:187596.3-187597.79" wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12601 - attribute \src "libresoc.v:187615.3-187616.79" + attribute \src "libresoc.v:187614.3-187615.79" wire $0\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12602 - attribute \src "libresoc.v:187625.3-187626.77" + attribute \src "libresoc.v:187624.3-187625.77" wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12603 - attribute \src "libresoc.v:187627.3-187628.79" + attribute \src "libresoc.v:187626.3-187627.79" wire $0\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12604 - attribute \src "libresoc.v:187609.3-187610.73" + attribute \src "libresoc.v:187608.3-187609.73" wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12605 - attribute \src "libresoc.v:187611.3-187612.73" + attribute \src "libresoc.v:187610.3-187611.73" wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12606 - attribute \src "libresoc.v:187619.3-187620.85" + attribute \src "libresoc.v:187618.3-187619.85" wire $0\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12607 - attribute \src "libresoc.v:187623.3-187624.79" + attribute \src "libresoc.v:187622.3-187623.79" wire $0\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12608 - attribute \src "libresoc.v:187607.3-187608.73" + attribute \src "libresoc.v:187606.3-187607.73" wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 - attribute \src "libresoc.v:187605.3-187606.73" + attribute \src "libresoc.v:187604.3-187605.73" wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12610 - attribute \src "libresoc.v:187613.3-187614.79" + attribute \src "libresoc.v:187612.3-187613.79" wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:187995.3-188003.6" + attribute \src "libresoc.v:187994.3-188002.6" wire $0\alui_l_r_alui$next[0:0]$12674 - attribute \src "libresoc.v:187573.3-187574.43" + attribute \src "libresoc.v:187572.3-187573.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:187879.3-187900.6" + attribute \src "libresoc.v:187878.3-187899.6" wire width 64 $0\data_r0__o$next[63:0]$12635 - attribute \src "libresoc.v:187593.3-187594.37" + attribute \src "libresoc.v:187592.3-187593.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:187879.3-187900.6" + attribute \src "libresoc.v:187878.3-187899.6" wire $0\data_r0__o_ok$next[0:0]$12636 - attribute \src "libresoc.v:187595.3-187596.43" + attribute \src "libresoc.v:187594.3-187595.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:187901.3-187922.6" + attribute \src "libresoc.v:187900.3-187921.6" wire width 4 $0\data_r1__cr_a$next[3:0]$12643 - attribute \src "libresoc.v:187589.3-187590.43" + attribute \src "libresoc.v:187588.3-187589.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:187901.3-187922.6" + attribute \src "libresoc.v:187900.3-187921.6" wire $0\data_r1__cr_a_ok$next[0:0]$12644 - attribute \src "libresoc.v:187591.3-187592.49" + attribute \src "libresoc.v:187590.3-187591.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:187923.3-187944.6" + attribute \src "libresoc.v:187922.3-187943.6" wire width 2 $0\data_r2__xer_ca$next[1:0]$12651 - attribute \src "libresoc.v:187585.3-187586.47" + attribute \src "libresoc.v:187584.3-187585.47" wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:187923.3-187944.6" + attribute \src "libresoc.v:187922.3-187943.6" wire $0\data_r2__xer_ca_ok$next[0:0]$12652 - attribute \src "libresoc.v:187587.3-187588.53" + attribute \src "libresoc.v:187586.3-187587.53" wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:188013.3-188022.6" + attribute \src "libresoc.v:188012.3-188021.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:188023.3-188032.6" + attribute \src "libresoc.v:188022.3-188031.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:188033.3-188042.6" + attribute \src "libresoc.v:188032.3-188041.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:186878.7-186878.20" + attribute \src "libresoc.v:186877.7-186877.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187796.3-187804.6" + attribute \src "libresoc.v:187795.3-187803.6" wire $0\opc_l_r_opc$next[0:0]$12579 - attribute \src "libresoc.v:187639.3-187640.39" + attribute \src "libresoc.v:187638.3-187639.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:187787.3-187795.6" + attribute \src "libresoc.v:187786.3-187794.6" wire $0\opc_l_s_opc$next[0:0]$12576 - attribute \src "libresoc.v:187641.3-187642.39" + attribute \src "libresoc.v:187640.3-187641.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:188043.3-188051.6" + attribute \src "libresoc.v:188042.3-188050.6" wire width 3 $0\prev_wr_go$next[2:0]$12683 - attribute \src "libresoc.v:187651.3-187652.37" + attribute \src "libresoc.v:187650.3-187651.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:187741.3-187750.6" + attribute \src "libresoc.v:187740.3-187749.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:187832.3-187840.6" + attribute \src "libresoc.v:187831.3-187839.6" wire width 3 $0\req_l_r_req$next[2:0]$12591 - attribute \src "libresoc.v:187631.3-187632.39" + attribute \src "libresoc.v:187630.3-187631.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:187823.3-187831.6" + attribute \src "libresoc.v:187822.3-187830.6" wire width 3 $0\req_l_s_req$next[2:0]$12588 - attribute \src "libresoc.v:187633.3-187634.39" + attribute \src "libresoc.v:187632.3-187633.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:187760.3-187768.6" + attribute \src "libresoc.v:187759.3-187767.6" wire $0\rok_l_r_rdok$next[0:0]$12567 - attribute \src "libresoc.v:187647.3-187648.41" + attribute \src "libresoc.v:187646.3-187647.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:187751.3-187759.6" + attribute \src "libresoc.v:187750.3-187758.6" wire $0\rok_l_s_rdok$next[0:0]$12564 - attribute \src "libresoc.v:187649.3-187650.41" + attribute \src "libresoc.v:187648.3-187649.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:187778.3-187786.6" + attribute \src "libresoc.v:187777.3-187785.6" wire $0\rst_l_r_rst$next[0:0]$12573 - attribute \src "libresoc.v:187643.3-187644.39" + attribute \src "libresoc.v:187642.3-187643.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:187769.3-187777.6" + attribute \src "libresoc.v:187768.3-187776.6" wire $0\rst_l_s_rst$next[0:0]$12570 - attribute \src "libresoc.v:187645.3-187646.39" + attribute \src "libresoc.v:187644.3-187645.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:187814.3-187822.6" + attribute \src "libresoc.v:187813.3-187821.6" wire width 5 $0\src_l_r_src$next[4:0]$12585 - attribute \src "libresoc.v:187635.3-187636.39" + attribute \src "libresoc.v:187634.3-187635.39" wire width 5 $0\src_l_r_src[4:0] - attribute \src "libresoc.v:187805.3-187813.6" + attribute \src "libresoc.v:187804.3-187812.6" wire width 5 $0\src_l_s_src$next[4:0]$12582 - attribute \src "libresoc.v:187637.3-187638.39" + attribute \src "libresoc.v:187636.3-187637.39" wire width 5 $0\src_l_s_src[4:0] - attribute \src "libresoc.v:187945.3-187954.6" + attribute \src "libresoc.v:187944.3-187953.6" wire width 64 $0\src_r0$next[63:0]$12659 - attribute \src "libresoc.v:187583.3-187584.29" + attribute \src "libresoc.v:187582.3-187583.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:187955.3-187964.6" + attribute \src "libresoc.v:187954.3-187963.6" wire width 64 $0\src_r1$next[63:0]$12662 - attribute \src "libresoc.v:187581.3-187582.29" + attribute \src "libresoc.v:187580.3-187581.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:187965.3-187974.6" + attribute \src "libresoc.v:187964.3-187973.6" wire width 64 $0\src_r2$next[63:0]$12665 - attribute \src "libresoc.v:187579.3-187580.29" + attribute \src "libresoc.v:187578.3-187579.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:187975.3-187984.6" + attribute \src "libresoc.v:187974.3-187983.6" wire $0\src_r3$next[0:0]$12668 - attribute \src "libresoc.v:187577.3-187578.29" + attribute \src "libresoc.v:187576.3-187577.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:187985.3-187994.6" + attribute \src "libresoc.v:187984.3-187993.6" wire width 2 $0\src_r4$next[1:0]$12671 - attribute \src "libresoc.v:187575.3-187576.29" + attribute \src "libresoc.v:187574.3-187575.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:187000.7-187000.24" + attribute \src "libresoc.v:186999.7-186999.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:187010.7-187010.26" + attribute \src "libresoc.v:187009.7-187009.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:188004.3-188012.6" + attribute \src "libresoc.v:188003.3-188011.6" wire $1\alu_l_r_alu$next[0:0]$12678 - attribute \src "libresoc.v:187018.7-187018.25" + attribute \src "libresoc.v:187017.7-187017.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire width 14 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 - attribute \src "libresoc.v:187061.14-187061.54" + attribute \src "libresoc.v:187060.14-187060.54" wire width 14 $1\alu_shift_rot0_sr_op__fn_unit[13:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 - attribute \src "libresoc.v:187065.14-187065.73" + attribute \src "libresoc.v:187064.14-187064.73" wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 - attribute \src "libresoc.v:187069.7-187069.48" + attribute \src "libresoc.v:187068.7-187068.48" wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 - attribute \src "libresoc.v:187077.13-187077.53" + attribute \src "libresoc.v:187076.13-187076.53" wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 - attribute \src "libresoc.v:187081.7-187081.44" + attribute \src "libresoc.v:187080.7-187080.44" wire $1\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 - attribute \src "libresoc.v:187085.14-187085.48" + attribute \src "libresoc.v:187084.14-187084.48" wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 - attribute \src "libresoc.v:187164.13-187164.52" + attribute \src "libresoc.v:187163.13-187163.52" wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 - attribute \src "libresoc.v:187168.7-187168.45" + attribute \src "libresoc.v:187167.7-187167.45" wire $1\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 - attribute \src "libresoc.v:187172.7-187172.44" + attribute \src "libresoc.v:187171.7-187171.44" wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 - attribute \src "libresoc.v:187176.7-187176.45" + attribute \src "libresoc.v:187175.7-187175.45" wire $1\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 - attribute \src "libresoc.v:187180.7-187180.42" + attribute \src "libresoc.v:187179.7-187179.42" wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 - attribute \src "libresoc.v:187184.7-187184.42" + attribute \src "libresoc.v:187183.7-187183.42" wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 - attribute \src "libresoc.v:187188.7-187188.48" + attribute \src "libresoc.v:187187.7-187187.48" wire $1\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 - attribute \src "libresoc.v:187192.7-187192.45" + attribute \src "libresoc.v:187191.7-187191.45" wire $1\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 - attribute \src "libresoc.v:187196.7-187196.42" + attribute \src "libresoc.v:187195.7-187195.42" wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 - attribute \src "libresoc.v:187200.7-187200.42" + attribute \src "libresoc.v:187199.7-187199.42" wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 - attribute \src "libresoc.v:187204.7-187204.45" + attribute \src "libresoc.v:187203.7-187203.45" wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:187995.3-188003.6" + attribute \src "libresoc.v:187994.3-188002.6" wire $1\alui_l_r_alui$next[0:0]$12675 - attribute \src "libresoc.v:187216.7-187216.27" + attribute \src "libresoc.v:187215.7-187215.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:187879.3-187900.6" + attribute \src "libresoc.v:187878.3-187899.6" wire width 64 $1\data_r0__o$next[63:0]$12637 - attribute \src "libresoc.v:187250.14-187250.47" + attribute \src "libresoc.v:187249.14-187249.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:187879.3-187900.6" + attribute \src "libresoc.v:187878.3-187899.6" wire $1\data_r0__o_ok$next[0:0]$12638 - attribute \src "libresoc.v:187254.7-187254.27" + attribute \src "libresoc.v:187253.7-187253.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:187901.3-187922.6" + attribute \src "libresoc.v:187900.3-187921.6" wire width 4 $1\data_r1__cr_a$next[3:0]$12645 - attribute \src "libresoc.v:187258.13-187258.33" + attribute \src "libresoc.v:187257.13-187257.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:187901.3-187922.6" + attribute \src "libresoc.v:187900.3-187921.6" wire $1\data_r1__cr_a_ok$next[0:0]$12646 - attribute \src "libresoc.v:187262.7-187262.30" + attribute \src "libresoc.v:187261.7-187261.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:187923.3-187944.6" + attribute \src "libresoc.v:187922.3-187943.6" wire width 2 $1\data_r2__xer_ca$next[1:0]$12653 - attribute \src "libresoc.v:187266.13-187266.35" + attribute \src "libresoc.v:187265.13-187265.35" wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:187923.3-187944.6" + attribute \src "libresoc.v:187922.3-187943.6" wire $1\data_r2__xer_ca_ok$next[0:0]$12654 - attribute \src "libresoc.v:187270.7-187270.32" + attribute \src "libresoc.v:187269.7-187269.32" wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:188013.3-188022.6" + attribute \src "libresoc.v:188012.3-188021.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:188023.3-188032.6" + attribute \src "libresoc.v:188022.3-188031.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:188033.3-188042.6" + attribute \src "libresoc.v:188032.3-188041.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:187796.3-187804.6" + attribute \src "libresoc.v:187795.3-187803.6" wire $1\opc_l_r_opc$next[0:0]$12580 - attribute \src "libresoc.v:187287.7-187287.25" + attribute \src "libresoc.v:187286.7-187286.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:187787.3-187795.6" + attribute \src "libresoc.v:187786.3-187794.6" wire $1\opc_l_s_opc$next[0:0]$12577 - attribute \src "libresoc.v:187291.7-187291.25" + attribute \src "libresoc.v:187290.7-187290.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:188043.3-188051.6" + attribute \src "libresoc.v:188042.3-188050.6" wire width 3 $1\prev_wr_go$next[2:0]$12684 - attribute \src "libresoc.v:187423.13-187423.30" + attribute \src "libresoc.v:187422.13-187422.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:187741.3-187750.6" + attribute \src "libresoc.v:187740.3-187749.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:187832.3-187840.6" + attribute \src "libresoc.v:187831.3-187839.6" wire width 3 $1\req_l_r_req$next[2:0]$12592 - attribute \src "libresoc.v:187431.13-187431.31" + attribute \src "libresoc.v:187430.13-187430.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:187823.3-187831.6" + attribute \src "libresoc.v:187822.3-187830.6" wire width 3 $1\req_l_s_req$next[2:0]$12589 - attribute \src "libresoc.v:187435.13-187435.31" + attribute \src "libresoc.v:187434.13-187434.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:187760.3-187768.6" + attribute \src "libresoc.v:187759.3-187767.6" wire $1\rok_l_r_rdok$next[0:0]$12568 - attribute \src "libresoc.v:187447.7-187447.26" + attribute \src "libresoc.v:187446.7-187446.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:187751.3-187759.6" + attribute \src "libresoc.v:187750.3-187758.6" wire $1\rok_l_s_rdok$next[0:0]$12565 - attribute \src "libresoc.v:187451.7-187451.26" + attribute \src "libresoc.v:187450.7-187450.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:187778.3-187786.6" + attribute \src "libresoc.v:187777.3-187785.6" wire $1\rst_l_r_rst$next[0:0]$12574 - attribute \src "libresoc.v:187455.7-187455.25" + attribute \src "libresoc.v:187454.7-187454.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:187769.3-187777.6" + attribute \src "libresoc.v:187768.3-187776.6" wire $1\rst_l_s_rst$next[0:0]$12571 - attribute \src "libresoc.v:187459.7-187459.25" + attribute \src "libresoc.v:187458.7-187458.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:187814.3-187822.6" + attribute \src "libresoc.v:187813.3-187821.6" wire width 5 $1\src_l_r_src$next[4:0]$12586 - attribute \src "libresoc.v:187477.13-187477.32" + attribute \src "libresoc.v:187476.13-187476.32" wire width 5 $1\src_l_r_src[4:0] - attribute \src "libresoc.v:187805.3-187813.6" + attribute \src "libresoc.v:187804.3-187812.6" wire width 5 $1\src_l_s_src$next[4:0]$12583 - attribute \src "libresoc.v:187481.13-187481.32" + attribute \src "libresoc.v:187480.13-187480.32" wire width 5 $1\src_l_s_src[4:0] - attribute \src "libresoc.v:187945.3-187954.6" + attribute \src "libresoc.v:187944.3-187953.6" wire width 64 $1\src_r0$next[63:0]$12660 - attribute \src "libresoc.v:187487.14-187487.43" + attribute \src "libresoc.v:187486.14-187486.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:187955.3-187964.6" + attribute \src "libresoc.v:187954.3-187963.6" wire width 64 $1\src_r1$next[63:0]$12663 - attribute \src "libresoc.v:187491.14-187491.43" + attribute \src "libresoc.v:187490.14-187490.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:187965.3-187974.6" + attribute \src "libresoc.v:187964.3-187973.6" wire width 64 $1\src_r2$next[63:0]$12666 - attribute \src "libresoc.v:187495.14-187495.43" + attribute \src "libresoc.v:187494.14-187494.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:187975.3-187984.6" + attribute \src "libresoc.v:187974.3-187983.6" wire $1\src_r3$next[0:0]$12669 - attribute \src "libresoc.v:187499.7-187499.20" + attribute \src "libresoc.v:187498.7-187498.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:187985.3-187994.6" + attribute \src "libresoc.v:187984.3-187993.6" wire width 2 $1\src_r4$next[1:0]$12672 - attribute \src "libresoc.v:187503.13-187503.26" + attribute \src "libresoc.v:187502.13-187502.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 - attribute \src "libresoc.v:187841.3-187878.6" + attribute \src "libresoc.v:187840.3-187877.6" wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 - attribute \src "libresoc.v:187879.3-187900.6" + attribute \src "libresoc.v:187878.3-187899.6" wire width 64 $2\data_r0__o$next[63:0]$12639 - attribute \src "libresoc.v:187879.3-187900.6" + attribute \src "libresoc.v:187878.3-187899.6" wire $2\data_r0__o_ok$next[0:0]$12640 - attribute \src "libresoc.v:187901.3-187922.6" + attribute \src "libresoc.v:187900.3-187921.6" wire width 4 $2\data_r1__cr_a$next[3:0]$12647 - attribute \src "libresoc.v:187901.3-187922.6" + attribute \src "libresoc.v:187900.3-187921.6" wire $2\data_r1__cr_a_ok$next[0:0]$12648 - attribute \src "libresoc.v:187923.3-187944.6" + attribute \src "libresoc.v:187922.3-187943.6" wire width 2 $2\data_r2__xer_ca$next[1:0]$12655 - attribute \src "libresoc.v:187923.3-187944.6" + attribute \src "libresoc.v:187922.3-187943.6" wire $2\data_r2__xer_ca_ok$next[0:0]$12656 - attribute \src "libresoc.v:187879.3-187900.6" + attribute \src "libresoc.v:187878.3-187899.6" wire $3\data_r0__o_ok$next[0:0]$12641 - attribute \src "libresoc.v:187901.3-187922.6" + attribute \src "libresoc.v:187900.3-187921.6" wire $3\data_r1__cr_a_ok$next[0:0]$12649 - attribute \src "libresoc.v:187923.3-187944.6" + attribute \src "libresoc.v:187922.3-187943.6" wire $3\data_r2__xer_ca_ok$next[0:0]$12657 - attribute \src "libresoc.v:187513.19-187513.114" - wire width 5 $and$libresoc.v:187513$12461_Y + attribute \src "libresoc.v:187512.19-187512.114" + wire width 5 $and$libresoc.v:187512$12461_Y + attribute \src "libresoc.v:187513.19-187513.125" + wire $and$libresoc.v:187513$12462_Y attribute \src "libresoc.v:187514.19-187514.125" - wire $and$libresoc.v:187514$12462_Y + wire $and$libresoc.v:187514$12463_Y attribute \src "libresoc.v:187515.19-187515.125" - wire $and$libresoc.v:187515$12463_Y - attribute \src "libresoc.v:187516.19-187516.125" - wire $and$libresoc.v:187516$12464_Y - attribute \src "libresoc.v:187517.18-187517.110" - wire $and$libresoc.v:187517$12465_Y - attribute \src "libresoc.v:187518.19-187518.141" - wire width 3 $and$libresoc.v:187518$12466_Y - attribute \src "libresoc.v:187519.19-187519.121" - wire width 3 $and$libresoc.v:187519$12467_Y + wire $and$libresoc.v:187515$12464_Y + attribute \src "libresoc.v:187516.18-187516.110" + wire $and$libresoc.v:187516$12465_Y + attribute \src "libresoc.v:187517.19-187517.141" + wire width 3 $and$libresoc.v:187517$12466_Y + attribute \src "libresoc.v:187518.19-187518.121" + wire width 3 $and$libresoc.v:187518$12467_Y + attribute \src "libresoc.v:187519.19-187519.127" + wire $and$libresoc.v:187519$12468_Y attribute \src "libresoc.v:187520.19-187520.127" - wire $and$libresoc.v:187520$12468_Y + wire $and$libresoc.v:187520$12469_Y attribute \src "libresoc.v:187521.19-187521.127" - wire $and$libresoc.v:187521$12469_Y - attribute \src "libresoc.v:187522.19-187522.127" - wire $and$libresoc.v:187522$12470_Y - attribute \src "libresoc.v:187524.18-187524.98" - wire $and$libresoc.v:187524$12472_Y - attribute \src "libresoc.v:187526.18-187526.100" - wire $and$libresoc.v:187526$12474_Y - attribute \src "libresoc.v:187527.18-187527.149" - wire width 3 $and$libresoc.v:187527$12475_Y - attribute \src "libresoc.v:187529.18-187529.119" - wire width 3 $and$libresoc.v:187529$12477_Y - attribute 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$and$libresoc.v:187567$12516_Y + attribute \src "libresoc.v:187569.18-187569.129" + wire width 5 $and$libresoc.v:187569$12518_Y + attribute \src "libresoc.v:187539.18-187539.113" + wire $eq$libresoc.v:187539$12488_Y + attribute \src "libresoc.v:187541.18-187541.119" + wire $eq$libresoc.v:187541$12490_Y + attribute \src "libresoc.v:187511.19-187511.115" + wire width 5 $not$libresoc.v:187511$12460_Y + attribute \src "libresoc.v:187522.18-187522.97" + wire $not$libresoc.v:187522$12471_Y + attribute \src "libresoc.v:187524.18-187524.99" + wire $not$libresoc.v:187524$12473_Y + attribute \src "libresoc.v:187527.18-187527.113" + wire width 3 $not$libresoc.v:187527$12476_Y attribute \src "libresoc.v:187530.18-187530.106" - wire $reduce_or$libresoc.v:187530$12478_Y - attribute \src "libresoc.v:187534.18-187534.113" - wire $reduce_or$libresoc.v:187534$12482_Y + wire $not$libresoc.v:187530$12479_Y + attribute \src "libresoc.v:187536.18-187536.126" + wire $not$libresoc.v:187536$12485_Y + attribute \src "libresoc.v:187547.17-187547.113" + wire width 5 $not$libresoc.v:187547$12496_Y + attribute \src "libresoc.v:187568.18-187568.136" + wire $not$libresoc.v:187568$12517_Y attribute \src "libresoc.v:187535.18-187535.112" - wire $reduce_or$libresoc.v:187535$12483_Y - attribute \src "libresoc.v:187557.18-187557.165" - wire $ternary$libresoc.v:187557$12505_Y - attribute \src "libresoc.v:187558.18-187558.182" - wire width 64 $ternary$libresoc.v:187558$12506_Y - attribute \src "libresoc.v:187560.18-187560.118" - wire width 64 $ternary$libresoc.v:187560$12508_Y - attribute \src "libresoc.v:187561.18-187561.115" - wire width 64 $ternary$libresoc.v:187561$12509_Y + wire $or$libresoc.v:187535$12484_Y + attribute \src "libresoc.v:187545.18-187545.122" + wire $or$libresoc.v:187545$12494_Y + attribute \src "libresoc.v:187546.18-187546.124" + wire $or$libresoc.v:187546$12495_Y + attribute \src "libresoc.v:187548.18-187548.155" + wire width 3 $or$libresoc.v:187548$12497_Y + attribute \src "libresoc.v:187549.18-187549.181" + wire width 5 $or$libresoc.v:187549$12498_Y + attribute \src "libresoc.v:187552.18-187552.120" + wire width 3 $or$libresoc.v:187552$12501_Y + attribute \src "libresoc.v:187558.17-187558.117" + wire width 5 $or$libresoc.v:187558$12507_Y + attribute \src "libresoc.v:187564.17-187564.104" + wire $reduce_and$libresoc.v:187564$12513_Y + attribute \src "libresoc.v:187529.18-187529.106" + wire $reduce_or$libresoc.v:187529$12478_Y + attribute \src "libresoc.v:187533.18-187533.113" + wire $reduce_or$libresoc.v:187533$12482_Y + attribute \src "libresoc.v:187534.18-187534.112" + wire $reduce_or$libresoc.v:187534$12483_Y + attribute \src "libresoc.v:187556.18-187556.165" + wire $ternary$libresoc.v:187556$12505_Y + attribute \src "libresoc.v:187557.18-187557.182" + wire width 64 $ternary$libresoc.v:187557$12506_Y + attribute \src "libresoc.v:187559.18-187559.118" + wire width 64 $ternary$libresoc.v:187559$12508_Y + attribute \src "libresoc.v:187560.18-187560.115" + wire width 64 $ternary$libresoc.v:187560$12509_Y + attribute \src "libresoc.v:187561.18-187561.118" + wire width 64 $ternary$libresoc.v:187561$12510_Y attribute \src "libresoc.v:187562.18-187562.118" - wire width 64 $ternary$libresoc.v:187562$12510_Y + wire $ternary$libresoc.v:187562$12511_Y attribute \src "libresoc.v:187563.18-187563.118" - wire $ternary$libresoc.v:187563$12511_Y - attribute \src "libresoc.v:187564.18-187564.118" - wire width 2 $ternary$libresoc.v:187564$12512_Y + wire width 2 $ternary$libresoc.v:187563$12512_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -388724,7 +385534,7 @@ module \shiftrot0 wire width 4 output 34 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 36 \dest3_o - attribute \src "libresoc.v:186878.7-186878.15" + attribute \src "libresoc.v:186877.7-186877.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 29 \o_ok @@ -388957,7 +385767,7 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 35 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187513$12461 + cell $and $and$libresoc.v:187512$12461 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -388965,10 +385775,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$98 connect \B \$100 - connect \Y $and$libresoc.v:187513$12461_Y + connect \Y $and$libresoc.v:187512$12461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187514$12462 + cell $and $and$libresoc.v:187513$12462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388976,10 +385786,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187514$12462_Y + connect \Y $and$libresoc.v:187513$12462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187515$12463 + cell $and $and$libresoc.v:187514$12463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388987,10 +385797,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187515$12463_Y + connect \Y $and$libresoc.v:187514$12463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187516$12464 + cell $and $and$libresoc.v:187515$12464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -388998,10 +385808,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187516$12464_Y + connect \Y $and$libresoc.v:187515$12464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:187517$12465 + cell $and $and$libresoc.v:187516$12465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389009,10 +385819,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:187517$12465_Y + connect \Y $and$libresoc.v:187516$12465_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:187518$12466 + cell $and $and$libresoc.v:187517$12466 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389020,10 +385830,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$104 \$106 \$108 } - connect \Y $and$libresoc.v:187518$12466_Y + connect \Y $and$libresoc.v:187517$12466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:187519$12467 + cell $and $and$libresoc.v:187518$12467 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389031,10 +385841,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187519$12467_Y + connect \Y $and$libresoc.v:187518$12467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187520$12468 + cell $and $and$libresoc.v:187519$12468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389042,10 +385852,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:187520$12468_Y + connect \Y $and$libresoc.v:187519$12468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187521$12469 + cell $and $and$libresoc.v:187520$12469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389053,10 +385863,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:187521$12469_Y + connect \Y $and$libresoc.v:187520$12469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187522$12470 + cell $and $and$libresoc.v:187521$12470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389064,10 +385874,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:187522$12470_Y + connect \Y $and$libresoc.v:187521$12470_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:187524$12472 + cell $and $and$libresoc.v:187523$12472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389075,10 +385885,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:187524$12472_Y + connect \Y $and$libresoc.v:187523$12472_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:187526$12474 + cell $and $and$libresoc.v:187525$12474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389086,10 +385896,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:187526$12474_Y + connect \Y $and$libresoc.v:187525$12474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:187527$12475 + cell $and $and$libresoc.v:187526$12475 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389097,10 +385907,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:187527$12475_Y + connect \Y $and$libresoc.v:187526$12475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:187529$12477 + cell $and $and$libresoc.v:187528$12477 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389108,10 +385918,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:187529$12477_Y + connect \Y $and$libresoc.v:187528$12477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:187532$12480 + cell $and $and$libresoc.v:187531$12480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389119,10 +385929,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:187532$12480_Y + connect \Y $and$libresoc.v:187531$12480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:187533$12481 + cell $and $and$libresoc.v:187532$12481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389130,10 +385940,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:187533$12481_Y + connect \Y $and$libresoc.v:187532$12481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:187538$12486 + cell $and $and$libresoc.v:187537$12486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389141,10 +385951,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:187538$12486_Y + connect \Y $and$libresoc.v:187537$12486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:187539$12487 + cell $and $and$libresoc.v:187538$12487 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389152,10 +385962,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187539$12487_Y + connect \Y $and$libresoc.v:187538$12487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:187541$12489 + cell $and $and$libresoc.v:187540$12489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389163,10 +385973,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:187541$12489_Y + connect \Y $and$libresoc.v:187540$12489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187543$12491 + cell $and $and$libresoc.v:187542$12491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389174,10 +385984,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_shift_rot0_n_ready_i - connect \Y $and$libresoc.v:187543$12491_Y + connect \Y $and$libresoc.v:187542$12491_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187544$12492 + cell $and $and$libresoc.v:187543$12492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389185,10 +385995,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_shift_rot0_n_valid_o - connect \Y $and$libresoc.v:187544$12492_Y + connect \Y $and$libresoc.v:187543$12492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187545$12493 + cell $and $and$libresoc.v:187544$12493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389196,10 +386006,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:187545$12493_Y + connect \Y $and$libresoc.v:187544$12493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:187551$12499 + cell $and $and$libresoc.v:187550$12499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389207,10 +386017,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:187551$12499_Y + connect \Y $and$libresoc.v:187550$12499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:187552$12500 + cell $and $and$libresoc.v:187551$12500 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389218,10 +386028,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187552$12500_Y + connect \Y $and$libresoc.v:187551$12500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187554$12502 + cell $and $and$libresoc.v:187553$12502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389229,10 +386039,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:187554$12502_Y + connect \Y $and$libresoc.v:187553$12502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187555$12503 + cell $and $and$libresoc.v:187554$12503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389240,10 +386050,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:187555$12503_Y + connect \Y $and$libresoc.v:187554$12503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187556$12504 + cell $and $and$libresoc.v:187555$12504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389251,10 +386061,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:187556$12504_Y + connect \Y $and$libresoc.v:187555$12504_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:187566$12514 + cell $and $and$libresoc.v:187565$12514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389262,10 +386072,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:187566$12514_Y + connect \Y $and$libresoc.v:187565$12514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:187567$12515 + cell $and $and$libresoc.v:187566$12515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389273,10 +386083,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:187567$12515_Y + connect \Y $and$libresoc.v:187566$12515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187568$12516 + cell $and $and$libresoc.v:187567$12516 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -389284,10 +386094,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:187568$12516_Y + connect \Y $and$libresoc.v:187567$12516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187570$12518 + cell $and $and$libresoc.v:187569$12518 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -389295,10 +386105,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$94 connect \B { 3'111 \$96 1'1 } - connect \Y $and$libresoc.v:187570$12518_Y + connect \Y $and$libresoc.v:187569$12518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:187540$12488 + cell $eq $eq$libresoc.v:187539$12488 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389306,10 +386116,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:187540$12488_Y + connect \Y $eq$libresoc.v:187539$12488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:187542$12490 + cell $eq $eq$libresoc.v:187541$12490 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389317,74 +386127,74 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:187542$12490_Y + connect \Y $eq$libresoc.v:187541$12490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:187512$12460 + cell $not $not$libresoc.v:187511$12460 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:187512$12460_Y + connect \Y $not$libresoc.v:187511$12460_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:187523$12471 + cell $not $not$libresoc.v:187522$12471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:187523$12471_Y + connect \Y $not$libresoc.v:187522$12471_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:187525$12473 + cell $not $not$libresoc.v:187524$12473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:187525$12473_Y + connect \Y $not$libresoc.v:187524$12473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:187528$12476 + cell $not $not$libresoc.v:187527$12476 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:187528$12476_Y + connect \Y $not$libresoc.v:187527$12476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:187531$12479 + cell $not $not$libresoc.v:187530$12479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:187531$12479_Y + connect \Y $not$libresoc.v:187530$12479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:187537$12485 + cell $not $not$libresoc.v:187536$12485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_ready_i - connect \Y $not$libresoc.v:187537$12485_Y + connect \Y $not$libresoc.v:187536$12485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:187548$12496 + cell $not $not$libresoc.v:187547$12496 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:187548$12496_Y + connect \Y $not$libresoc.v:187547$12496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:187569$12517 + cell $not $not$libresoc.v:187568$12517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $not$libresoc.v:187569$12517_Y + connect \Y $not$libresoc.v:187568$12517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:187536$12484 + cell $or $or$libresoc.v:187535$12484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389392,10 +386202,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:187536$12484_Y + connect \Y $or$libresoc.v:187535$12484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:187546$12494 + cell $or $or$libresoc.v:187545$12494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389403,10 +386213,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:187546$12494_Y + connect \Y $or$libresoc.v:187545$12494_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:187547$12495 + cell $or $or$libresoc.v:187546$12495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -389414,10 +386224,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:187547$12495_Y + connect \Y $or$libresoc.v:187546$12495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:187549$12497 + cell $or $or$libresoc.v:187548$12497 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389425,10 +386235,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:187549$12497_Y + connect \Y $or$libresoc.v:187548$12497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:187550$12498 + cell $or $or$libresoc.v:187549$12498 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -389436,10 +386246,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:187550$12498_Y + connect \Y $or$libresoc.v:187549$12498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:187553$12501 + cell $or $or$libresoc.v:187552$12501 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -389447,10 +386257,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:187553$12501_Y + connect \Y $or$libresoc.v:187552$12501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:187559$12507 + cell $or $or$libresoc.v:187558$12507 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -389458,98 +386268,98 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:187559$12507_Y + connect \Y $or$libresoc.v:187558$12507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:187565$12513 + cell $reduce_and $reduce_and$libresoc.v:187564$12513 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:187565$12513_Y + connect \Y $reduce_and$libresoc.v:187564$12513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:187530$12478 + cell $reduce_or $reduce_or$libresoc.v:187529$12478 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:187530$12478_Y + connect \Y $reduce_or$libresoc.v:187529$12478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:187534$12482 + cell $reduce_or $reduce_or$libresoc.v:187533$12482 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:187534$12482_Y + connect \Y $reduce_or$libresoc.v:187533$12482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:187535$12483 + cell $reduce_or $reduce_or$libresoc.v:187534$12483 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:187535$12483_Y + connect \Y $reduce_or$libresoc.v:187534$12483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:187557$12505 + cell $mux $ternary$libresoc.v:187556$12505 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:187557$12505_Y + connect \Y $ternary$libresoc.v:187556$12505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:187558$12506 + cell $mux $ternary$libresoc.v:187557$12506 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_shift_rot0_sr_op__imm_data__data connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:187558$12506_Y + connect \Y $ternary$libresoc.v:187557$12506_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187560$12508 + cell $mux $ternary$libresoc.v:187559$12508 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:187560$12508_Y + connect \Y $ternary$libresoc.v:187559$12508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187561$12509 + cell $mux $ternary$libresoc.v:187560$12509 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:187561$12509_Y + connect \Y $ternary$libresoc.v:187560$12509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187562$12510 + cell $mux $ternary$libresoc.v:187561$12510 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:187562$12510_Y + connect \Y $ternary$libresoc.v:187561$12510_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187563$12511 + cell $mux $ternary$libresoc.v:187562$12511 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:187563$12511_Y + connect \Y $ternary$libresoc.v:187562$12511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187564$12512 + cell $mux $ternary$libresoc.v:187563$12512 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:187564$12512_Y + connect \Y $ternary$libresoc.v:187563$12512_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:187657.15-187663.4" + attribute \src "libresoc.v:187656.15-187662.4" cell \alu_l$125 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -389558,7 +386368,7 @@ module \shiftrot0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:187664.18-187699.4" + attribute \src "libresoc.v:187663.18-187698.4" cell \alu_shift_rot0 \alu_shift_rot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -389596,7 +386406,7 @@ module \shiftrot0 connect \xer_so \alu_shift_rot0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:187700.16-187706.4" + attribute \src "libresoc.v:187699.16-187705.4" cell \alui_l$124 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -389605,7 +386415,7 @@ module \shiftrot0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:187707.15-187713.4" + attribute \src "libresoc.v:187706.15-187712.4" cell \opc_l$120 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -389614,7 +386424,7 @@ module \shiftrot0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:187714.15-187720.4" + attribute \src "libresoc.v:187713.15-187719.4" cell \req_l$121 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -389623,7 +386433,7 @@ module \shiftrot0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:187721.15-187727.4" + attribute \src "libresoc.v:187720.15-187726.4" cell \rok_l$123 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -389632,7 +386442,7 @@ module \shiftrot0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:187728.15-187733.4" + attribute \src "libresoc.v:187727.15-187732.4" cell \rst_l$122 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -389640,7 +386450,7 @@ module \shiftrot0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:187734.15-187740.4" + attribute \src "libresoc.v:187733.15-187739.4" cell \src_l$119 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -389648,667 +386458,667 @@ module \shiftrot0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:186878.7-186878.20" - process $proc$libresoc.v:186878$12685 + attribute \src "libresoc.v:186877.7-186877.20" + process $proc$libresoc.v:186877$12685 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:187000.7-187000.24" - process $proc$libresoc.v:187000$12686 + attribute \src "libresoc.v:186999.7-186999.24" + process $proc$libresoc.v:186999$12686 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:187010.7-187010.26" - process $proc$libresoc.v:187010$12687 + attribute \src "libresoc.v:187009.7-187009.26" + process $proc$libresoc.v:187009$12687 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:187018.7-187018.25" - process $proc$libresoc.v:187018$12688 + attribute \src "libresoc.v:187017.7-187017.25" + process $proc$libresoc.v:187017$12688 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:187061.14-187061.54" - process $proc$libresoc.v:187061$12689 + attribute \src "libresoc.v:187060.14-187060.54" + process $proc$libresoc.v:187060$12689 assign { } { } assign $1\alu_shift_rot0_sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:187065.14-187065.73" - process $proc$libresoc.v:187065$12690 + attribute \src "libresoc.v:187064.14-187064.73" + process $proc$libresoc.v:187064$12690 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:187069.7-187069.48" - process $proc$libresoc.v:187069$12691 + attribute \src "libresoc.v:187068.7-187068.48" + process $proc$libresoc.v:187068$12691 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:187077.13-187077.53" - process $proc$libresoc.v:187077$12692 + attribute \src "libresoc.v:187076.13-187076.53" + process $proc$libresoc.v:187076$12692 assign { } { } assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 sync always sync init update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:187081.7-187081.44" - process $proc$libresoc.v:187081$12693 + attribute \src "libresoc.v:187080.7-187080.44" + process $proc$libresoc.v:187080$12693 assign { } { } assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:187085.14-187085.48" - process $proc$libresoc.v:187085$12694 + attribute \src "libresoc.v:187084.14-187084.48" + process $proc$libresoc.v:187084$12694 assign { } { } assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 sync always sync init update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:187164.13-187164.52" - process $proc$libresoc.v:187164$12695 + attribute \src "libresoc.v:187163.13-187163.52" + process $proc$libresoc.v:187163$12695 assign { } { } assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:187168.7-187168.45" - process $proc$libresoc.v:187168$12696 + attribute \src "libresoc.v:187167.7-187167.45" + process $proc$libresoc.v:187167$12696 assign { } { } assign $1\alu_shift_rot0_sr_op__invert_in[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__invert_in $1\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:187172.7-187172.44" - process $proc$libresoc.v:187172$12697 + attribute \src "libresoc.v:187171.7-187171.44" + process $proc$libresoc.v:187171$12697 assign { } { } assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:187176.7-187176.45" - process $proc$libresoc.v:187176$12698 + attribute \src "libresoc.v:187175.7-187175.45" + process $proc$libresoc.v:187175$12698 assign { } { } assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:187180.7-187180.42" - process $proc$libresoc.v:187180$12699 + attribute \src "libresoc.v:187179.7-187179.42" + process $proc$libresoc.v:187179$12699 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:187184.7-187184.42" - process $proc$libresoc.v:187184$12700 + attribute \src "libresoc.v:187183.7-187183.42" + process $proc$libresoc.v:187183$12700 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:187188.7-187188.48" - process $proc$libresoc.v:187188$12701 + attribute \src "libresoc.v:187187.7-187187.48" + process $proc$libresoc.v:187187$12701 assign { } { } assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:187192.7-187192.45" - process $proc$libresoc.v:187192$12702 + attribute \src "libresoc.v:187191.7-187191.45" + process $proc$libresoc.v:187191$12702 assign { } { } assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:187196.7-187196.42" - process $proc$libresoc.v:187196$12703 + attribute \src "libresoc.v:187195.7-187195.42" + process $proc$libresoc.v:187195$12703 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:187200.7-187200.42" - process $proc$libresoc.v:187200$12704 + attribute \src "libresoc.v:187199.7-187199.42" + process $proc$libresoc.v:187199$12704 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:187204.7-187204.45" - process $proc$libresoc.v:187204$12705 + attribute \src "libresoc.v:187203.7-187203.45" + process $proc$libresoc.v:187203$12705 assign { } { } assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:187216.7-187216.27" - process $proc$libresoc.v:187216$12706 + attribute \src "libresoc.v:187215.7-187215.27" + process $proc$libresoc.v:187215$12706 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:187250.14-187250.47" - process $proc$libresoc.v:187250$12707 + attribute \src "libresoc.v:187249.14-187249.47" + process $proc$libresoc.v:187249$12707 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:187254.7-187254.27" - process $proc$libresoc.v:187254$12708 + attribute \src "libresoc.v:187253.7-187253.27" + process $proc$libresoc.v:187253$12708 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:187258.13-187258.33" - process $proc$libresoc.v:187258$12709 + attribute \src "libresoc.v:187257.13-187257.33" + process $proc$libresoc.v:187257$12709 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:187262.7-187262.30" - process $proc$libresoc.v:187262$12710 + attribute \src "libresoc.v:187261.7-187261.30" + process $proc$libresoc.v:187261$12710 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:187266.13-187266.35" - process $proc$libresoc.v:187266$12711 + attribute \src "libresoc.v:187265.13-187265.35" + process $proc$libresoc.v:187265$12711 assign { } { } assign $1\data_r2__xer_ca[1:0] 2'00 sync always sync init update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:187270.7-187270.32" - process $proc$libresoc.v:187270$12712 + attribute \src "libresoc.v:187269.7-187269.32" + process $proc$libresoc.v:187269$12712 assign { } { } assign $1\data_r2__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:187287.7-187287.25" - process $proc$libresoc.v:187287$12713 + attribute \src "libresoc.v:187286.7-187286.25" + process $proc$libresoc.v:187286$12713 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:187291.7-187291.25" - process $proc$libresoc.v:187291$12714 + attribute \src "libresoc.v:187290.7-187290.25" + process $proc$libresoc.v:187290$12714 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:187423.13-187423.30" - process $proc$libresoc.v:187423$12715 + attribute \src "libresoc.v:187422.13-187422.30" + process $proc$libresoc.v:187422$12715 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:187431.13-187431.31" - process $proc$libresoc.v:187431$12716 + attribute \src "libresoc.v:187430.13-187430.31" + process $proc$libresoc.v:187430$12716 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:187435.13-187435.31" - process $proc$libresoc.v:187435$12717 + attribute \src "libresoc.v:187434.13-187434.31" + process $proc$libresoc.v:187434$12717 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:187447.7-187447.26" - process $proc$libresoc.v:187447$12718 + attribute \src "libresoc.v:187446.7-187446.26" + process $proc$libresoc.v:187446$12718 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:187451.7-187451.26" - process $proc$libresoc.v:187451$12719 + attribute \src "libresoc.v:187450.7-187450.26" + process $proc$libresoc.v:187450$12719 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:187455.7-187455.25" - process $proc$libresoc.v:187455$12720 + attribute \src "libresoc.v:187454.7-187454.25" + process $proc$libresoc.v:187454$12720 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:187459.7-187459.25" - process $proc$libresoc.v:187459$12721 + attribute \src "libresoc.v:187458.7-187458.25" + process $proc$libresoc.v:187458$12721 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:187477.13-187477.32" - process $proc$libresoc.v:187477$12722 + attribute \src "libresoc.v:187476.13-187476.32" + process $proc$libresoc.v:187476$12722 assign { } { } assign $1\src_l_r_src[4:0] 5'11111 sync always sync init update \src_l_r_src $1\src_l_r_src[4:0] end - attribute \src "libresoc.v:187481.13-187481.32" - process $proc$libresoc.v:187481$12723 + attribute \src "libresoc.v:187480.13-187480.32" + process $proc$libresoc.v:187480$12723 assign { } { } assign $1\src_l_s_src[4:0] 5'00000 sync always sync init update \src_l_s_src $1\src_l_s_src[4:0] end - attribute \src "libresoc.v:187487.14-187487.43" - process $proc$libresoc.v:187487$12724 + attribute \src "libresoc.v:187486.14-187486.43" + process $proc$libresoc.v:187486$12724 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:187491.14-187491.43" - process $proc$libresoc.v:187491$12725 + attribute \src "libresoc.v:187490.14-187490.43" + process $proc$libresoc.v:187490$12725 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:187495.14-187495.43" - process $proc$libresoc.v:187495$12726 + attribute \src "libresoc.v:187494.14-187494.43" + process $proc$libresoc.v:187494$12726 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:187499.7-187499.20" - process $proc$libresoc.v:187499$12727 + attribute \src "libresoc.v:187498.7-187498.20" + process $proc$libresoc.v:187498$12727 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:187503.13-187503.26" - process $proc$libresoc.v:187503$12728 + attribute \src "libresoc.v:187502.13-187502.26" + process $proc$libresoc.v:187502$12728 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:187571.3-187572.39" - process $proc$libresoc.v:187571$12519 + attribute \src "libresoc.v:187570.3-187571.39" + process $proc$libresoc.v:187570$12519 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:187573.3-187574.43" - process $proc$libresoc.v:187573$12520 + attribute \src "libresoc.v:187572.3-187573.43" + process $proc$libresoc.v:187572$12520 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:187575.3-187576.29" - process $proc$libresoc.v:187575$12521 + attribute \src "libresoc.v:187574.3-187575.29" + process $proc$libresoc.v:187574$12521 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:187577.3-187578.29" - process $proc$libresoc.v:187577$12522 + attribute \src "libresoc.v:187576.3-187577.29" + process $proc$libresoc.v:187576$12522 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:187579.3-187580.29" - process $proc$libresoc.v:187579$12523 + attribute \src "libresoc.v:187578.3-187579.29" + process $proc$libresoc.v:187578$12523 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:187581.3-187582.29" - process $proc$libresoc.v:187581$12524 + attribute \src "libresoc.v:187580.3-187581.29" + process $proc$libresoc.v:187580$12524 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:187583.3-187584.29" - process $proc$libresoc.v:187583$12525 + attribute \src "libresoc.v:187582.3-187583.29" + process $proc$libresoc.v:187582$12525 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:187585.3-187586.47" - process $proc$libresoc.v:187585$12526 + attribute \src "libresoc.v:187584.3-187585.47" + process $proc$libresoc.v:187584$12526 assign { } { } assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next sync posedge \coresync_clk update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:187587.3-187588.53" - process $proc$libresoc.v:187587$12527 + attribute \src "libresoc.v:187586.3-187587.53" + process $proc$libresoc.v:187586$12527 assign { } { } assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next sync posedge \coresync_clk update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:187589.3-187590.43" - process $proc$libresoc.v:187589$12528 + attribute \src "libresoc.v:187588.3-187589.43" + process $proc$libresoc.v:187588$12528 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:187591.3-187592.49" - process $proc$libresoc.v:187591$12529 + attribute \src "libresoc.v:187590.3-187591.49" + process $proc$libresoc.v:187590$12529 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:187593.3-187594.37" - process $proc$libresoc.v:187593$12530 + attribute \src "libresoc.v:187592.3-187593.37" + process $proc$libresoc.v:187592$12530 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:187595.3-187596.43" - process $proc$libresoc.v:187595$12531 + attribute \src "libresoc.v:187594.3-187595.43" + process $proc$libresoc.v:187594$12531 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:187597.3-187598.79" - process $proc$libresoc.v:187597$12532 + attribute \src "libresoc.v:187596.3-187597.79" + process $proc$libresoc.v:187596$12532 assign { } { } assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:187599.3-187600.75" - process $proc$libresoc.v:187599$12533 + attribute \src "libresoc.v:187598.3-187599.75" + process $proc$libresoc.v:187598$12533 assign { } { } assign $0\alu_shift_rot0_sr_op__fn_unit[13:0] \alu_shift_rot0_sr_op__fn_unit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:187601.3-187602.89" - process $proc$libresoc.v:187601$12534 + attribute \src "libresoc.v:187600.3-187601.89" + process $proc$libresoc.v:187600$12534 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:187603.3-187604.85" - process $proc$libresoc.v:187603$12535 + attribute \src "libresoc.v:187602.3-187603.85" + process $proc$libresoc.v:187602$12535 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:187605.3-187606.73" - process $proc$libresoc.v:187605$12536 + attribute \src "libresoc.v:187604.3-187605.73" + process $proc$libresoc.v:187604$12536 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:187607.3-187608.73" - process $proc$libresoc.v:187607$12537 + attribute \src "libresoc.v:187606.3-187607.73" + process $proc$libresoc.v:187606$12537 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:187609.3-187610.73" - process $proc$libresoc.v:187609$12538 + attribute \src "libresoc.v:187608.3-187609.73" + process $proc$libresoc.v:187608$12538 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:187611.3-187612.73" - process $proc$libresoc.v:187611$12539 + attribute \src "libresoc.v:187610.3-187611.73" + process $proc$libresoc.v:187610$12539 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:187613.3-187614.79" - process $proc$libresoc.v:187613$12540 + attribute \src "libresoc.v:187612.3-187613.79" + process $proc$libresoc.v:187612$12540 assign { } { } assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:187615.3-187616.79" - process $proc$libresoc.v:187615$12541 + attribute \src "libresoc.v:187614.3-187615.79" + process $proc$libresoc.v:187614$12541 assign { } { } assign $0\alu_shift_rot0_sr_op__invert_in[0:0] \alu_shift_rot0_sr_op__invert_in$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__invert_in $0\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:187617.3-187618.83" - process $proc$libresoc.v:187617$12542 + attribute \src "libresoc.v:187616.3-187617.83" + process $proc$libresoc.v:187616$12542 assign { } { } assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:187619.3-187620.85" - process $proc$libresoc.v:187619$12543 + attribute \src "libresoc.v:187618.3-187619.85" + process $proc$libresoc.v:187618$12543 assign { } { } assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:187621.3-187622.77" - process $proc$libresoc.v:187621$12544 + attribute \src "libresoc.v:187620.3-187621.77" + process $proc$libresoc.v:187620$12544 assign { } { } assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:187623.3-187624.79" - process $proc$libresoc.v:187623$12545 + attribute \src "libresoc.v:187622.3-187623.79" + process $proc$libresoc.v:187622$12545 assign { } { } assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:187625.3-187626.77" - process $proc$libresoc.v:187625$12546 + attribute \src "libresoc.v:187624.3-187625.77" + process $proc$libresoc.v:187624$12546 assign { } { } assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:187627.3-187628.79" - process $proc$libresoc.v:187627$12547 + attribute \src "libresoc.v:187626.3-187627.79" + process $proc$libresoc.v:187626$12547 assign { } { } assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:187629.3-187630.69" - process $proc$libresoc.v:187629$12548 + attribute \src "libresoc.v:187628.3-187629.69" + process $proc$libresoc.v:187628$12548 assign { } { } assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:187631.3-187632.39" - process $proc$libresoc.v:187631$12549 + attribute \src "libresoc.v:187630.3-187631.39" + process $proc$libresoc.v:187630$12549 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:187633.3-187634.39" - process $proc$libresoc.v:187633$12550 + attribute \src "libresoc.v:187632.3-187633.39" + process $proc$libresoc.v:187632$12550 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:187635.3-187636.39" - process $proc$libresoc.v:187635$12551 + attribute \src "libresoc.v:187634.3-187635.39" + process $proc$libresoc.v:187634$12551 assign { } { } assign $0\src_l_r_src[4:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[4:0] end - attribute \src "libresoc.v:187637.3-187638.39" - process $proc$libresoc.v:187637$12552 + attribute \src "libresoc.v:187636.3-187637.39" + process $proc$libresoc.v:187636$12552 assign { } { } assign $0\src_l_s_src[4:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[4:0] end - attribute \src "libresoc.v:187639.3-187640.39" - process $proc$libresoc.v:187639$12553 + attribute \src "libresoc.v:187638.3-187639.39" + process $proc$libresoc.v:187638$12553 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:187641.3-187642.39" - process $proc$libresoc.v:187641$12554 + attribute \src "libresoc.v:187640.3-187641.39" + process $proc$libresoc.v:187640$12554 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:187643.3-187644.39" - process $proc$libresoc.v:187643$12555 + attribute \src "libresoc.v:187642.3-187643.39" + process $proc$libresoc.v:187642$12555 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:187645.3-187646.39" - process $proc$libresoc.v:187645$12556 + attribute \src "libresoc.v:187644.3-187645.39" + process $proc$libresoc.v:187644$12556 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:187647.3-187648.41" - process $proc$libresoc.v:187647$12557 + attribute \src "libresoc.v:187646.3-187647.41" + process $proc$libresoc.v:187646$12557 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:187649.3-187650.41" - process $proc$libresoc.v:187649$12558 + attribute \src "libresoc.v:187648.3-187649.41" + process $proc$libresoc.v:187648$12558 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:187651.3-187652.37" - process $proc$libresoc.v:187651$12559 + attribute \src "libresoc.v:187650.3-187651.37" + process $proc$libresoc.v:187650$12559 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:187653.3-187654.46" - process $proc$libresoc.v:187653$12560 + attribute \src "libresoc.v:187652.3-187653.46" + process $proc$libresoc.v:187652$12560 assign { } { } assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:187655.3-187656.25" - process $proc$libresoc.v:187655$12561 + attribute \src "libresoc.v:187654.3-187655.25" + process $proc$libresoc.v:187654$12561 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:187741.3-187750.6" - process $proc$libresoc.v:187741$12562 + attribute \src "libresoc.v:187740.3-187749.6" + process $proc$libresoc.v:187740$12562 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:187742.5-187742.29" + attribute \src "libresoc.v:187741.5-187741.29" switch \initial - attribute \src "libresoc.v:187742.9-187742.17" + attribute \src "libresoc.v:187741.9-187741.17" case 1'1 case end @@ -390324,14 +387134,14 @@ module \shiftrot0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:187751.3-187759.6" - process $proc$libresoc.v:187751$12563 + attribute \src "libresoc.v:187750.3-187758.6" + process $proc$libresoc.v:187750$12563 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$12564 $1\rok_l_s_rdok$next[0:0]$12565 - attribute \src "libresoc.v:187752.5-187752.29" + attribute \src "libresoc.v:187751.5-187751.29" switch \initial - attribute \src "libresoc.v:187752.9-187752.17" + attribute \src "libresoc.v:187751.9-187751.17" case 1'1 case end @@ -390347,14 +387157,14 @@ module \shiftrot0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12564 end - attribute \src "libresoc.v:187760.3-187768.6" - process $proc$libresoc.v:187760$12566 + attribute \src "libresoc.v:187759.3-187767.6" + process $proc$libresoc.v:187759$12566 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$12567 $1\rok_l_r_rdok$next[0:0]$12568 - attribute \src "libresoc.v:187761.5-187761.29" + attribute \src "libresoc.v:187760.5-187760.29" switch \initial - attribute \src "libresoc.v:187761.9-187761.17" + attribute \src "libresoc.v:187760.9-187760.17" case 1'1 case end @@ -390370,14 +387180,14 @@ module \shiftrot0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12567 end - attribute \src "libresoc.v:187769.3-187777.6" - process $proc$libresoc.v:187769$12569 + attribute \src "libresoc.v:187768.3-187776.6" + process $proc$libresoc.v:187768$12569 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$12570 $1\rst_l_s_rst$next[0:0]$12571 - attribute \src "libresoc.v:187770.5-187770.29" + attribute \src "libresoc.v:187769.5-187769.29" switch \initial - attribute \src "libresoc.v:187770.9-187770.17" + attribute \src "libresoc.v:187769.9-187769.17" case 1'1 case end @@ -390393,14 +387203,14 @@ module \shiftrot0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12570 end - attribute \src "libresoc.v:187778.3-187786.6" - process $proc$libresoc.v:187778$12572 + attribute \src "libresoc.v:187777.3-187785.6" + process $proc$libresoc.v:187777$12572 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$12573 $1\rst_l_r_rst$next[0:0]$12574 - attribute \src "libresoc.v:187779.5-187779.29" + attribute \src "libresoc.v:187778.5-187778.29" switch \initial - attribute \src "libresoc.v:187779.9-187779.17" + attribute \src "libresoc.v:187778.9-187778.17" case 1'1 case end @@ -390416,14 +387226,14 @@ module \shiftrot0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12573 end - attribute \src "libresoc.v:187787.3-187795.6" - process $proc$libresoc.v:187787$12575 + attribute \src "libresoc.v:187786.3-187794.6" + process $proc$libresoc.v:187786$12575 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$12576 $1\opc_l_s_opc$next[0:0]$12577 - attribute \src "libresoc.v:187788.5-187788.29" + attribute \src "libresoc.v:187787.5-187787.29" switch \initial - attribute \src "libresoc.v:187788.9-187788.17" + attribute \src "libresoc.v:187787.9-187787.17" case 1'1 case end @@ -390439,14 +387249,14 @@ module \shiftrot0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12576 end - attribute \src "libresoc.v:187796.3-187804.6" - process $proc$libresoc.v:187796$12578 + attribute \src "libresoc.v:187795.3-187803.6" + process $proc$libresoc.v:187795$12578 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$12579 $1\opc_l_r_opc$next[0:0]$12580 - attribute \src "libresoc.v:187797.5-187797.29" + attribute \src "libresoc.v:187796.5-187796.29" switch \initial - attribute \src "libresoc.v:187797.9-187797.17" + attribute \src "libresoc.v:187796.9-187796.17" case 1'1 case end @@ -390462,14 +387272,14 @@ module \shiftrot0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12579 end - attribute \src "libresoc.v:187805.3-187813.6" - process $proc$libresoc.v:187805$12581 + attribute \src "libresoc.v:187804.3-187812.6" + process $proc$libresoc.v:187804$12581 assign { } { } assign { } { } assign $0\src_l_s_src$next[4:0]$12582 $1\src_l_s_src$next[4:0]$12583 - attribute \src "libresoc.v:187806.5-187806.29" + attribute \src "libresoc.v:187805.5-187805.29" switch \initial - attribute \src "libresoc.v:187806.9-187806.17" + attribute \src "libresoc.v:187805.9-187805.17" case 1'1 case end @@ -390485,14 +387295,14 @@ module \shiftrot0 sync always update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12582 end - attribute \src "libresoc.v:187814.3-187822.6" - process $proc$libresoc.v:187814$12584 + attribute \src "libresoc.v:187813.3-187821.6" + process $proc$libresoc.v:187813$12584 assign { } { } assign { } { } assign $0\src_l_r_src$next[4:0]$12585 $1\src_l_r_src$next[4:0]$12586 - attribute \src "libresoc.v:187815.5-187815.29" + attribute \src "libresoc.v:187814.5-187814.29" switch \initial - attribute \src "libresoc.v:187815.9-187815.17" + attribute \src "libresoc.v:187814.9-187814.17" case 1'1 case end @@ -390508,14 +387318,14 @@ module \shiftrot0 sync always update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12585 end - attribute \src "libresoc.v:187823.3-187831.6" - process $proc$libresoc.v:187823$12587 + attribute \src "libresoc.v:187822.3-187830.6" + process $proc$libresoc.v:187822$12587 assign { } { } assign { } { } assign $0\req_l_s_req$next[2:0]$12588 $1\req_l_s_req$next[2:0]$12589 - attribute \src "libresoc.v:187824.5-187824.29" + attribute \src "libresoc.v:187823.5-187823.29" switch \initial - attribute \src "libresoc.v:187824.9-187824.17" + attribute \src "libresoc.v:187823.9-187823.17" case 1'1 case end @@ -390531,14 +387341,14 @@ module \shiftrot0 sync always update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12588 end - attribute \src "libresoc.v:187832.3-187840.6" - process $proc$libresoc.v:187832$12590 + attribute \src "libresoc.v:187831.3-187839.6" + process $proc$libresoc.v:187831$12590 assign { } { } assign { } { } assign $0\req_l_r_req$next[2:0]$12591 $1\req_l_r_req$next[2:0]$12592 - attribute \src "libresoc.v:187833.5-187833.29" + attribute \src "libresoc.v:187832.5-187832.29" switch \initial - attribute \src "libresoc.v:187833.9-187833.17" + attribute \src "libresoc.v:187832.9-187832.17" case 1'1 case end @@ -390554,8 +387364,8 @@ module \shiftrot0 sync always update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12591 end - attribute \src "libresoc.v:187841.3-187878.6" - process $proc$libresoc.v:187841$12593 + attribute \src "libresoc.v:187840.3-187877.6" + process $proc$libresoc.v:187840$12593 assign { } { } assign { } { } assign { } { } @@ -390613,9 +387423,9 @@ module \shiftrot0 assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12605 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12608 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 - attribute \src "libresoc.v:187842.5-187842.29" + attribute \src "libresoc.v:187841.5-187841.29" switch \initial - attribute \src "libresoc.v:187842.9-187842.17" + attribute \src "libresoc.v:187841.9-187841.17" case 1'1 case end @@ -390703,8 +387513,8 @@ module \shiftrot0 update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12610 end - attribute \src "libresoc.v:187879.3-187900.6" - process $proc$libresoc.v:187879$12634 + attribute \src "libresoc.v:187878.3-187899.6" + process $proc$libresoc.v:187878$12634 assign { } { } assign { } { } assign { } { } @@ -390714,9 +387524,9 @@ module \shiftrot0 assign $0\data_r0__o$next[63:0]$12635 $2\data_r0__o$next[63:0]$12639 assign { } { } assign $0\data_r0__o_ok$next[0:0]$12636 $3\data_r0__o_ok$next[0:0]$12641 - attribute \src "libresoc.v:187880.5-187880.29" + attribute \src "libresoc.v:187879.5-187879.29" switch \initial - attribute \src "libresoc.v:187880.9-187880.17" + attribute \src "libresoc.v:187879.9-187879.17" case 1'1 case end @@ -390755,8 +387565,8 @@ module \shiftrot0 update \data_r0__o$next $0\data_r0__o$next[63:0]$12635 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12636 end - attribute \src "libresoc.v:187901.3-187922.6" - process $proc$libresoc.v:187901$12642 + attribute \src "libresoc.v:187900.3-187921.6" + process $proc$libresoc.v:187900$12642 assign { } { } assign { } { } assign { } { } @@ -390766,9 +387576,9 @@ module \shiftrot0 assign $0\data_r1__cr_a$next[3:0]$12643 $2\data_r1__cr_a$next[3:0]$12647 assign { } { } assign $0\data_r1__cr_a_ok$next[0:0]$12644 $3\data_r1__cr_a_ok$next[0:0]$12649 - attribute \src "libresoc.v:187902.5-187902.29" + attribute \src "libresoc.v:187901.5-187901.29" switch \initial - attribute \src "libresoc.v:187902.9-187902.17" + attribute \src "libresoc.v:187901.9-187901.17" case 1'1 case end @@ -390807,8 +387617,8 @@ module \shiftrot0 update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12643 update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12644 end - attribute \src "libresoc.v:187923.3-187944.6" - process $proc$libresoc.v:187923$12650 + attribute \src "libresoc.v:187922.3-187943.6" + process $proc$libresoc.v:187922$12650 assign { } { } assign { } { } assign { } { } @@ -390818,9 +387628,9 @@ module \shiftrot0 assign $0\data_r2__xer_ca$next[1:0]$12651 $2\data_r2__xer_ca$next[1:0]$12655 assign { } { } assign $0\data_r2__xer_ca_ok$next[0:0]$12652 $3\data_r2__xer_ca_ok$next[0:0]$12657 - attribute \src "libresoc.v:187924.5-187924.29" + attribute \src "libresoc.v:187923.5-187923.29" switch \initial - attribute \src "libresoc.v:187924.9-187924.17" + attribute \src "libresoc.v:187923.9-187923.17" case 1'1 case end @@ -390859,14 +387669,14 @@ module \shiftrot0 update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12651 update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12652 end - attribute \src "libresoc.v:187945.3-187954.6" - process $proc$libresoc.v:187945$12658 + attribute \src "libresoc.v:187944.3-187953.6" + process $proc$libresoc.v:187944$12658 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$12659 $1\src_r0$next[63:0]$12660 - attribute \src "libresoc.v:187946.5-187946.29" + attribute \src "libresoc.v:187945.5-187945.29" switch \initial - attribute \src "libresoc.v:187946.9-187946.17" + attribute \src "libresoc.v:187945.9-187945.17" case 1'1 case end @@ -390882,14 +387692,14 @@ module \shiftrot0 sync always update \src_r0$next $0\src_r0$next[63:0]$12659 end - attribute \src "libresoc.v:187955.3-187964.6" - process $proc$libresoc.v:187955$12661 + attribute \src "libresoc.v:187954.3-187963.6" + process $proc$libresoc.v:187954$12661 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$12662 $1\src_r1$next[63:0]$12663 - attribute \src "libresoc.v:187956.5-187956.29" + attribute \src "libresoc.v:187955.5-187955.29" switch \initial - attribute \src "libresoc.v:187956.9-187956.17" + attribute \src "libresoc.v:187955.9-187955.17" case 1'1 case end @@ -390905,14 +387715,14 @@ module \shiftrot0 sync always update \src_r1$next $0\src_r1$next[63:0]$12662 end - attribute \src "libresoc.v:187965.3-187974.6" - process $proc$libresoc.v:187965$12664 + attribute \src "libresoc.v:187964.3-187973.6" + process $proc$libresoc.v:187964$12664 assign { } { } assign { } { } assign $0\src_r2$next[63:0]$12665 $1\src_r2$next[63:0]$12666 - attribute \src "libresoc.v:187966.5-187966.29" + attribute \src "libresoc.v:187965.5-187965.29" switch \initial - attribute \src "libresoc.v:187966.9-187966.17" + attribute \src "libresoc.v:187965.9-187965.17" case 1'1 case end @@ -390928,14 +387738,14 @@ module \shiftrot0 sync always update \src_r2$next $0\src_r2$next[63:0]$12665 end - attribute \src "libresoc.v:187975.3-187984.6" - process $proc$libresoc.v:187975$12667 + attribute \src "libresoc.v:187974.3-187983.6" + process $proc$libresoc.v:187974$12667 assign { } { } assign { } { } assign $0\src_r3$next[0:0]$12668 $1\src_r3$next[0:0]$12669 - attribute \src "libresoc.v:187976.5-187976.29" + attribute \src "libresoc.v:187975.5-187975.29" switch \initial - attribute \src "libresoc.v:187976.9-187976.17" + attribute \src "libresoc.v:187975.9-187975.17" case 1'1 case end @@ -390951,14 +387761,14 @@ module \shiftrot0 sync always update \src_r3$next $0\src_r3$next[0:0]$12668 end - attribute \src "libresoc.v:187985.3-187994.6" - process $proc$libresoc.v:187985$12670 + attribute \src "libresoc.v:187984.3-187993.6" + process $proc$libresoc.v:187984$12670 assign { } { } assign { } { } assign $0\src_r4$next[1:0]$12671 $1\src_r4$next[1:0]$12672 - attribute \src "libresoc.v:187986.5-187986.29" + attribute \src "libresoc.v:187985.5-187985.29" switch \initial - attribute \src "libresoc.v:187986.9-187986.17" + attribute \src "libresoc.v:187985.9-187985.17" case 1'1 case end @@ -390974,14 +387784,14 @@ module \shiftrot0 sync always update \src_r4$next $0\src_r4$next[1:0]$12671 end - attribute \src "libresoc.v:187995.3-188003.6" - process $proc$libresoc.v:187995$12673 + attribute \src "libresoc.v:187994.3-188002.6" + process $proc$libresoc.v:187994$12673 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$12674 $1\alui_l_r_alui$next[0:0]$12675 - attribute \src "libresoc.v:187996.5-187996.29" + attribute \src "libresoc.v:187995.5-187995.29" switch \initial - attribute \src "libresoc.v:187996.9-187996.17" + attribute \src "libresoc.v:187995.9-187995.17" case 1'1 case end @@ -390997,14 +387807,14 @@ module \shiftrot0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12674 end - attribute \src "libresoc.v:188004.3-188012.6" - process $proc$libresoc.v:188004$12676 + attribute \src "libresoc.v:188003.3-188011.6" + process $proc$libresoc.v:188003$12676 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$12677 $1\alu_l_r_alu$next[0:0]$12678 - attribute \src "libresoc.v:188005.5-188005.29" + attribute \src "libresoc.v:188004.5-188004.29" switch \initial - attribute \src "libresoc.v:188005.9-188005.17" + attribute \src "libresoc.v:188004.9-188004.17" case 1'1 case end @@ -391020,14 +387830,14 @@ module \shiftrot0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12677 end - attribute \src "libresoc.v:188013.3-188022.6" - process $proc$libresoc.v:188013$12679 + attribute \src "libresoc.v:188012.3-188021.6" + process $proc$libresoc.v:188012$12679 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:188014.5-188014.29" + attribute \src "libresoc.v:188013.5-188013.29" switch \initial - attribute \src "libresoc.v:188014.9-188014.17" + attribute \src "libresoc.v:188013.9-188013.17" case 1'1 case end @@ -391043,14 +387853,14 @@ module \shiftrot0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:188023.3-188032.6" - process $proc$libresoc.v:188023$12680 + attribute \src "libresoc.v:188022.3-188031.6" + process $proc$libresoc.v:188022$12680 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:188024.5-188024.29" + attribute \src "libresoc.v:188023.5-188023.29" switch \initial - attribute \src "libresoc.v:188024.9-188024.17" + attribute \src "libresoc.v:188023.9-188023.17" case 1'1 case end @@ -391066,14 +387876,14 @@ module \shiftrot0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:188033.3-188042.6" - process $proc$libresoc.v:188033$12681 + attribute \src "libresoc.v:188032.3-188041.6" + process $proc$libresoc.v:188032$12681 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:188034.5-188034.29" + attribute \src "libresoc.v:188033.5-188033.29" switch \initial - attribute \src "libresoc.v:188034.9-188034.17" + attribute \src "libresoc.v:188033.9-188033.17" case 1'1 case end @@ -391089,14 +387899,14 @@ module \shiftrot0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:188043.3-188051.6" - process $proc$libresoc.v:188043$12682 + attribute \src "libresoc.v:188042.3-188050.6" + process $proc$libresoc.v:188042$12682 assign { } { } assign { } { } assign $0\prev_wr_go$next[2:0]$12683 $1\prev_wr_go$next[2:0]$12684 - attribute \src "libresoc.v:188044.5-188044.29" + attribute \src "libresoc.v:188043.5-188043.29" switch \initial - attribute \src "libresoc.v:188044.9-188044.17" + attribute \src "libresoc.v:188043.9-188043.17" case 1'1 case end @@ -391112,65 +387922,65 @@ module \shiftrot0 sync always update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12683 end - connect \$100 $not$libresoc.v:187512$12460_Y - connect \$102 $and$libresoc.v:187513$12461_Y - connect \$104 $and$libresoc.v:187514$12462_Y - connect \$106 $and$libresoc.v:187515$12463_Y - connect \$108 $and$libresoc.v:187516$12464_Y - connect \$10 $and$libresoc.v:187517$12465_Y - connect \$110 $and$libresoc.v:187518$12466_Y - connect \$112 $and$libresoc.v:187519$12467_Y - connect \$114 $and$libresoc.v:187520$12468_Y - connect \$116 $and$libresoc.v:187521$12469_Y - connect \$118 $and$libresoc.v:187522$12470_Y - connect \$12 $not$libresoc.v:187523$12471_Y - connect \$14 $and$libresoc.v:187524$12472_Y - connect \$16 $not$libresoc.v:187525$12473_Y - connect \$18 $and$libresoc.v:187526$12474_Y - connect \$20 $and$libresoc.v:187527$12475_Y - connect \$24 $not$libresoc.v:187528$12476_Y - connect \$26 $and$libresoc.v:187529$12477_Y - connect \$23 $reduce_or$libresoc.v:187530$12478_Y - connect \$22 $not$libresoc.v:187531$12479_Y - connect \$2 $and$libresoc.v:187532$12480_Y - connect \$30 $and$libresoc.v:187533$12481_Y - connect \$32 $reduce_or$libresoc.v:187534$12482_Y - connect \$34 $reduce_or$libresoc.v:187535$12483_Y - connect \$36 $or$libresoc.v:187536$12484_Y - connect \$38 $not$libresoc.v:187537$12485_Y - connect \$40 $and$libresoc.v:187538$12486_Y - connect \$42 $and$libresoc.v:187539$12487_Y - connect \$44 $eq$libresoc.v:187540$12488_Y - connect \$46 $and$libresoc.v:187541$12489_Y - connect \$48 $eq$libresoc.v:187542$12490_Y - connect \$50 $and$libresoc.v:187543$12491_Y - connect \$52 $and$libresoc.v:187544$12492_Y - connect \$54 $and$libresoc.v:187545$12493_Y - connect \$56 $or$libresoc.v:187546$12494_Y - connect \$58 $or$libresoc.v:187547$12495_Y - connect \$5 $not$libresoc.v:187548$12496_Y - connect \$60 $or$libresoc.v:187549$12497_Y - connect \$62 $or$libresoc.v:187550$12498_Y - connect \$64 $and$libresoc.v:187551$12499_Y - connect \$66 $and$libresoc.v:187552$12500_Y - connect \$68 $or$libresoc.v:187553$12501_Y - connect \$70 $and$libresoc.v:187554$12502_Y - connect \$72 $and$libresoc.v:187555$12503_Y - connect \$74 $and$libresoc.v:187556$12504_Y - connect \$76 $ternary$libresoc.v:187557$12505_Y - connect \$78 $ternary$libresoc.v:187558$12506_Y - connect \$7 $or$libresoc.v:187559$12507_Y - connect \$80 $ternary$libresoc.v:187560$12508_Y - connect \$82 $ternary$libresoc.v:187561$12509_Y - connect \$84 $ternary$libresoc.v:187562$12510_Y - connect \$86 $ternary$libresoc.v:187563$12511_Y - connect \$88 $ternary$libresoc.v:187564$12512_Y - connect \$4 $reduce_and$libresoc.v:187565$12513_Y - connect \$90 $and$libresoc.v:187566$12514_Y - connect \$92 $and$libresoc.v:187567$12515_Y - connect \$94 $and$libresoc.v:187568$12516_Y - connect \$96 $not$libresoc.v:187569$12517_Y - connect \$98 $and$libresoc.v:187570$12518_Y + connect \$100 $not$libresoc.v:187511$12460_Y + connect \$102 $and$libresoc.v:187512$12461_Y + connect \$104 $and$libresoc.v:187513$12462_Y + connect \$106 $and$libresoc.v:187514$12463_Y + connect \$108 $and$libresoc.v:187515$12464_Y + connect \$10 $and$libresoc.v:187516$12465_Y + connect \$110 $and$libresoc.v:187517$12466_Y + connect \$112 $and$libresoc.v:187518$12467_Y + connect \$114 $and$libresoc.v:187519$12468_Y + connect \$116 $and$libresoc.v:187520$12469_Y + connect \$118 $and$libresoc.v:187521$12470_Y + connect \$12 $not$libresoc.v:187522$12471_Y + connect \$14 $and$libresoc.v:187523$12472_Y + connect \$16 $not$libresoc.v:187524$12473_Y + connect \$18 $and$libresoc.v:187525$12474_Y + connect \$20 $and$libresoc.v:187526$12475_Y + connect \$24 $not$libresoc.v:187527$12476_Y + connect \$26 $and$libresoc.v:187528$12477_Y + connect \$23 $reduce_or$libresoc.v:187529$12478_Y + connect \$22 $not$libresoc.v:187530$12479_Y + connect \$2 $and$libresoc.v:187531$12480_Y + connect \$30 $and$libresoc.v:187532$12481_Y + connect \$32 $reduce_or$libresoc.v:187533$12482_Y + connect \$34 $reduce_or$libresoc.v:187534$12483_Y + connect \$36 $or$libresoc.v:187535$12484_Y + connect \$38 $not$libresoc.v:187536$12485_Y + connect \$40 $and$libresoc.v:187537$12486_Y + connect \$42 $and$libresoc.v:187538$12487_Y + connect \$44 $eq$libresoc.v:187539$12488_Y + connect \$46 $and$libresoc.v:187540$12489_Y + connect \$48 $eq$libresoc.v:187541$12490_Y + connect \$50 $and$libresoc.v:187542$12491_Y + connect \$52 $and$libresoc.v:187543$12492_Y + connect \$54 $and$libresoc.v:187544$12493_Y + connect \$56 $or$libresoc.v:187545$12494_Y + connect \$58 $or$libresoc.v:187546$12495_Y + connect \$5 $not$libresoc.v:187547$12496_Y + connect \$60 $or$libresoc.v:187548$12497_Y + connect \$62 $or$libresoc.v:187549$12498_Y + connect \$64 $and$libresoc.v:187550$12499_Y + connect \$66 $and$libresoc.v:187551$12500_Y + connect \$68 $or$libresoc.v:187552$12501_Y + connect \$70 $and$libresoc.v:187553$12502_Y + connect \$72 $and$libresoc.v:187554$12503_Y + connect \$74 $and$libresoc.v:187555$12504_Y + connect \$76 $ternary$libresoc.v:187556$12505_Y + connect \$78 $ternary$libresoc.v:187557$12506_Y + connect \$7 $or$libresoc.v:187558$12507_Y + connect \$80 $ternary$libresoc.v:187559$12508_Y + connect \$82 $ternary$libresoc.v:187560$12509_Y + connect \$84 $ternary$libresoc.v:187561$12510_Y + connect \$86 $ternary$libresoc.v:187562$12511_Y + connect \$88 $ternary$libresoc.v:187563$12512_Y + connect \$4 $reduce_and$libresoc.v:187564$12513_Y + connect \$90 $and$libresoc.v:187565$12514_Y + connect \$92 $and$libresoc.v:187566$12515_Y + connect \$94 $and$libresoc.v:187567$12516_Y + connect \$96 $not$libresoc.v:187568$12517_Y + connect \$98 $and$libresoc.v:187569$12518_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -391204,48 +388014,48 @@ module \shiftrot0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:188088.1-188268.10" +attribute \src "libresoc.v:188087.1-188267.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.spr" attribute \generator "nMigen" module \spr - attribute \src "libresoc.v:188240.3-188243.6" - wire width 7 $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 - attribute \src "libresoc.v:188240.3-188243.6" - wire width 64 $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 - attribute \src "libresoc.v:188240.3-188243.6" - wire width 64 $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 - attribute \src "libresoc.v:188240.3-188243.6" + attribute \src "libresoc.v:188239.3-188242.6" + wire width 7 $0$memwr$\memory$libresoc.v:188241$12842_ADDR[6:0]$12845 + attribute \src "libresoc.v:188239.3-188242.6" + wire width 64 $0$memwr$\memory$libresoc.v:188241$12842_DATA[63:0]$12846 + attribute \src "libresoc.v:188239.3-188242.6" + wire width 64 $0$memwr$\memory$libresoc.v:188241$12842_EN[63:0]$12847 + attribute \src "libresoc.v:188239.3-188242.6" wire width 7 $0\_0_[6:0] - attribute \src "libresoc.v:188089.7-188089.20" + attribute \src "libresoc.v:188088.7-188088.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188245.3-188253.6" + attribute \src "libresoc.v:188244.3-188252.6" wire $0\ren_delay$next[0:0]$12850 - attribute \src "libresoc.v:188121.3-188122.35" + attribute \src "libresoc.v:188120.3-188121.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:188254.3-188263.6" + attribute \src "libresoc.v:188253.3-188262.6" wire width 64 $0\spr1__data_o[63:0] - attribute \src "libresoc.v:188245.3-188253.6" + attribute \src "libresoc.v:188244.3-188252.6" wire $1\ren_delay$next[0:0]$12851 - attribute \src "libresoc.v:188105.7-188105.23" + attribute \src "libresoc.v:188104.7-188104.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:188254.3-188263.6" + attribute \src "libresoc.v:188253.3-188262.6" wire width 64 $1\spr1__data_o[63:0] - attribute \src "libresoc.v:188244.26-188244.32" - wire width 64 $memrd$\memory$libresoc.v:188244$12848_DATA + attribute \src "libresoc.v:188243.26-188243.32" + wire width 64 $memrd$\memory$libresoc.v:188243$12848_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 7 $memwr$\memory$libresoc.v:188242$12842_ADDR + wire width 7 $memwr$\memory$libresoc.v:188241$12842_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:188242$12842_DATA + wire width 64 $memwr$\memory$libresoc.v:188241$12842_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:188242$12842_EN - attribute \src "libresoc.v:188239.13-188239.16" + wire width 64 $memwr$\memory$libresoc.v:188241$12842_EN + attribute \src "libresoc.v:188238.13-188238.16" wire width 7 \_0_ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 8 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:188089.7-188089.15" + attribute \src "libresoc.v:188088.7-188088.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 7 \memory_r_addr @@ -391273,7 +388083,7 @@ module \spr wire input 4 \spr1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 7 \spr1__wen - attribute \src "libresoc.v:188123.14-188123.20" + attribute \src "libresoc.v:188122.14-188122.20" memory width 64 size 113 \memory attribute \src "libresoc.v:0.0-0.0" cell $meminit $meminit$\memory$libresoc.v:0$12853 @@ -392405,8 +389215,8 @@ module \spr connect \ADDR 112 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:188244.26-188244.32" - cell $memrd $memrd$\memory$libresoc.v:188244$12848 + attribute \src "libresoc.v:188243.26-188243.32" + cell $memrd $memrd$\memory$libresoc.v:188243$12848 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -392415,7 +389225,7 @@ module \spr parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:188244$12848_DATA + connect \DATA $memrd$\memory$libresoc.v:188243$12848_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" @@ -392426,72 +389236,72 @@ module \spr parameter \MEMID "\\memory" parameter \PRIORITY 12966 parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:188242$12842_ADDR + connect \ADDR $memwr$\memory$libresoc.v:188241$12842_ADDR connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:188242$12842_DATA - connect \EN $memwr$\memory$libresoc.v:188242$12842_EN + connect \DATA $memwr$\memory$libresoc.v:188241$12842_DATA + connect \EN $memwr$\memory$libresoc.v:188241$12842_EN end attribute \src "libresoc.v:0.0-0.0" process $proc$libresoc.v:0$12969 sync always sync init end - attribute \src "libresoc.v:188089.7-188089.20" - process $proc$libresoc.v:188089$12967 + attribute \src "libresoc.v:188088.7-188088.20" + process $proc$libresoc.v:188088$12967 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188105.7-188105.23" - process $proc$libresoc.v:188105$12968 + attribute \src "libresoc.v:188104.7-188104.23" + process $proc$libresoc.v:188104$12968 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:188121.3-188122.35" - process $proc$libresoc.v:188121$12843 + attribute \src "libresoc.v:188120.3-188121.35" + process $proc$libresoc.v:188120$12843 assign { } { } assign $0\ren_delay[0:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:188240.3-188243.6" - process $proc$libresoc.v:188240$12844 + attribute \src "libresoc.v:188239.3-188242.6" + process $proc$libresoc.v:188239$12844 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 7'xxxxxxx - assign $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:188241$12842_ADDR[6:0]$12845 7'xxxxxxx + assign $0$memwr$\memory$libresoc.v:188241$12842_DATA[63:0]$12846 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:188241$12842_EN[63:0]$12847 64'0000000000000000000000000000000000000000000000000000000000000000 assign $0\_0_[6:0] \spr1__addr - attribute \src "libresoc.v:188242.5-188242.59" + attribute \src "libresoc.v:188241.5-188241.59" switch \spr1__wen - attribute \src "libresoc.v:188242.9-188242.18" + attribute \src "libresoc.v:188241.9-188241.18" case 1'1 - assign $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 \spr1__addr$1 - assign $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 \spr1__data_i - assign $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 64'1111111111111111111111111111111111111111111111111111111111111111 + assign $0$memwr$\memory$libresoc.v:188241$12842_ADDR[6:0]$12845 \spr1__addr$1 + assign $0$memwr$\memory$libresoc.v:188241$12842_DATA[63:0]$12846 \spr1__data_i + assign $0$memwr$\memory$libresoc.v:188241$12842_EN[63:0]$12847 64'1111111111111111111111111111111111111111111111111111111111111111 case end sync posedge \coresync_clk update \_0_ $0\_0_[6:0] - update $memwr$\memory$libresoc.v:188242$12842_ADDR $0$memwr$\memory$libresoc.v:188242$12842_ADDR[6:0]$12845 - update $memwr$\memory$libresoc.v:188242$12842_DATA $0$memwr$\memory$libresoc.v:188242$12842_DATA[63:0]$12846 - update $memwr$\memory$libresoc.v:188242$12842_EN $0$memwr$\memory$libresoc.v:188242$12842_EN[63:0]$12847 + update $memwr$\memory$libresoc.v:188241$12842_ADDR $0$memwr$\memory$libresoc.v:188241$12842_ADDR[6:0]$12845 + update $memwr$\memory$libresoc.v:188241$12842_DATA $0$memwr$\memory$libresoc.v:188241$12842_DATA[63:0]$12846 + update $memwr$\memory$libresoc.v:188241$12842_EN $0$memwr$\memory$libresoc.v:188241$12842_EN[63:0]$12847 end - attribute \src "libresoc.v:188245.3-188253.6" - process $proc$libresoc.v:188245$12849 + attribute \src "libresoc.v:188244.3-188252.6" + process $proc$libresoc.v:188244$12849 assign { } { } assign { } { } assign $0\ren_delay$next[0:0]$12850 $1\ren_delay$next[0:0]$12851 - attribute \src "libresoc.v:188246.5-188246.29" + attribute \src "libresoc.v:188245.5-188245.29" switch \initial - attribute \src "libresoc.v:188246.9-188246.17" + attribute \src "libresoc.v:188245.9-188245.17" case 1'1 case end @@ -392507,14 +389317,14 @@ module \spr sync always update \ren_delay$next $0\ren_delay$next[0:0]$12850 end - attribute \src "libresoc.v:188254.3-188263.6" - process $proc$libresoc.v:188254$12852 + attribute \src "libresoc.v:188253.3-188262.6" + process $proc$libresoc.v:188253$12852 assign { } { } assign { } { } assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] - attribute \src "libresoc.v:188255.5-188255.29" + attribute \src "libresoc.v:188254.5-188254.29" switch \initial - attribute \src "libresoc.v:188255.9-188255.17" + attribute \src "libresoc.v:188254.9-188254.17" case 1'1 case end @@ -392530,503 +389340,503 @@ module \spr sync always update \spr1__data_o $0\spr1__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:188244$12848_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:188243$12848_DATA connect \memory_w_data \spr1__data_i connect \memory_w_en \spr1__wen connect \memory_w_addr \spr1__addr$1 connect \memory_r_addr \spr1__addr end -attribute \src "libresoc.v:188272.1-189525.10" +attribute \src "libresoc.v:188271.1-189524.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0" attribute \generator "nMigen" module \spr0 - attribute \src "libresoc.v:189022.3-189023.25" + attribute \src "libresoc.v:189021.3-189022.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:189020.3-189021.40" + attribute \src "libresoc.v:189019.3-189020.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:189416.3-189424.6" + attribute \src "libresoc.v:189415.3-189423.6" wire $0\alu_l_r_alu$next[0:0]$13183 - attribute \src "libresoc.v:188950.3-188951.39" + attribute \src "libresoc.v:188949.3-188950.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:189202.3-189214.6" + attribute \src "libresoc.v:189201.3-189213.6" wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$13105 - attribute \src "libresoc.v:188992.3-188993.65" + attribute \src "libresoc.v:188991.3-188992.65" wire width 14 $0\alu_spr0_spr_op__fn_unit[13:0] - attribute \src "libresoc.v:189202.3-189214.6" + attribute \src "libresoc.v:189201.3-189213.6" wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$13106 - attribute \src "libresoc.v:188994.3-188995.59" + attribute \src "libresoc.v:188993.3-188994.59" wire width 32 $0\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:189202.3-189214.6" + attribute \src "libresoc.v:189201.3-189213.6" wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 - attribute \src "libresoc.v:188990.3-188991.69" + attribute \src "libresoc.v:188989.3-188990.69" wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:189202.3-189214.6" + attribute \src "libresoc.v:189201.3-189213.6" wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 - attribute \src "libresoc.v:188996.3-188997.67" + attribute \src "libresoc.v:188995.3-188996.67" wire $0\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:189407.3-189415.6" + attribute \src "libresoc.v:189406.3-189414.6" wire $0\alui_l_r_alui$next[0:0]$13180 - attribute \src "libresoc.v:188952.3-188953.43" + attribute \src "libresoc.v:188951.3-188952.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:189215.3-189236.6" + attribute \src "libresoc.v:189214.3-189235.6" wire width 64 $0\data_r0__o$next[63:0]$13114 - attribute \src "libresoc.v:188986.3-188987.37" + attribute \src "libresoc.v:188985.3-188986.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:189215.3-189236.6" + attribute \src "libresoc.v:189214.3-189235.6" wire $0\data_r0__o_ok$next[0:0]$13115 - attribute \src "libresoc.v:188988.3-188989.43" + attribute \src "libresoc.v:188987.3-188988.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:189237.3-189258.6" + attribute \src "libresoc.v:189236.3-189257.6" wire width 64 $0\data_r1__spr1$next[63:0]$13122 - attribute \src "libresoc.v:188982.3-188983.43" + attribute \src "libresoc.v:188981.3-188982.43" wire width 64 $0\data_r1__spr1[63:0] - attribute \src "libresoc.v:189237.3-189258.6" + attribute \src "libresoc.v:189236.3-189257.6" wire $0\data_r1__spr1_ok$next[0:0]$13123 - attribute \src "libresoc.v:188984.3-188985.49" + attribute \src "libresoc.v:188983.3-188984.49" wire $0\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:189259.3-189280.6" + attribute \src "libresoc.v:189258.3-189279.6" wire width 64 $0\data_r2__fast1$next[63:0]$13130 - attribute \src "libresoc.v:188978.3-188979.45" + attribute \src "libresoc.v:188977.3-188978.45" wire width 64 $0\data_r2__fast1[63:0] - attribute \src "libresoc.v:189259.3-189280.6" + attribute \src "libresoc.v:189258.3-189279.6" wire $0\data_r2__fast1_ok$next[0:0]$13131 - attribute \src "libresoc.v:188980.3-188981.51" + attribute \src "libresoc.v:188979.3-188980.51" wire $0\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:189281.3-189302.6" + attribute \src "libresoc.v:189280.3-189301.6" wire $0\data_r3__xer_so$next[0:0]$13138 - attribute \src "libresoc.v:188974.3-188975.47" + attribute \src "libresoc.v:188973.3-188974.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:189281.3-189302.6" + attribute \src "libresoc.v:189280.3-189301.6" wire $0\data_r3__xer_so_ok$next[0:0]$13139 - attribute \src "libresoc.v:188976.3-188977.53" + attribute \src "libresoc.v:188975.3-188976.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:189303.3-189324.6" + attribute \src "libresoc.v:189302.3-189323.6" wire width 2 $0\data_r4__xer_ov$next[1:0]$13146 - attribute \src "libresoc.v:188970.3-188971.47" + attribute \src "libresoc.v:188969.3-188970.47" wire width 2 $0\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:189303.3-189324.6" + attribute \src "libresoc.v:189302.3-189323.6" wire $0\data_r4__xer_ov_ok$next[0:0]$13147 - attribute \src "libresoc.v:188972.3-188973.53" + attribute \src "libresoc.v:188971.3-188972.53" wire $0\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:189325.3-189346.6" + attribute \src "libresoc.v:189324.3-189345.6" wire width 2 $0\data_r5__xer_ca$next[1:0]$13154 - attribute \src "libresoc.v:188966.3-188967.47" + attribute \src "libresoc.v:188965.3-188966.47" wire width 2 $0\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:189325.3-189346.6" + attribute \src "libresoc.v:189324.3-189345.6" wire $0\data_r5__xer_ca_ok$next[0:0]$13155 - attribute \src "libresoc.v:188968.3-188969.53" + attribute \src "libresoc.v:188967.3-188968.53" wire $0\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:189425.3-189434.6" + attribute \src "libresoc.v:189424.3-189433.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:189435.3-189444.6" + attribute \src "libresoc.v:189434.3-189443.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:189445.3-189454.6" + attribute \src "libresoc.v:189444.3-189453.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:189455.3-189464.6" + attribute \src "libresoc.v:189454.3-189463.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:189465.3-189474.6" + attribute \src "libresoc.v:189464.3-189473.6" wire width 2 $0\dest5_o[1:0] - attribute \src "libresoc.v:189475.3-189484.6" + attribute \src "libresoc.v:189474.3-189483.6" wire width 2 $0\dest6_o[1:0] - attribute \src "libresoc.v:188273.7-188273.20" + attribute \src "libresoc.v:188272.7-188272.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189157.3-189165.6" + attribute \src "libresoc.v:189156.3-189164.6" wire $0\opc_l_r_opc$next[0:0]$13090 - attribute \src "libresoc.v:189006.3-189007.39" + attribute \src "libresoc.v:189005.3-189006.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:189148.3-189156.6" + attribute \src "libresoc.v:189147.3-189155.6" wire $0\opc_l_s_opc$next[0:0]$13087 - attribute \src "libresoc.v:189008.3-189009.39" + attribute \src "libresoc.v:189007.3-189008.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:189485.3-189493.6" + attribute \src "libresoc.v:189484.3-189492.6" wire width 6 $0\prev_wr_go$next[5:0]$13192 - attribute \src "libresoc.v:189018.3-189019.37" + attribute \src "libresoc.v:189017.3-189018.37" wire width 6 $0\prev_wr_go[5:0] - attribute \src "libresoc.v:189102.3-189111.6" + attribute \src "libresoc.v:189101.3-189110.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:189193.3-189201.6" + attribute \src "libresoc.v:189192.3-189200.6" wire width 6 $0\req_l_r_req$next[5:0]$13102 - attribute \src "libresoc.v:188998.3-188999.39" + attribute \src "libresoc.v:188997.3-188998.39" wire width 6 $0\req_l_r_req[5:0] - attribute \src "libresoc.v:189184.3-189192.6" + attribute \src "libresoc.v:189183.3-189191.6" wire width 6 $0\req_l_s_req$next[5:0]$13099 - attribute \src "libresoc.v:189000.3-189001.39" + attribute \src "libresoc.v:188999.3-189000.39" wire width 6 $0\req_l_s_req[5:0] - attribute \src "libresoc.v:189121.3-189129.6" + attribute \src "libresoc.v:189120.3-189128.6" wire $0\rok_l_r_rdok$next[0:0]$13078 - attribute \src "libresoc.v:189014.3-189015.41" + attribute \src "libresoc.v:189013.3-189014.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:189112.3-189120.6" + attribute \src "libresoc.v:189111.3-189119.6" wire $0\rok_l_s_rdok$next[0:0]$13075 - attribute \src "libresoc.v:189016.3-189017.41" + attribute \src "libresoc.v:189015.3-189016.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:189139.3-189147.6" + attribute \src "libresoc.v:189138.3-189146.6" wire $0\rst_l_r_rst$next[0:0]$13084 - attribute \src "libresoc.v:189010.3-189011.39" + attribute \src "libresoc.v:189009.3-189010.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:189130.3-189138.6" + attribute \src "libresoc.v:189129.3-189137.6" wire $0\rst_l_s_rst$next[0:0]$13081 - attribute \src "libresoc.v:189012.3-189013.39" + attribute \src "libresoc.v:189011.3-189012.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:189175.3-189183.6" + attribute \src "libresoc.v:189174.3-189182.6" wire width 6 $0\src_l_r_src$next[5:0]$13096 - attribute \src "libresoc.v:189002.3-189003.39" + attribute \src "libresoc.v:189001.3-189002.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:189166.3-189174.6" + attribute \src "libresoc.v:189165.3-189173.6" wire width 6 $0\src_l_s_src$next[5:0]$13093 - attribute \src "libresoc.v:189004.3-189005.39" + attribute \src "libresoc.v:189003.3-189004.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:189347.3-189356.6" + attribute \src "libresoc.v:189346.3-189355.6" wire width 64 $0\src_r0$next[63:0]$13162 - attribute \src "libresoc.v:188964.3-188965.29" + attribute \src "libresoc.v:188963.3-188964.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:189357.3-189366.6" + attribute \src "libresoc.v:189356.3-189365.6" wire width 64 $0\src_r1$next[63:0]$13165 - attribute \src "libresoc.v:188962.3-188963.29" + attribute \src "libresoc.v:188961.3-188962.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:189367.3-189376.6" + attribute \src "libresoc.v:189366.3-189375.6" wire width 64 $0\src_r2$next[63:0]$13168 - attribute \src "libresoc.v:188960.3-188961.29" + attribute \src "libresoc.v:188959.3-188960.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:189377.3-189386.6" + attribute \src "libresoc.v:189376.3-189385.6" wire $0\src_r3$next[0:0]$13171 - attribute \src "libresoc.v:188958.3-188959.29" + attribute \src "libresoc.v:188957.3-188958.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:189387.3-189396.6" + attribute \src "libresoc.v:189386.3-189395.6" wire width 2 $0\src_r4$next[1:0]$13174 - attribute \src "libresoc.v:188956.3-188957.29" + attribute \src "libresoc.v:188955.3-188956.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:189397.3-189406.6" + attribute \src "libresoc.v:189396.3-189405.6" wire width 2 $0\src_r5$next[1:0]$13177 - attribute \src "libresoc.v:188954.3-188955.29" + attribute \src "libresoc.v:188953.3-188954.29" wire width 2 $0\src_r5[1:0] - attribute \src "libresoc.v:188409.7-188409.24" + attribute \src "libresoc.v:188408.7-188408.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:188419.7-188419.26" + attribute \src "libresoc.v:188418.7-188418.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:189416.3-189424.6" + attribute \src "libresoc.v:189415.3-189423.6" wire $1\alu_l_r_alu$next[0:0]$13184 - attribute \src "libresoc.v:188427.7-188427.25" + attribute \src "libresoc.v:188426.7-188426.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:189202.3-189214.6" + attribute \src "libresoc.v:189201.3-189213.6" wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 - attribute \src "libresoc.v:188472.14-188472.49" + attribute \src "libresoc.v:188471.14-188471.49" wire width 14 $1\alu_spr0_spr_op__fn_unit[13:0] - attribute \src "libresoc.v:189202.3-189214.6" + attribute \src "libresoc.v:189201.3-189213.6" wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$13110 - attribute \src "libresoc.v:188476.14-188476.43" + attribute \src "libresoc.v:188475.14-188475.43" wire width 32 $1\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:189202.3-189214.6" + attribute \src "libresoc.v:189201.3-189213.6" wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 - attribute \src "libresoc.v:188555.13-188555.47" + attribute \src "libresoc.v:188554.13-188554.47" wire width 7 $1\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:189202.3-189214.6" + attribute \src "libresoc.v:189201.3-189213.6" wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 - attribute \src "libresoc.v:188559.7-188559.39" + attribute \src "libresoc.v:188558.7-188558.39" wire $1\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:189407.3-189415.6" + attribute \src "libresoc.v:189406.3-189414.6" wire $1\alui_l_r_alui$next[0:0]$13181 - attribute \src "libresoc.v:188577.7-188577.27" + attribute \src "libresoc.v:188576.7-188576.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:189215.3-189236.6" + attribute \src "libresoc.v:189214.3-189235.6" wire width 64 $1\data_r0__o$next[63:0]$13116 - attribute \src "libresoc.v:188609.14-188609.47" + attribute \src "libresoc.v:188608.14-188608.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:189215.3-189236.6" + attribute \src "libresoc.v:189214.3-189235.6" wire $1\data_r0__o_ok$next[0:0]$13117 - attribute \src "libresoc.v:188613.7-188613.27" + attribute \src "libresoc.v:188612.7-188612.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:189237.3-189258.6" + attribute \src "libresoc.v:189236.3-189257.6" wire width 64 $1\data_r1__spr1$next[63:0]$13124 - attribute \src "libresoc.v:188617.14-188617.50" + attribute \src "libresoc.v:188616.14-188616.50" wire width 64 $1\data_r1__spr1[63:0] - attribute \src "libresoc.v:189237.3-189258.6" + attribute \src "libresoc.v:189236.3-189257.6" wire $1\data_r1__spr1_ok$next[0:0]$13125 - attribute \src "libresoc.v:188621.7-188621.30" + attribute \src "libresoc.v:188620.7-188620.30" wire $1\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:189259.3-189280.6" + attribute \src "libresoc.v:189258.3-189279.6" wire width 64 $1\data_r2__fast1$next[63:0]$13132 - attribute \src "libresoc.v:188625.14-188625.51" + attribute \src "libresoc.v:188624.14-188624.51" wire width 64 $1\data_r2__fast1[63:0] - attribute \src "libresoc.v:189259.3-189280.6" + attribute \src "libresoc.v:189258.3-189279.6" wire $1\data_r2__fast1_ok$next[0:0]$13133 - attribute \src "libresoc.v:188629.7-188629.31" + attribute \src "libresoc.v:188628.7-188628.31" wire $1\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:189281.3-189302.6" + attribute \src "libresoc.v:189280.3-189301.6" wire $1\data_r3__xer_so$next[0:0]$13140 - attribute \src "libresoc.v:188633.7-188633.29" + attribute \src "libresoc.v:188632.7-188632.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:189281.3-189302.6" + attribute \src "libresoc.v:189280.3-189301.6" wire $1\data_r3__xer_so_ok$next[0:0]$13141 - attribute \src "libresoc.v:188637.7-188637.32" + attribute \src "libresoc.v:188636.7-188636.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:189303.3-189324.6" + attribute \src "libresoc.v:189302.3-189323.6" wire width 2 $1\data_r4__xer_ov$next[1:0]$13148 - attribute \src "libresoc.v:188641.13-188641.35" + attribute \src "libresoc.v:188640.13-188640.35" wire width 2 $1\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:189303.3-189324.6" + attribute \src "libresoc.v:189302.3-189323.6" wire $1\data_r4__xer_ov_ok$next[0:0]$13149 - attribute \src "libresoc.v:188645.7-188645.32" + attribute \src "libresoc.v:188644.7-188644.32" wire $1\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:189325.3-189346.6" + attribute \src "libresoc.v:189324.3-189345.6" wire width 2 $1\data_r5__xer_ca$next[1:0]$13156 - attribute \src "libresoc.v:188649.13-188649.35" + attribute \src "libresoc.v:188648.13-188648.35" wire width 2 $1\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:189325.3-189346.6" + attribute \src "libresoc.v:189324.3-189345.6" wire $1\data_r5__xer_ca_ok$next[0:0]$13157 - attribute \src "libresoc.v:188653.7-188653.32" + attribute \src "libresoc.v:188652.7-188652.32" wire $1\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:189425.3-189434.6" + attribute \src "libresoc.v:189424.3-189433.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:189435.3-189444.6" + attribute \src "libresoc.v:189434.3-189443.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:189445.3-189454.6" + attribute \src "libresoc.v:189444.3-189453.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:189455.3-189464.6" + attribute \src "libresoc.v:189454.3-189463.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:189465.3-189474.6" + attribute \src "libresoc.v:189464.3-189473.6" wire width 2 $1\dest5_o[1:0] - attribute \src "libresoc.v:189475.3-189484.6" + attribute \src "libresoc.v:189474.3-189483.6" wire width 2 $1\dest6_o[1:0] - attribute \src "libresoc.v:189157.3-189165.6" + attribute \src "libresoc.v:189156.3-189164.6" wire $1\opc_l_r_opc$next[0:0]$13091 - attribute \src "libresoc.v:188681.7-188681.25" + attribute \src "libresoc.v:188680.7-188680.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:189148.3-189156.6" + attribute \src "libresoc.v:189147.3-189155.6" wire $1\opc_l_s_opc$next[0:0]$13088 - attribute \src "libresoc.v:188685.7-188685.25" + attribute \src "libresoc.v:188684.7-188684.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:189485.3-189493.6" + attribute \src "libresoc.v:189484.3-189492.6" wire width 6 $1\prev_wr_go$next[5:0]$13193 - attribute \src "libresoc.v:188787.13-188787.31" + attribute \src "libresoc.v:188786.13-188786.31" wire width 6 $1\prev_wr_go[5:0] - attribute \src "libresoc.v:189102.3-189111.6" + attribute \src "libresoc.v:189101.3-189110.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:189193.3-189201.6" + attribute \src "libresoc.v:189192.3-189200.6" wire width 6 $1\req_l_r_req$next[5:0]$13103 - attribute \src "libresoc.v:188795.13-188795.32" + attribute \src "libresoc.v:188794.13-188794.32" wire width 6 $1\req_l_r_req[5:0] - attribute \src "libresoc.v:189184.3-189192.6" + attribute \src "libresoc.v:189183.3-189191.6" wire width 6 $1\req_l_s_req$next[5:0]$13100 - attribute \src "libresoc.v:188799.13-188799.32" + attribute \src "libresoc.v:188798.13-188798.32" wire width 6 $1\req_l_s_req[5:0] - attribute \src "libresoc.v:189121.3-189129.6" + attribute \src "libresoc.v:189120.3-189128.6" wire $1\rok_l_r_rdok$next[0:0]$13079 - attribute \src "libresoc.v:188811.7-188811.26" + attribute \src "libresoc.v:188810.7-188810.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:189112.3-189120.6" + attribute \src "libresoc.v:189111.3-189119.6" wire $1\rok_l_s_rdok$next[0:0]$13076 - attribute \src "libresoc.v:188815.7-188815.26" + attribute \src "libresoc.v:188814.7-188814.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:189139.3-189147.6" + attribute \src "libresoc.v:189138.3-189146.6" wire $1\rst_l_r_rst$next[0:0]$13085 - attribute \src "libresoc.v:188819.7-188819.25" + attribute \src "libresoc.v:188818.7-188818.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:189130.3-189138.6" + attribute \src "libresoc.v:189129.3-189137.6" wire $1\rst_l_s_rst$next[0:0]$13082 - attribute \src "libresoc.v:188823.7-188823.25" + attribute \src "libresoc.v:188822.7-188822.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:189175.3-189183.6" + attribute \src "libresoc.v:189174.3-189182.6" wire width 6 $1\src_l_r_src$next[5:0]$13097 - attribute \src "libresoc.v:188845.13-188845.32" + attribute \src "libresoc.v:188844.13-188844.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:189166.3-189174.6" + attribute \src "libresoc.v:189165.3-189173.6" wire width 6 $1\src_l_s_src$next[5:0]$13094 - attribute \src "libresoc.v:188849.13-188849.32" + attribute \src "libresoc.v:188848.13-188848.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:189347.3-189356.6" + attribute \src "libresoc.v:189346.3-189355.6" wire width 64 $1\src_r0$next[63:0]$13163 - attribute \src "libresoc.v:188853.14-188853.43" + attribute \src "libresoc.v:188852.14-188852.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:189357.3-189366.6" + attribute \src "libresoc.v:189356.3-189365.6" wire width 64 $1\src_r1$next[63:0]$13166 - attribute \src "libresoc.v:188857.14-188857.43" + attribute \src "libresoc.v:188856.14-188856.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:189367.3-189376.6" + attribute \src "libresoc.v:189366.3-189375.6" wire width 64 $1\src_r2$next[63:0]$13169 - attribute \src "libresoc.v:188861.14-188861.43" + attribute \src "libresoc.v:188860.14-188860.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:189377.3-189386.6" + attribute \src "libresoc.v:189376.3-189385.6" wire $1\src_r3$next[0:0]$13172 - attribute \src "libresoc.v:188865.7-188865.20" + attribute \src "libresoc.v:188864.7-188864.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:189387.3-189396.6" + attribute \src "libresoc.v:189386.3-189395.6" wire width 2 $1\src_r4$next[1:0]$13175 - attribute \src "libresoc.v:188869.13-188869.26" + attribute \src "libresoc.v:188868.13-188868.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:189397.3-189406.6" + attribute \src "libresoc.v:189396.3-189405.6" wire width 2 $1\src_r5$next[1:0]$13178 - attribute \src "libresoc.v:188873.13-188873.26" + attribute \src "libresoc.v:188872.13-188872.26" wire width 2 $1\src_r5[1:0] - attribute \src "libresoc.v:189215.3-189236.6" + attribute \src "libresoc.v:189214.3-189235.6" wire width 64 $2\data_r0__o$next[63:0]$13118 - attribute \src "libresoc.v:189215.3-189236.6" + attribute \src "libresoc.v:189214.3-189235.6" wire $2\data_r0__o_ok$next[0:0]$13119 - attribute \src "libresoc.v:189237.3-189258.6" + attribute \src "libresoc.v:189236.3-189257.6" wire width 64 $2\data_r1__spr1$next[63:0]$13126 - attribute \src "libresoc.v:189237.3-189258.6" + attribute \src "libresoc.v:189236.3-189257.6" wire $2\data_r1__spr1_ok$next[0:0]$13127 - attribute \src "libresoc.v:189259.3-189280.6" + attribute \src "libresoc.v:189258.3-189279.6" wire width 64 $2\data_r2__fast1$next[63:0]$13134 - attribute \src "libresoc.v:189259.3-189280.6" + attribute \src "libresoc.v:189258.3-189279.6" wire $2\data_r2__fast1_ok$next[0:0]$13135 - attribute \src "libresoc.v:189281.3-189302.6" + attribute \src "libresoc.v:189280.3-189301.6" wire $2\data_r3__xer_so$next[0:0]$13142 - attribute \src "libresoc.v:189281.3-189302.6" + attribute \src "libresoc.v:189280.3-189301.6" wire $2\data_r3__xer_so_ok$next[0:0]$13143 - attribute \src "libresoc.v:189303.3-189324.6" + attribute \src "libresoc.v:189302.3-189323.6" wire width 2 $2\data_r4__xer_ov$next[1:0]$13150 - attribute \src "libresoc.v:189303.3-189324.6" + attribute \src "libresoc.v:189302.3-189323.6" wire $2\data_r4__xer_ov_ok$next[0:0]$13151 - attribute \src "libresoc.v:189325.3-189346.6" + attribute \src "libresoc.v:189324.3-189345.6" wire width 2 $2\data_r5__xer_ca$next[1:0]$13158 - attribute \src "libresoc.v:189325.3-189346.6" + attribute \src "libresoc.v:189324.3-189345.6" wire $2\data_r5__xer_ca_ok$next[0:0]$13159 - attribute \src "libresoc.v:189215.3-189236.6" + attribute \src "libresoc.v:189214.3-189235.6" wire $3\data_r0__o_ok$next[0:0]$13120 - attribute \src "libresoc.v:189237.3-189258.6" + attribute \src "libresoc.v:189236.3-189257.6" wire $3\data_r1__spr1_ok$next[0:0]$13128 - attribute \src "libresoc.v:189259.3-189280.6" + attribute \src "libresoc.v:189258.3-189279.6" wire $3\data_r2__fast1_ok$next[0:0]$13136 - attribute \src "libresoc.v:189281.3-189302.6" + attribute \src "libresoc.v:189280.3-189301.6" wire $3\data_r3__xer_so_ok$next[0:0]$13144 - attribute \src "libresoc.v:189303.3-189324.6" + attribute \src "libresoc.v:189302.3-189323.6" wire $3\data_r4__xer_ov_ok$next[0:0]$13152 - attribute \src "libresoc.v:189325.3-189346.6" + attribute \src "libresoc.v:189324.3-189345.6" wire $3\data_r5__xer_ca_ok$next[0:0]$13160 - attribute \src "libresoc.v:188885.19-188885.133" - wire $and$libresoc.v:188885$12971_Y - attribute \src "libresoc.v:188886.19-188886.183" - wire width 6 $and$libresoc.v:188886$12972_Y - attribute \src "libresoc.v:188887.19-188887.115" - wire width 6 $and$libresoc.v:188887$12973_Y - attribute \src "libresoc.v:188889.19-188889.115" - wire width 6 $and$libresoc.v:188889$12975_Y + attribute \src "libresoc.v:188884.19-188884.133" + wire $and$libresoc.v:188884$12971_Y + attribute \src "libresoc.v:188885.19-188885.183" + wire width 6 $and$libresoc.v:188885$12972_Y + attribute \src "libresoc.v:188886.19-188886.115" + wire width 6 $and$libresoc.v:188886$12973_Y + attribute \src "libresoc.v:188888.19-188888.115" + wire width 6 $and$libresoc.v:188888$12975_Y + attribute \src "libresoc.v:188889.19-188889.125" + wire $and$libresoc.v:188889$12976_Y attribute \src "libresoc.v:188890.19-188890.125" - wire $and$libresoc.v:188890$12976_Y + wire $and$libresoc.v:188890$12977_Y attribute \src "libresoc.v:188891.19-188891.125" - wire $and$libresoc.v:188891$12977_Y + wire $and$libresoc.v:188891$12978_Y attribute \src "libresoc.v:188892.19-188892.125" - wire $and$libresoc.v:188892$12978_Y + wire $and$libresoc.v:188892$12979_Y attribute \src "libresoc.v:188893.19-188893.125" - wire $and$libresoc.v:188893$12979_Y - attribute \src "libresoc.v:188894.19-188894.125" - wire $and$libresoc.v:188894$12980_Y - attribute \src "libresoc.v:188896.19-188896.125" - wire $and$libresoc.v:188896$12982_Y - attribute \src "libresoc.v:188897.19-188897.165" - wire width 6 $and$libresoc.v:188897$12983_Y - attribute \src "libresoc.v:188898.19-188898.121" - wire width 6 $and$libresoc.v:188898$12984_Y + wire $and$libresoc.v:188893$12980_Y + attribute \src "libresoc.v:188895.19-188895.125" + wire $and$libresoc.v:188895$12982_Y + attribute \src "libresoc.v:188896.19-188896.165" + wire width 6 $and$libresoc.v:188896$12983_Y + attribute \src "libresoc.v:188897.19-188897.121" + wire width 6 $and$libresoc.v:188897$12984_Y + attribute \src "libresoc.v:188898.19-188898.127" + wire $and$libresoc.v:188898$12985_Y attribute \src "libresoc.v:188899.19-188899.127" - wire $and$libresoc.v:188899$12985_Y - attribute \src "libresoc.v:188900.19-188900.127" - wire $and$libresoc.v:188900$12986_Y + wire $and$libresoc.v:188899$12986_Y + attribute \src "libresoc.v:188901.19-188901.127" + wire $and$libresoc.v:188901$12988_Y attribute \src "libresoc.v:188902.19-188902.127" - wire $and$libresoc.v:188902$12988_Y + wire $and$libresoc.v:188902$12989_Y attribute \src "libresoc.v:188903.19-188903.127" - wire $and$libresoc.v:188903$12989_Y + wire $and$libresoc.v:188903$12990_Y attribute \src "libresoc.v:188904.19-188904.127" - wire $and$libresoc.v:188904$12990_Y - attribute \src "libresoc.v:188905.19-188905.127" - wire $and$libresoc.v:188905$12991_Y - attribute \src "libresoc.v:188906.18-188906.110" - wire $and$libresoc.v:188906$12992_Y - attribute \src "libresoc.v:188908.18-188908.98" - wire $and$libresoc.v:188908$12994_Y - attribute \src "libresoc.v:188910.18-188910.100" - wire $and$libresoc.v:188910$12996_Y - attribute \src "libresoc.v:188911.18-188911.182" - wire width 6 $and$libresoc.v:188911$12997_Y - attribute \src "libresoc.v:188913.18-188913.119" - wire width 6 $and$libresoc.v:188913$12999_Y - attribute \src "libresoc.v:188916.18-188916.116" - wire $and$libresoc.v:188916$13002_Y - attribute \src "libresoc.v:188921.18-188921.113" - wire $and$libresoc.v:188921$13007_Y - attribute \src "libresoc.v:188922.18-188922.125" - wire width 6 $and$libresoc.v:188922$13008_Y - attribute \src "libresoc.v:188924.18-188924.112" - wire $and$libresoc.v:188924$13010_Y + wire $and$libresoc.v:188904$12991_Y + attribute \src "libresoc.v:188905.18-188905.110" + wire $and$libresoc.v:188905$12992_Y + attribute \src "libresoc.v:188907.18-188907.98" + wire $and$libresoc.v:188907$12994_Y + attribute \src "libresoc.v:188909.18-188909.100" + wire $and$libresoc.v:188909$12996_Y + attribute \src "libresoc.v:188910.18-188910.182" + wire width 6 $and$libresoc.v:188910$12997_Y + attribute \src "libresoc.v:188912.18-188912.119" + wire width 6 $and$libresoc.v:188912$12999_Y + attribute \src "libresoc.v:188915.18-188915.116" + wire $and$libresoc.v:188915$13002_Y + attribute \src "libresoc.v:188920.18-188920.113" + wire $and$libresoc.v:188920$13007_Y + attribute \src "libresoc.v:188921.18-188921.125" + wire width 6 $and$libresoc.v:188921$13008_Y + attribute \src "libresoc.v:188923.18-188923.112" + wire $and$libresoc.v:188923$13010_Y + attribute \src "libresoc.v:188925.18-188925.126" + wire $and$libresoc.v:188925$13012_Y attribute \src "libresoc.v:188926.18-188926.126" - wire $and$libresoc.v:188926$13012_Y - attribute \src "libresoc.v:188927.18-188927.126" - wire $and$libresoc.v:188927$13013_Y - attribute \src "libresoc.v:188928.18-188928.117" - wire $and$libresoc.v:188928$13014_Y - attribute \src "libresoc.v:188933.18-188933.130" - wire $and$libresoc.v:188933$13019_Y - attribute \src "libresoc.v:188934.17-188934.123" - wire $and$libresoc.v:188934$13020_Y - attribute \src "libresoc.v:188935.18-188935.124" - wire width 6 $and$libresoc.v:188935$13021_Y - attribute \src "libresoc.v:188937.18-188937.116" - wire $and$libresoc.v:188937$13023_Y - attribute \src "libresoc.v:188938.18-188938.119" - wire $and$libresoc.v:188938$13024_Y - attribute \src "libresoc.v:188939.18-188939.120" - wire $and$libresoc.v:188939$13025_Y + wire $and$libresoc.v:188926$13013_Y + attribute \src "libresoc.v:188927.18-188927.117" + wire $and$libresoc.v:188927$13014_Y + attribute \src "libresoc.v:188932.18-188932.130" + wire $and$libresoc.v:188932$13019_Y + attribute \src "libresoc.v:188933.17-188933.123" + wire $and$libresoc.v:188933$13020_Y + attribute \src "libresoc.v:188934.18-188934.124" + wire width 6 $and$libresoc.v:188934$13021_Y + attribute \src "libresoc.v:188936.18-188936.116" + wire $and$libresoc.v:188936$13023_Y + attribute \src "libresoc.v:188937.18-188937.119" + wire $and$libresoc.v:188937$13024_Y + attribute \src "libresoc.v:188938.18-188938.120" + wire $and$libresoc.v:188938$13025_Y + attribute \src "libresoc.v:188939.18-188939.121" + wire $and$libresoc.v:188939$13026_Y attribute \src "libresoc.v:188940.18-188940.121" - wire $and$libresoc.v:188940$13026_Y + wire $and$libresoc.v:188940$13027_Y attribute \src "libresoc.v:188941.18-188941.121" - wire $and$libresoc.v:188941$13027_Y - attribute \src "libresoc.v:188942.18-188942.121" - wire $and$libresoc.v:188942$13028_Y - attribute \src "libresoc.v:188949.18-188949.134" - wire $and$libresoc.v:188949$13035_Y - attribute \src "libresoc.v:188923.18-188923.113" - wire $eq$libresoc.v:188923$13009_Y - attribute \src "libresoc.v:188925.18-188925.119" - wire $eq$libresoc.v:188925$13011_Y - attribute \src "libresoc.v:188884.17-188884.113" - wire width 6 $not$libresoc.v:188884$12970_Y - attribute \src "libresoc.v:188888.19-188888.115" - wire width 6 $not$libresoc.v:188888$12974_Y - attribute \src "libresoc.v:188907.18-188907.97" - wire $not$libresoc.v:188907$12993_Y - attribute \src "libresoc.v:188909.18-188909.99" - wire $not$libresoc.v:188909$12995_Y - attribute \src "libresoc.v:188912.18-188912.113" - wire width 6 $not$libresoc.v:188912$12998_Y - attribute \src "libresoc.v:188915.18-188915.106" - wire $not$libresoc.v:188915$13001_Y - attribute \src "libresoc.v:188920.18-188920.120" - wire $not$libresoc.v:188920$13006_Y - attribute \src "libresoc.v:188895.18-188895.118" - wire width 6 $or$libresoc.v:188895$12981_Y - attribute \src "libresoc.v:188919.18-188919.112" - wire $or$libresoc.v:188919$13005_Y - attribute \src "libresoc.v:188929.18-188929.122" - wire $or$libresoc.v:188929$13015_Y - attribute \src "libresoc.v:188930.18-188930.124" - wire $or$libresoc.v:188930$13016_Y - attribute \src "libresoc.v:188931.18-188931.194" - wire width 6 $or$libresoc.v:188931$13017_Y - attribute \src "libresoc.v:188932.18-188932.194" - wire width 6 $or$libresoc.v:188932$13018_Y - attribute \src "libresoc.v:188936.18-188936.120" - wire width 6 $or$libresoc.v:188936$13022_Y - attribute \src "libresoc.v:188901.17-188901.105" - wire $reduce_and$libresoc.v:188901$12987_Y + wire $and$libresoc.v:188941$13028_Y + attribute \src "libresoc.v:188948.18-188948.134" + wire $and$libresoc.v:188948$13035_Y + attribute \src "libresoc.v:188922.18-188922.113" + wire $eq$libresoc.v:188922$13009_Y + attribute \src "libresoc.v:188924.18-188924.119" + wire $eq$libresoc.v:188924$13011_Y + attribute \src "libresoc.v:188883.17-188883.113" + wire width 6 $not$libresoc.v:188883$12970_Y + attribute \src "libresoc.v:188887.19-188887.115" + wire width 6 $not$libresoc.v:188887$12974_Y + attribute \src "libresoc.v:188906.18-188906.97" + wire $not$libresoc.v:188906$12993_Y + attribute \src "libresoc.v:188908.18-188908.99" + wire $not$libresoc.v:188908$12995_Y + attribute \src "libresoc.v:188911.18-188911.113" + wire width 6 $not$libresoc.v:188911$12998_Y attribute \src "libresoc.v:188914.18-188914.106" - wire $reduce_or$libresoc.v:188914$13000_Y - attribute \src "libresoc.v:188917.18-188917.113" - wire $reduce_or$libresoc.v:188917$13003_Y + wire $not$libresoc.v:188914$13001_Y + attribute \src "libresoc.v:188919.18-188919.120" + wire $not$libresoc.v:188919$13006_Y + attribute \src "libresoc.v:188894.18-188894.118" + wire width 6 $or$libresoc.v:188894$12981_Y attribute \src "libresoc.v:188918.18-188918.112" - wire $reduce_or$libresoc.v:188918$13004_Y + wire $or$libresoc.v:188918$13005_Y + attribute \src "libresoc.v:188928.18-188928.122" + wire $or$libresoc.v:188928$13015_Y + attribute \src "libresoc.v:188929.18-188929.124" + wire $or$libresoc.v:188929$13016_Y + attribute \src "libresoc.v:188930.18-188930.194" + wire width 6 $or$libresoc.v:188930$13017_Y + attribute \src "libresoc.v:188931.18-188931.194" + wire width 6 $or$libresoc.v:188931$13018_Y + attribute \src "libresoc.v:188935.18-188935.120" + wire width 6 $or$libresoc.v:188935$13022_Y + attribute \src "libresoc.v:188900.17-188900.105" + wire $reduce_and$libresoc.v:188900$12987_Y + attribute \src "libresoc.v:188913.18-188913.106" + wire $reduce_or$libresoc.v:188913$13000_Y + attribute \src "libresoc.v:188916.18-188916.113" + wire $reduce_or$libresoc.v:188916$13003_Y + attribute \src "libresoc.v:188917.18-188917.112" + wire $reduce_or$libresoc.v:188917$13004_Y + attribute \src "libresoc.v:188942.18-188942.118" + wire width 64 $ternary$libresoc.v:188942$13029_Y attribute \src "libresoc.v:188943.18-188943.118" - wire width 64 $ternary$libresoc.v:188943$13029_Y + wire width 64 $ternary$libresoc.v:188943$13030_Y attribute \src "libresoc.v:188944.18-188944.118" - wire width 64 $ternary$libresoc.v:188944$13030_Y + wire width 64 $ternary$libresoc.v:188944$13031_Y attribute \src "libresoc.v:188945.18-188945.118" - wire width 64 $ternary$libresoc.v:188945$13031_Y + wire $ternary$libresoc.v:188945$13032_Y attribute \src "libresoc.v:188946.18-188946.118" - wire $ternary$libresoc.v:188946$13032_Y + wire width 2 $ternary$libresoc.v:188946$13033_Y attribute \src "libresoc.v:188947.18-188947.118" - wire width 2 $ternary$libresoc.v:188947$13033_Y - attribute \src "libresoc.v:188948.18-188948.118" - wire width 2 $ternary$libresoc.v:188948$13034_Y + wire width 2 $ternary$libresoc.v:188947$13034_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -393423,7 +390233,7 @@ module \spr0 wire width 2 output 22 \dest6_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 27 \fast1_ok - attribute \src "libresoc.v:188273.7-188273.15" + attribute \src "libresoc.v:188272.7-188272.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \o_ok @@ -393634,7 +390444,7 @@ module \spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 25 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:188885$12971 + cell $and $and$libresoc.v:188884$12971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393642,10 +390452,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:188885$12971_Y + connect \Y $and$libresoc.v:188884$12971_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:188886$12972 + cell $and $and$libresoc.v:188885$12972 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393653,10 +390463,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:188886$12972_Y + connect \Y $and$libresoc.v:188885$12972_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:188887$12973 + cell $and $and$libresoc.v:188886$12973 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393664,10 +390474,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$102 connect \B 6'111111 - connect \Y $and$libresoc.v:188887$12973_Y + connect \Y $and$libresoc.v:188886$12973_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:188889$12975 + cell $and $and$libresoc.v:188888$12975 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393675,10 +390485,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:188889$12975_Y + connect \Y $and$libresoc.v:188888$12975_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188890$12976 + cell $and $and$libresoc.v:188889$12976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393686,10 +390496,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188890$12976_Y + connect \Y $and$libresoc.v:188889$12976_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188891$12977 + cell $and $and$libresoc.v:188890$12977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393697,10 +390507,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188891$12977_Y + connect \Y $and$libresoc.v:188890$12977_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188892$12978 + cell $and $and$libresoc.v:188891$12978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393708,10 +390518,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188892$12978_Y + connect \Y $and$libresoc.v:188891$12978_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188893$12979 + cell $and $and$libresoc.v:188892$12979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393719,10 +390529,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188893$12979_Y + connect \Y $and$libresoc.v:188892$12979_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188894$12980 + cell $and $and$libresoc.v:188893$12980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393730,10 +390540,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188894$12980_Y + connect \Y $and$libresoc.v:188893$12980_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188896$12982 + cell $and $and$libresoc.v:188895$12982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393741,10 +390551,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188896$12982_Y + connect \Y $and$libresoc.v:188895$12982_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:188897$12983 + cell $and $and$libresoc.v:188896$12983 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393752,10 +390562,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 \$118 \$120 } - connect \Y $and$libresoc.v:188897$12983_Y + connect \Y $and$libresoc.v:188896$12983_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:188898$12984 + cell $and $and$libresoc.v:188897$12984 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393763,10 +390573,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$122 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:188898$12984_Y + connect \Y $and$libresoc.v:188897$12984_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188899$12985 + cell $and $and$libresoc.v:188898$12985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393774,10 +390584,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188899$12985_Y + connect \Y $and$libresoc.v:188898$12985_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188900$12986 + cell $and $and$libresoc.v:188899$12986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393785,10 +390595,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188900$12986_Y + connect \Y $and$libresoc.v:188899$12986_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188902$12988 + cell $and $and$libresoc.v:188901$12988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393796,10 +390606,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188902$12988_Y + connect \Y $and$libresoc.v:188901$12988_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188903$12989 + cell $and $and$libresoc.v:188902$12989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393807,10 +390617,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188903$12989_Y + connect \Y $and$libresoc.v:188902$12989_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188904$12990 + cell $and $and$libresoc.v:188903$12990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393818,10 +390628,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188904$12990_Y + connect \Y $and$libresoc.v:188903$12990_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188905$12991 + cell $and $and$libresoc.v:188904$12991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393829,10 +390639,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [5] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188905$12991_Y + connect \Y $and$libresoc.v:188904$12991_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:188906$12992 + cell $and $and$libresoc.v:188905$12992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393840,10 +390650,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$6 connect \B \$8 - connect \Y $and$libresoc.v:188906$12992_Y + connect \Y $and$libresoc.v:188905$12992_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:188908$12994 + cell $and $and$libresoc.v:188907$12994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393851,10 +390661,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$16 - connect \Y $and$libresoc.v:188908$12994_Y + connect \Y $and$libresoc.v:188907$12994_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:188910$12996 + cell $and $and$libresoc.v:188909$12996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393862,10 +390672,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$20 - connect \Y $and$libresoc.v:188910$12996_Y + connect \Y $and$libresoc.v:188909$12996_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:188911$12997 + cell $and $and$libresoc.v:188910$12997 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393873,10 +390683,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:188911$12997_Y + connect \Y $and$libresoc.v:188910$12997_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:188913$12999 + cell $and $and$libresoc.v:188912$12999 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393884,10 +390694,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__rel_o connect \B \$28 - connect \Y $and$libresoc.v:188913$12999_Y + connect \Y $and$libresoc.v:188912$12999_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:188916$13002 + cell $and $and$libresoc.v:188915$13002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393895,10 +390705,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$26 - connect \Y $and$libresoc.v:188916$13002_Y + connect \Y $and$libresoc.v:188915$13002_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:188921$13007 + cell $and $and$libresoc.v:188920$13007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393906,10 +390716,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$42 - connect \Y $and$libresoc.v:188921$13007_Y + connect \Y $and$libresoc.v:188920$13007_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:188922$13008 + cell $and $and$libresoc.v:188921$13008 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393917,10 +390727,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:188922$13008_Y + connect \Y $and$libresoc.v:188921$13008_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:188924$13010 + cell $and $and$libresoc.v:188923$13010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393928,10 +390738,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$48 - connect \Y $and$libresoc.v:188924$13010_Y + connect \Y $and$libresoc.v:188923$13010_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:188926$13012 + cell $and $and$libresoc.v:188925$13012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393939,10 +390749,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \alu_spr0_n_ready_i - connect \Y $and$libresoc.v:188926$13012_Y + connect \Y $and$libresoc.v:188925$13012_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:188927$13013 + cell $and $and$libresoc.v:188926$13013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393950,10 +390760,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$54 connect \B \alu_spr0_n_valid_o - connect \Y $and$libresoc.v:188927$13013_Y + connect \Y $and$libresoc.v:188926$13013_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:188928$13014 + cell $and $and$libresoc.v:188927$13014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393961,10 +390771,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$56 connect \B \cu_busy_o - connect \Y $and$libresoc.v:188928$13014_Y + connect \Y $and$libresoc.v:188927$13014_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:188933$13019 + cell $and $and$libresoc.v:188932$13019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393972,10 +390782,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:188933$13019_Y + connect \Y $and$libresoc.v:188932$13019_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:188934$13020 + cell $and $and$libresoc.v:188933$13020 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -393983,10 +390793,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:188934$13020_Y + connect \Y $and$libresoc.v:188933$13020_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:188935$13021 + cell $and $and$libresoc.v:188934$13021 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -393994,10 +390804,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:188935$13021_Y + connect \Y $and$libresoc.v:188934$13021_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188937$13023 + cell $and $and$libresoc.v:188936$13023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394005,10 +390815,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188937$13023_Y + connect \Y $and$libresoc.v:188936$13023_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188938$13024 + cell $and $and$libresoc.v:188937$13024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394016,10 +390826,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \spr1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188938$13024_Y + connect \Y $and$libresoc.v:188937$13024_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188939$13025 + cell $and $and$libresoc.v:188938$13025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394027,10 +390837,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188939$13025_Y + connect \Y $and$libresoc.v:188938$13025_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188940$13026 + cell $and $and$libresoc.v:188939$13026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394038,10 +390848,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188940$13026_Y + connect \Y $and$libresoc.v:188939$13026_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188941$13027 + cell $and $and$libresoc.v:188940$13027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394049,10 +390859,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188941$13027_Y + connect \Y $and$libresoc.v:188940$13027_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188942$13028 + cell $and $and$libresoc.v:188941$13028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394060,10 +390870,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188942$13028_Y + connect \Y $and$libresoc.v:188941$13028_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:188949$13035 + cell $and $and$libresoc.v:188948$13035 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394071,10 +390881,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:188949$13035_Y + connect \Y $and$libresoc.v:188948$13035_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:188923$13009 + cell $eq $eq$libresoc.v:188922$13009 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -394082,10 +390892,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$46 connect \B 1'0 - connect \Y $eq$libresoc.v:188923$13009_Y + connect \Y $eq$libresoc.v:188922$13009_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:188925$13011 + cell $eq $eq$libresoc.v:188924$13011 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -394093,66 +390903,66 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:188925$13011_Y + connect \Y $eq$libresoc.v:188924$13011_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:188884$12970 + cell $not $not$libresoc.v:188883$12970 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:188884$12970_Y + connect \Y $not$libresoc.v:188883$12970_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:188888$12974 + cell $not $not$libresoc.v:188887$12974 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:188888$12974_Y + connect \Y $not$libresoc.v:188887$12974_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:188907$12993 + cell $not $not$libresoc.v:188906$12993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:188907$12993_Y + connect \Y $not$libresoc.v:188906$12993_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:188909$12995 + cell $not $not$libresoc.v:188908$12995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:188909$12995_Y + connect \Y $not$libresoc.v:188908$12995_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:188912$12998 + cell $not $not$libresoc.v:188911$12998 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:188912$12998_Y + connect \Y $not$libresoc.v:188911$12998_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:188915$13001 + cell $not $not$libresoc.v:188914$13001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $not$libresoc.v:188915$13001_Y + connect \Y $not$libresoc.v:188914$13001_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:188920$13006 + cell $not $not$libresoc.v:188919$13006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_ready_i - connect \Y $not$libresoc.v:188920$13006_Y + connect \Y $not$libresoc.v:188919$13006_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:188895$12981 + cell $or $or$libresoc.v:188894$12981 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -394160,10 +390970,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$9 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:188895$12981_Y + connect \Y $or$libresoc.v:188894$12981_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:188919$13005 + cell $or $or$libresoc.v:188918$13005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394171,10 +390981,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:188919$13005_Y + connect \Y $or$libresoc.v:188918$13005_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:188929$13015 + cell $or $or$libresoc.v:188928$13015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394182,10 +390992,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:188929$13015_Y + connect \Y $or$libresoc.v:188928$13015_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:188930$13016 + cell $or $or$libresoc.v:188929$13016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -394193,10 +391003,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:188930$13016_Y + connect \Y $or$libresoc.v:188929$13016_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:188931$13017 + cell $or $or$libresoc.v:188930$13017 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -394204,10 +391014,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:188931$13017_Y + connect \Y $or$libresoc.v:188930$13017_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:188932$13018 + cell $or $or$libresoc.v:188931$13018 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -394215,10 +391025,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:188932$13018_Y + connect \Y $or$libresoc.v:188931$13018_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:188936$13022 + cell $or $or$libresoc.v:188935$13022 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -394226,90 +391036,90 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:188936$13022_Y + connect \Y $or$libresoc.v:188935$13022_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:188901$12987 + cell $reduce_and $reduce_and$libresoc.v:188900$12987 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$11 - connect \Y $reduce_and$libresoc.v:188901$12987_Y + connect \Y $reduce_and$libresoc.v:188900$12987_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:188914$13000 + cell $reduce_or $reduce_or$libresoc.v:188913$13000 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$30 - connect \Y $reduce_or$libresoc.v:188914$13000_Y + connect \Y $reduce_or$libresoc.v:188913$13000_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:188917$13003 + cell $reduce_or $reduce_or$libresoc.v:188916$13003 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:188917$13003_Y + connect \Y $reduce_or$libresoc.v:188916$13003_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:188918$13004 + cell $reduce_or $reduce_or$libresoc.v:188917$13004 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:188918$13004_Y + connect \Y $reduce_or$libresoc.v:188917$13004_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188943$13029 + cell $mux $ternary$libresoc.v:188942$13029 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:188943$13029_Y + connect \Y $ternary$libresoc.v:188942$13029_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188944$13030 + cell $mux $ternary$libresoc.v:188943$13030 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:188944$13030_Y + connect \Y $ternary$libresoc.v:188943$13030_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188945$13031 + cell $mux $ternary$libresoc.v:188944$13031 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:188945$13031_Y + connect \Y $ternary$libresoc.v:188944$13031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188946$13032 + cell $mux $ternary$libresoc.v:188945$13032 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:188946$13032_Y + connect \Y $ternary$libresoc.v:188945$13032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188947$13033 + cell $mux $ternary$libresoc.v:188946$13033 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:188947$13033_Y + connect \Y $ternary$libresoc.v:188946$13033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188948$13034 + cell $mux $ternary$libresoc.v:188947$13034 parameter \WIDTH 2 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:188948$13034_Y + connect \Y $ternary$libresoc.v:188947$13034_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:189024.14-189030.4" + attribute \src "libresoc.v:189023.14-189029.4" cell \alu_l$73 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394318,7 +391128,7 @@ module \spr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:189031.12-189060.4" + attribute \src "libresoc.v:189030.12-189059.4" cell \alu_spr0 \alu_spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394350,7 +391160,7 @@ module \spr0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:189061.15-189067.4" + attribute \src "libresoc.v:189060.15-189066.4" cell \alui_l$72 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394359,7 +391169,7 @@ module \spr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:189068.14-189074.4" + attribute \src "libresoc.v:189067.14-189073.4" cell \opc_l$68 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394368,7 +391178,7 @@ module \spr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:189075.14-189081.4" + attribute \src "libresoc.v:189074.14-189080.4" cell \req_l$69 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394377,7 +391187,7 @@ module \spr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:189082.14-189088.4" + attribute \src "libresoc.v:189081.14-189087.4" cell \rok_l$71 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394386,7 +391196,7 @@ module \spr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:189089.14-189094.4" + attribute \src "libresoc.v:189088.14-189093.4" cell \rst_l$70 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394394,7 +391204,7 @@ module \spr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:189095.14-189101.4" + attribute \src "libresoc.v:189094.14-189100.4" cell \src_l$67 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -394402,577 +391212,577 @@ module \spr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:188273.7-188273.20" - process $proc$libresoc.v:188273$13194 + attribute \src "libresoc.v:188272.7-188272.20" + process $proc$libresoc.v:188272$13194 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188409.7-188409.24" - process $proc$libresoc.v:188409$13195 + attribute \src "libresoc.v:188408.7-188408.24" + process $proc$libresoc.v:188408$13195 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:188419.7-188419.26" - process $proc$libresoc.v:188419$13196 + attribute \src "libresoc.v:188418.7-188418.26" + process $proc$libresoc.v:188418$13196 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:188427.7-188427.25" - process $proc$libresoc.v:188427$13197 + attribute \src "libresoc.v:188426.7-188426.25" + process $proc$libresoc.v:188426$13197 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:188472.14-188472.49" - process $proc$libresoc.v:188472$13198 + attribute \src "libresoc.v:188471.14-188471.49" + process $proc$libresoc.v:188471$13198 assign { } { } assign $1\alu_spr0_spr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[13:0] end - attribute \src "libresoc.v:188476.14-188476.43" - process $proc$libresoc.v:188476$13199 + attribute \src "libresoc.v:188475.14-188475.43" + process $proc$libresoc.v:188475$13199 assign { } { } assign $1\alu_spr0_spr_op__insn[31:0] 0 sync always sync init update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:188555.13-188555.47" - process $proc$libresoc.v:188555$13200 + attribute \src "libresoc.v:188554.13-188554.47" + process $proc$libresoc.v:188554$13200 assign { } { } assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:188559.7-188559.39" - process $proc$libresoc.v:188559$13201 + attribute \src "libresoc.v:188558.7-188558.39" + process $proc$libresoc.v:188558$13201 assign { } { } assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:188577.7-188577.27" - process $proc$libresoc.v:188577$13202 + attribute \src "libresoc.v:188576.7-188576.27" + process $proc$libresoc.v:188576$13202 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:188609.14-188609.47" - process $proc$libresoc.v:188609$13203 + attribute \src "libresoc.v:188608.14-188608.47" + process $proc$libresoc.v:188608$13203 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:188613.7-188613.27" - process $proc$libresoc.v:188613$13204 + attribute \src "libresoc.v:188612.7-188612.27" + process $proc$libresoc.v:188612$13204 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:188617.14-188617.50" - process $proc$libresoc.v:188617$13205 + attribute \src "libresoc.v:188616.14-188616.50" + process $proc$libresoc.v:188616$13205 assign { } { } assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__spr1 $1\data_r1__spr1[63:0] end - attribute \src "libresoc.v:188621.7-188621.30" - process $proc$libresoc.v:188621$13206 + attribute \src "libresoc.v:188620.7-188620.30" + process $proc$libresoc.v:188620$13206 assign { } { } assign $1\data_r1__spr1_ok[0:0] 1'0 sync always sync init update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:188625.14-188625.51" - process $proc$libresoc.v:188625$13207 + attribute \src "libresoc.v:188624.14-188624.51" + process $proc$libresoc.v:188624$13207 assign { } { } assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast1 $1\data_r2__fast1[63:0] end - attribute \src "libresoc.v:188629.7-188629.31" - process $proc$libresoc.v:188629$13208 + attribute \src "libresoc.v:188628.7-188628.31" + process $proc$libresoc.v:188628$13208 assign { } { } assign $1\data_r2__fast1_ok[0:0] 1'0 sync always sync init update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:188633.7-188633.29" - process $proc$libresoc.v:188633$13209 + attribute \src "libresoc.v:188632.7-188632.29" + process $proc$libresoc.v:188632$13209 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:188637.7-188637.32" - process $proc$libresoc.v:188637$13210 + attribute \src "libresoc.v:188636.7-188636.32" + process $proc$libresoc.v:188636$13210 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:188641.13-188641.35" - process $proc$libresoc.v:188641$13211 + attribute \src "libresoc.v:188640.13-188640.35" + process $proc$libresoc.v:188640$13211 assign { } { } assign $1\data_r4__xer_ov[1:0] 2'00 sync always sync init update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:188645.7-188645.32" - process $proc$libresoc.v:188645$13212 + attribute \src "libresoc.v:188644.7-188644.32" + process $proc$libresoc.v:188644$13212 assign { } { } assign $1\data_r4__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:188649.13-188649.35" - process $proc$libresoc.v:188649$13213 + attribute \src "libresoc.v:188648.13-188648.35" + process $proc$libresoc.v:188648$13213 assign { } { } assign $1\data_r5__xer_ca[1:0] 2'00 sync always sync init update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:188653.7-188653.32" - process $proc$libresoc.v:188653$13214 + attribute \src "libresoc.v:188652.7-188652.32" + process $proc$libresoc.v:188652$13214 assign { } { } assign $1\data_r5__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:188681.7-188681.25" - process $proc$libresoc.v:188681$13215 + attribute \src "libresoc.v:188680.7-188680.25" + process $proc$libresoc.v:188680$13215 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:188685.7-188685.25" - process $proc$libresoc.v:188685$13216 + attribute \src "libresoc.v:188684.7-188684.25" + process $proc$libresoc.v:188684$13216 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:188787.13-188787.31" - process $proc$libresoc.v:188787$13217 + attribute \src "libresoc.v:188786.13-188786.31" + process $proc$libresoc.v:188786$13217 assign { } { } assign $1\prev_wr_go[5:0] 6'000000 sync always sync init update \prev_wr_go $1\prev_wr_go[5:0] end - attribute \src "libresoc.v:188795.13-188795.32" - process $proc$libresoc.v:188795$13218 + attribute \src "libresoc.v:188794.13-188794.32" + process $proc$libresoc.v:188794$13218 assign { } { } assign $1\req_l_r_req[5:0] 6'111111 sync always sync init update \req_l_r_req $1\req_l_r_req[5:0] end - attribute \src "libresoc.v:188799.13-188799.32" - process $proc$libresoc.v:188799$13219 + attribute \src "libresoc.v:188798.13-188798.32" + process $proc$libresoc.v:188798$13219 assign { } { } assign $1\req_l_s_req[5:0] 6'000000 sync always sync init update \req_l_s_req $1\req_l_s_req[5:0] end - attribute \src "libresoc.v:188811.7-188811.26" - process $proc$libresoc.v:188811$13220 + attribute \src "libresoc.v:188810.7-188810.26" + process $proc$libresoc.v:188810$13220 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:188815.7-188815.26" - process $proc$libresoc.v:188815$13221 + attribute \src "libresoc.v:188814.7-188814.26" + process $proc$libresoc.v:188814$13221 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:188819.7-188819.25" - process $proc$libresoc.v:188819$13222 + attribute \src "libresoc.v:188818.7-188818.25" + process $proc$libresoc.v:188818$13222 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:188823.7-188823.25" - process $proc$libresoc.v:188823$13223 + attribute \src "libresoc.v:188822.7-188822.25" + process $proc$libresoc.v:188822$13223 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:188845.13-188845.32" - process $proc$libresoc.v:188845$13224 + attribute \src "libresoc.v:188844.13-188844.32" + process $proc$libresoc.v:188844$13224 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:188849.13-188849.32" - process $proc$libresoc.v:188849$13225 + attribute \src "libresoc.v:188848.13-188848.32" + process $proc$libresoc.v:188848$13225 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:188853.14-188853.43" - process $proc$libresoc.v:188853$13226 + attribute \src "libresoc.v:188852.14-188852.43" + process $proc$libresoc.v:188852$13226 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:188857.14-188857.43" - process $proc$libresoc.v:188857$13227 + attribute \src "libresoc.v:188856.14-188856.43" + process $proc$libresoc.v:188856$13227 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:188861.14-188861.43" - process $proc$libresoc.v:188861$13228 + attribute \src "libresoc.v:188860.14-188860.43" + process $proc$libresoc.v:188860$13228 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:188865.7-188865.20" - process $proc$libresoc.v:188865$13229 + attribute \src "libresoc.v:188864.7-188864.20" + process $proc$libresoc.v:188864$13229 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:188869.13-188869.26" - process $proc$libresoc.v:188869$13230 + attribute \src "libresoc.v:188868.13-188868.26" + process $proc$libresoc.v:188868$13230 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:188873.13-188873.26" - process $proc$libresoc.v:188873$13231 + attribute \src "libresoc.v:188872.13-188872.26" + process $proc$libresoc.v:188872$13231 assign { } { } assign $1\src_r5[1:0] 2'00 sync always sync init update \src_r5 $1\src_r5[1:0] end - attribute \src "libresoc.v:188950.3-188951.39" - process $proc$libresoc.v:188950$13036 + attribute \src "libresoc.v:188949.3-188950.39" + process $proc$libresoc.v:188949$13036 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:188952.3-188953.43" - process $proc$libresoc.v:188952$13037 + attribute \src "libresoc.v:188951.3-188952.43" + process $proc$libresoc.v:188951$13037 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:188954.3-188955.29" - process $proc$libresoc.v:188954$13038 + attribute \src "libresoc.v:188953.3-188954.29" + process $proc$libresoc.v:188953$13038 assign { } { } assign $0\src_r5[1:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[1:0] end - attribute \src "libresoc.v:188956.3-188957.29" - process $proc$libresoc.v:188956$13039 + attribute \src "libresoc.v:188955.3-188956.29" + process $proc$libresoc.v:188955$13039 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:188958.3-188959.29" - process $proc$libresoc.v:188958$13040 + attribute \src "libresoc.v:188957.3-188958.29" + process $proc$libresoc.v:188957$13040 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:188960.3-188961.29" - process $proc$libresoc.v:188960$13041 + attribute \src "libresoc.v:188959.3-188960.29" + process $proc$libresoc.v:188959$13041 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:188962.3-188963.29" - process $proc$libresoc.v:188962$13042 + attribute \src "libresoc.v:188961.3-188962.29" + process $proc$libresoc.v:188961$13042 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:188964.3-188965.29" - process $proc$libresoc.v:188964$13043 + attribute \src "libresoc.v:188963.3-188964.29" + process $proc$libresoc.v:188963$13043 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:188966.3-188967.47" - process $proc$libresoc.v:188966$13044 + attribute \src "libresoc.v:188965.3-188966.47" + process $proc$libresoc.v:188965$13044 assign { } { } assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next sync posedge \coresync_clk update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:188968.3-188969.53" - process $proc$libresoc.v:188968$13045 + attribute \src "libresoc.v:188967.3-188968.53" + process $proc$libresoc.v:188967$13045 assign { } { } assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next sync posedge \coresync_clk update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:188970.3-188971.47" - process $proc$libresoc.v:188970$13046 + attribute \src "libresoc.v:188969.3-188970.47" + process $proc$libresoc.v:188969$13046 assign { } { } assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next sync posedge \coresync_clk update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:188972.3-188973.53" - process $proc$libresoc.v:188972$13047 + attribute \src "libresoc.v:188971.3-188972.53" + process $proc$libresoc.v:188971$13047 assign { } { } assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next sync posedge \coresync_clk update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:188974.3-188975.47" - process $proc$libresoc.v:188974$13048 + attribute \src "libresoc.v:188973.3-188974.47" + process $proc$libresoc.v:188973$13048 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:188976.3-188977.53" - process $proc$libresoc.v:188976$13049 + attribute \src "libresoc.v:188975.3-188976.53" + process $proc$libresoc.v:188975$13049 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:188978.3-188979.45" - process $proc$libresoc.v:188978$13050 + attribute \src "libresoc.v:188977.3-188978.45" + process $proc$libresoc.v:188977$13050 assign { } { } assign $0\data_r2__fast1[63:0] \data_r2__fast1$next sync posedge \coresync_clk update \data_r2__fast1 $0\data_r2__fast1[63:0] end - attribute \src "libresoc.v:188980.3-188981.51" - process $proc$libresoc.v:188980$13051 + attribute \src "libresoc.v:188979.3-188980.51" + process $proc$libresoc.v:188979$13051 assign { } { } assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next sync posedge \coresync_clk update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:188982.3-188983.43" - process $proc$libresoc.v:188982$13052 + attribute \src "libresoc.v:188981.3-188982.43" + process $proc$libresoc.v:188981$13052 assign { } { } assign $0\data_r1__spr1[63:0] \data_r1__spr1$next sync posedge \coresync_clk update \data_r1__spr1 $0\data_r1__spr1[63:0] end - attribute \src "libresoc.v:188984.3-188985.49" - process $proc$libresoc.v:188984$13053 + attribute \src "libresoc.v:188983.3-188984.49" + process $proc$libresoc.v:188983$13053 assign { } { } assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next sync posedge \coresync_clk update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:188986.3-188987.37" - process $proc$libresoc.v:188986$13054 + attribute \src "libresoc.v:188985.3-188986.37" + process $proc$libresoc.v:188985$13054 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:188988.3-188989.43" - process $proc$libresoc.v:188988$13055 + attribute \src "libresoc.v:188987.3-188988.43" + process $proc$libresoc.v:188987$13055 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:188990.3-188991.69" - process $proc$libresoc.v:188990$13056 + attribute \src "libresoc.v:188989.3-188990.69" + process $proc$libresoc.v:188989$13056 assign { } { } assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:188992.3-188993.65" - process $proc$libresoc.v:188992$13057 + attribute \src "libresoc.v:188991.3-188992.65" + process $proc$libresoc.v:188991$13057 assign { } { } assign $0\alu_spr0_spr_op__fn_unit[13:0] \alu_spr0_spr_op__fn_unit$next sync posedge \coresync_clk update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[13:0] end - attribute \src "libresoc.v:188994.3-188995.59" - process $proc$libresoc.v:188994$13058 + attribute \src "libresoc.v:188993.3-188994.59" + process $proc$libresoc.v:188993$13058 assign { } { } assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:188996.3-188997.67" - process $proc$libresoc.v:188996$13059 + attribute \src "libresoc.v:188995.3-188996.67" + process $proc$libresoc.v:188995$13059 assign { } { } assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next sync posedge \coresync_clk update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:188998.3-188999.39" - process $proc$libresoc.v:188998$13060 + attribute \src "libresoc.v:188997.3-188998.39" + process $proc$libresoc.v:188997$13060 assign { } { } assign $0\req_l_r_req[5:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[5:0] end - attribute \src "libresoc.v:189000.3-189001.39" - process $proc$libresoc.v:189000$13061 + attribute \src "libresoc.v:188999.3-189000.39" + process $proc$libresoc.v:188999$13061 assign { } { } assign $0\req_l_s_req[5:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[5:0] end - attribute \src "libresoc.v:189002.3-189003.39" - process $proc$libresoc.v:189002$13062 + attribute \src "libresoc.v:189001.3-189002.39" + process $proc$libresoc.v:189001$13062 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:189004.3-189005.39" - process $proc$libresoc.v:189004$13063 + attribute \src "libresoc.v:189003.3-189004.39" + process $proc$libresoc.v:189003$13063 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:189006.3-189007.39" - process $proc$libresoc.v:189006$13064 + attribute \src "libresoc.v:189005.3-189006.39" + process $proc$libresoc.v:189005$13064 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:189008.3-189009.39" - process $proc$libresoc.v:189008$13065 + attribute \src "libresoc.v:189007.3-189008.39" + process $proc$libresoc.v:189007$13065 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:189010.3-189011.39" - process $proc$libresoc.v:189010$13066 + attribute \src "libresoc.v:189009.3-189010.39" + process $proc$libresoc.v:189009$13066 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:189012.3-189013.39" - process $proc$libresoc.v:189012$13067 + attribute \src "libresoc.v:189011.3-189012.39" + process $proc$libresoc.v:189011$13067 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:189014.3-189015.41" - process $proc$libresoc.v:189014$13068 + attribute \src "libresoc.v:189013.3-189014.41" + process $proc$libresoc.v:189013$13068 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:189016.3-189017.41" - process $proc$libresoc.v:189016$13069 + attribute \src "libresoc.v:189015.3-189016.41" + process $proc$libresoc.v:189015$13069 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:189018.3-189019.37" - process $proc$libresoc.v:189018$13070 + attribute \src "libresoc.v:189017.3-189018.37" + process $proc$libresoc.v:189017$13070 assign { } { } assign $0\prev_wr_go[5:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[5:0] end - attribute \src "libresoc.v:189020.3-189021.40" - process $proc$libresoc.v:189020$13071 + attribute \src "libresoc.v:189019.3-189020.40" + process $proc$libresoc.v:189019$13071 assign { } { } assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:189022.3-189023.25" - process $proc$libresoc.v:189022$13072 + attribute \src "libresoc.v:189021.3-189022.25" + process $proc$libresoc.v:189021$13072 assign { } { } assign $0\all_rd_dly[0:0] \$14 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:189102.3-189111.6" - process $proc$libresoc.v:189102$13073 + attribute \src "libresoc.v:189101.3-189110.6" + process $proc$libresoc.v:189101$13073 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:189103.5-189103.29" + attribute \src "libresoc.v:189102.5-189102.29" switch \initial - attribute \src "libresoc.v:189103.9-189103.17" + attribute \src "libresoc.v:189102.9-189102.17" case 1'1 case end @@ -394988,14 +391798,14 @@ module \spr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:189112.3-189120.6" - process $proc$libresoc.v:189112$13074 + attribute \src "libresoc.v:189111.3-189119.6" + process $proc$libresoc.v:189111$13074 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$13075 $1\rok_l_s_rdok$next[0:0]$13076 - attribute \src "libresoc.v:189113.5-189113.29" + attribute \src "libresoc.v:189112.5-189112.29" switch \initial - attribute \src "libresoc.v:189113.9-189113.17" + attribute \src "libresoc.v:189112.9-189112.17" case 1'1 case end @@ -395011,14 +391821,14 @@ module \spr0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13075 end - attribute \src "libresoc.v:189121.3-189129.6" - process $proc$libresoc.v:189121$13077 + attribute \src "libresoc.v:189120.3-189128.6" + process $proc$libresoc.v:189120$13077 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$13078 $1\rok_l_r_rdok$next[0:0]$13079 - attribute \src "libresoc.v:189122.5-189122.29" + attribute \src "libresoc.v:189121.5-189121.29" switch \initial - attribute \src "libresoc.v:189122.9-189122.17" + attribute \src "libresoc.v:189121.9-189121.17" case 1'1 case end @@ -395034,14 +391844,14 @@ module \spr0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13078 end - attribute \src "libresoc.v:189130.3-189138.6" - process $proc$libresoc.v:189130$13080 + attribute \src "libresoc.v:189129.3-189137.6" + process $proc$libresoc.v:189129$13080 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$13081 $1\rst_l_s_rst$next[0:0]$13082 - attribute \src "libresoc.v:189131.5-189131.29" + attribute \src "libresoc.v:189130.5-189130.29" switch \initial - attribute \src "libresoc.v:189131.9-189131.17" + attribute \src "libresoc.v:189130.9-189130.17" case 1'1 case end @@ -395057,14 +391867,14 @@ module \spr0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13081 end - attribute \src "libresoc.v:189139.3-189147.6" - process $proc$libresoc.v:189139$13083 + attribute \src "libresoc.v:189138.3-189146.6" + process $proc$libresoc.v:189138$13083 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$13084 $1\rst_l_r_rst$next[0:0]$13085 - attribute \src "libresoc.v:189140.5-189140.29" + attribute \src "libresoc.v:189139.5-189139.29" switch \initial - attribute \src "libresoc.v:189140.9-189140.17" + attribute \src "libresoc.v:189139.9-189139.17" case 1'1 case end @@ -395080,14 +391890,14 @@ module \spr0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13084 end - attribute \src "libresoc.v:189148.3-189156.6" - process $proc$libresoc.v:189148$13086 + attribute \src "libresoc.v:189147.3-189155.6" + process $proc$libresoc.v:189147$13086 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$13087 $1\opc_l_s_opc$next[0:0]$13088 - attribute \src "libresoc.v:189149.5-189149.29" + attribute \src "libresoc.v:189148.5-189148.29" switch \initial - attribute \src "libresoc.v:189149.9-189149.17" + attribute \src "libresoc.v:189148.9-189148.17" case 1'1 case end @@ -395103,14 +391913,14 @@ module \spr0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$13087 end - attribute \src "libresoc.v:189157.3-189165.6" - process $proc$libresoc.v:189157$13089 + attribute \src "libresoc.v:189156.3-189164.6" + process $proc$libresoc.v:189156$13089 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$13090 $1\opc_l_r_opc$next[0:0]$13091 - attribute \src "libresoc.v:189158.5-189158.29" + attribute \src "libresoc.v:189157.5-189157.29" switch \initial - attribute \src "libresoc.v:189158.9-189158.17" + attribute \src "libresoc.v:189157.9-189157.17" case 1'1 case end @@ -395126,14 +391936,14 @@ module \spr0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$13090 end - attribute \src "libresoc.v:189166.3-189174.6" - process $proc$libresoc.v:189166$13092 + attribute \src "libresoc.v:189165.3-189173.6" + process $proc$libresoc.v:189165$13092 assign { } { } assign { } { } assign $0\src_l_s_src$next[5:0]$13093 $1\src_l_s_src$next[5:0]$13094 - attribute \src "libresoc.v:189167.5-189167.29" + attribute \src "libresoc.v:189166.5-189166.29" switch \initial - attribute \src "libresoc.v:189167.9-189167.17" + attribute \src "libresoc.v:189166.9-189166.17" case 1'1 case end @@ -395149,14 +391959,14 @@ module \spr0 sync always update \src_l_s_src$next $0\src_l_s_src$next[5:0]$13093 end - attribute \src "libresoc.v:189175.3-189183.6" - process $proc$libresoc.v:189175$13095 + attribute \src "libresoc.v:189174.3-189182.6" + process $proc$libresoc.v:189174$13095 assign { } { } assign { } { } assign $0\src_l_r_src$next[5:0]$13096 $1\src_l_r_src$next[5:0]$13097 - attribute \src "libresoc.v:189176.5-189176.29" + attribute \src "libresoc.v:189175.5-189175.29" switch \initial - attribute \src "libresoc.v:189176.9-189176.17" + attribute \src "libresoc.v:189175.9-189175.17" case 1'1 case end @@ -395172,14 +391982,14 @@ module \spr0 sync always update \src_l_r_src$next $0\src_l_r_src$next[5:0]$13096 end - attribute \src "libresoc.v:189184.3-189192.6" - process $proc$libresoc.v:189184$13098 + attribute \src "libresoc.v:189183.3-189191.6" + process $proc$libresoc.v:189183$13098 assign { } { } assign { } { } assign $0\req_l_s_req$next[5:0]$13099 $1\req_l_s_req$next[5:0]$13100 - attribute \src "libresoc.v:189185.5-189185.29" + attribute \src "libresoc.v:189184.5-189184.29" switch \initial - attribute \src "libresoc.v:189185.9-189185.17" + attribute \src "libresoc.v:189184.9-189184.17" case 1'1 case end @@ -395195,14 +392005,14 @@ module \spr0 sync always update \req_l_s_req$next $0\req_l_s_req$next[5:0]$13099 end - attribute \src "libresoc.v:189193.3-189201.6" - process $proc$libresoc.v:189193$13101 + attribute \src "libresoc.v:189192.3-189200.6" + process $proc$libresoc.v:189192$13101 assign { } { } assign { } { } assign $0\req_l_r_req$next[5:0]$13102 $1\req_l_r_req$next[5:0]$13103 - attribute \src "libresoc.v:189194.5-189194.29" + attribute \src "libresoc.v:189193.5-189193.29" switch \initial - attribute \src "libresoc.v:189194.9-189194.17" + attribute \src "libresoc.v:189193.9-189193.17" case 1'1 case end @@ -395218,8 +392028,8 @@ module \spr0 sync always update \req_l_r_req$next $0\req_l_r_req$next[5:0]$13102 end - attribute \src "libresoc.v:189202.3-189214.6" - process $proc$libresoc.v:189202$13104 + attribute \src "libresoc.v:189201.3-189213.6" + process $proc$libresoc.v:189201$13104 assign { } { } assign { } { } assign { } { } @@ -395232,9 +392042,9 @@ module \spr0 assign $0\alu_spr0_spr_op__insn$next[31:0]$13106 $1\alu_spr0_spr_op__insn$next[31:0]$13110 assign $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 - attribute \src "libresoc.v:189203.5-189203.29" + attribute \src "libresoc.v:189202.5-189202.29" switch \initial - attribute \src "libresoc.v:189203.9-189203.17" + attribute \src "libresoc.v:189202.9-189202.17" case 1'1 case end @@ -395259,8 +392069,8 @@ module \spr0 update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 end - attribute \src "libresoc.v:189215.3-189236.6" - process $proc$libresoc.v:189215$13113 + attribute \src "libresoc.v:189214.3-189235.6" + process $proc$libresoc.v:189214$13113 assign { } { } assign { } { } assign { } { } @@ -395270,9 +392080,9 @@ module \spr0 assign $0\data_r0__o$next[63:0]$13114 $2\data_r0__o$next[63:0]$13118 assign { } { } assign $0\data_r0__o_ok$next[0:0]$13115 $3\data_r0__o_ok$next[0:0]$13120 - attribute \src "libresoc.v:189216.5-189216.29" + attribute \src "libresoc.v:189215.5-189215.29" switch \initial - attribute \src "libresoc.v:189216.9-189216.17" + attribute \src "libresoc.v:189215.9-189215.17" case 1'1 case end @@ -395311,8 +392121,8 @@ module \spr0 update \data_r0__o$next $0\data_r0__o$next[63:0]$13114 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$13115 end - attribute \src "libresoc.v:189237.3-189258.6" - process $proc$libresoc.v:189237$13121 + attribute \src "libresoc.v:189236.3-189257.6" + process $proc$libresoc.v:189236$13121 assign { } { } assign { } { } assign { } { } @@ -395322,9 +392132,9 @@ module \spr0 assign $0\data_r1__spr1$next[63:0]$13122 $2\data_r1__spr1$next[63:0]$13126 assign { } { } assign $0\data_r1__spr1_ok$next[0:0]$13123 $3\data_r1__spr1_ok$next[0:0]$13128 - attribute \src "libresoc.v:189238.5-189238.29" + attribute \src "libresoc.v:189237.5-189237.29" switch \initial - attribute \src "libresoc.v:189238.9-189238.17" + attribute \src "libresoc.v:189237.9-189237.17" case 1'1 case end @@ -395363,8 +392173,8 @@ module \spr0 update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$13122 update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$13123 end - attribute \src "libresoc.v:189259.3-189280.6" - process $proc$libresoc.v:189259$13129 + attribute \src "libresoc.v:189258.3-189279.6" + process $proc$libresoc.v:189258$13129 assign { } { } assign { } { } assign { } { } @@ -395374,9 +392184,9 @@ module \spr0 assign $0\data_r2__fast1$next[63:0]$13130 $2\data_r2__fast1$next[63:0]$13134 assign { } { } assign $0\data_r2__fast1_ok$next[0:0]$13131 $3\data_r2__fast1_ok$next[0:0]$13136 - attribute \src "libresoc.v:189260.5-189260.29" + attribute \src "libresoc.v:189259.5-189259.29" switch \initial - attribute \src "libresoc.v:189260.9-189260.17" + attribute \src "libresoc.v:189259.9-189259.17" case 1'1 case end @@ -395415,8 +392225,8 @@ module \spr0 update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$13130 update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$13131 end - attribute \src "libresoc.v:189281.3-189302.6" - process $proc$libresoc.v:189281$13137 + attribute \src "libresoc.v:189280.3-189301.6" + process $proc$libresoc.v:189280$13137 assign { } { } assign { } { } assign { } { } @@ -395426,9 +392236,9 @@ module \spr0 assign $0\data_r3__xer_so$next[0:0]$13138 $2\data_r3__xer_so$next[0:0]$13142 assign { } { } assign $0\data_r3__xer_so_ok$next[0:0]$13139 $3\data_r3__xer_so_ok$next[0:0]$13144 - attribute \src "libresoc.v:189282.5-189282.29" + attribute \src "libresoc.v:189281.5-189281.29" switch \initial - attribute \src "libresoc.v:189282.9-189282.17" + attribute \src "libresoc.v:189281.9-189281.17" case 1'1 case end @@ -395467,8 +392277,8 @@ module \spr0 update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$13138 update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$13139 end - attribute \src "libresoc.v:189303.3-189324.6" - process $proc$libresoc.v:189303$13145 + attribute \src "libresoc.v:189302.3-189323.6" + process $proc$libresoc.v:189302$13145 assign { } { } assign { } { } assign { } { } @@ -395478,9 +392288,9 @@ module \spr0 assign $0\data_r4__xer_ov$next[1:0]$13146 $2\data_r4__xer_ov$next[1:0]$13150 assign { } { } assign $0\data_r4__xer_ov_ok$next[0:0]$13147 $3\data_r4__xer_ov_ok$next[0:0]$13152 - attribute \src "libresoc.v:189304.5-189304.29" + attribute \src "libresoc.v:189303.5-189303.29" switch \initial - attribute \src "libresoc.v:189304.9-189304.17" + attribute \src "libresoc.v:189303.9-189303.17" case 1'1 case end @@ -395519,8 +392329,8 @@ module \spr0 update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$13146 update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$13147 end - attribute \src "libresoc.v:189325.3-189346.6" - process $proc$libresoc.v:189325$13153 + attribute \src "libresoc.v:189324.3-189345.6" + process $proc$libresoc.v:189324$13153 assign { } { } assign { } { } assign { } { } @@ -395530,9 +392340,9 @@ module \spr0 assign $0\data_r5__xer_ca$next[1:0]$13154 $2\data_r5__xer_ca$next[1:0]$13158 assign { } { } assign $0\data_r5__xer_ca_ok$next[0:0]$13155 $3\data_r5__xer_ca_ok$next[0:0]$13160 - attribute \src "libresoc.v:189326.5-189326.29" + attribute \src "libresoc.v:189325.5-189325.29" switch \initial - attribute \src "libresoc.v:189326.9-189326.17" + attribute \src "libresoc.v:189325.9-189325.17" case 1'1 case end @@ -395571,14 +392381,14 @@ module \spr0 update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$13154 update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$13155 end - attribute \src "libresoc.v:189347.3-189356.6" - process $proc$libresoc.v:189347$13161 + attribute \src "libresoc.v:189346.3-189355.6" + process $proc$libresoc.v:189346$13161 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$13162 $1\src_r0$next[63:0]$13163 - attribute \src "libresoc.v:189348.5-189348.29" + attribute \src "libresoc.v:189347.5-189347.29" switch \initial - attribute \src "libresoc.v:189348.9-189348.17" + attribute \src "libresoc.v:189347.9-189347.17" case 1'1 case end @@ -395594,14 +392404,14 @@ module \spr0 sync always update \src_r0$next $0\src_r0$next[63:0]$13162 end - attribute \src "libresoc.v:189357.3-189366.6" - process $proc$libresoc.v:189357$13164 + attribute \src "libresoc.v:189356.3-189365.6" + process $proc$libresoc.v:189356$13164 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$13165 $1\src_r1$next[63:0]$13166 - attribute \src "libresoc.v:189358.5-189358.29" + attribute \src "libresoc.v:189357.5-189357.29" switch \initial - attribute \src "libresoc.v:189358.9-189358.17" + attribute \src "libresoc.v:189357.9-189357.17" case 1'1 case end @@ -395617,14 +392427,14 @@ module \spr0 sync always update \src_r1$next $0\src_r1$next[63:0]$13165 end - attribute \src "libresoc.v:189367.3-189376.6" - process $proc$libresoc.v:189367$13167 + attribute \src "libresoc.v:189366.3-189375.6" + process $proc$libresoc.v:189366$13167 assign { } { } assign { } { } assign $0\src_r2$next[63:0]$13168 $1\src_r2$next[63:0]$13169 - attribute \src "libresoc.v:189368.5-189368.29" + attribute \src "libresoc.v:189367.5-189367.29" switch \initial - attribute \src "libresoc.v:189368.9-189368.17" + attribute \src "libresoc.v:189367.9-189367.17" case 1'1 case end @@ -395640,14 +392450,14 @@ module \spr0 sync always update \src_r2$next $0\src_r2$next[63:0]$13168 end - attribute \src "libresoc.v:189377.3-189386.6" - process $proc$libresoc.v:189377$13170 + attribute \src "libresoc.v:189376.3-189385.6" + process $proc$libresoc.v:189376$13170 assign { } { } assign { } { } assign $0\src_r3$next[0:0]$13171 $1\src_r3$next[0:0]$13172 - attribute \src "libresoc.v:189378.5-189378.29" + attribute \src "libresoc.v:189377.5-189377.29" switch \initial - attribute \src "libresoc.v:189378.9-189378.17" + attribute \src "libresoc.v:189377.9-189377.17" case 1'1 case end @@ -395663,14 +392473,14 @@ module \spr0 sync always update \src_r3$next $0\src_r3$next[0:0]$13171 end - attribute \src "libresoc.v:189387.3-189396.6" - process $proc$libresoc.v:189387$13173 + attribute \src "libresoc.v:189386.3-189395.6" + process $proc$libresoc.v:189386$13173 assign { } { } assign { } { } assign $0\src_r4$next[1:0]$13174 $1\src_r4$next[1:0]$13175 - attribute \src "libresoc.v:189388.5-189388.29" + attribute \src "libresoc.v:189387.5-189387.29" switch \initial - attribute \src "libresoc.v:189388.9-189388.17" + attribute \src "libresoc.v:189387.9-189387.17" case 1'1 case end @@ -395686,14 +392496,14 @@ module \spr0 sync always update \src_r4$next $0\src_r4$next[1:0]$13174 end - attribute \src "libresoc.v:189397.3-189406.6" - process $proc$libresoc.v:189397$13176 + attribute \src "libresoc.v:189396.3-189405.6" + process $proc$libresoc.v:189396$13176 assign { } { } assign { } { } assign $0\src_r5$next[1:0]$13177 $1\src_r5$next[1:0]$13178 - attribute \src "libresoc.v:189398.5-189398.29" + attribute \src "libresoc.v:189397.5-189397.29" switch \initial - attribute \src "libresoc.v:189398.9-189398.17" + attribute \src "libresoc.v:189397.9-189397.17" case 1'1 case end @@ -395709,14 +392519,14 @@ module \spr0 sync always update \src_r5$next $0\src_r5$next[1:0]$13177 end - attribute \src "libresoc.v:189407.3-189415.6" - process $proc$libresoc.v:189407$13179 + attribute \src "libresoc.v:189406.3-189414.6" + process $proc$libresoc.v:189406$13179 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$13180 $1\alui_l_r_alui$next[0:0]$13181 - attribute \src "libresoc.v:189408.5-189408.29" + attribute \src "libresoc.v:189407.5-189407.29" switch \initial - attribute \src "libresoc.v:189408.9-189408.17" + attribute \src "libresoc.v:189407.9-189407.17" case 1'1 case end @@ -395732,14 +392542,14 @@ module \spr0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$13180 end - attribute \src "libresoc.v:189416.3-189424.6" - process $proc$libresoc.v:189416$13182 + attribute \src "libresoc.v:189415.3-189423.6" + process $proc$libresoc.v:189415$13182 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$13183 $1\alu_l_r_alu$next[0:0]$13184 - attribute \src "libresoc.v:189417.5-189417.29" + attribute \src "libresoc.v:189416.5-189416.29" switch \initial - attribute \src "libresoc.v:189417.9-189417.17" + attribute \src "libresoc.v:189416.9-189416.17" case 1'1 case end @@ -395755,14 +392565,14 @@ module \spr0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$13183 end - attribute \src "libresoc.v:189425.3-189434.6" - process $proc$libresoc.v:189425$13185 + attribute \src "libresoc.v:189424.3-189433.6" + process $proc$libresoc.v:189424$13185 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:189426.5-189426.29" + attribute \src "libresoc.v:189425.5-189425.29" switch \initial - attribute \src "libresoc.v:189426.9-189426.17" + attribute \src "libresoc.v:189425.9-189425.17" case 1'1 case end @@ -395778,14 +392588,14 @@ module \spr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:189435.3-189444.6" - process $proc$libresoc.v:189435$13186 + attribute \src "libresoc.v:189434.3-189443.6" + process $proc$libresoc.v:189434$13186 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:189436.5-189436.29" + attribute \src "libresoc.v:189435.5-189435.29" switch \initial - attribute \src "libresoc.v:189436.9-189436.17" + attribute \src "libresoc.v:189435.9-189435.17" case 1'1 case end @@ -395801,14 +392611,14 @@ module \spr0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:189445.3-189454.6" - process $proc$libresoc.v:189445$13187 + attribute \src "libresoc.v:189444.3-189453.6" + process $proc$libresoc.v:189444$13187 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:189446.5-189446.29" + attribute \src "libresoc.v:189445.5-189445.29" switch \initial - attribute \src "libresoc.v:189446.9-189446.17" + attribute \src "libresoc.v:189445.9-189445.17" case 1'1 case end @@ -395824,14 +392634,14 @@ module \spr0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:189455.3-189464.6" - process $proc$libresoc.v:189455$13188 + attribute \src "libresoc.v:189454.3-189463.6" + process $proc$libresoc.v:189454$13188 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:189456.5-189456.29" + attribute \src "libresoc.v:189455.5-189455.29" switch \initial - attribute \src "libresoc.v:189456.9-189456.17" + attribute \src "libresoc.v:189455.9-189455.17" case 1'1 case end @@ -395847,14 +392657,14 @@ module \spr0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:189465.3-189474.6" - process $proc$libresoc.v:189465$13189 + attribute \src "libresoc.v:189464.3-189473.6" + process $proc$libresoc.v:189464$13189 assign { } { } assign { } { } assign $0\dest5_o[1:0] $1\dest5_o[1:0] - attribute \src "libresoc.v:189466.5-189466.29" + attribute \src "libresoc.v:189465.5-189465.29" switch \initial - attribute \src "libresoc.v:189466.9-189466.17" + attribute \src "libresoc.v:189465.9-189465.17" case 1'1 case end @@ -395870,14 +392680,14 @@ module \spr0 sync always update \dest5_o $0\dest5_o[1:0] end - attribute \src "libresoc.v:189475.3-189484.6" - process $proc$libresoc.v:189475$13190 + attribute \src "libresoc.v:189474.3-189483.6" + process $proc$libresoc.v:189474$13190 assign { } { } assign { } { } assign $0\dest6_o[1:0] $1\dest6_o[1:0] - attribute \src "libresoc.v:189476.5-189476.29" + attribute \src "libresoc.v:189475.5-189475.29" switch \initial - attribute \src "libresoc.v:189476.9-189476.17" + attribute \src "libresoc.v:189475.9-189475.17" case 1'1 case end @@ -395893,14 +392703,14 @@ module \spr0 sync always update \dest6_o $0\dest6_o[1:0] end - attribute \src "libresoc.v:189485.3-189493.6" - process $proc$libresoc.v:189485$13191 + attribute \src "libresoc.v:189484.3-189492.6" + process $proc$libresoc.v:189484$13191 assign { } { } assign { } { } assign $0\prev_wr_go$next[5:0]$13192 $1\prev_wr_go$next[5:0]$13193 - attribute \src "libresoc.v:189486.5-189486.29" + attribute \src "libresoc.v:189485.5-189485.29" switch \initial - attribute \src "libresoc.v:189486.9-189486.17" + attribute \src "libresoc.v:189485.9-189485.17" case 1'1 case end @@ -395916,72 +392726,72 @@ module \spr0 sync always update \prev_wr_go$next $0\prev_wr_go$next[5:0]$13192 end - connect \$9 $not$libresoc.v:188884$12970_Y - connect \$100 $and$libresoc.v:188885$12971_Y - connect \$102 $and$libresoc.v:188886$12972_Y - connect \$104 $and$libresoc.v:188887$12973_Y - connect \$106 $not$libresoc.v:188888$12974_Y - connect \$108 $and$libresoc.v:188889$12975_Y - connect \$110 $and$libresoc.v:188890$12976_Y - connect \$112 $and$libresoc.v:188891$12977_Y - connect \$114 $and$libresoc.v:188892$12978_Y - connect \$116 $and$libresoc.v:188893$12979_Y - connect \$118 $and$libresoc.v:188894$12980_Y - connect \$11 $or$libresoc.v:188895$12981_Y - connect \$120 $and$libresoc.v:188896$12982_Y - connect \$122 $and$libresoc.v:188897$12983_Y - connect \$124 $and$libresoc.v:188898$12984_Y - connect \$126 $and$libresoc.v:188899$12985_Y - connect \$128 $and$libresoc.v:188900$12986_Y - connect \$8 $reduce_and$libresoc.v:188901$12987_Y - connect \$130 $and$libresoc.v:188902$12988_Y - connect \$132 $and$libresoc.v:188903$12989_Y - connect \$134 $and$libresoc.v:188904$12990_Y - connect \$136 $and$libresoc.v:188905$12991_Y - connect \$14 $and$libresoc.v:188906$12992_Y - connect \$16 $not$libresoc.v:188907$12993_Y - connect \$18 $and$libresoc.v:188908$12994_Y - connect \$20 $not$libresoc.v:188909$12995_Y - connect \$22 $and$libresoc.v:188910$12996_Y - connect \$24 $and$libresoc.v:188911$12997_Y - connect \$28 $not$libresoc.v:188912$12998_Y - connect \$30 $and$libresoc.v:188913$12999_Y - connect \$27 $reduce_or$libresoc.v:188914$13000_Y - connect \$26 $not$libresoc.v:188915$13001_Y - connect \$34 $and$libresoc.v:188916$13002_Y - connect \$36 $reduce_or$libresoc.v:188917$13003_Y - connect \$38 $reduce_or$libresoc.v:188918$13004_Y - connect \$40 $or$libresoc.v:188919$13005_Y - connect \$42 $not$libresoc.v:188920$13006_Y - connect \$44 $and$libresoc.v:188921$13007_Y - connect \$46 $and$libresoc.v:188922$13008_Y - connect \$48 $eq$libresoc.v:188923$13009_Y - connect \$50 $and$libresoc.v:188924$13010_Y - connect \$52 $eq$libresoc.v:188925$13011_Y - connect \$54 $and$libresoc.v:188926$13012_Y - connect \$56 $and$libresoc.v:188927$13013_Y - connect \$58 $and$libresoc.v:188928$13014_Y - connect \$60 $or$libresoc.v:188929$13015_Y - connect \$62 $or$libresoc.v:188930$13016_Y - connect \$64 $or$libresoc.v:188931$13017_Y - connect \$66 $or$libresoc.v:188932$13018_Y - connect \$68 $and$libresoc.v:188933$13019_Y - connect \$6 $and$libresoc.v:188934$13020_Y - connect \$70 $and$libresoc.v:188935$13021_Y - connect \$72 $or$libresoc.v:188936$13022_Y - connect \$74 $and$libresoc.v:188937$13023_Y - connect \$76 $and$libresoc.v:188938$13024_Y - connect \$78 $and$libresoc.v:188939$13025_Y - connect \$80 $and$libresoc.v:188940$13026_Y - connect \$82 $and$libresoc.v:188941$13027_Y - connect \$84 $and$libresoc.v:188942$13028_Y - connect \$86 $ternary$libresoc.v:188943$13029_Y - connect \$88 $ternary$libresoc.v:188944$13030_Y - connect \$90 $ternary$libresoc.v:188945$13031_Y - connect \$92 $ternary$libresoc.v:188946$13032_Y - connect \$94 $ternary$libresoc.v:188947$13033_Y - connect \$96 $ternary$libresoc.v:188948$13034_Y - connect \$98 $and$libresoc.v:188949$13035_Y + connect \$9 $not$libresoc.v:188883$12970_Y + connect \$100 $and$libresoc.v:188884$12971_Y + connect \$102 $and$libresoc.v:188885$12972_Y + connect \$104 $and$libresoc.v:188886$12973_Y + connect \$106 $not$libresoc.v:188887$12974_Y + connect \$108 $and$libresoc.v:188888$12975_Y + connect \$110 $and$libresoc.v:188889$12976_Y + connect \$112 $and$libresoc.v:188890$12977_Y + connect \$114 $and$libresoc.v:188891$12978_Y + connect \$116 $and$libresoc.v:188892$12979_Y + connect \$118 $and$libresoc.v:188893$12980_Y + connect \$11 $or$libresoc.v:188894$12981_Y + connect \$120 $and$libresoc.v:188895$12982_Y + connect \$122 $and$libresoc.v:188896$12983_Y + connect \$124 $and$libresoc.v:188897$12984_Y + connect \$126 $and$libresoc.v:188898$12985_Y + connect \$128 $and$libresoc.v:188899$12986_Y + connect \$8 $reduce_and$libresoc.v:188900$12987_Y + connect \$130 $and$libresoc.v:188901$12988_Y + connect \$132 $and$libresoc.v:188902$12989_Y + connect \$134 $and$libresoc.v:188903$12990_Y + connect \$136 $and$libresoc.v:188904$12991_Y + connect \$14 $and$libresoc.v:188905$12992_Y + connect \$16 $not$libresoc.v:188906$12993_Y + connect \$18 $and$libresoc.v:188907$12994_Y + connect \$20 $not$libresoc.v:188908$12995_Y + connect \$22 $and$libresoc.v:188909$12996_Y + connect \$24 $and$libresoc.v:188910$12997_Y + connect \$28 $not$libresoc.v:188911$12998_Y + connect \$30 $and$libresoc.v:188912$12999_Y + connect \$27 $reduce_or$libresoc.v:188913$13000_Y + connect \$26 $not$libresoc.v:188914$13001_Y + connect \$34 $and$libresoc.v:188915$13002_Y + connect \$36 $reduce_or$libresoc.v:188916$13003_Y + connect \$38 $reduce_or$libresoc.v:188917$13004_Y + connect \$40 $or$libresoc.v:188918$13005_Y + connect \$42 $not$libresoc.v:188919$13006_Y + connect \$44 $and$libresoc.v:188920$13007_Y + connect \$46 $and$libresoc.v:188921$13008_Y + connect \$48 $eq$libresoc.v:188922$13009_Y + connect \$50 $and$libresoc.v:188923$13010_Y + connect \$52 $eq$libresoc.v:188924$13011_Y + connect \$54 $and$libresoc.v:188925$13012_Y + connect \$56 $and$libresoc.v:188926$13013_Y + connect \$58 $and$libresoc.v:188927$13014_Y + connect \$60 $or$libresoc.v:188928$13015_Y + connect \$62 $or$libresoc.v:188929$13016_Y + connect \$64 $or$libresoc.v:188930$13017_Y + connect \$66 $or$libresoc.v:188931$13018_Y + connect \$68 $and$libresoc.v:188932$13019_Y + connect \$6 $and$libresoc.v:188933$13020_Y + connect \$70 $and$libresoc.v:188934$13021_Y + connect \$72 $or$libresoc.v:188935$13022_Y + connect \$74 $and$libresoc.v:188936$13023_Y + connect \$76 $and$libresoc.v:188937$13024_Y + connect \$78 $and$libresoc.v:188938$13025_Y + connect \$80 $and$libresoc.v:188939$13026_Y + connect \$82 $and$libresoc.v:188940$13027_Y + connect \$84 $and$libresoc.v:188941$13028_Y + connect \$86 $ternary$libresoc.v:188942$13029_Y + connect \$88 $ternary$libresoc.v:188943$13030_Y + connect \$90 $ternary$libresoc.v:188944$13031_Y + connect \$92 $ternary$libresoc.v:188945$13032_Y + connect \$94 $ternary$libresoc.v:188946$13033_Y + connect \$96 $ternary$libresoc.v:188947$13034_Y + connect \$98 $and$libresoc.v:188948$13035_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$124 @@ -396014,111 +392824,111 @@ module \spr0 connect \all_rd_dly$next \all_rd connect \all_rd \$14 end -attribute \src "libresoc.v:189529.1-190049.10" +attribute \src "libresoc.v:189528.1-190048.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" attribute \generator "nMigen" module \spr_main - attribute \src "libresoc.v:189802.3-189817.6" + attribute \src "libresoc.v:189801.3-189816.6" wire width 64 $0\fast1$7[63:0]$13240 - attribute \src "libresoc.v:189879.3-189894.6" + attribute \src "libresoc.v:189878.3-189893.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:189530.7-189530.20" + attribute \src "libresoc.v:189529.7-189529.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189837.3-189878.6" + attribute \src "libresoc.v:189836.3-189877.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:189837.3-189878.6" + attribute \src "libresoc.v:189836.3-189877.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:190027.3-190045.6" + attribute \src "libresoc.v:190026.3-190044.6" wire width 64 $0\spr1$6[63:0]$13265 - attribute \src "libresoc.v:189818.3-189836.6" + attribute \src "libresoc.v:189817.3-189835.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:189982.3-190005.6" + attribute \src "libresoc.v:189981.3-190004.6" wire width 2 $0\xer_ca$10[1:0]$13259 - attribute \src "libresoc.v:190006.3-190026.6" + attribute \src "libresoc.v:190005.3-190025.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:189937.3-189960.6" + attribute \src "libresoc.v:189936.3-189959.6" wire width 2 $0\xer_ov$9[1:0]$13253 - attribute \src "libresoc.v:189961.3-189981.6" + attribute \src "libresoc.v:189960.3-189980.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:189895.3-189915.6" + attribute \src "libresoc.v:189894.3-189914.6" wire $0\xer_so$8[0:0]$13247 - attribute \src "libresoc.v:189916.3-189936.6" + attribute \src "libresoc.v:189915.3-189935.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:189802.3-189817.6" + attribute \src "libresoc.v:189801.3-189816.6" wire width 64 $1\fast1$7[63:0]$13241 - attribute \src "libresoc.v:189879.3-189894.6" + attribute \src "libresoc.v:189878.3-189893.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:189837.3-189878.6" + attribute \src "libresoc.v:189836.3-189877.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:189837.3-189878.6" + attribute \src "libresoc.v:189836.3-189877.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:190027.3-190045.6" + attribute \src "libresoc.v:190026.3-190044.6" wire width 64 $1\spr1$6[63:0]$13266 - attribute \src "libresoc.v:189818.3-189836.6" + attribute \src "libresoc.v:189817.3-189835.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:189982.3-190005.6" + attribute \src "libresoc.v:189981.3-190004.6" wire width 2 $1\xer_ca$10[1:0]$13260 - attribute \src "libresoc.v:190006.3-190026.6" + attribute \src "libresoc.v:190005.3-190025.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:189937.3-189960.6" + attribute \src "libresoc.v:189936.3-189959.6" wire width 2 $1\xer_ov$9[1:0]$13254 - attribute \src "libresoc.v:189961.3-189981.6" + attribute \src "libresoc.v:189960.3-189980.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:189895.3-189915.6" + attribute \src "libresoc.v:189894.3-189914.6" wire $1\xer_so$8[0:0]$13248 - attribute \src "libresoc.v:189916.3-189936.6" + attribute \src "libresoc.v:189915.3-189935.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:189802.3-189817.6" + attribute \src "libresoc.v:189801.3-189816.6" wire width 64 $2\fast1$7[63:0]$13242 - attribute \src "libresoc.v:189879.3-189894.6" + attribute \src "libresoc.v:189878.3-189893.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:189837.3-189878.6" + attribute \src "libresoc.v:189836.3-189877.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:190027.3-190045.6" + attribute \src "libresoc.v:190026.3-190044.6" wire width 64 $2\spr1$6[63:0]$13267 - attribute \src "libresoc.v:189818.3-189836.6" + attribute \src "libresoc.v:189817.3-189835.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:189982.3-190005.6" + attribute \src "libresoc.v:189981.3-190004.6" wire width 2 $2\xer_ca$10[1:0]$13261 - attribute \src "libresoc.v:190006.3-190026.6" + attribute \src "libresoc.v:190005.3-190025.6" wire $2\xer_ca_ok[0:0] - attribute \src "libresoc.v:189937.3-189960.6" + attribute \src "libresoc.v:189936.3-189959.6" wire width 2 $2\xer_ov$9[1:0]$13255 - attribute \src "libresoc.v:189961.3-189981.6" + attribute \src "libresoc.v:189960.3-189980.6" wire $2\xer_ov_ok[0:0] - attribute \src "libresoc.v:189895.3-189915.6" + attribute \src "libresoc.v:189894.3-189914.6" wire $2\xer_so$8[0:0]$13249 - attribute \src "libresoc.v:189916.3-189936.6" + attribute \src "libresoc.v:189915.3-189935.6" wire $2\xer_so_ok[0:0] - attribute \src "libresoc.v:189837.3-189878.6" + attribute \src "libresoc.v:189836.3-189877.6" wire width 46 $3\o[63:18] - attribute \src "libresoc.v:189982.3-190005.6" + attribute \src "libresoc.v:189981.3-190004.6" wire width 2 $3\xer_ca$10[1:0]$13262 - attribute \src "libresoc.v:190006.3-190026.6" + attribute \src "libresoc.v:190005.3-190025.6" wire $3\xer_ca_ok[0:0] - attribute \src "libresoc.v:189937.3-189960.6" + attribute \src "libresoc.v:189936.3-189959.6" wire width 2 $3\xer_ov$9[1:0]$13256 - attribute \src "libresoc.v:189961.3-189981.6" + attribute \src "libresoc.v:189960.3-189980.6" wire $3\xer_ov_ok[0:0] - attribute \src "libresoc.v:189895.3-189915.6" + attribute \src "libresoc.v:189894.3-189914.6" wire $3\xer_so$8[0:0]$13250 - attribute \src "libresoc.v:189916.3-189936.6" + attribute \src "libresoc.v:189915.3-189935.6" wire $3\xer_so_ok[0:0] + attribute \src "libresoc.v:189794.18-189794.106" + wire $eq$libresoc.v:189794$13232_Y attribute \src "libresoc.v:189795.18-189795.106" - wire $eq$libresoc.v:189795$13232_Y + wire $eq$libresoc.v:189795$13233_Y attribute \src "libresoc.v:189796.18-189796.106" - wire $eq$libresoc.v:189796$13233_Y + wire $eq$libresoc.v:189796$13234_Y attribute \src "libresoc.v:189797.18-189797.106" - wire $eq$libresoc.v:189797$13234_Y + wire $eq$libresoc.v:189797$13235_Y attribute \src "libresoc.v:189798.18-189798.106" - wire $eq$libresoc.v:189798$13235_Y + wire $eq$libresoc.v:189798$13236_Y attribute \src "libresoc.v:189799.18-189799.106" - wire $eq$libresoc.v:189799$13236_Y + wire $eq$libresoc.v:189799$13237_Y attribute \src "libresoc.v:189800.18-189800.106" - wire $eq$libresoc.v:189800$13237_Y - attribute \src "libresoc.v:189801.18-189801.106" - wire $eq$libresoc.v:189801$13238_Y + wire $eq$libresoc.v:189800$13238_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" @@ -396139,7 +392949,7 @@ module \spr_main wire width 64 output 20 \fast1$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 21 \fast1_ok - attribute \src "libresoc.v:189530.7-189530.15" + attribute \src "libresoc.v:189529.7-189529.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 28 \muxid @@ -396374,7 +393184,7 @@ module \spr_main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 23 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189795$13232 + cell $eq $eq$libresoc.v:189794$13232 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -396382,10 +393192,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189795$13232_Y + connect \Y $eq$libresoc.v:189794$13232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189796$13233 + cell $eq $eq$libresoc.v:189795$13233 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -396393,10 +393203,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189796$13233_Y + connect \Y $eq$libresoc.v:189795$13233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189797$13234 + cell $eq $eq$libresoc.v:189796$13234 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -396404,10 +393214,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189797$13234_Y + connect \Y $eq$libresoc.v:189796$13234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189798$13235 + cell $eq $eq$libresoc.v:189797$13235 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -396415,10 +393225,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189798$13235_Y + connect \Y $eq$libresoc.v:189797$13235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189799$13236 + cell $eq $eq$libresoc.v:189798$13236 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -396426,10 +393236,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189799$13236_Y + connect \Y $eq$libresoc.v:189798$13236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189800$13237 + cell $eq $eq$libresoc.v:189799$13237 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -396437,10 +393247,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189800$13237_Y + connect \Y $eq$libresoc.v:189799$13237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - cell $eq $eq$libresoc.v:189801$13238 + cell $eq $eq$libresoc.v:189800$13238 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -396448,24 +393258,24 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189801$13238_Y + connect \Y $eq$libresoc.v:189800$13238_Y end - attribute \src "libresoc.v:189530.7-189530.20" - process $proc$libresoc.v:189530$13268 + attribute \src "libresoc.v:189529.7-189529.20" + process $proc$libresoc.v:189529$13268 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189802.3-189817.6" - process $proc$libresoc.v:189802$13239 + attribute \src "libresoc.v:189801.3-189816.6" + process $proc$libresoc.v:189801$13239 assign { } { } assign { } { } assign $0\fast1$7[63:0]$13240 $1\fast1$7[63:0]$13241 - attribute \src "libresoc.v:189803.5-189803.29" + attribute \src "libresoc.v:189802.5-189802.29" switch \initial - attribute \src "libresoc.v:189803.9-189803.17" + attribute \src "libresoc.v:189802.9-189802.17" case 1'1 case end @@ -396490,14 +393300,14 @@ module \spr_main sync always update \fast1$7 $0\fast1$7[63:0]$13240 end - attribute \src "libresoc.v:189818.3-189836.6" - process $proc$libresoc.v:189818$13243 + attribute \src "libresoc.v:189817.3-189835.6" + process $proc$libresoc.v:189817$13243 assign { } { } assign { } { } assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] - attribute \src "libresoc.v:189819.5-189819.29" + attribute \src "libresoc.v:189818.5-189818.29" switch \initial - attribute \src "libresoc.v:189819.9-189819.17" + attribute \src "libresoc.v:189818.9-189818.17" case 1'1 case end @@ -396523,17 +393333,17 @@ module \spr_main sync always update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:189837.3-189878.6" - process $proc$libresoc.v:189837$13244 + attribute \src "libresoc.v:189836.3-189877.6" + process $proc$libresoc.v:189836$13244 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:189838.5-189838.29" + attribute \src "libresoc.v:189837.5-189837.29" switch \initial - attribute \src "libresoc.v:189838.9-189838.17" + attribute \src "libresoc.v:189837.9-189837.17" case 1'1 case end @@ -396584,14 +393394,14 @@ module \spr_main update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:189879.3-189894.6" - process $proc$libresoc.v:189879$13245 + attribute \src "libresoc.v:189878.3-189893.6" + process $proc$libresoc.v:189878$13245 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:189880.5-189880.29" + attribute \src "libresoc.v:189879.5-189879.29" switch \initial - attribute \src "libresoc.v:189880.9-189880.17" + attribute \src "libresoc.v:189879.9-189879.17" case 1'1 case end @@ -396616,14 +393426,14 @@ module \spr_main sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:189895.3-189915.6" - process $proc$libresoc.v:189895$13246 + attribute \src "libresoc.v:189894.3-189914.6" + process $proc$libresoc.v:189894$13246 assign { } { } assign { } { } assign $0\xer_so$8[0:0]$13247 $1\xer_so$8[0:0]$13248 - attribute \src "libresoc.v:189896.5-189896.29" + attribute \src "libresoc.v:189895.5-189895.29" switch \initial - attribute \src "libresoc.v:189896.9-189896.17" + attribute \src "libresoc.v:189895.9-189895.17" case 1'1 case end @@ -396657,14 +393467,14 @@ module \spr_main sync always update \xer_so$8 $0\xer_so$8[0:0]$13247 end - attribute \src "libresoc.v:189916.3-189936.6" - process $proc$libresoc.v:189916$13251 + attribute \src "libresoc.v:189915.3-189935.6" + process $proc$libresoc.v:189915$13251 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:189917.5-189917.29" + attribute \src "libresoc.v:189916.5-189916.29" switch \initial - attribute \src "libresoc.v:189917.9-189917.17" + attribute \src "libresoc.v:189916.9-189916.17" case 1'1 case end @@ -396698,14 +393508,14 @@ module \spr_main sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:189937.3-189960.6" - process $proc$libresoc.v:189937$13252 + attribute \src "libresoc.v:189936.3-189959.6" + process $proc$libresoc.v:189936$13252 assign { } { } assign { } { } assign $0\xer_ov$9[1:0]$13253 $1\xer_ov$9[1:0]$13254 - attribute \src "libresoc.v:189938.5-189938.29" + attribute \src "libresoc.v:189937.5-189937.29" switch \initial - attribute \src "libresoc.v:189938.9-189938.17" + attribute \src "libresoc.v:189937.9-189937.17" case 1'1 case end @@ -396740,14 +393550,14 @@ module \spr_main sync always update \xer_ov$9 $0\xer_ov$9[1:0]$13253 end - attribute \src "libresoc.v:189961.3-189981.6" - process $proc$libresoc.v:189961$13257 + attribute \src "libresoc.v:189960.3-189980.6" + process $proc$libresoc.v:189960$13257 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:189962.5-189962.29" + attribute \src "libresoc.v:189961.5-189961.29" switch \initial - attribute \src "libresoc.v:189962.9-189962.17" + attribute \src "libresoc.v:189961.9-189961.17" case 1'1 case end @@ -396781,14 +393591,14 @@ module \spr_main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:189982.3-190005.6" - process $proc$libresoc.v:189982$13258 + attribute \src "libresoc.v:189981.3-190004.6" + process $proc$libresoc.v:189981$13258 assign { } { } assign { } { } assign $0\xer_ca$10[1:0]$13259 $1\xer_ca$10[1:0]$13260 - attribute \src "libresoc.v:189983.5-189983.29" + attribute \src "libresoc.v:189982.5-189982.29" switch \initial - attribute \src "libresoc.v:189983.9-189983.17" + attribute \src "libresoc.v:189982.9-189982.17" case 1'1 case end @@ -396823,14 +393633,14 @@ module \spr_main sync always update \xer_ca$10 $0\xer_ca$10[1:0]$13259 end - attribute \src "libresoc.v:190006.3-190026.6" - process $proc$libresoc.v:190006$13263 + attribute \src "libresoc.v:190005.3-190025.6" + process $proc$libresoc.v:190005$13263 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:190007.5-190007.29" + attribute \src "libresoc.v:190006.5-190006.29" switch \initial - attribute \src "libresoc.v:190007.9-190007.17" + attribute \src "libresoc.v:190006.9-190006.17" case 1'1 case end @@ -396864,14 +393674,14 @@ module \spr_main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:190027.3-190045.6" - process $proc$libresoc.v:190027$13264 + attribute \src "libresoc.v:190026.3-190044.6" + process $proc$libresoc.v:190026$13264 assign { } { } assign { } { } assign $0\spr1$6[63:0]$13265 $1\spr1$6[63:0]$13266 - attribute \src "libresoc.v:190028.5-190028.29" + attribute \src "libresoc.v:190027.5-190027.29" switch \initial - attribute \src "libresoc.v:190028.9-190028.17" + attribute \src "libresoc.v:190027.9-190027.17" case 1'1 case end @@ -396897,45 +393707,45 @@ module \spr_main sync always update \spr1$6 $0\spr1$6[63:0]$13265 end - connect \$11 $eq$libresoc.v:189795$13232_Y - connect \$13 $eq$libresoc.v:189796$13233_Y - connect \$15 $eq$libresoc.v:189797$13234_Y - connect \$17 $eq$libresoc.v:189798$13235_Y - connect \$19 $eq$libresoc.v:189799$13236_Y - connect \$21 $eq$libresoc.v:189800$13237_Y - connect \$23 $eq$libresoc.v:189801$13238_Y + connect \$11 $eq$libresoc.v:189794$13232_Y + connect \$13 $eq$libresoc.v:189795$13233_Y + connect \$15 $eq$libresoc.v:189796$13234_Y + connect \$17 $eq$libresoc.v:189797$13235_Y + connect \$19 $eq$libresoc.v:189798$13236_Y + connect \$21 $eq$libresoc.v:189799$13237_Y + connect \$23 $eq$libresoc.v:189800$13238_Y connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \muxid$1 \muxid connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } end -attribute \src "libresoc.v:190053.1-190889.10" +attribute \src "libresoc.v:190052.1-190888.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" attribute \generator "nMigen" module \sprmap - attribute \src "libresoc.v:190183.3-190213.6" + attribute \src "libresoc.v:190182.3-190212.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:190214.3-190244.6" + attribute \src "libresoc.v:190213.3-190243.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:190054.7-190054.20" + attribute \src "libresoc.v:190053.7-190053.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190245.3-190566.6" + attribute \src "libresoc.v:190244.3-190565.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:190567.3-190888.6" + attribute \src "libresoc.v:190566.3-190887.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:190183.3-190213.6" + attribute \src "libresoc.v:190182.3-190212.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:190214.3-190244.6" + attribute \src "libresoc.v:190213.3-190243.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:190245.3-190566.6" + attribute \src "libresoc.v:190244.3-190565.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:190567.3-190888.6" + attribute \src "libresoc.v:190566.3-190887.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \fast_o_ok - attribute \src "libresoc.v:190054.7-190054.15" + attribute \src "libresoc.v:190053.7-190053.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" wire width 10 input 5 \spr_i @@ -397057,22 +393867,22 @@ module \sprmap wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \spr_o_ok - attribute \src "libresoc.v:190054.7-190054.20" - process $proc$libresoc.v:190054$13273 + attribute \src "libresoc.v:190053.7-190053.20" + process $proc$libresoc.v:190053$13273 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190183.3-190213.6" - process $proc$libresoc.v:190183$13269 + attribute \src "libresoc.v:190182.3-190212.6" + process $proc$libresoc.v:190182$13269 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:190184.5-190184.29" + attribute \src "libresoc.v:190183.5-190183.29" switch \initial - attribute \src "libresoc.v:190184.9-190184.17" + attribute \src "libresoc.v:190183.9-190183.17" case 1'1 case end @@ -397116,14 +393926,14 @@ module \sprmap sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:190214.3-190244.6" - process $proc$libresoc.v:190214$13270 + attribute \src "libresoc.v:190213.3-190243.6" + process $proc$libresoc.v:190213$13270 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:190215.5-190215.29" + attribute \src "libresoc.v:190214.5-190214.29" switch \initial - attribute \src "libresoc.v:190215.9-190215.17" + attribute \src "libresoc.v:190214.9-190214.17" case 1'1 case end @@ -397167,14 +393977,14 @@ module \sprmap sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:190245.3-190566.6" - process $proc$libresoc.v:190245$13271 + attribute \src "libresoc.v:190244.3-190565.6" + process $proc$libresoc.v:190244$13271 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:190246.5-190246.29" + attribute \src "libresoc.v:190245.5-190245.29" switch \initial - attribute \src "libresoc.v:190246.9-190246.17" + attribute \src "libresoc.v:190245.9-190245.17" case 1'1 case end @@ -397606,14 +394416,14 @@ module \sprmap sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:190567.3-190888.6" - process $proc$libresoc.v:190567$13272 + attribute \src "libresoc.v:190566.3-190887.6" + process $proc$libresoc.v:190566$13272 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:190568.5-190568.29" + attribute \src "libresoc.v:190567.5-190567.29" switch \initial - attribute \src "libresoc.v:190568.9-190568.17" + attribute \src "libresoc.v:190567.9-190567.17" case 1'1 case end @@ -398046,34 +394856,34 @@ module \sprmap update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:190893.1-191729.10" +attribute \src "libresoc.v:190892.1-191728.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" attribute \generator "nMigen" module \sprmap$174 - attribute \src "libresoc.v:191023.3-191053.6" + attribute \src "libresoc.v:191022.3-191052.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:191054.3-191084.6" + attribute \src "libresoc.v:191053.3-191083.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:190894.7-190894.20" + attribute \src "libresoc.v:190893.7-190893.20" wire $0\initial[0:0] - attribute \src "libresoc.v:191085.3-191406.6" + attribute \src "libresoc.v:191084.3-191405.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:191407.3-191728.6" + attribute \src "libresoc.v:191406.3-191727.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:191023.3-191053.6" + attribute \src "libresoc.v:191022.3-191052.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:191054.3-191084.6" + attribute \src "libresoc.v:191053.3-191083.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:191085.3-191406.6" + attribute \src "libresoc.v:191084.3-191405.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:191407.3-191728.6" + attribute \src "libresoc.v:191406.3-191727.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \fast_o_ok - attribute \src "libresoc.v:190894.7-190894.15" + attribute \src "libresoc.v:190893.7-190893.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" wire width 10 input 5 \spr_i @@ -398195,22 +395005,22 @@ module \sprmap$174 wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \spr_o_ok - attribute \src "libresoc.v:190894.7-190894.20" - process $proc$libresoc.v:190894$13278 + attribute \src "libresoc.v:190893.7-190893.20" + process $proc$libresoc.v:190893$13278 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:191023.3-191053.6" - process $proc$libresoc.v:191023$13274 + attribute \src "libresoc.v:191022.3-191052.6" + process $proc$libresoc.v:191022$13274 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:191024.5-191024.29" + attribute \src "libresoc.v:191023.5-191023.29" switch \initial - attribute \src "libresoc.v:191024.9-191024.17" + attribute \src "libresoc.v:191023.9-191023.17" case 1'1 case end @@ -398254,14 +395064,14 @@ module \sprmap$174 sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:191054.3-191084.6" - process $proc$libresoc.v:191054$13275 + attribute \src "libresoc.v:191053.3-191083.6" + process $proc$libresoc.v:191053$13275 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:191055.5-191055.29" + attribute \src "libresoc.v:191054.5-191054.29" switch \initial - attribute \src "libresoc.v:191055.9-191055.17" + attribute \src "libresoc.v:191054.9-191054.17" case 1'1 case end @@ -398305,14 +395115,14 @@ module \sprmap$174 sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:191085.3-191406.6" - process $proc$libresoc.v:191085$13276 + attribute \src "libresoc.v:191084.3-191405.6" + process $proc$libresoc.v:191084$13276 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:191086.5-191086.29" + attribute \src "libresoc.v:191085.5-191085.29" switch \initial - attribute \src "libresoc.v:191086.9-191086.17" + attribute \src "libresoc.v:191085.9-191085.17" case 1'1 case end @@ -398744,14 +395554,14 @@ module \sprmap$174 sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:191407.3-191728.6" - process $proc$libresoc.v:191407$13277 + attribute \src "libresoc.v:191406.3-191727.6" + process $proc$libresoc.v:191406$13277 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:191408.5-191408.29" + attribute \src "libresoc.v:191407.5-191407.29" switch \initial - attribute \src "libresoc.v:191408.9-191408.17" + attribute \src "libresoc.v:191407.9-191407.17" case 1'1 case end @@ -399184,1337 +395994,37 @@ module \sprmap$174 update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:191733.1-191873.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.sram4k_0" -attribute \generator "nMigen" -module \sram4k_0 - attribute \src "libresoc.v:191808.3-191822.6" - wire width 9 $0\a[8:0] - attribute \src "libresoc.v:191838.3-191852.6" - wire width 64 $0\d[63:0] - attribute \src "libresoc.v:191734.7-191734.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:191793.3-191807.6" - wire $0\sram4k_0_wb__ack$next[0:0]$13283 - attribute \src "libresoc.v:191774.3-191775.49" - wire $0\sram4k_0_wb__ack[0:0] - attribute \src "libresoc.v:191823.3-191837.6" - wire width 64 $0\sram4k_0_wb__dat_r[63:0] - attribute \src "libresoc.v:191783.3-191792.6" - wire $0\wb_active[0:0] - attribute \src "libresoc.v:191853.3-191872.6" - wire $0\we[0:0] - attribute \src "libresoc.v:191808.3-191822.6" - wire width 9 $1\a[8:0] - attribute \src "libresoc.v:191838.3-191852.6" - wire width 64 $1\d[63:0] - attribute \src "libresoc.v:191793.3-191807.6" - wire $1\sram4k_0_wb__ack$next[0:0]$13284 - attribute \src "libresoc.v:191751.7-191751.30" - wire $1\sram4k_0_wb__ack[0:0] - attribute \src "libresoc.v:191823.3-191837.6" - wire width 64 $1\sram4k_0_wb__dat_r[63:0] - attribute \src "libresoc.v:191783.3-191792.6" - wire $1\wb_active[0:0] - attribute \src "libresoc.v:191853.3-191872.6" - wire $1\we[0:0] - attribute \src "libresoc.v:191808.3-191822.6" - wire width 9 $2\a[8:0] - attribute \src "libresoc.v:191838.3-191852.6" - wire width 64 $2\d[63:0] - attribute \src "libresoc.v:191793.3-191807.6" - wire $2\sram4k_0_wb__ack$next[0:0]$13285 - attribute \src "libresoc.v:191823.3-191837.6" - wire width 64 $2\sram4k_0_wb__dat_r[63:0] - attribute \src "libresoc.v:191853.3-191872.6" - wire $2\we[0:0] - attribute \src "libresoc.v:191853.3-191872.6" - wire $3\we[0:0] - attribute \src "libresoc.v:191773.17-191773.129" - wire $and$libresoc.v:191773$13279_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" - wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 11 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" - wire width 64 \d - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" - wire input 2 \enable - attribute \src "libresoc.v:191734.7-191734.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" - wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 5 \sram4k_0_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire \sram4k_0_wb__ack$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 6 \sram4k_0_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 3 \sram4k_0_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 7 \sram4k_0_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 8 \sram4k_0_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 10 \sram4k_0_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 4 \sram4k_0_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 9 \sram4k_0_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" - wire \wb_active - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" - wire \we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - cell $and $and$libresoc.v:191773$13279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sram4k_0_wb__cyc - connect \B \sram4k_0_wb__stb - connect \Y $and$libresoc.v:191773$13279_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:191776.21-191782.4" - cell \SPBlock_512W64B8W \U$$0 - connect \a \a - connect \clk \clk - connect \d \d - connect \q \q - connect \we \we - end - attribute \src "libresoc.v:191734.7-191734.20" - process $proc$libresoc.v:191734$13290 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:191751.7-191751.30" - process $proc$libresoc.v:191751$13291 - assign { } { } - assign $1\sram4k_0_wb__ack[0:0] 1'0 - sync always - sync init - update \sram4k_0_wb__ack $1\sram4k_0_wb__ack[0:0] - end - attribute \src "libresoc.v:191774.3-191775.49" - process $proc$libresoc.v:191774$13280 - assign { } { } - assign $0\sram4k_0_wb__ack[0:0] \sram4k_0_wb__ack$next - sync posedge \clk - update \sram4k_0_wb__ack $0\sram4k_0_wb__ack[0:0] - end - attribute \src "libresoc.v:191783.3-191792.6" - process $proc$libresoc.v:191783$13281 - assign { } { } - assign { } { } - assign $0\wb_active[0:0] $1\wb_active[0:0] - attribute \src "libresoc.v:191784.5-191784.29" - switch \initial - attribute \src "libresoc.v:191784.9-191784.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wb_active[0:0] \$1 - case - assign $1\wb_active[0:0] 1'0 - end - sync always - update \wb_active $0\wb_active[0:0] - end - attribute \src "libresoc.v:191793.3-191807.6" - process $proc$libresoc.v:191793$13282 - assign { } { } - assign { } { } - assign { } { } - assign $0\sram4k_0_wb__ack$next[0:0]$13283 $2\sram4k_0_wb__ack$next[0:0]$13285 - attribute \src "libresoc.v:191794.5-191794.29" - switch \initial - attribute \src "libresoc.v:191794.9-191794.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sram4k_0_wb__ack$next[0:0]$13284 \wb_active - case - assign $1\sram4k_0_wb__ack$next[0:0]$13284 \sram4k_0_wb__ack - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sram4k_0_wb__ack$next[0:0]$13285 1'0 - case - assign $2\sram4k_0_wb__ack$next[0:0]$13285 $1\sram4k_0_wb__ack$next[0:0]$13284 - end - sync always - update \sram4k_0_wb__ack$next $0\sram4k_0_wb__ack$next[0:0]$13283 - end - attribute \src "libresoc.v:191808.3-191822.6" - process $proc$libresoc.v:191808$13286 - assign { } { } - assign { } { } - assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:191809.5-191809.29" - switch \initial - attribute \src "libresoc.v:191809.9-191809.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a[8:0] $2\a[8:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" - switch \wb_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\a[8:0] \sram4k_0_wb__adr - case - assign $2\a[8:0] 9'000000000 - end - case - assign $1\a[8:0] 9'000000000 - end - sync always - update \a $0\a[8:0] - end - attribute \src "libresoc.v:191823.3-191837.6" - process $proc$libresoc.v:191823$13287 - assign { } { } - assign { } { } - assign $0\sram4k_0_wb__dat_r[63:0] $1\sram4k_0_wb__dat_r[63:0] - attribute \src "libresoc.v:191824.5-191824.29" - switch \initial - attribute \src "libresoc.v:191824.9-191824.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sram4k_0_wb__dat_r[63:0] $2\sram4k_0_wb__dat_r[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" - switch \wb_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sram4k_0_wb__dat_r[63:0] \q - case - assign $2\sram4k_0_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\sram4k_0_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \sram4k_0_wb__dat_r $0\sram4k_0_wb__dat_r[63:0] - end - attribute \src "libresoc.v:191838.3-191852.6" - process $proc$libresoc.v:191838$13288 - assign { } { } - assign { } { } - assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:191839.5-191839.29" - switch \initial - attribute \src "libresoc.v:191839.9-191839.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\d[63:0] $2\d[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" - switch \wb_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\d[63:0] \sram4k_0_wb__dat_w - case - assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \d $0\d[63:0] - end - attribute \src "libresoc.v:191853.3-191872.6" - process $proc$libresoc.v:191853$13289 - assign { } { } - assign { } { } - assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:191854.5-191854.29" - switch \initial - attribute \src "libresoc.v:191854.9-191854.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\we[0:0] $2\we[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" - switch \wb_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\we[0:0] $3\we[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" - switch \sram4k_0_wb__we - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\we[0:0] \sram4k_0_wb__sel [0] - case - assign $3\we[0:0] 1'0 - end - case - assign $2\we[0:0] 1'0 - end - case - assign $1\we[0:0] 1'0 - end - sync always - update \we $0\we[0:0] - end - connect \$1 $and$libresoc.v:191773$13279_Y -end -attribute \src "libresoc.v:191877.1-192017.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.sram4k_1" -attribute \generator "nMigen" -module \sram4k_1 - attribute \src "libresoc.v:191952.3-191966.6" - wire width 9 $0\a[8:0] - attribute \src "libresoc.v:191982.3-191996.6" - wire width 64 $0\d[63:0] - attribute \src "libresoc.v:191878.7-191878.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:191937.3-191951.6" - wire $0\sram4k_1_wb__ack$next[0:0]$13296 - attribute \src "libresoc.v:191918.3-191919.49" - wire $0\sram4k_1_wb__ack[0:0] - attribute \src "libresoc.v:191967.3-191981.6" - wire width 64 $0\sram4k_1_wb__dat_r[63:0] - attribute \src "libresoc.v:191927.3-191936.6" - wire $0\wb_active[0:0] - attribute \src "libresoc.v:191997.3-192016.6" - wire $0\we[0:0] - attribute \src "libresoc.v:191952.3-191966.6" - wire width 9 $1\a[8:0] - attribute \src "libresoc.v:191982.3-191996.6" - wire width 64 $1\d[63:0] - attribute \src "libresoc.v:191937.3-191951.6" - wire $1\sram4k_1_wb__ack$next[0:0]$13297 - attribute \src "libresoc.v:191895.7-191895.30" - wire $1\sram4k_1_wb__ack[0:0] - attribute \src "libresoc.v:191967.3-191981.6" - wire width 64 $1\sram4k_1_wb__dat_r[63:0] - attribute \src "libresoc.v:191927.3-191936.6" - wire $1\wb_active[0:0] - attribute \src "libresoc.v:191997.3-192016.6" - wire $1\we[0:0] - attribute \src "libresoc.v:191952.3-191966.6" - wire width 9 $2\a[8:0] - attribute \src "libresoc.v:191982.3-191996.6" - wire width 64 $2\d[63:0] - attribute \src "libresoc.v:191937.3-191951.6" - wire $2\sram4k_1_wb__ack$next[0:0]$13298 - attribute \src "libresoc.v:191967.3-191981.6" - wire width 64 $2\sram4k_1_wb__dat_r[63:0] - attribute \src "libresoc.v:191997.3-192016.6" - wire $2\we[0:0] - attribute \src "libresoc.v:191997.3-192016.6" - wire $3\we[0:0] - attribute \src "libresoc.v:191917.17-191917.129" - wire $and$libresoc.v:191917$13292_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" - wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 11 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" - wire width 64 \d - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" - wire input 2 \enable - attribute \src "libresoc.v:191878.7-191878.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" - wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 5 \sram4k_1_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire \sram4k_1_wb__ack$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 6 \sram4k_1_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 3 \sram4k_1_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 7 \sram4k_1_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 8 \sram4k_1_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 10 \sram4k_1_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 4 \sram4k_1_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 9 \sram4k_1_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" - wire \wb_active - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" - wire \we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - cell $and $and$libresoc.v:191917$13292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sram4k_1_wb__cyc - connect \B \sram4k_1_wb__stb - connect \Y $and$libresoc.v:191917$13292_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:191920.21-191926.4" - cell \SPBlock_512W64B8W \U$$0 - connect \a \a - connect \clk \clk - connect \d \d - connect \q \q - connect \we \we - end - attribute \src "libresoc.v:191878.7-191878.20" - process $proc$libresoc.v:191878$13303 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:191895.7-191895.30" - process $proc$libresoc.v:191895$13304 - assign { } { } - assign $1\sram4k_1_wb__ack[0:0] 1'0 - sync always - sync init - update \sram4k_1_wb__ack $1\sram4k_1_wb__ack[0:0] - end - attribute \src "libresoc.v:191918.3-191919.49" - process $proc$libresoc.v:191918$13293 - assign { } { } - assign $0\sram4k_1_wb__ack[0:0] \sram4k_1_wb__ack$next - sync posedge \clk - update \sram4k_1_wb__ack $0\sram4k_1_wb__ack[0:0] - end - attribute \src "libresoc.v:191927.3-191936.6" - process $proc$libresoc.v:191927$13294 - assign { } { } - assign { } { } - assign $0\wb_active[0:0] $1\wb_active[0:0] - attribute \src "libresoc.v:191928.5-191928.29" - switch \initial - attribute \src "libresoc.v:191928.9-191928.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wb_active[0:0] \$1 - case - assign $1\wb_active[0:0] 1'0 - end - sync always - update \wb_active $0\wb_active[0:0] - end - attribute \src "libresoc.v:191937.3-191951.6" - process $proc$libresoc.v:191937$13295 - assign { } { } - assign { } { } - assign { } { } - assign $0\sram4k_1_wb__ack$next[0:0]$13296 $2\sram4k_1_wb__ack$next[0:0]$13298 - attribute \src "libresoc.v:191938.5-191938.29" - switch \initial - attribute \src "libresoc.v:191938.9-191938.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sram4k_1_wb__ack$next[0:0]$13297 \wb_active - case - assign $1\sram4k_1_wb__ack$next[0:0]$13297 \sram4k_1_wb__ack - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sram4k_1_wb__ack$next[0:0]$13298 1'0 - case - assign $2\sram4k_1_wb__ack$next[0:0]$13298 $1\sram4k_1_wb__ack$next[0:0]$13297 - end - sync always - update \sram4k_1_wb__ack$next $0\sram4k_1_wb__ack$next[0:0]$13296 - end - attribute \src "libresoc.v:191952.3-191966.6" - process $proc$libresoc.v:191952$13299 - assign { } { } - assign { } { } - assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:191953.5-191953.29" - switch \initial - attribute \src "libresoc.v:191953.9-191953.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a[8:0] $2\a[8:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" - switch \wb_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\a[8:0] \sram4k_1_wb__adr - case - assign $2\a[8:0] 9'000000000 - end - case - assign $1\a[8:0] 9'000000000 - end - sync always - update \a $0\a[8:0] - end - attribute \src "libresoc.v:191967.3-191981.6" - process $proc$libresoc.v:191967$13300 - assign { } { } - assign { } { } - assign $0\sram4k_1_wb__dat_r[63:0] $1\sram4k_1_wb__dat_r[63:0] - attribute \src "libresoc.v:191968.5-191968.29" - switch \initial - attribute \src "libresoc.v:191968.9-191968.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sram4k_1_wb__dat_r[63:0] $2\sram4k_1_wb__dat_r[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" - switch \wb_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sram4k_1_wb__dat_r[63:0] \q - case - assign $2\sram4k_1_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\sram4k_1_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \sram4k_1_wb__dat_r $0\sram4k_1_wb__dat_r[63:0] - end - attribute \src "libresoc.v:191982.3-191996.6" - process $proc$libresoc.v:191982$13301 - assign { } { } - assign { } { } - assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:191983.5-191983.29" - switch \initial - attribute \src "libresoc.v:191983.9-191983.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\d[63:0] $2\d[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" - switch \wb_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\d[63:0] \sram4k_1_wb__dat_w - case - assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \d $0\d[63:0] - end - attribute \src "libresoc.v:191997.3-192016.6" - process $proc$libresoc.v:191997$13302 - assign { } { } - assign { } { } - assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:191998.5-191998.29" - switch \initial - attribute \src "libresoc.v:191998.9-191998.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\we[0:0] $2\we[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" - switch \wb_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\we[0:0] $3\we[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" - switch \sram4k_1_wb__we - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\we[0:0] \sram4k_1_wb__sel [0] - case - assign $3\we[0:0] 1'0 - end - case - assign $2\we[0:0] 1'0 - end - case - assign $1\we[0:0] 1'0 - end - sync always - update \we $0\we[0:0] - end - connect \$1 $and$libresoc.v:191917$13292_Y -end -attribute \src "libresoc.v:192021.1-192161.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.sram4k_2" -attribute \generator "nMigen" -module \sram4k_2 - attribute \src "libresoc.v:192096.3-192110.6" - wire width 9 $0\a[8:0] - attribute \src "libresoc.v:192126.3-192140.6" - wire width 64 $0\d[63:0] - attribute \src "libresoc.v:192022.7-192022.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:192081.3-192095.6" - wire $0\sram4k_2_wb__ack$next[0:0]$13309 - attribute \src "libresoc.v:192062.3-192063.49" - wire $0\sram4k_2_wb__ack[0:0] - attribute \src "libresoc.v:192111.3-192125.6" - wire width 64 $0\sram4k_2_wb__dat_r[63:0] - attribute \src "libresoc.v:192071.3-192080.6" - wire $0\wb_active[0:0] - attribute \src "libresoc.v:192141.3-192160.6" - wire $0\we[0:0] - attribute \src "libresoc.v:192096.3-192110.6" - wire width 9 $1\a[8:0] - attribute \src "libresoc.v:192126.3-192140.6" - wire width 64 $1\d[63:0] - attribute \src "libresoc.v:192081.3-192095.6" - wire $1\sram4k_2_wb__ack$next[0:0]$13310 - attribute \src "libresoc.v:192039.7-192039.30" - wire $1\sram4k_2_wb__ack[0:0] - attribute \src "libresoc.v:192111.3-192125.6" - wire width 64 $1\sram4k_2_wb__dat_r[63:0] - attribute \src "libresoc.v:192071.3-192080.6" - wire $1\wb_active[0:0] - attribute \src "libresoc.v:192141.3-192160.6" - wire $1\we[0:0] - attribute \src "libresoc.v:192096.3-192110.6" - wire width 9 $2\a[8:0] - attribute \src "libresoc.v:192126.3-192140.6" - wire width 64 $2\d[63:0] - attribute \src "libresoc.v:192081.3-192095.6" - wire $2\sram4k_2_wb__ack$next[0:0]$13311 - attribute \src "libresoc.v:192111.3-192125.6" - wire width 64 $2\sram4k_2_wb__dat_r[63:0] - attribute \src "libresoc.v:192141.3-192160.6" - wire $2\we[0:0] - attribute \src "libresoc.v:192141.3-192160.6" - wire $3\we[0:0] - attribute \src "libresoc.v:192061.17-192061.129" - wire $and$libresoc.v:192061$13305_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" - wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 11 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" - wire width 64 \d - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" - wire input 2 \enable - attribute \src "libresoc.v:192022.7-192022.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" - wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 5 \sram4k_2_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire \sram4k_2_wb__ack$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 6 \sram4k_2_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 3 \sram4k_2_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 7 \sram4k_2_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 8 \sram4k_2_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 10 \sram4k_2_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 4 \sram4k_2_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 9 \sram4k_2_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" - wire \wb_active - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" - wire \we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - cell $and $and$libresoc.v:192061$13305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sram4k_2_wb__cyc - connect \B \sram4k_2_wb__stb - connect \Y $and$libresoc.v:192061$13305_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:192064.21-192070.4" - cell \SPBlock_512W64B8W \U$$0 - connect \a \a - connect \clk \clk - connect \d \d - connect \q \q - connect \we \we - end - attribute \src "libresoc.v:192022.7-192022.20" - process $proc$libresoc.v:192022$13316 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:192039.7-192039.30" - process $proc$libresoc.v:192039$13317 - assign { } { } - assign $1\sram4k_2_wb__ack[0:0] 1'0 - sync always - sync init - update \sram4k_2_wb__ack $1\sram4k_2_wb__ack[0:0] - end - attribute \src "libresoc.v:192062.3-192063.49" - process $proc$libresoc.v:192062$13306 - assign { } { } - assign $0\sram4k_2_wb__ack[0:0] \sram4k_2_wb__ack$next - sync posedge \clk - update \sram4k_2_wb__ack $0\sram4k_2_wb__ack[0:0] - end - attribute \src "libresoc.v:192071.3-192080.6" - process $proc$libresoc.v:192071$13307 - assign { } { } - assign { } { } - assign $0\wb_active[0:0] $1\wb_active[0:0] - attribute \src "libresoc.v:192072.5-192072.29" - switch \initial - attribute \src "libresoc.v:192072.9-192072.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wb_active[0:0] \$1 - case - assign $1\wb_active[0:0] 1'0 - end - sync always - update \wb_active $0\wb_active[0:0] - end - attribute \src "libresoc.v:192081.3-192095.6" - process $proc$libresoc.v:192081$13308 - assign { } { } - assign { } { } - assign { } { } - assign $0\sram4k_2_wb__ack$next[0:0]$13309 $2\sram4k_2_wb__ack$next[0:0]$13311 - attribute \src "libresoc.v:192082.5-192082.29" - switch \initial - attribute \src "libresoc.v:192082.9-192082.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sram4k_2_wb__ack$next[0:0]$13310 \wb_active - case - assign $1\sram4k_2_wb__ack$next[0:0]$13310 \sram4k_2_wb__ack - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sram4k_2_wb__ack$next[0:0]$13311 1'0 - case - assign $2\sram4k_2_wb__ack$next[0:0]$13311 $1\sram4k_2_wb__ack$next[0:0]$13310 - end - sync always - update \sram4k_2_wb__ack$next $0\sram4k_2_wb__ack$next[0:0]$13309 - end - attribute \src "libresoc.v:192096.3-192110.6" - process $proc$libresoc.v:192096$13312 - assign { } { } - assign { } { } - assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:192097.5-192097.29" - switch \initial - attribute \src "libresoc.v:192097.9-192097.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a[8:0] $2\a[8:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" - switch \wb_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\a[8:0] \sram4k_2_wb__adr - case - assign $2\a[8:0] 9'000000000 - end - case - assign $1\a[8:0] 9'000000000 - end - sync always - update \a $0\a[8:0] - end - attribute \src "libresoc.v:192111.3-192125.6" - process $proc$libresoc.v:192111$13313 - assign { } { } - assign { } { } - assign $0\sram4k_2_wb__dat_r[63:0] $1\sram4k_2_wb__dat_r[63:0] - attribute \src "libresoc.v:192112.5-192112.29" - switch \initial - attribute \src "libresoc.v:192112.9-192112.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sram4k_2_wb__dat_r[63:0] $2\sram4k_2_wb__dat_r[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" - switch \wb_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sram4k_2_wb__dat_r[63:0] \q - case - assign $2\sram4k_2_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\sram4k_2_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \sram4k_2_wb__dat_r $0\sram4k_2_wb__dat_r[63:0] - end - attribute \src "libresoc.v:192126.3-192140.6" - process $proc$libresoc.v:192126$13314 - assign { } { } - assign { } { } - assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:192127.5-192127.29" - switch \initial - attribute \src "libresoc.v:192127.9-192127.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\d[63:0] $2\d[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" - switch \wb_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\d[63:0] \sram4k_2_wb__dat_w - case - assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \d $0\d[63:0] - end - attribute \src "libresoc.v:192141.3-192160.6" - process $proc$libresoc.v:192141$13315 - assign { } { } - assign { } { } - assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:192142.5-192142.29" - switch \initial - attribute \src "libresoc.v:192142.9-192142.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\we[0:0] $2\we[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" - switch \wb_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\we[0:0] $3\we[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" - switch \sram4k_2_wb__we - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\we[0:0] \sram4k_2_wb__sel [0] - case - assign $3\we[0:0] 1'0 - end - case - assign $2\we[0:0] 1'0 - end - case - assign $1\we[0:0] 1'0 - end - sync always - update \we $0\we[0:0] - end - connect \$1 $and$libresoc.v:192061$13305_Y -end -attribute \src "libresoc.v:192165.1-192305.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.sram4k_3" -attribute \generator "nMigen" -module \sram4k_3 - attribute \src "libresoc.v:192240.3-192254.6" - wire width 9 $0\a[8:0] - attribute \src "libresoc.v:192270.3-192284.6" - wire width 64 $0\d[63:0] - attribute \src "libresoc.v:192166.7-192166.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:192225.3-192239.6" - wire $0\sram4k_3_wb__ack$next[0:0]$13322 - attribute \src "libresoc.v:192206.3-192207.49" - wire $0\sram4k_3_wb__ack[0:0] - attribute \src "libresoc.v:192255.3-192269.6" - wire width 64 $0\sram4k_3_wb__dat_r[63:0] - attribute \src "libresoc.v:192215.3-192224.6" - wire $0\wb_active[0:0] - attribute \src "libresoc.v:192285.3-192304.6" - wire $0\we[0:0] - attribute \src "libresoc.v:192240.3-192254.6" - wire width 9 $1\a[8:0] - attribute \src "libresoc.v:192270.3-192284.6" - wire width 64 $1\d[63:0] - attribute \src "libresoc.v:192225.3-192239.6" - wire $1\sram4k_3_wb__ack$next[0:0]$13323 - attribute \src "libresoc.v:192183.7-192183.30" - wire $1\sram4k_3_wb__ack[0:0] - attribute \src "libresoc.v:192255.3-192269.6" - wire width 64 $1\sram4k_3_wb__dat_r[63:0] - attribute \src "libresoc.v:192215.3-192224.6" - wire $1\wb_active[0:0] - attribute \src "libresoc.v:192285.3-192304.6" - wire $1\we[0:0] - attribute \src "libresoc.v:192240.3-192254.6" - wire width 9 $2\a[8:0] - attribute \src "libresoc.v:192270.3-192284.6" - wire width 64 $2\d[63:0] - attribute \src "libresoc.v:192225.3-192239.6" - wire $2\sram4k_3_wb__ack$next[0:0]$13324 - attribute \src "libresoc.v:192255.3-192269.6" - wire width 64 $2\sram4k_3_wb__dat_r[63:0] - attribute \src "libresoc.v:192285.3-192304.6" - wire $2\we[0:0] - attribute \src "libresoc.v:192285.3-192304.6" - wire $3\we[0:0] - attribute \src "libresoc.v:192205.17-192205.129" - wire $and$libresoc.v:192205$13318_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" - wire width 9 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 11 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" - wire width 64 \d - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" - wire input 2 \enable - attribute \src "libresoc.v:192166.7-192166.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" - wire width 64 \q - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 5 \sram4k_3_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire \sram4k_3_wb__ack$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 6 \sram4k_3_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 3 \sram4k_3_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 7 \sram4k_3_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 8 \sram4k_3_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 10 \sram4k_3_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 4 \sram4k_3_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 9 \sram4k_3_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:55" - wire \wb_active - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" - wire \we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" - cell $and $and$libresoc.v:192205$13318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sram4k_3_wb__cyc - connect \B \sram4k_3_wb__stb - connect \Y $and$libresoc.v:192205$13318_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:192208.21-192214.4" - cell \SPBlock_512W64B8W \U$$0 - connect \a \a - connect \clk \clk - connect \d \d - connect \q \q - connect \we \we - end - attribute \src "libresoc.v:192166.7-192166.20" - process $proc$libresoc.v:192166$13329 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:192183.7-192183.30" - process $proc$libresoc.v:192183$13330 - assign { } { } - assign $1\sram4k_3_wb__ack[0:0] 1'0 - sync always - sync init - update \sram4k_3_wb__ack $1\sram4k_3_wb__ack[0:0] - end - attribute \src "libresoc.v:192206.3-192207.49" - process $proc$libresoc.v:192206$13319 - assign { } { } - assign $0\sram4k_3_wb__ack[0:0] \sram4k_3_wb__ack$next - sync posedge \clk - update \sram4k_3_wb__ack $0\sram4k_3_wb__ack[0:0] - end - attribute \src "libresoc.v:192215.3-192224.6" - process $proc$libresoc.v:192215$13320 - assign { } { } - assign { } { } - assign $0\wb_active[0:0] $1\wb_active[0:0] - attribute \src "libresoc.v:192216.5-192216.29" - switch \initial - attribute \src "libresoc.v:192216.9-192216.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wb_active[0:0] \$1 - case - assign $1\wb_active[0:0] 1'0 - end - sync always - update \wb_active $0\wb_active[0:0] - end - attribute \src "libresoc.v:192225.3-192239.6" - process $proc$libresoc.v:192225$13321 - assign { } { } - assign { } { } - assign { } { } - assign $0\sram4k_3_wb__ack$next[0:0]$13322 $2\sram4k_3_wb__ack$next[0:0]$13324 - attribute \src "libresoc.v:192226.5-192226.29" - switch \initial - attribute \src "libresoc.v:192226.9-192226.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sram4k_3_wb__ack$next[0:0]$13323 \wb_active - case - assign $1\sram4k_3_wb__ack$next[0:0]$13323 \sram4k_3_wb__ack - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sram4k_3_wb__ack$next[0:0]$13324 1'0 - case - assign $2\sram4k_3_wb__ack$next[0:0]$13324 $1\sram4k_3_wb__ack$next[0:0]$13323 - end - sync always - update \sram4k_3_wb__ack$next $0\sram4k_3_wb__ack$next[0:0]$13322 - end - attribute \src "libresoc.v:192240.3-192254.6" - process $proc$libresoc.v:192240$13325 - assign { } { } - assign { } { } - assign $0\a[8:0] $1\a[8:0] - attribute \src "libresoc.v:192241.5-192241.29" - switch \initial - attribute \src "libresoc.v:192241.9-192241.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a[8:0] $2\a[8:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" - switch \wb_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\a[8:0] \sram4k_3_wb__adr - case - assign $2\a[8:0] 9'000000000 - end - case - assign $1\a[8:0] 9'000000000 - end - sync always - update \a $0\a[8:0] - end - attribute \src "libresoc.v:192255.3-192269.6" - process $proc$libresoc.v:192255$13326 - assign { } { } - assign { } { } - assign $0\sram4k_3_wb__dat_r[63:0] $1\sram4k_3_wb__dat_r[63:0] - attribute \src "libresoc.v:192256.5-192256.29" - switch \initial - attribute \src "libresoc.v:192256.9-192256.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sram4k_3_wb__dat_r[63:0] $2\sram4k_3_wb__dat_r[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" - switch \wb_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sram4k_3_wb__dat_r[63:0] \q - case - assign $2\sram4k_3_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\sram4k_3_wb__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \sram4k_3_wb__dat_r $0\sram4k_3_wb__dat_r[63:0] - end - attribute \src "libresoc.v:192270.3-192284.6" - process $proc$libresoc.v:192270$13327 - assign { } { } - assign { } { } - assign $0\d[63:0] $1\d[63:0] - attribute \src "libresoc.v:192271.5-192271.29" - switch \initial - attribute \src "libresoc.v:192271.9-192271.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\d[63:0] $2\d[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" - switch \wb_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\d[63:0] \sram4k_3_wb__dat_w - case - assign $2\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \d $0\d[63:0] - end - attribute \src "libresoc.v:192285.3-192304.6" - process $proc$libresoc.v:192285$13328 - assign { } { } - assign { } { } - assign $0\we[0:0] $1\we[0:0] - attribute \src "libresoc.v:192286.5-192286.29" - switch \initial - attribute \src "libresoc.v:192286.9-192286.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:53" - switch \enable - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\we[0:0] $2\we[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:61" - switch \wb_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\we[0:0] $3\we[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:71" - switch \sram4k_3_wb__we - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\we[0:0] \sram4k_3_wb__sel [0] - case - assign $3\we[0:0] 1'0 - end - case - assign $2\we[0:0] 1'0 - end - case - assign $1\we[0:0] 1'0 - end - sync always - update \we $0\we[0:0] - end - connect \$1 $and$libresoc.v:192205$13318_Y -end -attribute \src "libresoc.v:192309.1-192367.10" +attribute \src "libresoc.v:191732.1-191790.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.src_l" attribute \generator "nMigen" module \src_l - attribute \src "libresoc.v:192310.7-192310.20" + attribute \src "libresoc.v:191733.7-191733.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192355.3-192363.6" - wire width 4 $0\q_int$next[3:0]$13341 - attribute \src "libresoc.v:192353.3-192354.27" + attribute \src "libresoc.v:191778.3-191786.6" + wire width 4 $0\q_int$next[3:0]$13289 + attribute \src "libresoc.v:191776.3-191777.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:192355.3-192363.6" - wire width 4 $1\q_int$next[3:0]$13342 - attribute \src "libresoc.v:192332.13-192332.25" + attribute \src "libresoc.v:191778.3-191786.6" + wire width 4 $1\q_int$next[3:0]$13290 + attribute \src "libresoc.v:191755.13-191755.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:192345.17-192345.96" - wire width 4 $and$libresoc.v:192345$13331_Y - attribute \src "libresoc.v:192350.17-192350.96" - wire width 4 $and$libresoc.v:192350$13336_Y - attribute \src "libresoc.v:192347.18-192347.93" - wire width 4 $not$libresoc.v:192347$13333_Y - attribute \src "libresoc.v:192349.17-192349.92" - wire width 4 $not$libresoc.v:192349$13335_Y - attribute \src "libresoc.v:192352.17-192352.92" - wire width 4 $not$libresoc.v:192352$13338_Y - attribute \src "libresoc.v:192346.18-192346.98" - wire width 4 $or$libresoc.v:192346$13332_Y - attribute \src "libresoc.v:192348.18-192348.99" - wire width 4 $or$libresoc.v:192348$13334_Y - attribute \src "libresoc.v:192351.17-192351.97" - wire width 4 $or$libresoc.v:192351$13337_Y + attribute \src "libresoc.v:191768.17-191768.96" + wire width 4 $and$libresoc.v:191768$13279_Y + attribute \src "libresoc.v:191773.17-191773.96" + wire width 4 $and$libresoc.v:191773$13284_Y + attribute \src "libresoc.v:191770.18-191770.93" + wire width 4 $not$libresoc.v:191770$13281_Y + attribute \src "libresoc.v:191772.17-191772.92" + wire width 4 $not$libresoc.v:191772$13283_Y + attribute \src "libresoc.v:191775.17-191775.92" + wire width 4 $not$libresoc.v:191775$13286_Y + attribute \src "libresoc.v:191769.18-191769.98" + wire width 4 $or$libresoc.v:191769$13280_Y + attribute \src "libresoc.v:191771.18-191771.99" + wire width 4 $or$libresoc.v:191771$13282_Y + attribute \src "libresoc.v:191774.17-191774.97" + wire width 4 $or$libresoc.v:191774$13285_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -400535,7 +396045,7 @@ module \src_l wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:192310.7-192310.15" + attribute \src "libresoc.v:191733.7-191733.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -400552,7 +396062,7 @@ module \src_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192345$13331 + cell $and $and$libresoc.v:191768$13279 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -400560,10 +396070,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192345$13331_Y + connect \Y $and$libresoc.v:191768$13279_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192350$13336 + cell $and $and$libresoc.v:191773$13284 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -400571,34 +396081,34 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192350$13336_Y + connect \Y $and$libresoc.v:191773$13284_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192347$13333 + cell $not $not$libresoc.v:191770$13281 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:192347$13333_Y + connect \Y $not$libresoc.v:191770$13281_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192349$13335 + cell $not $not$libresoc.v:191772$13283 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:192349$13335_Y + connect \Y $not$libresoc.v:191772$13283_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192352$13338 + cell $not $not$libresoc.v:191775$13286 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:192352$13338_Y + connect \Y $not$libresoc.v:191775$13286_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192346$13332 + cell $or $or$libresoc.v:191769$13280 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -400606,10 +396116,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192346$13332_Y + connect \Y $or$libresoc.v:191769$13280_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192348$13334 + cell $or $or$libresoc.v:191771$13282 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -400617,10 +396127,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192348$13334_Y + connect \Y $or$libresoc.v:191771$13282_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192351$13337 + cell $or $or$libresoc.v:191774$13285 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -400628,39 +396138,39 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192351$13337_Y + connect \Y $or$libresoc.v:191774$13285_Y end - attribute \src "libresoc.v:192310.7-192310.20" - process $proc$libresoc.v:192310$13343 + attribute \src "libresoc.v:191733.7-191733.20" + process $proc$libresoc.v:191733$13291 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192332.13-192332.25" - process $proc$libresoc.v:192332$13344 + attribute \src "libresoc.v:191755.13-191755.25" + process $proc$libresoc.v:191755$13292 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:192353.3-192354.27" - process $proc$libresoc.v:192353$13339 + attribute \src "libresoc.v:191776.3-191777.27" + process $proc$libresoc.v:191776$13287 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:192355.3-192363.6" - process $proc$libresoc.v:192355$13340 + attribute \src "libresoc.v:191778.3-191786.6" + process $proc$libresoc.v:191778$13288 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13341 $1\q_int$next[3:0]$13342 - attribute \src "libresoc.v:192356.5-192356.29" + assign $0\q_int$next[3:0]$13289 $1\q_int$next[3:0]$13290 + attribute \src "libresoc.v:191779.5-191779.29" switch \initial - attribute \src "libresoc.v:192356.9-192356.17" + attribute \src "libresoc.v:191779.9-191779.17" case 1'1 case end @@ -400669,56 +396179,56 @@ module \src_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$13342 4'0000 + assign $1\q_int$next[3:0]$13290 4'0000 case - assign $1\q_int$next[3:0]$13342 \$5 + assign $1\q_int$next[3:0]$13290 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$13341 + update \q_int$next $0\q_int$next[3:0]$13289 end - connect \$9 $and$libresoc.v:192345$13331_Y - connect \$11 $or$libresoc.v:192346$13332_Y - connect \$13 $not$libresoc.v:192347$13333_Y - connect \$15 $or$libresoc.v:192348$13334_Y - connect \$1 $not$libresoc.v:192349$13335_Y - connect \$3 $and$libresoc.v:192350$13336_Y - connect \$5 $or$libresoc.v:192351$13337_Y - connect \$7 $not$libresoc.v:192352$13338_Y + connect \$9 $and$libresoc.v:191768$13279_Y + connect \$11 $or$libresoc.v:191769$13280_Y + connect \$13 $not$libresoc.v:191770$13281_Y + connect \$15 $or$libresoc.v:191771$13282_Y + connect \$1 $not$libresoc.v:191772$13283_Y + connect \$3 $and$libresoc.v:191773$13284_Y + connect \$5 $or$libresoc.v:191774$13285_Y + connect \$7 $not$libresoc.v:191775$13286_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192371.1-192429.10" +attribute \src "libresoc.v:191794.1-191852.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.src_l" attribute \generator "nMigen" module \src_l$10 - attribute \src "libresoc.v:192372.7-192372.20" + attribute \src "libresoc.v:191795.7-191795.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192417.3-192425.6" - wire width 6 $0\q_int$next[5:0]$13355 - attribute \src "libresoc.v:192415.3-192416.27" + attribute \src "libresoc.v:191840.3-191848.6" + wire width 6 $0\q_int$next[5:0]$13303 + attribute \src "libresoc.v:191838.3-191839.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:192417.3-192425.6" - wire width 6 $1\q_int$next[5:0]$13356 - attribute \src "libresoc.v:192394.13-192394.26" + attribute \src "libresoc.v:191840.3-191848.6" + wire width 6 $1\q_int$next[5:0]$13304 + attribute \src "libresoc.v:191817.13-191817.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:192407.17-192407.96" - wire width 6 $and$libresoc.v:192407$13345_Y - attribute \src "libresoc.v:192412.17-192412.96" - wire width 6 $and$libresoc.v:192412$13350_Y - attribute \src "libresoc.v:192409.18-192409.93" - wire width 6 $not$libresoc.v:192409$13347_Y - attribute \src "libresoc.v:192411.17-192411.92" - wire width 6 $not$libresoc.v:192411$13349_Y - attribute \src "libresoc.v:192414.17-192414.92" - wire width 6 $not$libresoc.v:192414$13352_Y - attribute \src "libresoc.v:192408.18-192408.98" - wire width 6 $or$libresoc.v:192408$13346_Y - attribute \src "libresoc.v:192410.18-192410.99" - wire width 6 $or$libresoc.v:192410$13348_Y - attribute \src "libresoc.v:192413.17-192413.97" - wire width 6 $or$libresoc.v:192413$13351_Y + attribute \src "libresoc.v:191830.17-191830.96" + wire width 6 $and$libresoc.v:191830$13293_Y + attribute \src "libresoc.v:191835.17-191835.96" + wire width 6 $and$libresoc.v:191835$13298_Y + attribute \src "libresoc.v:191832.18-191832.93" + wire width 6 $not$libresoc.v:191832$13295_Y + attribute \src "libresoc.v:191834.17-191834.92" + wire width 6 $not$libresoc.v:191834$13297_Y + attribute \src "libresoc.v:191837.17-191837.92" + wire width 6 $not$libresoc.v:191837$13300_Y + attribute \src "libresoc.v:191831.18-191831.98" + wire width 6 $or$libresoc.v:191831$13294_Y + attribute \src "libresoc.v:191833.18-191833.99" + wire width 6 $or$libresoc.v:191833$13296_Y + attribute \src "libresoc.v:191836.17-191836.97" + wire width 6 $or$libresoc.v:191836$13299_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -400739,7 +396249,7 @@ module \src_l$10 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:192372.7-192372.15" + attribute \src "libresoc.v:191795.7-191795.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -400756,7 +396266,7 @@ module \src_l$10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192407$13345 + cell $and $and$libresoc.v:191830$13293 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400764,10 +396274,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192407$13345_Y + connect \Y $and$libresoc.v:191830$13293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192412$13350 + cell $and $and$libresoc.v:191835$13298 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400775,34 +396285,34 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192412$13350_Y + connect \Y $and$libresoc.v:191835$13298_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192409$13347 + cell $not $not$libresoc.v:191832$13295 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:192409$13347_Y + connect \Y $not$libresoc.v:191832$13295_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192411$13349 + cell $not $not$libresoc.v:191834$13297 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:192411$13349_Y + connect \Y $not$libresoc.v:191834$13297_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192414$13352 + cell $not $not$libresoc.v:191837$13300 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:192414$13352_Y + connect \Y $not$libresoc.v:191837$13300_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192408$13346 + cell $or $or$libresoc.v:191831$13294 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400810,10 +396320,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192408$13346_Y + connect \Y $or$libresoc.v:191831$13294_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192410$13348 + cell $or $or$libresoc.v:191833$13296 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400821,10 +396331,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192410$13348_Y + connect \Y $or$libresoc.v:191833$13296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192413$13351 + cell $or $or$libresoc.v:191836$13299 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -400832,39 +396342,39 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192413$13351_Y + connect \Y $or$libresoc.v:191836$13299_Y end - attribute \src "libresoc.v:192372.7-192372.20" - process $proc$libresoc.v:192372$13357 + attribute \src "libresoc.v:191795.7-191795.20" + process $proc$libresoc.v:191795$13305 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192394.13-192394.26" - process $proc$libresoc.v:192394$13358 + attribute \src "libresoc.v:191817.13-191817.26" + process $proc$libresoc.v:191817$13306 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:192415.3-192416.27" - process $proc$libresoc.v:192415$13353 + attribute \src "libresoc.v:191838.3-191839.27" + process $proc$libresoc.v:191838$13301 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:192417.3-192425.6" - process $proc$libresoc.v:192417$13354 + attribute \src "libresoc.v:191840.3-191848.6" + process $proc$libresoc.v:191840$13302 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13355 $1\q_int$next[5:0]$13356 - attribute \src "libresoc.v:192418.5-192418.29" + assign $0\q_int$next[5:0]$13303 $1\q_int$next[5:0]$13304 + attribute \src "libresoc.v:191841.5-191841.29" switch \initial - attribute \src "libresoc.v:192418.9-192418.17" + attribute \src "libresoc.v:191841.9-191841.17" case 1'1 case end @@ -400873,56 +396383,56 @@ module \src_l$10 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$13356 6'000000 + assign $1\q_int$next[5:0]$13304 6'000000 case - assign $1\q_int$next[5:0]$13356 \$5 + assign $1\q_int$next[5:0]$13304 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$13355 + update \q_int$next $0\q_int$next[5:0]$13303 end - connect \$9 $and$libresoc.v:192407$13345_Y - connect \$11 $or$libresoc.v:192408$13346_Y - connect \$13 $not$libresoc.v:192409$13347_Y - connect \$15 $or$libresoc.v:192410$13348_Y - connect \$1 $not$libresoc.v:192411$13349_Y - connect \$3 $and$libresoc.v:192412$13350_Y - connect \$5 $or$libresoc.v:192413$13351_Y - connect \$7 $not$libresoc.v:192414$13352_Y + connect \$9 $and$libresoc.v:191830$13293_Y + connect \$11 $or$libresoc.v:191831$13294_Y + connect \$13 $not$libresoc.v:191832$13295_Y + connect \$15 $or$libresoc.v:191833$13296_Y + connect \$1 $not$libresoc.v:191834$13297_Y + connect \$3 $and$libresoc.v:191835$13298_Y + connect \$5 $or$libresoc.v:191836$13299_Y + connect \$7 $not$libresoc.v:191837$13300_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192433.1-192491.10" +attribute \src "libresoc.v:191856.1-191914.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.src_l" attribute \generator "nMigen" module \src_l$101 - attribute \src "libresoc.v:192434.7-192434.20" + attribute \src "libresoc.v:191857.7-191857.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192479.3-192487.6" - wire width 3 $0\q_int$next[2:0]$13369 - attribute \src "libresoc.v:192477.3-192478.27" + attribute \src "libresoc.v:191902.3-191910.6" + wire width 3 $0\q_int$next[2:0]$13317 + attribute \src "libresoc.v:191900.3-191901.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:192479.3-192487.6" - wire width 3 $1\q_int$next[2:0]$13370 - attribute \src "libresoc.v:192456.13-192456.25" + attribute \src "libresoc.v:191902.3-191910.6" + wire width 3 $1\q_int$next[2:0]$13318 + attribute \src "libresoc.v:191879.13-191879.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:192469.17-192469.96" - wire width 3 $and$libresoc.v:192469$13359_Y - attribute \src "libresoc.v:192474.17-192474.96" - wire width 3 $and$libresoc.v:192474$13364_Y - attribute \src "libresoc.v:192471.18-192471.93" - wire width 3 $not$libresoc.v:192471$13361_Y - attribute \src "libresoc.v:192473.17-192473.92" - wire width 3 $not$libresoc.v:192473$13363_Y - attribute \src "libresoc.v:192476.17-192476.92" - wire width 3 $not$libresoc.v:192476$13366_Y - attribute \src "libresoc.v:192470.18-192470.98" - wire width 3 $or$libresoc.v:192470$13360_Y - attribute \src "libresoc.v:192472.18-192472.99" - wire width 3 $or$libresoc.v:192472$13362_Y - attribute \src "libresoc.v:192475.17-192475.97" - wire width 3 $or$libresoc.v:192475$13365_Y + attribute \src "libresoc.v:191892.17-191892.96" + wire width 3 $and$libresoc.v:191892$13307_Y + attribute \src "libresoc.v:191897.17-191897.96" + wire width 3 $and$libresoc.v:191897$13312_Y + attribute \src "libresoc.v:191894.18-191894.93" + wire width 3 $not$libresoc.v:191894$13309_Y + attribute \src "libresoc.v:191896.17-191896.92" + wire width 3 $not$libresoc.v:191896$13311_Y + attribute \src "libresoc.v:191899.17-191899.92" + wire width 3 $not$libresoc.v:191899$13314_Y + attribute \src "libresoc.v:191893.18-191893.98" + wire width 3 $or$libresoc.v:191893$13308_Y + attribute \src "libresoc.v:191895.18-191895.99" + wire width 3 $or$libresoc.v:191895$13310_Y + attribute \src "libresoc.v:191898.17-191898.97" + wire width 3 $or$libresoc.v:191898$13313_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -400943,7 +396453,7 @@ module \src_l$101 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:192434.7-192434.15" + attribute \src "libresoc.v:191857.7-191857.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -400960,7 +396470,7 @@ module \src_l$101 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192469$13359 + cell $and $and$libresoc.v:191892$13307 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -400968,10 +396478,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192469$13359_Y + connect \Y $and$libresoc.v:191892$13307_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192474$13364 + cell $and $and$libresoc.v:191897$13312 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -400979,34 +396489,34 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192474$13364_Y + connect \Y $and$libresoc.v:191897$13312_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192471$13361 + cell $not $not$libresoc.v:191894$13309 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:192471$13361_Y + connect \Y $not$libresoc.v:191894$13309_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192473$13363 + cell $not $not$libresoc.v:191896$13311 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192473$13363_Y + connect \Y $not$libresoc.v:191896$13311_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192476$13366 + cell $not $not$libresoc.v:191899$13314 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192476$13366_Y + connect \Y $not$libresoc.v:191899$13314_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192470$13360 + cell $or $or$libresoc.v:191893$13308 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401014,10 +396524,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192470$13360_Y + connect \Y $or$libresoc.v:191893$13308_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192472$13362 + cell $or $or$libresoc.v:191895$13310 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401025,10 +396535,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192472$13362_Y + connect \Y $or$libresoc.v:191895$13310_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192475$13365 + cell $or $or$libresoc.v:191898$13313 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401036,39 +396546,39 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192475$13365_Y + connect \Y $or$libresoc.v:191898$13313_Y end - attribute \src "libresoc.v:192434.7-192434.20" - process $proc$libresoc.v:192434$13371 + attribute \src "libresoc.v:191857.7-191857.20" + process $proc$libresoc.v:191857$13319 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192456.13-192456.25" - process $proc$libresoc.v:192456$13372 + attribute \src "libresoc.v:191879.13-191879.25" + process $proc$libresoc.v:191879$13320 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:192477.3-192478.27" - process $proc$libresoc.v:192477$13367 + attribute \src "libresoc.v:191900.3-191901.27" + process $proc$libresoc.v:191900$13315 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:192479.3-192487.6" - process $proc$libresoc.v:192479$13368 + attribute \src "libresoc.v:191902.3-191910.6" + process $proc$libresoc.v:191902$13316 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13369 $1\q_int$next[2:0]$13370 - attribute \src "libresoc.v:192480.5-192480.29" + assign $0\q_int$next[2:0]$13317 $1\q_int$next[2:0]$13318 + attribute \src "libresoc.v:191903.5-191903.29" switch \initial - attribute \src "libresoc.v:192480.9-192480.17" + attribute \src "libresoc.v:191903.9-191903.17" case 1'1 case end @@ -401077,56 +396587,56 @@ module \src_l$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13370 3'000 + assign $1\q_int$next[2:0]$13318 3'000 case - assign $1\q_int$next[2:0]$13370 \$5 + assign $1\q_int$next[2:0]$13318 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13369 + update \q_int$next $0\q_int$next[2:0]$13317 end - connect \$9 $and$libresoc.v:192469$13359_Y - connect \$11 $or$libresoc.v:192470$13360_Y - connect \$13 $not$libresoc.v:192471$13361_Y - connect \$15 $or$libresoc.v:192472$13362_Y - connect \$1 $not$libresoc.v:192473$13363_Y - connect \$3 $and$libresoc.v:192474$13364_Y - connect \$5 $or$libresoc.v:192475$13365_Y - connect \$7 $not$libresoc.v:192476$13366_Y + connect \$9 $and$libresoc.v:191892$13307_Y + connect \$11 $or$libresoc.v:191893$13308_Y + connect \$13 $not$libresoc.v:191894$13309_Y + connect \$15 $or$libresoc.v:191895$13310_Y + connect \$1 $not$libresoc.v:191896$13311_Y + connect \$3 $and$libresoc.v:191897$13312_Y + connect \$5 $or$libresoc.v:191898$13313_Y + connect \$7 $not$libresoc.v:191899$13314_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192495.1-192553.10" +attribute \src "libresoc.v:191918.1-191976.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l" attribute \generator "nMigen" module \src_l$119 - attribute \src "libresoc.v:192496.7-192496.20" + attribute \src "libresoc.v:191919.7-191919.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192541.3-192549.6" - wire width 5 $0\q_int$next[4:0]$13383 - attribute \src "libresoc.v:192539.3-192540.27" + attribute \src "libresoc.v:191964.3-191972.6" + wire width 5 $0\q_int$next[4:0]$13331 + attribute \src "libresoc.v:191962.3-191963.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:192541.3-192549.6" - wire width 5 $1\q_int$next[4:0]$13384 - attribute \src "libresoc.v:192518.13-192518.26" + attribute \src "libresoc.v:191964.3-191972.6" + wire width 5 $1\q_int$next[4:0]$13332 + attribute \src "libresoc.v:191941.13-191941.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:192531.17-192531.96" - wire width 5 $and$libresoc.v:192531$13373_Y - attribute \src "libresoc.v:192536.17-192536.96" - wire width 5 $and$libresoc.v:192536$13378_Y - attribute \src "libresoc.v:192533.18-192533.93" - wire width 5 $not$libresoc.v:192533$13375_Y - attribute \src "libresoc.v:192535.17-192535.92" - wire width 5 $not$libresoc.v:192535$13377_Y - attribute \src "libresoc.v:192538.17-192538.92" - wire width 5 $not$libresoc.v:192538$13380_Y - attribute \src "libresoc.v:192532.18-192532.98" - wire width 5 $or$libresoc.v:192532$13374_Y - attribute \src "libresoc.v:192534.18-192534.99" - wire width 5 $or$libresoc.v:192534$13376_Y - attribute \src "libresoc.v:192537.17-192537.97" - wire width 5 $or$libresoc.v:192537$13379_Y + attribute \src "libresoc.v:191954.17-191954.96" + wire width 5 $and$libresoc.v:191954$13321_Y + attribute \src "libresoc.v:191959.17-191959.96" + wire width 5 $and$libresoc.v:191959$13326_Y + attribute \src "libresoc.v:191956.18-191956.93" + wire width 5 $not$libresoc.v:191956$13323_Y + attribute \src "libresoc.v:191958.17-191958.92" + wire width 5 $not$libresoc.v:191958$13325_Y + attribute \src "libresoc.v:191961.17-191961.92" + wire width 5 $not$libresoc.v:191961$13328_Y + attribute \src "libresoc.v:191955.18-191955.98" + wire width 5 $or$libresoc.v:191955$13322_Y + attribute \src "libresoc.v:191957.18-191957.99" + wire width 5 $or$libresoc.v:191957$13324_Y + attribute \src "libresoc.v:191960.17-191960.97" + wire width 5 $or$libresoc.v:191960$13327_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -401147,7 +396657,7 @@ module \src_l$119 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:192496.7-192496.15" + attribute \src "libresoc.v:191919.7-191919.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -401164,7 +396674,7 @@ module \src_l$119 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192531$13373 + cell $and $and$libresoc.v:191954$13321 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -401172,10 +396682,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192531$13373_Y + connect \Y $and$libresoc.v:191954$13321_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192536$13378 + cell $and $and$libresoc.v:191959$13326 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -401183,34 +396693,34 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192536$13378_Y + connect \Y $and$libresoc.v:191959$13326_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192533$13375 + cell $not $not$libresoc.v:191956$13323 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_src - connect \Y $not$libresoc.v:192533$13375_Y + connect \Y $not$libresoc.v:191956$13323_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192535$13377 + cell $not $not$libresoc.v:191958$13325 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:192535$13377_Y + connect \Y $not$libresoc.v:191958$13325_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192538$13380 + cell $not $not$libresoc.v:191961$13328 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:192538$13380_Y + connect \Y $not$libresoc.v:191961$13328_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192532$13374 + cell $or $or$libresoc.v:191955$13322 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -401218,10 +396728,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192532$13374_Y + connect \Y $or$libresoc.v:191955$13322_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192534$13376 + cell $or $or$libresoc.v:191957$13324 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -401229,10 +396739,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192534$13376_Y + connect \Y $or$libresoc.v:191957$13324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192537$13379 + cell $or $or$libresoc.v:191960$13327 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -401240,39 +396750,39 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192537$13379_Y + connect \Y $or$libresoc.v:191960$13327_Y end - attribute \src "libresoc.v:192496.7-192496.20" - process $proc$libresoc.v:192496$13385 + attribute \src "libresoc.v:191919.7-191919.20" + process $proc$libresoc.v:191919$13333 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192518.13-192518.26" - process $proc$libresoc.v:192518$13386 + attribute \src "libresoc.v:191941.13-191941.26" + process $proc$libresoc.v:191941$13334 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:192539.3-192540.27" - process $proc$libresoc.v:192539$13381 + attribute \src "libresoc.v:191962.3-191963.27" + process $proc$libresoc.v:191962$13329 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:192541.3-192549.6" - process $proc$libresoc.v:192541$13382 + attribute \src "libresoc.v:191964.3-191972.6" + process $proc$libresoc.v:191964$13330 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$13383 $1\q_int$next[4:0]$13384 - attribute \src "libresoc.v:192542.5-192542.29" + assign $0\q_int$next[4:0]$13331 $1\q_int$next[4:0]$13332 + attribute \src "libresoc.v:191965.5-191965.29" switch \initial - attribute \src "libresoc.v:192542.9-192542.17" + attribute \src "libresoc.v:191965.9-191965.17" case 1'1 case end @@ -401281,56 +396791,56 @@ module \src_l$119 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$13384 5'00000 + assign $1\q_int$next[4:0]$13332 5'00000 case - assign $1\q_int$next[4:0]$13384 \$5 + assign $1\q_int$next[4:0]$13332 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$13383 + update \q_int$next $0\q_int$next[4:0]$13331 end - connect \$9 $and$libresoc.v:192531$13373_Y - connect \$11 $or$libresoc.v:192532$13374_Y - connect \$13 $not$libresoc.v:192533$13375_Y - connect \$15 $or$libresoc.v:192534$13376_Y - connect \$1 $not$libresoc.v:192535$13377_Y - connect \$3 $and$libresoc.v:192536$13378_Y - connect \$5 $or$libresoc.v:192537$13379_Y - connect \$7 $not$libresoc.v:192538$13380_Y + connect \$9 $and$libresoc.v:191954$13321_Y + connect \$11 $or$libresoc.v:191955$13322_Y + connect \$13 $not$libresoc.v:191956$13323_Y + connect \$15 $or$libresoc.v:191957$13324_Y + connect \$1 $not$libresoc.v:191958$13325_Y + connect \$3 $and$libresoc.v:191959$13326_Y + connect \$5 $or$libresoc.v:191960$13327_Y + connect \$7 $not$libresoc.v:191961$13328_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192557.1-192615.10" +attribute \src "libresoc.v:191980.1-192038.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l" attribute \generator "nMigen" module \src_l$127 - attribute \src "libresoc.v:192558.7-192558.20" + attribute \src "libresoc.v:191981.7-191981.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192603.3-192611.6" - wire width 3 $0\q_int$next[2:0]$13397 - attribute \src "libresoc.v:192601.3-192602.27" + attribute \src "libresoc.v:192026.3-192034.6" + wire width 3 $0\q_int$next[2:0]$13345 + attribute \src "libresoc.v:192024.3-192025.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:192603.3-192611.6" - wire width 3 $1\q_int$next[2:0]$13398 - attribute \src "libresoc.v:192580.13-192580.25" + attribute \src "libresoc.v:192026.3-192034.6" + wire width 3 $1\q_int$next[2:0]$13346 + attribute \src "libresoc.v:192003.13-192003.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:192593.17-192593.96" - wire width 3 $and$libresoc.v:192593$13387_Y - attribute \src "libresoc.v:192598.17-192598.96" - wire width 3 $and$libresoc.v:192598$13392_Y - attribute \src "libresoc.v:192595.18-192595.93" - wire width 3 $not$libresoc.v:192595$13389_Y - attribute \src "libresoc.v:192597.17-192597.92" - wire width 3 $not$libresoc.v:192597$13391_Y - attribute \src "libresoc.v:192600.17-192600.92" - wire width 3 $not$libresoc.v:192600$13394_Y - attribute \src "libresoc.v:192594.18-192594.98" - wire width 3 $or$libresoc.v:192594$13388_Y - attribute \src "libresoc.v:192596.18-192596.99" - wire width 3 $or$libresoc.v:192596$13390_Y - attribute \src "libresoc.v:192599.17-192599.97" - wire width 3 $or$libresoc.v:192599$13393_Y + attribute \src "libresoc.v:192016.17-192016.96" + wire width 3 $and$libresoc.v:192016$13335_Y + attribute \src "libresoc.v:192021.17-192021.96" + wire width 3 $and$libresoc.v:192021$13340_Y + attribute \src "libresoc.v:192018.18-192018.93" + wire width 3 $not$libresoc.v:192018$13337_Y + attribute \src "libresoc.v:192020.17-192020.92" + wire width 3 $not$libresoc.v:192020$13339_Y + attribute \src "libresoc.v:192023.17-192023.92" + wire width 3 $not$libresoc.v:192023$13342_Y + attribute \src "libresoc.v:192017.18-192017.98" + wire width 3 $or$libresoc.v:192017$13336_Y + attribute \src "libresoc.v:192019.18-192019.99" + wire width 3 $or$libresoc.v:192019$13338_Y + attribute \src "libresoc.v:192022.17-192022.97" + wire width 3 $or$libresoc.v:192022$13341_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -401351,7 +396861,7 @@ module \src_l$127 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:192558.7-192558.15" + attribute \src "libresoc.v:191981.7-191981.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -401368,7 +396878,7 @@ module \src_l$127 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192593$13387 + cell $and $and$libresoc.v:192016$13335 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401376,10 +396886,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192593$13387_Y + connect \Y $and$libresoc.v:192016$13335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192598$13392 + cell $and $and$libresoc.v:192021$13340 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401387,34 +396897,34 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192598$13392_Y + connect \Y $and$libresoc.v:192021$13340_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192595$13389 + cell $not $not$libresoc.v:192018$13337 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:192595$13389_Y + connect \Y $not$libresoc.v:192018$13337_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192597$13391 + cell $not $not$libresoc.v:192020$13339 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192597$13391_Y + connect \Y $not$libresoc.v:192020$13339_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192600$13394 + cell $not $not$libresoc.v:192023$13342 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192600$13394_Y + connect \Y $not$libresoc.v:192023$13342_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192594$13388 + cell $or $or$libresoc.v:192017$13336 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401422,10 +396932,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192594$13388_Y + connect \Y $or$libresoc.v:192017$13336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192596$13390 + cell $or $or$libresoc.v:192019$13338 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401433,10 +396943,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192596$13390_Y + connect \Y $or$libresoc.v:192019$13338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192599$13393 + cell $or $or$libresoc.v:192022$13341 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401444,39 +396954,39 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192599$13393_Y + connect \Y $or$libresoc.v:192022$13341_Y end - attribute \src "libresoc.v:192558.7-192558.20" - process $proc$libresoc.v:192558$13399 + attribute \src "libresoc.v:191981.7-191981.20" + process $proc$libresoc.v:191981$13347 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192580.13-192580.25" - process $proc$libresoc.v:192580$13400 + attribute \src "libresoc.v:192003.13-192003.25" + process $proc$libresoc.v:192003$13348 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:192601.3-192602.27" - process $proc$libresoc.v:192601$13395 + attribute \src "libresoc.v:192024.3-192025.27" + process $proc$libresoc.v:192024$13343 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:192603.3-192611.6" - process $proc$libresoc.v:192603$13396 + attribute \src "libresoc.v:192026.3-192034.6" + process $proc$libresoc.v:192026$13344 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13397 $1\q_int$next[2:0]$13398 - attribute \src "libresoc.v:192604.5-192604.29" + assign $0\q_int$next[2:0]$13345 $1\q_int$next[2:0]$13346 + attribute \src "libresoc.v:192027.5-192027.29" switch \initial - attribute \src "libresoc.v:192604.9-192604.17" + attribute \src "libresoc.v:192027.9-192027.17" case 1'1 case end @@ -401485,56 +396995,56 @@ module \src_l$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13398 3'000 + assign $1\q_int$next[2:0]$13346 3'000 case - assign $1\q_int$next[2:0]$13398 \$5 + assign $1\q_int$next[2:0]$13346 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13397 + update \q_int$next $0\q_int$next[2:0]$13345 end - connect \$9 $and$libresoc.v:192593$13387_Y - connect \$11 $or$libresoc.v:192594$13388_Y - connect \$13 $not$libresoc.v:192595$13389_Y - connect \$15 $or$libresoc.v:192596$13390_Y - connect \$1 $not$libresoc.v:192597$13391_Y - connect \$3 $and$libresoc.v:192598$13392_Y - connect \$5 $or$libresoc.v:192599$13393_Y - connect \$7 $not$libresoc.v:192600$13394_Y + connect \$9 $and$libresoc.v:192016$13335_Y + connect \$11 $or$libresoc.v:192017$13336_Y + connect \$13 $not$libresoc.v:192018$13337_Y + connect \$15 $or$libresoc.v:192019$13338_Y + connect \$1 $not$libresoc.v:192020$13339_Y + connect \$3 $and$libresoc.v:192021$13340_Y + connect \$5 $or$libresoc.v:192022$13341_Y + connect \$7 $not$libresoc.v:192023$13342_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192619.1-192677.10" +attribute \src "libresoc.v:192042.1-192100.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.src_l" attribute \generator "nMigen" module \src_l$23 - attribute \src "libresoc.v:192620.7-192620.20" + attribute \src "libresoc.v:192043.7-192043.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192665.3-192673.6" - wire width 3 $0\q_int$next[2:0]$13411 - attribute \src "libresoc.v:192663.3-192664.27" + attribute \src "libresoc.v:192088.3-192096.6" + wire width 3 $0\q_int$next[2:0]$13359 + attribute \src "libresoc.v:192086.3-192087.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:192665.3-192673.6" - wire width 3 $1\q_int$next[2:0]$13412 - attribute \src "libresoc.v:192642.13-192642.25" + attribute \src "libresoc.v:192088.3-192096.6" + wire width 3 $1\q_int$next[2:0]$13360 + attribute \src "libresoc.v:192065.13-192065.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:192655.17-192655.96" - wire width 3 $and$libresoc.v:192655$13401_Y - attribute \src "libresoc.v:192660.17-192660.96" - wire width 3 $and$libresoc.v:192660$13406_Y - attribute \src "libresoc.v:192657.18-192657.93" - wire width 3 $not$libresoc.v:192657$13403_Y - attribute \src "libresoc.v:192659.17-192659.92" - wire width 3 $not$libresoc.v:192659$13405_Y - attribute \src "libresoc.v:192662.17-192662.92" - wire width 3 $not$libresoc.v:192662$13408_Y - attribute \src "libresoc.v:192656.18-192656.98" - wire width 3 $or$libresoc.v:192656$13402_Y - attribute \src "libresoc.v:192658.18-192658.99" - wire width 3 $or$libresoc.v:192658$13404_Y - attribute \src "libresoc.v:192661.17-192661.97" - wire width 3 $or$libresoc.v:192661$13407_Y + attribute \src "libresoc.v:192078.17-192078.96" + wire width 3 $and$libresoc.v:192078$13349_Y + attribute \src "libresoc.v:192083.17-192083.96" + wire width 3 $and$libresoc.v:192083$13354_Y + attribute \src "libresoc.v:192080.18-192080.93" + wire width 3 $not$libresoc.v:192080$13351_Y + attribute \src "libresoc.v:192082.17-192082.92" + wire width 3 $not$libresoc.v:192082$13353_Y + attribute \src "libresoc.v:192085.17-192085.92" + wire width 3 $not$libresoc.v:192085$13356_Y + attribute \src "libresoc.v:192079.18-192079.98" + wire width 3 $or$libresoc.v:192079$13350_Y + attribute \src "libresoc.v:192081.18-192081.99" + wire width 3 $or$libresoc.v:192081$13352_Y + attribute \src "libresoc.v:192084.17-192084.97" + wire width 3 $or$libresoc.v:192084$13355_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -401555,7 +397065,7 @@ module \src_l$23 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:192620.7-192620.15" + attribute \src "libresoc.v:192043.7-192043.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -401572,7 +397082,7 @@ module \src_l$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192655$13401 + cell $and $and$libresoc.v:192078$13349 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401580,10 +397090,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192655$13401_Y + connect \Y $and$libresoc.v:192078$13349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192660$13406 + cell $and $and$libresoc.v:192083$13354 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401591,34 +397101,34 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192660$13406_Y + connect \Y $and$libresoc.v:192083$13354_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192657$13403 + cell $not $not$libresoc.v:192080$13351 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:192657$13403_Y + connect \Y $not$libresoc.v:192080$13351_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192659$13405 + cell $not $not$libresoc.v:192082$13353 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192659$13405_Y + connect \Y $not$libresoc.v:192082$13353_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192662$13408 + cell $not $not$libresoc.v:192085$13356 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192662$13408_Y + connect \Y $not$libresoc.v:192085$13356_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192656$13402 + cell $or $or$libresoc.v:192079$13350 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401626,10 +397136,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192656$13402_Y + connect \Y $or$libresoc.v:192079$13350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192658$13404 + cell $or $or$libresoc.v:192081$13352 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401637,10 +397147,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192658$13404_Y + connect \Y $or$libresoc.v:192081$13352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192661$13407 + cell $or $or$libresoc.v:192084$13355 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401648,39 +397158,39 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192661$13407_Y + connect \Y $or$libresoc.v:192084$13355_Y end - attribute \src "libresoc.v:192620.7-192620.20" - process $proc$libresoc.v:192620$13413 + attribute \src "libresoc.v:192043.7-192043.20" + process $proc$libresoc.v:192043$13361 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192642.13-192642.25" - process $proc$libresoc.v:192642$13414 + attribute \src "libresoc.v:192065.13-192065.25" + process $proc$libresoc.v:192065$13362 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:192663.3-192664.27" - process $proc$libresoc.v:192663$13409 + attribute \src "libresoc.v:192086.3-192087.27" + process $proc$libresoc.v:192086$13357 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:192665.3-192673.6" - process $proc$libresoc.v:192665$13410 + attribute \src "libresoc.v:192088.3-192096.6" + process $proc$libresoc.v:192088$13358 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13411 $1\q_int$next[2:0]$13412 - attribute \src "libresoc.v:192666.5-192666.29" + assign $0\q_int$next[2:0]$13359 $1\q_int$next[2:0]$13360 + attribute \src "libresoc.v:192089.5-192089.29" switch \initial - attribute \src "libresoc.v:192666.9-192666.17" + attribute \src "libresoc.v:192089.9-192089.17" case 1'1 case end @@ -401689,56 +397199,56 @@ module \src_l$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13412 3'000 + assign $1\q_int$next[2:0]$13360 3'000 case - assign $1\q_int$next[2:0]$13412 \$5 + assign $1\q_int$next[2:0]$13360 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13411 + update \q_int$next $0\q_int$next[2:0]$13359 end - connect \$9 $and$libresoc.v:192655$13401_Y - connect \$11 $or$libresoc.v:192656$13402_Y - connect \$13 $not$libresoc.v:192657$13403_Y - connect \$15 $or$libresoc.v:192658$13404_Y - connect \$1 $not$libresoc.v:192659$13405_Y - connect \$3 $and$libresoc.v:192660$13406_Y - connect \$5 $or$libresoc.v:192661$13407_Y - connect \$7 $not$libresoc.v:192662$13408_Y + connect \$9 $and$libresoc.v:192078$13349_Y + connect \$11 $or$libresoc.v:192079$13350_Y + connect \$13 $not$libresoc.v:192080$13351_Y + connect \$15 $or$libresoc.v:192081$13352_Y + connect \$1 $not$libresoc.v:192082$13353_Y + connect \$3 $and$libresoc.v:192083$13354_Y + connect \$5 $or$libresoc.v:192084$13355_Y + connect \$7 $not$libresoc.v:192085$13356_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192681.1-192739.10" +attribute \src "libresoc.v:192104.1-192162.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.src_l" attribute \generator "nMigen" module \src_l$39 - attribute \src "libresoc.v:192682.7-192682.20" + attribute \src "libresoc.v:192105.7-192105.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192727.3-192735.6" - wire width 4 $0\q_int$next[3:0]$13425 - attribute \src "libresoc.v:192725.3-192726.27" + attribute \src "libresoc.v:192150.3-192158.6" + wire width 4 $0\q_int$next[3:0]$13373 + attribute \src "libresoc.v:192148.3-192149.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:192727.3-192735.6" - wire width 4 $1\q_int$next[3:0]$13426 - attribute \src "libresoc.v:192704.13-192704.25" + attribute \src "libresoc.v:192150.3-192158.6" + wire width 4 $1\q_int$next[3:0]$13374 + attribute \src "libresoc.v:192127.13-192127.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:192717.17-192717.96" - wire width 4 $and$libresoc.v:192717$13415_Y - attribute \src "libresoc.v:192722.17-192722.96" - wire width 4 $and$libresoc.v:192722$13420_Y - attribute \src "libresoc.v:192719.18-192719.93" - wire width 4 $not$libresoc.v:192719$13417_Y - attribute \src "libresoc.v:192721.17-192721.92" - wire width 4 $not$libresoc.v:192721$13419_Y - attribute \src "libresoc.v:192724.17-192724.92" - wire width 4 $not$libresoc.v:192724$13422_Y - attribute \src "libresoc.v:192718.18-192718.98" - wire width 4 $or$libresoc.v:192718$13416_Y - attribute \src "libresoc.v:192720.18-192720.99" - wire width 4 $or$libresoc.v:192720$13418_Y - attribute \src "libresoc.v:192723.17-192723.97" - wire width 4 $or$libresoc.v:192723$13421_Y + attribute \src "libresoc.v:192140.17-192140.96" + wire width 4 $and$libresoc.v:192140$13363_Y + attribute \src "libresoc.v:192145.17-192145.96" + wire width 4 $and$libresoc.v:192145$13368_Y + attribute \src "libresoc.v:192142.18-192142.93" + wire width 4 $not$libresoc.v:192142$13365_Y + attribute \src "libresoc.v:192144.17-192144.92" + wire width 4 $not$libresoc.v:192144$13367_Y + attribute \src "libresoc.v:192147.17-192147.92" + wire width 4 $not$libresoc.v:192147$13370_Y + attribute \src "libresoc.v:192141.18-192141.98" + wire width 4 $or$libresoc.v:192141$13364_Y + attribute \src "libresoc.v:192143.18-192143.99" + wire width 4 $or$libresoc.v:192143$13366_Y + attribute \src "libresoc.v:192146.17-192146.97" + wire width 4 $or$libresoc.v:192146$13369_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -401759,7 +397269,7 @@ module \src_l$39 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:192682.7-192682.15" + attribute \src "libresoc.v:192105.7-192105.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -401776,7 +397286,7 @@ module \src_l$39 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192717$13415 + cell $and $and$libresoc.v:192140$13363 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -401784,10 +397294,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192717$13415_Y + connect \Y $and$libresoc.v:192140$13363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192722$13420 + cell $and $and$libresoc.v:192145$13368 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -401795,34 +397305,34 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192722$13420_Y + connect \Y $and$libresoc.v:192145$13368_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192719$13417 + cell $not $not$libresoc.v:192142$13365 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:192719$13417_Y + connect \Y $not$libresoc.v:192142$13365_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192721$13419 + cell $not $not$libresoc.v:192144$13367 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:192721$13419_Y + connect \Y $not$libresoc.v:192144$13367_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192724$13422 + cell $not $not$libresoc.v:192147$13370 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:192724$13422_Y + connect \Y $not$libresoc.v:192147$13370_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192718$13416 + cell $or $or$libresoc.v:192141$13364 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -401830,10 +397340,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192718$13416_Y + connect \Y $or$libresoc.v:192141$13364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192720$13418 + cell $or $or$libresoc.v:192143$13366 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -401841,10 +397351,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192720$13418_Y + connect \Y $or$libresoc.v:192143$13366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192723$13421 + cell $or $or$libresoc.v:192146$13369 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -401852,39 +397362,39 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192723$13421_Y + connect \Y $or$libresoc.v:192146$13369_Y end - attribute \src "libresoc.v:192682.7-192682.20" - process $proc$libresoc.v:192682$13427 + attribute \src "libresoc.v:192105.7-192105.20" + process $proc$libresoc.v:192105$13375 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192704.13-192704.25" - process $proc$libresoc.v:192704$13428 + attribute \src "libresoc.v:192127.13-192127.25" + process $proc$libresoc.v:192127$13376 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:192725.3-192726.27" - process $proc$libresoc.v:192725$13423 + attribute \src "libresoc.v:192148.3-192149.27" + process $proc$libresoc.v:192148$13371 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:192727.3-192735.6" - process $proc$libresoc.v:192727$13424 + attribute \src "libresoc.v:192150.3-192158.6" + process $proc$libresoc.v:192150$13372 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13425 $1\q_int$next[3:0]$13426 - attribute \src "libresoc.v:192728.5-192728.29" + assign $0\q_int$next[3:0]$13373 $1\q_int$next[3:0]$13374 + attribute \src "libresoc.v:192151.5-192151.29" switch \initial - attribute \src "libresoc.v:192728.9-192728.17" + attribute \src "libresoc.v:192151.9-192151.17" case 1'1 case end @@ -401893,56 +397403,56 @@ module \src_l$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$13426 4'0000 + assign $1\q_int$next[3:0]$13374 4'0000 case - assign $1\q_int$next[3:0]$13426 \$5 + assign $1\q_int$next[3:0]$13374 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$13425 + update \q_int$next $0\q_int$next[3:0]$13373 end - connect \$9 $and$libresoc.v:192717$13415_Y - connect \$11 $or$libresoc.v:192718$13416_Y - connect \$13 $not$libresoc.v:192719$13417_Y - connect \$15 $or$libresoc.v:192720$13418_Y - connect \$1 $not$libresoc.v:192721$13419_Y - connect \$3 $and$libresoc.v:192722$13420_Y - connect \$5 $or$libresoc.v:192723$13421_Y - connect \$7 $not$libresoc.v:192724$13422_Y + connect \$9 $and$libresoc.v:192140$13363_Y + connect \$11 $or$libresoc.v:192141$13364_Y + connect \$13 $not$libresoc.v:192142$13365_Y + connect \$15 $or$libresoc.v:192143$13366_Y + connect \$1 $not$libresoc.v:192144$13367_Y + connect \$3 $and$libresoc.v:192145$13368_Y + connect \$5 $or$libresoc.v:192146$13369_Y + connect \$7 $not$libresoc.v:192147$13370_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192743.1-192801.10" +attribute \src "libresoc.v:192166.1-192224.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.src_l" attribute \generator "nMigen" module \src_l$55 - attribute \src "libresoc.v:192744.7-192744.20" + attribute \src "libresoc.v:192167.7-192167.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192789.3-192797.6" - wire width 3 $0\q_int$next[2:0]$13439 - attribute \src "libresoc.v:192787.3-192788.27" + attribute \src "libresoc.v:192212.3-192220.6" + wire width 3 $0\q_int$next[2:0]$13387 + attribute \src "libresoc.v:192210.3-192211.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:192789.3-192797.6" - wire width 3 $1\q_int$next[2:0]$13440 - attribute \src "libresoc.v:192766.13-192766.25" + attribute \src "libresoc.v:192212.3-192220.6" + wire width 3 $1\q_int$next[2:0]$13388 + attribute \src "libresoc.v:192189.13-192189.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:192779.17-192779.96" - wire width 3 $and$libresoc.v:192779$13429_Y - attribute \src "libresoc.v:192784.17-192784.96" - wire width 3 $and$libresoc.v:192784$13434_Y - attribute \src "libresoc.v:192781.18-192781.93" - wire width 3 $not$libresoc.v:192781$13431_Y - attribute \src "libresoc.v:192783.17-192783.92" - wire width 3 $not$libresoc.v:192783$13433_Y - attribute \src "libresoc.v:192786.17-192786.92" - wire width 3 $not$libresoc.v:192786$13436_Y - attribute \src "libresoc.v:192780.18-192780.98" - wire width 3 $or$libresoc.v:192780$13430_Y - attribute \src "libresoc.v:192782.18-192782.99" - wire width 3 $or$libresoc.v:192782$13432_Y - attribute \src "libresoc.v:192785.17-192785.97" - wire width 3 $or$libresoc.v:192785$13435_Y + attribute \src "libresoc.v:192202.17-192202.96" + wire width 3 $and$libresoc.v:192202$13377_Y + attribute \src "libresoc.v:192207.17-192207.96" + wire width 3 $and$libresoc.v:192207$13382_Y + attribute \src "libresoc.v:192204.18-192204.93" + wire width 3 $not$libresoc.v:192204$13379_Y + attribute \src "libresoc.v:192206.17-192206.92" + wire width 3 $not$libresoc.v:192206$13381_Y + attribute \src "libresoc.v:192209.17-192209.92" + wire width 3 $not$libresoc.v:192209$13384_Y + attribute \src "libresoc.v:192203.18-192203.98" + wire width 3 $or$libresoc.v:192203$13378_Y + attribute \src "libresoc.v:192205.18-192205.99" + wire width 3 $or$libresoc.v:192205$13380_Y + attribute \src "libresoc.v:192208.17-192208.97" + wire width 3 $or$libresoc.v:192208$13383_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -401963,7 +397473,7 @@ module \src_l$55 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:192744.7-192744.15" + attribute \src "libresoc.v:192167.7-192167.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -401980,7 +397490,7 @@ module \src_l$55 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192779$13429 + cell $and $and$libresoc.v:192202$13377 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401988,10 +397498,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192779$13429_Y + connect \Y $and$libresoc.v:192202$13377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192784$13434 + cell $and $and$libresoc.v:192207$13382 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -401999,34 +397509,34 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192784$13434_Y + connect \Y $and$libresoc.v:192207$13382_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192781$13431 + cell $not $not$libresoc.v:192204$13379 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:192781$13431_Y + connect \Y $not$libresoc.v:192204$13379_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192783$13433 + cell $not $not$libresoc.v:192206$13381 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192783$13433_Y + connect \Y $not$libresoc.v:192206$13381_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192786$13436 + cell $not $not$libresoc.v:192209$13384 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192786$13436_Y + connect \Y $not$libresoc.v:192209$13384_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192780$13430 + cell $or $or$libresoc.v:192203$13378 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -402034,10 +397544,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192780$13430_Y + connect \Y $or$libresoc.v:192203$13378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192782$13432 + cell $or $or$libresoc.v:192205$13380 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -402045,10 +397555,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192782$13432_Y + connect \Y $or$libresoc.v:192205$13380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192785$13435 + cell $or $or$libresoc.v:192208$13383 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -402056,39 +397566,39 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192785$13435_Y + connect \Y $or$libresoc.v:192208$13383_Y end - attribute \src "libresoc.v:192744.7-192744.20" - process $proc$libresoc.v:192744$13441 + attribute \src "libresoc.v:192167.7-192167.20" + process $proc$libresoc.v:192167$13389 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192766.13-192766.25" - process $proc$libresoc.v:192766$13442 + attribute \src "libresoc.v:192189.13-192189.25" + process $proc$libresoc.v:192189$13390 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:192787.3-192788.27" - process $proc$libresoc.v:192787$13437 + attribute \src "libresoc.v:192210.3-192211.27" + process $proc$libresoc.v:192210$13385 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:192789.3-192797.6" - process $proc$libresoc.v:192789$13438 + attribute \src "libresoc.v:192212.3-192220.6" + process $proc$libresoc.v:192212$13386 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13439 $1\q_int$next[2:0]$13440 - attribute \src "libresoc.v:192790.5-192790.29" + assign $0\q_int$next[2:0]$13387 $1\q_int$next[2:0]$13388 + attribute \src "libresoc.v:192213.5-192213.29" switch \initial - attribute \src "libresoc.v:192790.9-192790.17" + attribute \src "libresoc.v:192213.9-192213.17" case 1'1 case end @@ -402097,56 +397607,56 @@ module \src_l$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13440 3'000 + assign $1\q_int$next[2:0]$13388 3'000 case - assign $1\q_int$next[2:0]$13440 \$5 + assign $1\q_int$next[2:0]$13388 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13439 + update \q_int$next $0\q_int$next[2:0]$13387 end - connect \$9 $and$libresoc.v:192779$13429_Y - connect \$11 $or$libresoc.v:192780$13430_Y - connect \$13 $not$libresoc.v:192781$13431_Y - connect \$15 $or$libresoc.v:192782$13432_Y - connect \$1 $not$libresoc.v:192783$13433_Y - connect \$3 $and$libresoc.v:192784$13434_Y - connect \$5 $or$libresoc.v:192785$13435_Y - connect \$7 $not$libresoc.v:192786$13436_Y + connect \$9 $and$libresoc.v:192202$13377_Y + connect \$11 $or$libresoc.v:192203$13378_Y + connect \$13 $not$libresoc.v:192204$13379_Y + connect \$15 $or$libresoc.v:192205$13380_Y + connect \$1 $not$libresoc.v:192206$13381_Y + connect \$3 $and$libresoc.v:192207$13382_Y + connect \$5 $or$libresoc.v:192208$13383_Y + connect \$7 $not$libresoc.v:192209$13384_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192805.1-192863.10" +attribute \src "libresoc.v:192228.1-192286.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.src_l" attribute \generator "nMigen" module \src_l$67 - attribute \src "libresoc.v:192806.7-192806.20" + attribute \src "libresoc.v:192229.7-192229.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192851.3-192859.6" - wire width 6 $0\q_int$next[5:0]$13453 - attribute \src "libresoc.v:192849.3-192850.27" + attribute \src "libresoc.v:192274.3-192282.6" + wire width 6 $0\q_int$next[5:0]$13401 + attribute \src "libresoc.v:192272.3-192273.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:192851.3-192859.6" - wire width 6 $1\q_int$next[5:0]$13454 - attribute \src "libresoc.v:192828.13-192828.26" + attribute \src "libresoc.v:192274.3-192282.6" + wire width 6 $1\q_int$next[5:0]$13402 + attribute \src "libresoc.v:192251.13-192251.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:192841.17-192841.96" - wire width 6 $and$libresoc.v:192841$13443_Y - attribute \src "libresoc.v:192846.17-192846.96" - wire width 6 $and$libresoc.v:192846$13448_Y - attribute \src "libresoc.v:192843.18-192843.93" - wire width 6 $not$libresoc.v:192843$13445_Y - attribute \src "libresoc.v:192845.17-192845.92" - wire width 6 $not$libresoc.v:192845$13447_Y - attribute \src "libresoc.v:192848.17-192848.92" - wire width 6 $not$libresoc.v:192848$13450_Y - attribute \src "libresoc.v:192842.18-192842.98" - wire width 6 $or$libresoc.v:192842$13444_Y - attribute \src "libresoc.v:192844.18-192844.99" - wire width 6 $or$libresoc.v:192844$13446_Y - attribute \src "libresoc.v:192847.17-192847.97" - wire width 6 $or$libresoc.v:192847$13449_Y + attribute \src "libresoc.v:192264.17-192264.96" + wire width 6 $and$libresoc.v:192264$13391_Y + attribute \src "libresoc.v:192269.17-192269.96" + wire width 6 $and$libresoc.v:192269$13396_Y + attribute \src "libresoc.v:192266.18-192266.93" + wire width 6 $not$libresoc.v:192266$13393_Y + attribute \src "libresoc.v:192268.17-192268.92" + wire width 6 $not$libresoc.v:192268$13395_Y + attribute \src "libresoc.v:192271.17-192271.92" + wire width 6 $not$libresoc.v:192271$13398_Y + attribute \src "libresoc.v:192265.18-192265.98" + wire width 6 $or$libresoc.v:192265$13392_Y + attribute \src "libresoc.v:192267.18-192267.99" + wire width 6 $or$libresoc.v:192267$13394_Y + attribute \src "libresoc.v:192270.17-192270.97" + wire width 6 $or$libresoc.v:192270$13397_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -402167,7 +397677,7 @@ module \src_l$67 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:192806.7-192806.15" + attribute \src "libresoc.v:192229.7-192229.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -402184,7 +397694,7 @@ module \src_l$67 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192841$13443 + cell $and $and$libresoc.v:192264$13391 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -402192,10 +397702,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192841$13443_Y + connect \Y $and$libresoc.v:192264$13391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192846$13448 + cell $and $and$libresoc.v:192269$13396 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -402203,34 +397713,34 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192846$13448_Y + connect \Y $and$libresoc.v:192269$13396_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192843$13445 + cell $not $not$libresoc.v:192266$13393 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:192843$13445_Y + connect \Y $not$libresoc.v:192266$13393_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192845$13447 + cell $not $not$libresoc.v:192268$13395 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:192845$13447_Y + connect \Y $not$libresoc.v:192268$13395_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192848$13450 + cell $not $not$libresoc.v:192271$13398 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:192848$13450_Y + connect \Y $not$libresoc.v:192271$13398_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192842$13444 + cell $or $or$libresoc.v:192265$13392 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -402238,10 +397748,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192842$13444_Y + connect \Y $or$libresoc.v:192265$13392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192844$13446 + cell $or $or$libresoc.v:192267$13394 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -402249,10 +397759,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192844$13446_Y + connect \Y $or$libresoc.v:192267$13394_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192847$13449 + cell $or $or$libresoc.v:192270$13397 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -402260,39 +397770,39 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192847$13449_Y + connect \Y $or$libresoc.v:192270$13397_Y end - attribute \src "libresoc.v:192806.7-192806.20" - process $proc$libresoc.v:192806$13455 + attribute \src "libresoc.v:192229.7-192229.20" + process $proc$libresoc.v:192229$13403 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192828.13-192828.26" - process $proc$libresoc.v:192828$13456 + attribute \src "libresoc.v:192251.13-192251.26" + process $proc$libresoc.v:192251$13404 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:192849.3-192850.27" - process $proc$libresoc.v:192849$13451 + attribute \src "libresoc.v:192272.3-192273.27" + process $proc$libresoc.v:192272$13399 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:192851.3-192859.6" - process $proc$libresoc.v:192851$13452 + attribute \src "libresoc.v:192274.3-192282.6" + process $proc$libresoc.v:192274$13400 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13453 $1\q_int$next[5:0]$13454 - attribute \src "libresoc.v:192852.5-192852.29" + assign $0\q_int$next[5:0]$13401 $1\q_int$next[5:0]$13402 + attribute \src "libresoc.v:192275.5-192275.29" switch \initial - attribute \src "libresoc.v:192852.9-192852.17" + attribute \src "libresoc.v:192275.9-192275.17" case 1'1 case end @@ -402301,56 +397811,56 @@ module \src_l$67 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$13454 6'000000 + assign $1\q_int$next[5:0]$13402 6'000000 case - assign $1\q_int$next[5:0]$13454 \$5 + assign $1\q_int$next[5:0]$13402 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$13453 + update \q_int$next $0\q_int$next[5:0]$13401 end - connect \$9 $and$libresoc.v:192841$13443_Y - connect \$11 $or$libresoc.v:192842$13444_Y - connect \$13 $not$libresoc.v:192843$13445_Y - connect \$15 $or$libresoc.v:192844$13446_Y - connect \$1 $not$libresoc.v:192845$13447_Y - connect \$3 $and$libresoc.v:192846$13448_Y - connect \$5 $or$libresoc.v:192847$13449_Y - connect \$7 $not$libresoc.v:192848$13450_Y + connect \$9 $and$libresoc.v:192264$13391_Y + connect \$11 $or$libresoc.v:192265$13392_Y + connect \$13 $not$libresoc.v:192266$13393_Y + connect \$15 $or$libresoc.v:192267$13394_Y + connect \$1 $not$libresoc.v:192268$13395_Y + connect \$3 $and$libresoc.v:192269$13396_Y + connect \$5 $or$libresoc.v:192270$13397_Y + connect \$7 $not$libresoc.v:192271$13398_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192867.1-192925.10" +attribute \src "libresoc.v:192290.1-192348.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l" attribute \generator "nMigen" module \src_l$84 - attribute \src "libresoc.v:192868.7-192868.20" + attribute \src "libresoc.v:192291.7-192291.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192913.3-192921.6" - wire width 3 $0\q_int$next[2:0]$13467 - attribute \src "libresoc.v:192911.3-192912.27" + attribute \src "libresoc.v:192336.3-192344.6" + wire width 3 $0\q_int$next[2:0]$13415 + attribute \src "libresoc.v:192334.3-192335.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:192913.3-192921.6" - wire width 3 $1\q_int$next[2:0]$13468 - attribute \src "libresoc.v:192890.13-192890.25" + attribute \src "libresoc.v:192336.3-192344.6" + wire width 3 $1\q_int$next[2:0]$13416 + attribute \src "libresoc.v:192313.13-192313.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:192903.17-192903.96" - wire width 3 $and$libresoc.v:192903$13457_Y - attribute \src "libresoc.v:192908.17-192908.96" - wire width 3 $and$libresoc.v:192908$13462_Y - attribute \src "libresoc.v:192905.18-192905.93" - wire width 3 $not$libresoc.v:192905$13459_Y - attribute \src "libresoc.v:192907.17-192907.92" - wire width 3 $not$libresoc.v:192907$13461_Y - attribute \src "libresoc.v:192910.17-192910.92" - wire width 3 $not$libresoc.v:192910$13464_Y - attribute \src "libresoc.v:192904.18-192904.98" - wire width 3 $or$libresoc.v:192904$13458_Y - attribute \src "libresoc.v:192906.18-192906.99" - wire width 3 $or$libresoc.v:192906$13460_Y - attribute \src "libresoc.v:192909.17-192909.97" - wire width 3 $or$libresoc.v:192909$13463_Y + attribute \src "libresoc.v:192326.17-192326.96" + wire width 3 $and$libresoc.v:192326$13405_Y + attribute \src "libresoc.v:192331.17-192331.96" + wire width 3 $and$libresoc.v:192331$13410_Y + attribute \src "libresoc.v:192328.18-192328.93" + wire width 3 $not$libresoc.v:192328$13407_Y + attribute \src "libresoc.v:192330.17-192330.92" + wire width 3 $not$libresoc.v:192330$13409_Y + attribute \src "libresoc.v:192333.17-192333.92" + wire width 3 $not$libresoc.v:192333$13412_Y + attribute \src "libresoc.v:192327.18-192327.98" + wire width 3 $or$libresoc.v:192327$13406_Y + attribute \src "libresoc.v:192329.18-192329.99" + wire width 3 $or$libresoc.v:192329$13408_Y + attribute \src "libresoc.v:192332.17-192332.97" + wire width 3 $or$libresoc.v:192332$13411_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -402371,7 +397881,7 @@ module \src_l$84 wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:192868.7-192868.15" + attribute \src "libresoc.v:192291.7-192291.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -402388,7 +397898,7 @@ module \src_l$84 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192903$13457 + cell $and $and$libresoc.v:192326$13405 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -402396,10 +397906,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192903$13457_Y + connect \Y $and$libresoc.v:192326$13405_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192908$13462 + cell $and $and$libresoc.v:192331$13410 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -402407,34 +397917,34 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192908$13462_Y + connect \Y $and$libresoc.v:192331$13410_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192905$13459 + cell $not $not$libresoc.v:192328$13407 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:192905$13459_Y + connect \Y $not$libresoc.v:192328$13407_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192907$13461 + cell $not $not$libresoc.v:192330$13409 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192907$13461_Y + connect \Y $not$libresoc.v:192330$13409_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192910$13464 + cell $not $not$libresoc.v:192333$13412 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192910$13464_Y + connect \Y $not$libresoc.v:192333$13412_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192904$13458 + cell $or $or$libresoc.v:192327$13406 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -402442,10 +397952,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192904$13458_Y + connect \Y $or$libresoc.v:192327$13406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192906$13460 + cell $or $or$libresoc.v:192329$13408 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -402453,10 +397963,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192906$13460_Y + connect \Y $or$libresoc.v:192329$13408_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192909$13463 + cell $or $or$libresoc.v:192332$13411 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -402464,39 +397974,39 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192909$13463_Y + connect \Y $or$libresoc.v:192332$13411_Y end - attribute \src "libresoc.v:192868.7-192868.20" - process $proc$libresoc.v:192868$13469 + attribute \src "libresoc.v:192291.7-192291.20" + process $proc$libresoc.v:192291$13417 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192890.13-192890.25" - process $proc$libresoc.v:192890$13470 + attribute \src "libresoc.v:192313.13-192313.25" + process $proc$libresoc.v:192313$13418 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:192911.3-192912.27" - process $proc$libresoc.v:192911$13465 + attribute \src "libresoc.v:192334.3-192335.27" + process $proc$libresoc.v:192334$13413 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:192913.3-192921.6" - process $proc$libresoc.v:192913$13466 + attribute \src "libresoc.v:192336.3-192344.6" + process $proc$libresoc.v:192336$13414 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13467 $1\q_int$next[2:0]$13468 - attribute \src "libresoc.v:192914.5-192914.29" + assign $0\q_int$next[2:0]$13415 $1\q_int$next[2:0]$13416 + attribute \src "libresoc.v:192337.5-192337.29" switch \initial - attribute \src "libresoc.v:192914.9-192914.17" + attribute \src "libresoc.v:192337.9-192337.17" case 1'1 case end @@ -402505,56 +398015,56 @@ module \src_l$84 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13468 3'000 + assign $1\q_int$next[2:0]$13416 3'000 case - assign $1\q_int$next[2:0]$13468 \$5 + assign $1\q_int$next[2:0]$13416 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13467 + update \q_int$next $0\q_int$next[2:0]$13415 end - connect \$9 $and$libresoc.v:192903$13457_Y - connect \$11 $or$libresoc.v:192904$13458_Y - connect \$13 $not$libresoc.v:192905$13459_Y - connect \$15 $or$libresoc.v:192906$13460_Y - connect \$1 $not$libresoc.v:192907$13461_Y - connect \$3 $and$libresoc.v:192908$13462_Y - connect \$5 $or$libresoc.v:192909$13463_Y - connect \$7 $not$libresoc.v:192910$13464_Y + connect \$9 $and$libresoc.v:192326$13405_Y + connect \$11 $or$libresoc.v:192327$13406_Y + connect \$13 $not$libresoc.v:192328$13407_Y + connect \$15 $or$libresoc.v:192329$13408_Y + connect \$1 $not$libresoc.v:192330$13409_Y + connect \$3 $and$libresoc.v:192331$13410_Y + connect \$5 $or$libresoc.v:192332$13411_Y + connect \$7 $not$libresoc.v:192333$13412_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192929.1-192987.10" +attribute \src "libresoc.v:192352.1-192410.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_active" attribute \generator "nMigen" module \st_active - attribute \src "libresoc.v:192930.7-192930.20" + attribute \src "libresoc.v:192353.7-192353.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192975.3-192983.6" - wire $0\q_int$next[0:0]$13481 - attribute \src "libresoc.v:192973.3-192974.27" + attribute \src "libresoc.v:192398.3-192406.6" + wire $0\q_int$next[0:0]$13429 + attribute \src "libresoc.v:192396.3-192397.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:192975.3-192983.6" - wire $1\q_int$next[0:0]$13482 - attribute \src "libresoc.v:192952.7-192952.19" + attribute \src "libresoc.v:192398.3-192406.6" + wire $1\q_int$next[0:0]$13430 + attribute \src "libresoc.v:192375.7-192375.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:192965.17-192965.96" - wire $and$libresoc.v:192965$13471_Y - attribute \src "libresoc.v:192970.17-192970.96" - wire $and$libresoc.v:192970$13476_Y - attribute \src "libresoc.v:192967.18-192967.99" - wire $not$libresoc.v:192967$13473_Y - attribute \src "libresoc.v:192969.17-192969.98" - wire $not$libresoc.v:192969$13475_Y - attribute \src "libresoc.v:192972.17-192972.98" - wire $not$libresoc.v:192972$13478_Y - attribute \src "libresoc.v:192966.18-192966.104" - wire $or$libresoc.v:192966$13472_Y - attribute \src "libresoc.v:192968.18-192968.105" - wire $or$libresoc.v:192968$13474_Y - attribute \src "libresoc.v:192971.17-192971.103" - wire $or$libresoc.v:192971$13477_Y + attribute \src "libresoc.v:192388.17-192388.96" + wire $and$libresoc.v:192388$13419_Y + attribute \src "libresoc.v:192393.17-192393.96" + wire $and$libresoc.v:192393$13424_Y + attribute \src "libresoc.v:192390.18-192390.99" + wire $not$libresoc.v:192390$13421_Y + attribute \src "libresoc.v:192392.17-192392.98" + wire $not$libresoc.v:192392$13423_Y + attribute \src "libresoc.v:192395.17-192395.98" + wire $not$libresoc.v:192395$13426_Y + attribute \src "libresoc.v:192389.18-192389.104" + wire $or$libresoc.v:192389$13420_Y + attribute \src "libresoc.v:192391.18-192391.105" + wire $or$libresoc.v:192391$13422_Y + attribute \src "libresoc.v:192394.17-192394.103" + wire $or$libresoc.v:192394$13425_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -402575,7 +398085,7 @@ module \st_active wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:192930.7-192930.15" + attribute \src "libresoc.v:192353.7-192353.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -402592,7 +398102,7 @@ module \st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192965$13471 + cell $and $and$libresoc.v:192388$13419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402600,10 +398110,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192965$13471_Y + connect \Y $and$libresoc.v:192388$13419_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192970$13476 + cell $and $and$libresoc.v:192393$13424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402611,34 +398121,34 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192970$13476_Y + connect \Y $and$libresoc.v:192393$13424_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192967$13473 + cell $not $not$libresoc.v:192390$13421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_active - connect \Y $not$libresoc.v:192967$13473_Y + connect \Y $not$libresoc.v:192390$13421_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192969$13475 + cell $not $not$libresoc.v:192392$13423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:192969$13475_Y + connect \Y $not$libresoc.v:192392$13423_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192972$13478 + cell $not $not$libresoc.v:192395$13426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:192972$13478_Y + connect \Y $not$libresoc.v:192395$13426_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192966$13472 + cell $or $or$libresoc.v:192389$13420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402646,10 +398156,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_active - connect \Y $or$libresoc.v:192966$13472_Y + connect \Y $or$libresoc.v:192389$13420_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192968$13474 + cell $or $or$libresoc.v:192391$13422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402657,10 +398167,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_st_active connect \B \q_int - connect \Y $or$libresoc.v:192968$13474_Y + connect \Y $or$libresoc.v:192391$13422_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192971$13477 + cell $or $or$libresoc.v:192394$13425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402668,39 +398178,39 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_active - connect \Y $or$libresoc.v:192971$13477_Y + connect \Y $or$libresoc.v:192394$13425_Y end - attribute \src "libresoc.v:192930.7-192930.20" - process $proc$libresoc.v:192930$13483 + attribute \src "libresoc.v:192353.7-192353.20" + process $proc$libresoc.v:192353$13431 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192952.7-192952.19" - process $proc$libresoc.v:192952$13484 + attribute \src "libresoc.v:192375.7-192375.19" + process $proc$libresoc.v:192375$13432 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:192973.3-192974.27" - process $proc$libresoc.v:192973$13479 + attribute \src "libresoc.v:192396.3-192397.27" + process $proc$libresoc.v:192396$13427 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:192975.3-192983.6" - process $proc$libresoc.v:192975$13480 + attribute \src "libresoc.v:192398.3-192406.6" + process $proc$libresoc.v:192398$13428 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13481 $1\q_int$next[0:0]$13482 - attribute \src "libresoc.v:192976.5-192976.29" + assign $0\q_int$next[0:0]$13429 $1\q_int$next[0:0]$13430 + attribute \src "libresoc.v:192399.5-192399.29" switch \initial - attribute \src "libresoc.v:192976.9-192976.17" + attribute \src "libresoc.v:192399.9-192399.17" case 1'1 case end @@ -402709,56 +398219,56 @@ module \st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13482 1'0 + assign $1\q_int$next[0:0]$13430 1'0 case - assign $1\q_int$next[0:0]$13482 \$5 + assign $1\q_int$next[0:0]$13430 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13481 + update \q_int$next $0\q_int$next[0:0]$13429 end - connect \$9 $and$libresoc.v:192965$13471_Y - connect \$11 $or$libresoc.v:192966$13472_Y - connect \$13 $not$libresoc.v:192967$13473_Y - connect \$15 $or$libresoc.v:192968$13474_Y - connect \$1 $not$libresoc.v:192969$13475_Y - connect \$3 $and$libresoc.v:192970$13476_Y - connect \$5 $or$libresoc.v:192971$13477_Y - connect \$7 $not$libresoc.v:192972$13478_Y + connect \$9 $and$libresoc.v:192388$13419_Y + connect \$11 $or$libresoc.v:192389$13420_Y + connect \$13 $not$libresoc.v:192390$13421_Y + connect \$15 $or$libresoc.v:192391$13422_Y + connect \$1 $not$libresoc.v:192392$13423_Y + connect \$3 $and$libresoc.v:192393$13424_Y + connect \$5 $or$libresoc.v:192394$13425_Y + connect \$7 $not$libresoc.v:192395$13426_Y connect \qlq_st_active \$15 connect \qn_st_active \$13 connect \q_st_active \$11 end -attribute \src "libresoc.v:192991.1-193049.10" +attribute \src "libresoc.v:192414.1-192472.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_done" attribute \generator "nMigen" module \st_done - attribute \src "libresoc.v:192992.7-192992.20" + attribute \src "libresoc.v:192415.7-192415.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193037.3-193045.6" - wire $0\q_int$next[0:0]$13495 - attribute \src "libresoc.v:193035.3-193036.27" + attribute \src "libresoc.v:192460.3-192468.6" + wire $0\q_int$next[0:0]$13443 + attribute \src "libresoc.v:192458.3-192459.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:193037.3-193045.6" - wire $1\q_int$next[0:0]$13496 - attribute \src "libresoc.v:193014.7-193014.19" + attribute \src "libresoc.v:192460.3-192468.6" + wire $1\q_int$next[0:0]$13444 + attribute \src "libresoc.v:192437.7-192437.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:193027.17-193027.96" - wire $and$libresoc.v:193027$13485_Y - attribute \src "libresoc.v:193032.17-193032.96" - wire $and$libresoc.v:193032$13490_Y - attribute \src "libresoc.v:193029.18-193029.97" - wire $not$libresoc.v:193029$13487_Y - attribute \src "libresoc.v:193031.17-193031.96" - wire $not$libresoc.v:193031$13489_Y - attribute \src "libresoc.v:193034.17-193034.96" - wire $not$libresoc.v:193034$13492_Y - attribute \src "libresoc.v:193028.18-193028.102" - wire $or$libresoc.v:193028$13486_Y - attribute \src "libresoc.v:193030.18-193030.103" - wire $or$libresoc.v:193030$13488_Y - attribute \src "libresoc.v:193033.17-193033.101" - wire $or$libresoc.v:193033$13491_Y + attribute \src "libresoc.v:192450.17-192450.96" + wire $and$libresoc.v:192450$13433_Y + attribute \src "libresoc.v:192455.17-192455.96" + wire $and$libresoc.v:192455$13438_Y + attribute \src "libresoc.v:192452.18-192452.97" + wire $not$libresoc.v:192452$13435_Y + attribute \src "libresoc.v:192454.17-192454.96" + wire $not$libresoc.v:192454$13437_Y + attribute \src "libresoc.v:192457.17-192457.96" + wire $not$libresoc.v:192457$13440_Y + attribute \src "libresoc.v:192451.18-192451.102" + wire $or$libresoc.v:192451$13434_Y + attribute \src "libresoc.v:192453.18-192453.103" + wire $or$libresoc.v:192453$13436_Y + attribute \src "libresoc.v:192456.17-192456.101" + wire $or$libresoc.v:192456$13439_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -402779,7 +398289,7 @@ module \st_done wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:192992.7-192992.15" + attribute \src "libresoc.v:192415.7-192415.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -402796,7 +398306,7 @@ module \st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:193027$13485 + cell $and $and$libresoc.v:192450$13433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402804,10 +398314,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:193027$13485_Y + connect \Y $and$libresoc.v:192450$13433_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:193032$13490 + cell $and $and$libresoc.v:192455$13438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402815,34 +398325,34 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:193032$13490_Y + connect \Y $and$libresoc.v:192455$13438_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:193029$13487 + cell $not $not$libresoc.v:192452$13435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_done - connect \Y $not$libresoc.v:193029$13487_Y + connect \Y $not$libresoc.v:192452$13435_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:193031$13489 + cell $not $not$libresoc.v:192454$13437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:193031$13489_Y + connect \Y $not$libresoc.v:192454$13437_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:193034$13492 + cell $not $not$libresoc.v:192457$13440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:193034$13492_Y + connect \Y $not$libresoc.v:192457$13440_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:193028$13486 + cell $or $or$libresoc.v:192451$13434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402850,10 +398360,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_done - connect \Y $or$libresoc.v:193028$13486_Y + connect \Y $or$libresoc.v:192451$13434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:193030$13488 + cell $or $or$libresoc.v:192453$13436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402861,10 +398371,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_st_done connect \B \q_int - connect \Y $or$libresoc.v:193030$13488_Y + connect \Y $or$libresoc.v:192453$13436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:193033$13491 + cell $or $or$libresoc.v:192456$13439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -402872,39 +398382,39 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_done - connect \Y $or$libresoc.v:193033$13491_Y + connect \Y $or$libresoc.v:192456$13439_Y end - attribute \src "libresoc.v:192992.7-192992.20" - process $proc$libresoc.v:192992$13497 + attribute \src "libresoc.v:192415.7-192415.20" + process $proc$libresoc.v:192415$13445 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193014.7-193014.19" - process $proc$libresoc.v:193014$13498 + attribute \src "libresoc.v:192437.7-192437.19" + process $proc$libresoc.v:192437$13446 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:193035.3-193036.27" - process $proc$libresoc.v:193035$13493 + attribute \src "libresoc.v:192458.3-192459.27" + process $proc$libresoc.v:192458$13441 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:193037.3-193045.6" - process $proc$libresoc.v:193037$13494 + attribute \src "libresoc.v:192460.3-192468.6" + process $proc$libresoc.v:192460$13442 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13495 $1\q_int$next[0:0]$13496 - attribute \src "libresoc.v:193038.5-193038.29" + assign $0\q_int$next[0:0]$13443 $1\q_int$next[0:0]$13444 + attribute \src "libresoc.v:192461.5-192461.29" switch \initial - attribute \src "libresoc.v:193038.9-193038.17" + attribute \src "libresoc.v:192461.9-192461.17" case 1'1 case end @@ -402913,86 +398423,86 @@ module \st_done attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13496 1'0 + assign $1\q_int$next[0:0]$13444 1'0 case - assign $1\q_int$next[0:0]$13496 \$5 + assign $1\q_int$next[0:0]$13444 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13495 + update \q_int$next $0\q_int$next[0:0]$13443 end - connect \$9 $and$libresoc.v:193027$13485_Y - connect \$11 $or$libresoc.v:193028$13486_Y - connect \$13 $not$libresoc.v:193029$13487_Y - connect \$15 $or$libresoc.v:193030$13488_Y - connect \$1 $not$libresoc.v:193031$13489_Y - connect \$3 $and$libresoc.v:193032$13490_Y - connect \$5 $or$libresoc.v:193033$13491_Y - connect \$7 $not$libresoc.v:193034$13492_Y + connect \$9 $and$libresoc.v:192450$13433_Y + connect \$11 $or$libresoc.v:192451$13434_Y + connect \$13 $not$libresoc.v:192452$13435_Y + connect \$15 $or$libresoc.v:192453$13436_Y + connect \$1 $not$libresoc.v:192454$13437_Y + connect \$3 $and$libresoc.v:192455$13438_Y + connect \$5 $or$libresoc.v:192456$13439_Y + connect \$7 $not$libresoc.v:192457$13440_Y connect \qlq_st_done \$15 connect \qn_st_done \$13 connect \q_st_done \$11 end -attribute \src "libresoc.v:193053.1-193349.10" +attribute \src "libresoc.v:192476.1-192772.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state" attribute \generator "nMigen" module \state - attribute \src "libresoc.v:193301.3-193310.6" + attribute \src "libresoc.v:192724.3-192733.6" wire width 64 $0\cia__data_o[63:0] - attribute \src "libresoc.v:193054.7-193054.20" + attribute \src "libresoc.v:192477.7-192477.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193320.3-193329.6" + attribute \src "libresoc.v:192743.3-192752.6" wire width 64 $0\msr__data_o[63:0] - attribute \src "libresoc.v:193311.3-193319.6" - wire width 3 $0\ren_delay$12$next[2:0]$13522 - attribute \src "libresoc.v:193215.3-193216.43" - wire width 3 $0\ren_delay$12[2:0]$13511 - attribute \src "libresoc.v:193182.13-193182.34" - wire width 3 $0\ren_delay$12[2:0]$13528 - attribute \src "libresoc.v:193273.3-193281.6" - wire width 3 $0\ren_delay$19$next[2:0]$13514 - attribute \src "libresoc.v:193213.3-193214.43" - wire width 3 $0\ren_delay$19[2:0]$13509 - attribute \src "libresoc.v:193186.13-193186.34" - wire width 3 $0\ren_delay$19[2:0]$13530 - attribute \src "libresoc.v:193292.3-193300.6" - wire width 3 $0\ren_delay$next[2:0]$13518 - attribute \src "libresoc.v:193217.3-193218.35" + attribute \src "libresoc.v:192734.3-192742.6" + wire width 3 $0\ren_delay$12$next[2:0]$13470 + attribute \src "libresoc.v:192638.3-192639.43" + wire width 3 $0\ren_delay$12[2:0]$13459 + attribute \src "libresoc.v:192605.13-192605.34" + wire width 3 $0\ren_delay$12[2:0]$13476 + attribute \src "libresoc.v:192696.3-192704.6" + wire width 3 $0\ren_delay$19$next[2:0]$13462 + attribute \src "libresoc.v:192636.3-192637.43" + wire width 3 $0\ren_delay$19[2:0]$13457 + attribute \src "libresoc.v:192609.13-192609.34" + wire width 3 $0\ren_delay$19[2:0]$13478 + attribute \src "libresoc.v:192715.3-192723.6" + wire width 3 $0\ren_delay$next[2:0]$13466 + attribute \src "libresoc.v:192640.3-192641.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:193282.3-193291.6" + attribute \src "libresoc.v:192705.3-192714.6" wire width 64 $0\sv__data_o[63:0] - attribute \src "libresoc.v:193301.3-193310.6" + attribute \src "libresoc.v:192724.3-192733.6" wire width 64 $1\cia__data_o[63:0] - attribute \src "libresoc.v:193320.3-193329.6" + attribute \src "libresoc.v:192743.3-192752.6" wire width 64 $1\msr__data_o[63:0] - attribute \src "libresoc.v:193311.3-193319.6" - wire width 3 $1\ren_delay$12$next[2:0]$13523 - attribute \src "libresoc.v:193273.3-193281.6" - wire width 3 $1\ren_delay$19$next[2:0]$13515 - attribute \src "libresoc.v:193292.3-193300.6" - wire width 3 $1\ren_delay$next[2:0]$13519 - attribute \src "libresoc.v:193180.13-193180.29" + attribute \src "libresoc.v:192734.3-192742.6" + wire width 3 $1\ren_delay$12$next[2:0]$13471 + attribute \src "libresoc.v:192696.3-192704.6" + wire width 3 $1\ren_delay$19$next[2:0]$13463 + attribute \src "libresoc.v:192715.3-192723.6" + wire width 3 $1\ren_delay$next[2:0]$13467 + attribute \src "libresoc.v:192603.13-192603.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:193282.3-193291.6" + attribute \src "libresoc.v:192705.3-192714.6" wire width 64 $1\sv__data_o[63:0] - attribute \src "libresoc.v:193204.18-193204.109" - wire width 64 $or$libresoc.v:193204$13499_Y - attribute \src "libresoc.v:193206.18-193206.124" - wire width 64 $or$libresoc.v:193206$13501_Y - attribute \src "libresoc.v:193207.18-193207.110" - wire width 64 $or$libresoc.v:193207$13502_Y - attribute \src "libresoc.v:193209.18-193209.122" - wire width 64 $or$libresoc.v:193209$13504_Y - attribute \src "libresoc.v:193210.18-193210.109" - wire width 64 $or$libresoc.v:193210$13505_Y - attribute \src "libresoc.v:193212.17-193212.123" - wire width 64 $or$libresoc.v:193212$13507_Y - attribute \src "libresoc.v:193205.18-193205.100" - wire $reduce_or$libresoc.v:193205$13500_Y - attribute \src "libresoc.v:193208.18-193208.100" - wire $reduce_or$libresoc.v:193208$13503_Y - attribute \src "libresoc.v:193211.17-193211.95" - wire $reduce_or$libresoc.v:193211$13506_Y + attribute \src "libresoc.v:192627.18-192627.109" + wire width 64 $or$libresoc.v:192627$13447_Y + attribute \src "libresoc.v:192629.18-192629.124" + wire width 64 $or$libresoc.v:192629$13449_Y + attribute \src "libresoc.v:192630.18-192630.110" + wire width 64 $or$libresoc.v:192630$13450_Y + attribute \src "libresoc.v:192632.18-192632.122" + wire width 64 $or$libresoc.v:192632$13452_Y + attribute \src "libresoc.v:192633.18-192633.109" + wire width 64 $or$libresoc.v:192633$13453_Y + attribute \src "libresoc.v:192635.17-192635.123" + wire width 64 $or$libresoc.v:192635$13455_Y + attribute \src "libresoc.v:192628.18-192628.100" + wire $reduce_or$libresoc.v:192628$13448_Y + attribute \src "libresoc.v:192631.18-192631.100" + wire $reduce_or$libresoc.v:192631$13451_Y + attribute \src "libresoc.v:192634.17-192634.95" + wire $reduce_or$libresoc.v:192634$13454_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$10 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" @@ -403027,7 +398537,7 @@ module \state wire width 64 input 13 \data_i$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 14 \data_i$4 - attribute \src "libresoc.v:193054.7-193054.15" + attribute \src "libresoc.v:192477.7-192477.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 9 \msr__data_o @@ -403142,7 +398652,7 @@ module \state attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:193204$13499 + cell $or $or$libresoc.v:192627$13447 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -403150,10 +398660,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_cia0__data_o connect \B \$8 - connect \Y $or$libresoc.v:193204$13499_Y + connect \Y $or$libresoc.v:192627$13447_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:193206$13501 + cell $or $or$libresoc.v:192629$13449 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -403161,10 +398671,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_msr1__data_o connect \B \reg_2_msr2__data_o - connect \Y $or$libresoc.v:193206$13501_Y + connect \Y $or$libresoc.v:192629$13449_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:193207$13502 + cell $or $or$libresoc.v:192630$13450 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -403172,10 +398682,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_msr0__data_o connect \B \$15 - connect \Y $or$libresoc.v:193207$13502_Y + connect \Y $or$libresoc.v:192630$13450_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:193209$13504 + cell $or $or$libresoc.v:192632$13452 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -403183,10 +398693,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_sv1__data_o connect \B \reg_2_sv2__data_o - connect \Y $or$libresoc.v:193209$13504_Y + connect \Y $or$libresoc.v:192632$13452_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:193210$13505 + cell $or $or$libresoc.v:192633$13453 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -403194,10 +398704,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_sv0__data_o connect \B \$22 - connect \Y $or$libresoc.v:193210$13505_Y + connect \Y $or$libresoc.v:192633$13453_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:193212$13507 + cell $or $or$libresoc.v:192635$13455 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -403205,34 +398715,34 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_cia1__data_o connect \B \reg_2_cia2__data_o - connect \Y $or$libresoc.v:193212$13507_Y + connect \Y $or$libresoc.v:192635$13455_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:193205$13500 + cell $reduce_or $reduce_or$libresoc.v:192628$13448 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$12 - connect \Y $reduce_or$libresoc.v:193205$13500_Y + connect \Y $reduce_or$libresoc.v:192628$13448_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:193208$13503 + cell $reduce_or $reduce_or$libresoc.v:192631$13451 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$19 - connect \Y $reduce_or$libresoc.v:193208$13503_Y + connect \Y $reduce_or$libresoc.v:192631$13451_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:193211$13506 + cell $reduce_or $reduce_or$libresoc.v:192634$13454 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:193211$13506_Y + connect \Y $reduce_or$libresoc.v:192634$13454_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:193219.15-193236.4" + attribute \src "libresoc.v:192642.15-192659.4" cell \reg_0$135 \reg_0 connect \cia0__data_o \reg_0_cia0__data_o connect \cia0__ren \reg_0_cia0__ren @@ -403252,7 +398762,7 @@ module \state connect \sv0__wen \reg_0_sv0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:193237.15-193254.4" + attribute \src "libresoc.v:192660.15-192677.4" cell \reg_1$136 \reg_1 connect \cia1__data_o \reg_1_cia1__data_o connect \cia1__ren \reg_1_cia1__ren @@ -403272,7 +398782,7 @@ module \state connect \sv1__wen \reg_1_sv1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:193255.15-193272.4" + attribute \src "libresoc.v:192678.15-192695.4" cell \reg_2$137 \reg_2 connect \cia2__data_o \reg_2_cia2__data_o connect \cia2__ren \reg_2_cia2__ren @@ -403291,67 +398801,67 @@ module \state connect \sv2__ren \reg_2_sv2__ren connect \sv2__wen \reg_2_sv2__wen end - attribute \src "libresoc.v:193054.7-193054.20" - process $proc$libresoc.v:193054$13525 + attribute \src "libresoc.v:192477.7-192477.20" + process $proc$libresoc.v:192477$13473 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193180.13-193180.29" - process $proc$libresoc.v:193180$13526 + attribute \src "libresoc.v:192603.13-192603.29" + process $proc$libresoc.v:192603$13474 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:193182.13-193182.34" - process $proc$libresoc.v:193182$13527 + attribute \src "libresoc.v:192605.13-192605.34" + process $proc$libresoc.v:192605$13475 assign { } { } - assign $0\ren_delay$12[2:0]$13528 3'000 + assign $0\ren_delay$12[2:0]$13476 3'000 sync always sync init - update \ren_delay$12 $0\ren_delay$12[2:0]$13528 + update \ren_delay$12 $0\ren_delay$12[2:0]$13476 end - attribute \src "libresoc.v:193186.13-193186.34" - process $proc$libresoc.v:193186$13529 + attribute \src "libresoc.v:192609.13-192609.34" + process $proc$libresoc.v:192609$13477 assign { } { } - assign $0\ren_delay$19[2:0]$13530 3'000 + assign $0\ren_delay$19[2:0]$13478 3'000 sync always sync init - update \ren_delay$19 $0\ren_delay$19[2:0]$13530 + update \ren_delay$19 $0\ren_delay$19[2:0]$13478 end - attribute \src "libresoc.v:193213.3-193214.43" - process $proc$libresoc.v:193213$13508 + attribute \src "libresoc.v:192636.3-192637.43" + process $proc$libresoc.v:192636$13456 assign { } { } - assign $0\ren_delay$19[2:0]$13509 \ren_delay$19$next + assign $0\ren_delay$19[2:0]$13457 \ren_delay$19$next sync posedge \coresync_clk - update \ren_delay$19 $0\ren_delay$19[2:0]$13509 + update \ren_delay$19 $0\ren_delay$19[2:0]$13457 end - attribute \src "libresoc.v:193215.3-193216.43" - process $proc$libresoc.v:193215$13510 + attribute \src "libresoc.v:192638.3-192639.43" + process $proc$libresoc.v:192638$13458 assign { } { } - assign $0\ren_delay$12[2:0]$13511 \ren_delay$12$next + assign $0\ren_delay$12[2:0]$13459 \ren_delay$12$next sync posedge \coresync_clk - update \ren_delay$12 $0\ren_delay$12[2:0]$13511 + update \ren_delay$12 $0\ren_delay$12[2:0]$13459 end - attribute \src "libresoc.v:193217.3-193218.35" - process $proc$libresoc.v:193217$13512 + attribute \src "libresoc.v:192640.3-192641.35" + process $proc$libresoc.v:192640$13460 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:193273.3-193281.6" - process $proc$libresoc.v:193273$13513 + attribute \src "libresoc.v:192696.3-192704.6" + process $proc$libresoc.v:192696$13461 assign { } { } assign { } { } - assign $0\ren_delay$19$next[2:0]$13514 $1\ren_delay$19$next[2:0]$13515 - attribute \src "libresoc.v:193274.5-193274.29" + assign $0\ren_delay$19$next[2:0]$13462 $1\ren_delay$19$next[2:0]$13463 + attribute \src "libresoc.v:192697.5-192697.29" switch \initial - attribute \src "libresoc.v:193274.9-193274.17" + attribute \src "libresoc.v:192697.9-192697.17" case 1'1 case end @@ -403360,21 +398870,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$19$next[2:0]$13515 3'000 + assign $1\ren_delay$19$next[2:0]$13463 3'000 case - assign $1\ren_delay$19$next[2:0]$13515 \sv__ren + assign $1\ren_delay$19$next[2:0]$13463 \sv__ren end sync always - update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13514 + update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13462 end - attribute \src "libresoc.v:193282.3-193291.6" - process $proc$libresoc.v:193282$13516 + attribute \src "libresoc.v:192705.3-192714.6" + process $proc$libresoc.v:192705$13464 assign { } { } assign { } { } assign $0\sv__data_o[63:0] $1\sv__data_o[63:0] - attribute \src "libresoc.v:193283.5-193283.29" + attribute \src "libresoc.v:192706.5-192706.29" switch \initial - attribute \src "libresoc.v:193283.9-193283.17" + attribute \src "libresoc.v:192706.9-192706.17" case 1'1 case end @@ -403390,14 +398900,14 @@ module \state sync always update \sv__data_o $0\sv__data_o[63:0] end - attribute \src "libresoc.v:193292.3-193300.6" - process $proc$libresoc.v:193292$13517 + attribute \src "libresoc.v:192715.3-192723.6" + process $proc$libresoc.v:192715$13465 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$13518 $1\ren_delay$next[2:0]$13519 - attribute \src "libresoc.v:193293.5-193293.29" + assign $0\ren_delay$next[2:0]$13466 $1\ren_delay$next[2:0]$13467 + attribute \src "libresoc.v:192716.5-192716.29" switch \initial - attribute \src "libresoc.v:193293.9-193293.17" + attribute \src "libresoc.v:192716.9-192716.17" case 1'1 case end @@ -403406,21 +398916,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$13519 3'000 + assign $1\ren_delay$next[2:0]$13467 3'000 case - assign $1\ren_delay$next[2:0]$13519 \cia__ren + assign $1\ren_delay$next[2:0]$13467 \cia__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$13518 + update \ren_delay$next $0\ren_delay$next[2:0]$13466 end - attribute \src "libresoc.v:193301.3-193310.6" - process $proc$libresoc.v:193301$13520 + attribute \src "libresoc.v:192724.3-192733.6" + process $proc$libresoc.v:192724$13468 assign { } { } assign { } { } assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] - attribute \src "libresoc.v:193302.5-193302.29" + attribute \src "libresoc.v:192725.5-192725.29" switch \initial - attribute \src "libresoc.v:193302.9-193302.17" + attribute \src "libresoc.v:192725.9-192725.17" case 1'1 case end @@ -403436,14 +398946,14 @@ module \state sync always update \cia__data_o $0\cia__data_o[63:0] end - attribute \src "libresoc.v:193311.3-193319.6" - process $proc$libresoc.v:193311$13521 + attribute \src "libresoc.v:192734.3-192742.6" + process $proc$libresoc.v:192734$13469 assign { } { } assign { } { } - assign $0\ren_delay$12$next[2:0]$13522 $1\ren_delay$12$next[2:0]$13523 - attribute \src "libresoc.v:193312.5-193312.29" + assign $0\ren_delay$12$next[2:0]$13470 $1\ren_delay$12$next[2:0]$13471 + attribute \src "libresoc.v:192735.5-192735.29" switch \initial - attribute \src "libresoc.v:193312.9-193312.17" + attribute \src "libresoc.v:192735.9-192735.17" case 1'1 case end @@ -403452,21 +398962,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$12$next[2:0]$13523 3'000 + assign $1\ren_delay$12$next[2:0]$13471 3'000 case - assign $1\ren_delay$12$next[2:0]$13523 \msr__ren + assign $1\ren_delay$12$next[2:0]$13471 \msr__ren end sync always - update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13522 + update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13470 end - attribute \src "libresoc.v:193320.3-193329.6" - process $proc$libresoc.v:193320$13524 + attribute \src "libresoc.v:192743.3-192752.6" + process $proc$libresoc.v:192743$13472 assign { } { } assign { } { } assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] - attribute \src "libresoc.v:193321.5-193321.29" + attribute \src "libresoc.v:192744.5-192744.29" switch \initial - attribute \src "libresoc.v:193321.9-193321.17" + attribute \src "libresoc.v:192744.9-192744.17" case 1'1 case end @@ -403482,15 +398992,15 @@ module \state sync always update \msr__data_o $0\msr__data_o[63:0] end - connect \$10 $or$libresoc.v:193204$13499_Y - connect \$13 $reduce_or$libresoc.v:193205$13500_Y - connect \$15 $or$libresoc.v:193206$13501_Y - connect \$17 $or$libresoc.v:193207$13502_Y - connect \$20 $reduce_or$libresoc.v:193208$13503_Y - connect \$22 $or$libresoc.v:193209$13504_Y - connect \$24 $or$libresoc.v:193210$13505_Y - connect \$6 $reduce_or$libresoc.v:193211$13506_Y - connect \$8 $or$libresoc.v:193212$13507_Y + connect \$10 $or$libresoc.v:192627$13447_Y + connect \$13 $reduce_or$libresoc.v:192628$13448_Y + connect \$15 $or$libresoc.v:192629$13449_Y + connect \$17 $or$libresoc.v:192630$13450_Y + connect \$20 $reduce_or$libresoc.v:192631$13451_Y + connect \$22 $or$libresoc.v:192632$13452_Y + connect \$24 $or$libresoc.v:192633$13453_Y + connect \$6 $reduce_or$libresoc.v:192634$13454_Y + connect \$8 $or$libresoc.v:192635$13455_Y connect \reg_2_d_wr12__data_i \data_i connect \reg_1_d_wr11__data_i \data_i connect \reg_0_d_wr10__data_i \data_i @@ -403511,37 +399021,37 @@ module \state connect { \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren connect { \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren end -attribute \src "libresoc.v:193353.1-193411.10" +attribute \src "libresoc.v:192776.1-192834.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l" attribute \generator "nMigen" module \sto_l - attribute \src "libresoc.v:193354.7-193354.20" + attribute \src "libresoc.v:192777.7-192777.20" wire $0\initial[0:0] - attribute \src "libresoc.v:193399.3-193407.6" - wire $0\q_int$next[0:0]$13541 - attribute \src "libresoc.v:193397.3-193398.27" + attribute \src "libresoc.v:192822.3-192830.6" + wire $0\q_int$next[0:0]$13489 + attribute \src "libresoc.v:192820.3-192821.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:193399.3-193407.6" - wire $1\q_int$next[0:0]$13542 - attribute \src "libresoc.v:193376.7-193376.19" + attribute \src "libresoc.v:192822.3-192830.6" + wire $1\q_int$next[0:0]$13490 + attribute \src "libresoc.v:192799.7-192799.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:193389.17-193389.96" - wire $and$libresoc.v:193389$13531_Y - attribute \src "libresoc.v:193394.17-193394.96" - wire $and$libresoc.v:193394$13536_Y - attribute \src "libresoc.v:193391.18-193391.93" - wire $not$libresoc.v:193391$13533_Y - attribute \src "libresoc.v:193393.17-193393.92" - wire $not$libresoc.v:193393$13535_Y - attribute \src "libresoc.v:193396.17-193396.92" - wire $not$libresoc.v:193396$13538_Y - attribute \src "libresoc.v:193390.18-193390.98" - wire $or$libresoc.v:193390$13532_Y - attribute \src "libresoc.v:193392.18-193392.99" - wire $or$libresoc.v:193392$13534_Y - attribute \src "libresoc.v:193395.17-193395.97" - wire $or$libresoc.v:193395$13537_Y + attribute \src "libresoc.v:192812.17-192812.96" + wire $and$libresoc.v:192812$13479_Y + attribute \src "libresoc.v:192817.17-192817.96" + wire $and$libresoc.v:192817$13484_Y + attribute \src "libresoc.v:192814.18-192814.93" + wire $not$libresoc.v:192814$13481_Y + attribute \src "libresoc.v:192816.17-192816.92" + wire $not$libresoc.v:192816$13483_Y + attribute \src "libresoc.v:192819.17-192819.92" + wire $not$libresoc.v:192819$13486_Y + attribute \src "libresoc.v:192813.18-192813.98" + wire $or$libresoc.v:192813$13480_Y + attribute \src "libresoc.v:192815.18-192815.99" + wire $or$libresoc.v:192815$13482_Y + attribute \src "libresoc.v:192818.17-192818.97" + wire $or$libresoc.v:192818$13485_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -403562,7 +399072,7 @@ module \sto_l wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:193354.7-193354.15" + attribute \src "libresoc.v:192777.7-192777.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -403579,7 +399089,7 @@ module \sto_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:193389$13531 + cell $and $and$libresoc.v:192812$13479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -403587,10 +399097,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:193389$13531_Y + connect \Y $and$libresoc.v:192812$13479_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:193394$13536 + cell $and $and$libresoc.v:192817$13484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -403598,34 +399108,34 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:193394$13536_Y + connect \Y $and$libresoc.v:192817$13484_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:193391$13533 + cell $not $not$libresoc.v:192814$13481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_sto - connect \Y $not$libresoc.v:193391$13533_Y + connect \Y $not$libresoc.v:192814$13481_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:193393$13535 + cell $not $not$libresoc.v:192816$13483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:193393$13535_Y + connect \Y $not$libresoc.v:192816$13483_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:193396$13538 + cell $not $not$libresoc.v:192819$13486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:193396$13538_Y + connect \Y $not$libresoc.v:192819$13486_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:193390$13532 + cell $or $or$libresoc.v:192813$13480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -403633,10 +399143,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_sto - connect \Y $or$libresoc.v:193390$13532_Y + connect \Y $or$libresoc.v:192813$13480_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:193392$13534 + cell $or $or$libresoc.v:192815$13482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -403644,10 +399154,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_sto connect \B \q_int - connect \Y $or$libresoc.v:193392$13534_Y + connect \Y $or$libresoc.v:192815$13482_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:193395$13537 + cell $or $or$libresoc.v:192818$13485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -403655,39 +399165,39 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_sto - connect \Y $or$libresoc.v:193395$13537_Y + connect \Y $or$libresoc.v:192818$13485_Y end - attribute \src "libresoc.v:193354.7-193354.20" - process $proc$libresoc.v:193354$13543 + attribute \src "libresoc.v:192777.7-192777.20" + process $proc$libresoc.v:192777$13491 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:193376.7-193376.19" - process $proc$libresoc.v:193376$13544 + attribute \src "libresoc.v:192799.7-192799.19" + process $proc$libresoc.v:192799$13492 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:193397.3-193398.27" - process $proc$libresoc.v:193397$13539 + attribute \src "libresoc.v:192820.3-192821.27" + process $proc$libresoc.v:192820$13487 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:193399.3-193407.6" - process $proc$libresoc.v:193399$13540 + attribute \src "libresoc.v:192822.3-192830.6" + process $proc$libresoc.v:192822$13488 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13541 $1\q_int$next[0:0]$13542 - attribute \src "libresoc.v:193400.5-193400.29" + assign $0\q_int$next[0:0]$13489 $1\q_int$next[0:0]$13490 + attribute \src "libresoc.v:192823.5-192823.29" switch \initial - attribute \src "libresoc.v:193400.9-193400.17" + attribute \src "libresoc.v:192823.9-192823.17" case 1'1 case end @@ -403696,26 +399206,26 @@ module \sto_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13542 1'0 + assign $1\q_int$next[0:0]$13490 1'0 case - assign $1\q_int$next[0:0]$13542 \$5 + assign $1\q_int$next[0:0]$13490 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13541 + update \q_int$next $0\q_int$next[0:0]$13489 end - connect \$9 $and$libresoc.v:193389$13531_Y - connect \$11 $or$libresoc.v:193390$13532_Y - connect \$13 $not$libresoc.v:193391$13533_Y - connect \$15 $or$libresoc.v:193392$13534_Y - connect \$1 $not$libresoc.v:193393$13535_Y - connect \$3 $and$libresoc.v:193394$13536_Y - connect \$5 $or$libresoc.v:193395$13537_Y - connect \$7 $not$libresoc.v:193396$13538_Y + connect \$9 $and$libresoc.v:192812$13479_Y + connect \$11 $or$libresoc.v:192813$13480_Y + connect \$13 $not$libresoc.v:192814$13481_Y + connect \$15 $or$libresoc.v:192815$13482_Y + connect \$1 $not$libresoc.v:192816$13483_Y + connect \$3 $and$libresoc.v:192817$13484_Y + connect \$5 $or$libresoc.v:192818$13485_Y + connect \$7 $not$libresoc.v:192819$13486_Y connect \qlq_sto \$15 connect \qn_sto \$13 connect \q_sto \$11 end -attribute \src "libresoc.v:193416.1-194641.10" +attribute \src "libresoc.v:192839.1-193960.10" attribute \cells_not_processed 1 attribute \top 1 attribute \nmigen.hierarchy "test_issuer" @@ -403732,9 +399242,9 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" wire output 5 \busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 400 \clk + wire input 364 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" - wire width 2 input 402 \clk_sel_i + wire width 2 input 366 \clk_sel_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:224" wire input 4 \core_bigendian_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" @@ -403986,43 +399496,43 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire input 330 \ibus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 387 \icp_wb__ack + wire output 351 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 381 \icp_wb__adr + wire width 28 input 345 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 385 \icp_wb__cyc + wire input 349 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 383 \icp_wb__dat_r + wire width 32 output 347 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 382 \icp_wb__dat_w + wire width 32 input 346 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 389 \icp_wb__err + wire input 353 \icp_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 384 \icp_wb__sel + wire width 4 input 348 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 386 \icp_wb__stb + wire input 350 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 388 \icp_wb__we + wire input 352 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 396 \ics_wb__ack + wire output 360 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 390 \ics_wb__adr + wire width 28 input 354 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 394 \ics_wb__cyc + wire input 358 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 392 \ics_wb__dat_r + wire width 32 output 356 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 391 \ics_wb__dat_w + wire width 32 input 355 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 398 \ics_wb__err + wire input 362 \ics_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 4 input 393 \ics_wb__sel + wire width 4 input 357 \ics_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 395 \ics_wb__stb + wire input 359 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 397 \ics_wb__we + wire input 361 \ics_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 399 \int_level_i + wire width 16 input 363 \int_level_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire input 17 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" @@ -404092,19 +399602,19 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 142 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 405 \pc_i + wire width 64 input 369 \pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 1 \pc_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221" wire width 64 output 2 \pc_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1079" - wire output 403 \pll_18_o + wire output 367 \pll_18_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" wire \pll_clk_24_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" wire \pll_clk_pll_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" - wire output 404 \pll_lck_o + wire output 368 \pll_lck_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" wire \pll_pll_18_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" @@ -404120,7 +399630,7 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 148 \pwm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 401 \rst + wire input 365 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 155 \sd0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -404469,82 +399979,10 @@ module \test_issuer wire input 263 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 264 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 352 \sram4k_0_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 345 \sram4k_0_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 349 \sram4k_0_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 347 \sram4k_0_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 346 \sram4k_0_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 353 \sram4k_0_wb__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 348 \sram4k_0_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 350 \sram4k_0_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 351 \sram4k_0_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 361 \sram4k_1_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 354 \sram4k_1_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 358 \sram4k_1_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 356 \sram4k_1_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 355 \sram4k_1_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 362 \sram4k_1_wb__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 357 \sram4k_1_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 359 \sram4k_1_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 360 \sram4k_1_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 370 \sram4k_2_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 363 \sram4k_2_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 367 \sram4k_2_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 365 \sram4k_2_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 364 \sram4k_2_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 371 \sram4k_2_wb__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 366 \sram4k_2_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 368 \sram4k_2_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 369 \sram4k_2_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 379 \sram4k_3_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 372 \sram4k_3_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 376 \sram4k_3_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 374 \sram4k_3_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 373 \sram4k_3_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 380 \sram4k_3_wb__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 375 \sram4k_3_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 377 \sram4k_3_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 378 \sram4k_3_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire \ti_coresync_clk attribute \module_not_derived 1 - attribute \src "libresoc.v:194239.7-194245.4" + attribute \src "libresoc.v:193590.7-193596.4" cell \pll \pll connect \clk_24_i \pll_clk_24_i connect \clk_pll_o \pll_clk_pll_o @@ -404553,7 +399991,7 @@ module \test_issuer connect \pll_lck_o \pll_lck_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:194246.6-194635.4" + attribute \src "libresoc.v:193597.6-193954.4" cell \ti \ti connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -404911,38 +400349,6 @@ module \test_issuer connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o connect \sdr_we_n__core__o \sdr_we_n__core__o connect \sdr_we_n__pad__o \sdr_we_n__pad__o - connect \sram4k_0_wb__ack \sram4k_0_wb__ack - connect \sram4k_0_wb__adr \sram4k_0_wb__adr - connect \sram4k_0_wb__cyc \sram4k_0_wb__cyc - connect \sram4k_0_wb__dat_r \sram4k_0_wb__dat_r - connect \sram4k_0_wb__dat_w \sram4k_0_wb__dat_w - connect \sram4k_0_wb__sel \sram4k_0_wb__sel - connect \sram4k_0_wb__stb \sram4k_0_wb__stb - connect \sram4k_0_wb__we \sram4k_0_wb__we - connect \sram4k_1_wb__ack \sram4k_1_wb__ack - connect \sram4k_1_wb__adr \sram4k_1_wb__adr - connect \sram4k_1_wb__cyc \sram4k_1_wb__cyc - connect \sram4k_1_wb__dat_r \sram4k_1_wb__dat_r - connect \sram4k_1_wb__dat_w \sram4k_1_wb__dat_w - connect \sram4k_1_wb__sel \sram4k_1_wb__sel - connect \sram4k_1_wb__stb \sram4k_1_wb__stb - connect \sram4k_1_wb__we \sram4k_1_wb__we - connect \sram4k_2_wb__ack \sram4k_2_wb__ack - connect \sram4k_2_wb__adr \sram4k_2_wb__adr - connect \sram4k_2_wb__cyc \sram4k_2_wb__cyc - connect \sram4k_2_wb__dat_r \sram4k_2_wb__dat_r - connect \sram4k_2_wb__dat_w \sram4k_2_wb__dat_w - connect \sram4k_2_wb__sel \sram4k_2_wb__sel - connect \sram4k_2_wb__stb \sram4k_2_wb__stb - connect \sram4k_2_wb__we \sram4k_2_wb__we - connect \sram4k_3_wb__ack \sram4k_3_wb__ack - connect \sram4k_3_wb__adr \sram4k_3_wb__adr - connect \sram4k_3_wb__cyc \sram4k_3_wb__cyc - connect \sram4k_3_wb__dat_r \sram4k_3_wb__dat_r - connect \sram4k_3_wb__dat_w \sram4k_3_wb__dat_w - connect \sram4k_3_wb__sel \sram4k_3_wb__sel - connect \sram4k_3_wb__stb \sram4k_3_wb__stb - connect \sram4k_3_wb__we \sram4k_3_wb__we end connect \ti_coresync_clk \pll_clk_pll_o connect \pllclk_rst \rst @@ -404950,1795 +400356,1795 @@ module \test_issuer connect \pll_clk_24_i \clk connect \pllclk_clk \pll_clk_pll_o end -attribute \src "libresoc.v:194645.1-199858.10" +attribute \src "libresoc.v:193964.1-199046.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti" attribute \generator "nMigen" module \ti - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $0\core_asmcode$next[7:0]$14042 - attribute \src "libresoc.v:197237.3-197238.41" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 8 $0\core_asmcode$next[7:0]$13984 + attribute \src "libresoc.v:196482.3-196483.41" wire width 8 $0\core_asmcode[7:0] - attribute \src "libresoc.v:198140.3-198164.6" - wire $0\core_bigendian_i$10$next[0:0]$13837 - attribute \src "libresoc.v:197367.3-197368.57" - wire $0\core_bigendian_i$10[0:0]$13756 - attribute \src "libresoc.v:194920.7-194920.35" - wire $0\core_bigendian_i$10[0:0]$14249 - attribute \src "libresoc.v:198723.3-198735.6" + attribute \src "libresoc.v:197313.3-197337.6" + wire $0\core_bigendian_i$10$next[0:0]$13779 + attribute \src "libresoc.v:196612.3-196613.57" + wire $0\core_bigendian_i$10[0:0]$13704 + attribute \src "libresoc.v:194239.7-194239.35" + wire $0\core_bigendian_i$10[0:0]$14197 + attribute \src "libresoc.v:197896.3-197908.6" wire width 3 $0\core_cia__ren[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 64 $0\core_core_core_cia$next[63:0]$14043 - attribute \src "libresoc.v:197311.3-197312.53" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 64 $0\core_core_core_cia$next[63:0]$13985 + attribute \src "libresoc.v:196556.3-196557.53" wire width 64 $0\core_core_core_cia[63:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $0\core_core_core_cr_rd$next[7:0]$14044 - attribute \src "libresoc.v:197355.3-197356.57" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 8 $0\core_core_core_cr_rd$next[7:0]$13986 + attribute \src "libresoc.v:196600.3-196601.57" wire width 8 $0\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_cr_rd_ok$next[0:0]$14045 - attribute \src "libresoc.v:197357.3-197358.63" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_core_cr_rd_ok$next[0:0]$13987 + attribute \src "libresoc.v:196602.3-196603.63" wire $0\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $0\core_core_core_cr_wr$next[7:0]$14046 - attribute \src "libresoc.v:197359.3-197360.57" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 8 $0\core_core_core_cr_wr$next[7:0]$13988 + attribute \src "libresoc.v:196604.3-196605.57" wire width 8 $0\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_exc_$signal$3$next[0:0]$14047 - attribute \src "libresoc.v:197337.3-197338.75" - wire $0\core_core_core_exc_$signal$3[0:0]$13734 - attribute \src "libresoc.v:194946.7-194946.44" - wire $0\core_core_core_exc_$signal$3[0:0]$14257 - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_exc_$signal$4$next[0:0]$14048 - attribute \src "libresoc.v:197339.3-197340.75" - wire $0\core_core_core_exc_$signal$4[0:0]$13736 - attribute \src "libresoc.v:194950.7-194950.44" - wire $0\core_core_core_exc_$signal$4[0:0]$14259 - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_exc_$signal$5$next[0:0]$14049 - attribute \src "libresoc.v:197341.3-197342.75" - wire $0\core_core_core_exc_$signal$5[0:0]$13738 - attribute \src "libresoc.v:194954.7-194954.44" - wire $0\core_core_core_exc_$signal$5[0:0]$14261 - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_exc_$signal$6$next[0:0]$14050 - attribute \src "libresoc.v:197343.3-197344.75" - wire $0\core_core_core_exc_$signal$6[0:0]$13740 - attribute \src "libresoc.v:194958.7-194958.44" - wire $0\core_core_core_exc_$signal$6[0:0]$14263 - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_exc_$signal$7$next[0:0]$14051 - attribute \src "libresoc.v:197347.3-197348.75" - wire $0\core_core_core_exc_$signal$7[0:0]$13743 - attribute \src "libresoc.v:194962.7-194962.44" - wire $0\core_core_core_exc_$signal$7[0:0]$14265 - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_exc_$signal$8$next[0:0]$14052 - attribute \src "libresoc.v:197349.3-197350.75" - wire $0\core_core_core_exc_$signal$8[0:0]$13745 - attribute \src "libresoc.v:194966.7-194966.44" - wire $0\core_core_core_exc_$signal$8[0:0]$14267 - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_exc_$signal$9$next[0:0]$14053 - attribute \src "libresoc.v:197351.3-197352.75" - wire $0\core_core_core_exc_$signal$9[0:0]$13747 - attribute \src "libresoc.v:194970.7-194970.44" - wire $0\core_core_core_exc_$signal$9[0:0]$14269 - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_exc_$signal$next[0:0]$14054 - attribute \src "libresoc.v:197335.3-197336.71" - wire $0\core_core_core_exc_$signal[0:0]$13732 - attribute \src "libresoc.v:194944.7-194944.42" - wire $0\core_core_core_exc_$signal[0:0]$14255 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 14 $0\core_core_core_fn_unit$next[13:0]$14055 - attribute \src "libresoc.v:197317.3-197318.61" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_core_exc_$signal$3$next[0:0]$13989 + attribute \src "libresoc.v:196582.3-196583.75" + wire $0\core_core_core_exc_$signal$3[0:0]$13682 + attribute \src "libresoc.v:194265.7-194265.44" + wire $0\core_core_core_exc_$signal$3[0:0]$14205 + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_core_exc_$signal$4$next[0:0]$13990 + attribute \src "libresoc.v:196584.3-196585.75" + wire $0\core_core_core_exc_$signal$4[0:0]$13684 + attribute \src "libresoc.v:194269.7-194269.44" + wire $0\core_core_core_exc_$signal$4[0:0]$14207 + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_core_exc_$signal$5$next[0:0]$13991 + attribute \src "libresoc.v:196586.3-196587.75" + wire $0\core_core_core_exc_$signal$5[0:0]$13686 + attribute \src "libresoc.v:194273.7-194273.44" + wire $0\core_core_core_exc_$signal$5[0:0]$14209 + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_core_exc_$signal$6$next[0:0]$13992 + attribute \src "libresoc.v:196588.3-196589.75" + wire $0\core_core_core_exc_$signal$6[0:0]$13688 + attribute \src "libresoc.v:194277.7-194277.44" + wire $0\core_core_core_exc_$signal$6[0:0]$14211 + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_core_exc_$signal$7$next[0:0]$13993 + attribute \src "libresoc.v:196592.3-196593.75" + wire $0\core_core_core_exc_$signal$7[0:0]$13691 + attribute \src "libresoc.v:194281.7-194281.44" + wire $0\core_core_core_exc_$signal$7[0:0]$14213 + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_core_exc_$signal$8$next[0:0]$13994 + attribute \src "libresoc.v:196594.3-196595.75" + wire $0\core_core_core_exc_$signal$8[0:0]$13693 + attribute \src "libresoc.v:194285.7-194285.44" + wire $0\core_core_core_exc_$signal$8[0:0]$14215 + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_core_exc_$signal$9$next[0:0]$13995 + attribute \src "libresoc.v:196596.3-196597.75" + wire $0\core_core_core_exc_$signal$9[0:0]$13695 + attribute \src "libresoc.v:194289.7-194289.44" + wire $0\core_core_core_exc_$signal$9[0:0]$14217 + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_core_exc_$signal$next[0:0]$13996 + attribute \src "libresoc.v:196580.3-196581.71" + wire $0\core_core_core_exc_$signal[0:0]$13680 + attribute \src "libresoc.v:194263.7-194263.42" + wire $0\core_core_core_exc_$signal[0:0]$14203 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 14 $0\core_core_core_fn_unit$next[13:0]$13997 + attribute \src "libresoc.v:196562.3-196563.61" wire width 14 $0\core_core_core_fn_unit[13:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 2 $0\core_core_core_input_carry$next[1:0]$14056 - attribute \src "libresoc.v:197331.3-197332.69" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 2 $0\core_core_core_input_carry$next[1:0]$13998 + attribute \src "libresoc.v:196576.3-196577.69" wire width 2 $0\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 32 $0\core_core_core_insn$next[31:0]$14057 - attribute \src "libresoc.v:197313.3-197314.55" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 32 $0\core_core_core_insn$next[31:0]$13999 + attribute \src "libresoc.v:196558.3-196559.55" wire width 32 $0\core_core_core_insn[31:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_core_insn_type$next[6:0]$14058 - attribute \src "libresoc.v:197315.3-197316.65" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $0\core_core_core_insn_type$next[6:0]$14000 + attribute \src "libresoc.v:196560.3-196561.65" wire width 7 $0\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_is_32bit$next[0:0]$14059 - attribute \src "libresoc.v:197363.3-197364.63" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_core_is_32bit$next[0:0]$14001 + attribute \src "libresoc.v:196608.3-196609.63" wire $0\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 64 $0\core_core_core_msr$next[63:0]$14060 - attribute \src "libresoc.v:197309.3-197310.53" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 64 $0\core_core_core_msr$next[63:0]$14002 + attribute \src "libresoc.v:196554.3-196555.53" wire width 64 $0\core_core_core_msr[63:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_oe$next[0:0]$14061 - attribute \src "libresoc.v:197327.3-197328.51" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_core_oe$next[0:0]$14003 + attribute \src "libresoc.v:196572.3-196573.51" wire $0\core_core_core_oe[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_oe_ok$next[0:0]$14062 - attribute \src "libresoc.v:197329.3-197330.57" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_core_oe_ok$next[0:0]$14004 + attribute \src "libresoc.v:196574.3-196575.57" wire $0\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_rc$next[0:0]$14063 - attribute \src "libresoc.v:197321.3-197322.51" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_core_rc$next[0:0]$14005 + attribute \src "libresoc.v:196566.3-196567.51" wire $0\core_core_core_rc[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_core_rc_ok$next[0:0]$14064 - attribute \src "libresoc.v:197325.3-197326.57" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_core_rc_ok$next[0:0]$14006 + attribute \src "libresoc.v:196570.3-196571.57" wire $0\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 13 $0\core_core_core_trapaddr$next[12:0]$14065 - attribute \src "libresoc.v:197353.3-197354.63" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 13 $0\core_core_core_trapaddr$next[12:0]$14007 + attribute \src "libresoc.v:196598.3-196599.63" wire width 13 $0\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $0\core_core_core_traptype$next[7:0]$14066 - attribute \src "libresoc.v:197333.3-197334.63" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 8 $0\core_core_core_traptype$next[7:0]$14008 + attribute \src "libresoc.v:196578.3-196579.63" wire width 8 $0\core_core_core_traptype[7:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_cr_in1$next[6:0]$14067 - attribute \src "libresoc.v:197291.3-197292.49" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $0\core_core_cr_in1$next[6:0]$14009 + attribute \src "libresoc.v:196536.3-196537.49" wire width 7 $0\core_core_cr_in1[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_cr_in1_ok$next[0:0]$14068 - attribute \src "libresoc.v:197293.3-197294.55" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_cr_in1_ok$next[0:0]$14010 + attribute \src "libresoc.v:196538.3-196539.55" wire $0\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_cr_in2$1$next[6:0]$14069 - attribute \src "libresoc.v:197299.3-197300.55" - wire width 7 $0\core_core_cr_in2$1[6:0]$13712 - attribute \src "libresoc.v:195128.13-195128.41" - wire width 7 $0\core_core_cr_in2$1[6:0]$14286 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_cr_in2$next[6:0]$14070 - attribute \src "libresoc.v:197295.3-197296.49" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $0\core_core_cr_in2$1$next[6:0]$14011 + attribute \src "libresoc.v:196544.3-196545.55" + wire width 7 $0\core_core_cr_in2$1[6:0]$13660 + attribute \src "libresoc.v:194447.13-194447.41" + wire width 7 $0\core_core_cr_in2$1[6:0]$14234 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $0\core_core_cr_in2$next[6:0]$14012 + attribute \src "libresoc.v:196540.3-196541.49" wire width 7 $0\core_core_cr_in2[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_cr_in2_ok$2$next[0:0]$14071 - attribute \src "libresoc.v:197303.3-197304.61" - wire $0\core_core_cr_in2_ok$2[0:0]$13715 - attribute \src "libresoc.v:195136.7-195136.37" - wire $0\core_core_cr_in2_ok$2[0:0]$14289 - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_cr_in2_ok$next[0:0]$14072 - attribute \src "libresoc.v:197297.3-197298.55" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_cr_in2_ok$2$next[0:0]$14013 + attribute \src "libresoc.v:196548.3-196549.61" + wire $0\core_core_cr_in2_ok$2[0:0]$13663 + attribute \src "libresoc.v:194455.7-194455.37" + wire $0\core_core_cr_in2_ok$2[0:0]$14237 + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_cr_in2_ok$next[0:0]$14014 + attribute \src "libresoc.v:196542.3-196543.55" wire $0\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_cr_out$next[6:0]$14073 - attribute \src "libresoc.v:197305.3-197306.49" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $0\core_core_cr_out$next[6:0]$14015 + attribute \src "libresoc.v:196550.3-196551.49" wire width 7 $0\core_core_cr_out[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_cr_wr_ok$next[0:0]$14074 - attribute \src "libresoc.v:197361.3-197362.53" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_cr_wr_ok$next[0:0]$14016 + attribute \src "libresoc.v:196606.3-196607.53" wire $0\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $0\core_core_dststep$next[6:0]$13791 - attribute \src "libresoc.v:197227.3-197228.51" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 7 $0\core_core_dststep$next[6:0]$13733 + attribute \src "libresoc.v:196472.3-196473.51" wire width 7 $0\core_core_dststep[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_ea$next[6:0]$14075 - attribute \src "libresoc.v:197243.3-197244.41" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $0\core_core_ea$next[6:0]$14017 + attribute \src "libresoc.v:196488.3-196489.41" wire width 7 $0\core_core_ea[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $0\core_core_fast1$next[2:0]$14076 - attribute \src "libresoc.v:197273.3-197274.47" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 3 $0\core_core_fast1$next[2:0]$14018 + attribute \src "libresoc.v:196518.3-196519.47" wire width 3 $0\core_core_fast1[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_fast1_ok$next[0:0]$14077 - attribute \src "libresoc.v:197275.3-197276.53" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_fast1_ok$next[0:0]$14019 + attribute \src "libresoc.v:196520.3-196521.53" wire $0\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $0\core_core_fast2$next[2:0]$14078 - attribute \src "libresoc.v:197277.3-197278.47" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 3 $0\core_core_fast2$next[2:0]$14020 + attribute \src "libresoc.v:196522.3-196523.47" wire width 3 $0\core_core_fast2[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_fast2_ok$next[0:0]$14079 - attribute \src "libresoc.v:197281.3-197282.53" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_fast2_ok$next[0:0]$14021 + attribute \src "libresoc.v:196526.3-196527.53" wire $0\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $0\core_core_fasto1$next[2:0]$14080 - attribute \src "libresoc.v:197283.3-197284.49" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 3 $0\core_core_fasto1$next[2:0]$14022 + attribute \src "libresoc.v:196528.3-196529.49" wire width 3 $0\core_core_fasto1[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $0\core_core_fasto2$next[2:0]$14081 - attribute \src "libresoc.v:197287.3-197288.49" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 3 $0\core_core_fasto2$next[2:0]$14023 + attribute \src "libresoc.v:196532.3-196533.49" wire width 3 $0\core_core_fasto2[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_lk$next[0:0]$14082 - attribute \src "libresoc.v:197319.3-197320.41" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_lk$next[0:0]$14024 + attribute \src "libresoc.v:196564.3-196565.41" wire $0\core_core_lk[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $0\core_core_maxvl$next[6:0]$13792 - attribute \src "libresoc.v:197233.3-197234.47" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 7 $0\core_core_maxvl$next[6:0]$13734 + attribute \src "libresoc.v:196478.3-196479.47" wire width 7 $0\core_core_maxvl[6:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $0\core_core_pc$next[63:0]$13793 - attribute \src "libresoc.v:197205.3-197206.41" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 64 $0\core_core_pc$next[63:0]$13735 + attribute \src "libresoc.v:196450.3-196451.41" wire width 64 $0\core_core_pc[63:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_reg1$next[6:0]$14083 - attribute \src "libresoc.v:197247.3-197248.45" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $0\core_core_reg1$next[6:0]$14025 + attribute \src "libresoc.v:196492.3-196493.45" wire width 7 $0\core_core_reg1[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_reg1_ok$next[0:0]$14084 - attribute \src "libresoc.v:197249.3-197250.51" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_reg1_ok$next[0:0]$14026 + attribute \src "libresoc.v:196494.3-196495.51" wire $0\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_reg2$next[6:0]$14085 - attribute \src "libresoc.v:197251.3-197252.45" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $0\core_core_reg2$next[6:0]$14027 + attribute \src "libresoc.v:196496.3-196497.45" wire width 7 $0\core_core_reg2[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_reg2_ok$next[0:0]$14086 - attribute \src "libresoc.v:197253.3-197254.51" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_reg2_ok$next[0:0]$14028 + attribute \src "libresoc.v:196498.3-196499.51" wire $0\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_reg3$next[6:0]$14087 - attribute \src "libresoc.v:197255.3-197256.45" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $0\core_core_reg3$next[6:0]$14029 + attribute \src "libresoc.v:196500.3-196501.45" wire width 7 $0\core_core_reg3[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_reg3_ok$next[0:0]$14088 - attribute \src "libresoc.v:197259.3-197260.51" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_reg3_ok$next[0:0]$14030 + attribute \src "libresoc.v:196504.3-196505.51" wire $0\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $0\core_core_rego$next[6:0]$14089 - attribute \src "libresoc.v:197239.3-197240.45" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $0\core_core_rego$next[6:0]$14031 + attribute \src "libresoc.v:196484.3-196485.45" wire width 7 $0\core_core_rego[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 10 $0\core_core_spr1$next[9:0]$14090 - attribute \src "libresoc.v:197265.3-197266.45" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 10 $0\core_core_spr1$next[9:0]$14032 + attribute \src "libresoc.v:196510.3-196511.45" wire width 10 $0\core_core_spr1[9:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_core_spr1_ok$next[0:0]$14091 - attribute \src "libresoc.v:197267.3-197268.51" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_core_spr1_ok$next[0:0]$14033 + attribute \src "libresoc.v:196512.3-196513.51" wire $0\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 10 $0\core_core_spro$next[9:0]$14092 - attribute \src "libresoc.v:197261.3-197262.45" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 10 $0\core_core_spro$next[9:0]$14034 + attribute \src "libresoc.v:196506.3-196507.45" wire width 10 $0\core_core_spro[9:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $0\core_core_srcstep$next[6:0]$13794 - attribute \src "libresoc.v:197229.3-197230.51" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 7 $0\core_core_srcstep$next[6:0]$13736 + attribute \src "libresoc.v:196474.3-196475.51" wire width 7 $0\core_core_srcstep[6:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 2 $0\core_core_subvl$next[1:0]$13795 - attribute \src "libresoc.v:197225.3-197226.47" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 2 $0\core_core_subvl$next[1:0]$13737 + attribute \src "libresoc.v:196470.3-196471.47" wire width 2 $0\core_core_subvl[1:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 2 $0\core_core_svstep$next[1:0]$13796 - attribute \src "libresoc.v:197223.3-197224.49" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 2 $0\core_core_svstep$next[1:0]$13738 + attribute \src "libresoc.v:196468.3-196469.49" wire width 2 $0\core_core_svstep[1:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $0\core_core_vl$next[6:0]$13797 - attribute \src "libresoc.v:197231.3-197232.41" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 7 $0\core_core_vl$next[6:0]$13739 + attribute \src "libresoc.v:196476.3-196477.41" wire width 7 $0\core_core_vl[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $0\core_core_xer_in$next[2:0]$14093 - attribute \src "libresoc.v:197269.3-197270.49" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 3 $0\core_core_xer_in$next[2:0]$14035 + attribute \src "libresoc.v:196514.3-196515.49" wire width 3 $0\core_core_xer_in[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_cr_out_ok$next[0:0]$14094 - attribute \src "libresoc.v:197307.3-197308.45" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_cr_out_ok$next[0:0]$14036 + attribute \src "libresoc.v:196552.3-196553.45" wire $0\core_cr_out_ok[0:0] - attribute \src "libresoc.v:198308.3-198317.6" - wire width 64 $0\core_data_i$12[63:0]$13856 - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:197481.3-197490.6" + wire width 64 $0\core_data_i$12[63:0]$13798 + attribute \src "libresoc.v:198015.3-198082.6" wire width 64 $0\core_data_i[63:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $0\core_dec$next[63:0]$13798 - attribute \src "libresoc.v:197221.3-197222.33" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 64 $0\core_dec$next[63:0]$13740 + attribute \src "libresoc.v:196466.3-196467.33" wire width 64 $0\core_dec[63:0] - attribute \src "libresoc.v:198421.3-198430.6" + attribute \src "libresoc.v:197594.3-197603.6" wire width 5 $0\core_dmi__addr[4:0] - attribute \src "libresoc.v:198431.3-198440.6" + attribute \src "libresoc.v:197604.3-197613.6" wire $0\core_dmi__ren[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_ea_ok$next[0:0]$14095 - attribute \src "libresoc.v:197245.3-197246.37" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_ea_ok$next[0:0]$14037 + attribute \src "libresoc.v:196490.3-196491.37" wire $0\core_ea_ok[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire $0\core_eint$next[0:0]$13799 - attribute \src "libresoc.v:197219.3-197220.35" + attribute \src "libresoc.v:197247.3-197291.6" + wire $0\core_eint$next[0:0]$13741 + attribute \src "libresoc.v:196464.3-196465.35" wire $0\core_eint[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_fasto1_ok$next[0:0]$14096 - attribute \src "libresoc.v:197285.3-197286.45" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_fasto1_ok$next[0:0]$14038 + attribute \src "libresoc.v:196530.3-196531.45" wire $0\core_fasto1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_fasto2_ok$next[0:0]$14097 - attribute \src "libresoc.v:197289.3-197290.45" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_fasto2_ok$next[0:0]$14039 + attribute \src "libresoc.v:196534.3-196535.45" wire $0\core_fasto2_ok[0:0] - attribute \src "libresoc.v:198470.3-198479.6" + attribute \src "libresoc.v:197643.3-197652.6" wire width 8 $0\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:198509.3-198518.6" + attribute \src "libresoc.v:197682.3-197691.6" wire width 3 $0\core_full_rd__ren[2:0] - attribute \src "libresoc.v:198617.3-198631.6" - wire width 3 $0\core_issue__addr$13[2:0]$13896 - attribute \src "libresoc.v:198548.3-198562.6" + attribute \src "libresoc.v:197790.3-197804.6" + wire width 3 $0\core_issue__addr$13[2:0]$13838 + attribute \src "libresoc.v:197721.3-197735.6" wire width 3 $0\core_issue__addr[2:0] - attribute \src "libresoc.v:198647.3-198661.6" + attribute \src "libresoc.v:197820.3-197834.6" wire width 64 $0\core_issue__data_i[63:0] - attribute \src "libresoc.v:198563.3-198577.6" + attribute \src "libresoc.v:197736.3-197750.6" wire $0\core_issue__ren[0:0] - attribute \src "libresoc.v:198632.3-198646.6" + attribute \src "libresoc.v:197805.3-197819.6" wire $0\core_issue__wen[0:0] - attribute \src "libresoc.v:198354.3-198369.6" + attribute \src "libresoc.v:197527.3-197542.6" wire $0\core_issue_i[0:0] - attribute \src "libresoc.v:198329.3-198353.6" + attribute \src "libresoc.v:197502.3-197526.6" wire $0\core_ivalid_i[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $0\core_msr$next[63:0]$13800 - attribute \src "libresoc.v:197217.3-197218.33" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 64 $0\core_msr$next[63:0]$13742 + attribute \src "libresoc.v:196462.3-196463.33" wire width 64 $0\core_msr[63:0] - attribute \src "libresoc.v:198919.3-198934.6" + attribute \src "libresoc.v:198083.3-198098.6" wire width 3 $0\core_msr__ren[2:0] - attribute \src "libresoc.v:198119.3-198139.6" - wire width 32 $0\core_raw_insn_i$next[31:0]$13832 - attribute \src "libresoc.v:197389.3-197390.47" + attribute \src "libresoc.v:197292.3-197312.6" + wire width 32 $0\core_raw_insn_i$next[31:0]$13774 + attribute \src "libresoc.v:196634.3-196635.47" wire width 32 $0\core_raw_insn_i[31:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_rego_ok$next[0:0]$14098 - attribute \src "libresoc.v:197241.3-197242.41" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_rego_ok$next[0:0]$14040 + attribute \src "libresoc.v:196486.3-196487.41" wire $0\core_rego_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_spro_ok$next[0:0]$14099 - attribute \src "libresoc.v:197263.3-197264.41" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_spro_ok$next[0:0]$14041 + attribute \src "libresoc.v:196508.3-196509.41" wire $0\core_spro_ok[0:0] - attribute \src "libresoc.v:199449.3-199479.6" + attribute \src "libresoc.v:198622.3-198652.6" wire $0\core_stopped_i[0:0] - attribute \src "libresoc.v:198761.3-198773.6" + attribute \src "libresoc.v:197934.3-197946.6" wire width 3 $0\core_sv__ren[2:0] - attribute \src "libresoc.v:198165.3-198189.6" - wire $0\core_sv_a_nz$next[0:0]$13842 - attribute \src "libresoc.v:197345.3-197346.41" + attribute \src "libresoc.v:197338.3-197362.6" + wire $0\core_sv_a_nz$next[0:0]$13784 + attribute \src "libresoc.v:196590.3-196591.41" wire $0\core_sv_a_nz[0:0] - attribute \src "libresoc.v:198298.3-198307.6" - wire width 3 $0\core_wen$11[2:0]$13853 - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:197471.3-197480.6" + wire width 3 $0\core_wen$11[2:0]$13795 + attribute \src "libresoc.v:197947.3-198014.6" wire width 3 $0\core_wen[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $0\core_xer_out$next[0:0]$14100 - attribute \src "libresoc.v:197271.3-197272.41" + attribute \src "libresoc.v:198886.3-198996.6" + wire $0\core_xer_out$next[0:0]$14042 + attribute \src "libresoc.v:196516.3-196517.41" wire $0\core_xer_out[0:0] - attribute \src "libresoc.v:197403.3-197404.43" + attribute \src "libresoc.v:196648.3-196649.43" wire $0\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $0\cur_cur_dststep$next[6:0]$13937 - attribute \src "libresoc.v:197387.3-197388.47" + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $0\cur_cur_dststep$next[6:0]$13879 + attribute \src "libresoc.v:196632.3-196633.47" wire width 7 $0\cur_cur_dststep[6:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $0\cur_cur_maxvl$next[6:0]$13938 - attribute \src "libresoc.v:197395.3-197396.43" + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $0\cur_cur_maxvl$next[6:0]$13880 + attribute \src "libresoc.v:196640.3-196641.43" wire width 7 $0\cur_cur_maxvl[6:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $0\cur_cur_srcstep$next[6:0]$13939 - attribute \src "libresoc.v:197391.3-197392.47" + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $0\cur_cur_srcstep$next[6:0]$13881 + attribute \src "libresoc.v:196636.3-196637.47" wire width 7 $0\cur_cur_srcstep[6:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $0\cur_cur_subvl$next[1:0]$13940 - attribute \src "libresoc.v:197385.3-197386.43" + attribute \src "libresoc.v:198233.3-198271.6" + wire width 2 $0\cur_cur_subvl$next[1:0]$13882 + attribute \src "libresoc.v:196630.3-196631.43" wire width 2 $0\cur_cur_subvl[1:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $0\cur_cur_svstep$next[1:0]$13941 - attribute \src "libresoc.v:197383.3-197384.45" + attribute \src "libresoc.v:198233.3-198271.6" + wire width 2 $0\cur_cur_svstep$next[1:0]$13883 + attribute \src "libresoc.v:196628.3-196629.45" wire width 2 $0\cur_cur_svstep[1:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $0\cur_cur_vl$next[6:0]$13942 - attribute \src "libresoc.v:197393.3-197394.37" + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $0\cur_cur_vl$next[6:0]$13884 + attribute \src "libresoc.v:196638.3-196639.37" wire width 7 $0\cur_cur_vl[6:0] - attribute \src "libresoc.v:198480.3-198488.6" - wire $0\d_cr_delay$next[0:0]$13878 - attribute \src "libresoc.v:197279.3-197280.37" + attribute \src "libresoc.v:197653.3-197661.6" + wire $0\d_cr_delay$next[0:0]$13820 + attribute \src "libresoc.v:196524.3-196525.37" wire $0\d_cr_delay[0:0] - attribute \src "libresoc.v:198441.3-198449.6" - wire $0\d_reg_delay$next[0:0]$13872 - attribute \src "libresoc.v:197301.3-197302.39" + attribute \src "libresoc.v:197614.3-197622.6" + wire $0\d_reg_delay$next[0:0]$13814 + attribute \src "libresoc.v:196546.3-196547.39" wire $0\d_reg_delay[0:0] - attribute \src "libresoc.v:198519.3-198527.6" - wire $0\d_xer_delay$next[0:0]$13884 - attribute \src "libresoc.v:197257.3-197258.39" + attribute \src "libresoc.v:197692.3-197700.6" + wire $0\d_xer_delay$next[0:0]$13826 + attribute \src "libresoc.v:196502.3-196503.39" wire $0\d_xer_delay[0:0] - attribute \src "libresoc.v:199480.3-199510.6" + attribute \src "libresoc.v:198653.3-198683.6" wire $0\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:198499.3-198508.6" + attribute \src "libresoc.v:197672.3-197681.6" wire $0\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:198489.3-198498.6" + attribute \src "libresoc.v:197662.3-197671.6" wire width 64 $0\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:198460.3-198469.6" + attribute \src "libresoc.v:197633.3-197642.6" wire $0\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:198450.3-198459.6" + attribute \src "libresoc.v:197623.3-197632.6" wire width 64 $0\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:198538.3-198547.6" + attribute \src "libresoc.v:197711.3-197720.6" wire $0\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:198528.3-198537.6" + attribute \src "libresoc.v:197701.3-197710.6" wire width 64 $0\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:198037.3-198045.6" - wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13779 - attribute \src "libresoc.v:197215.3-197216.45" + attribute \src "libresoc.v:197229.3-197237.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13727 + attribute \src "libresoc.v:196460.3-196461.45" wire width 4 $0\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:198774.3-198782.6" - wire width 64 $0\dbg_dmi_din$next[63:0]$13919 - attribute \src "libresoc.v:197209.3-197210.39" + attribute \src "libresoc.v:198099.3-198107.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$13864 + attribute \src "libresoc.v:196454.3-196455.39" wire width 64 $0\dbg_dmi_din[63:0] - attribute \src "libresoc.v:198046.3-198054.6" - wire $0\dbg_dmi_req_i$next[0:0]$13782 - attribute \src "libresoc.v:197213.3-197214.43" + attribute \src "libresoc.v:197238.3-197246.6" + wire $0\dbg_dmi_req_i$next[0:0]$13730 + attribute \src "libresoc.v:196458.3-196459.43" wire $0\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:198689.3-198697.6" - wire $0\dbg_dmi_we_i$next[0:0]$13906 - attribute \src "libresoc.v:197211.3-197212.41" + attribute \src "libresoc.v:197862.3-197870.6" + wire $0\dbg_dmi_we_i$next[0:0]$13848 + attribute \src "libresoc.v:196456.3-196457.41" wire $0\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:198662.3-198677.6" - wire width 64 $0\dec2_cur_dec$next[63:0]$13901 - attribute \src "libresoc.v:197203.3-197204.41" + attribute \src "libresoc.v:197835.3-197850.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$13843 + attribute \src "libresoc.v:196448.3-196449.41" wire width 64 $0\dec2_cur_dec[63:0] - attribute \src "libresoc.v:198055.3-198063.6" - wire $0\dec2_cur_eint$next[0:0]$13785 - attribute \src "libresoc.v:197407.3-197408.43" + attribute \src "libresoc.v:198997.3-199005.6" + wire $0\dec2_cur_eint$next[0:0]$14189 + attribute \src "libresoc.v:196652.3-196653.43" wire $0\dec2_cur_eint[0:0] - attribute \src "libresoc.v:199192.3-199212.6" - wire width 64 $0\dec2_cur_msr$next[63:0]$13985 - attribute \src "libresoc.v:197377.3-197378.41" + attribute \src "libresoc.v:198365.3-198385.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$13927 + attribute \src "libresoc.v:196622.3-196623.41" wire width 64 $0\dec2_cur_msr[63:0] - attribute \src "libresoc.v:199039.3-199059.6" - wire width 64 $0\dec2_cur_pc$next[63:0]$13932 - attribute \src "libresoc.v:197397.3-197398.39" + attribute \src "libresoc.v:198212.3-198232.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$13874 + attribute \src "libresoc.v:196642.3-196643.39" wire width 64 $0\dec2_cur_pc[63:0] - attribute \src "libresoc.v:199232.3-199262.6" - wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13994 - attribute \src "libresoc.v:197373.3-197374.53" + attribute \src "libresoc.v:198405.3-198435.6" + wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13936 + attribute \src "libresoc.v:196618.3-196619.53" wire width 32 $0\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:198064.3-198073.6" - wire width 2 $0\delay$next[1:0]$13788 - attribute \src "libresoc.v:197405.3-197406.27" + attribute \src "libresoc.v:199006.3-199015.6" + wire width 2 $0\delay$next[1:0]$14192 + attribute \src "libresoc.v:196650.3-196651.27" wire width 2 $0\delay[1:0] - attribute \src "libresoc.v:198370.3-198404.6" - wire $0\exec_fsm_state$next[0:0]$13862 - attribute \src "libresoc.v:197323.3-197324.45" + attribute \src "libresoc.v:197543.3-197577.6" + wire $0\exec_fsm_state$next[0:0]$13804 + attribute \src "libresoc.v:196568.3-196569.45" wire $0\exec_fsm_state[0:0] - attribute \src "libresoc.v:198318.3-198328.6" + attribute \src "libresoc.v:197491.3-197501.6" wire $0\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:198250.3-198260.6" + attribute \src "libresoc.v:197423.3-197433.6" wire $0\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:198261.3-198276.6" + attribute \src "libresoc.v:197434.3-197449.6" wire $0\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:198405.3-198420.6" + attribute \src "libresoc.v:197578.3-197593.6" wire $0\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:199138.3-199191.6" - wire width 2 $0\fetch_fsm_state$next[1:0]$13977 - attribute \src "libresoc.v:197379.3-197380.47" + attribute \src "libresoc.v:198311.3-198364.6" + wire width 2 $0\fetch_fsm_state$next[1:0]$13919 + attribute \src "libresoc.v:196624.3-196625.47" wire width 2 $0\fetch_fsm_state[1:0] - attribute \src "libresoc.v:199702.3-199712.6" + attribute \src "libresoc.v:198875.3-198885.6" wire $0\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:199263.3-199273.6" + attribute \src "libresoc.v:198436.3-198446.6" wire $0\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:198944.3-198954.6" + attribute \src "libresoc.v:198108.3-198118.6" wire $0\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:199334.3-199349.6" + attribute \src "libresoc.v:198507.3-198522.6" wire $0\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:198578.3-198605.6" - wire width 2 $0\fsm_state$next[1:0]$13891 - attribute \src "libresoc.v:197235.3-197236.35" + attribute \src "libresoc.v:197751.3-197778.6" + wire width 2 $0\fsm_state$next[1:0]$13833 + attribute \src "libresoc.v:196480.3-196481.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:198955.3-198970.6" + attribute \src "libresoc.v:198119.3-198134.6" wire width 48 $0\imem_a_pc_i[47:0] - attribute \src "libresoc.v:198971.3-199004.6" + attribute \src "libresoc.v:198144.3-198177.6" wire $0\imem_a_valid_i[0:0] - attribute \src "libresoc.v:199005.3-199038.6" + attribute \src "libresoc.v:198178.3-198211.6" wire $0\imem_f_valid_i[0:0] - attribute \src "libresoc.v:194646.7-194646.20" + attribute \src "libresoc.v:193965.7-193965.20" wire $0\initial[0:0] - attribute \src "libresoc.v:198190.3-198227.6" + attribute \src "libresoc.v:197363.3-197400.6" wire $0\insn_done[0:0] - attribute \src "libresoc.v:198277.3-198297.6" + attribute \src "libresoc.v:197450.3-197470.6" wire $0\is_last[0:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $0\issue_fsm_state$next[2:0]$14002 - attribute \src "libresoc.v:197371.3-197372.47" + attribute \src "libresoc.v:198523.3-198621.6" + wire width 3 $0\issue_fsm_state$next[2:0]$13944 + attribute \src "libresoc.v:196616.3-196617.47" wire width 3 $0\issue_fsm_state[2:0] - attribute \src "libresoc.v:198935.3-198943.6" - wire $0\jtag_dmi0__ack_o$next[0:0]$13925 - attribute \src "libresoc.v:197207.3-197208.49" + attribute \src "libresoc.v:198135.3-198143.6" + wire $0\jtag_dmi0__ack_o$next[0:0]$13869 + attribute \src "libresoc.v:196452.3-196453.49" wire $0\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:199099.3-199107.6" - wire width 64 $0\jtag_dmi0__dout$next[63:0]$13968 - attribute \src "libresoc.v:197409.3-197410.47" + attribute \src "libresoc.v:198302.3-198310.6" + wire width 64 $0\jtag_dmi0__dout$next[63:0]$13916 + attribute \src "libresoc.v:196654.3-196655.47" wire width 64 $0\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:199108.3-199137.6" - wire $0\msr_read$next[0:0]$13971 - attribute \src "libresoc.v:197381.3-197382.33" + attribute \src "libresoc.v:198272.3-198301.6" + wire $0\msr_read$next[0:0]$13910 + attribute \src "libresoc.v:196626.3-196627.33" wire $0\msr_read[0:0] - attribute \src "libresoc.v:198606.3-198616.6" + attribute \src "libresoc.v:197779.3-197789.6" wire width 64 $0\new_dec[63:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $0\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $0\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $0\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 2 $0\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 2 $0\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $0\new_svstate_vl[6:0] - attribute \src "libresoc.v:198678.3-198688.6" + attribute \src "libresoc.v:197851.3-197861.6" wire width 64 $0\new_tb[63:0] - attribute \src "libresoc.v:199213.3-199231.6" - wire width 64 $0\nia$next[63:0]$13990 - attribute \src "libresoc.v:197375.3-197376.23" + attribute \src "libresoc.v:198386.3-198404.6" + wire width 64 $0\nia$next[63:0]$13932 + attribute \src "libresoc.v:196620.3-196621.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:198707.3-198722.6" + attribute \src "libresoc.v:197880.3-197895.6" wire width 64 $0\pc[63:0] - attribute \src "libresoc.v:199511.3-199577.6" - wire $0\pc_changed$next[0:0]$14018 - attribute \src "libresoc.v:197369.3-197370.37" + attribute \src "libresoc.v:198684.3-198750.6" + wire $0\pc_changed$next[0:0]$13960 + attribute \src "libresoc.v:196614.3-196615.37" wire $0\pc_changed[0:0] - attribute \src "libresoc.v:198698.3-198706.6" - wire $0\pc_ok_delay$next[0:0]$13909 - attribute \src "libresoc.v:197401.3-197402.39" + attribute \src "libresoc.v:197871.3-197879.6" + wire $0\pc_ok_delay$next[0:0]$13851 + attribute \src "libresoc.v:196646.3-196647.39" wire $0\pc_ok_delay[0:0] - attribute \src "libresoc.v:198228.3-198238.6" + attribute \src "libresoc.v:197401.3-197411.6" wire $0\pred_insn_valid_i[0:0] - attribute \src "libresoc.v:198239.3-198249.6" + attribute \src "libresoc.v:197412.3-197422.6" wire $0\pred_mask_ready_i[0:0] - attribute \src "libresoc.v:199635.3-199701.6" - wire $0\sv_changed$next[0:0]$14030 - attribute \src "libresoc.v:197365.3-197366.37" + attribute \src "libresoc.v:198808.3-198874.6" + wire $0\sv_changed$next[0:0]$13972 + attribute \src "libresoc.v:196610.3-196611.37" wire $0\sv_changed[0:0] - attribute \src "libresoc.v:198745.3-198760.6" + attribute \src "libresoc.v:197918.3-197933.6" wire width 64 $0\svstate[63:0] - attribute \src "libresoc.v:198736.3-198744.6" - wire $0\svstate_ok_delay$next[0:0]$13914 - attribute \src "libresoc.v:197399.3-197400.49" + attribute \src "libresoc.v:197909.3-197917.6" + wire $0\svstate_ok_delay$next[0:0]$13856 + attribute \src "libresoc.v:196644.3-196645.49" wire $0\svstate_ok_delay[0:0] - attribute \src "libresoc.v:199578.3-199634.6" + attribute \src "libresoc.v:198751.3-198807.6" wire $0\update_svstate[0:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $10\issue_fsm_state$next[2:0]$14012 - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $11\issue_fsm_state$next[2:0]$14013 - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $12\issue_fsm_state$next[2:0]$14014 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $1\core_asmcode$next[7:0]$14101 - attribute \src "libresoc.v:194914.13-194914.33" + attribute \src "libresoc.v:198523.3-198621.6" + wire width 3 $10\issue_fsm_state$next[2:0]$13954 + attribute \src "libresoc.v:198523.3-198621.6" + wire width 3 $11\issue_fsm_state$next[2:0]$13955 + attribute \src "libresoc.v:198523.3-198621.6" + wire width 3 $12\issue_fsm_state$next[2:0]$13956 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 8 $1\core_asmcode$next[7:0]$14043 + attribute \src "libresoc.v:194233.13-194233.33" wire width 8 $1\core_asmcode[7:0] - attribute \src "libresoc.v:198140.3-198164.6" - wire $1\core_bigendian_i$10$next[0:0]$13838 - attribute \src "libresoc.v:198723.3-198735.6" + attribute \src "libresoc.v:197313.3-197337.6" + wire $1\core_bigendian_i$10$next[0:0]$13780 + attribute \src "libresoc.v:197896.3-197908.6" wire width 3 $1\core_cia__ren[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 64 $1\core_core_core_cia$next[63:0]$14102 - attribute \src "libresoc.v:194928.14-194928.55" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 64 $1\core_core_core_cia$next[63:0]$14044 + attribute \src "libresoc.v:194247.14-194247.55" wire width 64 $1\core_core_core_cia[63:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $1\core_core_core_cr_rd$next[7:0]$14103 - attribute \src "libresoc.v:194932.13-194932.41" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 8 $1\core_core_core_cr_rd$next[7:0]$14045 + attribute \src "libresoc.v:194251.13-194251.41" wire width 8 $1\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_cr_rd_ok$next[0:0]$14104 - attribute \src "libresoc.v:194936.7-194936.37" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_core_cr_rd_ok$next[0:0]$14046 + attribute \src "libresoc.v:194255.7-194255.37" wire $1\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $1\core_core_core_cr_wr$next[7:0]$14105 - attribute \src "libresoc.v:194940.13-194940.41" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 8 $1\core_core_core_cr_wr$next[7:0]$14047 + attribute \src "libresoc.v:194259.13-194259.41" wire width 8 $1\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_exc_$signal$3$next[0:0]$14106 - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_exc_$signal$4$next[0:0]$14107 - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_exc_$signal$5$next[0:0]$14108 - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_exc_$signal$6$next[0:0]$14109 - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_exc_$signal$7$next[0:0]$14110 - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_exc_$signal$8$next[0:0]$14111 - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_exc_$signal$9$next[0:0]$14112 - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_exc_$signal$next[0:0]$14113 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 14 $1\core_core_core_fn_unit$next[13:0]$14114 - attribute \src "libresoc.v:194991.14-194991.47" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_core_exc_$signal$3$next[0:0]$14048 + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_core_exc_$signal$4$next[0:0]$14049 + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_core_exc_$signal$5$next[0:0]$14050 + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_core_exc_$signal$6$next[0:0]$14051 + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_core_exc_$signal$7$next[0:0]$14052 + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_core_exc_$signal$8$next[0:0]$14053 + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_core_exc_$signal$9$next[0:0]$14054 + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_core_exc_$signal$next[0:0]$14055 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 14 $1\core_core_core_fn_unit$next[13:0]$14056 + attribute \src "libresoc.v:194310.14-194310.47" wire width 14 $1\core_core_core_fn_unit[13:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 2 $1\core_core_core_input_carry$next[1:0]$14115 - attribute \src "libresoc.v:194999.13-194999.46" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 2 $1\core_core_core_input_carry$next[1:0]$14057 + attribute \src "libresoc.v:194318.13-194318.46" wire width 2 $1\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 32 $1\core_core_core_insn$next[31:0]$14116 - attribute \src "libresoc.v:195003.14-195003.41" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 32 $1\core_core_core_insn$next[31:0]$14058 + attribute \src "libresoc.v:194322.14-194322.41" wire width 32 $1\core_core_core_insn[31:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_core_insn_type$next[6:0]$14117 - attribute \src "libresoc.v:195082.13-195082.45" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $1\core_core_core_insn_type$next[6:0]$14059 + attribute \src "libresoc.v:194401.13-194401.45" wire width 7 $1\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_is_32bit$next[0:0]$14118 - attribute \src "libresoc.v:195086.7-195086.37" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_core_is_32bit$next[0:0]$14060 + attribute \src "libresoc.v:194405.7-194405.37" wire $1\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 64 $1\core_core_core_msr$next[63:0]$14119 - attribute \src "libresoc.v:195090.14-195090.55" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 64 $1\core_core_core_msr$next[63:0]$14061 + attribute \src "libresoc.v:194409.14-194409.55" wire width 64 $1\core_core_core_msr[63:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_oe$next[0:0]$14120 - attribute \src "libresoc.v:195094.7-195094.31" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_core_oe$next[0:0]$14062 + attribute \src "libresoc.v:194413.7-194413.31" wire $1\core_core_core_oe[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_oe_ok$next[0:0]$14121 - attribute \src "libresoc.v:195098.7-195098.34" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_core_oe_ok$next[0:0]$14063 + attribute \src "libresoc.v:194417.7-194417.34" wire $1\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_rc$next[0:0]$14122 - attribute \src "libresoc.v:195102.7-195102.31" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_core_rc$next[0:0]$14064 + attribute \src "libresoc.v:194421.7-194421.31" wire $1\core_core_core_rc[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_core_rc_ok$next[0:0]$14123 - attribute \src "libresoc.v:195106.7-195106.34" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_core_rc_ok$next[0:0]$14065 + attribute \src "libresoc.v:194425.7-194425.34" wire $1\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 13 $1\core_core_core_trapaddr$next[12:0]$14124 - attribute \src "libresoc.v:195110.14-195110.48" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 13 $1\core_core_core_trapaddr$next[12:0]$14066 + attribute \src "libresoc.v:194429.14-194429.48" wire width 13 $1\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $1\core_core_core_traptype$next[7:0]$14125 - attribute \src "libresoc.v:195114.13-195114.44" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 8 $1\core_core_core_traptype$next[7:0]$14067 + attribute \src "libresoc.v:194433.13-194433.44" wire width 8 $1\core_core_core_traptype[7:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_cr_in1$next[6:0]$14126 - attribute \src "libresoc.v:195118.13-195118.37" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $1\core_core_cr_in1$next[6:0]$14068 + attribute \src "libresoc.v:194437.13-194437.37" wire width 7 $1\core_core_cr_in1[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_cr_in1_ok$next[0:0]$14127 - attribute \src "libresoc.v:195122.7-195122.33" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_cr_in1_ok$next[0:0]$14069 + attribute \src "libresoc.v:194441.7-194441.33" wire $1\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_cr_in2$1$next[6:0]$14128 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_cr_in2$next[6:0]$14129 - attribute \src "libresoc.v:195126.13-195126.37" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $1\core_core_cr_in2$1$next[6:0]$14070 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $1\core_core_cr_in2$next[6:0]$14071 + attribute \src "libresoc.v:194445.13-194445.37" wire width 7 $1\core_core_cr_in2[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_cr_in2_ok$2$next[0:0]$14130 - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_cr_in2_ok$next[0:0]$14131 - attribute \src "libresoc.v:195134.7-195134.33" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_cr_in2_ok$2$next[0:0]$14072 + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_cr_in2_ok$next[0:0]$14073 + attribute \src "libresoc.v:194453.7-194453.33" wire $1\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_cr_out$next[6:0]$14132 - attribute \src "libresoc.v:195142.13-195142.37" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $1\core_core_cr_out$next[6:0]$14074 + attribute \src "libresoc.v:194461.13-194461.37" wire width 7 $1\core_core_cr_out[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_cr_wr_ok$next[0:0]$14133 - attribute \src "libresoc.v:195146.7-195146.32" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_cr_wr_ok$next[0:0]$14075 + attribute \src "libresoc.v:194465.7-194465.32" wire $1\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $1\core_core_dststep$next[6:0]$13801 - attribute \src "libresoc.v:195150.13-195150.38" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 7 $1\core_core_dststep$next[6:0]$13743 + attribute \src "libresoc.v:194469.13-194469.38" wire width 7 $1\core_core_dststep[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_ea$next[6:0]$14134 - attribute \src "libresoc.v:195154.13-195154.33" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $1\core_core_ea$next[6:0]$14076 + attribute \src "libresoc.v:194473.13-194473.33" wire width 7 $1\core_core_ea[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $1\core_core_fast1$next[2:0]$14135 - attribute \src "libresoc.v:195158.13-195158.35" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 3 $1\core_core_fast1$next[2:0]$14077 + attribute \src "libresoc.v:194477.13-194477.35" wire width 3 $1\core_core_fast1[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_fast1_ok$next[0:0]$14136 - attribute \src "libresoc.v:195162.7-195162.32" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_fast1_ok$next[0:0]$14078 + attribute \src "libresoc.v:194481.7-194481.32" wire $1\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $1\core_core_fast2$next[2:0]$14137 - attribute \src "libresoc.v:195166.13-195166.35" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 3 $1\core_core_fast2$next[2:0]$14079 + attribute \src "libresoc.v:194485.13-194485.35" wire width 3 $1\core_core_fast2[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_fast2_ok$next[0:0]$14138 - attribute \src "libresoc.v:195170.7-195170.32" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_fast2_ok$next[0:0]$14080 + attribute \src "libresoc.v:194489.7-194489.32" wire $1\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $1\core_core_fasto1$next[2:0]$14139 - attribute \src "libresoc.v:195174.13-195174.36" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 3 $1\core_core_fasto1$next[2:0]$14081 + attribute \src "libresoc.v:194493.13-194493.36" wire width 3 $1\core_core_fasto1[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $1\core_core_fasto2$next[2:0]$14140 - attribute \src "libresoc.v:195178.13-195178.36" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 3 $1\core_core_fasto2$next[2:0]$14082 + attribute \src "libresoc.v:194497.13-194497.36" wire width 3 $1\core_core_fasto2[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_lk$next[0:0]$14141 - attribute \src "libresoc.v:195182.7-195182.26" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_lk$next[0:0]$14083 + attribute \src "libresoc.v:194501.7-194501.26" wire $1\core_core_lk[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $1\core_core_maxvl$next[6:0]$13802 - attribute \src "libresoc.v:195186.13-195186.36" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 7 $1\core_core_maxvl$next[6:0]$13744 + attribute \src "libresoc.v:194505.13-194505.36" wire width 7 $1\core_core_maxvl[6:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $1\core_core_pc$next[63:0]$13803 - attribute \src "libresoc.v:195190.14-195190.49" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 64 $1\core_core_pc$next[63:0]$13745 + attribute \src "libresoc.v:194509.14-194509.49" wire width 64 $1\core_core_pc[63:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_reg1$next[6:0]$14142 - attribute \src "libresoc.v:195194.13-195194.35" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $1\core_core_reg1$next[6:0]$14084 + attribute \src "libresoc.v:194513.13-194513.35" wire width 7 $1\core_core_reg1[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_reg1_ok$next[0:0]$14143 - attribute \src "libresoc.v:195198.7-195198.31" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_reg1_ok$next[0:0]$14085 + attribute \src "libresoc.v:194517.7-194517.31" wire $1\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_reg2$next[6:0]$14144 - attribute \src "libresoc.v:195202.13-195202.35" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $1\core_core_reg2$next[6:0]$14086 + attribute \src "libresoc.v:194521.13-194521.35" wire width 7 $1\core_core_reg2[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_reg2_ok$next[0:0]$14145 - attribute \src "libresoc.v:195206.7-195206.31" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_reg2_ok$next[0:0]$14087 + attribute \src "libresoc.v:194525.7-194525.31" wire $1\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_reg3$next[6:0]$14146 - attribute \src "libresoc.v:195210.13-195210.35" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $1\core_core_reg3$next[6:0]$14088 + attribute \src "libresoc.v:194529.13-194529.35" wire width 7 $1\core_core_reg3[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_reg3_ok$next[0:0]$14147 - attribute \src "libresoc.v:195214.7-195214.31" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_reg3_ok$next[0:0]$14089 + attribute \src "libresoc.v:194533.7-194533.31" wire $1\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $1\core_core_rego$next[6:0]$14148 - attribute \src "libresoc.v:195218.13-195218.35" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $1\core_core_rego$next[6:0]$14090 + attribute \src "libresoc.v:194537.13-194537.35" wire width 7 $1\core_core_rego[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 10 $1\core_core_spr1$next[9:0]$14149 - attribute \src "libresoc.v:195336.13-195336.37" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 10 $1\core_core_spr1$next[9:0]$14091 + attribute \src "libresoc.v:194655.13-194655.37" wire width 10 $1\core_core_spr1[9:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_core_spr1_ok$next[0:0]$14150 - attribute \src "libresoc.v:195340.7-195340.31" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_core_spr1_ok$next[0:0]$14092 + attribute \src "libresoc.v:194659.7-194659.31" wire $1\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 10 $1\core_core_spro$next[9:0]$14151 - attribute \src "libresoc.v:195458.13-195458.37" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 10 $1\core_core_spro$next[9:0]$14093 + attribute \src "libresoc.v:194777.13-194777.37" wire width 10 $1\core_core_spro[9:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $1\core_core_srcstep$next[6:0]$13804 - attribute \src "libresoc.v:195462.13-195462.38" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 7 $1\core_core_srcstep$next[6:0]$13746 + attribute \src "libresoc.v:194781.13-194781.38" wire width 7 $1\core_core_srcstep[6:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 2 $1\core_core_subvl$next[1:0]$13805 - attribute \src "libresoc.v:195466.13-195466.35" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 2 $1\core_core_subvl$next[1:0]$13747 + attribute \src "libresoc.v:194785.13-194785.35" wire width 2 $1\core_core_subvl[1:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 2 $1\core_core_svstep$next[1:0]$13806 - attribute \src "libresoc.v:195470.13-195470.36" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 2 $1\core_core_svstep$next[1:0]$13748 + attribute \src "libresoc.v:194789.13-194789.36" wire width 2 $1\core_core_svstep[1:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $1\core_core_vl$next[6:0]$13807 - attribute \src "libresoc.v:195476.13-195476.33" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 7 $1\core_core_vl$next[6:0]$13749 + attribute \src "libresoc.v:194795.13-194795.33" wire width 7 $1\core_core_vl[6:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $1\core_core_xer_in$next[2:0]$14152 - attribute \src "libresoc.v:195480.13-195480.36" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 3 $1\core_core_xer_in$next[2:0]$14094 + attribute \src "libresoc.v:194799.13-194799.36" wire width 3 $1\core_core_xer_in[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_cr_out_ok$next[0:0]$14153 - attribute \src "libresoc.v:195488.7-195488.28" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_cr_out_ok$next[0:0]$14095 + attribute \src "libresoc.v:194807.7-194807.28" wire $1\core_cr_out_ok[0:0] - attribute \src "libresoc.v:198308.3-198317.6" - wire width 64 $1\core_data_i$12[63:0]$13857 - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:197481.3-197490.6" + wire width 64 $1\core_data_i$12[63:0]$13799 + attribute \src "libresoc.v:198015.3-198082.6" wire width 64 $1\core_data_i[63:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $1\core_dec$next[63:0]$13808 - attribute \src "libresoc.v:195504.14-195504.45" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 64 $1\core_dec$next[63:0]$13750 + attribute \src "libresoc.v:194823.14-194823.45" wire width 64 $1\core_dec[63:0] - attribute \src "libresoc.v:198421.3-198430.6" + attribute \src "libresoc.v:197594.3-197603.6" wire width 5 $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:198431.3-198440.6" + attribute \src "libresoc.v:197604.3-197613.6" wire $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_ea_ok$next[0:0]$14154 - attribute \src "libresoc.v:195514.7-195514.24" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_ea_ok$next[0:0]$14096 + attribute \src "libresoc.v:194833.7-194833.24" wire $1\core_ea_ok[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire $1\core_eint$next[0:0]$13809 - attribute \src "libresoc.v:195518.7-195518.23" + attribute \src "libresoc.v:197247.3-197291.6" + wire $1\core_eint$next[0:0]$13751 + attribute \src "libresoc.v:194837.7-194837.23" wire $1\core_eint[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_fasto1_ok$next[0:0]$14155 - attribute \src "libresoc.v:195522.7-195522.28" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_fasto1_ok$next[0:0]$14097 + attribute \src "libresoc.v:194841.7-194841.28" wire $1\core_fasto1_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_fasto2_ok$next[0:0]$14156 - attribute \src "libresoc.v:195526.7-195526.28" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_fasto2_ok$next[0:0]$14098 + attribute \src "libresoc.v:194845.7-194845.28" wire $1\core_fasto2_ok[0:0] - attribute \src "libresoc.v:198470.3-198479.6" + attribute \src "libresoc.v:197643.3-197652.6" wire width 8 $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:198509.3-198518.6" + attribute \src "libresoc.v:197682.3-197691.6" wire width 3 $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:198617.3-198631.6" - wire width 3 $1\core_issue__addr$13[2:0]$13897 - attribute \src "libresoc.v:198548.3-198562.6" + attribute \src "libresoc.v:197790.3-197804.6" + wire width 3 $1\core_issue__addr$13[2:0]$13839 + attribute \src "libresoc.v:197721.3-197735.6" wire width 3 $1\core_issue__addr[2:0] - attribute \src "libresoc.v:198647.3-198661.6" + attribute \src "libresoc.v:197820.3-197834.6" wire width 64 $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:198563.3-198577.6" + attribute \src "libresoc.v:197736.3-197750.6" wire $1\core_issue__ren[0:0] - attribute \src "libresoc.v:198632.3-198646.6" + attribute \src "libresoc.v:197805.3-197819.6" wire $1\core_issue__wen[0:0] - attribute \src "libresoc.v:198354.3-198369.6" + attribute \src "libresoc.v:197527.3-197542.6" wire $1\core_issue_i[0:0] - attribute \src "libresoc.v:198329.3-198353.6" + attribute \src "libresoc.v:197502.3-197526.6" wire $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $1\core_msr$next[63:0]$13810 - attribute \src "libresoc.v:195554.14-195554.45" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 64 $1\core_msr$next[63:0]$13752 + attribute \src "libresoc.v:194873.14-194873.45" wire width 64 $1\core_msr[63:0] - attribute \src "libresoc.v:198919.3-198934.6" + attribute \src "libresoc.v:198083.3-198098.6" wire width 3 $1\core_msr__ren[2:0] - attribute \src "libresoc.v:198119.3-198139.6" - wire width 32 $1\core_raw_insn_i$next[31:0]$13833 - attribute \src "libresoc.v:195562.14-195562.37" + attribute \src "libresoc.v:197292.3-197312.6" + wire width 32 $1\core_raw_insn_i$next[31:0]$13775 + attribute \src "libresoc.v:194881.14-194881.37" wire width 32 $1\core_raw_insn_i[31:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_rego_ok$next[0:0]$14157 - attribute \src "libresoc.v:195566.7-195566.26" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_rego_ok$next[0:0]$14099 + attribute \src "libresoc.v:194885.7-194885.26" wire $1\core_rego_ok[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_spro_ok$next[0:0]$14158 - attribute \src "libresoc.v:195570.7-195570.26" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_spro_ok$next[0:0]$14100 + attribute \src "libresoc.v:194889.7-194889.26" wire $1\core_spro_ok[0:0] - attribute \src "libresoc.v:199449.3-199479.6" + attribute \src "libresoc.v:198622.3-198652.6" wire $1\core_stopped_i[0:0] - attribute \src "libresoc.v:198761.3-198773.6" + attribute \src "libresoc.v:197934.3-197946.6" wire width 3 $1\core_sv__ren[2:0] - attribute \src "libresoc.v:198165.3-198189.6" - wire $1\core_sv_a_nz$next[0:0]$13843 - attribute \src "libresoc.v:195582.7-195582.26" + attribute \src "libresoc.v:197338.3-197362.6" + wire $1\core_sv_a_nz$next[0:0]$13785 + attribute \src "libresoc.v:194901.7-194901.26" wire $1\core_sv_a_nz[0:0] - attribute \src "libresoc.v:198298.3-198307.6" - wire width 3 $1\core_wen$11[2:0]$13854 - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:197471.3-197480.6" + wire width 3 $1\core_wen$11[2:0]$13796 + attribute \src "libresoc.v:197947.3-198014.6" wire width 3 $1\core_wen[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $1\core_xer_out$next[0:0]$14159 - attribute \src "libresoc.v:195592.7-195592.26" + attribute \src "libresoc.v:198886.3-198996.6" + wire $1\core_xer_out$next[0:0]$14101 + attribute \src "libresoc.v:194911.7-194911.26" wire $1\core_xer_out[0:0] - attribute \src "libresoc.v:195598.7-195598.30" + attribute \src "libresoc.v:194917.7-194917.30" wire $1\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $1\cur_cur_dststep$next[6:0]$13943 - attribute \src "libresoc.v:195604.13-195604.36" + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $1\cur_cur_dststep$next[6:0]$13885 + attribute \src "libresoc.v:194923.13-194923.36" wire width 7 $1\cur_cur_dststep[6:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $1\cur_cur_maxvl$next[6:0]$13944 - attribute \src "libresoc.v:195608.13-195608.34" + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $1\cur_cur_maxvl$next[6:0]$13886 + attribute \src "libresoc.v:194927.13-194927.34" wire width 7 $1\cur_cur_maxvl[6:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $1\cur_cur_srcstep$next[6:0]$13945 - attribute \src "libresoc.v:195612.13-195612.36" + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $1\cur_cur_srcstep$next[6:0]$13887 + attribute \src "libresoc.v:194931.13-194931.36" wire width 7 $1\cur_cur_srcstep[6:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $1\cur_cur_subvl$next[1:0]$13946 - attribute \src "libresoc.v:195616.13-195616.33" + attribute \src "libresoc.v:198233.3-198271.6" + wire width 2 $1\cur_cur_subvl$next[1:0]$13888 + attribute \src "libresoc.v:194935.13-194935.33" wire width 2 $1\cur_cur_subvl[1:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $1\cur_cur_svstep$next[1:0]$13947 - attribute \src "libresoc.v:195620.13-195620.34" + attribute \src "libresoc.v:198233.3-198271.6" + wire width 2 $1\cur_cur_svstep$next[1:0]$13889 + attribute \src "libresoc.v:194939.13-194939.34" wire width 2 $1\cur_cur_svstep[1:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $1\cur_cur_vl$next[6:0]$13948 - attribute \src "libresoc.v:195624.13-195624.31" + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $1\cur_cur_vl$next[6:0]$13890 + attribute \src "libresoc.v:194943.13-194943.31" wire width 7 $1\cur_cur_vl[6:0] - attribute \src "libresoc.v:198480.3-198488.6" - wire $1\d_cr_delay$next[0:0]$13879 - attribute \src "libresoc.v:195628.7-195628.24" + attribute \src "libresoc.v:197653.3-197661.6" + wire $1\d_cr_delay$next[0:0]$13821 + attribute \src "libresoc.v:194947.7-194947.24" wire $1\d_cr_delay[0:0] - attribute \src "libresoc.v:198441.3-198449.6" - wire $1\d_reg_delay$next[0:0]$13873 - attribute \src "libresoc.v:195632.7-195632.25" + attribute \src "libresoc.v:197614.3-197622.6" + wire $1\d_reg_delay$next[0:0]$13815 + attribute \src "libresoc.v:194951.7-194951.25" wire $1\d_reg_delay[0:0] - attribute \src "libresoc.v:198519.3-198527.6" - wire $1\d_xer_delay$next[0:0]$13885 - attribute \src "libresoc.v:195636.7-195636.25" + attribute \src "libresoc.v:197692.3-197700.6" + wire $1\d_xer_delay$next[0:0]$13827 + attribute \src "libresoc.v:194955.7-194955.25" wire $1\d_xer_delay[0:0] - attribute \src "libresoc.v:199480.3-199510.6" + attribute \src "libresoc.v:198653.3-198683.6" wire $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:198499.3-198508.6" + attribute \src "libresoc.v:197672.3-197681.6" wire $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:198489.3-198498.6" + attribute \src "libresoc.v:197662.3-197671.6" wire width 64 $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:198460.3-198469.6" + attribute \src "libresoc.v:197633.3-197642.6" wire $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:198450.3-198459.6" + attribute \src "libresoc.v:197623.3-197632.6" wire width 64 $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:198538.3-198547.6" + attribute \src "libresoc.v:197711.3-197720.6" wire $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:198528.3-198537.6" + attribute \src "libresoc.v:197701.3-197710.6" wire width 64 $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:198037.3-198045.6" - wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13780 - attribute \src "libresoc.v:195684.13-195684.34" + attribute \src "libresoc.v:197229.3-197237.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13728 + attribute \src "libresoc.v:195003.13-195003.34" wire width 4 $1\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:198774.3-198782.6" - wire width 64 $1\dbg_dmi_din$next[63:0]$13920 - attribute \src "libresoc.v:195688.14-195688.48" + attribute \src "libresoc.v:198099.3-198107.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$13865 + attribute \src "libresoc.v:195007.14-195007.48" wire width 64 $1\dbg_dmi_din[63:0] - attribute \src "libresoc.v:198046.3-198054.6" - wire $1\dbg_dmi_req_i$next[0:0]$13783 - attribute \src "libresoc.v:195694.7-195694.27" + attribute \src "libresoc.v:197238.3-197246.6" + wire $1\dbg_dmi_req_i$next[0:0]$13731 + attribute \src "libresoc.v:195013.7-195013.27" wire $1\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:198689.3-198697.6" - wire $1\dbg_dmi_we_i$next[0:0]$13907 - attribute \src "libresoc.v:195698.7-195698.26" + attribute \src "libresoc.v:197862.3-197870.6" + wire $1\dbg_dmi_we_i$next[0:0]$13849 + attribute \src "libresoc.v:195017.7-195017.26" wire $1\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:198662.3-198677.6" - wire width 64 $1\dec2_cur_dec$next[63:0]$13902 - attribute \src "libresoc.v:195752.14-195752.49" + attribute \src "libresoc.v:197835.3-197850.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$13844 + attribute \src "libresoc.v:195071.14-195071.49" wire width 64 $1\dec2_cur_dec[63:0] - attribute \src "libresoc.v:198055.3-198063.6" - wire $1\dec2_cur_eint$next[0:0]$13786 - attribute \src "libresoc.v:195756.7-195756.27" + attribute \src "libresoc.v:198997.3-199005.6" + wire $1\dec2_cur_eint$next[0:0]$14190 + attribute \src "libresoc.v:195075.7-195075.27" wire $1\dec2_cur_eint[0:0] - attribute \src "libresoc.v:199192.3-199212.6" - wire width 64 $1\dec2_cur_msr$next[63:0]$13986 - attribute \src "libresoc.v:195760.14-195760.49" + attribute \src "libresoc.v:198365.3-198385.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$13928 + attribute \src "libresoc.v:195079.14-195079.49" wire width 64 $1\dec2_cur_msr[63:0] - attribute \src "libresoc.v:199039.3-199059.6" - wire width 64 $1\dec2_cur_pc$next[63:0]$13933 - attribute \src "libresoc.v:195764.14-195764.48" + attribute \src "libresoc.v:198212.3-198232.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$13875 + attribute \src "libresoc.v:195083.14-195083.48" wire width 64 $1\dec2_cur_pc[63:0] - attribute \src "libresoc.v:199232.3-199262.6" - wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13995 - attribute \src "libresoc.v:195916.14-195916.40" + attribute \src "libresoc.v:198405.3-198435.6" + wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13937 + attribute \src "libresoc.v:195235.14-195235.40" wire width 32 $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:198064.3-198073.6" - wire width 2 $1\delay$next[1:0]$13789 - attribute \src "libresoc.v:196186.13-196186.25" + attribute \src "libresoc.v:199006.3-199015.6" + wire width 2 $1\delay$next[1:0]$14193 + attribute \src "libresoc.v:195505.13-195505.25" wire width 2 $1\delay[1:0] - attribute \src "libresoc.v:198370.3-198404.6" - wire $1\exec_fsm_state$next[0:0]$13863 - attribute \src "libresoc.v:196202.7-196202.28" + attribute \src "libresoc.v:197543.3-197577.6" + wire $1\exec_fsm_state$next[0:0]$13805 + attribute \src "libresoc.v:195521.7-195521.28" wire $1\exec_fsm_state[0:0] - attribute \src "libresoc.v:198318.3-198328.6" + attribute \src "libresoc.v:197491.3-197501.6" wire $1\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:198250.3-198260.6" + attribute \src "libresoc.v:197423.3-197433.6" wire $1\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:198261.3-198276.6" + attribute \src "libresoc.v:197434.3-197449.6" wire $1\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:198405.3-198420.6" + attribute \src "libresoc.v:197578.3-197593.6" wire $1\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:199138.3-199191.6" - wire width 2 $1\fetch_fsm_state$next[1:0]$13978 - attribute \src "libresoc.v:196214.13-196214.35" + attribute \src "libresoc.v:198311.3-198364.6" + wire width 2 $1\fetch_fsm_state$next[1:0]$13920 + attribute \src "libresoc.v:195533.13-195533.35" wire width 2 $1\fetch_fsm_state[1:0] - attribute \src "libresoc.v:199702.3-199712.6" + attribute \src "libresoc.v:198875.3-198885.6" wire $1\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:199263.3-199273.6" + attribute \src "libresoc.v:198436.3-198446.6" wire $1\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:198944.3-198954.6" + attribute \src "libresoc.v:198108.3-198118.6" wire $1\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:199334.3-199349.6" + attribute \src "libresoc.v:198507.3-198522.6" wire $1\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:198578.3-198605.6" - wire width 2 $1\fsm_state$next[1:0]$13892 - attribute \src "libresoc.v:196226.13-196226.29" + attribute \src "libresoc.v:197751.3-197778.6" + wire width 2 $1\fsm_state$next[1:0]$13834 + attribute \src "libresoc.v:195545.13-195545.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:198955.3-198970.6" + attribute \src "libresoc.v:198119.3-198134.6" wire width 48 $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:198971.3-199004.6" + attribute \src "libresoc.v:198144.3-198177.6" wire $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:199005.3-199038.6" + attribute \src "libresoc.v:198178.3-198211.6" wire $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:198190.3-198227.6" + attribute \src "libresoc.v:197363.3-197400.6" wire $1\insn_done[0:0] - attribute \src "libresoc.v:198277.3-198297.6" + attribute \src "libresoc.v:197450.3-197470.6" wire $1\is_last[0:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $1\issue_fsm_state$next[2:0]$14003 - attribute \src "libresoc.v:196486.13-196486.35" + attribute \src "libresoc.v:198523.3-198621.6" + wire width 3 $1\issue_fsm_state$next[2:0]$13945 + attribute \src "libresoc.v:195805.13-195805.35" wire width 3 $1\issue_fsm_state[2:0] - attribute \src "libresoc.v:198935.3-198943.6" - wire $1\jtag_dmi0__ack_o$next[0:0]$13926 - attribute \src "libresoc.v:196490.7-196490.30" + attribute \src "libresoc.v:198135.3-198143.6" + wire $1\jtag_dmi0__ack_o$next[0:0]$13870 + attribute \src "libresoc.v:195809.7-195809.30" wire $1\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:199099.3-199107.6" - wire width 64 $1\jtag_dmi0__dout$next[63:0]$13969 - attribute \src "libresoc.v:196498.14-196498.52" + attribute \src "libresoc.v:198302.3-198310.6" + wire width 64 $1\jtag_dmi0__dout$next[63:0]$13917 + attribute \src "libresoc.v:195817.14-195817.52" wire width 64 $1\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:199108.3-199137.6" - wire $1\msr_read$next[0:0]$13972 - attribute \src "libresoc.v:196556.7-196556.22" + attribute \src "libresoc.v:198272.3-198301.6" + wire $1\msr_read$next[0:0]$13911 + attribute \src "libresoc.v:195873.7-195873.22" wire $1\msr_read[0:0] - attribute \src "libresoc.v:198606.3-198616.6" + attribute \src "libresoc.v:197779.3-197789.6" wire width 64 $1\new_dec[63:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $1\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $1\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $1\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 2 $1\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 2 $1\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $1\new_svstate_vl[6:0] - attribute \src "libresoc.v:198678.3-198688.6" + attribute \src "libresoc.v:197851.3-197861.6" wire width 64 $1\new_tb[63:0] - attribute \src "libresoc.v:199213.3-199231.6" - wire width 64 $1\nia$next[63:0]$13991 - attribute \src "libresoc.v:196596.14-196596.40" + attribute \src "libresoc.v:198386.3-198404.6" + wire width 64 $1\nia$next[63:0]$13933 + attribute \src "libresoc.v:195913.14-195913.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:198707.3-198722.6" + attribute \src "libresoc.v:197880.3-197895.6" wire width 64 $1\pc[63:0] - attribute \src "libresoc.v:199511.3-199577.6" - wire $1\pc_changed$next[0:0]$14019 - attribute \src "libresoc.v:196602.7-196602.24" + attribute \src "libresoc.v:198684.3-198750.6" + wire $1\pc_changed$next[0:0]$13961 + attribute \src "libresoc.v:195919.7-195919.24" wire $1\pc_changed[0:0] - attribute \src "libresoc.v:198698.3-198706.6" - wire $1\pc_ok_delay$next[0:0]$13910 - attribute \src "libresoc.v:196612.7-196612.25" + attribute \src "libresoc.v:197871.3-197879.6" + wire $1\pc_ok_delay$next[0:0]$13852 + attribute \src "libresoc.v:195929.7-195929.25" wire $1\pc_ok_delay[0:0] - attribute \src "libresoc.v:198228.3-198238.6" + attribute \src "libresoc.v:197401.3-197411.6" wire $1\pred_insn_valid_i[0:0] - attribute \src "libresoc.v:198239.3-198249.6" + attribute \src "libresoc.v:197412.3-197422.6" wire $1\pred_mask_ready_i[0:0] - attribute \src "libresoc.v:199635.3-199701.6" - wire $1\sv_changed$next[0:0]$14031 - attribute \src "libresoc.v:197056.7-197056.24" + attribute \src "libresoc.v:198808.3-198874.6" + wire $1\sv_changed$next[0:0]$13973 + attribute \src "libresoc.v:196301.7-196301.24" wire $1\sv_changed[0:0] - attribute \src "libresoc.v:198745.3-198760.6" + attribute \src "libresoc.v:197918.3-197933.6" wire width 64 $1\svstate[63:0] - attribute \src "libresoc.v:198736.3-198744.6" - wire $1\svstate_ok_delay$next[0:0]$13915 - attribute \src "libresoc.v:197066.7-197066.30" + attribute \src "libresoc.v:197909.3-197917.6" + wire $1\svstate_ok_delay$next[0:0]$13857 + attribute \src "libresoc.v:196311.7-196311.30" wire $1\svstate_ok_delay[0:0] - attribute \src "libresoc.v:199578.3-199634.6" + attribute \src "libresoc.v:198751.3-198807.6" wire $1\update_svstate[0:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $2\core_asmcode$next[7:0]$14160 - attribute \src "libresoc.v:198140.3-198164.6" - wire $2\core_bigendian_i$10$next[0:0]$13839 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 64 $2\core_core_core_cia$next[63:0]$14161 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $2\core_core_core_cr_rd$next[7:0]$14162 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_cr_rd_ok$next[0:0]$14163 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $2\core_core_core_cr_wr$next[7:0]$14164 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_exc_$signal$3$next[0:0]$14165 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_exc_$signal$4$next[0:0]$14166 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_exc_$signal$5$next[0:0]$14167 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_exc_$signal$6$next[0:0]$14168 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_exc_$signal$7$next[0:0]$14169 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_exc_$signal$8$next[0:0]$14170 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_exc_$signal$9$next[0:0]$14171 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_exc_$signal$next[0:0]$14172 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 14 $2\core_core_core_fn_unit$next[13:0]$14173 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 2 $2\core_core_core_input_carry$next[1:0]$14174 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 32 $2\core_core_core_insn$next[31:0]$14175 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_core_insn_type$next[6:0]$14176 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_is_32bit$next[0:0]$14177 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 64 $2\core_core_core_msr$next[63:0]$14178 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_oe$next[0:0]$14179 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_oe_ok$next[0:0]$14180 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_rc$next[0:0]$14181 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_core_rc_ok$next[0:0]$14182 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 13 $2\core_core_core_trapaddr$next[12:0]$14183 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 8 $2\core_core_core_traptype$next[7:0]$14184 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_cr_in1$next[6:0]$14185 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_cr_in1_ok$next[0:0]$14186 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_cr_in2$1$next[6:0]$14187 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_cr_in2$next[6:0]$14188 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_cr_in2_ok$2$next[0:0]$14189 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_cr_in2_ok$next[0:0]$14190 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_cr_out$next[6:0]$14191 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_cr_wr_ok$next[0:0]$14192 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $2\core_core_dststep$next[6:0]$13811 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_ea$next[6:0]$14193 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $2\core_core_fast1$next[2:0]$14194 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_fast1_ok$next[0:0]$14195 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $2\core_core_fast2$next[2:0]$14196 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_fast2_ok$next[0:0]$14197 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $2\core_core_fasto1$next[2:0]$14198 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $2\core_core_fasto2$next[2:0]$14199 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_lk$next[0:0]$14200 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $2\core_core_maxvl$next[6:0]$13812 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $2\core_core_pc$next[63:0]$13813 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_reg1$next[6:0]$14201 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_reg1_ok$next[0:0]$14202 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_reg2$next[6:0]$14203 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_reg2_ok$next[0:0]$14204 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_reg3$next[6:0]$14205 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_reg3_ok$next[0:0]$14206 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 7 $2\core_core_rego$next[6:0]$14207 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 10 $2\core_core_spr1$next[9:0]$14208 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_core_spr1_ok$next[0:0]$14209 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 10 $2\core_core_spro$next[9:0]$14210 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $2\core_core_srcstep$next[6:0]$13814 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 2 $2\core_core_subvl$next[1:0]$13815 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 2 $2\core_core_svstep$next[1:0]$13816 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $2\core_core_vl$next[6:0]$13817 - attribute \src "libresoc.v:199713.3-199823.6" - wire width 3 $2\core_core_xer_in$next[2:0]$14211 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_cr_out_ok$next[0:0]$14212 - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:198886.3-198996.6" + wire width 8 $2\core_asmcode$next[7:0]$14102 + attribute \src "libresoc.v:197313.3-197337.6" + wire $2\core_bigendian_i$10$next[0:0]$13781 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 64 $2\core_core_core_cia$next[63:0]$14103 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 8 $2\core_core_core_cr_rd$next[7:0]$14104 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_core_cr_rd_ok$next[0:0]$14105 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 8 $2\core_core_core_cr_wr$next[7:0]$14106 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_core_exc_$signal$3$next[0:0]$14107 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_core_exc_$signal$4$next[0:0]$14108 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_core_exc_$signal$5$next[0:0]$14109 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_core_exc_$signal$6$next[0:0]$14110 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_core_exc_$signal$7$next[0:0]$14111 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_core_exc_$signal$8$next[0:0]$14112 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_core_exc_$signal$9$next[0:0]$14113 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_core_exc_$signal$next[0:0]$14114 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 14 $2\core_core_core_fn_unit$next[13:0]$14115 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 2 $2\core_core_core_input_carry$next[1:0]$14116 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 32 $2\core_core_core_insn$next[31:0]$14117 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $2\core_core_core_insn_type$next[6:0]$14118 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_core_is_32bit$next[0:0]$14119 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 64 $2\core_core_core_msr$next[63:0]$14120 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_core_oe$next[0:0]$14121 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_core_oe_ok$next[0:0]$14122 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_core_rc$next[0:0]$14123 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_core_rc_ok$next[0:0]$14124 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 13 $2\core_core_core_trapaddr$next[12:0]$14125 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 8 $2\core_core_core_traptype$next[7:0]$14126 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $2\core_core_cr_in1$next[6:0]$14127 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_cr_in1_ok$next[0:0]$14128 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $2\core_core_cr_in2$1$next[6:0]$14129 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $2\core_core_cr_in2$next[6:0]$14130 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_cr_in2_ok$2$next[0:0]$14131 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_cr_in2_ok$next[0:0]$14132 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $2\core_core_cr_out$next[6:0]$14133 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_cr_wr_ok$next[0:0]$14134 + attribute \src "libresoc.v:197247.3-197291.6" + wire width 7 $2\core_core_dststep$next[6:0]$13753 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $2\core_core_ea$next[6:0]$14135 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 3 $2\core_core_fast1$next[2:0]$14136 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_fast1_ok$next[0:0]$14137 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 3 $2\core_core_fast2$next[2:0]$14138 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_fast2_ok$next[0:0]$14139 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 3 $2\core_core_fasto1$next[2:0]$14140 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 3 $2\core_core_fasto2$next[2:0]$14141 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_lk$next[0:0]$14142 + attribute \src "libresoc.v:197247.3-197291.6" + wire width 7 $2\core_core_maxvl$next[6:0]$13754 + attribute \src "libresoc.v:197247.3-197291.6" + wire width 64 $2\core_core_pc$next[63:0]$13755 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $2\core_core_reg1$next[6:0]$14143 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_reg1_ok$next[0:0]$14144 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $2\core_core_reg2$next[6:0]$14145 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_reg2_ok$next[0:0]$14146 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $2\core_core_reg3$next[6:0]$14147 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_reg3_ok$next[0:0]$14148 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 7 $2\core_core_rego$next[6:0]$14149 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 10 $2\core_core_spr1$next[9:0]$14150 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_core_spr1_ok$next[0:0]$14151 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 10 $2\core_core_spro$next[9:0]$14152 + attribute \src "libresoc.v:197247.3-197291.6" + wire width 7 $2\core_core_srcstep$next[6:0]$13756 + attribute \src "libresoc.v:197247.3-197291.6" + wire width 2 $2\core_core_subvl$next[1:0]$13757 + attribute \src "libresoc.v:197247.3-197291.6" + wire width 2 $2\core_core_svstep$next[1:0]$13758 + attribute \src "libresoc.v:197247.3-197291.6" + wire width 7 $2\core_core_vl$next[6:0]$13759 + attribute \src "libresoc.v:198886.3-198996.6" + wire width 3 $2\core_core_xer_in$next[2:0]$14153 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_cr_out_ok$next[0:0]$14154 + attribute \src "libresoc.v:198015.3-198082.6" wire width 64 $2\core_data_i[63:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $2\core_dec$next[63:0]$13818 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_ea_ok$next[0:0]$14213 - attribute \src "libresoc.v:198074.3-198118.6" - wire $2\core_eint$next[0:0]$13819 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_fasto1_ok$next[0:0]$14214 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_fasto2_ok$next[0:0]$14215 - attribute \src "libresoc.v:198354.3-198369.6" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 64 $2\core_dec$next[63:0]$13760 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_ea_ok$next[0:0]$14155 + attribute \src "libresoc.v:197247.3-197291.6" + wire $2\core_eint$next[0:0]$13761 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_fasto1_ok$next[0:0]$14156 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_fasto2_ok$next[0:0]$14157 + attribute \src "libresoc.v:197527.3-197542.6" wire $2\core_issue_i[0:0] - attribute \src "libresoc.v:198329.3-198353.6" + attribute \src "libresoc.v:197502.3-197526.6" wire $2\core_ivalid_i[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $2\core_msr$next[63:0]$13820 - attribute \src "libresoc.v:198919.3-198934.6" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 64 $2\core_msr$next[63:0]$13762 + attribute \src "libresoc.v:198083.3-198098.6" wire width 3 $2\core_msr__ren[2:0] - attribute \src "libresoc.v:198119.3-198139.6" - wire width 32 $2\core_raw_insn_i$next[31:0]$13834 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_rego_ok$next[0:0]$14216 - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_spro_ok$next[0:0]$14217 - attribute \src "libresoc.v:199449.3-199479.6" + attribute \src "libresoc.v:197292.3-197312.6" + wire width 32 $2\core_raw_insn_i$next[31:0]$13776 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_rego_ok$next[0:0]$14158 + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_spro_ok$next[0:0]$14159 + attribute \src "libresoc.v:198622.3-198652.6" wire $2\core_stopped_i[0:0] - attribute \src "libresoc.v:198165.3-198189.6" - wire $2\core_sv_a_nz$next[0:0]$13844 - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:197338.3-197362.6" + wire $2\core_sv_a_nz$next[0:0]$13786 + attribute \src "libresoc.v:197947.3-198014.6" wire width 3 $2\core_wen[2:0] - attribute \src "libresoc.v:199713.3-199823.6" - wire $2\core_xer_out$next[0:0]$14218 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $2\cur_cur_dststep$next[6:0]$13949 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $2\cur_cur_maxvl$next[6:0]$13950 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $2\cur_cur_srcstep$next[6:0]$13951 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $2\cur_cur_subvl$next[1:0]$13952 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $2\cur_cur_svstep$next[1:0]$13953 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $2\cur_cur_vl$next[6:0]$13954 - attribute \src "libresoc.v:199480.3-199510.6" + attribute \src "libresoc.v:198886.3-198996.6" + wire $2\core_xer_out$next[0:0]$14160 + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $2\cur_cur_dststep$next[6:0]$13891 + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $2\cur_cur_maxvl$next[6:0]$13892 + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $2\cur_cur_srcstep$next[6:0]$13893 + attribute \src "libresoc.v:198233.3-198271.6" + wire width 2 $2\cur_cur_subvl$next[1:0]$13894 + attribute \src "libresoc.v:198233.3-198271.6" + wire width 2 $2\cur_cur_svstep$next[1:0]$13895 + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $2\cur_cur_vl$next[6:0]$13896 + attribute \src "libresoc.v:198653.3-198683.6" wire $2\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:198662.3-198677.6" - wire width 64 $2\dec2_cur_dec$next[63:0]$13903 - attribute \src "libresoc.v:199192.3-199212.6" - wire width 64 $2\dec2_cur_msr$next[63:0]$13987 - attribute \src "libresoc.v:199039.3-199059.6" - wire width 64 $2\dec2_cur_pc$next[63:0]$13934 - attribute \src "libresoc.v:199232.3-199262.6" - wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13996 - attribute \src "libresoc.v:198370.3-198404.6" - wire $2\exec_fsm_state$next[0:0]$13864 - attribute \src "libresoc.v:198261.3-198276.6" + attribute \src "libresoc.v:197835.3-197850.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$13845 + attribute \src "libresoc.v:198365.3-198385.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$13929 + attribute \src "libresoc.v:198212.3-198232.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$13876 + attribute \src "libresoc.v:198405.3-198435.6" + wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13938 + attribute \src "libresoc.v:197543.3-197577.6" + wire $2\exec_fsm_state$next[0:0]$13806 + attribute \src "libresoc.v:197434.3-197449.6" wire $2\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:198405.3-198420.6" + attribute \src "libresoc.v:197578.3-197593.6" wire $2\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:199138.3-199191.6" - wire width 2 $2\fetch_fsm_state$next[1:0]$13979 - attribute \src "libresoc.v:199334.3-199349.6" + attribute \src "libresoc.v:198311.3-198364.6" + wire width 2 $2\fetch_fsm_state$next[1:0]$13921 + attribute \src "libresoc.v:198507.3-198522.6" wire $2\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:198578.3-198605.6" - wire width 2 $2\fsm_state$next[1:0]$13893 - attribute \src "libresoc.v:198955.3-198970.6" + attribute \src "libresoc.v:197751.3-197778.6" + wire width 2 $2\fsm_state$next[1:0]$13835 + attribute \src "libresoc.v:198119.3-198134.6" wire width 48 $2\imem_a_pc_i[47:0] - attribute \src "libresoc.v:198971.3-199004.6" + attribute \src "libresoc.v:198144.3-198177.6" wire $2\imem_a_valid_i[0:0] - attribute \src "libresoc.v:199005.3-199038.6" + attribute \src "libresoc.v:198178.3-198211.6" wire $2\imem_f_valid_i[0:0] - attribute \src "libresoc.v:198190.3-198227.6" + attribute \src "libresoc.v:197363.3-197400.6" wire $2\insn_done[0:0] - attribute \src "libresoc.v:198277.3-198297.6" + attribute \src "libresoc.v:197450.3-197470.6" wire $2\is_last[0:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $2\issue_fsm_state$next[2:0]$14004 - attribute \src "libresoc.v:199108.3-199137.6" - wire $2\msr_read$next[0:0]$13973 - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198523.3-198621.6" + wire width 3 $2\issue_fsm_state$next[2:0]$13946 + attribute \src "libresoc.v:198272.3-198301.6" + wire $2\msr_read$next[0:0]$13912 + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $2\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $2\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $2\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 2 $2\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 2 $2\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $2\new_svstate_vl[6:0] - attribute \src "libresoc.v:199213.3-199231.6" - wire width 64 $2\nia$next[63:0]$13992 - attribute \src "libresoc.v:198707.3-198722.6" + attribute \src "libresoc.v:198386.3-198404.6" + wire width 64 $2\nia$next[63:0]$13934 + attribute \src "libresoc.v:197880.3-197895.6" wire width 64 $2\pc[63:0] - attribute \src "libresoc.v:199511.3-199577.6" - wire $2\pc_changed$next[0:0]$14020 - attribute \src "libresoc.v:199635.3-199701.6" - wire $2\sv_changed$next[0:0]$14032 - attribute \src "libresoc.v:198745.3-198760.6" + attribute \src "libresoc.v:198684.3-198750.6" + wire $2\pc_changed$next[0:0]$13962 + attribute \src "libresoc.v:198808.3-198874.6" + wire $2\sv_changed$next[0:0]$13974 + attribute \src "libresoc.v:197918.3-197933.6" wire width 64 $2\svstate[63:0] - attribute \src "libresoc.v:199578.3-199634.6" + attribute \src "libresoc.v:198751.3-198807.6" wire $2\update_svstate[0:0] - attribute \src "libresoc.v:198140.3-198164.6" - wire $3\core_bigendian_i$10$next[0:0]$13840 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_cr_rd_ok$next[0:0]$14219 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_exc_$signal$3$next[0:0]$14220 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_exc_$signal$4$next[0:0]$14221 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_exc_$signal$5$next[0:0]$14222 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_exc_$signal$6$next[0:0]$14223 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_exc_$signal$7$next[0:0]$14224 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_exc_$signal$8$next[0:0]$14225 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_exc_$signal$9$next[0:0]$14226 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_exc_$signal$next[0:0]$14227 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_oe_ok$next[0:0]$14228 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_core_rc_ok$next[0:0]$14229 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_cr_in1_ok$next[0:0]$14230 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_cr_in2_ok$2$next[0:0]$14231 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_cr_in2_ok$next[0:0]$14232 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_cr_wr_ok$next[0:0]$14233 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $3\core_core_dststep$next[6:0]$13821 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_fast1_ok$next[0:0]$14234 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_fast2_ok$next[0:0]$14235 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $3\core_core_maxvl$next[6:0]$13822 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $3\core_core_pc$next[63:0]$13823 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_reg1_ok$next[0:0]$14236 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_reg2_ok$next[0:0]$14237 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_reg3_ok$next[0:0]$14238 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_core_spr1_ok$next[0:0]$14239 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $3\core_core_srcstep$next[6:0]$13824 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 2 $3\core_core_subvl$next[1:0]$13825 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 2 $3\core_core_svstep$next[1:0]$13826 - attribute \src "libresoc.v:198074.3-198118.6" - wire width 7 $3\core_core_vl$next[6:0]$13827 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_cr_out_ok$next[0:0]$14240 - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:197313.3-197337.6" + wire $3\core_bigendian_i$10$next[0:0]$13782 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_core_cr_rd_ok$next[0:0]$14161 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_core_exc_$signal$3$next[0:0]$14162 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_core_exc_$signal$4$next[0:0]$14163 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_core_exc_$signal$5$next[0:0]$14164 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_core_exc_$signal$6$next[0:0]$14165 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_core_exc_$signal$7$next[0:0]$14166 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_core_exc_$signal$8$next[0:0]$14167 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_core_exc_$signal$9$next[0:0]$14168 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_core_exc_$signal$next[0:0]$14169 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_core_oe_ok$next[0:0]$14170 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_core_rc_ok$next[0:0]$14171 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_cr_in1_ok$next[0:0]$14172 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_cr_in2_ok$2$next[0:0]$14173 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_cr_in2_ok$next[0:0]$14174 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_cr_wr_ok$next[0:0]$14175 + attribute \src "libresoc.v:197247.3-197291.6" + wire width 7 $3\core_core_dststep$next[6:0]$13763 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_fast1_ok$next[0:0]$14176 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_fast2_ok$next[0:0]$14177 + attribute \src "libresoc.v:197247.3-197291.6" + wire width 7 $3\core_core_maxvl$next[6:0]$13764 + attribute \src "libresoc.v:197247.3-197291.6" + wire width 64 $3\core_core_pc$next[63:0]$13765 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_reg1_ok$next[0:0]$14178 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_reg2_ok$next[0:0]$14179 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_reg3_ok$next[0:0]$14180 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_core_spr1_ok$next[0:0]$14181 + attribute \src "libresoc.v:197247.3-197291.6" + wire width 7 $3\core_core_srcstep$next[6:0]$13766 + attribute \src "libresoc.v:197247.3-197291.6" + wire width 2 $3\core_core_subvl$next[1:0]$13767 + attribute \src "libresoc.v:197247.3-197291.6" + wire width 2 $3\core_core_svstep$next[1:0]$13768 + attribute \src "libresoc.v:197247.3-197291.6" + wire width 7 $3\core_core_vl$next[6:0]$13769 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_cr_out_ok$next[0:0]$14182 + attribute \src "libresoc.v:198015.3-198082.6" wire width 64 $3\core_data_i[63:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $3\core_dec$next[63:0]$13828 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_ea_ok$next[0:0]$14241 - attribute \src "libresoc.v:198074.3-198118.6" - wire $3\core_eint$next[0:0]$13829 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_fasto1_ok$next[0:0]$14242 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_fasto2_ok$next[0:0]$14243 - attribute \src "libresoc.v:198329.3-198353.6" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 64 $3\core_dec$next[63:0]$13770 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_ea_ok$next[0:0]$14183 + attribute \src "libresoc.v:197247.3-197291.6" + wire $3\core_eint$next[0:0]$13771 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_fasto1_ok$next[0:0]$14184 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_fasto2_ok$next[0:0]$14185 + attribute \src "libresoc.v:197502.3-197526.6" wire $3\core_ivalid_i[0:0] - attribute \src "libresoc.v:198074.3-198118.6" - wire width 64 $3\core_msr$next[63:0]$13830 - attribute \src "libresoc.v:198119.3-198139.6" - wire width 32 $3\core_raw_insn_i$next[31:0]$13835 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_rego_ok$next[0:0]$14244 - attribute \src "libresoc.v:199713.3-199823.6" - wire $3\core_spro_ok$next[0:0]$14245 - attribute \src "libresoc.v:199449.3-199479.6" + attribute \src "libresoc.v:197247.3-197291.6" + wire width 64 $3\core_msr$next[63:0]$13772 + attribute \src "libresoc.v:197292.3-197312.6" + wire width 32 $3\core_raw_insn_i$next[31:0]$13777 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_rego_ok$next[0:0]$14186 + attribute \src "libresoc.v:198886.3-198996.6" + wire $3\core_spro_ok$next[0:0]$14187 + attribute \src "libresoc.v:198622.3-198652.6" wire $3\core_stopped_i[0:0] - attribute \src "libresoc.v:198165.3-198189.6" - wire $3\core_sv_a_nz$next[0:0]$13845 - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:197338.3-197362.6" + wire $3\core_sv_a_nz$next[0:0]$13787 + attribute \src "libresoc.v:197947.3-198014.6" wire width 3 $3\core_wen[2:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $3\cur_cur_dststep$next[6:0]$13955 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $3\cur_cur_maxvl$next[6:0]$13956 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $3\cur_cur_srcstep$next[6:0]$13957 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $3\cur_cur_subvl$next[1:0]$13958 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $3\cur_cur_svstep$next[1:0]$13959 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $3\cur_cur_vl$next[6:0]$13960 - attribute \src "libresoc.v:199480.3-199510.6" + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $3\cur_cur_dststep$next[6:0]$13897 + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $3\cur_cur_maxvl$next[6:0]$13898 + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $3\cur_cur_srcstep$next[6:0]$13899 + attribute \src "libresoc.v:198233.3-198271.6" + wire width 2 $3\cur_cur_subvl$next[1:0]$13900 + attribute \src "libresoc.v:198233.3-198271.6" + wire width 2 $3\cur_cur_svstep$next[1:0]$13901 + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $3\cur_cur_vl$next[6:0]$13902 + attribute \src "libresoc.v:198653.3-198683.6" wire $3\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:199192.3-199212.6" - wire width 64 $3\dec2_cur_msr$next[63:0]$13988 - attribute \src "libresoc.v:199039.3-199059.6" - wire width 64 $3\dec2_cur_pc$next[63:0]$13935 - attribute \src "libresoc.v:199232.3-199262.6" - wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13997 - attribute \src "libresoc.v:198370.3-198404.6" - wire $3\exec_fsm_state$next[0:0]$13865 - attribute \src "libresoc.v:199138.3-199191.6" - wire width 2 $3\fetch_fsm_state$next[1:0]$13980 - attribute \src "libresoc.v:198971.3-199004.6" + attribute \src "libresoc.v:198365.3-198385.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$13930 + attribute \src "libresoc.v:198212.3-198232.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$13877 + attribute \src "libresoc.v:198405.3-198435.6" + wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13939 + attribute \src "libresoc.v:197543.3-197577.6" + wire $3\exec_fsm_state$next[0:0]$13807 + attribute \src "libresoc.v:198311.3-198364.6" + wire width 2 $3\fetch_fsm_state$next[1:0]$13922 + attribute \src "libresoc.v:198144.3-198177.6" wire $3\imem_a_valid_i[0:0] - attribute \src "libresoc.v:199005.3-199038.6" + attribute \src "libresoc.v:198178.3-198211.6" wire $3\imem_f_valid_i[0:0] - attribute \src "libresoc.v:198190.3-198227.6" + attribute \src "libresoc.v:197363.3-197400.6" wire $3\insn_done[0:0] - attribute \src "libresoc.v:198277.3-198297.6" + attribute \src "libresoc.v:197450.3-197470.6" wire $3\is_last[0:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $3\issue_fsm_state$next[2:0]$14005 - attribute \src "libresoc.v:199108.3-199137.6" - wire $3\msr_read$next[0:0]$13974 - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198523.3-198621.6" + wire width 3 $3\issue_fsm_state$next[2:0]$13947 + attribute \src "libresoc.v:198272.3-198301.6" + wire $3\msr_read$next[0:0]$13913 + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $3\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $3\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $3\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 2 $3\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 2 $3\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $3\new_svstate_vl[6:0] - attribute \src "libresoc.v:199511.3-199577.6" - wire $3\pc_changed$next[0:0]$14021 - attribute \src "libresoc.v:199635.3-199701.6" - wire $3\sv_changed$next[0:0]$14033 - attribute \src "libresoc.v:199578.3-199634.6" + attribute \src "libresoc.v:198684.3-198750.6" + wire $3\pc_changed$next[0:0]$13963 + attribute \src "libresoc.v:198808.3-198874.6" + wire $3\sv_changed$next[0:0]$13975 + attribute \src "libresoc.v:198751.3-198807.6" wire $3\update_svstate[0:0] - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:198015.3-198082.6" wire width 64 $4\core_data_i[63:0] - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:197947.3-198014.6" wire width 3 $4\core_wen[2:0] - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $4\cur_cur_dststep$next[6:0]$13961 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $4\cur_cur_maxvl$next[6:0]$13962 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $4\cur_cur_srcstep$next[6:0]$13963 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $4\cur_cur_subvl$next[1:0]$13964 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 2 $4\cur_cur_svstep$next[1:0]$13965 - attribute \src "libresoc.v:199060.3-199098.6" - wire width 7 $4\cur_cur_vl$next[6:0]$13966 - attribute \src "libresoc.v:198370.3-198404.6" - wire $4\exec_fsm_state$next[0:0]$13866 - attribute \src "libresoc.v:199138.3-199191.6" - wire width 2 $4\fetch_fsm_state$next[1:0]$13981 - attribute \src "libresoc.v:198971.3-199004.6" + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $4\cur_cur_dststep$next[6:0]$13903 + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $4\cur_cur_maxvl$next[6:0]$13904 + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $4\cur_cur_srcstep$next[6:0]$13905 + attribute \src "libresoc.v:198233.3-198271.6" + wire width 2 $4\cur_cur_subvl$next[1:0]$13906 + attribute \src "libresoc.v:198233.3-198271.6" + wire width 2 $4\cur_cur_svstep$next[1:0]$13907 + attribute \src "libresoc.v:198233.3-198271.6" + wire width 7 $4\cur_cur_vl$next[6:0]$13908 + attribute \src "libresoc.v:197543.3-197577.6" + wire $4\exec_fsm_state$next[0:0]$13808 + attribute \src "libresoc.v:198311.3-198364.6" + wire width 2 $4\fetch_fsm_state$next[1:0]$13923 + attribute \src "libresoc.v:198144.3-198177.6" wire $4\imem_a_valid_i[0:0] - attribute \src "libresoc.v:199005.3-199038.6" + attribute \src "libresoc.v:198178.3-198211.6" wire $4\imem_f_valid_i[0:0] - attribute \src "libresoc.v:198190.3-198227.6" + attribute \src "libresoc.v:197363.3-197400.6" wire $4\insn_done[0:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $4\issue_fsm_state$next[2:0]$14006 - attribute \src "libresoc.v:199108.3-199137.6" - wire $4\msr_read$next[0:0]$13975 - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198523.3-198621.6" + wire width 3 $4\issue_fsm_state$next[2:0]$13948 + attribute \src "libresoc.v:198272.3-198301.6" + wire $4\msr_read$next[0:0]$13914 + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $4\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $4\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $4\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 2 $4\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 2 $4\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $4\new_svstate_vl[6:0] - attribute \src "libresoc.v:199511.3-199577.6" - wire $4\pc_changed$next[0:0]$14022 - attribute \src "libresoc.v:199635.3-199701.6" - wire $4\sv_changed$next[0:0]$14034 - attribute \src "libresoc.v:199578.3-199634.6" + attribute \src "libresoc.v:198684.3-198750.6" + wire $4\pc_changed$next[0:0]$13964 + attribute \src "libresoc.v:198808.3-198874.6" + wire $4\sv_changed$next[0:0]$13976 + attribute \src "libresoc.v:198751.3-198807.6" wire $4\update_svstate[0:0] - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:198015.3-198082.6" wire width 64 $5\core_data_i[63:0] - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:197947.3-198014.6" wire width 3 $5\core_wen[2:0] - attribute \src "libresoc.v:198370.3-198404.6" - wire $5\exec_fsm_state$next[0:0]$13867 - attribute \src "libresoc.v:199138.3-199191.6" - wire width 2 $5\fetch_fsm_state$next[1:0]$13982 - attribute \src "libresoc.v:198190.3-198227.6" + attribute \src "libresoc.v:197543.3-197577.6" + wire $5\exec_fsm_state$next[0:0]$13809 + attribute \src "libresoc.v:198311.3-198364.6" + wire width 2 $5\fetch_fsm_state$next[1:0]$13924 + attribute \src "libresoc.v:197363.3-197400.6" wire $5\insn_done[0:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $5\issue_fsm_state$next[2:0]$14007 - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198523.3-198621.6" + wire width 3 $5\issue_fsm_state$next[2:0]$13949 + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $5\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $5\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $5\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 2 $5\new_svstate_subvl[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 2 $5\new_svstate_svstep[1:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $5\new_svstate_vl[6:0] - attribute \src "libresoc.v:199511.3-199577.6" - wire $5\pc_changed$next[0:0]$14023 - attribute \src "libresoc.v:199635.3-199701.6" - wire $5\sv_changed$next[0:0]$14035 - attribute \src "libresoc.v:199578.3-199634.6" + attribute \src "libresoc.v:198684.3-198750.6" + wire $5\pc_changed$next[0:0]$13965 + attribute \src "libresoc.v:198808.3-198874.6" + wire $5\sv_changed$next[0:0]$13977 + attribute \src "libresoc.v:198751.3-198807.6" wire $5\update_svstate[0:0] - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:198015.3-198082.6" wire width 64 $6\core_data_i[63:0] - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:197947.3-198014.6" wire width 3 $6\core_wen[2:0] - attribute \src "libresoc.v:199138.3-199191.6" - wire width 2 $6\fetch_fsm_state$next[1:0]$13983 - attribute \src "libresoc.v:198190.3-198227.6" + attribute \src "libresoc.v:198311.3-198364.6" + wire width 2 $6\fetch_fsm_state$next[1:0]$13925 + attribute \src "libresoc.v:197363.3-197400.6" wire $6\insn_done[0:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $6\issue_fsm_state$next[2:0]$14008 - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198523.3-198621.6" + wire width 3 $6\issue_fsm_state$next[2:0]$13950 + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $6\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $6\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199511.3-199577.6" - wire $6\pc_changed$next[0:0]$14024 - attribute \src "libresoc.v:199635.3-199701.6" - wire $6\sv_changed$next[0:0]$14036 - attribute \src "libresoc.v:199578.3-199634.6" + attribute \src "libresoc.v:198684.3-198750.6" + wire $6\pc_changed$next[0:0]$13966 + attribute \src "libresoc.v:198808.3-198874.6" + wire $6\sv_changed$next[0:0]$13978 + attribute \src "libresoc.v:198751.3-198807.6" wire $6\update_svstate[0:0] - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:198015.3-198082.6" wire width 64 $7\core_data_i[63:0] - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:197947.3-198014.6" wire width 3 $7\core_wen[2:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $7\issue_fsm_state$next[2:0]$14009 - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198523.3-198621.6" + wire width 3 $7\issue_fsm_state$next[2:0]$13951 + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $7\new_svstate_dststep[6:0] - attribute \src "libresoc.v:199274.3-199333.6" + attribute \src "libresoc.v:198447.3-198506.6" wire width 7 $7\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:199511.3-199577.6" - wire $7\pc_changed$next[0:0]$14025 - attribute \src "libresoc.v:199635.3-199701.6" - wire $7\sv_changed$next[0:0]$14037 - attribute \src "libresoc.v:199578.3-199634.6" + attribute \src "libresoc.v:198684.3-198750.6" + wire $7\pc_changed$next[0:0]$13967 + attribute \src "libresoc.v:198808.3-198874.6" + wire $7\sv_changed$next[0:0]$13979 + attribute \src "libresoc.v:198751.3-198807.6" wire $7\update_svstate[0:0] - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:198015.3-198082.6" wire width 64 $8\core_data_i[63:0] - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:197947.3-198014.6" wire width 3 $8\core_wen[2:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $8\issue_fsm_state$next[2:0]$14010 - attribute \src "libresoc.v:199511.3-199577.6" - wire $8\pc_changed$next[0:0]$14026 - attribute \src "libresoc.v:199635.3-199701.6" - wire $8\sv_changed$next[0:0]$14038 - attribute \src "libresoc.v:198851.3-198918.6" + attribute \src "libresoc.v:198523.3-198621.6" + wire width 3 $8\issue_fsm_state$next[2:0]$13952 + attribute \src "libresoc.v:198684.3-198750.6" + wire $8\pc_changed$next[0:0]$13968 + attribute \src "libresoc.v:198808.3-198874.6" + wire $8\sv_changed$next[0:0]$13980 + attribute \src "libresoc.v:198015.3-198082.6" wire width 64 $9\core_data_i[63:0] - attribute \src "libresoc.v:198783.3-198850.6" + attribute \src "libresoc.v:197947.3-198014.6" wire width 3 $9\core_wen[2:0] - attribute \src "libresoc.v:199350.3-199448.6" - wire width 3 $9\issue_fsm_state$next[2:0]$14011 - attribute \src "libresoc.v:199511.3-199577.6" - wire $9\pc_changed$next[0:0]$14027 - attribute \src "libresoc.v:199635.3-199701.6" - wire $9\sv_changed$next[0:0]$14039 - attribute \src "libresoc.v:197083.19-197083.108" - wire width 65 $add$libresoc.v:197083$13545_Y - attribute \src "libresoc.v:197095.19-197095.112" - wire width 8 $add$libresoc.v:197095$13556_Y - attribute \src "libresoc.v:197096.19-197096.112" - wire width 8 $add$libresoc.v:197096$13557_Y - attribute \src "libresoc.v:197166.19-197166.116" - wire width 65 $add$libresoc.v:197166$13627_Y - attribute \src "libresoc.v:197200.18-197200.107" - wire width 65 $add$libresoc.v:197200$13660_Y - attribute \src "libresoc.v:197088.19-197088.104" - wire $and$libresoc.v:197088$13550_Y - attribute \src "libresoc.v:197091.19-197091.104" - wire $and$libresoc.v:197091$13553_Y - attribute \src "libresoc.v:197099.19-197099.104" - wire $and$libresoc.v:197099$13560_Y - attribute \src "libresoc.v:197102.19-197102.104" - wire $and$libresoc.v:197102$13563_Y - attribute \src "libresoc.v:197104.19-197104.111" - wire $and$libresoc.v:197104$13565_Y - attribute \src "libresoc.v:197107.19-197107.104" - wire $and$libresoc.v:197107$13568_Y - attribute \src "libresoc.v:197113.19-197113.104" - wire $and$libresoc.v:197113$13573_Y - attribute \src "libresoc.v:197116.19-197116.104" - wire $and$libresoc.v:197116$13576_Y - attribute \src "libresoc.v:197119.19-197119.104" - wire $and$libresoc.v:197119$13579_Y - attribute \src "libresoc.v:197122.19-197122.104" - wire $and$libresoc.v:197122$13582_Y - attribute \src "libresoc.v:197125.19-197125.104" - wire $and$libresoc.v:197125$13585_Y - attribute \src "libresoc.v:197128.19-197128.104" - wire $and$libresoc.v:197128$13588_Y - attribute \src "libresoc.v:197129.19-197129.115" - wire width 3 $and$libresoc.v:197129$13589_Y - attribute \src "libresoc.v:197133.19-197133.104" - wire $and$libresoc.v:197133$13593_Y - attribute \src "libresoc.v:197136.19-197136.104" - wire $and$libresoc.v:197136$13596_Y - attribute \src "libresoc.v:197142.19-197142.104" - wire $and$libresoc.v:197142$13601_Y - attribute \src "libresoc.v:197145.19-197145.104" - wire $and$libresoc.v:197145$13604_Y - attribute \src "libresoc.v:197146.19-197146.115" - wire width 3 $and$libresoc.v:197146$13605_Y - attribute \src "libresoc.v:197149.19-197149.111" - wire $and$libresoc.v:197149$13608_Y - attribute \src "libresoc.v:197154.19-197154.104" - wire $and$libresoc.v:197154$13613_Y - attribute \src "libresoc.v:197157.19-197157.104" - wire $and$libresoc.v:197157$13616_Y - attribute \src "libresoc.v:197172.18-197172.109" - wire $and$libresoc.v:197172$13633_Y - attribute \src "libresoc.v:197178.18-197178.101" - wire $and$libresoc.v:197178$13640_Y - attribute \src "libresoc.v:197180.18-197180.109" - wire $and$libresoc.v:197180$13642_Y - attribute \src "libresoc.v:197183.18-197183.101" - wire $and$libresoc.v:197183$13645_Y - attribute \src "libresoc.v:197189.18-197189.101" - wire $and$libresoc.v:197189$13650_Y - attribute \src "libresoc.v:197191.18-197191.109" - wire $and$libresoc.v:197191$13652_Y - attribute \src "libresoc.v:197194.18-197194.101" - wire $and$libresoc.v:197194$13655_Y - attribute \src "libresoc.v:197103.19-197103.108" - wire $eq$libresoc.v:197103$13564_Y - attribute \src "libresoc.v:197148.19-197148.108" - wire $eq$libresoc.v:197148$13607_Y - attribute \src "libresoc.v:197158.19-197158.116" - wire $eq$libresoc.v:197158$13617_Y - attribute \src "libresoc.v:197179.18-197179.107" - wire $eq$libresoc.v:197179$13641_Y - attribute \src "libresoc.v:197190.18-197190.107" - wire $eq$libresoc.v:197190$13651_Y - attribute \src "libresoc.v:197163.19-197163.114" - wire width 64 $extend$libresoc.v:197163$13622_Y - attribute \src "libresoc.v:197164.19-197164.113" - wire width 64 $extend$libresoc.v:197164$13624_Y - attribute \src "libresoc.v:197175.18-197175.109" - wire width 64 $extend$libresoc.v:197175$13636_Y - attribute \src "libresoc.v:197084.19-197084.106" - wire width 7 $mul$libresoc.v:197084$13546_Y - attribute \src "libresoc.v:197201.18-197201.110" - wire width 7 $mul$libresoc.v:197201$13661_Y - attribute \src "libresoc.v:197152.18-197152.102" - wire $ne$libresoc.v:197152$13611_Y - attribute \src "libresoc.v:197160.19-197160.123" - wire $ne$libresoc.v:197160$13619_Y - attribute \src "libresoc.v:197170.18-197170.102" - wire $ne$libresoc.v:197170$13631_Y - attribute \src "libresoc.v:197086.19-197086.107" - wire $not$libresoc.v:197086$13548_Y - attribute \src "libresoc.v:197087.19-197087.109" - wire $not$libresoc.v:197087$13549_Y - attribute \src "libresoc.v:197089.19-197089.107" - wire $not$libresoc.v:197089$13551_Y - attribute \src "libresoc.v:197090.19-197090.109" - wire $not$libresoc.v:197090$13552_Y - attribute \src "libresoc.v:197097.19-197097.107" - wire $not$libresoc.v:197097$13558_Y - attribute \src "libresoc.v:197098.19-197098.109" - wire $not$libresoc.v:197098$13559_Y - attribute \src "libresoc.v:197100.19-197100.107" - wire $not$libresoc.v:197100$13561_Y - attribute \src "libresoc.v:197101.19-197101.109" - wire $not$libresoc.v:197101$13562_Y - attribute \src "libresoc.v:197105.19-197105.107" - wire $not$libresoc.v:197105$13566_Y - attribute \src "libresoc.v:197106.19-197106.109" - wire $not$libresoc.v:197106$13567_Y - attribute \src "libresoc.v:197111.19-197111.107" - wire $not$libresoc.v:197111$13571_Y - attribute \src "libresoc.v:197112.19-197112.109" - wire $not$libresoc.v:197112$13572_Y - attribute \src "libresoc.v:197114.19-197114.107" - wire $not$libresoc.v:197114$13574_Y - attribute \src "libresoc.v:197115.19-197115.109" - wire $not$libresoc.v:197115$13575_Y - attribute \src "libresoc.v:197117.19-197117.107" - wire $not$libresoc.v:197117$13577_Y - attribute \src "libresoc.v:197118.19-197118.109" - wire $not$libresoc.v:197118$13578_Y - attribute \src "libresoc.v:197120.19-197120.107" - wire $not$libresoc.v:197120$13580_Y - attribute \src "libresoc.v:197121.19-197121.109" - wire $not$libresoc.v:197121$13581_Y - attribute \src "libresoc.v:197123.19-197123.107" - wire $not$libresoc.v:197123$13583_Y - attribute \src "libresoc.v:197124.19-197124.109" - wire $not$libresoc.v:197124$13584_Y - attribute \src "libresoc.v:197126.19-197126.107" - wire $not$libresoc.v:197126$13586_Y - attribute \src "libresoc.v:197127.19-197127.109" - wire $not$libresoc.v:197127$13587_Y - attribute \src "libresoc.v:197131.19-197131.107" - wire $not$libresoc.v:197131$13591_Y - attribute \src "libresoc.v:197132.19-197132.109" - wire $not$libresoc.v:197132$13592_Y - attribute \src "libresoc.v:197134.19-197134.107" - wire $not$libresoc.v:197134$13594_Y - attribute \src "libresoc.v:197135.19-197135.109" - wire $not$libresoc.v:197135$13595_Y - attribute \src "libresoc.v:197140.19-197140.107" - wire $not$libresoc.v:197140$13599_Y - attribute \src "libresoc.v:197141.19-197141.109" - wire $not$libresoc.v:197141$13600_Y - attribute \src "libresoc.v:197143.19-197143.107" - wire $not$libresoc.v:197143$13602_Y - attribute \src "libresoc.v:197144.19-197144.109" - wire $not$libresoc.v:197144$13603_Y - attribute \src "libresoc.v:197150.19-197150.107" - wire $not$libresoc.v:197150$13609_Y - attribute \src "libresoc.v:197151.19-197151.107" - wire $not$libresoc.v:197151$13610_Y - attribute \src "libresoc.v:197153.19-197153.109" - wire $not$libresoc.v:197153$13612_Y - attribute \src "libresoc.v:197155.19-197155.107" - wire $not$libresoc.v:197155$13614_Y - attribute \src "libresoc.v:197156.19-197156.109" - wire $not$libresoc.v:197156$13615_Y - attribute \src "libresoc.v:197161.19-197161.107" - wire $not$libresoc.v:197161$13620_Y - attribute \src "libresoc.v:197162.19-197162.107" - wire $not$libresoc.v:197162$13621_Y - attribute \src "libresoc.v:197171.18-197171.103" - wire $not$libresoc.v:197171$13632_Y - attribute \src "libresoc.v:197173.18-197173.97" - wire $not$libresoc.v:197173$13634_Y - attribute \src "libresoc.v:197174.18-197174.102" - wire $not$libresoc.v:197174$13635_Y - attribute \src "libresoc.v:197176.18-197176.106" - wire $not$libresoc.v:197176$13638_Y - attribute \src "libresoc.v:197177.18-197177.108" - wire $not$libresoc.v:197177$13639_Y - attribute \src "libresoc.v:197181.18-197181.106" - wire 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"libresoc.v:196408.19-196408.114" + wire width 64 $pos$libresoc.v:196408$13571_Y + attribute \src "libresoc.v:196409.19-196409.113" + wire width 64 $pos$libresoc.v:196409$13573_Y + attribute \src "libresoc.v:196420.18-196420.109" + wire width 64 $pos$libresoc.v:196420$13585_Y + attribute \src "libresoc.v:196375.19-196375.93" + wire $reduce_or$libresoc.v:196375$13538_Y + attribute \src "libresoc.v:196392.19-196392.93" + wire $reduce_or$libresoc.v:196392$13554_Y + attribute \src "libresoc.v:196330.18-196330.41" + wire width 64 $shr$libresoc.v:196330$13495_Y + attribute \src "libresoc.v:196447.18-196447.40" + wire width 64 $shr$libresoc.v:196447$13610_Y + attribute \src "libresoc.v:196410.19-196410.116" + wire width 65 $sub$libresoc.v:196410$13574_Y + attribute \src "libresoc.v:196412.18-196412.101" + wire width 3 $sub$libresoc.v:196412$13576_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" wire width 65 \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" @@ -407004,7 +402410,7 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" wire output 3 \busy_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 388 \clk + wire input 356 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \core_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" @@ -408528,35 +403934,35 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire output 20 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 372 \icp_wb__ack + wire output 340 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 378 \icp_wb__adr + wire width 28 input 346 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 373 \icp_wb__cyc + wire input 341 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 374 \icp_wb__dat_r + wire width 32 output 342 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 375 \icp_wb__dat_w + wire width 32 input 343 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 379 \icp_wb__sel + wire width 4 input 347 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 376 \icp_wb__stb + wire input 344 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 377 \icp_wb__we + wire input 345 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 385 \ics_wb__ack + wire output 353 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 380 \ics_wb__adr + wire width 28 input 348 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 382 \ics_wb__cyc + wire input 350 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 384 \ics_wb__dat_r + wire width 32 output 352 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 386 \ics_wb__dat_w + wire width 32 input 354 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 383 \ics_wb__stb + wire input 351 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 387 \ics_wb__we + wire input 355 \ics_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" wire width 48 \imem_a_pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" @@ -408569,12 +403975,12 @@ module \ti wire \imem_f_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire \imem_wb_icache_en - attribute \src "libresoc.v:194646.7-194646.15" + attribute \src "libresoc.v:193965.7-193965.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" wire \insn_done attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 381 \int_level_i + wire width 16 input 349 \int_level_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" wire \is_last attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" @@ -408615,8 +404021,6 @@ module \ti wire output 333 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire output 334 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" - wire \jtag_wb_sram_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 75 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -409077,78 +404481,6 @@ module \ti wire input 146 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 299 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" - wire \sram4k_0_enable - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 342 \sram4k_0_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 343 \sram4k_0_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 340 \sram4k_0_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 344 \sram4k_0_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 345 \sram4k_0_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 347 \sram4k_0_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 341 \sram4k_0_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 346 \sram4k_0_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" - wire \sram4k_1_enable - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 350 \sram4k_1_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 351 \sram4k_1_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 348 \sram4k_1_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 352 \sram4k_1_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 353 \sram4k_1_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 355 \sram4k_1_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 349 \sram4k_1_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 354 \sram4k_1_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" - wire \sram4k_2_enable - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 358 \sram4k_2_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 359 \sram4k_2_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 356 \sram4k_2_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 360 \sram4k_2_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 361 \sram4k_2_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 363 \sram4k_2_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 357 \sram4k_2_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 362 \sram4k_2_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:16" - wire \sram4k_3_enable - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire output 366 \sram4k_3_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 9 input 367 \sram4k_3_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 364 \sram4k_3_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 output 368 \sram4k_3_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 64 input 369 \sram4k_3_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire width 8 input 371 \sram4k_3_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 365 \sram4k_3_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" - wire input 370 \sram4k_3_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" wire \sv_changed attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" @@ -409178,7 +404510,7 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 \xics_ics_icp_o_src attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" - cell $add $add$libresoc.v:197083$13545 + cell $add $add$libresoc.v:196328$13493 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -409186,10 +404518,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:197083$13545_Y + connect \Y $add$libresoc.v:196328$13493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:507" - cell $add $add$libresoc.v:197095$13556 + cell $add $add$libresoc.v:196340$13504 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -409197,10 +404529,10 @@ module \ti parameter \Y_WIDTH 8 connect \A \cur_cur_srcstep connect \B 1'1 - connect \Y $add$libresoc.v:197095$13556_Y + connect \Y $add$libresoc.v:196340$13504_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508" - cell $add $add$libresoc.v:197096$13557 + cell $add $add$libresoc.v:196341$13505 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -409208,10 +404540,10 @@ module \ti parameter \Y_WIDTH 8 connect \A \cur_cur_dststep connect \B 1'1 - connect \Y $add$libresoc.v:197096$13557_Y + connect \Y $add$libresoc.v:196341$13505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017" - cell $add $add$libresoc.v:197166$13627 + cell $add $add$libresoc.v:196411$13575 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -409219,10 +404551,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $add$libresoc.v:197166$13627_Y + connect \Y $add$libresoc.v:196411$13575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:338" - cell $add $add$libresoc.v:197200$13660 + cell $add $add$libresoc.v:196445$13608 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -409230,10 +404562,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:197200$13660_Y + connect \Y $add$libresoc.v:196445$13608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197088$13550 + cell $and $and$libresoc.v:196333$13498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409241,10 +404573,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$106 connect \B \$108 - connect \Y $and$libresoc.v:197088$13550_Y + connect \Y $and$libresoc.v:196333$13498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197091$13553 + cell $and $and$libresoc.v:196336$13501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409252,10 +404584,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$112 connect \B \$114 - connect \Y $and$libresoc.v:197091$13553_Y + connect \Y $and$libresoc.v:196336$13501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197099$13560 + cell $and $and$libresoc.v:196344$13508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409263,10 +404595,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$130 connect \B \$132 - connect \Y $and$libresoc.v:197099$13560_Y + connect \Y $and$libresoc.v:196344$13508_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197102$13563 + cell $and $and$libresoc.v:196347$13511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409274,10 +404606,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$136 connect \B \$138 - connect \Y $and$libresoc.v:197102$13563_Y + connect \Y $and$libresoc.v:196347$13511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $and $and$libresoc.v:197104$13565 + cell $and $and$libresoc.v:196349$13513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409285,10 +404617,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$142 - connect \Y $and$libresoc.v:197104$13565_Y + connect \Y $and$libresoc.v:196349$13513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197107$13568 + cell $and $and$libresoc.v:196352$13516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409296,10 +404628,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$146 connect \B \$148 - connect \Y $and$libresoc.v:197107$13568_Y + connect \Y $and$libresoc.v:196352$13516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197113$13573 + cell $and $and$libresoc.v:196358$13521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409307,10 +404639,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$158 connect \B \$160 - connect \Y $and$libresoc.v:197113$13573_Y + connect \Y $and$libresoc.v:196358$13521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197116$13576 + cell $and $and$libresoc.v:196361$13524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409318,10 +404650,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$164 connect \B \$166 - connect \Y $and$libresoc.v:197116$13576_Y + connect \Y $and$libresoc.v:196361$13524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197119$13579 + cell $and $and$libresoc.v:196364$13527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409329,10 +404661,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$170 connect \B \$172 - connect \Y $and$libresoc.v:197119$13579_Y + connect \Y $and$libresoc.v:196364$13527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197122$13582 + cell $and $and$libresoc.v:196367$13530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409340,10 +404672,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$176 connect \B \$178 - connect \Y $and$libresoc.v:197122$13582_Y + connect \Y $and$libresoc.v:196367$13530_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197125$13585 + cell $and $and$libresoc.v:196370$13533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409351,10 +404683,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$182 connect \B \$184 - connect \Y $and$libresoc.v:197125$13585_Y + connect \Y $and$libresoc.v:196370$13533_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197128$13588 + cell $and $and$libresoc.v:196373$13536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409362,10 +404694,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$188 connect \B \$190 - connect \Y $and$libresoc.v:197128$13588_Y + connect \Y $and$libresoc.v:196373$13536_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" - cell $and $and$libresoc.v:197129$13589 + cell $and $and$libresoc.v:196374$13537 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -409373,10 +404705,10 @@ module \ti parameter \Y_WIDTH 3 connect \A \core_state_nia_wen connect \B 1'1 - connect \Y $and$libresoc.v:197129$13589_Y + connect \Y $and$libresoc.v:196374$13537_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197133$13593 + cell $and $and$libresoc.v:196378$13541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409384,10 +404716,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$198 connect \B \$200 - connect \Y $and$libresoc.v:197133$13593_Y + connect \Y $and$libresoc.v:196378$13541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197136$13596 + cell $and $and$libresoc.v:196381$13544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409395,10 +404727,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$204 connect \B \$206 - connect \Y $and$libresoc.v:197136$13596_Y + connect \Y $and$libresoc.v:196381$13544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197142$13601 + cell $and $and$libresoc.v:196387$13549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409406,10 +404738,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$216 connect \B \$218 - connect \Y $and$libresoc.v:197142$13601_Y + connect \Y $and$libresoc.v:196387$13549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197145$13604 + cell $and $and$libresoc.v:196390$13552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409417,10 +404749,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$222 connect \B \$224 - connect \Y $and$libresoc.v:197145$13604_Y + connect \Y $and$libresoc.v:196390$13552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:726" - cell $and $and$libresoc.v:197146$13605 + cell $and $and$libresoc.v:196391$13553 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -409428,10 +404760,10 @@ module \ti parameter \Y_WIDTH 3 connect \A \core_state_nia_wen connect \B 3'100 - connect \Y $and$libresoc.v:197146$13605_Y + connect \Y $and$libresoc.v:196391$13553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $and $and$libresoc.v:197149$13608 + cell $and $and$libresoc.v:196394$13556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409439,10 +404771,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$232 - connect \Y $and$libresoc.v:197149$13608_Y + connect \Y $and$libresoc.v:196394$13556_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197154$13613 + cell $and $and$libresoc.v:196399$13561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409450,10 +404782,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$238 connect \B \$240 - connect \Y $and$libresoc.v:197154$13613_Y + connect \Y $and$libresoc.v:196399$13561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197157$13616 + cell $and $and$libresoc.v:196402$13564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409461,10 +404793,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$244 connect \B \$246 - connect \Y $and$libresoc.v:197157$13616_Y + connect \Y $and$libresoc.v:196402$13564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:197172$13633 + cell $and $and$libresoc.v:196417$13581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409472,10 +404804,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \core_cu_st__rel_o connect \B \$34 - connect \Y $and$libresoc.v:197172$13633_Y + connect \Y $and$libresoc.v:196417$13581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197178$13640 + cell $and $and$libresoc.v:196423$13588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409483,10 +404815,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:197178$13640_Y + connect \Y $and$libresoc.v:196423$13588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $and $and$libresoc.v:197180$13642 + cell $and $and$libresoc.v:196425$13590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409494,10 +404826,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$50 - connect \Y $and$libresoc.v:197180$13642_Y + connect \Y $and$libresoc.v:196425$13590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197183$13645 + cell $and $and$libresoc.v:196428$13593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409505,10 +404837,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$54 connect \B \$56 - connect \Y $and$libresoc.v:197183$13645_Y + connect \Y $and$libresoc.v:196428$13593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:197189$13650 + cell $and $and$libresoc.v:196434$13598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409516,10 +404848,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$66 connect \B \$68 - connect \Y $and$libresoc.v:197189$13650_Y + connect \Y $and$libresoc.v:196434$13598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $and $and$libresoc.v:197191$13652 + cell $and $and$libresoc.v:196436$13600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409527,10 +404859,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$72 - connect \Y $and$libresoc.v:197191$13652_Y + connect \Y $and$libresoc.v:196436$13600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:197194$13655 + cell $and $and$libresoc.v:196439$13603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409538,10 +404870,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$76 connect \B \$78 - connect \Y $and$libresoc.v:197194$13655_Y + connect \Y $and$libresoc.v:196439$13603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $eq $eq$libresoc.v:197103$13564 + cell $eq $eq$libresoc.v:196348$13512 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -409549,10 +404881,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:197103$13564_Y + connect \Y $eq$libresoc.v:196348$13512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $eq $eq$libresoc.v:197148$13607 + cell $eq $eq$libresoc.v:196393$13555 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -409560,10 +404892,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:197148$13607_Y + connect \Y $eq$libresoc.v:196393$13555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" - cell $eq $eq$libresoc.v:197158$13617 + cell $eq $eq$libresoc.v:196403$13565 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -409571,10 +404903,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \next_srcstep connect \B \cur_cur_vl - connect \Y $eq$libresoc.v:197158$13617_Y + connect \Y $eq$libresoc.v:196403$13565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $eq $eq$libresoc.v:197179$13641 + cell $eq $eq$libresoc.v:196424$13589 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -409582,10 +404914,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:197179$13641_Y + connect \Y $eq$libresoc.v:196424$13589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $eq $eq$libresoc.v:197190$13651 + cell $eq $eq$libresoc.v:196435$13599 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -409593,34 +404925,34 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:197190$13651_Y + connect \Y $eq$libresoc.v:196435$13599_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $extend$libresoc.v:197163$13622 + cell $pos $extend$libresoc.v:196408$13570 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \core_full_rd2__data_o - connect \Y $extend$libresoc.v:197163$13622_Y + connect \Y $extend$libresoc.v:196408$13570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $extend$libresoc.v:197164$13624 + cell $pos $extend$libresoc.v:196409$13572 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \core_full_rd__data_o - connect \Y $extend$libresoc.v:197164$13624_Y + connect \Y $extend$libresoc.v:196409$13572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:197175$13636 + cell $pos $extend$libresoc.v:196420$13584 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \svstate_i - connect \Y $extend$libresoc.v:197175$13636_Y + connect \Y $extend$libresoc.v:196420$13584_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:197084$13546 + cell $mul $mul$libresoc.v:196329$13494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409628,10 +404960,10 @@ module \ti parameter \Y_WIDTH 7 connect \A \$100 [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:197084$13546_Y + connect \Y $mul$libresoc.v:196329$13494_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:197201$13661 + cell $mul $mul$libresoc.v:196446$13609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -409639,10 +404971,10 @@ module \ti parameter \Y_WIDTH 7 connect \A \dec2_cur_pc [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:197201$13661_Y + connect \Y $mul$libresoc.v:196446$13609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" - cell $ne $ne$libresoc.v:197152$13611 + cell $ne $ne$libresoc.v:196397$13559 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -409650,10 +404982,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \delay connect \B 1'0 - connect \Y $ne$libresoc.v:197152$13611_Y + connect \Y $ne$libresoc.v:196397$13559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" - cell $ne $ne$libresoc.v:197160$13619 + cell $ne $ne$libresoc.v:196405$13567 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -409661,10 +404993,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \core_core_core_insn_type connect \B 7'0000001 - connect \Y $ne$libresoc.v:197160$13619_Y + connect \Y $ne$libresoc.v:196405$13567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" - cell $ne $ne$libresoc.v:197170$13631 + cell $ne $ne$libresoc.v:196415$13579 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -409672,410 +405004,410 @@ module \ti parameter \Y_WIDTH 1 connect \A \delay connect \B \$30 - connect \Y $ne$libresoc.v:197170$13631_Y + connect \Y $ne$libresoc.v:196415$13579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197086$13548 + cell $not $not$libresoc.v:196331$13496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197086$13548_Y + connect \Y $not$libresoc.v:196331$13496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197087$13549 + cell $not $not$libresoc.v:196332$13497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197087$13549_Y + connect \Y $not$libresoc.v:196332$13497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197089$13551 + cell $not $not$libresoc.v:196334$13499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197089$13551_Y + connect \Y $not$libresoc.v:196334$13499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197090$13552 + cell $not $not$libresoc.v:196335$13500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197090$13552_Y + connect \Y $not$libresoc.v:196335$13500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197097$13558 + cell $not $not$libresoc.v:196342$13506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197097$13558_Y + connect \Y $not$libresoc.v:196342$13506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197098$13559 + cell $not $not$libresoc.v:196343$13507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197098$13559_Y + connect \Y $not$libresoc.v:196343$13507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197100$13561 + cell $not $not$libresoc.v:196345$13509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197100$13561_Y + connect \Y $not$libresoc.v:196345$13509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197101$13562 + cell $not $not$libresoc.v:196346$13510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197101$13562_Y + connect \Y $not$libresoc.v:196346$13510_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197105$13566 + cell $not $not$libresoc.v:196350$13514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197105$13566_Y + connect \Y $not$libresoc.v:196350$13514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197106$13567 + cell $not $not$libresoc.v:196351$13515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197106$13567_Y + connect \Y $not$libresoc.v:196351$13515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197111$13571 + cell $not $not$libresoc.v:196356$13519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197111$13571_Y + connect \Y $not$libresoc.v:196356$13519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197112$13572 + cell $not $not$libresoc.v:196357$13520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197112$13572_Y + connect \Y $not$libresoc.v:196357$13520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197114$13574 + cell $not $not$libresoc.v:196359$13522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197114$13574_Y + connect \Y $not$libresoc.v:196359$13522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197115$13575 + cell $not $not$libresoc.v:196360$13523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197115$13575_Y + connect \Y $not$libresoc.v:196360$13523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197117$13577 + cell $not $not$libresoc.v:196362$13525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197117$13577_Y + connect \Y $not$libresoc.v:196362$13525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197118$13578 + cell $not $not$libresoc.v:196363$13526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197118$13578_Y + connect \Y $not$libresoc.v:196363$13526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197120$13580 + cell $not $not$libresoc.v:196365$13528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197120$13580_Y + connect \Y $not$libresoc.v:196365$13528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197121$13581 + cell $not $not$libresoc.v:196366$13529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197121$13581_Y + connect \Y $not$libresoc.v:196366$13529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197123$13583 + cell $not $not$libresoc.v:196368$13531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197123$13583_Y + connect \Y $not$libresoc.v:196368$13531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197124$13584 + cell $not $not$libresoc.v:196369$13532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197124$13584_Y + connect \Y $not$libresoc.v:196369$13532_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197126$13586 + cell $not $not$libresoc.v:196371$13534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197126$13586_Y + connect \Y $not$libresoc.v:196371$13534_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197127$13587 + cell $not $not$libresoc.v:196372$13535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197127$13587_Y + connect \Y $not$libresoc.v:196372$13535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197131$13591 + cell $not $not$libresoc.v:196376$13539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197131$13591_Y + connect \Y $not$libresoc.v:196376$13539_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197132$13592 + cell $not $not$libresoc.v:196377$13540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197132$13592_Y + connect \Y $not$libresoc.v:196377$13540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197134$13594 + cell $not $not$libresoc.v:196379$13542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197134$13594_Y + connect \Y $not$libresoc.v:196379$13542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197135$13595 + cell $not $not$libresoc.v:196380$13543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197135$13595_Y + connect \Y $not$libresoc.v:196380$13543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197140$13599 + cell $not $not$libresoc.v:196385$13547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197140$13599_Y + connect \Y $not$libresoc.v:196385$13547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197141$13600 + cell $not $not$libresoc.v:196386$13548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197141$13600_Y + connect \Y $not$libresoc.v:196386$13548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197143$13602 + cell $not $not$libresoc.v:196388$13550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197143$13602_Y + connect \Y $not$libresoc.v:196388$13550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197144$13603 + cell $not $not$libresoc.v:196389$13551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197144$13603_Y + connect \Y $not$libresoc.v:196389$13551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" - cell $not $not$libresoc.v:197150$13609 + cell $not $not$libresoc.v:196395$13557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:197150$13609_Y + connect \Y $not$libresoc.v:196395$13557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197151$13610 + cell $not $not$libresoc.v:196396$13558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197151$13610_Y + connect \Y $not$libresoc.v:196396$13558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197153$13612 + cell $not $not$libresoc.v:196398$13560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197153$13612_Y + connect \Y $not$libresoc.v:196398$13560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197155$13614 + cell $not $not$libresoc.v:196400$13562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197155$13614_Y + connect \Y $not$libresoc.v:196400$13562_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197156$13615 + cell $not $not$libresoc.v:196401$13563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197156$13615_Y + connect \Y $not$libresoc.v:196401$13563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" - cell $not $not$libresoc.v:197161$13620 + cell $not $not$libresoc.v:196406$13568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:197161$13620_Y + connect \Y $not$libresoc.v:196406$13568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" - cell $not $not$libresoc.v:197162$13621 + cell $not $not$libresoc.v:196407$13569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:197162$13621_Y + connect \Y $not$libresoc.v:196407$13569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:197171$13632 + cell $not $not$libresoc.v:196416$13580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o_dly - connect \Y $not$libresoc.v:197171$13632_Y + connect \Y $not$libresoc.v:196416$13580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" - cell $not $not$libresoc.v:197173$13634 + cell $not $not$libresoc.v:196418$13582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_i_ok - connect \Y $not$libresoc.v:197173$13634_Y + connect \Y $not$libresoc.v:196418$13582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" - cell $not $not$libresoc.v:197174$13635 + cell $not $not$libresoc.v:196419$13583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \svstate_i_ok - connect \Y $not$libresoc.v:197174$13635_Y + connect \Y $not$libresoc.v:196419$13583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197176$13638 + cell $not $not$libresoc.v:196421$13586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197176$13638_Y + connect \Y $not$libresoc.v:196421$13586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197177$13639 + cell $not $not$libresoc.v:196422$13587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197177$13639_Y + connect \Y $not$libresoc.v:196422$13587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197181$13643 + cell $not $not$libresoc.v:196426$13591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197181$13643_Y + connect \Y $not$libresoc.v:196426$13591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197182$13644 + cell $not $not$libresoc.v:196427$13592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197182$13644_Y + connect \Y $not$libresoc.v:196427$13592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197187$13648 + cell $not $not$libresoc.v:196432$13596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197187$13648_Y + connect \Y $not$libresoc.v:196432$13596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:197188$13649 + cell $not $not$libresoc.v:196433$13597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197188$13649_Y + connect \Y $not$libresoc.v:196433$13597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197192$13653 + cell $not $not$libresoc.v:196437$13601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:197192$13653_Y + connect \Y $not$libresoc.v:196437$13601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:197193$13654 + cell $not $not$libresoc.v:196438$13602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:197193$13654_Y + connect \Y $not$libresoc.v:196438$13602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" - cell $not $not$libresoc.v:197198$13658 + cell $not $not$libresoc.v:196443$13606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msr_read - connect \Y $not$libresoc.v:197198$13658_Y + connect \Y $not$libresoc.v:196443$13606_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" - cell $not $not$libresoc.v:197199$13659 + cell $not $not$libresoc.v:196444$13607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msr_read - connect \Y $not$libresoc.v:197199$13659_Y + connect \Y $not$libresoc.v:196444$13607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" - cell $or $or$libresoc.v:197092$13554 + cell $or $or$libresoc.v:196337$13502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410083,10 +405415,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:197092$13554_Y + connect \Y $or$libresoc.v:196337$13502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" - cell $or $or$libresoc.v:197094$13555 + cell $or $or$libresoc.v:196339$13503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410094,10 +405426,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$120 connect \B \is_last - connect \Y $or$libresoc.v:197094$13555_Y + connect \Y $or$libresoc.v:196339$13503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" - cell $or $or$libresoc.v:197108$13569 + cell $or $or$libresoc.v:196353$13517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410105,10 +405437,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:197108$13569_Y + connect \Y $or$libresoc.v:196353$13517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" - cell $or $or$libresoc.v:197110$13570 + cell $or $or$libresoc.v:196355$13518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410116,10 +405448,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$154 connect \B \is_last - connect \Y $or$libresoc.v:197110$13570_Y + connect \Y $or$libresoc.v:196355$13518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" - cell $or $or$libresoc.v:197137$13597 + cell $or $or$libresoc.v:196382$13545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410127,10 +405459,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:197137$13597_Y + connect \Y $or$libresoc.v:196382$13545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" - cell $or $or$libresoc.v:197139$13598 + cell $or $or$libresoc.v:196384$13546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410138,10 +405470,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$212 connect \B \is_last - connect \Y $or$libresoc.v:197139$13598_Y + connect \Y $or$libresoc.v:196384$13546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" - cell $or $or$libresoc.v:197168$13629 + cell $or $or$libresoc.v:196413$13577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410149,10 +405481,10 @@ module \ti parameter \Y_WIDTH 1 connect \A 1'0 connect \B \dbg_core_rst_o - connect \Y $or$libresoc.v:197168$13629_Y + connect \Y $or$libresoc.v:196413$13577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" - cell $or $or$libresoc.v:197169$13630 + cell $or $or$libresoc.v:196414$13578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410160,10 +405492,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$28 connect \B \rst - connect \Y $or$libresoc.v:197169$13630_Y + connect \Y $or$libresoc.v:196414$13578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" - cell $or $or$libresoc.v:197184$13646 + cell $or $or$libresoc.v:196429$13594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410171,10 +405503,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:197184$13646_Y + connect \Y $or$libresoc.v:196429$13594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" - cell $or $or$libresoc.v:197186$13647 + cell $or $or$libresoc.v:196431$13595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410182,10 +405514,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$62 connect \B \is_last - connect \Y $or$libresoc.v:197186$13647_Y + connect \Y $or$libresoc.v:196431$13595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" - cell $or $or$libresoc.v:197195$13656 + cell $or $or$libresoc.v:196440$13604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410193,10 +405525,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:197195$13656_Y + connect \Y $or$libresoc.v:196440$13604_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" - cell $or $or$libresoc.v:197197$13657 + cell $or $or$libresoc.v:196442$13605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -410204,58 +405536,58 @@ module \ti parameter \Y_WIDTH 1 connect \A \$84 connect \B \is_last - connect \Y $or$libresoc.v:197197$13657_Y + connect \Y $or$libresoc.v:196442$13605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:197159$13618 + cell $pos $pos$libresoc.v:196404$13566 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } - connect \Y $pos$libresoc.v:197159$13618_Y + connect \Y $pos$libresoc.v:196404$13566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:197163$13623 + cell $pos $pos$libresoc.v:196408$13571 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:197163$13622_Y - connect \Y $pos$libresoc.v:197163$13623_Y + connect \A $extend$libresoc.v:196408$13570_Y + connect \Y $pos$libresoc.v:196408$13571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:197164$13625 + cell $pos $pos$libresoc.v:196409$13573 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:197164$13624_Y - connect \Y $pos$libresoc.v:197164$13625_Y + connect \A $extend$libresoc.v:196409$13572_Y + connect \Y $pos$libresoc.v:196409$13573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:197175$13637 + cell $pos $pos$libresoc.v:196420$13585 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:197175$13636_Y - connect \Y $pos$libresoc.v:197175$13637_Y + connect \A $extend$libresoc.v:196420$13584_Y + connect \Y $pos$libresoc.v:196420$13585_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:197130$13590 + cell $reduce_or $reduce_or$libresoc.v:196375$13538 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$195 - connect \Y $reduce_or$libresoc.v:197130$13590_Y + connect \Y $reduce_or$libresoc.v:196375$13538_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:197147$13606 + cell $reduce_or $reduce_or$libresoc.v:196392$13554 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$229 - connect \Y $reduce_or$libresoc.v:197147$13606_Y + connect \Y $reduce_or$libresoc.v:196392$13554_Y end - attribute \src "libresoc.v:197085.18-197085.41" - cell $shr $shr$libresoc.v:197085$13547 + attribute \src "libresoc.v:196330.18-196330.41" + cell $shr $shr$libresoc.v:196330$13495 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -410263,10 +405595,10 @@ module \ti parameter \Y_WIDTH 64 connect \A \imem_f_instr_o connect \B \$103 - connect \Y $shr$libresoc.v:197085$13547_Y + connect \Y $shr$libresoc.v:196330$13495_Y end - attribute \src "libresoc.v:197202.18-197202.40" - cell $shr $shr$libresoc.v:197202$13662 + attribute \src "libresoc.v:196447.18-196447.40" + cell $shr $shr$libresoc.v:196447$13610 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -410274,10 +405606,10 @@ module \ti parameter \Y_WIDTH 64 connect \A \imem_f_instr_o connect \B \$96 - connect \Y $shr$libresoc.v:197202$13662_Y + connect \Y $shr$libresoc.v:196447$13610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1001" - cell $sub $sub$libresoc.v:197165$13626 + cell $sub $sub$libresoc.v:196410$13574 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -410285,10 +405617,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $sub$libresoc.v:197165$13626_Y + connect \Y $sub$libresoc.v:196410$13574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" - cell $sub $sub$libresoc.v:197167$13628 + cell $sub $sub$libresoc.v:196412$13576 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -410296,10 +405628,10 @@ module \ti parameter \Y_WIDTH 3 connect \A \delay connect \B 1'1 - connect \Y $sub$libresoc.v:197167$13628_Y + connect \Y $sub$libresoc.v:196412$13576_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:197411.8-197509.4" + attribute \src "libresoc.v:196656.8-196754.4" cell \core \core connect \bigendian_i \core_bigendian_i$10 connect \cia__data_o \core_cia__data_o @@ -410400,7 +405732,7 @@ module \ti connect \wen$10 \core_wen$11 end attribute \module_not_derived 1 - attribute \src "libresoc.v:197510.7-197541.4" + attribute \src "libresoc.v:196755.7-196786.4" cell \dbg \dbg connect \clk \clk connect \core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_dststep @@ -410434,7 +405766,7 @@ module \ti connect \terminate_i \dbg_terminate_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:197542.8-197609.4" + attribute \src "libresoc.v:196787.8-196854.4" cell \dec2 \dec2 connect \asmcode \dec2_asmcode connect \bigendian \dec2_bigendian @@ -410504,7 +405836,7 @@ module \ti connect \xer_out \dec2_xer_out end attribute \module_not_derived 1 - attribute \src "libresoc.v:197610.8-197626.4" + attribute \src "libresoc.v:196855.8-196871.4" cell \imem \imem connect \a_pc_i \imem_a_pc_i connect \a_valid_i \imem_a_valid_i @@ -410523,7 +405855,7 @@ module \ti connect \wb_icache_en \imem_wb_icache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:197627.8-197955.4" + attribute \src "libresoc.v:196872.8-197199.4" cell \jtag \jtag connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -410851,70 +406183,9 @@ module \ti connect \sdr_we_n__pad__o \sdr_we_n__pad__o connect \wb_dcache_en \core_wb_dcache_en connect \wb_icache_en \imem_wb_icache_en - connect \wb_sram_en \jtag_wb_sram_en - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:197956.12-197968.4" - cell \sram4k_0 \sram4k_0 - connect \clk \clk - connect \enable \sram4k_0_enable - connect \rst \rst - connect \sram4k_0_wb__ack \sram4k_0_wb__ack - connect \sram4k_0_wb__adr \sram4k_0_wb__adr - connect \sram4k_0_wb__cyc \sram4k_0_wb__cyc - connect \sram4k_0_wb__dat_r \sram4k_0_wb__dat_r - connect \sram4k_0_wb__dat_w \sram4k_0_wb__dat_w - connect \sram4k_0_wb__sel \sram4k_0_wb__sel - connect \sram4k_0_wb__stb \sram4k_0_wb__stb - connect \sram4k_0_wb__we \sram4k_0_wb__we - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:197969.12-197981.4" - cell \sram4k_1 \sram4k_1 - connect \clk \clk - connect \enable \sram4k_1_enable - connect \rst \rst - connect \sram4k_1_wb__ack \sram4k_1_wb__ack - connect \sram4k_1_wb__adr \sram4k_1_wb__adr - connect \sram4k_1_wb__cyc \sram4k_1_wb__cyc - connect \sram4k_1_wb__dat_r \sram4k_1_wb__dat_r - connect \sram4k_1_wb__dat_w \sram4k_1_wb__dat_w - connect \sram4k_1_wb__sel \sram4k_1_wb__sel - connect \sram4k_1_wb__stb \sram4k_1_wb__stb - connect \sram4k_1_wb__we \sram4k_1_wb__we - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:197982.12-197994.4" - cell \sram4k_2 \sram4k_2 - connect \clk \clk - connect \enable \sram4k_2_enable - connect \rst \rst - connect \sram4k_2_wb__ack \sram4k_2_wb__ack - connect \sram4k_2_wb__adr \sram4k_2_wb__adr - connect \sram4k_2_wb__cyc \sram4k_2_wb__cyc - connect \sram4k_2_wb__dat_r \sram4k_2_wb__dat_r - connect \sram4k_2_wb__dat_w \sram4k_2_wb__dat_w - connect \sram4k_2_wb__sel \sram4k_2_wb__sel - connect \sram4k_2_wb__stb \sram4k_2_wb__stb - connect \sram4k_2_wb__we \sram4k_2_wb__we end attribute \module_not_derived 1 - attribute \src "libresoc.v:197995.12-198007.4" - cell \sram4k_3 \sram4k_3 - connect \clk \clk - connect \enable \sram4k_3_enable - connect \rst \rst - connect \sram4k_3_wb__ack \sram4k_3_wb__ack - connect \sram4k_3_wb__adr \sram4k_3_wb__adr - connect \sram4k_3_wb__cyc \sram4k_3_wb__cyc - connect \sram4k_3_wb__dat_r \sram4k_3_wb__dat_r - connect \sram4k_3_wb__dat_w \sram4k_3_wb__dat_w - connect \sram4k_3_wb__sel \sram4k_3_wb__sel - connect \sram4k_3_wb__stb \sram4k_3_wb__stb - connect \sram4k_3_wb__we \sram4k_3_wb__we - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:198008.12-198022.4" + attribute \src "libresoc.v:197200.12-197214.4" cell \xics_icp \xics_icp connect \clk \clk connect \core_irq_o \xics_icp_core_irq_o @@ -410931,7 +406202,7 @@ module \ti connect \rst \rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:198023.12-198036.4" + attribute \src "libresoc.v:197215.12-197228.4" cell \xics_ics \xics_ics connect \clk \clk connect \icp_o_pri \xics_ics_icp_o_pri @@ -410946,1582 +406217,1582 @@ module \ti connect \int_level_i \int_level_i connect \rst \rst end - attribute \src "libresoc.v:194646.7-194646.20" - process $proc$libresoc.v:194646$14246 + attribute \src "libresoc.v:193965.7-193965.20" + process $proc$libresoc.v:193965$14194 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:194914.13-194914.33" - process $proc$libresoc.v:194914$14247 + attribute \src "libresoc.v:194233.13-194233.33" + process $proc$libresoc.v:194233$14195 assign { } { } assign $1\core_asmcode[7:0] 8'00000000 sync always sync init update \core_asmcode $1\core_asmcode[7:0] end - attribute \src "libresoc.v:194920.7-194920.35" - process $proc$libresoc.v:194920$14248 + attribute \src "libresoc.v:194239.7-194239.35" + process $proc$libresoc.v:194239$14196 assign { } { } - assign $0\core_bigendian_i$10[0:0]$14249 1'0 + assign $0\core_bigendian_i$10[0:0]$14197 1'0 sync always sync init - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14249 + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14197 end - attribute \src "libresoc.v:194928.14-194928.55" - process $proc$libresoc.v:194928$14250 + attribute \src "libresoc.v:194247.14-194247.55" + process $proc$libresoc.v:194247$14198 assign { } { } assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_cia $1\core_core_core_cia[63:0] end - attribute \src "libresoc.v:194932.13-194932.41" - process $proc$libresoc.v:194932$14251 + attribute \src "libresoc.v:194251.13-194251.41" + process $proc$libresoc.v:194251$14199 assign { } { } assign $1\core_core_core_cr_rd[7:0] 8'00000000 sync always sync init update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:194936.7-194936.37" - process $proc$libresoc.v:194936$14252 + attribute \src "libresoc.v:194255.7-194255.37" + process $proc$libresoc.v:194255$14200 assign { } { } assign $1\core_core_core_cr_rd_ok[0:0] 1'0 sync always sync init update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:194940.13-194940.41" - process $proc$libresoc.v:194940$14253 + attribute \src "libresoc.v:194259.13-194259.41" + process $proc$libresoc.v:194259$14201 assign { } { } assign $1\core_core_core_cr_wr[7:0] 8'00000000 sync always sync init update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:194944.7-194944.42" - process $proc$libresoc.v:194944$14254 + attribute \src "libresoc.v:194263.7-194263.42" + process $proc$libresoc.v:194263$14202 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$14255 1'0 + assign $0\core_core_core_exc_$signal[0:0]$14203 1'0 sync always sync init - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14255 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14203 end - attribute \src "libresoc.v:194946.7-194946.44" - process $proc$libresoc.v:194946$14256 + attribute \src "libresoc.v:194265.7-194265.44" + process $proc$libresoc.v:194265$14204 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$14257 1'0 + assign $0\core_core_core_exc_$signal$3[0:0]$14205 1'0 sync always sync init - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14257 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14205 end - attribute \src "libresoc.v:194950.7-194950.44" - process $proc$libresoc.v:194950$14258 + attribute \src "libresoc.v:194269.7-194269.44" + process $proc$libresoc.v:194269$14206 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$14259 1'0 + assign $0\core_core_core_exc_$signal$4[0:0]$14207 1'0 sync always sync init - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14259 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14207 end - attribute \src "libresoc.v:194954.7-194954.44" - process $proc$libresoc.v:194954$14260 + attribute \src "libresoc.v:194273.7-194273.44" + process $proc$libresoc.v:194273$14208 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$14261 1'0 + assign $0\core_core_core_exc_$signal$5[0:0]$14209 1'0 sync always sync init - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14261 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14209 end - attribute \src "libresoc.v:194958.7-194958.44" - process $proc$libresoc.v:194958$14262 + attribute \src "libresoc.v:194277.7-194277.44" + process $proc$libresoc.v:194277$14210 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$14263 1'0 + assign $0\core_core_core_exc_$signal$6[0:0]$14211 1'0 sync always sync init - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14263 + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14211 end - attribute \src "libresoc.v:194962.7-194962.44" - process $proc$libresoc.v:194962$14264 + attribute \src "libresoc.v:194281.7-194281.44" + process $proc$libresoc.v:194281$14212 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$14265 1'0 + assign $0\core_core_core_exc_$signal$7[0:0]$14213 1'0 sync always sync init - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14265 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14213 end - attribute \src "libresoc.v:194966.7-194966.44" - process $proc$libresoc.v:194966$14266 + attribute \src "libresoc.v:194285.7-194285.44" + process $proc$libresoc.v:194285$14214 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$14267 1'0 + assign $0\core_core_core_exc_$signal$8[0:0]$14215 1'0 sync always sync init - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14267 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14215 end - attribute \src "libresoc.v:194970.7-194970.44" - process $proc$libresoc.v:194970$14268 + attribute \src "libresoc.v:194289.7-194289.44" + process $proc$libresoc.v:194289$14216 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$14269 1'0 + assign $0\core_core_core_exc_$signal$9[0:0]$14217 1'0 sync always sync init - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14269 + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14217 end - attribute \src "libresoc.v:194991.14-194991.47" - process $proc$libresoc.v:194991$14270 + attribute \src "libresoc.v:194310.14-194310.47" + process $proc$libresoc.v:194310$14218 assign { } { } assign $1\core_core_core_fn_unit[13:0] 14'00000000000000 sync always sync init update \core_core_core_fn_unit $1\core_core_core_fn_unit[13:0] end - attribute \src "libresoc.v:194999.13-194999.46" - process $proc$libresoc.v:194999$14271 + attribute \src "libresoc.v:194318.13-194318.46" + process $proc$libresoc.v:194318$14219 assign { } { } assign $1\core_core_core_input_carry[1:0] 2'00 sync always sync init update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:195003.14-195003.41" - process $proc$libresoc.v:195003$14272 + attribute \src "libresoc.v:194322.14-194322.41" + process $proc$libresoc.v:194322$14220 assign { } { } assign $1\core_core_core_insn[31:0] 0 sync always sync init update \core_core_core_insn $1\core_core_core_insn[31:0] end - attribute \src "libresoc.v:195082.13-195082.45" - process $proc$libresoc.v:195082$14273 + attribute \src "libresoc.v:194401.13-194401.45" + process $proc$libresoc.v:194401$14221 assign { } { } assign $1\core_core_core_insn_type[6:0] 7'0000000 sync always sync init update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:195086.7-195086.37" - process $proc$libresoc.v:195086$14274 + attribute \src "libresoc.v:194405.7-194405.37" + process $proc$libresoc.v:194405$14222 assign { } { } assign $1\core_core_core_is_32bit[0:0] 1'0 sync always sync init update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:195090.14-195090.55" - process $proc$libresoc.v:195090$14275 + attribute \src "libresoc.v:194409.14-194409.55" + process $proc$libresoc.v:194409$14223 assign { } { } assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_msr $1\core_core_core_msr[63:0] end - attribute \src "libresoc.v:195094.7-195094.31" - process $proc$libresoc.v:195094$14276 + attribute \src "libresoc.v:194413.7-194413.31" + process $proc$libresoc.v:194413$14224 assign { } { } assign $1\core_core_core_oe[0:0] 1'0 sync always sync init update \core_core_core_oe $1\core_core_core_oe[0:0] end - attribute \src "libresoc.v:195098.7-195098.34" - process $proc$libresoc.v:195098$14277 + attribute \src "libresoc.v:194417.7-194417.34" + process $proc$libresoc.v:194417$14225 assign { } { } assign $1\core_core_core_oe_ok[0:0] 1'0 sync always sync init update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:195102.7-195102.31" - process $proc$libresoc.v:195102$14278 + attribute \src "libresoc.v:194421.7-194421.31" + process $proc$libresoc.v:194421$14226 assign { } { } assign $1\core_core_core_rc[0:0] 1'0 sync always sync init update \core_core_core_rc $1\core_core_core_rc[0:0] end - attribute \src "libresoc.v:195106.7-195106.34" - process $proc$libresoc.v:195106$14279 + attribute \src "libresoc.v:194425.7-194425.34" + process $proc$libresoc.v:194425$14227 assign { } { } assign $1\core_core_core_rc_ok[0:0] 1'0 sync always sync init update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:195110.14-195110.48" - process $proc$libresoc.v:195110$14280 + attribute \src "libresoc.v:194429.14-194429.48" + process $proc$libresoc.v:194429$14228 assign { } { } assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 sync always sync init update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:195114.13-195114.44" - process $proc$libresoc.v:195114$14281 + attribute \src "libresoc.v:194433.13-194433.44" + process $proc$libresoc.v:194433$14229 assign { } { } assign $1\core_core_core_traptype[7:0] 8'00000000 sync always sync init update \core_core_core_traptype $1\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:195118.13-195118.37" - process $proc$libresoc.v:195118$14282 + attribute \src "libresoc.v:194437.13-194437.37" + process $proc$libresoc.v:194437$14230 assign { } { } assign $1\core_core_cr_in1[6:0] 7'0000000 sync always sync init update \core_core_cr_in1 $1\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:195122.7-195122.33" - process $proc$libresoc.v:195122$14283 + attribute \src "libresoc.v:194441.7-194441.33" + process $proc$libresoc.v:194441$14231 assign { } { } assign $1\core_core_cr_in1_ok[0:0] 1'0 sync always sync init update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:195126.13-195126.37" - process $proc$libresoc.v:195126$14284 + attribute \src "libresoc.v:194445.13-194445.37" + process $proc$libresoc.v:194445$14232 assign { } { } assign $1\core_core_cr_in2[6:0] 7'0000000 sync always sync init update \core_core_cr_in2 $1\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:195128.13-195128.41" - process $proc$libresoc.v:195128$14285 + attribute \src "libresoc.v:194447.13-194447.41" + process $proc$libresoc.v:194447$14233 assign { } { } - assign $0\core_core_cr_in2$1[6:0]$14286 7'0000000 + assign $0\core_core_cr_in2$1[6:0]$14234 7'0000000 sync always sync init - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14286 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14234 end - attribute \src "libresoc.v:195134.7-195134.33" - process $proc$libresoc.v:195134$14287 + attribute \src "libresoc.v:194453.7-194453.33" + process $proc$libresoc.v:194453$14235 assign { } { } assign $1\core_core_cr_in2_ok[0:0] 1'0 sync always sync init update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:195136.7-195136.37" - process $proc$libresoc.v:195136$14288 + attribute \src "libresoc.v:194455.7-194455.37" + process $proc$libresoc.v:194455$14236 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$14289 1'0 + assign $0\core_core_cr_in2_ok$2[0:0]$14237 1'0 sync always sync init - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14289 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14237 end - attribute \src "libresoc.v:195142.13-195142.37" - process $proc$libresoc.v:195142$14290 + attribute \src "libresoc.v:194461.13-194461.37" + process $proc$libresoc.v:194461$14238 assign { } { } assign $1\core_core_cr_out[6:0] 7'0000000 sync always sync init update \core_core_cr_out $1\core_core_cr_out[6:0] end - attribute \src "libresoc.v:195146.7-195146.32" - process $proc$libresoc.v:195146$14291 + attribute \src "libresoc.v:194465.7-194465.32" + process $proc$libresoc.v:194465$14239 assign { } { } assign $1\core_core_cr_wr_ok[0:0] 1'0 sync always sync init update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:195150.13-195150.38" - process $proc$libresoc.v:195150$14292 + attribute \src "libresoc.v:194469.13-194469.38" + process $proc$libresoc.v:194469$14240 assign { } { } assign $1\core_core_dststep[6:0] 7'0000000 sync always sync init update \core_core_dststep $1\core_core_dststep[6:0] end - attribute \src "libresoc.v:195154.13-195154.33" - process $proc$libresoc.v:195154$14293 + attribute \src "libresoc.v:194473.13-194473.33" + process $proc$libresoc.v:194473$14241 assign { } { } assign $1\core_core_ea[6:0] 7'0000000 sync always sync init update \core_core_ea $1\core_core_ea[6:0] end - attribute \src "libresoc.v:195158.13-195158.35" - process $proc$libresoc.v:195158$14294 + attribute \src "libresoc.v:194477.13-194477.35" + process $proc$libresoc.v:194477$14242 assign { } { } assign $1\core_core_fast1[2:0] 3'000 sync always sync init update \core_core_fast1 $1\core_core_fast1[2:0] end - attribute \src "libresoc.v:195162.7-195162.32" - process $proc$libresoc.v:195162$14295 + attribute \src "libresoc.v:194481.7-194481.32" + process $proc$libresoc.v:194481$14243 assign { } { } assign $1\core_core_fast1_ok[0:0] 1'0 sync always sync init update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:195166.13-195166.35" - process $proc$libresoc.v:195166$14296 + attribute \src "libresoc.v:194485.13-194485.35" + process $proc$libresoc.v:194485$14244 assign { } { } assign $1\core_core_fast2[2:0] 3'000 sync always sync init update \core_core_fast2 $1\core_core_fast2[2:0] end - attribute \src "libresoc.v:195170.7-195170.32" - process $proc$libresoc.v:195170$14297 + attribute \src "libresoc.v:194489.7-194489.32" + process $proc$libresoc.v:194489$14245 assign { } { } assign $1\core_core_fast2_ok[0:0] 1'0 sync always sync init update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:195174.13-195174.36" - process $proc$libresoc.v:195174$14298 + attribute \src "libresoc.v:194493.13-194493.36" + process $proc$libresoc.v:194493$14246 assign { } { } assign $1\core_core_fasto1[2:0] 3'000 sync always sync init update \core_core_fasto1 $1\core_core_fasto1[2:0] end - attribute \src "libresoc.v:195178.13-195178.36" - process $proc$libresoc.v:195178$14299 + attribute \src "libresoc.v:194497.13-194497.36" + process $proc$libresoc.v:194497$14247 assign { } { } assign $1\core_core_fasto2[2:0] 3'000 sync always sync init update \core_core_fasto2 $1\core_core_fasto2[2:0] end - attribute \src "libresoc.v:195182.7-195182.26" - process $proc$libresoc.v:195182$14300 + attribute \src "libresoc.v:194501.7-194501.26" + process $proc$libresoc.v:194501$14248 assign { } { } assign $1\core_core_lk[0:0] 1'0 sync always sync init update \core_core_lk $1\core_core_lk[0:0] end - attribute \src "libresoc.v:195186.13-195186.36" - process $proc$libresoc.v:195186$14301 + attribute \src "libresoc.v:194505.13-194505.36" + process $proc$libresoc.v:194505$14249 assign { } { } assign $1\core_core_maxvl[6:0] 7'0000000 sync always sync init update \core_core_maxvl $1\core_core_maxvl[6:0] end - attribute \src "libresoc.v:195190.14-195190.49" - process $proc$libresoc.v:195190$14302 + attribute \src "libresoc.v:194509.14-194509.49" + process $proc$libresoc.v:194509$14250 assign { } { } assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_pc $1\core_core_pc[63:0] end - attribute \src "libresoc.v:195194.13-195194.35" - process $proc$libresoc.v:195194$14303 + attribute \src "libresoc.v:194513.13-194513.35" + process $proc$libresoc.v:194513$14251 assign { } { } assign $1\core_core_reg1[6:0] 7'0000000 sync always sync init update \core_core_reg1 $1\core_core_reg1[6:0] end - attribute \src "libresoc.v:195198.7-195198.31" - process $proc$libresoc.v:195198$14304 + attribute \src "libresoc.v:194517.7-194517.31" + process $proc$libresoc.v:194517$14252 assign { } { } assign $1\core_core_reg1_ok[0:0] 1'0 sync always sync init update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:195202.13-195202.35" - process $proc$libresoc.v:195202$14305 + attribute \src "libresoc.v:194521.13-194521.35" + process $proc$libresoc.v:194521$14253 assign { } { } assign $1\core_core_reg2[6:0] 7'0000000 sync always sync init update \core_core_reg2 $1\core_core_reg2[6:0] end - attribute \src "libresoc.v:195206.7-195206.31" - process $proc$libresoc.v:195206$14306 + attribute \src "libresoc.v:194525.7-194525.31" + process $proc$libresoc.v:194525$14254 assign { } { } assign $1\core_core_reg2_ok[0:0] 1'0 sync always sync init update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:195210.13-195210.35" - process $proc$libresoc.v:195210$14307 + attribute \src "libresoc.v:194529.13-194529.35" + process $proc$libresoc.v:194529$14255 assign { } { } assign $1\core_core_reg3[6:0] 7'0000000 sync always sync init update \core_core_reg3 $1\core_core_reg3[6:0] end - attribute \src "libresoc.v:195214.7-195214.31" - process $proc$libresoc.v:195214$14308 + attribute \src "libresoc.v:194533.7-194533.31" + process $proc$libresoc.v:194533$14256 assign { } { } assign $1\core_core_reg3_ok[0:0] 1'0 sync always sync init update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:195218.13-195218.35" - process $proc$libresoc.v:195218$14309 + attribute \src "libresoc.v:194537.13-194537.35" + process $proc$libresoc.v:194537$14257 assign { } { } assign $1\core_core_rego[6:0] 7'0000000 sync always sync init update \core_core_rego $1\core_core_rego[6:0] end - attribute \src "libresoc.v:195336.13-195336.37" - process $proc$libresoc.v:195336$14310 + attribute \src "libresoc.v:194655.13-194655.37" + process $proc$libresoc.v:194655$14258 assign { } { } assign $1\core_core_spr1[9:0] 10'0000000000 sync always sync init update \core_core_spr1 $1\core_core_spr1[9:0] end - attribute \src "libresoc.v:195340.7-195340.31" - process $proc$libresoc.v:195340$14311 + attribute \src "libresoc.v:194659.7-194659.31" + process $proc$libresoc.v:194659$14259 assign { } { } assign $1\core_core_spr1_ok[0:0] 1'0 sync always sync init update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:195458.13-195458.37" - process $proc$libresoc.v:195458$14312 + attribute \src "libresoc.v:194777.13-194777.37" + process $proc$libresoc.v:194777$14260 assign { } { } assign $1\core_core_spro[9:0] 10'0000000000 sync always sync init update \core_core_spro $1\core_core_spro[9:0] end - attribute \src "libresoc.v:195462.13-195462.38" - process $proc$libresoc.v:195462$14313 + attribute \src "libresoc.v:194781.13-194781.38" + process $proc$libresoc.v:194781$14261 assign { } { } assign $1\core_core_srcstep[6:0] 7'0000000 sync always sync init update \core_core_srcstep $1\core_core_srcstep[6:0] end - attribute \src "libresoc.v:195466.13-195466.35" - process $proc$libresoc.v:195466$14314 + attribute \src "libresoc.v:194785.13-194785.35" + process $proc$libresoc.v:194785$14262 assign { } { } assign $1\core_core_subvl[1:0] 2'00 sync always sync init update \core_core_subvl $1\core_core_subvl[1:0] end - attribute \src "libresoc.v:195470.13-195470.36" - process $proc$libresoc.v:195470$14315 + attribute \src "libresoc.v:194789.13-194789.36" + process $proc$libresoc.v:194789$14263 assign { } { } assign $1\core_core_svstep[1:0] 2'00 sync always sync init update \core_core_svstep $1\core_core_svstep[1:0] end - attribute \src "libresoc.v:195476.13-195476.33" - process $proc$libresoc.v:195476$14316 + attribute \src "libresoc.v:194795.13-194795.33" + process $proc$libresoc.v:194795$14264 assign { } { } assign $1\core_core_vl[6:0] 7'0000000 sync always sync init update \core_core_vl $1\core_core_vl[6:0] end - attribute \src "libresoc.v:195480.13-195480.36" - process $proc$libresoc.v:195480$14317 + attribute \src "libresoc.v:194799.13-194799.36" + process $proc$libresoc.v:194799$14265 assign { } { } assign $1\core_core_xer_in[2:0] 3'000 sync always sync init update \core_core_xer_in $1\core_core_xer_in[2:0] end - attribute \src "libresoc.v:195488.7-195488.28" - process $proc$libresoc.v:195488$14318 + attribute \src "libresoc.v:194807.7-194807.28" + process $proc$libresoc.v:194807$14266 assign { } { } assign $1\core_cr_out_ok[0:0] 1'0 sync always sync init update \core_cr_out_ok $1\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:195504.14-195504.45" - process $proc$libresoc.v:195504$14319 + attribute \src "libresoc.v:194823.14-194823.45" + process $proc$libresoc.v:194823$14267 assign { } { } assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_dec $1\core_dec[63:0] end - attribute \src "libresoc.v:195514.7-195514.24" - process $proc$libresoc.v:195514$14320 + attribute \src "libresoc.v:194833.7-194833.24" + process $proc$libresoc.v:194833$14268 assign { } { } assign $1\core_ea_ok[0:0] 1'0 sync always sync init update \core_ea_ok $1\core_ea_ok[0:0] end - attribute \src "libresoc.v:195518.7-195518.23" - process $proc$libresoc.v:195518$14321 + attribute \src "libresoc.v:194837.7-194837.23" + process $proc$libresoc.v:194837$14269 assign { } { } assign $1\core_eint[0:0] 1'0 sync always sync init update \core_eint $1\core_eint[0:0] end - attribute \src "libresoc.v:195522.7-195522.28" - process $proc$libresoc.v:195522$14322 + attribute \src "libresoc.v:194841.7-194841.28" + process $proc$libresoc.v:194841$14270 assign { } { } assign $1\core_fasto1_ok[0:0] 1'0 sync always sync init update \core_fasto1_ok $1\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:195526.7-195526.28" - process $proc$libresoc.v:195526$14323 + attribute \src "libresoc.v:194845.7-194845.28" + process $proc$libresoc.v:194845$14271 assign { } { } assign $1\core_fasto2_ok[0:0] 1'0 sync always sync init update \core_fasto2_ok $1\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:195554.14-195554.45" - process $proc$libresoc.v:195554$14324 + attribute \src "libresoc.v:194873.14-194873.45" + process $proc$libresoc.v:194873$14272 assign { } { } assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_msr $1\core_msr[63:0] end - attribute \src "libresoc.v:195562.14-195562.37" - process $proc$libresoc.v:195562$14325 + attribute \src "libresoc.v:194881.14-194881.37" + process $proc$libresoc.v:194881$14273 assign { } { } assign $1\core_raw_insn_i[31:0] 0 sync always sync init update \core_raw_insn_i $1\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:195566.7-195566.26" - process $proc$libresoc.v:195566$14326 + attribute \src "libresoc.v:194885.7-194885.26" + process $proc$libresoc.v:194885$14274 assign { } { } assign $1\core_rego_ok[0:0] 1'0 sync always sync init update \core_rego_ok $1\core_rego_ok[0:0] end - attribute \src "libresoc.v:195570.7-195570.26" - process $proc$libresoc.v:195570$14327 + attribute \src "libresoc.v:194889.7-194889.26" + process $proc$libresoc.v:194889$14275 assign { } { } assign $1\core_spro_ok[0:0] 1'0 sync always sync init update \core_spro_ok $1\core_spro_ok[0:0] end - attribute \src "libresoc.v:195582.7-195582.26" - process $proc$libresoc.v:195582$14328 + attribute \src "libresoc.v:194901.7-194901.26" + process $proc$libresoc.v:194901$14276 assign { } { } assign $1\core_sv_a_nz[0:0] 1'0 sync always sync init update \core_sv_a_nz $1\core_sv_a_nz[0:0] end - attribute \src "libresoc.v:195592.7-195592.26" - process $proc$libresoc.v:195592$14329 + attribute \src "libresoc.v:194911.7-194911.26" + process $proc$libresoc.v:194911$14277 assign { } { } assign $1\core_xer_out[0:0] 1'0 sync always sync init update \core_xer_out $1\core_xer_out[0:0] end - attribute \src "libresoc.v:195598.7-195598.30" - process $proc$libresoc.v:195598$14330 + attribute \src "libresoc.v:194917.7-194917.30" + process $proc$libresoc.v:194917$14278 assign { } { } assign $1\cu_st__rel_o_dly[0:0] 1'0 sync always sync init update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:195604.13-195604.36" - process $proc$libresoc.v:195604$14331 + attribute \src "libresoc.v:194923.13-194923.36" + process $proc$libresoc.v:194923$14279 assign { } { } assign $1\cur_cur_dststep[6:0] 7'0000000 sync always sync init update \cur_cur_dststep $1\cur_cur_dststep[6:0] end - attribute \src "libresoc.v:195608.13-195608.34" - process $proc$libresoc.v:195608$14332 + attribute \src "libresoc.v:194927.13-194927.34" + process $proc$libresoc.v:194927$14280 assign { } { } assign $1\cur_cur_maxvl[6:0] 7'0000000 sync always sync init update \cur_cur_maxvl $1\cur_cur_maxvl[6:0] end - attribute \src "libresoc.v:195612.13-195612.36" - process $proc$libresoc.v:195612$14333 + attribute \src "libresoc.v:194931.13-194931.36" + process $proc$libresoc.v:194931$14281 assign { } { } assign $1\cur_cur_srcstep[6:0] 7'0000000 sync always sync init update \cur_cur_srcstep $1\cur_cur_srcstep[6:0] end - attribute \src "libresoc.v:195616.13-195616.33" - process $proc$libresoc.v:195616$14334 + attribute \src "libresoc.v:194935.13-194935.33" + process $proc$libresoc.v:194935$14282 assign { } { } assign $1\cur_cur_subvl[1:0] 2'00 sync always sync init update \cur_cur_subvl $1\cur_cur_subvl[1:0] end - attribute \src "libresoc.v:195620.13-195620.34" - process $proc$libresoc.v:195620$14335 + attribute \src "libresoc.v:194939.13-194939.34" + process $proc$libresoc.v:194939$14283 assign { } { } assign $1\cur_cur_svstep[1:0] 2'00 sync always sync init update \cur_cur_svstep $1\cur_cur_svstep[1:0] end - attribute \src "libresoc.v:195624.13-195624.31" - process $proc$libresoc.v:195624$14336 + attribute \src "libresoc.v:194943.13-194943.31" + process $proc$libresoc.v:194943$14284 assign { } { } assign $1\cur_cur_vl[6:0] 7'0000000 sync always sync init update \cur_cur_vl $1\cur_cur_vl[6:0] end - attribute \src "libresoc.v:195628.7-195628.24" - process $proc$libresoc.v:195628$14337 + attribute \src "libresoc.v:194947.7-194947.24" + process $proc$libresoc.v:194947$14285 assign { } { } assign $1\d_cr_delay[0:0] 1'0 sync always sync init update \d_cr_delay $1\d_cr_delay[0:0] end - attribute \src "libresoc.v:195632.7-195632.25" - process $proc$libresoc.v:195632$14338 + attribute \src "libresoc.v:194951.7-194951.25" + process $proc$libresoc.v:194951$14286 assign { } { } assign $1\d_reg_delay[0:0] 1'0 sync always sync init update \d_reg_delay $1\d_reg_delay[0:0] end - attribute \src "libresoc.v:195636.7-195636.25" - process $proc$libresoc.v:195636$14339 + attribute \src "libresoc.v:194955.7-194955.25" + process $proc$libresoc.v:194955$14287 assign { } { } assign $1\d_xer_delay[0:0] 1'0 sync always sync init update \d_xer_delay $1\d_xer_delay[0:0] end - attribute \src "libresoc.v:195684.13-195684.34" - process $proc$libresoc.v:195684$14340 + attribute \src "libresoc.v:195003.13-195003.34" + process $proc$libresoc.v:195003$14288 assign { } { } assign $1\dbg_dmi_addr_i[3:0] 4'0000 sync always sync init update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:195688.14-195688.48" - process $proc$libresoc.v:195688$14341 + attribute \src "libresoc.v:195007.14-195007.48" + process $proc$libresoc.v:195007$14289 assign { } { } assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbg_dmi_din $1\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:195694.7-195694.27" - process $proc$libresoc.v:195694$14342 + attribute \src "libresoc.v:195013.7-195013.27" + process $proc$libresoc.v:195013$14290 assign { } { } assign $1\dbg_dmi_req_i[0:0] 1'0 sync always sync init update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:195698.7-195698.26" - process $proc$libresoc.v:195698$14343 + attribute \src "libresoc.v:195017.7-195017.26" + process $proc$libresoc.v:195017$14291 assign { } { } assign $1\dbg_dmi_we_i[0:0] 1'0 sync always sync init update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:195752.14-195752.49" - process $proc$libresoc.v:195752$14344 + attribute \src "libresoc.v:195071.14-195071.49" + process $proc$libresoc.v:195071$14292 assign { } { } assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_dec $1\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:195756.7-195756.27" - process $proc$libresoc.v:195756$14345 + attribute \src "libresoc.v:195075.7-195075.27" + process $proc$libresoc.v:195075$14293 assign { } { } assign $1\dec2_cur_eint[0:0] 1'0 sync always sync init update \dec2_cur_eint $1\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:195760.14-195760.49" - process $proc$libresoc.v:195760$14346 + attribute \src "libresoc.v:195079.14-195079.49" + process $proc$libresoc.v:195079$14294 assign { } { } assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_msr $1\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:195764.14-195764.48" - process $proc$libresoc.v:195764$14347 + attribute \src "libresoc.v:195083.14-195083.48" + process $proc$libresoc.v:195083$14295 assign { } { } assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_pc $1\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:195916.14-195916.40" - process $proc$libresoc.v:195916$14348 + attribute \src "libresoc.v:195235.14-195235.40" + process $proc$libresoc.v:195235$14296 assign { } { } assign $1\dec2_raw_opcode_in[31:0] 0 sync always sync init update \dec2_raw_opcode_in $1\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:196186.13-196186.25" - process $proc$libresoc.v:196186$14349 + attribute \src "libresoc.v:195505.13-195505.25" + process $proc$libresoc.v:195505$14297 assign { } { } assign $1\delay[1:0] 2'11 sync always sync init update \delay $1\delay[1:0] end - attribute \src "libresoc.v:196202.7-196202.28" - process $proc$libresoc.v:196202$14350 + attribute \src "libresoc.v:195521.7-195521.28" + process $proc$libresoc.v:195521$14298 assign { } { } assign $1\exec_fsm_state[0:0] 1'0 sync always sync init update \exec_fsm_state $1\exec_fsm_state[0:0] end - attribute \src "libresoc.v:196214.13-196214.35" - process $proc$libresoc.v:196214$14351 + attribute \src "libresoc.v:195533.13-195533.35" + process $proc$libresoc.v:195533$14299 assign { } { } assign $1\fetch_fsm_state[1:0] 2'00 sync always sync init update \fetch_fsm_state $1\fetch_fsm_state[1:0] end - attribute \src "libresoc.v:196226.13-196226.29" - process $proc$libresoc.v:196226$14352 + attribute \src "libresoc.v:195545.13-195545.29" + process $proc$libresoc.v:195545$14300 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:196486.13-196486.35" - process $proc$libresoc.v:196486$14353 + attribute \src "libresoc.v:195805.13-195805.35" + process $proc$libresoc.v:195805$14301 assign { } { } assign $1\issue_fsm_state[2:0] 3'000 sync always sync init update \issue_fsm_state $1\issue_fsm_state[2:0] end - attribute \src "libresoc.v:196490.7-196490.30" - process $proc$libresoc.v:196490$14354 + attribute \src "libresoc.v:195809.7-195809.30" + process $proc$libresoc.v:195809$14302 assign { } { } assign $1\jtag_dmi0__ack_o[0:0] 1'0 sync always sync init update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:196498.14-196498.52" - process $proc$libresoc.v:196498$14355 + attribute \src "libresoc.v:195817.14-195817.52" + process $proc$libresoc.v:195817$14303 assign { } { } assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:196556.7-196556.22" - process $proc$libresoc.v:196556$14356 + attribute \src "libresoc.v:195873.7-195873.22" + process $proc$libresoc.v:195873$14304 assign { } { } assign $1\msr_read[0:0] 1'1 sync always sync init update \msr_read $1\msr_read[0:0] end - attribute \src "libresoc.v:196596.14-196596.40" - process $proc$libresoc.v:196596$14357 + attribute \src "libresoc.v:195913.14-195913.40" + process $proc$libresoc.v:195913$14305 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:196602.7-196602.24" - process $proc$libresoc.v:196602$14358 + attribute \src "libresoc.v:195919.7-195919.24" + process $proc$libresoc.v:195919$14306 assign { } { } assign $1\pc_changed[0:0] 1'0 sync always sync init update \pc_changed $1\pc_changed[0:0] end - attribute \src "libresoc.v:196612.7-196612.25" - process $proc$libresoc.v:196612$14359 + attribute \src "libresoc.v:195929.7-195929.25" + process $proc$libresoc.v:195929$14307 assign { } { } assign $1\pc_ok_delay[0:0] 1'0 sync always sync init update \pc_ok_delay $1\pc_ok_delay[0:0] end - attribute \src "libresoc.v:197056.7-197056.24" - process $proc$libresoc.v:197056$14360 + attribute \src "libresoc.v:196301.7-196301.24" + process $proc$libresoc.v:196301$14308 assign { } { } assign $1\sv_changed[0:0] 1'0 sync always sync init update \sv_changed $1\sv_changed[0:0] end - attribute \src "libresoc.v:197066.7-197066.30" - process $proc$libresoc.v:197066$14361 + attribute \src "libresoc.v:196311.7-196311.30" + process $proc$libresoc.v:196311$14309 assign { } { } assign $1\svstate_ok_delay[0:0] 1'0 sync always sync init update \svstate_ok_delay $1\svstate_ok_delay[0:0] end - attribute \src "libresoc.v:197203.3-197204.41" - process $proc$libresoc.v:197203$13663 + attribute \src "libresoc.v:196448.3-196449.41" + process $proc$libresoc.v:196448$13611 assign { } { } assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next sync posedge \clk update \dec2_cur_dec $0\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:197205.3-197206.41" - process $proc$libresoc.v:197205$13664 + attribute \src "libresoc.v:196450.3-196451.41" + process $proc$libresoc.v:196450$13612 assign { } { } assign $0\core_core_pc[63:0] \core_core_pc$next sync posedge \clk update \core_core_pc $0\core_core_pc[63:0] end - attribute \src "libresoc.v:197207.3-197208.49" - process $proc$libresoc.v:197207$13665 + attribute \src "libresoc.v:196452.3-196453.49" + process $proc$libresoc.v:196452$13613 assign { } { } assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next sync posedge \clk update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:197209.3-197210.39" - process $proc$libresoc.v:197209$13666 + attribute \src "libresoc.v:196454.3-196455.39" + process $proc$libresoc.v:196454$13614 assign { } { } assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next sync posedge \clk update \dbg_dmi_din $0\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:197211.3-197212.41" - process $proc$libresoc.v:197211$13667 + attribute \src "libresoc.v:196456.3-196457.41" + process $proc$libresoc.v:196456$13615 assign { } { } assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next sync posedge \clk update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:197213.3-197214.43" - process $proc$libresoc.v:197213$13668 + attribute \src "libresoc.v:196458.3-196459.43" + process $proc$libresoc.v:196458$13616 assign { } { } assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next sync posedge \clk update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:197215.3-197216.45" - process $proc$libresoc.v:197215$13669 + attribute \src "libresoc.v:196460.3-196461.45" + process $proc$libresoc.v:196460$13617 assign { } { } assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next sync posedge \clk update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:197217.3-197218.33" - process $proc$libresoc.v:197217$13670 + attribute \src "libresoc.v:196462.3-196463.33" + process $proc$libresoc.v:196462$13618 assign { } { } assign $0\core_msr[63:0] \core_msr$next sync posedge \clk update \core_msr $0\core_msr[63:0] end - attribute \src "libresoc.v:197219.3-197220.35" - process $proc$libresoc.v:197219$13671 + attribute \src "libresoc.v:196464.3-196465.35" + process $proc$libresoc.v:196464$13619 assign { } { } assign $0\core_eint[0:0] \core_eint$next sync posedge \clk update \core_eint $0\core_eint[0:0] end - attribute \src "libresoc.v:197221.3-197222.33" - process $proc$libresoc.v:197221$13672 + attribute \src "libresoc.v:196466.3-196467.33" + process $proc$libresoc.v:196466$13620 assign { } { } assign $0\core_dec[63:0] \core_dec$next sync posedge \clk update \core_dec $0\core_dec[63:0] end - attribute \src "libresoc.v:197223.3-197224.49" - process $proc$libresoc.v:197223$13673 + attribute \src "libresoc.v:196468.3-196469.49" + process $proc$libresoc.v:196468$13621 assign { } { } assign $0\core_core_svstep[1:0] \core_core_svstep$next sync posedge \clk update \core_core_svstep $0\core_core_svstep[1:0] end - attribute \src "libresoc.v:197225.3-197226.47" - process $proc$libresoc.v:197225$13674 + attribute \src "libresoc.v:196470.3-196471.47" + process $proc$libresoc.v:196470$13622 assign { } { } assign $0\core_core_subvl[1:0] \core_core_subvl$next sync posedge \clk update \core_core_subvl $0\core_core_subvl[1:0] end - attribute \src "libresoc.v:197227.3-197228.51" - process $proc$libresoc.v:197227$13675 + attribute \src "libresoc.v:196472.3-196473.51" + process $proc$libresoc.v:196472$13623 assign { } { } assign $0\core_core_dststep[6:0] \core_core_dststep$next sync posedge \clk update \core_core_dststep $0\core_core_dststep[6:0] end - attribute \src "libresoc.v:197229.3-197230.51" - process $proc$libresoc.v:197229$13676 + attribute \src "libresoc.v:196474.3-196475.51" + process $proc$libresoc.v:196474$13624 assign { } { } assign $0\core_core_srcstep[6:0] \core_core_srcstep$next sync posedge \clk update \core_core_srcstep $0\core_core_srcstep[6:0] end - attribute \src "libresoc.v:197231.3-197232.41" - process $proc$libresoc.v:197231$13677 + attribute \src "libresoc.v:196476.3-196477.41" + process $proc$libresoc.v:196476$13625 assign { } { } assign $0\core_core_vl[6:0] \core_core_vl$next sync posedge \clk update \core_core_vl $0\core_core_vl[6:0] end - attribute \src "libresoc.v:197233.3-197234.47" - process $proc$libresoc.v:197233$13678 + attribute \src "libresoc.v:196478.3-196479.47" + process $proc$libresoc.v:196478$13626 assign { } { } assign $0\core_core_maxvl[6:0] \core_core_maxvl$next sync posedge \clk update \core_core_maxvl $0\core_core_maxvl[6:0] end - attribute \src "libresoc.v:197235.3-197236.35" - process $proc$libresoc.v:197235$13679 + attribute \src "libresoc.v:196480.3-196481.35" + process $proc$libresoc.v:196480$13627 assign { } { } assign $0\fsm_state[1:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:197237.3-197238.41" - process $proc$libresoc.v:197237$13680 + attribute \src "libresoc.v:196482.3-196483.41" + process $proc$libresoc.v:196482$13628 assign { } { } assign $0\core_asmcode[7:0] \core_asmcode$next sync posedge \clk update \core_asmcode $0\core_asmcode[7:0] end - attribute \src "libresoc.v:197239.3-197240.45" - process $proc$libresoc.v:197239$13681 + attribute \src "libresoc.v:196484.3-196485.45" + process $proc$libresoc.v:196484$13629 assign { } { } assign $0\core_core_rego[6:0] \core_core_rego$next sync posedge \clk update \core_core_rego $0\core_core_rego[6:0] end - attribute \src "libresoc.v:197241.3-197242.41" - process $proc$libresoc.v:197241$13682 + attribute \src "libresoc.v:196486.3-196487.41" + process $proc$libresoc.v:196486$13630 assign { } { } assign $0\core_rego_ok[0:0] \core_rego_ok$next sync posedge \clk update \core_rego_ok $0\core_rego_ok[0:0] end - attribute \src "libresoc.v:197243.3-197244.41" - process $proc$libresoc.v:197243$13683 + attribute \src "libresoc.v:196488.3-196489.41" + process $proc$libresoc.v:196488$13631 assign { } { } assign $0\core_core_ea[6:0] \core_core_ea$next sync posedge \clk update \core_core_ea $0\core_core_ea[6:0] end - attribute \src "libresoc.v:197245.3-197246.37" - process $proc$libresoc.v:197245$13684 + attribute \src "libresoc.v:196490.3-196491.37" + process $proc$libresoc.v:196490$13632 assign { } { } assign $0\core_ea_ok[0:0] \core_ea_ok$next sync posedge \clk update \core_ea_ok $0\core_ea_ok[0:0] end - attribute \src "libresoc.v:197247.3-197248.45" - process $proc$libresoc.v:197247$13685 + attribute \src "libresoc.v:196492.3-196493.45" + process $proc$libresoc.v:196492$13633 assign { } { } assign $0\core_core_reg1[6:0] \core_core_reg1$next sync posedge \clk update \core_core_reg1 $0\core_core_reg1[6:0] end - attribute \src "libresoc.v:197249.3-197250.51" - process $proc$libresoc.v:197249$13686 + attribute \src "libresoc.v:196494.3-196495.51" + process $proc$libresoc.v:196494$13634 assign { } { } assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next sync posedge \clk update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:197251.3-197252.45" - process $proc$libresoc.v:197251$13687 + attribute \src "libresoc.v:196496.3-196497.45" + process $proc$libresoc.v:196496$13635 assign { } { } assign $0\core_core_reg2[6:0] \core_core_reg2$next sync posedge \clk update \core_core_reg2 $0\core_core_reg2[6:0] end - attribute \src "libresoc.v:197253.3-197254.51" - process $proc$libresoc.v:197253$13688 + attribute \src "libresoc.v:196498.3-196499.51" + process $proc$libresoc.v:196498$13636 assign { } { } assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next sync posedge \clk update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:197255.3-197256.45" - process $proc$libresoc.v:197255$13689 + attribute \src "libresoc.v:196500.3-196501.45" + process $proc$libresoc.v:196500$13637 assign { } { } assign $0\core_core_reg3[6:0] \core_core_reg3$next sync posedge \clk update \core_core_reg3 $0\core_core_reg3[6:0] end - attribute \src "libresoc.v:197257.3-197258.39" - process $proc$libresoc.v:197257$13690 + attribute \src "libresoc.v:196502.3-196503.39" + process $proc$libresoc.v:196502$13638 assign { } { } assign $0\d_xer_delay[0:0] \d_xer_delay$next sync posedge \clk update \d_xer_delay $0\d_xer_delay[0:0] end - attribute \src "libresoc.v:197259.3-197260.51" - process $proc$libresoc.v:197259$13691 + attribute \src "libresoc.v:196504.3-196505.51" + process $proc$libresoc.v:196504$13639 assign { } { } assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next sync posedge \clk update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:197261.3-197262.45" - process $proc$libresoc.v:197261$13692 + attribute \src "libresoc.v:196506.3-196507.45" + process $proc$libresoc.v:196506$13640 assign { } { } assign $0\core_core_spro[9:0] \core_core_spro$next sync posedge \clk update \core_core_spro $0\core_core_spro[9:0] end - attribute \src "libresoc.v:197263.3-197264.41" - process $proc$libresoc.v:197263$13693 + attribute \src "libresoc.v:196508.3-196509.41" + process $proc$libresoc.v:196508$13641 assign { } { } assign $0\core_spro_ok[0:0] \core_spro_ok$next sync posedge \clk update \core_spro_ok $0\core_spro_ok[0:0] end - attribute \src "libresoc.v:197265.3-197266.45" - process $proc$libresoc.v:197265$13694 + attribute \src "libresoc.v:196510.3-196511.45" + process $proc$libresoc.v:196510$13642 assign { } { } assign $0\core_core_spr1[9:0] \core_core_spr1$next sync posedge \clk update \core_core_spr1 $0\core_core_spr1[9:0] end - attribute \src "libresoc.v:197267.3-197268.51" - process $proc$libresoc.v:197267$13695 + attribute \src "libresoc.v:196512.3-196513.51" + process $proc$libresoc.v:196512$13643 assign { } { } assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next sync posedge \clk update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:197269.3-197270.49" - process $proc$libresoc.v:197269$13696 + attribute \src "libresoc.v:196514.3-196515.49" + process $proc$libresoc.v:196514$13644 assign { } { } assign $0\core_core_xer_in[2:0] \core_core_xer_in$next sync posedge \clk update \core_core_xer_in $0\core_core_xer_in[2:0] end - attribute \src "libresoc.v:197271.3-197272.41" - process $proc$libresoc.v:197271$13697 + attribute \src "libresoc.v:196516.3-196517.41" + process $proc$libresoc.v:196516$13645 assign { } { } assign $0\core_xer_out[0:0] \core_xer_out$next sync posedge \clk update \core_xer_out $0\core_xer_out[0:0] end - attribute \src "libresoc.v:197273.3-197274.47" - process $proc$libresoc.v:197273$13698 + attribute \src "libresoc.v:196518.3-196519.47" + process $proc$libresoc.v:196518$13646 assign { } { } assign $0\core_core_fast1[2:0] \core_core_fast1$next sync posedge \clk update \core_core_fast1 $0\core_core_fast1[2:0] end - attribute \src "libresoc.v:197275.3-197276.53" - process $proc$libresoc.v:197275$13699 + attribute \src "libresoc.v:196520.3-196521.53" + process $proc$libresoc.v:196520$13647 assign { } { } assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next sync posedge \clk update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:197277.3-197278.47" - process $proc$libresoc.v:197277$13700 + attribute \src "libresoc.v:196522.3-196523.47" + process $proc$libresoc.v:196522$13648 assign { } { } assign $0\core_core_fast2[2:0] \core_core_fast2$next sync posedge \clk update \core_core_fast2 $0\core_core_fast2[2:0] end - attribute \src "libresoc.v:197279.3-197280.37" - process $proc$libresoc.v:197279$13701 + attribute \src "libresoc.v:196524.3-196525.37" + process $proc$libresoc.v:196524$13649 assign { } { } assign $0\d_cr_delay[0:0] \d_cr_delay$next sync posedge \clk update \d_cr_delay $0\d_cr_delay[0:0] end - attribute \src "libresoc.v:197281.3-197282.53" - process $proc$libresoc.v:197281$13702 + attribute \src "libresoc.v:196526.3-196527.53" + process $proc$libresoc.v:196526$13650 assign { } { } assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next sync posedge \clk update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:197283.3-197284.49" - process $proc$libresoc.v:197283$13703 + attribute \src "libresoc.v:196528.3-196529.49" + process $proc$libresoc.v:196528$13651 assign { } { } assign $0\core_core_fasto1[2:0] \core_core_fasto1$next sync posedge \clk update \core_core_fasto1 $0\core_core_fasto1[2:0] end - attribute \src "libresoc.v:197285.3-197286.45" - process $proc$libresoc.v:197285$13704 + attribute \src "libresoc.v:196530.3-196531.45" + process $proc$libresoc.v:196530$13652 assign { } { } assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next sync posedge \clk update \core_fasto1_ok $0\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:197287.3-197288.49" - process $proc$libresoc.v:197287$13705 + attribute \src "libresoc.v:196532.3-196533.49" + process $proc$libresoc.v:196532$13653 assign { } { } assign $0\core_core_fasto2[2:0] \core_core_fasto2$next sync posedge \clk update \core_core_fasto2 $0\core_core_fasto2[2:0] end - attribute \src "libresoc.v:197289.3-197290.45" - process $proc$libresoc.v:197289$13706 + attribute \src "libresoc.v:196534.3-196535.45" + process $proc$libresoc.v:196534$13654 assign { } { } assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next sync posedge \clk update \core_fasto2_ok $0\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:197291.3-197292.49" - process $proc$libresoc.v:197291$13707 + attribute \src "libresoc.v:196536.3-196537.49" + process $proc$libresoc.v:196536$13655 assign { } { } assign $0\core_core_cr_in1[6:0] \core_core_cr_in1$next sync posedge \clk update \core_core_cr_in1 $0\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:197293.3-197294.55" - process $proc$libresoc.v:197293$13708 + attribute \src "libresoc.v:196538.3-196539.55" + process $proc$libresoc.v:196538$13656 assign { } { } assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next sync posedge \clk update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:197295.3-197296.49" - process $proc$libresoc.v:197295$13709 + attribute \src "libresoc.v:196540.3-196541.49" + process $proc$libresoc.v:196540$13657 assign { } { } assign $0\core_core_cr_in2[6:0] \core_core_cr_in2$next sync posedge \clk update \core_core_cr_in2 $0\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:197297.3-197298.55" - process $proc$libresoc.v:197297$13710 + attribute \src "libresoc.v:196542.3-196543.55" + process $proc$libresoc.v:196542$13658 assign { } { } assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next sync posedge \clk update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:197299.3-197300.55" - process $proc$libresoc.v:197299$13711 + attribute \src "libresoc.v:196544.3-196545.55" + process $proc$libresoc.v:196544$13659 assign { } { } - assign $0\core_core_cr_in2$1[6:0]$13712 \core_core_cr_in2$1$next + assign $0\core_core_cr_in2$1[6:0]$13660 \core_core_cr_in2$1$next sync posedge \clk - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13712 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13660 end - attribute \src "libresoc.v:197301.3-197302.39" - process $proc$libresoc.v:197301$13713 + attribute \src "libresoc.v:196546.3-196547.39" + process $proc$libresoc.v:196546$13661 assign { } { } assign $0\d_reg_delay[0:0] \d_reg_delay$next sync posedge \clk update \d_reg_delay $0\d_reg_delay[0:0] end - attribute \src "libresoc.v:197303.3-197304.61" - process $proc$libresoc.v:197303$13714 + attribute \src "libresoc.v:196548.3-196549.61" + process $proc$libresoc.v:196548$13662 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$13715 \core_core_cr_in2_ok$2$next + assign $0\core_core_cr_in2_ok$2[0:0]$13663 \core_core_cr_in2_ok$2$next sync posedge \clk - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13715 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13663 end - attribute \src "libresoc.v:197305.3-197306.49" - process $proc$libresoc.v:197305$13716 + attribute \src "libresoc.v:196550.3-196551.49" + process $proc$libresoc.v:196550$13664 assign { } { } assign $0\core_core_cr_out[6:0] \core_core_cr_out$next sync posedge \clk update \core_core_cr_out $0\core_core_cr_out[6:0] end - attribute \src "libresoc.v:197307.3-197308.45" - process $proc$libresoc.v:197307$13717 + attribute \src "libresoc.v:196552.3-196553.45" + process $proc$libresoc.v:196552$13665 assign { } { } assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next sync posedge \clk update \core_cr_out_ok $0\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:197309.3-197310.53" - process $proc$libresoc.v:197309$13718 + attribute \src "libresoc.v:196554.3-196555.53" + process $proc$libresoc.v:196554$13666 assign { } { } assign $0\core_core_core_msr[63:0] \core_core_core_msr$next sync posedge \clk update \core_core_core_msr $0\core_core_core_msr[63:0] end - attribute \src "libresoc.v:197311.3-197312.53" - process $proc$libresoc.v:197311$13719 + attribute \src "libresoc.v:196556.3-196557.53" + process $proc$libresoc.v:196556$13667 assign { } { } assign $0\core_core_core_cia[63:0] \core_core_core_cia$next sync posedge \clk update \core_core_core_cia $0\core_core_core_cia[63:0] end - attribute \src "libresoc.v:197313.3-197314.55" - process $proc$libresoc.v:197313$13720 + attribute \src "libresoc.v:196558.3-196559.55" + process $proc$libresoc.v:196558$13668 assign { } { } assign $0\core_core_core_insn[31:0] \core_core_core_insn$next sync posedge \clk update \core_core_core_insn $0\core_core_core_insn[31:0] end - attribute \src "libresoc.v:197315.3-197316.65" - process $proc$libresoc.v:197315$13721 + attribute \src "libresoc.v:196560.3-196561.65" + process $proc$libresoc.v:196560$13669 assign { } { } assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next sync posedge \clk update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:197317.3-197318.61" - process $proc$libresoc.v:197317$13722 + attribute \src "libresoc.v:196562.3-196563.61" + process $proc$libresoc.v:196562$13670 assign { } { } assign $0\core_core_core_fn_unit[13:0] \core_core_core_fn_unit$next sync posedge \clk update \core_core_core_fn_unit $0\core_core_core_fn_unit[13:0] end - attribute \src "libresoc.v:197319.3-197320.41" - process $proc$libresoc.v:197319$13723 + attribute \src "libresoc.v:196564.3-196565.41" + process $proc$libresoc.v:196564$13671 assign { } { } assign $0\core_core_lk[0:0] \core_core_lk$next sync posedge \clk update \core_core_lk $0\core_core_lk[0:0] end - attribute \src "libresoc.v:197321.3-197322.51" - process $proc$libresoc.v:197321$13724 + attribute \src "libresoc.v:196566.3-196567.51" + process $proc$libresoc.v:196566$13672 assign { } { } assign $0\core_core_core_rc[0:0] \core_core_core_rc$next sync posedge \clk update \core_core_core_rc $0\core_core_core_rc[0:0] end - attribute \src "libresoc.v:197323.3-197324.45" - process $proc$libresoc.v:197323$13725 + attribute \src "libresoc.v:196568.3-196569.45" + process $proc$libresoc.v:196568$13673 assign { } { } assign $0\exec_fsm_state[0:0] \exec_fsm_state$next sync posedge \clk update \exec_fsm_state $0\exec_fsm_state[0:0] end - attribute \src "libresoc.v:197325.3-197326.57" - process $proc$libresoc.v:197325$13726 + attribute \src "libresoc.v:196570.3-196571.57" + process $proc$libresoc.v:196570$13674 assign { } { } assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next sync posedge \clk update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:197327.3-197328.51" - process $proc$libresoc.v:197327$13727 + attribute \src "libresoc.v:196572.3-196573.51" + process $proc$libresoc.v:196572$13675 assign { } { } assign $0\core_core_core_oe[0:0] \core_core_core_oe$next sync posedge \clk update \core_core_core_oe $0\core_core_core_oe[0:0] end - attribute \src "libresoc.v:197329.3-197330.57" - process $proc$libresoc.v:197329$13728 + attribute \src "libresoc.v:196574.3-196575.57" + process $proc$libresoc.v:196574$13676 assign { } { } assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next sync posedge \clk update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:197331.3-197332.69" - process $proc$libresoc.v:197331$13729 + attribute \src "libresoc.v:196576.3-196577.69" + process $proc$libresoc.v:196576$13677 assign { } { } assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next sync posedge \clk update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:197333.3-197334.63" - process $proc$libresoc.v:197333$13730 + attribute \src "libresoc.v:196578.3-196579.63" + process $proc$libresoc.v:196578$13678 assign { } { } assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next sync posedge \clk update \core_core_core_traptype $0\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:197335.3-197336.71" - process $proc$libresoc.v:197335$13731 + attribute \src "libresoc.v:196580.3-196581.71" + process $proc$libresoc.v:196580$13679 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$13732 \core_core_core_exc_$signal$next + assign $0\core_core_core_exc_$signal[0:0]$13680 \core_core_core_exc_$signal$next sync posedge \clk - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13732 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13680 end - attribute \src "libresoc.v:197337.3-197338.75" - process $proc$libresoc.v:197337$13733 + attribute \src "libresoc.v:196582.3-196583.75" + process $proc$libresoc.v:196582$13681 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$13734 \core_core_core_exc_$signal$3$next + assign $0\core_core_core_exc_$signal$3[0:0]$13682 \core_core_core_exc_$signal$3$next sync posedge \clk - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13734 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13682 end - attribute \src "libresoc.v:197339.3-197340.75" - process $proc$libresoc.v:197339$13735 + attribute \src "libresoc.v:196584.3-196585.75" + process $proc$libresoc.v:196584$13683 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$13736 \core_core_core_exc_$signal$4$next + assign $0\core_core_core_exc_$signal$4[0:0]$13684 \core_core_core_exc_$signal$4$next sync posedge \clk - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13736 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13684 end - attribute \src "libresoc.v:197341.3-197342.75" - process $proc$libresoc.v:197341$13737 + attribute \src "libresoc.v:196586.3-196587.75" + process $proc$libresoc.v:196586$13685 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$13738 \core_core_core_exc_$signal$5$next + assign $0\core_core_core_exc_$signal$5[0:0]$13686 \core_core_core_exc_$signal$5$next sync posedge \clk - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13738 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13686 end - attribute \src "libresoc.v:197343.3-197344.75" - process $proc$libresoc.v:197343$13739 + attribute \src "libresoc.v:196588.3-196589.75" + process $proc$libresoc.v:196588$13687 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$13740 \core_core_core_exc_$signal$6$next + assign $0\core_core_core_exc_$signal$6[0:0]$13688 \core_core_core_exc_$signal$6$next sync posedge \clk - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13740 + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13688 end - attribute \src "libresoc.v:197345.3-197346.41" - process $proc$libresoc.v:197345$13741 + attribute \src "libresoc.v:196590.3-196591.41" + process $proc$libresoc.v:196590$13689 assign { } { } assign $0\core_sv_a_nz[0:0] \core_sv_a_nz$next sync posedge \clk update \core_sv_a_nz $0\core_sv_a_nz[0:0] end - attribute \src "libresoc.v:197347.3-197348.75" - process $proc$libresoc.v:197347$13742 + attribute \src "libresoc.v:196592.3-196593.75" + process $proc$libresoc.v:196592$13690 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$13743 \core_core_core_exc_$signal$7$next + assign $0\core_core_core_exc_$signal$7[0:0]$13691 \core_core_core_exc_$signal$7$next sync posedge \clk - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13743 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13691 end - attribute \src "libresoc.v:197349.3-197350.75" - process $proc$libresoc.v:197349$13744 + attribute \src "libresoc.v:196594.3-196595.75" + process $proc$libresoc.v:196594$13692 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$13745 \core_core_core_exc_$signal$8$next + assign $0\core_core_core_exc_$signal$8[0:0]$13693 \core_core_core_exc_$signal$8$next sync posedge \clk - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13745 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13693 end - attribute \src "libresoc.v:197351.3-197352.75" - process $proc$libresoc.v:197351$13746 + attribute \src "libresoc.v:196596.3-196597.75" + process $proc$libresoc.v:196596$13694 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$13747 \core_core_core_exc_$signal$9$next + assign $0\core_core_core_exc_$signal$9[0:0]$13695 \core_core_core_exc_$signal$9$next sync posedge \clk - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13747 + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13695 end - attribute \src "libresoc.v:197353.3-197354.63" - process $proc$libresoc.v:197353$13748 + attribute \src "libresoc.v:196598.3-196599.63" + process $proc$libresoc.v:196598$13696 assign { } { } assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next sync posedge \clk update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:197355.3-197356.57" - process $proc$libresoc.v:197355$13749 + attribute \src "libresoc.v:196600.3-196601.57" + process $proc$libresoc.v:196600$13697 assign { } { } assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next sync posedge \clk update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:197357.3-197358.63" - process $proc$libresoc.v:197357$13750 + attribute \src "libresoc.v:196602.3-196603.63" + process $proc$libresoc.v:196602$13698 assign { } { } assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next sync posedge \clk update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:197359.3-197360.57" - process $proc$libresoc.v:197359$13751 + attribute \src "libresoc.v:196604.3-196605.57" + process $proc$libresoc.v:196604$13699 assign { } { } assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next sync posedge \clk update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:197361.3-197362.53" - process $proc$libresoc.v:197361$13752 + attribute \src "libresoc.v:196606.3-196607.53" + process $proc$libresoc.v:196606$13700 assign { } { } assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next sync posedge \clk update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:197363.3-197364.63" - process $proc$libresoc.v:197363$13753 + attribute \src "libresoc.v:196608.3-196609.63" + process $proc$libresoc.v:196608$13701 assign { } { } assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next sync posedge \clk update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:197365.3-197366.37" - process $proc$libresoc.v:197365$13754 + attribute \src "libresoc.v:196610.3-196611.37" + process $proc$libresoc.v:196610$13702 assign { } { } assign $0\sv_changed[0:0] \sv_changed$next sync posedge \clk update \sv_changed $0\sv_changed[0:0] end - attribute \src "libresoc.v:197367.3-197368.57" - process $proc$libresoc.v:197367$13755 + attribute \src "libresoc.v:196612.3-196613.57" + process $proc$libresoc.v:196612$13703 assign { } { } - assign $0\core_bigendian_i$10[0:0]$13756 \core_bigendian_i$10$next + assign $0\core_bigendian_i$10[0:0]$13704 \core_bigendian_i$10$next sync posedge \clk - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13756 + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13704 end - attribute \src "libresoc.v:197369.3-197370.37" - process $proc$libresoc.v:197369$13757 + attribute \src "libresoc.v:196614.3-196615.37" + process $proc$libresoc.v:196614$13705 assign { } { } assign $0\pc_changed[0:0] \pc_changed$next sync posedge \clk update \pc_changed $0\pc_changed[0:0] end - attribute \src "libresoc.v:197371.3-197372.47" - process $proc$libresoc.v:197371$13758 + attribute \src "libresoc.v:196616.3-196617.47" + process $proc$libresoc.v:196616$13706 assign { } { } assign $0\issue_fsm_state[2:0] \issue_fsm_state$next sync posedge \clk update \issue_fsm_state $0\issue_fsm_state[2:0] end - attribute \src "libresoc.v:197373.3-197374.53" - process $proc$libresoc.v:197373$13759 + attribute \src "libresoc.v:196618.3-196619.53" + process $proc$libresoc.v:196618$13707 assign { } { } assign $0\dec2_raw_opcode_in[31:0] \dec2_raw_opcode_in$next sync posedge \clk update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:197375.3-197376.23" - process $proc$libresoc.v:197375$13760 + attribute \src "libresoc.v:196620.3-196621.23" + process $proc$libresoc.v:196620$13708 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:197377.3-197378.41" - process $proc$libresoc.v:197377$13761 + attribute \src "libresoc.v:196622.3-196623.41" + process $proc$libresoc.v:196622$13709 assign { } { } assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next sync posedge \clk update \dec2_cur_msr $0\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:197379.3-197380.47" - process $proc$libresoc.v:197379$13762 + attribute \src "libresoc.v:196624.3-196625.47" + process $proc$libresoc.v:196624$13710 assign { } { } assign $0\fetch_fsm_state[1:0] \fetch_fsm_state$next sync posedge \clk update \fetch_fsm_state $0\fetch_fsm_state[1:0] end - attribute \src "libresoc.v:197381.3-197382.33" - process $proc$libresoc.v:197381$13763 + attribute \src "libresoc.v:196626.3-196627.33" + process $proc$libresoc.v:196626$13711 assign { } { } assign $0\msr_read[0:0] \msr_read$next sync posedge \clk update \msr_read $0\msr_read[0:0] end - attribute \src "libresoc.v:197383.3-197384.45" - process $proc$libresoc.v:197383$13764 + attribute \src "libresoc.v:196628.3-196629.45" + process $proc$libresoc.v:196628$13712 assign { } { } assign $0\cur_cur_svstep[1:0] \cur_cur_svstep$next sync posedge \clk update \cur_cur_svstep $0\cur_cur_svstep[1:0] end - attribute \src "libresoc.v:197385.3-197386.43" - process $proc$libresoc.v:197385$13765 + attribute \src "libresoc.v:196630.3-196631.43" + process $proc$libresoc.v:196630$13713 assign { } { } assign $0\cur_cur_subvl[1:0] \cur_cur_subvl$next sync posedge \clk update \cur_cur_subvl $0\cur_cur_subvl[1:0] end - attribute \src "libresoc.v:197387.3-197388.47" - process $proc$libresoc.v:197387$13766 + attribute \src "libresoc.v:196632.3-196633.47" + process $proc$libresoc.v:196632$13714 assign { } { } assign $0\cur_cur_dststep[6:0] \cur_cur_dststep$next sync posedge \clk update \cur_cur_dststep $0\cur_cur_dststep[6:0] end - attribute \src "libresoc.v:197389.3-197390.47" - process $proc$libresoc.v:197389$13767 + attribute \src "libresoc.v:196634.3-196635.47" + process $proc$libresoc.v:196634$13715 assign { } { } assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next sync posedge \clk update \core_raw_insn_i $0\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:197391.3-197392.47" - process $proc$libresoc.v:197391$13768 + attribute \src "libresoc.v:196636.3-196637.47" + process $proc$libresoc.v:196636$13716 assign { } { } assign $0\cur_cur_srcstep[6:0] \cur_cur_srcstep$next sync posedge \clk update \cur_cur_srcstep $0\cur_cur_srcstep[6:0] end - attribute \src "libresoc.v:197393.3-197394.37" - process $proc$libresoc.v:197393$13769 + attribute \src "libresoc.v:196638.3-196639.37" + process $proc$libresoc.v:196638$13717 assign { } { } assign $0\cur_cur_vl[6:0] \cur_cur_vl$next sync posedge \clk update \cur_cur_vl $0\cur_cur_vl[6:0] end - attribute \src "libresoc.v:197395.3-197396.43" - process $proc$libresoc.v:197395$13770 + attribute \src "libresoc.v:196640.3-196641.43" + process $proc$libresoc.v:196640$13718 assign { } { } assign $0\cur_cur_maxvl[6:0] \cur_cur_maxvl$next sync posedge \clk update \cur_cur_maxvl $0\cur_cur_maxvl[6:0] end - attribute \src "libresoc.v:197397.3-197398.39" - process $proc$libresoc.v:197397$13771 + attribute \src "libresoc.v:196642.3-196643.39" + process $proc$libresoc.v:196642$13719 assign { } { } assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next sync posedge \clk update \dec2_cur_pc $0\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:197399.3-197400.49" - process $proc$libresoc.v:197399$13772 + attribute \src "libresoc.v:196644.3-196645.49" + process $proc$libresoc.v:196644$13720 assign { } { } assign $0\svstate_ok_delay[0:0] \svstate_ok_delay$next sync posedge \clk update \svstate_ok_delay $0\svstate_ok_delay[0:0] end - attribute \src "libresoc.v:197401.3-197402.39" - process $proc$libresoc.v:197401$13773 + attribute \src "libresoc.v:196646.3-196647.39" + process $proc$libresoc.v:196646$13721 assign { } { } assign $0\pc_ok_delay[0:0] \pc_ok_delay$next sync posedge \clk update \pc_ok_delay $0\pc_ok_delay[0:0] end - attribute \src "libresoc.v:197403.3-197404.43" - process $proc$libresoc.v:197403$13774 + attribute \src "libresoc.v:196648.3-196649.43" + process $proc$libresoc.v:196648$13722 assign { } { } assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o sync posedge \clk update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:197405.3-197406.27" - process $proc$libresoc.v:197405$13775 + attribute \src "libresoc.v:196650.3-196651.27" + process $proc$libresoc.v:196650$13723 assign { } { } assign $0\delay[1:0] \delay$next sync posedge \por_clk update \delay $0\delay[1:0] end - attribute \src "libresoc.v:197407.3-197408.43" - process $proc$libresoc.v:197407$13776 + attribute \src "libresoc.v:196652.3-196653.43" + process $proc$libresoc.v:196652$13724 assign { } { } assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next sync posedge \clk update \dec2_cur_eint $0\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:197409.3-197410.47" - process $proc$libresoc.v:197409$13777 + attribute \src "libresoc.v:196654.3-196655.47" + process $proc$libresoc.v:196654$13725 assign { } { } assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next sync posedge \clk update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:198037.3-198045.6" - process $proc$libresoc.v:198037$13778 + attribute \src "libresoc.v:197229.3-197237.6" + process $proc$libresoc.v:197229$13726 assign { } { } assign { } { } - assign $0\dbg_dmi_addr_i$next[3:0]$13779 $1\dbg_dmi_addr_i$next[3:0]$13780 - attribute \src "libresoc.v:198038.5-198038.29" + assign $0\dbg_dmi_addr_i$next[3:0]$13727 $1\dbg_dmi_addr_i$next[3:0]$13728 + attribute \src "libresoc.v:197230.5-197230.29" switch \initial - attribute \src "libresoc.v:198038.9-198038.17" + attribute \src "libresoc.v:197230.9-197230.17" case 1'1 case end @@ -412530,21 +407801,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_addr_i$next[3:0]$13780 4'0000 + assign $1\dbg_dmi_addr_i$next[3:0]$13728 4'0000 case - assign $1\dbg_dmi_addr_i$next[3:0]$13780 \jtag_dmi0__addr_i + assign $1\dbg_dmi_addr_i$next[3:0]$13728 \jtag_dmi0__addr_i end sync always - update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13779 + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13727 end - attribute \src "libresoc.v:198046.3-198054.6" - process $proc$libresoc.v:198046$13781 + attribute \src "libresoc.v:197238.3-197246.6" + process $proc$libresoc.v:197238$13729 assign { } { } assign { } { } - assign $0\dbg_dmi_req_i$next[0:0]$13782 $1\dbg_dmi_req_i$next[0:0]$13783 - attribute \src "libresoc.v:198047.5-198047.29" + assign $0\dbg_dmi_req_i$next[0:0]$13730 $1\dbg_dmi_req_i$next[0:0]$13731 + attribute \src "libresoc.v:197239.5-197239.29" switch \initial - attribute \src "libresoc.v:198047.9-198047.17" + attribute \src "libresoc.v:197239.9-197239.17" case 1'1 case end @@ -412553,61 +407824,15 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_req_i$next[0:0]$13783 1'0 - case - assign $1\dbg_dmi_req_i$next[0:0]$13783 \jtag_dmi0__req_i - end - sync always - update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13782 - end - attribute \src "libresoc.v:198055.3-198063.6" - process $proc$libresoc.v:198055$13784 - assign { } { } - assign { } { } - assign $0\dec2_cur_eint$next[0:0]$13785 $1\dec2_cur_eint$next[0:0]$13786 - attribute \src "libresoc.v:198056.5-198056.29" - switch \initial - attribute \src "libresoc.v:198056.9-198056.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dec2_cur_eint$next[0:0]$13786 1'0 - case - assign $1\dec2_cur_eint$next[0:0]$13786 \xics_icp_core_irq_o - end - sync always - update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13785 - end - attribute \src "libresoc.v:198064.3-198073.6" - process $proc$libresoc.v:198064$13787 - assign { } { } - assign { } { } - assign $0\delay$next[1:0]$13788 $1\delay$next[1:0]$13789 - attribute \src "libresoc.v:198065.5-198065.29" - switch \initial - attribute \src "libresoc.v:198065.9-198065.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" - switch \$23 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\delay$next[1:0]$13789 \$25 [1:0] + assign $1\dbg_dmi_req_i$next[0:0]$13731 1'0 case - assign $1\delay$next[1:0]$13789 \delay + assign $1\dbg_dmi_req_i$next[0:0]$13731 \jtag_dmi0__req_i end sync always - update \delay$next $0\delay$next[1:0]$13788 + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13730 end - attribute \src "libresoc.v:198074.3-198118.6" - process $proc$libresoc.v:198074$13790 + attribute \src "libresoc.v:197247.3-197291.6" + process $proc$libresoc.v:197247$13732 assign { } { } assign { } { } assign { } { } @@ -412638,19 +407863,19 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_core_dststep$next[6:0]$13791 $3\core_core_dststep$next[6:0]$13821 - assign $0\core_core_maxvl$next[6:0]$13792 $3\core_core_maxvl$next[6:0]$13822 - assign $0\core_core_pc$next[63:0]$13793 $3\core_core_pc$next[63:0]$13823 - assign $0\core_core_srcstep$next[6:0]$13794 $3\core_core_srcstep$next[6:0]$13824 - assign $0\core_core_subvl$next[1:0]$13795 $3\core_core_subvl$next[1:0]$13825 - assign $0\core_core_svstep$next[1:0]$13796 $3\core_core_svstep$next[1:0]$13826 - assign $0\core_core_vl$next[6:0]$13797 $3\core_core_vl$next[6:0]$13827 - assign $0\core_dec$next[63:0]$13798 $3\core_dec$next[63:0]$13828 - assign $0\core_eint$next[0:0]$13799 $3\core_eint$next[0:0]$13829 - assign $0\core_msr$next[63:0]$13800 $3\core_msr$next[63:0]$13830 - attribute \src "libresoc.v:198075.5-198075.29" + assign $0\core_core_dststep$next[6:0]$13733 $3\core_core_dststep$next[6:0]$13763 + assign $0\core_core_maxvl$next[6:0]$13734 $3\core_core_maxvl$next[6:0]$13764 + assign $0\core_core_pc$next[63:0]$13735 $3\core_core_pc$next[63:0]$13765 + assign $0\core_core_srcstep$next[6:0]$13736 $3\core_core_srcstep$next[6:0]$13766 + assign $0\core_core_subvl$next[1:0]$13737 $3\core_core_subvl$next[1:0]$13767 + assign $0\core_core_svstep$next[1:0]$13738 $3\core_core_svstep$next[1:0]$13768 + assign $0\core_core_vl$next[6:0]$13739 $3\core_core_vl$next[6:0]$13769 + assign $0\core_dec$next[63:0]$13740 $3\core_dec$next[63:0]$13770 + assign $0\core_eint$next[0:0]$13741 $3\core_eint$next[0:0]$13771 + assign $0\core_msr$next[63:0]$13742 $3\core_msr$next[63:0]$13772 + attribute \src "libresoc.v:197248.5-197248.29" switch \initial - attribute \src "libresoc.v:198075.9-198075.17" + attribute \src "libresoc.v:197248.9-197248.17" case 1'1 case end @@ -412668,16 +407893,16 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\core_core_dststep$next[6:0]$13801 $2\core_core_dststep$next[6:0]$13811 - assign $1\core_core_maxvl$next[6:0]$13802 $2\core_core_maxvl$next[6:0]$13812 - assign $1\core_core_pc$next[63:0]$13803 $2\core_core_pc$next[63:0]$13813 - assign $1\core_core_srcstep$next[6:0]$13804 $2\core_core_srcstep$next[6:0]$13814 - assign $1\core_core_subvl$next[1:0]$13805 $2\core_core_subvl$next[1:0]$13815 - assign $1\core_core_svstep$next[1:0]$13806 $2\core_core_svstep$next[1:0]$13816 - assign $1\core_core_vl$next[6:0]$13807 $2\core_core_vl$next[6:0]$13817 - assign $1\core_dec$next[63:0]$13808 $2\core_dec$next[63:0]$13818 - assign $1\core_eint$next[0:0]$13809 $2\core_eint$next[0:0]$13819 - assign $1\core_msr$next[63:0]$13810 $2\core_msr$next[63:0]$13820 + assign $1\core_core_dststep$next[6:0]$13743 $2\core_core_dststep$next[6:0]$13753 + assign $1\core_core_maxvl$next[6:0]$13744 $2\core_core_maxvl$next[6:0]$13754 + assign $1\core_core_pc$next[63:0]$13745 $2\core_core_pc$next[63:0]$13755 + assign $1\core_core_srcstep$next[6:0]$13746 $2\core_core_srcstep$next[6:0]$13756 + assign $1\core_core_subvl$next[1:0]$13747 $2\core_core_subvl$next[1:0]$13757 + assign $1\core_core_svstep$next[1:0]$13748 $2\core_core_svstep$next[1:0]$13758 + assign $1\core_core_vl$next[6:0]$13749 $2\core_core_vl$next[6:0]$13759 + assign $1\core_dec$next[63:0]$13750 $2\core_dec$next[63:0]$13760 + assign $1\core_eint$next[0:0]$13751 $2\core_eint$next[0:0]$13761 + assign $1\core_msr$next[63:0]$13752 $2\core_msr$next[63:0]$13762 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" @@ -412692,18 +407917,18 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\core_core_maxvl$next[6:0]$13812 $2\core_core_vl$next[6:0]$13817 $2\core_core_srcstep$next[6:0]$13814 $2\core_core_dststep$next[6:0]$13811 $2\core_core_subvl$next[1:0]$13815 $2\core_core_svstep$next[1:0]$13816 $2\core_dec$next[63:0]$13818 $2\core_eint$next[0:0]$13819 $2\core_msr$next[63:0]$13820 $2\core_core_pc$next[63:0]$13813 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + assign { $2\core_core_maxvl$next[6:0]$13754 $2\core_core_vl$next[6:0]$13759 $2\core_core_srcstep$next[6:0]$13756 $2\core_core_dststep$next[6:0]$13753 $2\core_core_subvl$next[1:0]$13757 $2\core_core_svstep$next[1:0]$13758 $2\core_dec$next[63:0]$13760 $2\core_eint$next[0:0]$13761 $2\core_msr$next[63:0]$13762 $2\core_core_pc$next[63:0]$13755 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } case - assign $2\core_core_dststep$next[6:0]$13811 \core_core_dststep - assign $2\core_core_maxvl$next[6:0]$13812 \core_core_maxvl - assign $2\core_core_pc$next[63:0]$13813 \core_core_pc - assign $2\core_core_srcstep$next[6:0]$13814 \core_core_srcstep - assign $2\core_core_subvl$next[1:0]$13815 \core_core_subvl - assign $2\core_core_svstep$next[1:0]$13816 \core_core_svstep - assign $2\core_core_vl$next[6:0]$13817 \core_core_vl - assign $2\core_dec$next[63:0]$13818 \core_dec - assign $2\core_eint$next[0:0]$13819 \core_eint - assign $2\core_msr$next[63:0]$13820 \core_msr + assign $2\core_core_dststep$next[6:0]$13753 \core_core_dststep + assign $2\core_core_maxvl$next[6:0]$13754 \core_core_maxvl + assign $2\core_core_pc$next[63:0]$13755 \core_core_pc + assign $2\core_core_srcstep$next[6:0]$13756 \core_core_srcstep + assign $2\core_core_subvl$next[1:0]$13757 \core_core_subvl + assign $2\core_core_svstep$next[1:0]$13758 \core_core_svstep + assign $2\core_core_vl$next[6:0]$13759 \core_core_vl + assign $2\core_dec$next[63:0]$13760 \core_dec + assign $2\core_eint$next[0:0]$13761 \core_eint + assign $2\core_msr$next[63:0]$13762 \core_msr end attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -412717,18 +407942,18 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $1\core_core_maxvl$next[6:0]$13802 $1\core_core_vl$next[6:0]$13807 $1\core_core_srcstep$next[6:0]$13804 $1\core_core_dststep$next[6:0]$13801 $1\core_core_subvl$next[1:0]$13805 $1\core_core_svstep$next[1:0]$13806 $1\core_dec$next[63:0]$13808 $1\core_eint$next[0:0]$13809 $1\core_msr$next[63:0]$13810 $1\core_core_pc$next[63:0]$13803 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + assign { $1\core_core_maxvl$next[6:0]$13744 $1\core_core_vl$next[6:0]$13749 $1\core_core_srcstep$next[6:0]$13746 $1\core_core_dststep$next[6:0]$13743 $1\core_core_subvl$next[1:0]$13747 $1\core_core_svstep$next[1:0]$13748 $1\core_dec$next[63:0]$13750 $1\core_eint$next[0:0]$13751 $1\core_msr$next[63:0]$13752 $1\core_core_pc$next[63:0]$13745 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } case - assign $1\core_core_dststep$next[6:0]$13801 \core_core_dststep - assign $1\core_core_maxvl$next[6:0]$13802 \core_core_maxvl - assign $1\core_core_pc$next[63:0]$13803 \core_core_pc - assign $1\core_core_srcstep$next[6:0]$13804 \core_core_srcstep - assign $1\core_core_subvl$next[1:0]$13805 \core_core_subvl - assign $1\core_core_svstep$next[1:0]$13806 \core_core_svstep - assign $1\core_core_vl$next[6:0]$13807 \core_core_vl - assign $1\core_dec$next[63:0]$13808 \core_dec - assign $1\core_eint$next[0:0]$13809 \core_eint - assign $1\core_msr$next[63:0]$13810 \core_msr + assign $1\core_core_dststep$next[6:0]$13743 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13744 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13745 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13746 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13747 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13748 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13749 \core_core_vl + assign $1\core_dec$next[63:0]$13750 \core_dec + assign $1\core_eint$next[0:0]$13751 \core_eint + assign $1\core_msr$next[63:0]$13752 \core_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -412744,49 +407969,49 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $3\core_core_pc$next[63:0]$13823 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_msr$next[63:0]$13830 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_eint$next[0:0]$13829 1'0 - assign $3\core_dec$next[63:0]$13828 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_core_svstep$next[1:0]$13826 2'00 - assign $3\core_core_subvl$next[1:0]$13825 2'00 - assign $3\core_core_dststep$next[6:0]$13821 7'0000000 - assign $3\core_core_srcstep$next[6:0]$13824 7'0000000 - assign $3\core_core_vl$next[6:0]$13827 7'0000000 - assign $3\core_core_maxvl$next[6:0]$13822 7'0000000 + assign $3\core_core_pc$next[63:0]$13765 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_msr$next[63:0]$13772 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_eint$next[0:0]$13771 1'0 + assign $3\core_dec$next[63:0]$13770 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_core_svstep$next[1:0]$13768 2'00 + assign $3\core_core_subvl$next[1:0]$13767 2'00 + assign $3\core_core_dststep$next[6:0]$13763 7'0000000 + assign $3\core_core_srcstep$next[6:0]$13766 7'0000000 + assign $3\core_core_vl$next[6:0]$13769 7'0000000 + assign $3\core_core_maxvl$next[6:0]$13764 7'0000000 case - assign $3\core_core_dststep$next[6:0]$13821 $1\core_core_dststep$next[6:0]$13801 - assign $3\core_core_maxvl$next[6:0]$13822 $1\core_core_maxvl$next[6:0]$13802 - assign $3\core_core_pc$next[63:0]$13823 $1\core_core_pc$next[63:0]$13803 - assign $3\core_core_srcstep$next[6:0]$13824 $1\core_core_srcstep$next[6:0]$13804 - assign $3\core_core_subvl$next[1:0]$13825 $1\core_core_subvl$next[1:0]$13805 - assign $3\core_core_svstep$next[1:0]$13826 $1\core_core_svstep$next[1:0]$13806 - assign $3\core_core_vl$next[6:0]$13827 $1\core_core_vl$next[6:0]$13807 - assign $3\core_dec$next[63:0]$13828 $1\core_dec$next[63:0]$13808 - assign $3\core_eint$next[0:0]$13829 $1\core_eint$next[0:0]$13809 - assign $3\core_msr$next[63:0]$13830 $1\core_msr$next[63:0]$13810 + assign $3\core_core_dststep$next[6:0]$13763 $1\core_core_dststep$next[6:0]$13743 + assign $3\core_core_maxvl$next[6:0]$13764 $1\core_core_maxvl$next[6:0]$13744 + assign $3\core_core_pc$next[63:0]$13765 $1\core_core_pc$next[63:0]$13745 + assign $3\core_core_srcstep$next[6:0]$13766 $1\core_core_srcstep$next[6:0]$13746 + assign $3\core_core_subvl$next[1:0]$13767 $1\core_core_subvl$next[1:0]$13747 + assign $3\core_core_svstep$next[1:0]$13768 $1\core_core_svstep$next[1:0]$13748 + assign $3\core_core_vl$next[6:0]$13769 $1\core_core_vl$next[6:0]$13749 + assign $3\core_dec$next[63:0]$13770 $1\core_dec$next[63:0]$13750 + assign $3\core_eint$next[0:0]$13771 $1\core_eint$next[0:0]$13751 + assign $3\core_msr$next[63:0]$13772 $1\core_msr$next[63:0]$13752 end sync always - update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13791 - update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13792 - update \core_core_pc$next $0\core_core_pc$next[63:0]$13793 - update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13794 - update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13795 - update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13796 - update \core_core_vl$next $0\core_core_vl$next[6:0]$13797 - update \core_dec$next $0\core_dec$next[63:0]$13798 - update \core_eint$next $0\core_eint$next[0:0]$13799 - update \core_msr$next $0\core_msr$next[63:0]$13800 + update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13733 + update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13734 + update \core_core_pc$next $0\core_core_pc$next[63:0]$13735 + update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13736 + update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13737 + update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13738 + update \core_core_vl$next $0\core_core_vl$next[6:0]$13739 + update \core_dec$next $0\core_dec$next[63:0]$13740 + update \core_eint$next $0\core_eint$next[0:0]$13741 + update \core_msr$next $0\core_msr$next[63:0]$13742 end - attribute \src "libresoc.v:198119.3-198139.6" - process $proc$libresoc.v:198119$13831 + attribute \src "libresoc.v:197292.3-197312.6" + process $proc$libresoc.v:197292$13773 assign { } { } assign { } { } assign { } { } - assign $0\core_raw_insn_i$next[31:0]$13832 $3\core_raw_insn_i$next[31:0]$13835 - attribute \src "libresoc.v:198120.5-198120.29" + assign $0\core_raw_insn_i$next[31:0]$13774 $3\core_raw_insn_i$next[31:0]$13777 + attribute \src "libresoc.v:197293.5-197293.29" switch \initial - attribute \src "libresoc.v:198120.9-198120.17" + attribute \src "libresoc.v:197293.9-197293.17" case 1'1 case end @@ -412795,40 +408020,40 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13833 $2\core_raw_insn_i$next[31:0]$13834 + assign $1\core_raw_insn_i$next[31:0]$13775 $2\core_raw_insn_i$next[31:0]$13776 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_raw_insn_i$next[31:0]$13834 \dec2_raw_opcode_in + assign $2\core_raw_insn_i$next[31:0]$13776 \dec2_raw_opcode_in case - assign $2\core_raw_insn_i$next[31:0]$13834 \core_raw_insn_i + assign $2\core_raw_insn_i$next[31:0]$13776 \core_raw_insn_i end case - assign $1\core_raw_insn_i$next[31:0]$13833 \core_raw_insn_i + assign $1\core_raw_insn_i$next[31:0]$13775 \core_raw_insn_i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_raw_insn_i$next[31:0]$13835 0 + assign $3\core_raw_insn_i$next[31:0]$13777 0 case - assign $3\core_raw_insn_i$next[31:0]$13835 $1\core_raw_insn_i$next[31:0]$13833 + assign $3\core_raw_insn_i$next[31:0]$13777 $1\core_raw_insn_i$next[31:0]$13775 end sync always - update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13832 + update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13774 end - attribute \src "libresoc.v:198140.3-198164.6" - process $proc$libresoc.v:198140$13836 + attribute \src "libresoc.v:197313.3-197337.6" + process $proc$libresoc.v:197313$13778 assign { } { } assign { } { } assign { } { } - assign $0\core_bigendian_i$10$next[0:0]$13837 $3\core_bigendian_i$10$next[0:0]$13840 - attribute \src "libresoc.v:198141.5-198141.29" + assign $0\core_bigendian_i$10$next[0:0]$13779 $3\core_bigendian_i$10$next[0:0]$13782 + attribute \src "libresoc.v:197314.5-197314.29" switch \initial - attribute \src "libresoc.v:198141.9-198141.17" + attribute \src "libresoc.v:197314.9-197314.17" case 1'1 case end @@ -412837,44 +408062,44 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13838 $2\core_bigendian_i$10$next[0:0]$13839 + assign $1\core_bigendian_i$10$next[0:0]$13780 $2\core_bigendian_i$10$next[0:0]$13781 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_bigendian_i$10$next[0:0]$13839 \core_bigendian_i + assign $2\core_bigendian_i$10$next[0:0]$13781 \core_bigendian_i case - assign $2\core_bigendian_i$10$next[0:0]$13839 \core_bigendian_i$10 + assign $2\core_bigendian_i$10$next[0:0]$13781 \core_bigendian_i$10 end attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13838 \core_bigendian_i + assign $1\core_bigendian_i$10$next[0:0]$13780 \core_bigendian_i case - assign $1\core_bigendian_i$10$next[0:0]$13838 \core_bigendian_i$10 + assign $1\core_bigendian_i$10$next[0:0]$13780 \core_bigendian_i$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_bigendian_i$10$next[0:0]$13840 1'0 + assign $3\core_bigendian_i$10$next[0:0]$13782 1'0 case - assign $3\core_bigendian_i$10$next[0:0]$13840 $1\core_bigendian_i$10$next[0:0]$13838 + assign $3\core_bigendian_i$10$next[0:0]$13782 $1\core_bigendian_i$10$next[0:0]$13780 end sync always - update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13837 + update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13779 end - attribute \src "libresoc.v:198165.3-198189.6" - process $proc$libresoc.v:198165$13841 + attribute \src "libresoc.v:197338.3-197362.6" + process $proc$libresoc.v:197338$13783 assign { } { } assign { } { } assign { } { } - assign $0\core_sv_a_nz$next[0:0]$13842 $3\core_sv_a_nz$next[0:0]$13845 - attribute \src "libresoc.v:198166.5-198166.29" + assign $0\core_sv_a_nz$next[0:0]$13784 $3\core_sv_a_nz$next[0:0]$13787 + attribute \src "libresoc.v:197339.5-197339.29" switch \initial - attribute \src "libresoc.v:198166.9-198166.17" + attribute \src "libresoc.v:197339.9-197339.17" case 1'1 case end @@ -412883,44 +408108,44 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\core_sv_a_nz$next[0:0]$13843 $2\core_sv_a_nz$next[0:0]$13844 + assign $1\core_sv_a_nz$next[0:0]$13785 $2\core_sv_a_nz$next[0:0]$13786 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_sv_a_nz$next[0:0]$13844 \dec2_sv_a_nz + assign $2\core_sv_a_nz$next[0:0]$13786 \dec2_sv_a_nz case - assign $2\core_sv_a_nz$next[0:0]$13844 \core_sv_a_nz + assign $2\core_sv_a_nz$next[0:0]$13786 \core_sv_a_nz end attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } - assign $1\core_sv_a_nz$next[0:0]$13843 \dec2_sv_a_nz + assign $1\core_sv_a_nz$next[0:0]$13785 \dec2_sv_a_nz case - assign $1\core_sv_a_nz$next[0:0]$13843 \core_sv_a_nz + assign $1\core_sv_a_nz$next[0:0]$13785 \core_sv_a_nz end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_sv_a_nz$next[0:0]$13845 1'0 + assign $3\core_sv_a_nz$next[0:0]$13787 1'0 case - assign $3\core_sv_a_nz$next[0:0]$13845 $1\core_sv_a_nz$next[0:0]$13843 + assign $3\core_sv_a_nz$next[0:0]$13787 $1\core_sv_a_nz$next[0:0]$13785 end sync always - update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13842 + update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13784 end - attribute \src "libresoc.v:198190.3-198227.6" - process $proc$libresoc.v:198190$13846 + attribute \src "libresoc.v:197363.3-197400.6" + process $proc$libresoc.v:197363$13788 assign { } { } assign { } { } assign { } { } assign $0\insn_done[0:0] $4\insn_done[0:0] - attribute \src "libresoc.v:198191.5-198191.29" + attribute \src "libresoc.v:197364.5-197364.29" switch \initial - attribute \src "libresoc.v:198191.9-198191.17" + attribute \src "libresoc.v:197364.9-197364.17" case 1'1 case end @@ -412981,14 +408206,14 @@ module \ti sync always update \insn_done $0\insn_done[0:0] end - attribute \src "libresoc.v:198228.3-198238.6" - process $proc$libresoc.v:198228$13847 + attribute \src "libresoc.v:197401.3-197411.6" + process $proc$libresoc.v:197401$13789 assign { } { } assign { } { } assign $0\pred_insn_valid_i[0:0] $1\pred_insn_valid_i[0:0] - attribute \src "libresoc.v:198229.5-198229.29" + attribute \src "libresoc.v:197402.5-197402.29" switch \initial - attribute \src "libresoc.v:198229.9-198229.17" + attribute \src "libresoc.v:197402.9-197402.17" case 1'1 case end @@ -413004,14 +408229,14 @@ module \ti sync always update \pred_insn_valid_i $0\pred_insn_valid_i[0:0] end - attribute \src "libresoc.v:198239.3-198249.6" - process $proc$libresoc.v:198239$13848 + attribute \src "libresoc.v:197412.3-197422.6" + process $proc$libresoc.v:197412$13790 assign { } { } assign { } { } assign $0\pred_mask_ready_i[0:0] $1\pred_mask_ready_i[0:0] - attribute \src "libresoc.v:198240.5-198240.29" + attribute \src "libresoc.v:197413.5-197413.29" switch \initial - attribute \src "libresoc.v:198240.9-198240.17" + attribute \src "libresoc.v:197413.9-197413.17" case 1'1 case end @@ -413027,14 +408252,14 @@ module \ti sync always update \pred_mask_ready_i $0\pred_mask_ready_i[0:0] end - attribute \src "libresoc.v:198250.3-198260.6" - process $proc$libresoc.v:198250$13849 + attribute \src "libresoc.v:197423.3-197433.6" + process $proc$libresoc.v:197423$13791 assign { } { } assign { } { } assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:198251.5-198251.29" + attribute \src "libresoc.v:197424.5-197424.29" switch \initial - attribute \src "libresoc.v:198251.9-198251.17" + attribute \src "libresoc.v:197424.9-197424.17" case 1'1 case end @@ -413050,14 +408275,14 @@ module \ti sync always update \exec_insn_valid_i $0\exec_insn_valid_i[0:0] end - attribute \src "libresoc.v:198261.3-198276.6" - process $proc$libresoc.v:198261$13850 + attribute \src "libresoc.v:197434.3-197449.6" + process $proc$libresoc.v:197434$13792 assign { } { } assign { } { } assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:198262.5-198262.29" + attribute \src "libresoc.v:197435.5-197435.29" switch \initial - attribute \src "libresoc.v:198262.9-198262.17" + attribute \src "libresoc.v:197435.9-197435.17" case 1'1 case end @@ -413082,14 +408307,14 @@ module \ti sync always update \exec_pc_ready_i $0\exec_pc_ready_i[0:0] end - attribute \src "libresoc.v:198277.3-198297.6" - process $proc$libresoc.v:198277$13851 + attribute \src "libresoc.v:197450.3-197470.6" + process $proc$libresoc.v:197450$13793 assign { } { } assign { } { } assign $0\is_last[0:0] $1\is_last[0:0] - attribute \src "libresoc.v:198278.5-198278.29" + attribute \src "libresoc.v:197451.5-197451.29" switch \initial - attribute \src "libresoc.v:198278.9-198278.17" + attribute \src "libresoc.v:197451.9-197451.17" case 1'1 case end @@ -413123,14 +408348,14 @@ module \ti sync always update \is_last $0\is_last[0:0] end - attribute \src "libresoc.v:198298.3-198307.6" - process $proc$libresoc.v:198298$13852 + attribute \src "libresoc.v:197471.3-197480.6" + process $proc$libresoc.v:197471$13794 assign { } { } assign { } { } - assign $0\core_wen$11[2:0]$13853 $1\core_wen$11[2:0]$13854 - attribute \src "libresoc.v:198299.5-198299.29" + assign $0\core_wen$11[2:0]$13795 $1\core_wen$11[2:0]$13796 + attribute \src "libresoc.v:197472.5-197472.29" switch \initial - attribute \src "libresoc.v:198299.9-198299.17" + attribute \src "libresoc.v:197472.9-197472.17" case 1'1 case end @@ -413139,21 +408364,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_wen$11[2:0]$13854 3'100 + assign $1\core_wen$11[2:0]$13796 3'100 case - assign $1\core_wen$11[2:0]$13854 3'000 + assign $1\core_wen$11[2:0]$13796 3'000 end sync always - update \core_wen$11 $0\core_wen$11[2:0]$13853 + update \core_wen$11 $0\core_wen$11[2:0]$13795 end - attribute \src "libresoc.v:198308.3-198317.6" - process $proc$libresoc.v:198308$13855 + attribute \src "libresoc.v:197481.3-197490.6" + process $proc$libresoc.v:197481$13797 assign { } { } assign { } { } - assign $0\core_data_i$12[63:0]$13856 $1\core_data_i$12[63:0]$13857 - attribute \src "libresoc.v:198309.5-198309.29" + assign $0\core_data_i$12[63:0]$13798 $1\core_data_i$12[63:0]$13799 + attribute \src "libresoc.v:197482.5-197482.29" switch \initial - attribute \src "libresoc.v:198309.9-198309.17" + attribute \src "libresoc.v:197482.9-197482.17" case 1'1 case end @@ -413162,21 +408387,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_data_i$12[63:0]$13857 \$252 + assign $1\core_data_i$12[63:0]$13799 \$252 case - assign $1\core_data_i$12[63:0]$13857 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_data_i$12[63:0]$13799 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \core_data_i$12 $0\core_data_i$12[63:0]$13856 + update \core_data_i$12 $0\core_data_i$12[63:0]$13798 end - attribute \src "libresoc.v:198318.3-198328.6" - process $proc$libresoc.v:198318$13858 + attribute \src "libresoc.v:197491.3-197501.6" + process $proc$libresoc.v:197491$13800 assign { } { } assign { } { } assign $0\exec_insn_ready_o[0:0] $1\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:198319.5-198319.29" + attribute \src "libresoc.v:197492.5-197492.29" switch \initial - attribute \src "libresoc.v:198319.9-198319.17" + attribute \src "libresoc.v:197492.9-197492.17" case 1'1 case end @@ -413192,14 +408417,14 @@ module \ti sync always update \exec_insn_ready_o $0\exec_insn_ready_o[0:0] end - attribute \src "libresoc.v:198329.3-198353.6" - process $proc$libresoc.v:198329$13859 + attribute \src "libresoc.v:197502.3-197526.6" + process $proc$libresoc.v:197502$13801 assign { } { } assign { } { } assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:198330.5-198330.29" + attribute \src "libresoc.v:197503.5-197503.29" switch \initial - attribute \src "libresoc.v:198330.9-198330.17" + attribute \src "libresoc.v:197503.9-197503.17" case 1'1 case end @@ -413237,14 +408462,14 @@ module \ti sync always update \core_ivalid_i $0\core_ivalid_i[0:0] end - attribute \src "libresoc.v:198354.3-198369.6" - process $proc$libresoc.v:198354$13860 + attribute \src "libresoc.v:197527.3-197542.6" + process $proc$libresoc.v:197527$13802 assign { } { } assign { } { } assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] - attribute \src "libresoc.v:198355.5-198355.29" + attribute \src "libresoc.v:197528.5-197528.29" switch \initial - attribute \src "libresoc.v:198355.9-198355.17" + attribute \src "libresoc.v:197528.9-197528.17" case 1'1 case end @@ -413269,15 +408494,15 @@ module \ti sync always update \core_issue_i $0\core_issue_i[0:0] end - attribute \src "libresoc.v:198370.3-198404.6" - process $proc$libresoc.v:198370$13861 + attribute \src "libresoc.v:197543.3-197577.6" + process $proc$libresoc.v:197543$13803 assign { } { } assign { } { } assign { } { } - assign $0\exec_fsm_state$next[0:0]$13862 $5\exec_fsm_state$next[0:0]$13867 - attribute \src "libresoc.v:198371.5-198371.29" + assign $0\exec_fsm_state$next[0:0]$13804 $5\exec_fsm_state$next[0:0]$13809 + attribute \src "libresoc.v:197544.5-197544.29" switch \initial - attribute \src "libresoc.v:198371.9-198371.17" + attribute \src "libresoc.v:197544.9-197544.17" case 1'1 case end @@ -413286,61 +408511,61 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $1\exec_fsm_state$next[0:0]$13863 $2\exec_fsm_state$next[0:0]$13864 + assign $1\exec_fsm_state$next[0:0]$13805 $2\exec_fsm_state$next[0:0]$13806 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\exec_fsm_state$next[0:0]$13864 1'1 + assign $2\exec_fsm_state$next[0:0]$13806 1'1 case - assign $2\exec_fsm_state$next[0:0]$13864 \exec_fsm_state + assign $2\exec_fsm_state$next[0:0]$13806 \exec_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\exec_fsm_state$next[0:0]$13863 $3\exec_fsm_state$next[0:0]$13865 + assign $1\exec_fsm_state$next[0:0]$13805 $3\exec_fsm_state$next[0:0]$13807 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" switch \$256 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\exec_fsm_state$next[0:0]$13865 $4\exec_fsm_state$next[0:0]$13866 + assign $3\exec_fsm_state$next[0:0]$13807 $4\exec_fsm_state$next[0:0]$13808 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" switch \exec_pc_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\exec_fsm_state$next[0:0]$13866 1'0 + assign $4\exec_fsm_state$next[0:0]$13808 1'0 case - assign $4\exec_fsm_state$next[0:0]$13866 \exec_fsm_state + assign $4\exec_fsm_state$next[0:0]$13808 \exec_fsm_state end case - assign $3\exec_fsm_state$next[0:0]$13865 \exec_fsm_state + assign $3\exec_fsm_state$next[0:0]$13807 \exec_fsm_state end case - assign $1\exec_fsm_state$next[0:0]$13863 \exec_fsm_state + assign $1\exec_fsm_state$next[0:0]$13805 \exec_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\exec_fsm_state$next[0:0]$13867 1'0 + assign $5\exec_fsm_state$next[0:0]$13809 1'0 case - assign $5\exec_fsm_state$next[0:0]$13867 $1\exec_fsm_state$next[0:0]$13863 + assign $5\exec_fsm_state$next[0:0]$13809 $1\exec_fsm_state$next[0:0]$13805 end sync always - update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13862 + update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13804 end - attribute \src "libresoc.v:198405.3-198420.6" - process $proc$libresoc.v:198405$13868 + attribute \src "libresoc.v:197578.3-197593.6" + process $proc$libresoc.v:197578$13810 assign { } { } assign { } { } assign $0\exec_pc_valid_o[0:0] $1\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:198406.5-198406.29" + attribute \src "libresoc.v:197579.5-197579.29" switch \initial - attribute \src "libresoc.v:198406.9-198406.17" + attribute \src "libresoc.v:197579.9-197579.17" case 1'1 case end @@ -413365,14 +408590,14 @@ module \ti sync always update \exec_pc_valid_o $0\exec_pc_valid_o[0:0] end - attribute \src "libresoc.v:198421.3-198430.6" - process $proc$libresoc.v:198421$13869 + attribute \src "libresoc.v:197594.3-197603.6" + process $proc$libresoc.v:197594$13811 assign { } { } assign { } { } assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:198422.5-198422.29" + attribute \src "libresoc.v:197595.5-197595.29" switch \initial - attribute \src "libresoc.v:198422.9-198422.17" + attribute \src "libresoc.v:197595.9-197595.17" case 1'1 case end @@ -413388,14 +408613,14 @@ module \ti sync always update \core_dmi__addr $0\core_dmi__addr[4:0] end - attribute \src "libresoc.v:198431.3-198440.6" - process $proc$libresoc.v:198431$13870 + attribute \src "libresoc.v:197604.3-197613.6" + process $proc$libresoc.v:197604$13812 assign { } { } assign { } { } assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:198432.5-198432.29" + attribute \src "libresoc.v:197605.5-197605.29" switch \initial - attribute \src "libresoc.v:198432.9-198432.17" + attribute \src "libresoc.v:197605.9-197605.17" case 1'1 case end @@ -413411,14 +408636,14 @@ module \ti sync always update \core_dmi__ren $0\core_dmi__ren[0:0] end - attribute \src "libresoc.v:198441.3-198449.6" - process $proc$libresoc.v:198441$13871 + attribute \src "libresoc.v:197614.3-197622.6" + process $proc$libresoc.v:197614$13813 assign { } { } assign { } { } - assign $0\d_reg_delay$next[0:0]$13872 $1\d_reg_delay$next[0:0]$13873 - attribute \src "libresoc.v:198442.5-198442.29" + assign $0\d_reg_delay$next[0:0]$13814 $1\d_reg_delay$next[0:0]$13815 + attribute \src "libresoc.v:197615.5-197615.29" switch \initial - attribute \src "libresoc.v:198442.9-198442.17" + attribute \src "libresoc.v:197615.9-197615.17" case 1'1 case end @@ -413427,21 +408652,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_reg_delay$next[0:0]$13873 1'0 + assign $1\d_reg_delay$next[0:0]$13815 1'0 case - assign $1\d_reg_delay$next[0:0]$13873 \dbg_d_gpr_req + assign $1\d_reg_delay$next[0:0]$13815 \dbg_d_gpr_req end sync always - update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13872 + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13814 end - attribute \src "libresoc.v:198450.3-198459.6" - process $proc$libresoc.v:198450$13874 + attribute \src "libresoc.v:197623.3-197632.6" + process $proc$libresoc.v:197623$13816 assign { } { } assign { } { } assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:198451.5-198451.29" + attribute \src "libresoc.v:197624.5-197624.29" switch \initial - attribute \src "libresoc.v:198451.9-198451.17" + attribute \src "libresoc.v:197624.9-197624.17" case 1'1 case end @@ -413457,14 +408682,14 @@ module \ti sync always update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] end - attribute \src "libresoc.v:198460.3-198469.6" - process $proc$libresoc.v:198460$13875 + attribute \src "libresoc.v:197633.3-197642.6" + process $proc$libresoc.v:197633$13817 assign { } { } assign { } { } assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:198461.5-198461.29" + attribute \src "libresoc.v:197634.5-197634.29" switch \initial - attribute \src "libresoc.v:198461.9-198461.17" + attribute \src "libresoc.v:197634.9-197634.17" case 1'1 case end @@ -413480,14 +408705,14 @@ module \ti sync always update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] end - attribute \src "libresoc.v:198470.3-198479.6" - process $proc$libresoc.v:198470$13876 + attribute \src "libresoc.v:197643.3-197652.6" + process $proc$libresoc.v:197643$13818 assign { } { } assign { } { } assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:198471.5-198471.29" + attribute \src "libresoc.v:197644.5-197644.29" switch \initial - attribute \src "libresoc.v:198471.9-198471.17" + attribute \src "libresoc.v:197644.9-197644.17" case 1'1 case end @@ -413503,14 +408728,14 @@ module \ti sync always update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] end - attribute \src "libresoc.v:198480.3-198488.6" - process $proc$libresoc.v:198480$13877 + attribute \src "libresoc.v:197653.3-197661.6" + process $proc$libresoc.v:197653$13819 assign { } { } assign { } { } - assign $0\d_cr_delay$next[0:0]$13878 $1\d_cr_delay$next[0:0]$13879 - attribute \src "libresoc.v:198481.5-198481.29" + assign $0\d_cr_delay$next[0:0]$13820 $1\d_cr_delay$next[0:0]$13821 + attribute \src "libresoc.v:197654.5-197654.29" switch \initial - attribute \src "libresoc.v:198481.9-198481.17" + attribute \src "libresoc.v:197654.9-197654.17" case 1'1 case end @@ -413519,21 +408744,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_cr_delay$next[0:0]$13879 1'0 + assign $1\d_cr_delay$next[0:0]$13821 1'0 case - assign $1\d_cr_delay$next[0:0]$13879 \dbg_d_cr_req + assign $1\d_cr_delay$next[0:0]$13821 \dbg_d_cr_req end sync always - update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13878 + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13820 end - attribute \src "libresoc.v:198489.3-198498.6" - process $proc$libresoc.v:198489$13880 + attribute \src "libresoc.v:197662.3-197671.6" + process $proc$libresoc.v:197662$13822 assign { } { } assign { } { } assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:198490.5-198490.29" + attribute \src "libresoc.v:197663.5-197663.29" switch \initial - attribute \src "libresoc.v:198490.9-198490.17" + attribute \src "libresoc.v:197663.9-197663.17" case 1'1 case end @@ -413549,14 +408774,14 @@ module \ti sync always update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] end - attribute \src "libresoc.v:198499.3-198508.6" - process $proc$libresoc.v:198499$13881 + attribute \src "libresoc.v:197672.3-197681.6" + process $proc$libresoc.v:197672$13823 assign { } { } assign { } { } assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:198500.5-198500.29" + attribute \src "libresoc.v:197673.5-197673.29" switch \initial - attribute \src "libresoc.v:198500.9-198500.17" + attribute \src "libresoc.v:197673.9-197673.17" case 1'1 case end @@ -413572,14 +408797,14 @@ module \ti sync always update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] end - attribute \src "libresoc.v:198509.3-198518.6" - process $proc$libresoc.v:198509$13882 + attribute \src "libresoc.v:197682.3-197691.6" + process $proc$libresoc.v:197682$13824 assign { } { } assign { } { } assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:198510.5-198510.29" + attribute \src "libresoc.v:197683.5-197683.29" switch \initial - attribute \src "libresoc.v:198510.9-198510.17" + attribute \src "libresoc.v:197683.9-197683.17" case 1'1 case end @@ -413595,14 +408820,14 @@ module \ti sync always update \core_full_rd__ren $0\core_full_rd__ren[2:0] end - attribute \src "libresoc.v:198519.3-198527.6" - process $proc$libresoc.v:198519$13883 + attribute \src "libresoc.v:197692.3-197700.6" + process $proc$libresoc.v:197692$13825 assign { } { } assign { } { } - assign $0\d_xer_delay$next[0:0]$13884 $1\d_xer_delay$next[0:0]$13885 - attribute \src "libresoc.v:198520.5-198520.29" + assign $0\d_xer_delay$next[0:0]$13826 $1\d_xer_delay$next[0:0]$13827 + attribute \src "libresoc.v:197693.5-197693.29" switch \initial - attribute \src "libresoc.v:198520.9-198520.17" + attribute \src "libresoc.v:197693.9-197693.17" case 1'1 case end @@ -413611,21 +408836,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_xer_delay$next[0:0]$13885 1'0 + assign $1\d_xer_delay$next[0:0]$13827 1'0 case - assign $1\d_xer_delay$next[0:0]$13885 \dbg_d_xer_req + assign $1\d_xer_delay$next[0:0]$13827 \dbg_d_xer_req end sync always - update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13884 + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13826 end - attribute \src "libresoc.v:198528.3-198537.6" - process $proc$libresoc.v:198528$13886 + attribute \src "libresoc.v:197701.3-197710.6" + process $proc$libresoc.v:197701$13828 assign { } { } assign { } { } assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:198529.5-198529.29" + attribute \src "libresoc.v:197702.5-197702.29" switch \initial - attribute \src "libresoc.v:198529.9-198529.17" + attribute \src "libresoc.v:197702.9-197702.17" case 1'1 case end @@ -413641,14 +408866,14 @@ module \ti sync always update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] end - attribute \src "libresoc.v:198538.3-198547.6" - process $proc$libresoc.v:198538$13887 + attribute \src "libresoc.v:197711.3-197720.6" + process $proc$libresoc.v:197711$13829 assign { } { } assign { } { } assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:198539.5-198539.29" + attribute \src "libresoc.v:197712.5-197712.29" switch \initial - attribute \src "libresoc.v:198539.9-198539.17" + attribute \src "libresoc.v:197712.9-197712.17" case 1'1 case end @@ -413664,14 +408889,14 @@ module \ti sync always update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] end - attribute \src "libresoc.v:198548.3-198562.6" - process $proc$libresoc.v:198548$13888 + attribute \src "libresoc.v:197721.3-197735.6" + process $proc$libresoc.v:197721$13830 assign { } { } assign { } { } assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] - attribute \src "libresoc.v:198549.5-198549.29" + attribute \src "libresoc.v:197722.5-197722.29" switch \initial - attribute \src "libresoc.v:198549.9-198549.17" + attribute \src "libresoc.v:197722.9-197722.17" case 1'1 case end @@ -413691,14 +408916,14 @@ module \ti sync always update \core_issue__addr $0\core_issue__addr[2:0] end - attribute \src "libresoc.v:198563.3-198577.6" - process $proc$libresoc.v:198563$13889 + attribute \src "libresoc.v:197736.3-197750.6" + process $proc$libresoc.v:197736$13831 assign { } { } assign { } { } assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] - attribute \src "libresoc.v:198564.5-198564.29" + attribute \src "libresoc.v:197737.5-197737.29" switch \initial - attribute \src "libresoc.v:198564.9-198564.17" + attribute \src "libresoc.v:197737.9-197737.17" case 1'1 case end @@ -413718,15 +408943,15 @@ module \ti sync always update \core_issue__ren $0\core_issue__ren[0:0] end - attribute \src "libresoc.v:198578.3-198605.6" - process $proc$libresoc.v:198578$13890 + attribute \src "libresoc.v:197751.3-197778.6" + process $proc$libresoc.v:197751$13832 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[1:0]$13891 $2\fsm_state$next[1:0]$13893 - attribute \src "libresoc.v:198579.5-198579.29" + assign $0\fsm_state$next[1:0]$13833 $2\fsm_state$next[1:0]$13835 + attribute \src "libresoc.v:197752.5-197752.29" switch \initial - attribute \src "libresoc.v:198579.9-198579.17" + attribute \src "libresoc.v:197752.9-197752.17" case 1'1 case end @@ -413735,42 +408960,42 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fsm_state$next[1:0]$13892 2'01 + assign $1\fsm_state$next[1:0]$13834 2'01 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fsm_state$next[1:0]$13892 2'10 + assign $1\fsm_state$next[1:0]$13834 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fsm_state$next[1:0]$13892 2'11 + assign $1\fsm_state$next[1:0]$13834 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fsm_state$next[1:0]$13892 2'00 + assign $1\fsm_state$next[1:0]$13834 2'00 case - assign $1\fsm_state$next[1:0]$13892 \fsm_state + assign $1\fsm_state$next[1:0]$13834 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$next[1:0]$13893 2'00 + assign $2\fsm_state$next[1:0]$13835 2'00 case - assign $2\fsm_state$next[1:0]$13893 $1\fsm_state$next[1:0]$13892 + assign $2\fsm_state$next[1:0]$13835 $1\fsm_state$next[1:0]$13834 end sync always - update \fsm_state$next $0\fsm_state$next[1:0]$13891 + update \fsm_state$next $0\fsm_state$next[1:0]$13833 end - attribute \src "libresoc.v:198606.3-198616.6" - process $proc$libresoc.v:198606$13894 + attribute \src "libresoc.v:197779.3-197789.6" + process $proc$libresoc.v:197779$13836 assign { } { } assign { } { } assign $0\new_dec[63:0] $1\new_dec[63:0] - attribute \src "libresoc.v:198607.5-198607.29" + attribute \src "libresoc.v:197780.5-197780.29" switch \initial - attribute \src "libresoc.v:198607.9-198607.17" + attribute \src "libresoc.v:197780.9-197780.17" case 1'1 case end @@ -413786,14 +409011,14 @@ module \ti sync always update \new_dec $0\new_dec[63:0] end - attribute \src "libresoc.v:198617.3-198631.6" - process $proc$libresoc.v:198617$13895 + attribute \src "libresoc.v:197790.3-197804.6" + process $proc$libresoc.v:197790$13837 assign { } { } assign { } { } - assign $0\core_issue__addr$13[2:0]$13896 $1\core_issue__addr$13[2:0]$13897 - attribute \src "libresoc.v:198618.5-198618.29" + assign $0\core_issue__addr$13[2:0]$13838 $1\core_issue__addr$13[2:0]$13839 + attribute \src "libresoc.v:197791.5-197791.29" switch \initial - attribute \src "libresoc.v:198618.9-198618.17" + attribute \src "libresoc.v:197791.9-197791.17" case 1'1 case end @@ -413802,25 +409027,25 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\core_issue__addr$13[2:0]$13897 3'110 + assign $1\core_issue__addr$13[2:0]$13839 3'110 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\core_issue__addr$13[2:0]$13897 3'111 + assign $1\core_issue__addr$13[2:0]$13839 3'111 case - assign $1\core_issue__addr$13[2:0]$13897 3'000 + assign $1\core_issue__addr$13[2:0]$13839 3'000 end sync always - update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13896 + update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13838 end - attribute \src "libresoc.v:198632.3-198646.6" - process $proc$libresoc.v:198632$13898 + attribute \src "libresoc.v:197805.3-197819.6" + process $proc$libresoc.v:197805$13840 assign { } { } assign { } { } assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] - attribute \src "libresoc.v:198633.5-198633.29" + attribute \src "libresoc.v:197806.5-197806.29" switch \initial - attribute \src "libresoc.v:198633.9-198633.17" + attribute \src "libresoc.v:197806.9-197806.17" case 1'1 case end @@ -413840,14 +409065,14 @@ module \ti sync always update \core_issue__wen $0\core_issue__wen[0:0] end - attribute \src "libresoc.v:198647.3-198661.6" - process $proc$libresoc.v:198647$13899 + attribute \src "libresoc.v:197820.3-197834.6" + process $proc$libresoc.v:197820$13841 assign { } { } assign { } { } assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:198648.5-198648.29" + attribute \src "libresoc.v:197821.5-197821.29" switch \initial - attribute \src "libresoc.v:198648.9-198648.17" + attribute \src "libresoc.v:197821.9-197821.17" case 1'1 case end @@ -413867,15 +409092,15 @@ module \ti sync always update \core_issue__data_i $0\core_issue__data_i[63:0] end - attribute \src "libresoc.v:198662.3-198677.6" - process $proc$libresoc.v:198662$13900 + attribute \src "libresoc.v:197835.3-197850.6" + process $proc$libresoc.v:197835$13842 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_dec$next[63:0]$13901 $2\dec2_cur_dec$next[63:0]$13903 - attribute \src "libresoc.v:198663.5-198663.29" + assign $0\dec2_cur_dec$next[63:0]$13843 $2\dec2_cur_dec$next[63:0]$13845 + attribute \src "libresoc.v:197836.5-197836.29" switch \initial - attribute \src "libresoc.v:198663.9-198663.17" + attribute \src "libresoc.v:197836.9-197836.17" case 1'1 case end @@ -413884,30 +409109,30 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_dec$next[63:0]$13902 \new_dec + assign $1\dec2_cur_dec$next[63:0]$13844 \new_dec case - assign $1\dec2_cur_dec$next[63:0]$13902 \dec2_cur_dec + assign $1\dec2_cur_dec$next[63:0]$13844 \dec2_cur_dec end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_dec$next[63:0]$13903 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\dec2_cur_dec$next[63:0]$13845 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\dec2_cur_dec$next[63:0]$13903 $1\dec2_cur_dec$next[63:0]$13902 + assign $2\dec2_cur_dec$next[63:0]$13845 $1\dec2_cur_dec$next[63:0]$13844 end sync always - update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13901 + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13843 end - attribute \src "libresoc.v:198678.3-198688.6" - process $proc$libresoc.v:198678$13904 + attribute \src "libresoc.v:197851.3-197861.6" + process $proc$libresoc.v:197851$13846 assign { } { } assign { } { } assign $0\new_tb[63:0] $1\new_tb[63:0] - attribute \src "libresoc.v:198679.5-198679.29" + attribute \src "libresoc.v:197852.5-197852.29" switch \initial - attribute \src "libresoc.v:198679.9-198679.17" + attribute \src "libresoc.v:197852.9-197852.17" case 1'1 case end @@ -413923,14 +409148,14 @@ module \ti sync always update \new_tb $0\new_tb[63:0] end - attribute \src "libresoc.v:198689.3-198697.6" - process $proc$libresoc.v:198689$13905 + attribute \src "libresoc.v:197862.3-197870.6" + process $proc$libresoc.v:197862$13847 assign { } { } assign { } { } - assign $0\dbg_dmi_we_i$next[0:0]$13906 $1\dbg_dmi_we_i$next[0:0]$13907 - attribute \src "libresoc.v:198690.5-198690.29" + assign $0\dbg_dmi_we_i$next[0:0]$13848 $1\dbg_dmi_we_i$next[0:0]$13849 + attribute \src "libresoc.v:197863.5-197863.29" switch \initial - attribute \src "libresoc.v:198690.9-198690.17" + attribute \src "libresoc.v:197863.9-197863.17" case 1'1 case end @@ -413939,21 +409164,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_we_i$next[0:0]$13907 1'0 + assign $1\dbg_dmi_we_i$next[0:0]$13849 1'0 case - assign $1\dbg_dmi_we_i$next[0:0]$13907 \jtag_dmi0__we_i + assign $1\dbg_dmi_we_i$next[0:0]$13849 \jtag_dmi0__we_i end sync always - update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13906 + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13848 end - attribute \src "libresoc.v:198698.3-198706.6" - process $proc$libresoc.v:198698$13908 + attribute \src "libresoc.v:197871.3-197879.6" + process $proc$libresoc.v:197871$13850 assign { } { } assign { } { } - assign $0\pc_ok_delay$next[0:0]$13909 $1\pc_ok_delay$next[0:0]$13910 - attribute \src "libresoc.v:198699.5-198699.29" + assign $0\pc_ok_delay$next[0:0]$13851 $1\pc_ok_delay$next[0:0]$13852 + attribute \src "libresoc.v:197872.5-197872.29" switch \initial - attribute \src "libresoc.v:198699.9-198699.17" + attribute \src "libresoc.v:197872.9-197872.17" case 1'1 case end @@ -413962,22 +409187,22 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\pc_ok_delay$next[0:0]$13910 1'0 + assign $1\pc_ok_delay$next[0:0]$13852 1'0 case - assign $1\pc_ok_delay$next[0:0]$13910 \$38 + assign $1\pc_ok_delay$next[0:0]$13852 \$38 end sync always - update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13909 + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13851 end - attribute \src "libresoc.v:198707.3-198722.6" - process $proc$libresoc.v:198707$13911 + attribute \src "libresoc.v:197880.3-197895.6" + process $proc$libresoc.v:197880$13853 assign { } { } assign { } { } assign { } { } assign $0\pc[63:0] $2\pc[63:0] - attribute \src "libresoc.v:198708.5-198708.29" + attribute \src "libresoc.v:197881.5-197881.29" switch \initial - attribute \src "libresoc.v:198708.9-198708.17" + attribute \src "libresoc.v:197881.9-197881.17" case 1'1 case end @@ -414002,14 +409227,14 @@ module \ti sync always update \pc $0\pc[63:0] end - attribute \src "libresoc.v:198723.3-198735.6" - process $proc$libresoc.v:198723$13912 + attribute \src "libresoc.v:197896.3-197908.6" + process $proc$libresoc.v:197896$13854 assign { } { } assign { } { } assign $0\core_cia__ren[2:0] $1\core_cia__ren[2:0] - attribute \src "libresoc.v:198724.5-198724.29" + attribute \src "libresoc.v:197897.5-197897.29" switch \initial - attribute \src "libresoc.v:198724.9-198724.17" + attribute \src "libresoc.v:197897.9-197897.17" case 1'1 case end @@ -414026,14 +409251,14 @@ module \ti sync always update \core_cia__ren $0\core_cia__ren[2:0] end - attribute \src "libresoc.v:198736.3-198744.6" - process $proc$libresoc.v:198736$13913 + attribute \src "libresoc.v:197909.3-197917.6" + process $proc$libresoc.v:197909$13855 assign { } { } assign { } { } - assign $0\svstate_ok_delay$next[0:0]$13914 $1\svstate_ok_delay$next[0:0]$13915 - attribute \src "libresoc.v:198737.5-198737.29" + assign $0\svstate_ok_delay$next[0:0]$13856 $1\svstate_ok_delay$next[0:0]$13857 + attribute \src "libresoc.v:197910.5-197910.29" switch \initial - attribute \src "libresoc.v:198737.9-198737.17" + attribute \src "libresoc.v:197910.9-197910.17" case 1'1 case end @@ -414042,22 +409267,22 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\svstate_ok_delay$next[0:0]$13915 1'0 + assign $1\svstate_ok_delay$next[0:0]$13857 1'0 case - assign $1\svstate_ok_delay$next[0:0]$13915 \$40 + assign $1\svstate_ok_delay$next[0:0]$13857 \$40 end sync always - update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13914 + update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13856 end - attribute \src "libresoc.v:198745.3-198760.6" - process $proc$libresoc.v:198745$13916 + attribute \src "libresoc.v:197918.3-197933.6" + process $proc$libresoc.v:197918$13858 assign { } { } assign { } { } assign { } { } assign $0\svstate[63:0] $2\svstate[63:0] - attribute \src "libresoc.v:198746.5-198746.29" + attribute \src "libresoc.v:197919.5-197919.29" switch \initial - attribute \src "libresoc.v:198746.9-198746.17" + attribute \src "libresoc.v:197919.9-197919.17" case 1'1 case end @@ -414082,14 +409307,14 @@ module \ti sync always update \svstate $0\svstate[63:0] end - attribute \src "libresoc.v:198761.3-198773.6" - process $proc$libresoc.v:198761$13917 + attribute \src "libresoc.v:197934.3-197946.6" + process $proc$libresoc.v:197934$13859 assign { } { } assign { } { } assign $0\core_sv__ren[2:0] $1\core_sv__ren[2:0] - attribute \src "libresoc.v:198762.5-198762.29" + attribute \src "libresoc.v:197935.5-197935.29" switch \initial - attribute \src "libresoc.v:198762.9-198762.17" + attribute \src "libresoc.v:197935.9-197935.17" case 1'1 case end @@ -414106,37 +409331,14 @@ module \ti sync always update \core_sv__ren $0\core_sv__ren[2:0] end - attribute \src "libresoc.v:198774.3-198782.6" - process $proc$libresoc.v:198774$13918 - assign { } { } - assign { } { } - assign $0\dbg_dmi_din$next[63:0]$13919 $1\dbg_dmi_din$next[63:0]$13920 - attribute \src "libresoc.v:198775.5-198775.29" - switch \initial - attribute \src "libresoc.v:198775.9-198775.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbg_dmi_din$next[63:0]$13920 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $1\dbg_dmi_din$next[63:0]$13920 \jtag_dmi0__din - end - sync always - update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13919 - end - attribute \src "libresoc.v:198783.3-198850.6" - process $proc$libresoc.v:198783$13921 + attribute \src "libresoc.v:197947.3-198014.6" + process $proc$libresoc.v:197947$13860 assign { } { } assign { } { } assign $0\core_wen[2:0] $1\core_wen[2:0] - attribute \src "libresoc.v:198784.5-198784.29" + attribute \src "libresoc.v:197948.5-197948.29" switch \initial - attribute \src "libresoc.v:198784.9-198784.17" + attribute \src "libresoc.v:197948.9-197948.17" case 1'1 case end @@ -414238,14 +409440,14 @@ module \ti sync always update \core_wen $0\core_wen[2:0] end - attribute \src "libresoc.v:198851.3-198918.6" - process $proc$libresoc.v:198851$13922 + attribute \src "libresoc.v:198015.3-198082.6" + process $proc$libresoc.v:198015$13861 assign { } { } assign { } { } assign $0\core_data_i[63:0] $1\core_data_i[63:0] - attribute \src "libresoc.v:198852.5-198852.29" + attribute \src "libresoc.v:198016.5-198016.29" switch \initial - attribute \src "libresoc.v:198852.9-198852.17" + attribute \src "libresoc.v:198016.9-198016.17" case 1'1 case end @@ -414347,14 +409549,14 @@ module \ti sync always update \core_data_i $0\core_data_i[63:0] end - attribute \src "libresoc.v:198919.3-198934.6" - process $proc$libresoc.v:198919$13923 + attribute \src "libresoc.v:198083.3-198098.6" + process $proc$libresoc.v:198083$13862 assign { } { } assign { } { } assign $0\core_msr__ren[2:0] $1\core_msr__ren[2:0] - attribute \src "libresoc.v:198920.5-198920.29" + attribute \src "libresoc.v:198084.5-198084.29" switch \initial - attribute \src "libresoc.v:198920.9-198920.17" + attribute \src "libresoc.v:198084.9-198084.17" case 1'1 case end @@ -414379,14 +409581,14 @@ module \ti sync always update \core_msr__ren $0\core_msr__ren[2:0] end - attribute \src "libresoc.v:198935.3-198943.6" - process $proc$libresoc.v:198935$13924 + attribute \src "libresoc.v:198099.3-198107.6" + process $proc$libresoc.v:198099$13863 assign { } { } assign { } { } - assign $0\jtag_dmi0__ack_o$next[0:0]$13925 $1\jtag_dmi0__ack_o$next[0:0]$13926 - attribute \src "libresoc.v:198936.5-198936.29" + assign $0\dbg_dmi_din$next[63:0]$13864 $1\dbg_dmi_din$next[63:0]$13865 + attribute \src "libresoc.v:198100.5-198100.29" switch \initial - attribute \src "libresoc.v:198936.9-198936.17" + attribute \src "libresoc.v:198100.9-198100.17" case 1'1 case end @@ -414395,21 +409597,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_dmi0__ack_o$next[0:0]$13926 1'0 + assign $1\dbg_dmi_din$next[63:0]$13865 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\jtag_dmi0__ack_o$next[0:0]$13926 \dbg_dmi_ack_o + assign $1\dbg_dmi_din$next[63:0]$13865 \jtag_dmi0__din end sync always - update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13925 + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13864 end - attribute \src "libresoc.v:198944.3-198954.6" - process $proc$libresoc.v:198944$13927 + attribute \src "libresoc.v:198108.3-198118.6" + process $proc$libresoc.v:198108$13866 assign { } { } assign { } { } assign $0\fetch_pc_ready_o[0:0] $1\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:198945.5-198945.29" + attribute \src "libresoc.v:198109.5-198109.29" switch \initial - attribute \src "libresoc.v:198945.9-198945.17" + attribute \src "libresoc.v:198109.9-198109.17" case 1'1 case end @@ -414425,14 +409627,14 @@ module \ti sync always update \fetch_pc_ready_o $0\fetch_pc_ready_o[0:0] end - attribute \src "libresoc.v:198955.3-198970.6" - process $proc$libresoc.v:198955$13928 + attribute \src "libresoc.v:198119.3-198134.6" + process $proc$libresoc.v:198119$13867 assign { } { } assign { } { } assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:198956.5-198956.29" + attribute \src "libresoc.v:198120.5-198120.29" switch \initial - attribute \src "libresoc.v:198956.9-198956.17" + attribute \src "libresoc.v:198120.9-198120.17" case 1'1 case end @@ -414457,14 +409659,37 @@ module \ti sync always update \imem_a_pc_i $0\imem_a_pc_i[47:0] end - attribute \src "libresoc.v:198971.3-199004.6" - process $proc$libresoc.v:198971$13929 + attribute \src "libresoc.v:198135.3-198143.6" + process $proc$libresoc.v:198135$13868 + assign { } { } + assign { } { } + assign $0\jtag_dmi0__ack_o$next[0:0]$13869 $1\jtag_dmi0__ack_o$next[0:0]$13870 + attribute \src "libresoc.v:198136.5-198136.29" + switch \initial + attribute \src "libresoc.v:198136.9-198136.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0__ack_o$next[0:0]$13870 1'0 + case + assign $1\jtag_dmi0__ack_o$next[0:0]$13870 \dbg_dmi_ack_o + end + sync always + update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13869 + end + attribute \src "libresoc.v:198144.3-198177.6" + process $proc$libresoc.v:198144$13871 assign { } { } assign { } { } assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:198972.5-198972.29" + attribute \src "libresoc.v:198145.5-198145.29" switch \initial - attribute \src "libresoc.v:198972.9-198972.17" + attribute \src "libresoc.v:198145.9-198145.17" case 1'1 case end @@ -414515,14 +409740,14 @@ module \ti sync always update \imem_a_valid_i $0\imem_a_valid_i[0:0] end - attribute \src "libresoc.v:199005.3-199038.6" - process $proc$libresoc.v:199005$13930 + attribute \src "libresoc.v:198178.3-198211.6" + process $proc$libresoc.v:198178$13872 assign { } { } assign { } { } assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:199006.5-199006.29" + attribute \src "libresoc.v:198179.5-198179.29" switch \initial - attribute \src "libresoc.v:199006.9-199006.17" + attribute \src "libresoc.v:198179.9-198179.17" case 1'1 case end @@ -414573,15 +409798,15 @@ module \ti sync always update \imem_f_valid_i $0\imem_f_valid_i[0:0] end - attribute \src "libresoc.v:199039.3-199059.6" - process $proc$libresoc.v:199039$13931 + attribute \src "libresoc.v:198212.3-198232.6" + process $proc$libresoc.v:198212$13873 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_pc$next[63:0]$13932 $3\dec2_cur_pc$next[63:0]$13935 - attribute \src "libresoc.v:199040.5-199040.29" + assign $0\dec2_cur_pc$next[63:0]$13874 $3\dec2_cur_pc$next[63:0]$13877 + attribute \src "libresoc.v:198213.5-198213.29" switch \initial - attribute \src "libresoc.v:199040.9-199040.17" + attribute \src "libresoc.v:198213.9-198213.17" case 1'1 case end @@ -414590,33 +409815,33 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec2_cur_pc$next[63:0]$13933 $2\dec2_cur_pc$next[63:0]$13934 + assign $1\dec2_cur_pc$next[63:0]$13875 $2\dec2_cur_pc$next[63:0]$13876 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_pc$next[63:0]$13934 \pc + assign $2\dec2_cur_pc$next[63:0]$13876 \pc case - assign $2\dec2_cur_pc$next[63:0]$13934 \dec2_cur_pc + assign $2\dec2_cur_pc$next[63:0]$13876 \dec2_cur_pc end case - assign $1\dec2_cur_pc$next[63:0]$13933 \dec2_cur_pc + assign $1\dec2_cur_pc$next[63:0]$13875 \dec2_cur_pc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_pc$next[63:0]$13935 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec2_cur_pc$next[63:0]$13877 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dec2_cur_pc$next[63:0]$13935 $1\dec2_cur_pc$next[63:0]$13933 + assign $3\dec2_cur_pc$next[63:0]$13877 $1\dec2_cur_pc$next[63:0]$13875 end sync always - update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13932 + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13874 end - attribute \src "libresoc.v:199060.3-199098.6" - process $proc$libresoc.v:199060$13936 + attribute \src "libresoc.v:198233.3-198271.6" + process $proc$libresoc.v:198233$13878 assign { } { } assign { } { } assign { } { } @@ -414641,15 +409866,15 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\cur_cur_dststep$next[6:0]$13937 $4\cur_cur_dststep$next[6:0]$13961 - assign $0\cur_cur_maxvl$next[6:0]$13938 $4\cur_cur_maxvl$next[6:0]$13962 - assign $0\cur_cur_srcstep$next[6:0]$13939 $4\cur_cur_srcstep$next[6:0]$13963 - assign $0\cur_cur_subvl$next[1:0]$13940 $4\cur_cur_subvl$next[1:0]$13964 - assign $0\cur_cur_svstep$next[1:0]$13941 $4\cur_cur_svstep$next[1:0]$13965 - assign $0\cur_cur_vl$next[6:0]$13942 $4\cur_cur_vl$next[6:0]$13966 - attribute \src "libresoc.v:199061.5-199061.29" + assign $0\cur_cur_dststep$next[6:0]$13879 $4\cur_cur_dststep$next[6:0]$13903 + assign $0\cur_cur_maxvl$next[6:0]$13880 $4\cur_cur_maxvl$next[6:0]$13904 + assign $0\cur_cur_srcstep$next[6:0]$13881 $4\cur_cur_srcstep$next[6:0]$13905 + assign $0\cur_cur_subvl$next[1:0]$13882 $4\cur_cur_subvl$next[1:0]$13906 + assign $0\cur_cur_svstep$next[1:0]$13883 $4\cur_cur_svstep$next[1:0]$13907 + assign $0\cur_cur_vl$next[6:0]$13884 $4\cur_cur_vl$next[6:0]$13908 + attribute \src "libresoc.v:198234.5-198234.29" switch \initial - attribute \src "libresoc.v:199061.9-199061.17" + attribute \src "libresoc.v:198234.9-198234.17" case 1'1 case end @@ -414663,12 +409888,12 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\cur_cur_dststep$next[6:0]$13943 $2\cur_cur_dststep$next[6:0]$13949 - assign $1\cur_cur_maxvl$next[6:0]$13944 $2\cur_cur_maxvl$next[6:0]$13950 - assign $1\cur_cur_srcstep$next[6:0]$13945 $2\cur_cur_srcstep$next[6:0]$13951 - assign $1\cur_cur_subvl$next[1:0]$13946 $2\cur_cur_subvl$next[1:0]$13952 - assign $1\cur_cur_svstep$next[1:0]$13947 $2\cur_cur_svstep$next[1:0]$13953 - assign $1\cur_cur_vl$next[6:0]$13948 $2\cur_cur_vl$next[6:0]$13954 + assign $1\cur_cur_dststep$next[6:0]$13885 $2\cur_cur_dststep$next[6:0]$13891 + assign $1\cur_cur_maxvl$next[6:0]$13886 $2\cur_cur_maxvl$next[6:0]$13892 + assign $1\cur_cur_srcstep$next[6:0]$13887 $2\cur_cur_srcstep$next[6:0]$13893 + assign $1\cur_cur_subvl$next[1:0]$13888 $2\cur_cur_subvl$next[1:0]$13894 + assign $1\cur_cur_svstep$next[1:0]$13889 $2\cur_cur_svstep$next[1:0]$13895 + assign $1\cur_cur_vl$next[6:0]$13890 $2\cur_cur_vl$next[6:0]$13896 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" @@ -414679,22 +409904,22 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\cur_cur_maxvl$next[6:0]$13950 $2\cur_cur_vl$next[6:0]$13954 $2\cur_cur_srcstep$next[6:0]$13951 $2\cur_cur_dststep$next[6:0]$13949 $2\cur_cur_subvl$next[1:0]$13952 $2\cur_cur_svstep$next[1:0]$13953 } \svstate [31:0] + assign { $2\cur_cur_maxvl$next[6:0]$13892 $2\cur_cur_vl$next[6:0]$13896 $2\cur_cur_srcstep$next[6:0]$13893 $2\cur_cur_dststep$next[6:0]$13891 $2\cur_cur_subvl$next[1:0]$13894 $2\cur_cur_svstep$next[1:0]$13895 } \svstate [31:0] case - assign $2\cur_cur_dststep$next[6:0]$13949 \cur_cur_dststep - assign $2\cur_cur_maxvl$next[6:0]$13950 \cur_cur_maxvl - assign $2\cur_cur_srcstep$next[6:0]$13951 \cur_cur_srcstep - assign $2\cur_cur_subvl$next[1:0]$13952 \cur_cur_subvl - assign $2\cur_cur_svstep$next[1:0]$13953 \cur_cur_svstep - assign $2\cur_cur_vl$next[6:0]$13954 \cur_cur_vl + assign $2\cur_cur_dststep$next[6:0]$13891 \cur_cur_dststep + assign $2\cur_cur_maxvl$next[6:0]$13892 \cur_cur_maxvl + assign $2\cur_cur_srcstep$next[6:0]$13893 \cur_cur_srcstep + assign $2\cur_cur_subvl$next[1:0]$13894 \cur_cur_subvl + assign $2\cur_cur_svstep$next[1:0]$13895 \cur_cur_svstep + assign $2\cur_cur_vl$next[6:0]$13896 \cur_cur_vl end case - assign $1\cur_cur_dststep$next[6:0]$13943 \cur_cur_dststep - assign $1\cur_cur_maxvl$next[6:0]$13944 \cur_cur_maxvl - assign $1\cur_cur_srcstep$next[6:0]$13945 \cur_cur_srcstep - assign $1\cur_cur_subvl$next[1:0]$13946 \cur_cur_subvl - assign $1\cur_cur_svstep$next[1:0]$13947 \cur_cur_svstep - assign $1\cur_cur_vl$next[6:0]$13948 \cur_cur_vl + assign $1\cur_cur_dststep$next[6:0]$13885 \cur_cur_dststep + assign $1\cur_cur_maxvl$next[6:0]$13886 \cur_cur_maxvl + assign $1\cur_cur_srcstep$next[6:0]$13887 \cur_cur_srcstep + assign $1\cur_cur_subvl$next[1:0]$13888 \cur_cur_subvl + assign $1\cur_cur_svstep$next[1:0]$13889 \cur_cur_svstep + assign $1\cur_cur_vl$next[6:0]$13890 \cur_cur_vl end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" switch \update_svstate @@ -414706,14 +409931,14 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $3\cur_cur_maxvl$next[6:0]$13956 $3\cur_cur_vl$next[6:0]$13960 $3\cur_cur_srcstep$next[6:0]$13957 $3\cur_cur_dststep$next[6:0]$13955 $3\cur_cur_subvl$next[1:0]$13958 $3\cur_cur_svstep$next[1:0]$13959 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } + assign { $3\cur_cur_maxvl$next[6:0]$13898 $3\cur_cur_vl$next[6:0]$13902 $3\cur_cur_srcstep$next[6:0]$13899 $3\cur_cur_dststep$next[6:0]$13897 $3\cur_cur_subvl$next[1:0]$13900 $3\cur_cur_svstep$next[1:0]$13901 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } case - assign $3\cur_cur_dststep$next[6:0]$13955 $1\cur_cur_dststep$next[6:0]$13943 - assign $3\cur_cur_maxvl$next[6:0]$13956 $1\cur_cur_maxvl$next[6:0]$13944 - assign $3\cur_cur_srcstep$next[6:0]$13957 $1\cur_cur_srcstep$next[6:0]$13945 - assign $3\cur_cur_subvl$next[1:0]$13958 $1\cur_cur_subvl$next[1:0]$13946 - assign $3\cur_cur_svstep$next[1:0]$13959 $1\cur_cur_svstep$next[1:0]$13947 - assign $3\cur_cur_vl$next[6:0]$13960 $1\cur_cur_vl$next[6:0]$13948 + assign $3\cur_cur_dststep$next[6:0]$13897 $1\cur_cur_dststep$next[6:0]$13885 + assign $3\cur_cur_maxvl$next[6:0]$13898 $1\cur_cur_maxvl$next[6:0]$13886 + assign $3\cur_cur_srcstep$next[6:0]$13899 $1\cur_cur_srcstep$next[6:0]$13887 + assign $3\cur_cur_subvl$next[1:0]$13900 $1\cur_cur_subvl$next[1:0]$13888 + assign $3\cur_cur_svstep$next[1:0]$13901 $1\cur_cur_svstep$next[1:0]$13889 + assign $3\cur_cur_vl$next[6:0]$13902 $1\cur_cur_vl$next[6:0]$13890 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -414725,60 +409950,37 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $4\cur_cur_svstep$next[1:0]$13965 2'00 - assign $4\cur_cur_subvl$next[1:0]$13964 2'00 - assign $4\cur_cur_dststep$next[6:0]$13961 7'0000000 - assign $4\cur_cur_srcstep$next[6:0]$13963 7'0000000 - assign $4\cur_cur_vl$next[6:0]$13966 7'0000000 - assign $4\cur_cur_maxvl$next[6:0]$13962 7'0000000 + assign $4\cur_cur_svstep$next[1:0]$13907 2'00 + assign $4\cur_cur_subvl$next[1:0]$13906 2'00 + assign $4\cur_cur_dststep$next[6:0]$13903 7'0000000 + assign $4\cur_cur_srcstep$next[6:0]$13905 7'0000000 + assign $4\cur_cur_vl$next[6:0]$13908 7'0000000 + assign $4\cur_cur_maxvl$next[6:0]$13904 7'0000000 case - assign $4\cur_cur_dststep$next[6:0]$13961 $3\cur_cur_dststep$next[6:0]$13955 - assign $4\cur_cur_maxvl$next[6:0]$13962 $3\cur_cur_maxvl$next[6:0]$13956 - assign $4\cur_cur_srcstep$next[6:0]$13963 $3\cur_cur_srcstep$next[6:0]$13957 - assign $4\cur_cur_subvl$next[1:0]$13964 $3\cur_cur_subvl$next[1:0]$13958 - assign $4\cur_cur_svstep$next[1:0]$13965 $3\cur_cur_svstep$next[1:0]$13959 - assign $4\cur_cur_vl$next[6:0]$13966 $3\cur_cur_vl$next[6:0]$13960 + assign $4\cur_cur_dststep$next[6:0]$13903 $3\cur_cur_dststep$next[6:0]$13897 + assign $4\cur_cur_maxvl$next[6:0]$13904 $3\cur_cur_maxvl$next[6:0]$13898 + assign $4\cur_cur_srcstep$next[6:0]$13905 $3\cur_cur_srcstep$next[6:0]$13899 + assign $4\cur_cur_subvl$next[1:0]$13906 $3\cur_cur_subvl$next[1:0]$13900 + assign $4\cur_cur_svstep$next[1:0]$13907 $3\cur_cur_svstep$next[1:0]$13901 + assign $4\cur_cur_vl$next[6:0]$13908 $3\cur_cur_vl$next[6:0]$13902 end sync always - update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13937 - update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13938 - update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13939 - update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13940 - update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13941 - update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13942 + update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13879 + update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13880 + update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13881 + update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13882 + update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13883 + update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13884 end - attribute \src "libresoc.v:199099.3-199107.6" - process $proc$libresoc.v:199099$13967 - assign { } { } - assign { } { } - assign $0\jtag_dmi0__dout$next[63:0]$13968 $1\jtag_dmi0__dout$next[63:0]$13969 - attribute \src "libresoc.v:199100.5-199100.29" - switch \initial - attribute \src "libresoc.v:199100.9-199100.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_dmi0__dout$next[63:0]$13969 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $1\jtag_dmi0__dout$next[63:0]$13969 \dbg_dmi_dout - end - sync always - update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13968 - end - attribute \src "libresoc.v:199108.3-199137.6" - process $proc$libresoc.v:199108$13970 + attribute \src "libresoc.v:198272.3-198301.6" + process $proc$libresoc.v:198272$13909 assign { } { } assign { } { } assign { } { } - assign $0\msr_read$next[0:0]$13971 $4\msr_read$next[0:0]$13975 - attribute \src "libresoc.v:199109.5-199109.29" + assign $0\msr_read$next[0:0]$13910 $4\msr_read$next[0:0]$13914 + attribute \src "libresoc.v:198273.5-198273.29" switch \initial - attribute \src "libresoc.v:199109.9-199109.17" + attribute \src "libresoc.v:198273.9-198273.17" case 1'1 case end @@ -414787,53 +409989,76 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\msr_read$next[0:0]$13972 $2\msr_read$next[0:0]$13973 + assign $1\msr_read$next[0:0]$13911 $2\msr_read$next[0:0]$13912 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr_read$next[0:0]$13973 1'0 + assign $2\msr_read$next[0:0]$13912 1'0 case - assign $2\msr_read$next[0:0]$13973 \msr_read + assign $2\msr_read$next[0:0]$13912 \msr_read end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\msr_read$next[0:0]$13972 $3\msr_read$next[0:0]$13974 + assign $1\msr_read$next[0:0]$13911 $3\msr_read$next[0:0]$13913 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" switch \$88 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr_read$next[0:0]$13974 1'1 + assign $3\msr_read$next[0:0]$13913 1'1 case - assign $3\msr_read$next[0:0]$13974 \msr_read + assign $3\msr_read$next[0:0]$13913 \msr_read end case - assign $1\msr_read$next[0:0]$13972 \msr_read + assign $1\msr_read$next[0:0]$13911 \msr_read end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr_read$next[0:0]$13975 1'1 + assign $4\msr_read$next[0:0]$13914 1'1 case - assign $4\msr_read$next[0:0]$13975 $1\msr_read$next[0:0]$13972 + assign $4\msr_read$next[0:0]$13914 $1\msr_read$next[0:0]$13911 end sync always - update \msr_read$next $0\msr_read$next[0:0]$13971 + update \msr_read$next $0\msr_read$next[0:0]$13910 end - attribute \src "libresoc.v:199138.3-199191.6" - process $proc$libresoc.v:199138$13976 + attribute \src "libresoc.v:198302.3-198310.6" + process $proc$libresoc.v:198302$13915 + assign { } { } + assign { } { } + assign $0\jtag_dmi0__dout$next[63:0]$13916 $1\jtag_dmi0__dout$next[63:0]$13917 + attribute \src "libresoc.v:198303.5-198303.29" + switch \initial + attribute \src "libresoc.v:198303.9-198303.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0__dout$next[63:0]$13917 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\jtag_dmi0__dout$next[63:0]$13917 \dbg_dmi_dout + end + sync always + update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13916 + end + attribute \src "libresoc.v:198311.3-198364.6" + process $proc$libresoc.v:198311$13918 assign { } { } assign { } { } assign { } { } - assign $0\fetch_fsm_state$next[1:0]$13977 $6\fetch_fsm_state$next[1:0]$13983 - attribute \src "libresoc.v:199139.5-199139.29" + assign $0\fetch_fsm_state$next[1:0]$13919 $6\fetch_fsm_state$next[1:0]$13925 + attribute \src "libresoc.v:198312.5-198312.29" switch \initial - attribute \src "libresoc.v:199139.9-199139.17" + attribute \src "libresoc.v:198312.9-198312.17" case 1'1 case end @@ -414842,81 +410067,81 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13978 $2\fetch_fsm_state$next[1:0]$13979 + assign $1\fetch_fsm_state$next[1:0]$13920 $2\fetch_fsm_state$next[1:0]$13921 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fetch_fsm_state$next[1:0]$13979 2'01 + assign $2\fetch_fsm_state$next[1:0]$13921 2'01 case - assign $2\fetch_fsm_state$next[1:0]$13979 \fetch_fsm_state + assign $2\fetch_fsm_state$next[1:0]$13921 \fetch_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13978 $3\fetch_fsm_state$next[1:0]$13980 + assign $1\fetch_fsm_state$next[1:0]$13920 $3\fetch_fsm_state$next[1:0]$13922 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $3\fetch_fsm_state$next[1:0]$13980 \fetch_fsm_state + assign $3\fetch_fsm_state$next[1:0]$13922 \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $3\fetch_fsm_state$next[1:0]$13980 2'10 + assign $3\fetch_fsm_state$next[1:0]$13922 2'10 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13978 $4\fetch_fsm_state$next[1:0]$13981 + assign $1\fetch_fsm_state$next[1:0]$13920 $4\fetch_fsm_state$next[1:0]$13923 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\fetch_fsm_state$next[1:0]$13981 \fetch_fsm_state + assign $4\fetch_fsm_state$next[1:0]$13923 \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\fetch_fsm_state$next[1:0]$13981 2'10 + assign $4\fetch_fsm_state$next[1:0]$13923 2'10 end attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13978 $5\fetch_fsm_state$next[1:0]$13982 + assign $1\fetch_fsm_state$next[1:0]$13920 $5\fetch_fsm_state$next[1:0]$13924 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:371" switch \fetch_insn_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fetch_fsm_state$next[1:0]$13982 2'00 + assign $5\fetch_fsm_state$next[1:0]$13924 2'00 case - assign $5\fetch_fsm_state$next[1:0]$13982 \fetch_fsm_state + assign $5\fetch_fsm_state$next[1:0]$13924 \fetch_fsm_state end case - assign $1\fetch_fsm_state$next[1:0]$13978 \fetch_fsm_state + assign $1\fetch_fsm_state$next[1:0]$13920 \fetch_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\fetch_fsm_state$next[1:0]$13983 2'00 + assign $6\fetch_fsm_state$next[1:0]$13925 2'00 case - assign $6\fetch_fsm_state$next[1:0]$13983 $1\fetch_fsm_state$next[1:0]$13978 + assign $6\fetch_fsm_state$next[1:0]$13925 $1\fetch_fsm_state$next[1:0]$13920 end sync always - update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13977 + update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13919 end - attribute \src "libresoc.v:199192.3-199212.6" - process $proc$libresoc.v:199192$13984 + attribute \src "libresoc.v:198365.3-198385.6" + process $proc$libresoc.v:198365$13926 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_msr$next[63:0]$13985 $3\dec2_cur_msr$next[63:0]$13988 - attribute \src "libresoc.v:199193.5-199193.29" + assign $0\dec2_cur_msr$next[63:0]$13927 $3\dec2_cur_msr$next[63:0]$13930 + attribute \src "libresoc.v:198366.5-198366.29" switch \initial - attribute \src "libresoc.v:199193.9-199193.17" + attribute \src "libresoc.v:198366.9-198366.17" case 1'1 case end @@ -414925,39 +410150,39 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_msr$next[63:0]$13986 $2\dec2_cur_msr$next[63:0]$13987 + assign $1\dec2_cur_msr$next[63:0]$13928 $2\dec2_cur_msr$next[63:0]$13929 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" switch \$90 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_msr$next[63:0]$13987 \core_msr__data_o + assign $2\dec2_cur_msr$next[63:0]$13929 \core_msr__data_o case - assign $2\dec2_cur_msr$next[63:0]$13987 \dec2_cur_msr + assign $2\dec2_cur_msr$next[63:0]$13929 \dec2_cur_msr end case - assign $1\dec2_cur_msr$next[63:0]$13986 \dec2_cur_msr + assign $1\dec2_cur_msr$next[63:0]$13928 \dec2_cur_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_msr$next[63:0]$13988 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec2_cur_msr$next[63:0]$13930 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dec2_cur_msr$next[63:0]$13988 $1\dec2_cur_msr$next[63:0]$13986 + assign $3\dec2_cur_msr$next[63:0]$13930 $1\dec2_cur_msr$next[63:0]$13928 end sync always - update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13985 + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13927 end - attribute \src "libresoc.v:199213.3-199231.6" - process $proc$libresoc.v:199213$13989 + attribute \src "libresoc.v:198386.3-198404.6" + process $proc$libresoc.v:198386$13931 assign { } { } assign { } { } - assign $0\nia$next[63:0]$13990 $1\nia$next[63:0]$13991 - attribute \src "libresoc.v:199214.5-199214.29" + assign $0\nia$next[63:0]$13932 $1\nia$next[63:0]$13933 + attribute \src "libresoc.v:198387.5-198387.29" switch \initial - attribute \src "libresoc.v:199214.9-199214.17" + attribute \src "libresoc.v:198387.9-198387.17" case 1'1 case end @@ -414966,31 +410191,31 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\nia$next[63:0]$13991 $2\nia$next[63:0]$13992 + assign $1\nia$next[63:0]$13933 $2\nia$next[63:0]$13934 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\nia$next[63:0]$13992 \nia + assign $2\nia$next[63:0]$13934 \nia attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\nia$next[63:0]$13992 \$92 [63:0] + assign $2\nia$next[63:0]$13934 \$92 [63:0] end case - assign $1\nia$next[63:0]$13991 \nia + assign $1\nia$next[63:0]$13933 \nia end sync always - update \nia$next $0\nia$next[63:0]$13990 + update \nia$next $0\nia$next[63:0]$13932 end - attribute \src "libresoc.v:199232.3-199262.6" - process $proc$libresoc.v:199232$13993 + attribute \src "libresoc.v:198405.3-198435.6" + process $proc$libresoc.v:198405$13935 assign { } { } assign { } { } - assign $0\dec2_raw_opcode_in$next[31:0]$13994 $1\dec2_raw_opcode_in$next[31:0]$13995 - attribute \src "libresoc.v:199233.5-199233.29" + assign $0\dec2_raw_opcode_in$next[31:0]$13936 $1\dec2_raw_opcode_in$next[31:0]$13937 + attribute \src "libresoc.v:198406.5-198406.29" switch \initial - attribute \src "libresoc.v:199233.9-199233.17" + attribute \src "libresoc.v:198406.9-198406.17" case 1'1 case end @@ -414999,45 +410224,45 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_raw_opcode_in$next[31:0]$13995 $2\dec2_raw_opcode_in$next[31:0]$13996 + assign $1\dec2_raw_opcode_in$next[31:0]$13937 $2\dec2_raw_opcode_in$next[31:0]$13938 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\dec2_raw_opcode_in$next[31:0]$13996 \dec2_raw_opcode_in + assign $2\dec2_raw_opcode_in$next[31:0]$13938 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dec2_raw_opcode_in$next[31:0]$13996 \$95 + assign $2\dec2_raw_opcode_in$next[31:0]$13938 \$95 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\dec2_raw_opcode_in$next[31:0]$13995 $3\dec2_raw_opcode_in$next[31:0]$13997 + assign $1\dec2_raw_opcode_in$next[31:0]$13937 $3\dec2_raw_opcode_in$next[31:0]$13939 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $3\dec2_raw_opcode_in$next[31:0]$13997 \dec2_raw_opcode_in + assign $3\dec2_raw_opcode_in$next[31:0]$13939 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $3\dec2_raw_opcode_in$next[31:0]$13997 \$99 + assign $3\dec2_raw_opcode_in$next[31:0]$13939 \$99 end case - assign $1\dec2_raw_opcode_in$next[31:0]$13995 \dec2_raw_opcode_in + assign $1\dec2_raw_opcode_in$next[31:0]$13937 \dec2_raw_opcode_in end sync always - update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13994 + update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13936 end - attribute \src "libresoc.v:199263.3-199273.6" - process $proc$libresoc.v:199263$13998 + attribute \src "libresoc.v:198436.3-198446.6" + process $proc$libresoc.v:198436$13940 assign { } { } assign { } { } assign $0\fetch_insn_valid_o[0:0] $1\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:199264.5-199264.29" + attribute \src "libresoc.v:198437.5-198437.29" switch \initial - attribute \src "libresoc.v:199264.9-199264.17" + attribute \src "libresoc.v:198437.9-198437.17" case 1'1 case end @@ -415053,8 +410278,8 @@ module \ti sync always update \fetch_insn_valid_o $0\fetch_insn_valid_o[0:0] end - attribute \src "libresoc.v:199274.3-199333.6" - process $proc$libresoc.v:199274$13999 + attribute \src "libresoc.v:198447.3-198506.6" + process $proc$libresoc.v:198447$13941 assign { } { } assign { } { } assign { } { } @@ -415068,9 +410293,9 @@ module \ti assign $0\new_svstate_subvl[1:0] $1\new_svstate_subvl[1:0] assign $0\new_svstate_svstep[1:0] $1\new_svstate_svstep[1:0] assign $0\new_svstate_vl[6:0] $1\new_svstate_vl[6:0] - attribute \src "libresoc.v:199275.5-199275.29" + attribute \src "libresoc.v:198448.5-198448.29" switch \initial - attribute \src "libresoc.v:199275.9-199275.17" + attribute \src "libresoc.v:198448.9-198448.17" case 1'1 case end @@ -415239,14 +410464,14 @@ module \ti update \new_svstate_svstep $0\new_svstate_svstep[1:0] update \new_svstate_vl $0\new_svstate_vl[6:0] end - attribute \src "libresoc.v:199334.3-199349.6" - process $proc$libresoc.v:199334$14000 + attribute \src "libresoc.v:198507.3-198522.6" + process $proc$libresoc.v:198507$13942 assign { } { } assign { } { } assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:199335.5-199335.29" + attribute \src "libresoc.v:198508.5-198508.29" switch \initial - attribute \src "libresoc.v:199335.9-199335.17" + attribute \src "libresoc.v:198508.9-198508.17" case 1'1 case end @@ -415271,15 +410496,15 @@ module \ti sync always update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0] end - attribute \src "libresoc.v:199350.3-199448.6" - process $proc$libresoc.v:199350$14001 + attribute \src "libresoc.v:198523.3-198621.6" + process $proc$libresoc.v:198523$13943 assign { } { } assign { } { } assign { } { } - assign $0\issue_fsm_state$next[2:0]$14002 $12\issue_fsm_state$next[2:0]$14014 - attribute \src "libresoc.v:199351.5-199351.29" + assign $0\issue_fsm_state$next[2:0]$13944 $12\issue_fsm_state$next[2:0]$13956 + attribute \src "libresoc.v:198524.5-198524.29" switch \initial - attribute \src "libresoc.v:199351.9-199351.17" + attribute \src "libresoc.v:198524.9-198524.17" case 1'1 case end @@ -415288,152 +410513,152 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\issue_fsm_state$next[2:0]$14003 $2\issue_fsm_state$next[2:0]$14004 + assign $1\issue_fsm_state$next[2:0]$13945 $2\issue_fsm_state$next[2:0]$13946 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \$140 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\issue_fsm_state$next[2:0]$14004 $3\issue_fsm_state$next[2:0]$14005 + assign $2\issue_fsm_state$next[2:0]$13946 $3\issue_fsm_state$next[2:0]$13947 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" switch \fetch_pc_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\issue_fsm_state$next[2:0]$14005 3'001 + assign $3\issue_fsm_state$next[2:0]$13947 3'001 case - assign $3\issue_fsm_state$next[2:0]$14005 \issue_fsm_state + assign $3\issue_fsm_state$next[2:0]$13947 \issue_fsm_state end case - assign $2\issue_fsm_state$next[2:0]$14004 \issue_fsm_state + assign $2\issue_fsm_state$next[2:0]$13946 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\issue_fsm_state$next[2:0]$14003 $4\issue_fsm_state$next[2:0]$14006 + assign $1\issue_fsm_state$next[2:0]$13945 $4\issue_fsm_state$next[2:0]$13948 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\issue_fsm_state$next[2:0]$14006 $5\issue_fsm_state$next[2:0]$14007 + assign $4\issue_fsm_state$next[2:0]$13948 $5\issue_fsm_state$next[2:0]$13949 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" switch \$144 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\issue_fsm_state$next[2:0]$14007 3'000 + assign $5\issue_fsm_state$next[2:0]$13949 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $5\issue_fsm_state$next[2:0]$14007 3'010 + assign $5\issue_fsm_state$next[2:0]$13949 3'010 end case - assign $4\issue_fsm_state$next[2:0]$14006 \issue_fsm_state + assign $4\issue_fsm_state$next[2:0]$13948 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\issue_fsm_state$next[2:0]$14003 $6\issue_fsm_state$next[2:0]$14008 + assign $1\issue_fsm_state$next[2:0]$13945 $6\issue_fsm_state$next[2:0]$13950 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" switch \pred_insn_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\issue_fsm_state$next[2:0]$14008 3'100 + assign $6\issue_fsm_state$next[2:0]$13950 3'100 case - assign $6\issue_fsm_state$next[2:0]$14008 \issue_fsm_state + assign $6\issue_fsm_state$next[2:0]$13950 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\issue_fsm_state$next[2:0]$14003 $7\issue_fsm_state$next[2:0]$14009 + assign $1\issue_fsm_state$next[2:0]$13945 $7\issue_fsm_state$next[2:0]$13951 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" switch \pred_mask_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\issue_fsm_state$next[2:0]$14009 3'010 + assign $7\issue_fsm_state$next[2:0]$13951 3'010 case - assign $7\issue_fsm_state$next[2:0]$14009 \issue_fsm_state + assign $7\issue_fsm_state$next[2:0]$13951 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\issue_fsm_state$next[2:0]$14003 $8\issue_fsm_state$next[2:0]$14010 + assign $1\issue_fsm_state$next[2:0]$13945 $8\issue_fsm_state$next[2:0]$13952 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" switch \exec_insn_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\issue_fsm_state$next[2:0]$14010 3'101 + assign $8\issue_fsm_state$next[2:0]$13952 3'101 case - assign $8\issue_fsm_state$next[2:0]$14010 \issue_fsm_state + assign $8\issue_fsm_state$next[2:0]$13952 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } - assign $1\issue_fsm_state$next[2:0]$14003 $9\issue_fsm_state$next[2:0]$14011 + assign $1\issue_fsm_state$next[2:0]$13945 $9\issue_fsm_state$next[2:0]$13953 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" switch \$150 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\issue_fsm_state$next[2:0]$14011 $10\issue_fsm_state$next[2:0]$14012 + assign $9\issue_fsm_state$next[2:0]$13953 $10\issue_fsm_state$next[2:0]$13954 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $10\issue_fsm_state$next[2:0]$14012 $11\issue_fsm_state$next[2:0]$14013 + assign $10\issue_fsm_state$next[2:0]$13954 $11\issue_fsm_state$next[2:0]$13955 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" switch { \$156 \$152 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $11\issue_fsm_state$next[2:0]$14013 3'000 + assign $11\issue_fsm_state$next[2:0]$13955 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $11\issue_fsm_state$next[2:0]$14013 3'000 + assign $11\issue_fsm_state$next[2:0]$13955 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $11\issue_fsm_state$next[2:0]$14013 3'110 + assign $11\issue_fsm_state$next[2:0]$13955 3'110 end case - assign $10\issue_fsm_state$next[2:0]$14012 \issue_fsm_state + assign $10\issue_fsm_state$next[2:0]$13954 \issue_fsm_state end case - assign $9\issue_fsm_state$next[2:0]$14011 \issue_fsm_state + assign $9\issue_fsm_state$next[2:0]$13953 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } - assign $1\issue_fsm_state$next[2:0]$14003 3'010 + assign $1\issue_fsm_state$next[2:0]$13945 3'010 case - assign $1\issue_fsm_state$next[2:0]$14003 \issue_fsm_state + assign $1\issue_fsm_state$next[2:0]$13945 \issue_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $12\issue_fsm_state$next[2:0]$14014 3'000 + assign $12\issue_fsm_state$next[2:0]$13956 3'000 case - assign $12\issue_fsm_state$next[2:0]$14014 $1\issue_fsm_state$next[2:0]$14003 + assign $12\issue_fsm_state$next[2:0]$13956 $1\issue_fsm_state$next[2:0]$13945 end sync always - update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$14002 + update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13944 end - attribute \src "libresoc.v:199449.3-199479.6" - process $proc$libresoc.v:199449$14015 + attribute \src "libresoc.v:198622.3-198652.6" + process $proc$libresoc.v:198622$13957 assign { } { } assign { } { } assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] - attribute \src "libresoc.v:199450.5-199450.29" + attribute \src "libresoc.v:198623.5-198623.29" switch \initial - attribute \src "libresoc.v:199450.9-199450.17" + attribute \src "libresoc.v:198623.9-198623.17" case 1'1 case end @@ -415473,14 +410698,14 @@ module \ti sync always update \core_stopped_i $0\core_stopped_i[0:0] end - attribute \src "libresoc.v:199480.3-199510.6" - process $proc$libresoc.v:199480$14016 + attribute \src "libresoc.v:198653.3-198683.6" + process $proc$libresoc.v:198653$13958 assign { } { } assign { } { } assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:199481.5-199481.29" + attribute \src "libresoc.v:198654.5-198654.29" switch \initial - attribute \src "libresoc.v:199481.9-199481.17" + attribute \src "libresoc.v:198654.9-198654.17" case 1'1 case end @@ -415520,16 +410745,16 @@ module \ti sync always update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] end - attribute \src "libresoc.v:199511.3-199577.6" - process $proc$libresoc.v:199511$14017 + attribute \src "libresoc.v:198684.3-198750.6" + process $proc$libresoc.v:198684$13959 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\pc_changed$next[0:0]$14018 $9\pc_changed$next[0:0]$14027 - attribute \src "libresoc.v:199512.5-199512.29" + assign $0\pc_changed$next[0:0]$13960 $9\pc_changed$next[0:0]$13969 + attribute \src "libresoc.v:198685.5-198685.29" switch \initial - attribute \src "libresoc.v:199512.9-199512.17" + attribute \src "libresoc.v:198685.9-198685.17" case 1'1 case end @@ -415538,103 +410763,103 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\pc_changed$next[0:0]$14019 $2\pc_changed$next[0:0]$14020 + assign $1\pc_changed$next[0:0]$13961 $2\pc_changed$next[0:0]$13962 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \$186 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\pc_changed$next[0:0]$14020 \pc_changed + assign $2\pc_changed$next[0:0]$13962 \pc_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\pc_changed$next[0:0]$14020 $3\pc_changed$next[0:0]$14021 + assign $2\pc_changed$next[0:0]$13962 $3\pc_changed$next[0:0]$13963 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\pc_changed$next[0:0]$14021 1'1 + assign $3\pc_changed$next[0:0]$13963 1'1 case - assign $3\pc_changed$next[0:0]$14021 \pc_changed + assign $3\pc_changed$next[0:0]$13963 \pc_changed end end attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } - assign $1\pc_changed$next[0:0]$14019 $4\pc_changed$next[0:0]$14022 + assign $1\pc_changed$next[0:0]$13961 $4\pc_changed$next[0:0]$13964 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" switch \$192 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\pc_changed$next[0:0]$14022 \pc_changed + assign $4\pc_changed$next[0:0]$13964 \pc_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\pc_changed$next[0:0]$14022 $5\pc_changed$next[0:0]$14023 + assign $4\pc_changed$next[0:0]$13964 $5\pc_changed$next[0:0]$13965 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\pc_changed$next[0:0]$14023 1'1 + assign $5\pc_changed$next[0:0]$13965 1'1 case - assign $5\pc_changed$next[0:0]$14023 \pc_changed + assign $5\pc_changed$next[0:0]$13965 \pc_changed end end case - assign $1\pc_changed$next[0:0]$14019 \pc_changed + assign $1\pc_changed$next[0:0]$13961 \pc_changed end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $6\pc_changed$next[0:0]$14024 $7\pc_changed$next[0:0]$14025 + assign $6\pc_changed$next[0:0]$13966 $7\pc_changed$next[0:0]$13967 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\pc_changed$next[0:0]$14025 1'0 + assign $7\pc_changed$next[0:0]$13967 1'0 case - assign $7\pc_changed$next[0:0]$14025 $1\pc_changed$next[0:0]$14019 + assign $7\pc_changed$next[0:0]$13967 $1\pc_changed$next[0:0]$13961 end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\pc_changed$next[0:0]$14024 $8\pc_changed$next[0:0]$14026 + assign $6\pc_changed$next[0:0]$13966 $8\pc_changed$next[0:0]$13968 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" switch \$194 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\pc_changed$next[0:0]$14026 1'1 + assign $8\pc_changed$next[0:0]$13968 1'1 case - assign $8\pc_changed$next[0:0]$14026 $1\pc_changed$next[0:0]$14019 + assign $8\pc_changed$next[0:0]$13968 $1\pc_changed$next[0:0]$13961 end case - assign $6\pc_changed$next[0:0]$14024 $1\pc_changed$next[0:0]$14019 + assign $6\pc_changed$next[0:0]$13966 $1\pc_changed$next[0:0]$13961 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\pc_changed$next[0:0]$14027 1'0 + assign $9\pc_changed$next[0:0]$13969 1'0 case - assign $9\pc_changed$next[0:0]$14027 $6\pc_changed$next[0:0]$14024 + assign $9\pc_changed$next[0:0]$13969 $6\pc_changed$next[0:0]$13966 end sync always - update \pc_changed$next $0\pc_changed$next[0:0]$14018 + update \pc_changed$next $0\pc_changed$next[0:0]$13960 end - attribute \src "libresoc.v:199578.3-199634.6" - process $proc$libresoc.v:199578$14028 + attribute \src "libresoc.v:198751.3-198807.6" + process $proc$libresoc.v:198751$13970 assign { } { } assign { } { } assign $0\update_svstate[0:0] $1\update_svstate[0:0] - attribute \src "libresoc.v:199579.5-199579.29" + attribute \src "libresoc.v:198752.5-198752.29" switch \initial - attribute \src "libresoc.v:199579.9-199579.17" + attribute \src "libresoc.v:198752.9-198752.17" case 1'1 case end @@ -415715,16 +410940,16 @@ module \ti sync always update \update_svstate $0\update_svstate[0:0] end - attribute \src "libresoc.v:199635.3-199701.6" - process $proc$libresoc.v:199635$14029 + attribute \src "libresoc.v:198808.3-198874.6" + process $proc$libresoc.v:198808$13971 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sv_changed$next[0:0]$14030 $9\sv_changed$next[0:0]$14039 - attribute \src "libresoc.v:199636.5-199636.29" + assign $0\sv_changed$next[0:0]$13972 $9\sv_changed$next[0:0]$13981 + attribute \src "libresoc.v:198809.5-198809.29" switch \initial - attribute \src "libresoc.v:199636.9-199636.17" + attribute \src "libresoc.v:198809.9-198809.17" case 1'1 case end @@ -415733,103 +410958,103 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\sv_changed$next[0:0]$14031 $2\sv_changed$next[0:0]$14032 + assign $1\sv_changed$next[0:0]$13973 $2\sv_changed$next[0:0]$13974 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \$220 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\sv_changed$next[0:0]$14032 \sv_changed + assign $2\sv_changed$next[0:0]$13974 \sv_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\sv_changed$next[0:0]$14032 $3\sv_changed$next[0:0]$14033 + assign $2\sv_changed$next[0:0]$13974 $3\sv_changed$next[0:0]$13975 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv_changed$next[0:0]$14033 1'1 + assign $3\sv_changed$next[0:0]$13975 1'1 case - assign $3\sv_changed$next[0:0]$14033 \sv_changed + assign $3\sv_changed$next[0:0]$13975 \sv_changed end end attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } - assign $1\sv_changed$next[0:0]$14031 $4\sv_changed$next[0:0]$14034 + assign $1\sv_changed$next[0:0]$13973 $4\sv_changed$next[0:0]$13976 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" switch \$226 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\sv_changed$next[0:0]$14034 \sv_changed + assign $4\sv_changed$next[0:0]$13976 \sv_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\sv_changed$next[0:0]$14034 $5\sv_changed$next[0:0]$14035 + assign $4\sv_changed$next[0:0]$13976 $5\sv_changed$next[0:0]$13977 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv_changed$next[0:0]$14035 1'1 + assign $5\sv_changed$next[0:0]$13977 1'1 case - assign $5\sv_changed$next[0:0]$14035 \sv_changed + assign $5\sv_changed$next[0:0]$13977 \sv_changed end end case - assign $1\sv_changed$next[0:0]$14031 \sv_changed + assign $1\sv_changed$next[0:0]$13973 \sv_changed end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $6\sv_changed$next[0:0]$14036 $7\sv_changed$next[0:0]$14037 + assign $6\sv_changed$next[0:0]$13978 $7\sv_changed$next[0:0]$13979 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv_changed$next[0:0]$14037 1'0 + assign $7\sv_changed$next[0:0]$13979 1'0 case - assign $7\sv_changed$next[0:0]$14037 $1\sv_changed$next[0:0]$14031 + assign $7\sv_changed$next[0:0]$13979 $1\sv_changed$next[0:0]$13973 end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv_changed$next[0:0]$14036 $8\sv_changed$next[0:0]$14038 + assign $6\sv_changed$next[0:0]$13978 $8\sv_changed$next[0:0]$13980 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:726" switch \$228 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\sv_changed$next[0:0]$14038 1'1 + assign $8\sv_changed$next[0:0]$13980 1'1 case - assign $8\sv_changed$next[0:0]$14038 $1\sv_changed$next[0:0]$14031 + assign $8\sv_changed$next[0:0]$13980 $1\sv_changed$next[0:0]$13973 end case - assign $6\sv_changed$next[0:0]$14036 $1\sv_changed$next[0:0]$14031 + assign $6\sv_changed$next[0:0]$13978 $1\sv_changed$next[0:0]$13973 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\sv_changed$next[0:0]$14039 1'0 + assign $9\sv_changed$next[0:0]$13981 1'0 case - assign $9\sv_changed$next[0:0]$14039 $6\sv_changed$next[0:0]$14036 + assign $9\sv_changed$next[0:0]$13981 $6\sv_changed$next[0:0]$13978 end sync always - update \sv_changed$next $0\sv_changed$next[0:0]$14030 + update \sv_changed$next $0\sv_changed$next[0:0]$13972 end - attribute \src "libresoc.v:199702.3-199712.6" - process $proc$libresoc.v:199702$14040 + attribute \src "libresoc.v:198875.3-198885.6" + process $proc$libresoc.v:198875$13982 assign { } { } assign { } { } assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:199703.5-199703.29" + attribute \src "libresoc.v:198876.5-198876.29" switch \initial - attribute \src "libresoc.v:199703.9-199703.17" + attribute \src "libresoc.v:198876.9-198876.17" case 1'1 case end @@ -415845,8 +411070,8 @@ module \ti sync always update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0] end - attribute \src "libresoc.v:199713.3-199823.6" - process $proc$libresoc.v:199713$14041 + attribute \src "libresoc.v:198886.3-198996.6" + process $proc$libresoc.v:198886$13983 assign { } { } assign { } { } assign { } { } @@ -415965,11 +411190,11 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_asmcode$next[7:0]$14042 $1\core_asmcode$next[7:0]$14101 - assign $0\core_core_core_cia$next[63:0]$14043 $1\core_core_core_cia$next[63:0]$14102 - assign $0\core_core_core_cr_rd$next[7:0]$14044 $1\core_core_core_cr_rd$next[7:0]$14103 + assign $0\core_asmcode$next[7:0]$13984 $1\core_asmcode$next[7:0]$14043 + assign $0\core_core_core_cia$next[63:0]$13985 $1\core_core_core_cia$next[63:0]$14044 + assign $0\core_core_core_cr_rd$next[7:0]$13986 $1\core_core_core_cr_rd$next[7:0]$14045 assign { } { } - assign $0\core_core_core_cr_wr$next[7:0]$14046 $1\core_core_core_cr_wr$next[7:0]$14105 + assign $0\core_core_core_cr_wr$next[7:0]$13988 $1\core_core_core_cr_wr$next[7:0]$14047 assign { } { } assign { } { } assign { } { } @@ -415978,82 +411203,82 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_core_core_fn_unit$next[13:0]$14055 $1\core_core_core_fn_unit$next[13:0]$14114 - assign $0\core_core_core_input_carry$next[1:0]$14056 $1\core_core_core_input_carry$next[1:0]$14115 - assign $0\core_core_core_insn$next[31:0]$14057 $1\core_core_core_insn$next[31:0]$14116 - assign $0\core_core_core_insn_type$next[6:0]$14058 $1\core_core_core_insn_type$next[6:0]$14117 - assign $0\core_core_core_is_32bit$next[0:0]$14059 $1\core_core_core_is_32bit$next[0:0]$14118 - assign $0\core_core_core_msr$next[63:0]$14060 $1\core_core_core_msr$next[63:0]$14119 - assign $0\core_core_core_oe$next[0:0]$14061 $1\core_core_core_oe$next[0:0]$14120 + assign $0\core_core_core_fn_unit$next[13:0]$13997 $1\core_core_core_fn_unit$next[13:0]$14056 + assign $0\core_core_core_input_carry$next[1:0]$13998 $1\core_core_core_input_carry$next[1:0]$14057 + assign $0\core_core_core_insn$next[31:0]$13999 $1\core_core_core_insn$next[31:0]$14058 + assign $0\core_core_core_insn_type$next[6:0]$14000 $1\core_core_core_insn_type$next[6:0]$14059 + assign $0\core_core_core_is_32bit$next[0:0]$14001 $1\core_core_core_is_32bit$next[0:0]$14060 + assign $0\core_core_core_msr$next[63:0]$14002 $1\core_core_core_msr$next[63:0]$14061 + assign $0\core_core_core_oe$next[0:0]$14003 $1\core_core_core_oe$next[0:0]$14062 assign { } { } - assign $0\core_core_core_rc$next[0:0]$14063 $1\core_core_core_rc$next[0:0]$14122 + assign $0\core_core_core_rc$next[0:0]$14005 $1\core_core_core_rc$next[0:0]$14064 assign { } { } - assign $0\core_core_core_trapaddr$next[12:0]$14065 $1\core_core_core_trapaddr$next[12:0]$14124 - assign $0\core_core_core_traptype$next[7:0]$14066 $1\core_core_core_traptype$next[7:0]$14125 - assign $0\core_core_cr_in1$next[6:0]$14067 $1\core_core_cr_in1$next[6:0]$14126 + assign $0\core_core_core_trapaddr$next[12:0]$14007 $1\core_core_core_trapaddr$next[12:0]$14066 + assign $0\core_core_core_traptype$next[7:0]$14008 $1\core_core_core_traptype$next[7:0]$14067 + assign $0\core_core_cr_in1$next[6:0]$14009 $1\core_core_cr_in1$next[6:0]$14068 assign { } { } - assign $0\core_core_cr_in2$1$next[6:0]$14069 $1\core_core_cr_in2$1$next[6:0]$14128 - assign $0\core_core_cr_in2$next[6:0]$14070 $1\core_core_cr_in2$next[6:0]$14129 + assign $0\core_core_cr_in2$1$next[6:0]$14011 $1\core_core_cr_in2$1$next[6:0]$14070 + assign $0\core_core_cr_in2$next[6:0]$14012 $1\core_core_cr_in2$next[6:0]$14071 assign { } { } assign { } { } - assign $0\core_core_cr_out$next[6:0]$14073 $1\core_core_cr_out$next[6:0]$14132 + assign $0\core_core_cr_out$next[6:0]$14015 $1\core_core_cr_out$next[6:0]$14074 assign { } { } - assign $0\core_core_ea$next[6:0]$14075 $1\core_core_ea$next[6:0]$14134 - assign $0\core_core_fast1$next[2:0]$14076 $1\core_core_fast1$next[2:0]$14135 + assign $0\core_core_ea$next[6:0]$14017 $1\core_core_ea$next[6:0]$14076 + assign $0\core_core_fast1$next[2:0]$14018 $1\core_core_fast1$next[2:0]$14077 assign { } { } - assign $0\core_core_fast2$next[2:0]$14078 $1\core_core_fast2$next[2:0]$14137 + assign $0\core_core_fast2$next[2:0]$14020 $1\core_core_fast2$next[2:0]$14079 assign { } { } - assign $0\core_core_fasto1$next[2:0]$14080 $1\core_core_fasto1$next[2:0]$14139 - assign $0\core_core_fasto2$next[2:0]$14081 $1\core_core_fasto2$next[2:0]$14140 - assign $0\core_core_lk$next[0:0]$14082 $1\core_core_lk$next[0:0]$14141 - assign $0\core_core_reg1$next[6:0]$14083 $1\core_core_reg1$next[6:0]$14142 + assign $0\core_core_fasto1$next[2:0]$14022 $1\core_core_fasto1$next[2:0]$14081 + assign $0\core_core_fasto2$next[2:0]$14023 $1\core_core_fasto2$next[2:0]$14082 + assign $0\core_core_lk$next[0:0]$14024 $1\core_core_lk$next[0:0]$14083 + assign $0\core_core_reg1$next[6:0]$14025 $1\core_core_reg1$next[6:0]$14084 assign { } { } - assign $0\core_core_reg2$next[6:0]$14085 $1\core_core_reg2$next[6:0]$14144 + assign $0\core_core_reg2$next[6:0]$14027 $1\core_core_reg2$next[6:0]$14086 assign { } { } - assign $0\core_core_reg3$next[6:0]$14087 $1\core_core_reg3$next[6:0]$14146 + assign $0\core_core_reg3$next[6:0]$14029 $1\core_core_reg3$next[6:0]$14088 assign { } { } - assign $0\core_core_rego$next[6:0]$14089 $1\core_core_rego$next[6:0]$14148 - assign $0\core_core_spr1$next[9:0]$14090 $1\core_core_spr1$next[9:0]$14149 + assign $0\core_core_rego$next[6:0]$14031 $1\core_core_rego$next[6:0]$14090 + assign $0\core_core_spr1$next[9:0]$14032 $1\core_core_spr1$next[9:0]$14091 assign { } { } - assign $0\core_core_spro$next[9:0]$14092 $1\core_core_spro$next[9:0]$14151 - assign $0\core_core_xer_in$next[2:0]$14093 $1\core_core_xer_in$next[2:0]$14152 + assign $0\core_core_spro$next[9:0]$14034 $1\core_core_spro$next[9:0]$14093 + assign $0\core_core_xer_in$next[2:0]$14035 $1\core_core_xer_in$next[2:0]$14094 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\core_xer_out$next[0:0]$14100 $1\core_xer_out$next[0:0]$14159 - assign $0\core_core_core_cr_rd_ok$next[0:0]$14045 $3\core_core_core_cr_rd_ok$next[0:0]$14219 - assign $0\core_core_core_exc_$signal$3$next[0:0]$14047 $3\core_core_core_exc_$signal$3$next[0:0]$14220 - assign $0\core_core_core_exc_$signal$4$next[0:0]$14048 $3\core_core_core_exc_$signal$4$next[0:0]$14221 - assign $0\core_core_core_exc_$signal$5$next[0:0]$14049 $3\core_core_core_exc_$signal$5$next[0:0]$14222 - assign $0\core_core_core_exc_$signal$6$next[0:0]$14050 $3\core_core_core_exc_$signal$6$next[0:0]$14223 - assign $0\core_core_core_exc_$signal$7$next[0:0]$14051 $3\core_core_core_exc_$signal$7$next[0:0]$14224 - assign $0\core_core_core_exc_$signal$8$next[0:0]$14052 $3\core_core_core_exc_$signal$8$next[0:0]$14225 - assign $0\core_core_core_exc_$signal$9$next[0:0]$14053 $3\core_core_core_exc_$signal$9$next[0:0]$14226 - assign $0\core_core_core_exc_$signal$next[0:0]$14054 $3\core_core_core_exc_$signal$next[0:0]$14227 - assign $0\core_core_core_oe_ok$next[0:0]$14062 $3\core_core_core_oe_ok$next[0:0]$14228 - assign $0\core_core_core_rc_ok$next[0:0]$14064 $3\core_core_core_rc_ok$next[0:0]$14229 - assign $0\core_core_cr_in1_ok$next[0:0]$14068 $3\core_core_cr_in1_ok$next[0:0]$14230 - assign $0\core_core_cr_in2_ok$2$next[0:0]$14071 $3\core_core_cr_in2_ok$2$next[0:0]$14231 - assign $0\core_core_cr_in2_ok$next[0:0]$14072 $3\core_core_cr_in2_ok$next[0:0]$14232 - assign $0\core_core_cr_wr_ok$next[0:0]$14074 $3\core_core_cr_wr_ok$next[0:0]$14233 - assign $0\core_core_fast1_ok$next[0:0]$14077 $3\core_core_fast1_ok$next[0:0]$14234 - assign $0\core_core_fast2_ok$next[0:0]$14079 $3\core_core_fast2_ok$next[0:0]$14235 - assign $0\core_core_reg1_ok$next[0:0]$14084 $3\core_core_reg1_ok$next[0:0]$14236 - assign $0\core_core_reg2_ok$next[0:0]$14086 $3\core_core_reg2_ok$next[0:0]$14237 - assign $0\core_core_reg3_ok$next[0:0]$14088 $3\core_core_reg3_ok$next[0:0]$14238 - assign $0\core_core_spr1_ok$next[0:0]$14091 $3\core_core_spr1_ok$next[0:0]$14239 - assign $0\core_cr_out_ok$next[0:0]$14094 $3\core_cr_out_ok$next[0:0]$14240 - assign $0\core_ea_ok$next[0:0]$14095 $3\core_ea_ok$next[0:0]$14241 - assign $0\core_fasto1_ok$next[0:0]$14096 $3\core_fasto1_ok$next[0:0]$14242 - assign $0\core_fasto2_ok$next[0:0]$14097 $3\core_fasto2_ok$next[0:0]$14243 - assign $0\core_rego_ok$next[0:0]$14098 $3\core_rego_ok$next[0:0]$14244 - assign $0\core_spro_ok$next[0:0]$14099 $3\core_spro_ok$next[0:0]$14245 - attribute \src "libresoc.v:199714.5-199714.29" + assign $0\core_xer_out$next[0:0]$14042 $1\core_xer_out$next[0:0]$14101 + assign $0\core_core_core_cr_rd_ok$next[0:0]$13987 $3\core_core_core_cr_rd_ok$next[0:0]$14161 + assign $0\core_core_core_exc_$signal$3$next[0:0]$13989 $3\core_core_core_exc_$signal$3$next[0:0]$14162 + assign $0\core_core_core_exc_$signal$4$next[0:0]$13990 $3\core_core_core_exc_$signal$4$next[0:0]$14163 + assign $0\core_core_core_exc_$signal$5$next[0:0]$13991 $3\core_core_core_exc_$signal$5$next[0:0]$14164 + assign $0\core_core_core_exc_$signal$6$next[0:0]$13992 $3\core_core_core_exc_$signal$6$next[0:0]$14165 + assign $0\core_core_core_exc_$signal$7$next[0:0]$13993 $3\core_core_core_exc_$signal$7$next[0:0]$14166 + assign $0\core_core_core_exc_$signal$8$next[0:0]$13994 $3\core_core_core_exc_$signal$8$next[0:0]$14167 + assign $0\core_core_core_exc_$signal$9$next[0:0]$13995 $3\core_core_core_exc_$signal$9$next[0:0]$14168 + assign $0\core_core_core_exc_$signal$next[0:0]$13996 $3\core_core_core_exc_$signal$next[0:0]$14169 + assign $0\core_core_core_oe_ok$next[0:0]$14004 $3\core_core_core_oe_ok$next[0:0]$14170 + assign $0\core_core_core_rc_ok$next[0:0]$14006 $3\core_core_core_rc_ok$next[0:0]$14171 + assign $0\core_core_cr_in1_ok$next[0:0]$14010 $3\core_core_cr_in1_ok$next[0:0]$14172 + assign $0\core_core_cr_in2_ok$2$next[0:0]$14013 $3\core_core_cr_in2_ok$2$next[0:0]$14173 + assign $0\core_core_cr_in2_ok$next[0:0]$14014 $3\core_core_cr_in2_ok$next[0:0]$14174 + assign $0\core_core_cr_wr_ok$next[0:0]$14016 $3\core_core_cr_wr_ok$next[0:0]$14175 + assign $0\core_core_fast1_ok$next[0:0]$14019 $3\core_core_fast1_ok$next[0:0]$14176 + assign $0\core_core_fast2_ok$next[0:0]$14021 $3\core_core_fast2_ok$next[0:0]$14177 + assign $0\core_core_reg1_ok$next[0:0]$14026 $3\core_core_reg1_ok$next[0:0]$14178 + assign $0\core_core_reg2_ok$next[0:0]$14028 $3\core_core_reg2_ok$next[0:0]$14179 + assign $0\core_core_reg3_ok$next[0:0]$14030 $3\core_core_reg3_ok$next[0:0]$14180 + assign $0\core_core_spr1_ok$next[0:0]$14033 $3\core_core_spr1_ok$next[0:0]$14181 + assign $0\core_cr_out_ok$next[0:0]$14036 $3\core_cr_out_ok$next[0:0]$14182 + assign $0\core_ea_ok$next[0:0]$14037 $3\core_ea_ok$next[0:0]$14183 + assign $0\core_fasto1_ok$next[0:0]$14038 $3\core_fasto1_ok$next[0:0]$14184 + assign $0\core_fasto2_ok$next[0:0]$14039 $3\core_fasto2_ok$next[0:0]$14185 + assign $0\core_rego_ok$next[0:0]$14040 $3\core_rego_ok$next[0:0]$14186 + assign $0\core_spro_ok$next[0:0]$14041 $3\core_spro_ok$next[0:0]$14187 + attribute \src "libresoc.v:198887.5-198887.29" switch \initial - attribute \src "libresoc.v:199714.9-199714.17" + attribute \src "libresoc.v:198887.9-198887.17" case 1'1 case end @@ -416120,65 +411345,65 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\core_asmcode$next[7:0]$14101 $2\core_asmcode$next[7:0]$14160 - assign $1\core_core_core_cia$next[63:0]$14102 $2\core_core_core_cia$next[63:0]$14161 - assign $1\core_core_core_cr_rd$next[7:0]$14103 $2\core_core_core_cr_rd$next[7:0]$14162 - assign $1\core_core_core_cr_rd_ok$next[0:0]$14104 $2\core_core_core_cr_rd_ok$next[0:0]$14163 - assign $1\core_core_core_cr_wr$next[7:0]$14105 $2\core_core_core_cr_wr$next[7:0]$14164 - assign $1\core_core_core_exc_$signal$3$next[0:0]$14106 $2\core_core_core_exc_$signal$3$next[0:0]$14165 - assign $1\core_core_core_exc_$signal$4$next[0:0]$14107 $2\core_core_core_exc_$signal$4$next[0:0]$14166 - assign $1\core_core_core_exc_$signal$5$next[0:0]$14108 $2\core_core_core_exc_$signal$5$next[0:0]$14167 - assign $1\core_core_core_exc_$signal$6$next[0:0]$14109 $2\core_core_core_exc_$signal$6$next[0:0]$14168 - assign $1\core_core_core_exc_$signal$7$next[0:0]$14110 $2\core_core_core_exc_$signal$7$next[0:0]$14169 - assign $1\core_core_core_exc_$signal$8$next[0:0]$14111 $2\core_core_core_exc_$signal$8$next[0:0]$14170 - assign $1\core_core_core_exc_$signal$9$next[0:0]$14112 $2\core_core_core_exc_$signal$9$next[0:0]$14171 - assign $1\core_core_core_exc_$signal$next[0:0]$14113 $2\core_core_core_exc_$signal$next[0:0]$14172 - assign $1\core_core_core_fn_unit$next[13:0]$14114 $2\core_core_core_fn_unit$next[13:0]$14173 - assign $1\core_core_core_input_carry$next[1:0]$14115 $2\core_core_core_input_carry$next[1:0]$14174 - assign $1\core_core_core_insn$next[31:0]$14116 $2\core_core_core_insn$next[31:0]$14175 - assign $1\core_core_core_insn_type$next[6:0]$14117 $2\core_core_core_insn_type$next[6:0]$14176 - assign $1\core_core_core_is_32bit$next[0:0]$14118 $2\core_core_core_is_32bit$next[0:0]$14177 - assign $1\core_core_core_msr$next[63:0]$14119 $2\core_core_core_msr$next[63:0]$14178 - assign $1\core_core_core_oe$next[0:0]$14120 $2\core_core_core_oe$next[0:0]$14179 - assign $1\core_core_core_oe_ok$next[0:0]$14121 $2\core_core_core_oe_ok$next[0:0]$14180 - assign $1\core_core_core_rc$next[0:0]$14122 $2\core_core_core_rc$next[0:0]$14181 - assign $1\core_core_core_rc_ok$next[0:0]$14123 $2\core_core_core_rc_ok$next[0:0]$14182 - assign $1\core_core_core_trapaddr$next[12:0]$14124 $2\core_core_core_trapaddr$next[12:0]$14183 - assign $1\core_core_core_traptype$next[7:0]$14125 $2\core_core_core_traptype$next[7:0]$14184 - assign $1\core_core_cr_in1$next[6:0]$14126 $2\core_core_cr_in1$next[6:0]$14185 - assign $1\core_core_cr_in1_ok$next[0:0]$14127 $2\core_core_cr_in1_ok$next[0:0]$14186 - assign $1\core_core_cr_in2$1$next[6:0]$14128 $2\core_core_cr_in2$1$next[6:0]$14187 - assign $1\core_core_cr_in2$next[6:0]$14129 $2\core_core_cr_in2$next[6:0]$14188 - assign $1\core_core_cr_in2_ok$2$next[0:0]$14130 $2\core_core_cr_in2_ok$2$next[0:0]$14189 - assign $1\core_core_cr_in2_ok$next[0:0]$14131 $2\core_core_cr_in2_ok$next[0:0]$14190 - assign $1\core_core_cr_out$next[6:0]$14132 $2\core_core_cr_out$next[6:0]$14191 - assign $1\core_core_cr_wr_ok$next[0:0]$14133 $2\core_core_cr_wr_ok$next[0:0]$14192 - assign $1\core_core_ea$next[6:0]$14134 $2\core_core_ea$next[6:0]$14193 - assign $1\core_core_fast1$next[2:0]$14135 $2\core_core_fast1$next[2:0]$14194 - assign $1\core_core_fast1_ok$next[0:0]$14136 $2\core_core_fast1_ok$next[0:0]$14195 - assign $1\core_core_fast2$next[2:0]$14137 $2\core_core_fast2$next[2:0]$14196 - assign $1\core_core_fast2_ok$next[0:0]$14138 $2\core_core_fast2_ok$next[0:0]$14197 - assign $1\core_core_fasto1$next[2:0]$14139 $2\core_core_fasto1$next[2:0]$14198 - assign $1\core_core_fasto2$next[2:0]$14140 $2\core_core_fasto2$next[2:0]$14199 - assign $1\core_core_lk$next[0:0]$14141 $2\core_core_lk$next[0:0]$14200 - assign $1\core_core_reg1$next[6:0]$14142 $2\core_core_reg1$next[6:0]$14201 - assign $1\core_core_reg1_ok$next[0:0]$14143 $2\core_core_reg1_ok$next[0:0]$14202 - assign $1\core_core_reg2$next[6:0]$14144 $2\core_core_reg2$next[6:0]$14203 - assign $1\core_core_reg2_ok$next[0:0]$14145 $2\core_core_reg2_ok$next[0:0]$14204 - assign $1\core_core_reg3$next[6:0]$14146 $2\core_core_reg3$next[6:0]$14205 - assign $1\core_core_reg3_ok$next[0:0]$14147 $2\core_core_reg3_ok$next[0:0]$14206 - assign $1\core_core_rego$next[6:0]$14148 $2\core_core_rego$next[6:0]$14207 - assign $1\core_core_spr1$next[9:0]$14149 $2\core_core_spr1$next[9:0]$14208 - assign $1\core_core_spr1_ok$next[0:0]$14150 $2\core_core_spr1_ok$next[0:0]$14209 - assign $1\core_core_spro$next[9:0]$14151 $2\core_core_spro$next[9:0]$14210 - assign $1\core_core_xer_in$next[2:0]$14152 $2\core_core_xer_in$next[2:0]$14211 - assign $1\core_cr_out_ok$next[0:0]$14153 $2\core_cr_out_ok$next[0:0]$14212 - assign $1\core_ea_ok$next[0:0]$14154 $2\core_ea_ok$next[0:0]$14213 - assign $1\core_fasto1_ok$next[0:0]$14155 $2\core_fasto1_ok$next[0:0]$14214 - assign $1\core_fasto2_ok$next[0:0]$14156 $2\core_fasto2_ok$next[0:0]$14215 - assign $1\core_rego_ok$next[0:0]$14157 $2\core_rego_ok$next[0:0]$14216 - assign $1\core_spro_ok$next[0:0]$14158 $2\core_spro_ok$next[0:0]$14217 - assign $1\core_xer_out$next[0:0]$14159 $2\core_xer_out$next[0:0]$14218 + assign $1\core_asmcode$next[7:0]$14043 $2\core_asmcode$next[7:0]$14102 + assign $1\core_core_core_cia$next[63:0]$14044 $2\core_core_core_cia$next[63:0]$14103 + assign $1\core_core_core_cr_rd$next[7:0]$14045 $2\core_core_core_cr_rd$next[7:0]$14104 + assign $1\core_core_core_cr_rd_ok$next[0:0]$14046 $2\core_core_core_cr_rd_ok$next[0:0]$14105 + assign $1\core_core_core_cr_wr$next[7:0]$14047 $2\core_core_core_cr_wr$next[7:0]$14106 + assign $1\core_core_core_exc_$signal$3$next[0:0]$14048 $2\core_core_core_exc_$signal$3$next[0:0]$14107 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14049 $2\core_core_core_exc_$signal$4$next[0:0]$14108 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14050 $2\core_core_core_exc_$signal$5$next[0:0]$14109 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14051 $2\core_core_core_exc_$signal$6$next[0:0]$14110 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14052 $2\core_core_core_exc_$signal$7$next[0:0]$14111 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14053 $2\core_core_core_exc_$signal$8$next[0:0]$14112 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14054 $2\core_core_core_exc_$signal$9$next[0:0]$14113 + assign $1\core_core_core_exc_$signal$next[0:0]$14055 $2\core_core_core_exc_$signal$next[0:0]$14114 + assign $1\core_core_core_fn_unit$next[13:0]$14056 $2\core_core_core_fn_unit$next[13:0]$14115 + assign $1\core_core_core_input_carry$next[1:0]$14057 $2\core_core_core_input_carry$next[1:0]$14116 + assign $1\core_core_core_insn$next[31:0]$14058 $2\core_core_core_insn$next[31:0]$14117 + assign $1\core_core_core_insn_type$next[6:0]$14059 $2\core_core_core_insn_type$next[6:0]$14118 + assign $1\core_core_core_is_32bit$next[0:0]$14060 $2\core_core_core_is_32bit$next[0:0]$14119 + assign $1\core_core_core_msr$next[63:0]$14061 $2\core_core_core_msr$next[63:0]$14120 + assign $1\core_core_core_oe$next[0:0]$14062 $2\core_core_core_oe$next[0:0]$14121 + assign $1\core_core_core_oe_ok$next[0:0]$14063 $2\core_core_core_oe_ok$next[0:0]$14122 + assign $1\core_core_core_rc$next[0:0]$14064 $2\core_core_core_rc$next[0:0]$14123 + assign $1\core_core_core_rc_ok$next[0:0]$14065 $2\core_core_core_rc_ok$next[0:0]$14124 + assign $1\core_core_core_trapaddr$next[12:0]$14066 $2\core_core_core_trapaddr$next[12:0]$14125 + assign $1\core_core_core_traptype$next[7:0]$14067 $2\core_core_core_traptype$next[7:0]$14126 + assign $1\core_core_cr_in1$next[6:0]$14068 $2\core_core_cr_in1$next[6:0]$14127 + assign $1\core_core_cr_in1_ok$next[0:0]$14069 $2\core_core_cr_in1_ok$next[0:0]$14128 + assign $1\core_core_cr_in2$1$next[6:0]$14070 $2\core_core_cr_in2$1$next[6:0]$14129 + assign $1\core_core_cr_in2$next[6:0]$14071 $2\core_core_cr_in2$next[6:0]$14130 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14072 $2\core_core_cr_in2_ok$2$next[0:0]$14131 + assign $1\core_core_cr_in2_ok$next[0:0]$14073 $2\core_core_cr_in2_ok$next[0:0]$14132 + assign $1\core_core_cr_out$next[6:0]$14074 $2\core_core_cr_out$next[6:0]$14133 + assign $1\core_core_cr_wr_ok$next[0:0]$14075 $2\core_core_cr_wr_ok$next[0:0]$14134 + assign $1\core_core_ea$next[6:0]$14076 $2\core_core_ea$next[6:0]$14135 + assign $1\core_core_fast1$next[2:0]$14077 $2\core_core_fast1$next[2:0]$14136 + assign $1\core_core_fast1_ok$next[0:0]$14078 $2\core_core_fast1_ok$next[0:0]$14137 + assign $1\core_core_fast2$next[2:0]$14079 $2\core_core_fast2$next[2:0]$14138 + assign $1\core_core_fast2_ok$next[0:0]$14080 $2\core_core_fast2_ok$next[0:0]$14139 + assign $1\core_core_fasto1$next[2:0]$14081 $2\core_core_fasto1$next[2:0]$14140 + assign $1\core_core_fasto2$next[2:0]$14082 $2\core_core_fasto2$next[2:0]$14141 + assign $1\core_core_lk$next[0:0]$14083 $2\core_core_lk$next[0:0]$14142 + assign $1\core_core_reg1$next[6:0]$14084 $2\core_core_reg1$next[6:0]$14143 + assign $1\core_core_reg1_ok$next[0:0]$14085 $2\core_core_reg1_ok$next[0:0]$14144 + assign $1\core_core_reg2$next[6:0]$14086 $2\core_core_reg2$next[6:0]$14145 + assign $1\core_core_reg2_ok$next[0:0]$14087 $2\core_core_reg2_ok$next[0:0]$14146 + assign $1\core_core_reg3$next[6:0]$14088 $2\core_core_reg3$next[6:0]$14147 + assign $1\core_core_reg3_ok$next[0:0]$14089 $2\core_core_reg3_ok$next[0:0]$14148 + assign $1\core_core_rego$next[6:0]$14090 $2\core_core_rego$next[6:0]$14149 + assign $1\core_core_spr1$next[9:0]$14091 $2\core_core_spr1$next[9:0]$14150 + assign $1\core_core_spr1_ok$next[0:0]$14092 $2\core_core_spr1_ok$next[0:0]$14151 + assign $1\core_core_spro$next[9:0]$14093 $2\core_core_spro$next[9:0]$14152 + assign $1\core_core_xer_in$next[2:0]$14094 $2\core_core_xer_in$next[2:0]$14153 + assign $1\core_cr_out_ok$next[0:0]$14095 $2\core_cr_out_ok$next[0:0]$14154 + assign $1\core_ea_ok$next[0:0]$14096 $2\core_ea_ok$next[0:0]$14155 + assign $1\core_fasto1_ok$next[0:0]$14097 $2\core_fasto1_ok$next[0:0]$14156 + assign $1\core_fasto2_ok$next[0:0]$14098 $2\core_fasto2_ok$next[0:0]$14157 + assign $1\core_rego_ok$next[0:0]$14099 $2\core_rego_ok$next[0:0]$14158 + assign $1\core_spro_ok$next[0:0]$14100 $2\core_spro_ok$next[0:0]$14159 + assign $1\core_xer_out$next[0:0]$14101 $2\core_xer_out$next[0:0]$14160 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" @@ -416242,67 +411467,67 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\core_core_core_is_32bit$next[0:0]$14177 $2\core_core_cr_wr_ok$next[0:0]$14192 $2\core_core_core_cr_wr$next[7:0]$14164 $2\core_core_core_cr_rd_ok$next[0:0]$14163 $2\core_core_core_cr_rd$next[7:0]$14162 $2\core_core_core_trapaddr$next[12:0]$14183 $2\core_core_core_exc_$signal$9$next[0:0]$14171 $2\core_core_core_exc_$signal$8$next[0:0]$14170 $2\core_core_core_exc_$signal$7$next[0:0]$14169 $2\core_core_core_exc_$signal$6$next[0:0]$14168 $2\core_core_core_exc_$signal$5$next[0:0]$14167 $2\core_core_core_exc_$signal$4$next[0:0]$14166 $2\core_core_core_exc_$signal$3$next[0:0]$14165 $2\core_core_core_exc_$signal$next[0:0]$14172 $2\core_core_core_traptype$next[7:0]$14184 $2\core_core_core_input_carry$next[1:0]$14174 $2\core_core_core_oe_ok$next[0:0]$14180 $2\core_core_core_oe$next[0:0]$14179 $2\core_core_core_rc_ok$next[0:0]$14182 $2\core_core_core_rc$next[0:0]$14181 $2\core_core_lk$next[0:0]$14200 $2\core_core_core_fn_unit$next[13:0]$14173 $2\core_core_core_insn_type$next[6:0]$14176 $2\core_core_core_insn$next[31:0]$14175 $2\core_core_core_cia$next[63:0]$14161 $2\core_core_core_msr$next[63:0]$14178 $2\core_cr_out_ok$next[0:0]$14212 $2\core_core_cr_out$next[6:0]$14191 $2\core_core_cr_in2_ok$2$next[0:0]$14189 $2\core_core_cr_in2$1$next[6:0]$14187 $2\core_core_cr_in2_ok$next[0:0]$14190 $2\core_core_cr_in2$next[6:0]$14188 $2\core_core_cr_in1_ok$next[0:0]$14186 $2\core_core_cr_in1$next[6:0]$14185 $2\core_fasto2_ok$next[0:0]$14215 $2\core_core_fasto2$next[2:0]$14199 $2\core_fasto1_ok$next[0:0]$14214 $2\core_core_fasto1$next[2:0]$14198 $2\core_core_fast2_ok$next[0:0]$14197 $2\core_core_fast2$next[2:0]$14196 $2\core_core_fast1_ok$next[0:0]$14195 $2\core_core_fast1$next[2:0]$14194 $2\core_xer_out$next[0:0]$14218 $2\core_core_xer_in$next[2:0]$14211 $2\core_core_spr1_ok$next[0:0]$14209 $2\core_core_spr1$next[9:0]$14208 $2\core_spro_ok$next[0:0]$14217 $2\core_core_spro$next[9:0]$14210 $2\core_core_reg3_ok$next[0:0]$14206 $2\core_core_reg3$next[6:0]$14205 $2\core_core_reg2_ok$next[0:0]$14204 $2\core_core_reg2$next[6:0]$14203 $2\core_core_reg1_ok$next[0:0]$14202 $2\core_core_reg1$next[6:0]$14201 $2\core_ea_ok$next[0:0]$14213 $2\core_core_ea$next[6:0]$14193 $2\core_rego_ok$next[0:0]$14216 $2\core_core_rego$next[6:0]$14207 $2\core_asmcode$next[7:0]$14160 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + assign { $2\core_core_core_is_32bit$next[0:0]$14119 $2\core_core_cr_wr_ok$next[0:0]$14134 $2\core_core_core_cr_wr$next[7:0]$14106 $2\core_core_core_cr_rd_ok$next[0:0]$14105 $2\core_core_core_cr_rd$next[7:0]$14104 $2\core_core_core_trapaddr$next[12:0]$14125 $2\core_core_core_exc_$signal$9$next[0:0]$14113 $2\core_core_core_exc_$signal$8$next[0:0]$14112 $2\core_core_core_exc_$signal$7$next[0:0]$14111 $2\core_core_core_exc_$signal$6$next[0:0]$14110 $2\core_core_core_exc_$signal$5$next[0:0]$14109 $2\core_core_core_exc_$signal$4$next[0:0]$14108 $2\core_core_core_exc_$signal$3$next[0:0]$14107 $2\core_core_core_exc_$signal$next[0:0]$14114 $2\core_core_core_traptype$next[7:0]$14126 $2\core_core_core_input_carry$next[1:0]$14116 $2\core_core_core_oe_ok$next[0:0]$14122 $2\core_core_core_oe$next[0:0]$14121 $2\core_core_core_rc_ok$next[0:0]$14124 $2\core_core_core_rc$next[0:0]$14123 $2\core_core_lk$next[0:0]$14142 $2\core_core_core_fn_unit$next[13:0]$14115 $2\core_core_core_insn_type$next[6:0]$14118 $2\core_core_core_insn$next[31:0]$14117 $2\core_core_core_cia$next[63:0]$14103 $2\core_core_core_msr$next[63:0]$14120 $2\core_cr_out_ok$next[0:0]$14154 $2\core_core_cr_out$next[6:0]$14133 $2\core_core_cr_in2_ok$2$next[0:0]$14131 $2\core_core_cr_in2$1$next[6:0]$14129 $2\core_core_cr_in2_ok$next[0:0]$14132 $2\core_core_cr_in2$next[6:0]$14130 $2\core_core_cr_in1_ok$next[0:0]$14128 $2\core_core_cr_in1$next[6:0]$14127 $2\core_fasto2_ok$next[0:0]$14157 $2\core_core_fasto2$next[2:0]$14141 $2\core_fasto1_ok$next[0:0]$14156 $2\core_core_fasto1$next[2:0]$14140 $2\core_core_fast2_ok$next[0:0]$14139 $2\core_core_fast2$next[2:0]$14138 $2\core_core_fast1_ok$next[0:0]$14137 $2\core_core_fast1$next[2:0]$14136 $2\core_xer_out$next[0:0]$14160 $2\core_core_xer_in$next[2:0]$14153 $2\core_core_spr1_ok$next[0:0]$14151 $2\core_core_spr1$next[9:0]$14150 $2\core_spro_ok$next[0:0]$14159 $2\core_core_spro$next[9:0]$14152 $2\core_core_reg3_ok$next[0:0]$14148 $2\core_core_reg3$next[6:0]$14147 $2\core_core_reg2_ok$next[0:0]$14146 $2\core_core_reg2$next[6:0]$14145 $2\core_core_reg1_ok$next[0:0]$14144 $2\core_core_reg1$next[6:0]$14143 $2\core_ea_ok$next[0:0]$14155 $2\core_core_ea$next[6:0]$14135 $2\core_rego_ok$next[0:0]$14158 $2\core_core_rego$next[6:0]$14149 $2\core_asmcode$next[7:0]$14102 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } case - assign $2\core_asmcode$next[7:0]$14160 \core_asmcode - assign $2\core_core_core_cia$next[63:0]$14161 \core_core_core_cia - assign $2\core_core_core_cr_rd$next[7:0]$14162 \core_core_core_cr_rd - assign $2\core_core_core_cr_rd_ok$next[0:0]$14163 \core_core_core_cr_rd_ok - assign $2\core_core_core_cr_wr$next[7:0]$14164 \core_core_core_cr_wr - assign $2\core_core_core_exc_$signal$3$next[0:0]$14165 \core_core_core_exc_$signal$3 - assign $2\core_core_core_exc_$signal$4$next[0:0]$14166 \core_core_core_exc_$signal$4 - assign $2\core_core_core_exc_$signal$5$next[0:0]$14167 \core_core_core_exc_$signal$5 - assign $2\core_core_core_exc_$signal$6$next[0:0]$14168 \core_core_core_exc_$signal$6 - assign $2\core_core_core_exc_$signal$7$next[0:0]$14169 \core_core_core_exc_$signal$7 - assign $2\core_core_core_exc_$signal$8$next[0:0]$14170 \core_core_core_exc_$signal$8 - assign $2\core_core_core_exc_$signal$9$next[0:0]$14171 \core_core_core_exc_$signal$9 - assign $2\core_core_core_exc_$signal$next[0:0]$14172 \core_core_core_exc_$signal - assign $2\core_core_core_fn_unit$next[13:0]$14173 \core_core_core_fn_unit - assign $2\core_core_core_input_carry$next[1:0]$14174 \core_core_core_input_carry - assign $2\core_core_core_insn$next[31:0]$14175 \core_core_core_insn - assign $2\core_core_core_insn_type$next[6:0]$14176 \core_core_core_insn_type - assign $2\core_core_core_is_32bit$next[0:0]$14177 \core_core_core_is_32bit - assign $2\core_core_core_msr$next[63:0]$14178 \core_core_core_msr - assign $2\core_core_core_oe$next[0:0]$14179 \core_core_core_oe - assign $2\core_core_core_oe_ok$next[0:0]$14180 \core_core_core_oe_ok - assign $2\core_core_core_rc$next[0:0]$14181 \core_core_core_rc - assign $2\core_core_core_rc_ok$next[0:0]$14182 \core_core_core_rc_ok - assign $2\core_core_core_trapaddr$next[12:0]$14183 \core_core_core_trapaddr - assign $2\core_core_core_traptype$next[7:0]$14184 \core_core_core_traptype - assign $2\core_core_cr_in1$next[6:0]$14185 \core_core_cr_in1 - assign $2\core_core_cr_in1_ok$next[0:0]$14186 \core_core_cr_in1_ok - assign $2\core_core_cr_in2$1$next[6:0]$14187 \core_core_cr_in2$1 - assign $2\core_core_cr_in2$next[6:0]$14188 \core_core_cr_in2 - assign $2\core_core_cr_in2_ok$2$next[0:0]$14189 \core_core_cr_in2_ok$2 - assign $2\core_core_cr_in2_ok$next[0:0]$14190 \core_core_cr_in2_ok - assign $2\core_core_cr_out$next[6:0]$14191 \core_core_cr_out - assign $2\core_core_cr_wr_ok$next[0:0]$14192 \core_core_cr_wr_ok - assign $2\core_core_ea$next[6:0]$14193 \core_core_ea - assign $2\core_core_fast1$next[2:0]$14194 \core_core_fast1 - assign $2\core_core_fast1_ok$next[0:0]$14195 \core_core_fast1_ok - assign $2\core_core_fast2$next[2:0]$14196 \core_core_fast2 - assign $2\core_core_fast2_ok$next[0:0]$14197 \core_core_fast2_ok - assign $2\core_core_fasto1$next[2:0]$14198 \core_core_fasto1 - assign $2\core_core_fasto2$next[2:0]$14199 \core_core_fasto2 - assign $2\core_core_lk$next[0:0]$14200 \core_core_lk - assign $2\core_core_reg1$next[6:0]$14201 \core_core_reg1 - assign $2\core_core_reg1_ok$next[0:0]$14202 \core_core_reg1_ok - assign $2\core_core_reg2$next[6:0]$14203 \core_core_reg2 - assign $2\core_core_reg2_ok$next[0:0]$14204 \core_core_reg2_ok - assign $2\core_core_reg3$next[6:0]$14205 \core_core_reg3 - assign $2\core_core_reg3_ok$next[0:0]$14206 \core_core_reg3_ok - assign $2\core_core_rego$next[6:0]$14207 \core_core_rego - assign $2\core_core_spr1$next[9:0]$14208 \core_core_spr1 - assign $2\core_core_spr1_ok$next[0:0]$14209 \core_core_spr1_ok - assign $2\core_core_spro$next[9:0]$14210 \core_core_spro - assign $2\core_core_xer_in$next[2:0]$14211 \core_core_xer_in - assign $2\core_cr_out_ok$next[0:0]$14212 \core_cr_out_ok - assign $2\core_ea_ok$next[0:0]$14213 \core_ea_ok - assign $2\core_fasto1_ok$next[0:0]$14214 \core_fasto1_ok - assign $2\core_fasto2_ok$next[0:0]$14215 \core_fasto2_ok - assign $2\core_rego_ok$next[0:0]$14216 \core_rego_ok - assign $2\core_spro_ok$next[0:0]$14217 \core_spro_ok - assign $2\core_xer_out$next[0:0]$14218 \core_xer_out + assign $2\core_asmcode$next[7:0]$14102 \core_asmcode + assign $2\core_core_core_cia$next[63:0]$14103 \core_core_core_cia + assign $2\core_core_core_cr_rd$next[7:0]$14104 \core_core_core_cr_rd + assign $2\core_core_core_cr_rd_ok$next[0:0]$14105 \core_core_core_cr_rd_ok + assign $2\core_core_core_cr_wr$next[7:0]$14106 \core_core_core_cr_wr + assign $2\core_core_core_exc_$signal$3$next[0:0]$14107 \core_core_core_exc_$signal$3 + assign $2\core_core_core_exc_$signal$4$next[0:0]$14108 \core_core_core_exc_$signal$4 + assign $2\core_core_core_exc_$signal$5$next[0:0]$14109 \core_core_core_exc_$signal$5 + assign $2\core_core_core_exc_$signal$6$next[0:0]$14110 \core_core_core_exc_$signal$6 + assign $2\core_core_core_exc_$signal$7$next[0:0]$14111 \core_core_core_exc_$signal$7 + assign $2\core_core_core_exc_$signal$8$next[0:0]$14112 \core_core_core_exc_$signal$8 + assign $2\core_core_core_exc_$signal$9$next[0:0]$14113 \core_core_core_exc_$signal$9 + assign $2\core_core_core_exc_$signal$next[0:0]$14114 \core_core_core_exc_$signal + assign $2\core_core_core_fn_unit$next[13:0]$14115 \core_core_core_fn_unit + assign $2\core_core_core_input_carry$next[1:0]$14116 \core_core_core_input_carry + assign $2\core_core_core_insn$next[31:0]$14117 \core_core_core_insn + assign $2\core_core_core_insn_type$next[6:0]$14118 \core_core_core_insn_type + assign $2\core_core_core_is_32bit$next[0:0]$14119 \core_core_core_is_32bit + assign $2\core_core_core_msr$next[63:0]$14120 \core_core_core_msr + assign $2\core_core_core_oe$next[0:0]$14121 \core_core_core_oe + assign $2\core_core_core_oe_ok$next[0:0]$14122 \core_core_core_oe_ok + assign $2\core_core_core_rc$next[0:0]$14123 \core_core_core_rc + assign $2\core_core_core_rc_ok$next[0:0]$14124 \core_core_core_rc_ok + assign $2\core_core_core_trapaddr$next[12:0]$14125 \core_core_core_trapaddr + assign $2\core_core_core_traptype$next[7:0]$14126 \core_core_core_traptype + assign $2\core_core_cr_in1$next[6:0]$14127 \core_core_cr_in1 + assign $2\core_core_cr_in1_ok$next[0:0]$14128 \core_core_cr_in1_ok + assign $2\core_core_cr_in2$1$next[6:0]$14129 \core_core_cr_in2$1 + assign $2\core_core_cr_in2$next[6:0]$14130 \core_core_cr_in2 + assign $2\core_core_cr_in2_ok$2$next[0:0]$14131 \core_core_cr_in2_ok$2 + assign $2\core_core_cr_in2_ok$next[0:0]$14132 \core_core_cr_in2_ok + assign $2\core_core_cr_out$next[6:0]$14133 \core_core_cr_out + assign $2\core_core_cr_wr_ok$next[0:0]$14134 \core_core_cr_wr_ok + assign $2\core_core_ea$next[6:0]$14135 \core_core_ea + assign $2\core_core_fast1$next[2:0]$14136 \core_core_fast1 + assign $2\core_core_fast1_ok$next[0:0]$14137 \core_core_fast1_ok + assign $2\core_core_fast2$next[2:0]$14138 \core_core_fast2 + assign $2\core_core_fast2_ok$next[0:0]$14139 \core_core_fast2_ok + assign $2\core_core_fasto1$next[2:0]$14140 \core_core_fasto1 + assign $2\core_core_fasto2$next[2:0]$14141 \core_core_fasto2 + assign $2\core_core_lk$next[0:0]$14142 \core_core_lk + assign $2\core_core_reg1$next[6:0]$14143 \core_core_reg1 + assign $2\core_core_reg1_ok$next[0:0]$14144 \core_core_reg1_ok + assign $2\core_core_reg2$next[6:0]$14145 \core_core_reg2 + assign $2\core_core_reg2_ok$next[0:0]$14146 \core_core_reg2_ok + assign $2\core_core_reg3$next[6:0]$14147 \core_core_reg3 + assign $2\core_core_reg3_ok$next[0:0]$14148 \core_core_reg3_ok + assign $2\core_core_rego$next[6:0]$14149 \core_core_rego + assign $2\core_core_spr1$next[9:0]$14150 \core_core_spr1 + assign $2\core_core_spr1_ok$next[0:0]$14151 \core_core_spr1_ok + assign $2\core_core_spro$next[9:0]$14152 \core_core_spro + assign $2\core_core_xer_in$next[2:0]$14153 \core_core_xer_in + assign $2\core_cr_out_ok$next[0:0]$14154 \core_cr_out_ok + assign $2\core_ea_ok$next[0:0]$14155 \core_ea_ok + assign $2\core_fasto1_ok$next[0:0]$14156 \core_fasto1_ok + assign $2\core_fasto2_ok$next[0:0]$14157 \core_fasto2_ok + assign $2\core_rego_ok$next[0:0]$14158 \core_rego_ok + assign $2\core_spro_ok$next[0:0]$14159 \core_spro_ok + assign $2\core_xer_out$next[0:0]$14160 \core_xer_out end attribute \src "libresoc.v:0.0-0.0" case 3'110 @@ -416365,67 +411590,67 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $1\core_core_core_is_32bit$next[0:0]$14118 $1\core_core_cr_wr_ok$next[0:0]$14133 $1\core_core_core_cr_wr$next[7:0]$14105 $1\core_core_core_cr_rd_ok$next[0:0]$14104 $1\core_core_core_cr_rd$next[7:0]$14103 $1\core_core_core_trapaddr$next[12:0]$14124 $1\core_core_core_exc_$signal$9$next[0:0]$14112 $1\core_core_core_exc_$signal$8$next[0:0]$14111 $1\core_core_core_exc_$signal$7$next[0:0]$14110 $1\core_core_core_exc_$signal$6$next[0:0]$14109 $1\core_core_core_exc_$signal$5$next[0:0]$14108 $1\core_core_core_exc_$signal$4$next[0:0]$14107 $1\core_core_core_exc_$signal$3$next[0:0]$14106 $1\core_core_core_exc_$signal$next[0:0]$14113 $1\core_core_core_traptype$next[7:0]$14125 $1\core_core_core_input_carry$next[1:0]$14115 $1\core_core_core_oe_ok$next[0:0]$14121 $1\core_core_core_oe$next[0:0]$14120 $1\core_core_core_rc_ok$next[0:0]$14123 $1\core_core_core_rc$next[0:0]$14122 $1\core_core_lk$next[0:0]$14141 $1\core_core_core_fn_unit$next[13:0]$14114 $1\core_core_core_insn_type$next[6:0]$14117 $1\core_core_core_insn$next[31:0]$14116 $1\core_core_core_cia$next[63:0]$14102 $1\core_core_core_msr$next[63:0]$14119 $1\core_cr_out_ok$next[0:0]$14153 $1\core_core_cr_out$next[6:0]$14132 $1\core_core_cr_in2_ok$2$next[0:0]$14130 $1\core_core_cr_in2$1$next[6:0]$14128 $1\core_core_cr_in2_ok$next[0:0]$14131 $1\core_core_cr_in2$next[6:0]$14129 $1\core_core_cr_in1_ok$next[0:0]$14127 $1\core_core_cr_in1$next[6:0]$14126 $1\core_fasto2_ok$next[0:0]$14156 $1\core_core_fasto2$next[2:0]$14140 $1\core_fasto1_ok$next[0:0]$14155 $1\core_core_fasto1$next[2:0]$14139 $1\core_core_fast2_ok$next[0:0]$14138 $1\core_core_fast2$next[2:0]$14137 $1\core_core_fast1_ok$next[0:0]$14136 $1\core_core_fast1$next[2:0]$14135 $1\core_xer_out$next[0:0]$14159 $1\core_core_xer_in$next[2:0]$14152 $1\core_core_spr1_ok$next[0:0]$14150 $1\core_core_spr1$next[9:0]$14149 $1\core_spro_ok$next[0:0]$14158 $1\core_core_spro$next[9:0]$14151 $1\core_core_reg3_ok$next[0:0]$14147 $1\core_core_reg3$next[6:0]$14146 $1\core_core_reg2_ok$next[0:0]$14145 $1\core_core_reg2$next[6:0]$14144 $1\core_core_reg1_ok$next[0:0]$14143 $1\core_core_reg1$next[6:0]$14142 $1\core_ea_ok$next[0:0]$14154 $1\core_core_ea$next[6:0]$14134 $1\core_rego_ok$next[0:0]$14157 $1\core_core_rego$next[6:0]$14148 $1\core_asmcode$next[7:0]$14101 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + assign { $1\core_core_core_is_32bit$next[0:0]$14060 $1\core_core_cr_wr_ok$next[0:0]$14075 $1\core_core_core_cr_wr$next[7:0]$14047 $1\core_core_core_cr_rd_ok$next[0:0]$14046 $1\core_core_core_cr_rd$next[7:0]$14045 $1\core_core_core_trapaddr$next[12:0]$14066 $1\core_core_core_exc_$signal$9$next[0:0]$14054 $1\core_core_core_exc_$signal$8$next[0:0]$14053 $1\core_core_core_exc_$signal$7$next[0:0]$14052 $1\core_core_core_exc_$signal$6$next[0:0]$14051 $1\core_core_core_exc_$signal$5$next[0:0]$14050 $1\core_core_core_exc_$signal$4$next[0:0]$14049 $1\core_core_core_exc_$signal$3$next[0:0]$14048 $1\core_core_core_exc_$signal$next[0:0]$14055 $1\core_core_core_traptype$next[7:0]$14067 $1\core_core_core_input_carry$next[1:0]$14057 $1\core_core_core_oe_ok$next[0:0]$14063 $1\core_core_core_oe$next[0:0]$14062 $1\core_core_core_rc_ok$next[0:0]$14065 $1\core_core_core_rc$next[0:0]$14064 $1\core_core_lk$next[0:0]$14083 $1\core_core_core_fn_unit$next[13:0]$14056 $1\core_core_core_insn_type$next[6:0]$14059 $1\core_core_core_insn$next[31:0]$14058 $1\core_core_core_cia$next[63:0]$14044 $1\core_core_core_msr$next[63:0]$14061 $1\core_cr_out_ok$next[0:0]$14095 $1\core_core_cr_out$next[6:0]$14074 $1\core_core_cr_in2_ok$2$next[0:0]$14072 $1\core_core_cr_in2$1$next[6:0]$14070 $1\core_core_cr_in2_ok$next[0:0]$14073 $1\core_core_cr_in2$next[6:0]$14071 $1\core_core_cr_in1_ok$next[0:0]$14069 $1\core_core_cr_in1$next[6:0]$14068 $1\core_fasto2_ok$next[0:0]$14098 $1\core_core_fasto2$next[2:0]$14082 $1\core_fasto1_ok$next[0:0]$14097 $1\core_core_fasto1$next[2:0]$14081 $1\core_core_fast2_ok$next[0:0]$14080 $1\core_core_fast2$next[2:0]$14079 $1\core_core_fast1_ok$next[0:0]$14078 $1\core_core_fast1$next[2:0]$14077 $1\core_xer_out$next[0:0]$14101 $1\core_core_xer_in$next[2:0]$14094 $1\core_core_spr1_ok$next[0:0]$14092 $1\core_core_spr1$next[9:0]$14091 $1\core_spro_ok$next[0:0]$14100 $1\core_core_spro$next[9:0]$14093 $1\core_core_reg3_ok$next[0:0]$14089 $1\core_core_reg3$next[6:0]$14088 $1\core_core_reg2_ok$next[0:0]$14087 $1\core_core_reg2$next[6:0]$14086 $1\core_core_reg1_ok$next[0:0]$14085 $1\core_core_reg1$next[6:0]$14084 $1\core_ea_ok$next[0:0]$14096 $1\core_core_ea$next[6:0]$14076 $1\core_rego_ok$next[0:0]$14099 $1\core_core_rego$next[6:0]$14090 $1\core_asmcode$next[7:0]$14043 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } case - assign $1\core_asmcode$next[7:0]$14101 \core_asmcode - assign $1\core_core_core_cia$next[63:0]$14102 \core_core_core_cia - assign $1\core_core_core_cr_rd$next[7:0]$14103 \core_core_core_cr_rd - assign $1\core_core_core_cr_rd_ok$next[0:0]$14104 \core_core_core_cr_rd_ok - assign $1\core_core_core_cr_wr$next[7:0]$14105 \core_core_core_cr_wr - assign $1\core_core_core_exc_$signal$3$next[0:0]$14106 \core_core_core_exc_$signal$3 - assign $1\core_core_core_exc_$signal$4$next[0:0]$14107 \core_core_core_exc_$signal$4 - assign $1\core_core_core_exc_$signal$5$next[0:0]$14108 \core_core_core_exc_$signal$5 - assign $1\core_core_core_exc_$signal$6$next[0:0]$14109 \core_core_core_exc_$signal$6 - assign $1\core_core_core_exc_$signal$7$next[0:0]$14110 \core_core_core_exc_$signal$7 - assign $1\core_core_core_exc_$signal$8$next[0:0]$14111 \core_core_core_exc_$signal$8 - assign $1\core_core_core_exc_$signal$9$next[0:0]$14112 \core_core_core_exc_$signal$9 - assign $1\core_core_core_exc_$signal$next[0:0]$14113 \core_core_core_exc_$signal - assign $1\core_core_core_fn_unit$next[13:0]$14114 \core_core_core_fn_unit - assign $1\core_core_core_input_carry$next[1:0]$14115 \core_core_core_input_carry - assign $1\core_core_core_insn$next[31:0]$14116 \core_core_core_insn - assign $1\core_core_core_insn_type$next[6:0]$14117 \core_core_core_insn_type - assign $1\core_core_core_is_32bit$next[0:0]$14118 \core_core_core_is_32bit - assign $1\core_core_core_msr$next[63:0]$14119 \core_core_core_msr - assign $1\core_core_core_oe$next[0:0]$14120 \core_core_core_oe - assign $1\core_core_core_oe_ok$next[0:0]$14121 \core_core_core_oe_ok - assign $1\core_core_core_rc$next[0:0]$14122 \core_core_core_rc - assign $1\core_core_core_rc_ok$next[0:0]$14123 \core_core_core_rc_ok - assign $1\core_core_core_trapaddr$next[12:0]$14124 \core_core_core_trapaddr - assign $1\core_core_core_traptype$next[7:0]$14125 \core_core_core_traptype - assign $1\core_core_cr_in1$next[6:0]$14126 \core_core_cr_in1 - assign $1\core_core_cr_in1_ok$next[0:0]$14127 \core_core_cr_in1_ok - assign $1\core_core_cr_in2$1$next[6:0]$14128 \core_core_cr_in2$1 - assign $1\core_core_cr_in2$next[6:0]$14129 \core_core_cr_in2 - assign $1\core_core_cr_in2_ok$2$next[0:0]$14130 \core_core_cr_in2_ok$2 - assign $1\core_core_cr_in2_ok$next[0:0]$14131 \core_core_cr_in2_ok - assign $1\core_core_cr_out$next[6:0]$14132 \core_core_cr_out - assign $1\core_core_cr_wr_ok$next[0:0]$14133 \core_core_cr_wr_ok - assign $1\core_core_ea$next[6:0]$14134 \core_core_ea - assign $1\core_core_fast1$next[2:0]$14135 \core_core_fast1 - assign $1\core_core_fast1_ok$next[0:0]$14136 \core_core_fast1_ok - assign $1\core_core_fast2$next[2:0]$14137 \core_core_fast2 - assign $1\core_core_fast2_ok$next[0:0]$14138 \core_core_fast2_ok - assign $1\core_core_fasto1$next[2:0]$14139 \core_core_fasto1 - assign $1\core_core_fasto2$next[2:0]$14140 \core_core_fasto2 - assign $1\core_core_lk$next[0:0]$14141 \core_core_lk - assign $1\core_core_reg1$next[6:0]$14142 \core_core_reg1 - assign $1\core_core_reg1_ok$next[0:0]$14143 \core_core_reg1_ok - assign $1\core_core_reg2$next[6:0]$14144 \core_core_reg2 - assign $1\core_core_reg2_ok$next[0:0]$14145 \core_core_reg2_ok - assign $1\core_core_reg3$next[6:0]$14146 \core_core_reg3 - assign $1\core_core_reg3_ok$next[0:0]$14147 \core_core_reg3_ok - assign $1\core_core_rego$next[6:0]$14148 \core_core_rego - assign $1\core_core_spr1$next[9:0]$14149 \core_core_spr1 - assign $1\core_core_spr1_ok$next[0:0]$14150 \core_core_spr1_ok - assign $1\core_core_spro$next[9:0]$14151 \core_core_spro - assign $1\core_core_xer_in$next[2:0]$14152 \core_core_xer_in - assign $1\core_cr_out_ok$next[0:0]$14153 \core_cr_out_ok - assign $1\core_ea_ok$next[0:0]$14154 \core_ea_ok - assign $1\core_fasto1_ok$next[0:0]$14155 \core_fasto1_ok - assign $1\core_fasto2_ok$next[0:0]$14156 \core_fasto2_ok - assign $1\core_rego_ok$next[0:0]$14157 \core_rego_ok - assign $1\core_spro_ok$next[0:0]$14158 \core_spro_ok - assign $1\core_xer_out$next[0:0]$14159 \core_xer_out + assign $1\core_asmcode$next[7:0]$14043 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$14044 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$14045 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$14046 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$14047 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$14048 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14049 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14050 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14051 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14052 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14053 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14054 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$14055 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$14056 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$14057 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$14058 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$14059 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$14060 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$14061 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$14062 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$14063 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$14064 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$14065 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$14066 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$14067 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$14068 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$14069 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$14070 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$14071 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14072 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$14073 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$14074 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$14075 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$14076 \core_core_ea + assign $1\core_core_fast1$next[2:0]$14077 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$14078 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$14079 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$14080 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$14081 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$14082 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$14083 \core_core_lk + assign $1\core_core_reg1$next[6:0]$14084 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$14085 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$14086 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$14087 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$14088 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$14089 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$14090 \core_core_rego + assign $1\core_core_spr1$next[9:0]$14091 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$14092 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$14093 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$14094 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$14095 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$14096 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$14097 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$14098 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$14099 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$14100 \core_spro_ok + assign $1\core_xer_out$next[0:0]$14101 \core_xer_out end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -416458,243 +411683,289 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $3\core_rego_ok$next[0:0]$14244 1'0 - assign $3\core_ea_ok$next[0:0]$14241 1'0 - assign $3\core_core_reg1_ok$next[0:0]$14236 1'0 - assign $3\core_core_reg2_ok$next[0:0]$14237 1'0 - assign $3\core_core_reg3_ok$next[0:0]$14238 1'0 - assign $3\core_spro_ok$next[0:0]$14245 1'0 - assign $3\core_core_spr1_ok$next[0:0]$14239 1'0 - assign $3\core_core_fast1_ok$next[0:0]$14234 1'0 - assign $3\core_core_fast2_ok$next[0:0]$14235 1'0 - assign $3\core_fasto1_ok$next[0:0]$14242 1'0 - assign $3\core_fasto2_ok$next[0:0]$14243 1'0 - assign $3\core_core_cr_in1_ok$next[0:0]$14230 1'0 - assign $3\core_core_cr_in2_ok$next[0:0]$14232 1'0 - assign $3\core_core_cr_in2_ok$2$next[0:0]$14231 1'0 - assign $3\core_cr_out_ok$next[0:0]$14240 1'0 - assign $3\core_core_core_rc_ok$next[0:0]$14229 1'0 - assign $3\core_core_core_oe_ok$next[0:0]$14228 1'0 - assign $3\core_core_core_exc_$signal$next[0:0]$14227 1'0 - assign $3\core_core_core_exc_$signal$3$next[0:0]$14220 1'0 - assign $3\core_core_core_exc_$signal$4$next[0:0]$14221 1'0 - assign $3\core_core_core_exc_$signal$5$next[0:0]$14222 1'0 - assign $3\core_core_core_exc_$signal$6$next[0:0]$14223 1'0 - assign $3\core_core_core_exc_$signal$7$next[0:0]$14224 1'0 - assign $3\core_core_core_exc_$signal$8$next[0:0]$14225 1'0 - assign $3\core_core_core_exc_$signal$9$next[0:0]$14226 1'0 - assign $3\core_core_core_cr_rd_ok$next[0:0]$14219 1'0 - assign $3\core_core_cr_wr_ok$next[0:0]$14233 1'0 - case - assign $3\core_core_core_cr_rd_ok$next[0:0]$14219 $1\core_core_core_cr_rd_ok$next[0:0]$14104 - assign $3\core_core_core_exc_$signal$3$next[0:0]$14220 $1\core_core_core_exc_$signal$3$next[0:0]$14106 - assign $3\core_core_core_exc_$signal$4$next[0:0]$14221 $1\core_core_core_exc_$signal$4$next[0:0]$14107 - assign $3\core_core_core_exc_$signal$5$next[0:0]$14222 $1\core_core_core_exc_$signal$5$next[0:0]$14108 - assign $3\core_core_core_exc_$signal$6$next[0:0]$14223 $1\core_core_core_exc_$signal$6$next[0:0]$14109 - assign $3\core_core_core_exc_$signal$7$next[0:0]$14224 $1\core_core_core_exc_$signal$7$next[0:0]$14110 - assign $3\core_core_core_exc_$signal$8$next[0:0]$14225 $1\core_core_core_exc_$signal$8$next[0:0]$14111 - assign $3\core_core_core_exc_$signal$9$next[0:0]$14226 $1\core_core_core_exc_$signal$9$next[0:0]$14112 - assign $3\core_core_core_exc_$signal$next[0:0]$14227 $1\core_core_core_exc_$signal$next[0:0]$14113 - assign $3\core_core_core_oe_ok$next[0:0]$14228 $1\core_core_core_oe_ok$next[0:0]$14121 - assign $3\core_core_core_rc_ok$next[0:0]$14229 $1\core_core_core_rc_ok$next[0:0]$14123 - assign $3\core_core_cr_in1_ok$next[0:0]$14230 $1\core_core_cr_in1_ok$next[0:0]$14127 - assign $3\core_core_cr_in2_ok$2$next[0:0]$14231 $1\core_core_cr_in2_ok$2$next[0:0]$14130 - assign $3\core_core_cr_in2_ok$next[0:0]$14232 $1\core_core_cr_in2_ok$next[0:0]$14131 - assign $3\core_core_cr_wr_ok$next[0:0]$14233 $1\core_core_cr_wr_ok$next[0:0]$14133 - assign $3\core_core_fast1_ok$next[0:0]$14234 $1\core_core_fast1_ok$next[0:0]$14136 - assign $3\core_core_fast2_ok$next[0:0]$14235 $1\core_core_fast2_ok$next[0:0]$14138 - assign $3\core_core_reg1_ok$next[0:0]$14236 $1\core_core_reg1_ok$next[0:0]$14143 - assign $3\core_core_reg2_ok$next[0:0]$14237 $1\core_core_reg2_ok$next[0:0]$14145 - assign $3\core_core_reg3_ok$next[0:0]$14238 $1\core_core_reg3_ok$next[0:0]$14147 - assign $3\core_core_spr1_ok$next[0:0]$14239 $1\core_core_spr1_ok$next[0:0]$14150 - assign $3\core_cr_out_ok$next[0:0]$14240 $1\core_cr_out_ok$next[0:0]$14153 - assign $3\core_ea_ok$next[0:0]$14241 $1\core_ea_ok$next[0:0]$14154 - assign $3\core_fasto1_ok$next[0:0]$14242 $1\core_fasto1_ok$next[0:0]$14155 - assign $3\core_fasto2_ok$next[0:0]$14243 $1\core_fasto2_ok$next[0:0]$14156 - assign $3\core_rego_ok$next[0:0]$14244 $1\core_rego_ok$next[0:0]$14157 - assign $3\core_spro_ok$next[0:0]$14245 $1\core_spro_ok$next[0:0]$14158 - end - sync always - update \core_asmcode$next $0\core_asmcode$next[7:0]$14042 - update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$14043 - update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$14044 - update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$14045 - update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$14046 - update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$14047 - update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$14048 - update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$14049 - update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$14050 - update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$14051 - update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$14052 - update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$14053 - update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$14054 - update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$14055 - update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$14056 - update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$14057 - update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$14058 - update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$14059 - update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$14060 - update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$14061 - update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$14062 - update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$14063 - update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$14064 - update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$14065 - update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$14066 - update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$14067 - update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$14068 - update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$14069 - update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$14070 - update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$14071 - update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$14072 - update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$14073 - update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$14074 - update \core_core_ea$next $0\core_core_ea$next[6:0]$14075 - update \core_core_fast1$next $0\core_core_fast1$next[2:0]$14076 - update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$14077 - update \core_core_fast2$next $0\core_core_fast2$next[2:0]$14078 - update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$14079 - update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$14080 - update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$14081 - update \core_core_lk$next $0\core_core_lk$next[0:0]$14082 - update \core_core_reg1$next $0\core_core_reg1$next[6:0]$14083 - update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$14084 - update \core_core_reg2$next $0\core_core_reg2$next[6:0]$14085 - update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$14086 - update \core_core_reg3$next $0\core_core_reg3$next[6:0]$14087 - update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$14088 - update \core_core_rego$next $0\core_core_rego$next[6:0]$14089 - update \core_core_spr1$next $0\core_core_spr1$next[9:0]$14090 - update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$14091 - update \core_core_spro$next $0\core_core_spro$next[9:0]$14092 - update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$14093 - update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$14094 - update \core_ea_ok$next $0\core_ea_ok$next[0:0]$14095 - update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$14096 - update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$14097 - update \core_rego_ok$next $0\core_rego_ok$next[0:0]$14098 - update \core_spro_ok$next $0\core_spro_ok$next[0:0]$14099 - update \core_xer_out$next $0\core_xer_out$next[0:0]$14100 - end - connect \$101 $add$libresoc.v:197083$13545_Y - connect \$103 $mul$libresoc.v:197084$13546_Y - connect \$99 $shr$libresoc.v:197085$13547_Y [31:0] - connect \$106 $not$libresoc.v:197086$13548_Y - connect \$108 $not$libresoc.v:197087$13549_Y - connect \$110 $and$libresoc.v:197088$13550_Y - connect \$112 $not$libresoc.v:197089$13551_Y - connect \$114 $not$libresoc.v:197090$13552_Y - connect \$116 $and$libresoc.v:197091$13553_Y - connect \$118 $or$libresoc.v:197092$13554_Y + assign $3\core_rego_ok$next[0:0]$14186 1'0 + assign $3\core_ea_ok$next[0:0]$14183 1'0 + assign $3\core_core_reg1_ok$next[0:0]$14178 1'0 + assign $3\core_core_reg2_ok$next[0:0]$14179 1'0 + assign $3\core_core_reg3_ok$next[0:0]$14180 1'0 + assign $3\core_spro_ok$next[0:0]$14187 1'0 + assign $3\core_core_spr1_ok$next[0:0]$14181 1'0 + assign $3\core_core_fast1_ok$next[0:0]$14176 1'0 + assign $3\core_core_fast2_ok$next[0:0]$14177 1'0 + assign $3\core_fasto1_ok$next[0:0]$14184 1'0 + assign $3\core_fasto2_ok$next[0:0]$14185 1'0 + assign $3\core_core_cr_in1_ok$next[0:0]$14172 1'0 + assign $3\core_core_cr_in2_ok$next[0:0]$14174 1'0 + assign $3\core_core_cr_in2_ok$2$next[0:0]$14173 1'0 + assign $3\core_cr_out_ok$next[0:0]$14182 1'0 + assign $3\core_core_core_rc_ok$next[0:0]$14171 1'0 + assign $3\core_core_core_oe_ok$next[0:0]$14170 1'0 + assign $3\core_core_core_exc_$signal$next[0:0]$14169 1'0 + assign $3\core_core_core_exc_$signal$3$next[0:0]$14162 1'0 + assign $3\core_core_core_exc_$signal$4$next[0:0]$14163 1'0 + assign $3\core_core_core_exc_$signal$5$next[0:0]$14164 1'0 + assign $3\core_core_core_exc_$signal$6$next[0:0]$14165 1'0 + assign $3\core_core_core_exc_$signal$7$next[0:0]$14166 1'0 + assign $3\core_core_core_exc_$signal$8$next[0:0]$14167 1'0 + assign $3\core_core_core_exc_$signal$9$next[0:0]$14168 1'0 + assign $3\core_core_core_cr_rd_ok$next[0:0]$14161 1'0 + assign $3\core_core_cr_wr_ok$next[0:0]$14175 1'0 + case + assign $3\core_core_core_cr_rd_ok$next[0:0]$14161 $1\core_core_core_cr_rd_ok$next[0:0]$14046 + assign $3\core_core_core_exc_$signal$3$next[0:0]$14162 $1\core_core_core_exc_$signal$3$next[0:0]$14048 + assign $3\core_core_core_exc_$signal$4$next[0:0]$14163 $1\core_core_core_exc_$signal$4$next[0:0]$14049 + assign $3\core_core_core_exc_$signal$5$next[0:0]$14164 $1\core_core_core_exc_$signal$5$next[0:0]$14050 + assign $3\core_core_core_exc_$signal$6$next[0:0]$14165 $1\core_core_core_exc_$signal$6$next[0:0]$14051 + assign $3\core_core_core_exc_$signal$7$next[0:0]$14166 $1\core_core_core_exc_$signal$7$next[0:0]$14052 + assign $3\core_core_core_exc_$signal$8$next[0:0]$14167 $1\core_core_core_exc_$signal$8$next[0:0]$14053 + assign $3\core_core_core_exc_$signal$9$next[0:0]$14168 $1\core_core_core_exc_$signal$9$next[0:0]$14054 + assign $3\core_core_core_exc_$signal$next[0:0]$14169 $1\core_core_core_exc_$signal$next[0:0]$14055 + assign $3\core_core_core_oe_ok$next[0:0]$14170 $1\core_core_core_oe_ok$next[0:0]$14063 + assign $3\core_core_core_rc_ok$next[0:0]$14171 $1\core_core_core_rc_ok$next[0:0]$14065 + assign $3\core_core_cr_in1_ok$next[0:0]$14172 $1\core_core_cr_in1_ok$next[0:0]$14069 + assign $3\core_core_cr_in2_ok$2$next[0:0]$14173 $1\core_core_cr_in2_ok$2$next[0:0]$14072 + assign $3\core_core_cr_in2_ok$next[0:0]$14174 $1\core_core_cr_in2_ok$next[0:0]$14073 + assign $3\core_core_cr_wr_ok$next[0:0]$14175 $1\core_core_cr_wr_ok$next[0:0]$14075 + assign $3\core_core_fast1_ok$next[0:0]$14176 $1\core_core_fast1_ok$next[0:0]$14078 + assign $3\core_core_fast2_ok$next[0:0]$14177 $1\core_core_fast2_ok$next[0:0]$14080 + assign $3\core_core_reg1_ok$next[0:0]$14178 $1\core_core_reg1_ok$next[0:0]$14085 + assign $3\core_core_reg2_ok$next[0:0]$14179 $1\core_core_reg2_ok$next[0:0]$14087 + assign $3\core_core_reg3_ok$next[0:0]$14180 $1\core_core_reg3_ok$next[0:0]$14089 + assign $3\core_core_spr1_ok$next[0:0]$14181 $1\core_core_spr1_ok$next[0:0]$14092 + assign $3\core_cr_out_ok$next[0:0]$14182 $1\core_cr_out_ok$next[0:0]$14095 + assign $3\core_ea_ok$next[0:0]$14183 $1\core_ea_ok$next[0:0]$14096 + assign $3\core_fasto1_ok$next[0:0]$14184 $1\core_fasto1_ok$next[0:0]$14097 + assign $3\core_fasto2_ok$next[0:0]$14185 $1\core_fasto2_ok$next[0:0]$14098 + assign $3\core_rego_ok$next[0:0]$14186 $1\core_rego_ok$next[0:0]$14099 + assign $3\core_spro_ok$next[0:0]$14187 $1\core_spro_ok$next[0:0]$14100 + end + sync always + update \core_asmcode$next $0\core_asmcode$next[7:0]$13984 + update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13985 + update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13986 + update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13987 + update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13988 + update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13989 + update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13990 + update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13991 + update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13992 + update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13993 + update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13994 + update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13995 + update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13996 + update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$13997 + update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13998 + update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13999 + update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$14000 + update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$14001 + update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$14002 + update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$14003 + update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$14004 + update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$14005 + update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$14006 + update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$14007 + update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$14008 + update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$14009 + update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$14010 + update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$14011 + update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$14012 + update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$14013 + update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$14014 + update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$14015 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$14016 + update \core_core_ea$next $0\core_core_ea$next[6:0]$14017 + update \core_core_fast1$next $0\core_core_fast1$next[2:0]$14018 + update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$14019 + update \core_core_fast2$next $0\core_core_fast2$next[2:0]$14020 + update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$14021 + update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$14022 + update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$14023 + update \core_core_lk$next $0\core_core_lk$next[0:0]$14024 + update \core_core_reg1$next $0\core_core_reg1$next[6:0]$14025 + update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$14026 + update \core_core_reg2$next $0\core_core_reg2$next[6:0]$14027 + update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$14028 + update \core_core_reg3$next $0\core_core_reg3$next[6:0]$14029 + update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$14030 + update \core_core_rego$next $0\core_core_rego$next[6:0]$14031 + update \core_core_spr1$next $0\core_core_spr1$next[9:0]$14032 + update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$14033 + update \core_core_spro$next $0\core_core_spro$next[9:0]$14034 + update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$14035 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$14036 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$14037 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$14038 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$14039 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$14040 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$14041 + update \core_xer_out$next $0\core_xer_out$next[0:0]$14042 + end + attribute \src "libresoc.v:198997.3-199005.6" + process $proc$libresoc.v:198997$14188 + assign { } { } + assign { } { } + assign $0\dec2_cur_eint$next[0:0]$14189 $1\dec2_cur_eint$next[0:0]$14190 + attribute \src "libresoc.v:198998.5-198998.29" + switch \initial + attribute \src "libresoc.v:198998.9-198998.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dec2_cur_eint$next[0:0]$14190 1'0 + case + assign $1\dec2_cur_eint$next[0:0]$14190 \xics_icp_core_irq_o + end + sync always + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$14189 + end + attribute \src "libresoc.v:199006.3-199015.6" + process $proc$libresoc.v:199006$14191 + assign { } { } + assign { } { } + assign $0\delay$next[1:0]$14192 $1\delay$next[1:0]$14193 + attribute \src "libresoc.v:199007.5-199007.29" + switch \initial + attribute \src "libresoc.v:199007.9-199007.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\delay$next[1:0]$14193 \$25 [1:0] + case + assign $1\delay$next[1:0]$14193 \delay + end + sync always + update \delay$next $0\delay$next[1:0]$14192 + end + connect \$101 $add$libresoc.v:196328$13493_Y + connect \$103 $mul$libresoc.v:196329$13494_Y + connect \$99 $shr$libresoc.v:196330$13495_Y [31:0] + connect \$106 $not$libresoc.v:196331$13496_Y + connect \$108 $not$libresoc.v:196332$13497_Y + connect \$110 $and$libresoc.v:196333$13498_Y + connect \$112 $not$libresoc.v:196334$13499_Y + connect \$114 $not$libresoc.v:196335$13500_Y + connect \$116 $and$libresoc.v:196336$13501_Y + connect \$118 $or$libresoc.v:196337$13502_Y connect \$120 1'1 - connect \$122 $or$libresoc.v:197094$13555_Y - connect \$125 $add$libresoc.v:197095$13556_Y - connect \$128 $add$libresoc.v:197096$13557_Y - connect \$130 $not$libresoc.v:197097$13558_Y - connect \$132 $not$libresoc.v:197098$13559_Y - connect \$134 $and$libresoc.v:197099$13560_Y - connect \$136 $not$libresoc.v:197100$13561_Y - connect \$138 $not$libresoc.v:197101$13562_Y - connect \$140 $and$libresoc.v:197102$13563_Y - connect \$142 $eq$libresoc.v:197103$13564_Y - connect \$144 $and$libresoc.v:197104$13565_Y - connect \$146 $not$libresoc.v:197105$13566_Y - connect \$148 $not$libresoc.v:197106$13567_Y - connect \$150 $and$libresoc.v:197107$13568_Y - connect \$152 $or$libresoc.v:197108$13569_Y + connect \$122 $or$libresoc.v:196339$13503_Y + connect \$125 $add$libresoc.v:196340$13504_Y + connect \$128 $add$libresoc.v:196341$13505_Y + connect \$130 $not$libresoc.v:196342$13506_Y + connect \$132 $not$libresoc.v:196343$13507_Y + connect \$134 $and$libresoc.v:196344$13508_Y + connect \$136 $not$libresoc.v:196345$13509_Y + connect \$138 $not$libresoc.v:196346$13510_Y + connect \$140 $and$libresoc.v:196347$13511_Y + connect \$142 $eq$libresoc.v:196348$13512_Y + connect \$144 $and$libresoc.v:196349$13513_Y + connect \$146 $not$libresoc.v:196350$13514_Y + connect \$148 $not$libresoc.v:196351$13515_Y + connect \$150 $and$libresoc.v:196352$13516_Y + connect \$152 $or$libresoc.v:196353$13517_Y connect \$154 1'1 - connect \$156 $or$libresoc.v:197110$13570_Y - connect \$158 $not$libresoc.v:197111$13571_Y - connect \$160 $not$libresoc.v:197112$13572_Y - connect \$162 $and$libresoc.v:197113$13573_Y - connect \$164 $not$libresoc.v:197114$13574_Y - connect \$166 $not$libresoc.v:197115$13575_Y - connect \$168 $and$libresoc.v:197116$13576_Y - connect \$170 $not$libresoc.v:197117$13577_Y - connect \$172 $not$libresoc.v:197118$13578_Y - connect \$174 $and$libresoc.v:197119$13579_Y - connect \$176 $not$libresoc.v:197120$13580_Y - connect \$178 $not$libresoc.v:197121$13581_Y - connect \$180 $and$libresoc.v:197122$13582_Y - connect \$182 $not$libresoc.v:197123$13583_Y - connect \$184 $not$libresoc.v:197124$13584_Y - connect \$186 $and$libresoc.v:197125$13585_Y - connect \$188 $not$libresoc.v:197126$13586_Y - connect \$190 $not$libresoc.v:197127$13587_Y - connect \$192 $and$libresoc.v:197128$13588_Y - connect \$195 $and$libresoc.v:197129$13589_Y - connect \$194 $reduce_or$libresoc.v:197130$13590_Y - connect \$198 $not$libresoc.v:197131$13591_Y - connect \$200 $not$libresoc.v:197132$13592_Y - connect \$202 $and$libresoc.v:197133$13593_Y - connect \$204 $not$libresoc.v:197134$13594_Y - connect \$206 $not$libresoc.v:197135$13595_Y - connect \$208 $and$libresoc.v:197136$13596_Y - connect \$210 $or$libresoc.v:197137$13597_Y + connect \$156 $or$libresoc.v:196355$13518_Y + connect \$158 $not$libresoc.v:196356$13519_Y + connect \$160 $not$libresoc.v:196357$13520_Y + connect \$162 $and$libresoc.v:196358$13521_Y + connect \$164 $not$libresoc.v:196359$13522_Y + connect \$166 $not$libresoc.v:196360$13523_Y + connect \$168 $and$libresoc.v:196361$13524_Y + connect \$170 $not$libresoc.v:196362$13525_Y + connect \$172 $not$libresoc.v:196363$13526_Y + connect \$174 $and$libresoc.v:196364$13527_Y + connect \$176 $not$libresoc.v:196365$13528_Y + connect \$178 $not$libresoc.v:196366$13529_Y + connect \$180 $and$libresoc.v:196367$13530_Y + connect \$182 $not$libresoc.v:196368$13531_Y + connect \$184 $not$libresoc.v:196369$13532_Y + connect \$186 $and$libresoc.v:196370$13533_Y + connect \$188 $not$libresoc.v:196371$13534_Y + connect \$190 $not$libresoc.v:196372$13535_Y + connect \$192 $and$libresoc.v:196373$13536_Y + connect \$195 $and$libresoc.v:196374$13537_Y + connect \$194 $reduce_or$libresoc.v:196375$13538_Y + connect \$198 $not$libresoc.v:196376$13539_Y + connect \$200 $not$libresoc.v:196377$13540_Y + connect \$202 $and$libresoc.v:196378$13541_Y + connect \$204 $not$libresoc.v:196379$13542_Y + connect \$206 $not$libresoc.v:196380$13543_Y + connect \$208 $and$libresoc.v:196381$13544_Y + connect \$210 $or$libresoc.v:196382$13545_Y connect \$212 1'1 - connect \$214 $or$libresoc.v:197139$13598_Y - connect \$216 $not$libresoc.v:197140$13599_Y - connect \$218 $not$libresoc.v:197141$13600_Y - connect \$220 $and$libresoc.v:197142$13601_Y - connect \$222 $not$libresoc.v:197143$13602_Y - connect \$224 $not$libresoc.v:197144$13603_Y - connect \$226 $and$libresoc.v:197145$13604_Y - connect \$229 $and$libresoc.v:197146$13605_Y - connect \$228 $reduce_or$libresoc.v:197147$13606_Y - connect \$232 $eq$libresoc.v:197148$13607_Y - connect \$234 $and$libresoc.v:197149$13608_Y - connect \$236 $not$libresoc.v:197150$13609_Y - connect \$238 $not$libresoc.v:197151$13610_Y - connect \$23 $ne$libresoc.v:197152$13611_Y - connect \$240 $not$libresoc.v:197153$13612_Y - connect \$242 $and$libresoc.v:197154$13613_Y - connect \$244 $not$libresoc.v:197155$13614_Y - connect \$246 $not$libresoc.v:197156$13615_Y - connect \$248 $and$libresoc.v:197157$13616_Y - connect \$250 $eq$libresoc.v:197158$13617_Y - connect \$252 $pos$libresoc.v:197159$13618_Y - connect \$254 $ne$libresoc.v:197160$13619_Y - connect \$256 $not$libresoc.v:197161$13620_Y - connect \$258 $not$libresoc.v:197162$13621_Y - connect \$260 $pos$libresoc.v:197163$13623_Y - connect \$262 $pos$libresoc.v:197164$13625_Y - connect \$265 $sub$libresoc.v:197165$13626_Y - connect \$268 $add$libresoc.v:197166$13627_Y - connect \$26 $sub$libresoc.v:197167$13628_Y - connect \$28 $or$libresoc.v:197168$13629_Y - connect \$30 $or$libresoc.v:197169$13630_Y - connect \$32 $ne$libresoc.v:197170$13631_Y - connect \$34 $not$libresoc.v:197171$13632_Y - connect \$36 $and$libresoc.v:197172$13633_Y - connect \$38 $not$libresoc.v:197173$13634_Y - connect \$40 $not$libresoc.v:197174$13635_Y - connect \$42 $pos$libresoc.v:197175$13637_Y - connect \$44 $not$libresoc.v:197176$13638_Y - connect \$46 $not$libresoc.v:197177$13639_Y - connect \$48 $and$libresoc.v:197178$13640_Y - connect \$50 $eq$libresoc.v:197179$13641_Y - connect \$52 $and$libresoc.v:197180$13642_Y - connect \$54 $not$libresoc.v:197181$13643_Y - connect \$56 $not$libresoc.v:197182$13644_Y - connect \$58 $and$libresoc.v:197183$13645_Y - connect \$60 $or$libresoc.v:197184$13646_Y + connect \$214 $or$libresoc.v:196384$13546_Y + connect \$216 $not$libresoc.v:196385$13547_Y + connect \$218 $not$libresoc.v:196386$13548_Y + connect \$220 $and$libresoc.v:196387$13549_Y + connect \$222 $not$libresoc.v:196388$13550_Y + connect \$224 $not$libresoc.v:196389$13551_Y + connect \$226 $and$libresoc.v:196390$13552_Y + connect \$229 $and$libresoc.v:196391$13553_Y + connect \$228 $reduce_or$libresoc.v:196392$13554_Y + connect \$232 $eq$libresoc.v:196393$13555_Y + connect \$234 $and$libresoc.v:196394$13556_Y + connect \$236 $not$libresoc.v:196395$13557_Y + connect \$238 $not$libresoc.v:196396$13558_Y + connect \$23 $ne$libresoc.v:196397$13559_Y + connect \$240 $not$libresoc.v:196398$13560_Y + connect \$242 $and$libresoc.v:196399$13561_Y + connect \$244 $not$libresoc.v:196400$13562_Y + connect \$246 $not$libresoc.v:196401$13563_Y + connect \$248 $and$libresoc.v:196402$13564_Y + connect \$250 $eq$libresoc.v:196403$13565_Y + connect \$252 $pos$libresoc.v:196404$13566_Y + connect \$254 $ne$libresoc.v:196405$13567_Y + connect \$256 $not$libresoc.v:196406$13568_Y + connect \$258 $not$libresoc.v:196407$13569_Y + connect \$260 $pos$libresoc.v:196408$13571_Y + connect \$262 $pos$libresoc.v:196409$13573_Y + connect \$265 $sub$libresoc.v:196410$13574_Y + connect \$268 $add$libresoc.v:196411$13575_Y + connect \$26 $sub$libresoc.v:196412$13576_Y + connect \$28 $or$libresoc.v:196413$13577_Y + connect \$30 $or$libresoc.v:196414$13578_Y + connect \$32 $ne$libresoc.v:196415$13579_Y + connect \$34 $not$libresoc.v:196416$13580_Y + connect \$36 $and$libresoc.v:196417$13581_Y + connect \$38 $not$libresoc.v:196418$13582_Y + connect \$40 $not$libresoc.v:196419$13583_Y + connect \$42 $pos$libresoc.v:196420$13585_Y + connect \$44 $not$libresoc.v:196421$13586_Y + connect \$46 $not$libresoc.v:196422$13587_Y + connect \$48 $and$libresoc.v:196423$13588_Y + connect \$50 $eq$libresoc.v:196424$13589_Y + connect \$52 $and$libresoc.v:196425$13590_Y + connect \$54 $not$libresoc.v:196426$13591_Y + connect \$56 $not$libresoc.v:196427$13592_Y + connect \$58 $and$libresoc.v:196428$13593_Y + connect \$60 $or$libresoc.v:196429$13594_Y connect \$62 1'1 - connect \$64 $or$libresoc.v:197186$13647_Y - connect \$66 $not$libresoc.v:197187$13648_Y - connect \$68 $not$libresoc.v:197188$13649_Y - connect \$70 $and$libresoc.v:197189$13650_Y - connect \$72 $eq$libresoc.v:197190$13651_Y - connect \$74 $and$libresoc.v:197191$13652_Y - connect \$76 $not$libresoc.v:197192$13653_Y - connect \$78 $not$libresoc.v:197193$13654_Y - connect \$80 $and$libresoc.v:197194$13655_Y - connect \$82 $or$libresoc.v:197195$13656_Y + connect \$64 $or$libresoc.v:196431$13595_Y + connect \$66 $not$libresoc.v:196432$13596_Y + connect \$68 $not$libresoc.v:196433$13597_Y + connect \$70 $and$libresoc.v:196434$13598_Y + connect \$72 $eq$libresoc.v:196435$13599_Y + connect \$74 $and$libresoc.v:196436$13600_Y + connect \$76 $not$libresoc.v:196437$13601_Y + connect \$78 $not$libresoc.v:196438$13602_Y + connect \$80 $and$libresoc.v:196439$13603_Y + connect \$82 $or$libresoc.v:196440$13604_Y connect \$84 1'1 - connect \$86 $or$libresoc.v:197197$13657_Y - connect \$88 $not$libresoc.v:197198$13658_Y - connect \$90 $not$libresoc.v:197199$13659_Y - connect \$93 $add$libresoc.v:197200$13660_Y - connect \$96 $mul$libresoc.v:197201$13661_Y - connect \$95 $shr$libresoc.v:197202$13662_Y [31:0] + connect \$86 $or$libresoc.v:196442$13605_Y + connect \$88 $not$libresoc.v:196443$13606_Y + connect \$90 $not$libresoc.v:196444$13607_Y + connect \$93 $add$libresoc.v:196445$13608_Y + connect \$96 $mul$libresoc.v:196446$13609_Y + connect \$95 $shr$libresoc.v:196447$13610_Y [31:0] connect \$25 \$26 connect \$92 \$93 connect \$100 \$101 @@ -416725,490 +411996,486 @@ module \ti connect \ti_rst \$32 connect \por_clk \clk connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } - connect \sram4k_3_enable \jtag_wb_sram_en - connect \sram4k_2_enable \jtag_wb_sram_en - connect \sram4k_1_enable \jtag_wb_sram_en - connect \sram4k_0_enable \jtag_wb_sram_en end -attribute \src "libresoc.v:199862.1-201053.10" +attribute \src "libresoc.v:199050.1-200241.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0" attribute \generator "nMigen" module \trap0 - attribute \src "libresoc.v:200598.3-200599.25" + attribute \src "libresoc.v:199786.3-199787.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:200596.3-200597.41" + attribute \src "libresoc.v:199784.3-199785.41" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:200956.3-200964.6" - wire $0\alu_l_r_alu$next[0:0]$14567 - attribute \src "libresoc.v:200524.3-200525.39" + attribute \src "libresoc.v:200144.3-200152.6" + wire $0\alu_l_r_alu$next[0:0]$14515 + attribute \src "libresoc.v:199712.3-199713.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14493 - attribute \src "libresoc.v:200564.3-200565.61" + attribute \src "libresoc.v:199967.3-199984.6" + wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14441 + attribute \src "libresoc.v:199752.3-199753.61" wire width 64 $0\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14494 - attribute \src "libresoc.v:200558.3-200559.69" + attribute \src "libresoc.v:199967.3-199984.6" + wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14442 + attribute \src "libresoc.v:199746.3-199747.69" wire width 14 $0\alu_trap0_trap_op__fn_unit[13:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14495 - attribute \src "libresoc.v:200560.3-200561.63" + attribute \src "libresoc.v:199967.3-199984.6" + wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14443 + attribute \src "libresoc.v:199748.3-199749.63" wire width 32 $0\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14496 - attribute \src "libresoc.v:200556.3-200557.73" + attribute \src "libresoc.v:199967.3-199984.6" + wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14444 + attribute \src "libresoc.v:199744.3-199745.73" wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14497 - attribute \src "libresoc.v:200566.3-200567.71" + attribute \src "libresoc.v:199967.3-199984.6" + wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14445 + attribute \src "libresoc.v:199754.3-199755.71" wire $0\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14498 - attribute \src "libresoc.v:200572.3-200573.71" + attribute \src "libresoc.v:199967.3-199984.6" + wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14446 + attribute \src "libresoc.v:199760.3-199761.71" wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14499 - attribute \src "libresoc.v:200562.3-200563.61" + attribute \src "libresoc.v:199967.3-199984.6" + wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14447 + attribute \src "libresoc.v:199750.3-199751.61" wire width 64 $0\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14500 - attribute \src "libresoc.v:200570.3-200571.71" + attribute \src "libresoc.v:199967.3-199984.6" + wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14448 + attribute \src "libresoc.v:199758.3-199759.71" wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14501 - attribute \src "libresoc.v:200568.3-200569.71" + attribute \src "libresoc.v:199967.3-199984.6" + wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14449 + attribute \src "libresoc.v:199756.3-199757.71" wire width 8 $0\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:200947.3-200955.6" - wire $0\alui_l_r_alui$next[0:0]$14564 - attribute \src "libresoc.v:200526.3-200527.43" + attribute \src "libresoc.v:200135.3-200143.6" + wire $0\alui_l_r_alui$next[0:0]$14512 + attribute \src "libresoc.v:199714.3-199715.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:200797.3-200818.6" - wire width 64 $0\data_r0__o$next[63:0]$14512 - attribute \src "libresoc.v:200552.3-200553.37" + attribute \src "libresoc.v:199985.3-200006.6" + wire width 64 $0\data_r0__o$next[63:0]$14460 + attribute \src "libresoc.v:199740.3-199741.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:200797.3-200818.6" - wire $0\data_r0__o_ok$next[0:0]$14513 - attribute \src "libresoc.v:200554.3-200555.43" + attribute \src "libresoc.v:199985.3-200006.6" + wire $0\data_r0__o_ok$next[0:0]$14461 + attribute \src "libresoc.v:199742.3-199743.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:200819.3-200840.6" - wire width 64 $0\data_r1__fast1$next[63:0]$14520 - attribute \src "libresoc.v:200548.3-200549.45" + attribute \src "libresoc.v:200007.3-200028.6" + wire width 64 $0\data_r1__fast1$next[63:0]$14468 + attribute \src "libresoc.v:199736.3-199737.45" wire width 64 $0\data_r1__fast1[63:0] - attribute \src "libresoc.v:200819.3-200840.6" - wire $0\data_r1__fast1_ok$next[0:0]$14521 - attribute \src "libresoc.v:200550.3-200551.51" + attribute \src "libresoc.v:200007.3-200028.6" + wire $0\data_r1__fast1_ok$next[0:0]$14469 + attribute \src "libresoc.v:199738.3-199739.51" wire $0\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:200841.3-200862.6" - wire width 64 $0\data_r2__fast2$next[63:0]$14528 - attribute \src "libresoc.v:200544.3-200545.45" + attribute \src "libresoc.v:200029.3-200050.6" + wire width 64 $0\data_r2__fast2$next[63:0]$14476 + attribute \src "libresoc.v:199732.3-199733.45" wire width 64 $0\data_r2__fast2[63:0] - attribute \src "libresoc.v:200841.3-200862.6" - wire $0\data_r2__fast2_ok$next[0:0]$14529 - attribute \src "libresoc.v:200546.3-200547.51" + attribute \src "libresoc.v:200029.3-200050.6" + wire $0\data_r2__fast2_ok$next[0:0]$14477 + attribute \src "libresoc.v:199734.3-199735.51" wire $0\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:200863.3-200884.6" - wire width 64 $0\data_r3__nia$next[63:0]$14536 - attribute \src "libresoc.v:200540.3-200541.41" + attribute \src "libresoc.v:200051.3-200072.6" + wire width 64 $0\data_r3__nia$next[63:0]$14484 + attribute \src "libresoc.v:199728.3-199729.41" wire width 64 $0\data_r3__nia[63:0] - attribute \src "libresoc.v:200863.3-200884.6" - wire $0\data_r3__nia_ok$next[0:0]$14537 - attribute \src "libresoc.v:200542.3-200543.47" + attribute \src "libresoc.v:200051.3-200072.6" + wire $0\data_r3__nia_ok$next[0:0]$14485 + attribute \src "libresoc.v:199730.3-199731.47" wire $0\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:200885.3-200906.6" - wire width 64 $0\data_r4__msr$next[63:0]$14544 - attribute \src "libresoc.v:200536.3-200537.41" + attribute \src "libresoc.v:200073.3-200094.6" + wire width 64 $0\data_r4__msr$next[63:0]$14492 + attribute \src "libresoc.v:199724.3-199725.41" wire width 64 $0\data_r4__msr[63:0] - attribute \src "libresoc.v:200885.3-200906.6" - wire $0\data_r4__msr_ok$next[0:0]$14545 - attribute \src "libresoc.v:200538.3-200539.47" + attribute \src "libresoc.v:200073.3-200094.6" + wire $0\data_r4__msr_ok$next[0:0]$14493 + attribute \src "libresoc.v:199726.3-199727.47" wire $0\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:200965.3-200974.6" + attribute \src "libresoc.v:200153.3-200162.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:200975.3-200984.6" + attribute \src "libresoc.v:200163.3-200172.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:200985.3-200994.6" + attribute \src "libresoc.v:200173.3-200182.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:200995.3-201004.6" + attribute \src "libresoc.v:200183.3-200192.6" wire width 64 $0\dest4_o[63:0] - attribute \src "libresoc.v:201005.3-201014.6" + attribute \src "libresoc.v:200193.3-200202.6" wire width 64 $0\dest5_o[63:0] - attribute \src "libresoc.v:199863.7-199863.20" + attribute \src "libresoc.v:199051.7-199051.20" wire $0\initial[0:0] - attribute \src "libresoc.v:200734.3-200742.6" - wire $0\opc_l_r_opc$next[0:0]$14478 - attribute \src "libresoc.v:200582.3-200583.39" + attribute \src "libresoc.v:199922.3-199930.6" + wire $0\opc_l_r_opc$next[0:0]$14426 + attribute \src "libresoc.v:199770.3-199771.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:200725.3-200733.6" - wire $0\opc_l_s_opc$next[0:0]$14475 - attribute \src "libresoc.v:200584.3-200585.39" + attribute \src "libresoc.v:199913.3-199921.6" + wire $0\opc_l_s_opc$next[0:0]$14423 + attribute \src "libresoc.v:199772.3-199773.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:201015.3-201023.6" - wire width 5 $0\prev_wr_go$next[4:0]$14575 - attribute \src "libresoc.v:200594.3-200595.37" + attribute \src "libresoc.v:200203.3-200211.6" + wire width 5 $0\prev_wr_go$next[4:0]$14523 + attribute \src "libresoc.v:199782.3-199783.37" wire width 5 $0\prev_wr_go[4:0] - attribute \src "libresoc.v:200679.3-200688.6" + attribute \src "libresoc.v:199867.3-199876.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:200770.3-200778.6" - wire width 5 $0\req_l_r_req$next[4:0]$14490 - attribute \src "libresoc.v:200574.3-200575.39" + attribute \src "libresoc.v:199958.3-199966.6" + wire width 5 $0\req_l_r_req$next[4:0]$14438 + attribute \src "libresoc.v:199762.3-199763.39" wire width 5 $0\req_l_r_req[4:0] - attribute \src "libresoc.v:200761.3-200769.6" - wire width 5 $0\req_l_s_req$next[4:0]$14487 - attribute \src "libresoc.v:200576.3-200577.39" + attribute \src "libresoc.v:199949.3-199957.6" + wire width 5 $0\req_l_s_req$next[4:0]$14435 + attribute \src "libresoc.v:199764.3-199765.39" wire width 5 $0\req_l_s_req[4:0] - attribute \src "libresoc.v:200698.3-200706.6" - wire $0\rok_l_r_rdok$next[0:0]$14466 - attribute \src "libresoc.v:200590.3-200591.41" + attribute \src "libresoc.v:199886.3-199894.6" + wire $0\rok_l_r_rdok$next[0:0]$14414 + attribute \src "libresoc.v:199778.3-199779.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:200689.3-200697.6" - wire $0\rok_l_s_rdok$next[0:0]$14463 - attribute \src "libresoc.v:200592.3-200593.41" + attribute \src "libresoc.v:199877.3-199885.6" + wire $0\rok_l_s_rdok$next[0:0]$14411 + attribute \src "libresoc.v:199780.3-199781.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:200716.3-200724.6" - wire $0\rst_l_r_rst$next[0:0]$14472 - attribute \src "libresoc.v:200586.3-200587.39" + attribute \src "libresoc.v:199904.3-199912.6" + wire $0\rst_l_r_rst$next[0:0]$14420 + attribute \src "libresoc.v:199774.3-199775.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:200707.3-200715.6" - wire $0\rst_l_s_rst$next[0:0]$14469 - attribute \src "libresoc.v:200588.3-200589.39" + attribute \src "libresoc.v:199895.3-199903.6" + wire $0\rst_l_s_rst$next[0:0]$14417 + attribute \src "libresoc.v:199776.3-199777.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:200752.3-200760.6" - wire width 4 $0\src_l_r_src$next[3:0]$14484 - attribute \src "libresoc.v:200578.3-200579.39" + attribute \src "libresoc.v:199940.3-199948.6" + wire width 4 $0\src_l_r_src$next[3:0]$14432 + attribute \src "libresoc.v:199766.3-199767.39" wire width 4 $0\src_l_r_src[3:0] - attribute \src "libresoc.v:200743.3-200751.6" - wire width 4 $0\src_l_s_src$next[3:0]$14481 - attribute \src "libresoc.v:200580.3-200581.39" + attribute \src "libresoc.v:199931.3-199939.6" + wire width 4 $0\src_l_s_src$next[3:0]$14429 + attribute \src "libresoc.v:199768.3-199769.39" wire width 4 $0\src_l_s_src[3:0] - attribute \src "libresoc.v:200907.3-200916.6" - wire width 64 $0\src_r0$next[63:0]$14552 - attribute \src "libresoc.v:200534.3-200535.29" + attribute \src "libresoc.v:200095.3-200104.6" + wire width 64 $0\src_r0$next[63:0]$14500 + attribute \src "libresoc.v:199722.3-199723.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:200917.3-200926.6" - wire width 64 $0\src_r1$next[63:0]$14555 - attribute \src "libresoc.v:200532.3-200533.29" + attribute \src "libresoc.v:200105.3-200114.6" + wire width 64 $0\src_r1$next[63:0]$14503 + attribute \src "libresoc.v:199720.3-199721.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:200927.3-200936.6" - wire width 64 $0\src_r2$next[63:0]$14558 - attribute \src "libresoc.v:200530.3-200531.29" + attribute \src "libresoc.v:200115.3-200124.6" + wire width 64 $0\src_r2$next[63:0]$14506 + attribute \src "libresoc.v:199718.3-199719.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:200937.3-200946.6" - wire width 64 $0\src_r3$next[63:0]$14561 - attribute \src "libresoc.v:200528.3-200529.29" + attribute \src "libresoc.v:200125.3-200134.6" + wire width 64 $0\src_r3$next[63:0]$14509 + attribute \src "libresoc.v:199716.3-199717.29" wire width 64 $0\src_r3[63:0] - attribute \src "libresoc.v:199989.7-199989.24" + attribute \src "libresoc.v:199177.7-199177.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:199999.7-199999.26" + attribute \src "libresoc.v:199187.7-199187.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:200956.3-200964.6" - wire $1\alu_l_r_alu$next[0:0]$14568 - attribute \src "libresoc.v:200007.7-200007.25" + attribute \src "libresoc.v:200144.3-200152.6" + wire $1\alu_l_r_alu$next[0:0]$14516 + attribute \src "libresoc.v:199195.7-199195.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14502 - attribute \src "libresoc.v:200043.14-200043.59" + attribute \src "libresoc.v:199967.3-199984.6" + wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14450 + attribute \src "libresoc.v:199231.14-199231.59" wire width 64 $1\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 - attribute \src "libresoc.v:200062.14-200062.51" + attribute \src "libresoc.v:199967.3-199984.6" + wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14451 + attribute \src "libresoc.v:199250.14-199250.51" wire width 14 $1\alu_trap0_trap_op__fn_unit[13:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14504 - attribute \src "libresoc.v:200066.14-200066.45" + attribute \src "libresoc.v:199967.3-199984.6" + wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14452 + attribute \src "libresoc.v:199254.14-199254.45" wire width 32 $1\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 - attribute \src "libresoc.v:200145.13-200145.49" + attribute \src "libresoc.v:199967.3-199984.6" + wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14453 + attribute \src "libresoc.v:199333.13-199333.49" wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 - attribute \src "libresoc.v:200149.7-200149.41" + attribute \src "libresoc.v:199967.3-199984.6" + wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14454 + attribute \src "libresoc.v:199337.7-199337.41" wire $1\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 - attribute \src "libresoc.v:200153.13-200153.48" + attribute \src "libresoc.v:199967.3-199984.6" + wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14455 + attribute \src "libresoc.v:199341.13-199341.48" wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14508 - attribute \src "libresoc.v:200157.14-200157.59" + attribute \src "libresoc.v:199967.3-199984.6" + wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14456 + attribute \src "libresoc.v:199345.14-199345.59" wire width 64 $1\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 - attribute \src "libresoc.v:200161.14-200161.52" + attribute \src "libresoc.v:199967.3-199984.6" + wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14457 + attribute \src "libresoc.v:199349.14-199349.52" wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:200779.3-200796.6" - wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14510 - attribute \src "libresoc.v:200165.13-200165.48" + attribute \src "libresoc.v:199967.3-199984.6" + wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14458 + attribute \src "libresoc.v:199353.13-199353.48" wire width 8 $1\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:200947.3-200955.6" - wire $1\alui_l_r_alui$next[0:0]$14565 - attribute \src "libresoc.v:200171.7-200171.27" + attribute \src "libresoc.v:200135.3-200143.6" + wire $1\alui_l_r_alui$next[0:0]$14513 + attribute \src "libresoc.v:199359.7-199359.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:200797.3-200818.6" - wire width 64 $1\data_r0__o$next[63:0]$14514 - attribute \src "libresoc.v:200203.14-200203.47" + attribute \src "libresoc.v:199985.3-200006.6" + wire width 64 $1\data_r0__o$next[63:0]$14462 + attribute \src "libresoc.v:199391.14-199391.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:200797.3-200818.6" - wire $1\data_r0__o_ok$next[0:0]$14515 - attribute \src "libresoc.v:200207.7-200207.27" + attribute \src "libresoc.v:199985.3-200006.6" + wire $1\data_r0__o_ok$next[0:0]$14463 + attribute \src "libresoc.v:199395.7-199395.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:200819.3-200840.6" - wire width 64 $1\data_r1__fast1$next[63:0]$14522 - attribute \src "libresoc.v:200211.14-200211.51" + attribute \src "libresoc.v:200007.3-200028.6" + wire width 64 $1\data_r1__fast1$next[63:0]$14470 + attribute \src "libresoc.v:199399.14-199399.51" wire width 64 $1\data_r1__fast1[63:0] - attribute \src "libresoc.v:200819.3-200840.6" - wire $1\data_r1__fast1_ok$next[0:0]$14523 - attribute \src "libresoc.v:200215.7-200215.31" + attribute \src "libresoc.v:200007.3-200028.6" + wire $1\data_r1__fast1_ok$next[0:0]$14471 + attribute \src "libresoc.v:199403.7-199403.31" wire $1\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:200841.3-200862.6" - wire width 64 $1\data_r2__fast2$next[63:0]$14530 - attribute \src "libresoc.v:200219.14-200219.51" + attribute \src "libresoc.v:200029.3-200050.6" + wire width 64 $1\data_r2__fast2$next[63:0]$14478 + attribute \src "libresoc.v:199407.14-199407.51" wire width 64 $1\data_r2__fast2[63:0] - attribute \src "libresoc.v:200841.3-200862.6" - wire $1\data_r2__fast2_ok$next[0:0]$14531 - attribute \src "libresoc.v:200223.7-200223.31" + attribute \src "libresoc.v:200029.3-200050.6" + wire $1\data_r2__fast2_ok$next[0:0]$14479 + attribute \src "libresoc.v:199411.7-199411.31" wire $1\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:200863.3-200884.6" - wire width 64 $1\data_r3__nia$next[63:0]$14538 - attribute \src "libresoc.v:200227.14-200227.49" + attribute \src "libresoc.v:200051.3-200072.6" + wire width 64 $1\data_r3__nia$next[63:0]$14486 + attribute \src "libresoc.v:199415.14-199415.49" wire width 64 $1\data_r3__nia[63:0] - attribute \src "libresoc.v:200863.3-200884.6" - wire $1\data_r3__nia_ok$next[0:0]$14539 - attribute \src "libresoc.v:200231.7-200231.29" + attribute \src "libresoc.v:200051.3-200072.6" + wire $1\data_r3__nia_ok$next[0:0]$14487 + attribute \src "libresoc.v:199419.7-199419.29" wire $1\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:200885.3-200906.6" - wire width 64 $1\data_r4__msr$next[63:0]$14546 - attribute \src "libresoc.v:200235.14-200235.49" + attribute \src "libresoc.v:200073.3-200094.6" + wire width 64 $1\data_r4__msr$next[63:0]$14494 + attribute \src "libresoc.v:199423.14-199423.49" wire width 64 $1\data_r4__msr[63:0] - attribute \src "libresoc.v:200885.3-200906.6" - wire $1\data_r4__msr_ok$next[0:0]$14547 - attribute \src "libresoc.v:200239.7-200239.29" + attribute \src "libresoc.v:200073.3-200094.6" + wire $1\data_r4__msr_ok$next[0:0]$14495 + attribute \src "libresoc.v:199427.7-199427.29" wire $1\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:200965.3-200974.6" + attribute \src "libresoc.v:200153.3-200162.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:200975.3-200984.6" + attribute \src "libresoc.v:200163.3-200172.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:200985.3-200994.6" + attribute \src "libresoc.v:200173.3-200182.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:200995.3-201004.6" + attribute \src "libresoc.v:200183.3-200192.6" wire width 64 $1\dest4_o[63:0] - attribute \src "libresoc.v:201005.3-201014.6" + attribute \src "libresoc.v:200193.3-200202.6" wire width 64 $1\dest5_o[63:0] - attribute \src "libresoc.v:200734.3-200742.6" - wire $1\opc_l_r_opc$next[0:0]$14479 - attribute \src "libresoc.v:200270.7-200270.25" + attribute \src "libresoc.v:199922.3-199930.6" + wire $1\opc_l_r_opc$next[0:0]$14427 + attribute \src "libresoc.v:199458.7-199458.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:200725.3-200733.6" - wire $1\opc_l_s_opc$next[0:0]$14476 - attribute \src "libresoc.v:200274.7-200274.25" + attribute \src "libresoc.v:199913.3-199921.6" + wire $1\opc_l_s_opc$next[0:0]$14424 + attribute \src "libresoc.v:199462.7-199462.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:201015.3-201023.6" - wire width 5 $1\prev_wr_go$next[4:0]$14576 - attribute \src "libresoc.v:200386.13-200386.31" + attribute \src "libresoc.v:200203.3-200211.6" + wire width 5 $1\prev_wr_go$next[4:0]$14524 + attribute \src "libresoc.v:199574.13-199574.31" wire width 5 $1\prev_wr_go[4:0] - attribute \src "libresoc.v:200679.3-200688.6" + attribute \src "libresoc.v:199867.3-199876.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:200770.3-200778.6" - wire width 5 $1\req_l_r_req$next[4:0]$14491 - attribute \src "libresoc.v:200394.13-200394.32" + attribute \src "libresoc.v:199958.3-199966.6" + wire width 5 $1\req_l_r_req$next[4:0]$14439 + attribute \src "libresoc.v:199582.13-199582.32" wire width 5 $1\req_l_r_req[4:0] - attribute \src "libresoc.v:200761.3-200769.6" - wire width 5 $1\req_l_s_req$next[4:0]$14488 - attribute \src "libresoc.v:200398.13-200398.32" + attribute \src "libresoc.v:199949.3-199957.6" + wire width 5 $1\req_l_s_req$next[4:0]$14436 + attribute \src "libresoc.v:199586.13-199586.32" wire width 5 $1\req_l_s_req[4:0] - attribute \src "libresoc.v:200698.3-200706.6" - wire $1\rok_l_r_rdok$next[0:0]$14467 - attribute \src "libresoc.v:200410.7-200410.26" + attribute \src "libresoc.v:199886.3-199894.6" + wire $1\rok_l_r_rdok$next[0:0]$14415 + attribute \src "libresoc.v:199598.7-199598.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:200689.3-200697.6" - wire $1\rok_l_s_rdok$next[0:0]$14464 - attribute \src "libresoc.v:200414.7-200414.26" + attribute \src "libresoc.v:199877.3-199885.6" + wire $1\rok_l_s_rdok$next[0:0]$14412 + attribute \src "libresoc.v:199602.7-199602.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:200716.3-200724.6" - wire $1\rst_l_r_rst$next[0:0]$14473 - attribute \src "libresoc.v:200418.7-200418.25" + attribute \src "libresoc.v:199904.3-199912.6" + wire $1\rst_l_r_rst$next[0:0]$14421 + attribute \src "libresoc.v:199606.7-199606.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:200707.3-200715.6" - wire $1\rst_l_s_rst$next[0:0]$14470 - attribute \src "libresoc.v:200422.7-200422.25" + attribute \src "libresoc.v:199895.3-199903.6" + wire $1\rst_l_s_rst$next[0:0]$14418 + attribute \src "libresoc.v:199610.7-199610.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:200752.3-200760.6" - wire width 4 $1\src_l_r_src$next[3:0]$14485 - attribute \src "libresoc.v:200438.13-200438.31" + attribute \src "libresoc.v:199940.3-199948.6" + wire width 4 $1\src_l_r_src$next[3:0]$14433 + attribute \src "libresoc.v:199626.13-199626.31" wire width 4 $1\src_l_r_src[3:0] - attribute \src "libresoc.v:200743.3-200751.6" - wire width 4 $1\src_l_s_src$next[3:0]$14482 - attribute \src "libresoc.v:200442.13-200442.31" + attribute \src "libresoc.v:199931.3-199939.6" + wire width 4 $1\src_l_s_src$next[3:0]$14430 + attribute \src "libresoc.v:199630.13-199630.31" wire width 4 $1\src_l_s_src[3:0] - attribute \src "libresoc.v:200907.3-200916.6" - wire width 64 $1\src_r0$next[63:0]$14553 - attribute \src "libresoc.v:200446.14-200446.43" + attribute \src "libresoc.v:200095.3-200104.6" + wire width 64 $1\src_r0$next[63:0]$14501 + attribute \src "libresoc.v:199634.14-199634.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:200917.3-200926.6" - wire width 64 $1\src_r1$next[63:0]$14556 - attribute \src "libresoc.v:200450.14-200450.43" + attribute \src "libresoc.v:200105.3-200114.6" + wire width 64 $1\src_r1$next[63:0]$14504 + attribute \src "libresoc.v:199638.14-199638.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:200927.3-200936.6" - wire width 64 $1\src_r2$next[63:0]$14559 - attribute \src "libresoc.v:200454.14-200454.43" + attribute \src "libresoc.v:200115.3-200124.6" + wire width 64 $1\src_r2$next[63:0]$14507 + attribute \src "libresoc.v:199642.14-199642.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:200937.3-200946.6" - wire width 64 $1\src_r3$next[63:0]$14562 - attribute \src "libresoc.v:200458.14-200458.43" + attribute \src "libresoc.v:200125.3-200134.6" + wire width 64 $1\src_r3$next[63:0]$14510 + attribute \src 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"libresoc.v:199704.18-199704.118" + wire width 64 $ternary$libresoc.v:199704$14363_Y + attribute \src "libresoc.v:199705.18-199705.118" + wire width 64 $ternary$libresoc.v:199705$14364_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -417601,7 +412868,7 @@ module \trap0 wire output 24 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 25 \fast2_ok - attribute \src "libresoc.v:199863.7-199863.15" + attribute \src "libresoc.v:199051.7-199051.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 30 \msr_ok @@ -417806,7 +413073,7 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:200464$14363 + cell $and $and$libresoc.v:199652$14311 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -417814,10 +413081,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:200464$14363_Y + connect \Y $and$libresoc.v:199652$14311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:200465$14364 + cell $and $and$libresoc.v:199653$14312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417825,10 +413092,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:200465$14364_Y + connect \Y $and$libresoc.v:199653$14312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:200466$14365 + cell $and $and$libresoc.v:199654$14313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417836,10 +413103,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:200466$14365_Y + connect \Y $and$libresoc.v:199654$14313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:200467$14366 + cell $and $and$libresoc.v:199655$14314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417847,10 +413114,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:200467$14366_Y + connect \Y $and$libresoc.v:199655$14314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:200468$14367 + cell $and $and$libresoc.v:199656$14315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417858,10 +413125,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:200468$14367_Y + connect \Y $and$libresoc.v:199656$14315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:200469$14368 + cell $and $and$libresoc.v:199657$14316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417869,10 +413136,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:200469$14368_Y + connect \Y $and$libresoc.v:199657$14316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:200470$14369 + cell $and $and$libresoc.v:199658$14317 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -417880,10 +413147,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 \$107 \$109 } - connect \Y $and$libresoc.v:200470$14369_Y + connect \Y $and$libresoc.v:199658$14317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:200471$14370 + cell $and $and$libresoc.v:199659$14318 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -417891,10 +413158,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \$111 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:200471$14370_Y + connect \Y $and$libresoc.v:199659$14318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:200472$14371 + cell $and $and$libresoc.v:199660$14319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417902,10 +413169,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:200472$14371_Y + connect \Y $and$libresoc.v:199660$14319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:200473$14372 + cell $and $and$libresoc.v:199661$14320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417913,10 +413180,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:200473$14372_Y + connect \Y $and$libresoc.v:199661$14320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:200474$14373 + cell $and $and$libresoc.v:199662$14321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417924,10 +413191,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:200474$14373_Y + connect \Y $and$libresoc.v:199662$14321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:200475$14374 + cell $and $and$libresoc.v:199663$14322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417935,10 +413202,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:200475$14374_Y + connect \Y $and$libresoc.v:199663$14322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:200476$14375 + cell $and $and$libresoc.v:199664$14323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417946,10 +413213,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:200476$14375_Y + connect \Y $and$libresoc.v:199664$14323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:200477$14376 + cell $and $and$libresoc.v:199665$14324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417957,10 +413224,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:200477$14376_Y + connect \Y $and$libresoc.v:199665$14324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:200479$14378 + cell $and $and$libresoc.v:199667$14326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417968,10 +413235,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:200479$14378_Y + connect \Y $and$libresoc.v:199667$14326_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:200481$14380 + cell $and $and$libresoc.v:199669$14328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -417979,10 +413246,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:200481$14380_Y + connect \Y $and$libresoc.v:199669$14328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:200482$14381 + cell $and $and$libresoc.v:199670$14329 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -417990,10 +413257,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:200482$14381_Y + connect \Y $and$libresoc.v:199670$14329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:200484$14383 + cell $and $and$libresoc.v:199672$14331 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -418001,10 +413268,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:200484$14383_Y + connect \Y $and$libresoc.v:199672$14331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:200487$14386 + cell $and $and$libresoc.v:199675$14334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418012,10 +413279,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:200487$14386_Y + connect \Y $and$libresoc.v:199675$14334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:200491$14390 + cell $and $and$libresoc.v:199679$14338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418023,10 +413290,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:200491$14390_Y + connect \Y $and$libresoc.v:199679$14338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:200493$14392 + cell $and $and$libresoc.v:199681$14340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418034,10 +413301,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:200493$14392_Y + connect \Y $and$libresoc.v:199681$14340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:200494$14393 + cell $and $and$libresoc.v:199682$14341 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -418045,10 +413312,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:200494$14393_Y + connect \Y $and$libresoc.v:199682$14341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:200496$14395 + cell $and $and$libresoc.v:199684$14343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418056,10 +413323,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:200496$14395_Y + connect \Y $and$libresoc.v:199684$14343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:200498$14397 + cell $and $and$libresoc.v:199686$14345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418067,10 +413334,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_trap0_n_ready_i - connect \Y $and$libresoc.v:200498$14397_Y + connect \Y $and$libresoc.v:199686$14345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:200499$14398 + cell $and $and$libresoc.v:199687$14346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418078,10 +413345,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_trap0_n_valid_o - connect \Y $and$libresoc.v:200499$14398_Y + connect \Y $and$libresoc.v:199687$14346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:200500$14399 + cell $and $and$libresoc.v:199688$14347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418089,10 +413356,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:200500$14399_Y + connect \Y $and$libresoc.v:199688$14347_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:200505$14404 + cell $and $and$libresoc.v:199693$14352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418100,10 +413367,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:200505$14404_Y + connect \Y $and$libresoc.v:199693$14352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:200506$14405 + cell $and $and$libresoc.v:199694$14353 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -418111,10 +413378,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:200506$14405_Y + connect \Y $and$libresoc.v:199694$14353_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:200509$14408 + cell $and $and$libresoc.v:199697$14356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418122,10 +413389,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:200509$14408_Y + connect \Y $and$libresoc.v:199697$14356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:200510$14409 + cell $and $and$libresoc.v:199698$14357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418133,10 +413400,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:200510$14409_Y + connect \Y $and$libresoc.v:199698$14357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:200511$14410 + cell $and $and$libresoc.v:199699$14358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418144,10 +413411,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast2_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:200511$14410_Y + connect \Y $and$libresoc.v:199699$14358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:200512$14411 + cell $and $and$libresoc.v:199700$14359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418155,10 +413422,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \nia_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:200512$14411_Y + connect \Y $and$libresoc.v:199700$14359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:200513$14412 + cell $and $and$libresoc.v:199701$14360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418166,10 +413433,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \msr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:200513$14412_Y + connect \Y $and$libresoc.v:199701$14360_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:200519$14418 + cell $and $and$libresoc.v:199707$14366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418177,10 +413444,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:200519$14418_Y + connect \Y $and$libresoc.v:199707$14366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:200520$14419 + cell $and $and$libresoc.v:199708$14367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418188,10 +413455,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:200520$14419_Y + connect \Y $and$libresoc.v:199708$14367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:200521$14420 + cell $and $and$libresoc.v:199709$14368 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -418199,10 +413466,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:200521$14420_Y + connect \Y $and$libresoc.v:199709$14368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:200522$14421 + cell $and $and$libresoc.v:199710$14369 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -418210,10 +413477,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$93 connect \B 4'1111 - connect \Y $and$libresoc.v:200522$14421_Y + connect \Y $and$libresoc.v:199710$14369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:200495$14394 + cell $eq $eq$libresoc.v:199683$14342 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -418221,10 +413488,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:200495$14394_Y + connect \Y $eq$libresoc.v:199683$14342_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:200497$14396 + cell $eq $eq$libresoc.v:199685$14344 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -418232,66 +413499,66 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:200497$14396_Y + connect \Y $eq$libresoc.v:199685$14344_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:200478$14377 + cell $not $not$libresoc.v:199666$14325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:200478$14377_Y + connect \Y $not$libresoc.v:199666$14325_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:200480$14379 + cell $not $not$libresoc.v:199668$14327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:200480$14379_Y + connect \Y $not$libresoc.v:199668$14327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:200483$14382 + cell $not $not$libresoc.v:199671$14330 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:200483$14382_Y + connect \Y $not$libresoc.v:199671$14330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:200486$14385 + cell $not $not$libresoc.v:199674$14333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:200486$14385_Y + connect \Y $not$libresoc.v:199674$14333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:200492$14391 + cell $not $not$libresoc.v:199680$14339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_ready_i - connect \Y $not$libresoc.v:200492$14391_Y + connect \Y $not$libresoc.v:199680$14339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:200507$14406 + cell $not $not$libresoc.v:199695$14354 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:200507$14406_Y + connect \Y $not$libresoc.v:199695$14354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:200523$14422 + cell $not $not$libresoc.v:199711$14370 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:200523$14422_Y + connect \Y $not$libresoc.v:199711$14370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:200490$14389 + cell $or $or$libresoc.v:199678$14337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418299,10 +413566,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:200490$14389_Y + connect \Y $or$libresoc.v:199678$14337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:200501$14400 + cell $or $or$libresoc.v:199689$14348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418310,10 +413577,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:200501$14400_Y + connect \Y $or$libresoc.v:199689$14348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:200502$14401 + cell $or $or$libresoc.v:199690$14349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418321,10 +413588,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:200502$14401_Y + connect \Y $or$libresoc.v:199690$14349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:200503$14402 + cell $or $or$libresoc.v:199691$14350 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -418332,10 +413599,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:200503$14402_Y + connect \Y $or$libresoc.v:199691$14350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:200504$14403 + cell $or $or$libresoc.v:199692$14351 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -418343,10 +413610,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:200504$14403_Y + connect \Y $or$libresoc.v:199692$14351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:200508$14407 + cell $or $or$libresoc.v:199696$14355 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -418354,10 +413621,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:200508$14407_Y + connect \Y $or$libresoc.v:199696$14355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:200518$14417 + cell $or $or$libresoc.v:199706$14365 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -418365,74 +413632,74 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:200518$14417_Y + connect \Y $or$libresoc.v:199706$14365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:200463$14362 + cell $reduce_and $reduce_and$libresoc.v:199651$14310 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:200463$14362_Y + connect \Y $reduce_and$libresoc.v:199651$14310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:200485$14384 + cell $reduce_or $reduce_or$libresoc.v:199673$14332 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:200485$14384_Y + connect \Y $reduce_or$libresoc.v:199673$14332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:200488$14387 + cell $reduce_or $reduce_or$libresoc.v:199676$14335 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:200488$14387_Y + connect \Y $reduce_or$libresoc.v:199676$14335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:200489$14388 + cell $reduce_or $reduce_or$libresoc.v:199677$14336 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:200489$14388_Y + connect \Y $reduce_or$libresoc.v:199677$14336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:200514$14413 + cell $mux $ternary$libresoc.v:199702$14361 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:200514$14413_Y + connect \Y $ternary$libresoc.v:199702$14361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:200515$14414 + cell $mux $ternary$libresoc.v:199703$14362 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:200515$14414_Y + connect \Y $ternary$libresoc.v:199703$14362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:200516$14415 + cell $mux $ternary$libresoc.v:199704$14363 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:200516$14415_Y + connect \Y $ternary$libresoc.v:199704$14363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:200517$14416 + cell $mux $ternary$libresoc.v:199705$14364 parameter \WIDTH 64 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:200517$14416_Y + connect \Y $ternary$libresoc.v:199705$14364_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:200600.14-200606.4" + attribute \src "libresoc.v:199788.14-199794.4" cell \alu_l$45 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418441,7 +413708,7 @@ module \trap0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:200607.13-200637.4" + attribute \src "libresoc.v:199795.13-199825.4" cell \alu_trap0 \alu_trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418474,7 +413741,7 @@ module \trap0 connect \trap_op__traptype \alu_trap0_trap_op__traptype end attribute \module_not_derived 1 - attribute \src "libresoc.v:200638.15-200644.4" + attribute \src "libresoc.v:199826.15-199832.4" cell \alui_l$44 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418483,7 +413750,7 @@ module \trap0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:200645.14-200651.4" + attribute \src "libresoc.v:199833.14-199839.4" cell \opc_l$40 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418492,7 +413759,7 @@ module \trap0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:200652.14-200658.4" + attribute \src "libresoc.v:199840.14-199846.4" cell \req_l$41 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418501,7 +413768,7 @@ module \trap0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:200659.14-200665.4" + attribute \src "libresoc.v:199847.14-199853.4" cell \rok_l$43 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418510,7 +413777,7 @@ module \trap0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:200666.14-200671.4" + attribute \src "libresoc.v:199854.14-199859.4" cell \rst_l$42 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418518,7 +413785,7 @@ module \trap0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:200672.14-200678.4" + attribute \src "libresoc.v:199860.14-199866.4" cell \src_l$39 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -418526,592 +413793,592 @@ module \trap0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:199863.7-199863.20" - process $proc$libresoc.v:199863$14577 + attribute \src "libresoc.v:199051.7-199051.20" + process $proc$libresoc.v:199051$14525 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:199989.7-199989.24" - process $proc$libresoc.v:199989$14578 + attribute \src "libresoc.v:199177.7-199177.24" + process $proc$libresoc.v:199177$14526 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:199999.7-199999.26" - process $proc$libresoc.v:199999$14579 + attribute \src "libresoc.v:199187.7-199187.26" + process $proc$libresoc.v:199187$14527 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:200007.7-200007.25" - process $proc$libresoc.v:200007$14580 + attribute \src "libresoc.v:199195.7-199195.25" + process $proc$libresoc.v:199195$14528 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:200043.14-200043.59" - process $proc$libresoc.v:200043$14581 + attribute \src "libresoc.v:199231.14-199231.59" + process $proc$libresoc.v:199231$14529 assign { } { } assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:200062.14-200062.51" - process $proc$libresoc.v:200062$14582 + attribute \src "libresoc.v:199250.14-199250.51" + process $proc$libresoc.v:199250$14530 assign { } { } assign $1\alu_trap0_trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:200066.14-200066.45" - process $proc$libresoc.v:200066$14583 + attribute \src "libresoc.v:199254.14-199254.45" + process $proc$libresoc.v:199254$14531 assign { } { } assign $1\alu_trap0_trap_op__insn[31:0] 0 sync always sync init update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:200145.13-200145.49" - process $proc$libresoc.v:200145$14584 + attribute \src "libresoc.v:199333.13-199333.49" + process $proc$libresoc.v:199333$14532 assign { } { } assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:200149.7-200149.41" - process $proc$libresoc.v:200149$14585 + attribute \src "libresoc.v:199337.7-199337.41" + process $proc$libresoc.v:199337$14533 assign { } { } assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 sync always sync init update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:200153.13-200153.48" - process $proc$libresoc.v:200153$14586 + attribute \src "libresoc.v:199341.13-199341.48" + process $proc$libresoc.v:199341$14534 assign { } { } assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:200157.14-200157.59" - process $proc$libresoc.v:200157$14587 + attribute \src "libresoc.v:199345.14-199345.59" + process $proc$libresoc.v:199345$14535 assign { } { } assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:200161.14-200161.52" - process $proc$libresoc.v:200161$14588 + attribute \src "libresoc.v:199349.14-199349.52" + process $proc$libresoc.v:199349$14536 assign { } { } assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:200165.13-200165.48" - process $proc$libresoc.v:200165$14589 + attribute \src "libresoc.v:199353.13-199353.48" + process $proc$libresoc.v:199353$14537 assign { } { } assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:200171.7-200171.27" - process $proc$libresoc.v:200171$14590 + attribute \src "libresoc.v:199359.7-199359.27" + process $proc$libresoc.v:199359$14538 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:200203.14-200203.47" - process $proc$libresoc.v:200203$14591 + attribute \src "libresoc.v:199391.14-199391.47" + process $proc$libresoc.v:199391$14539 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:200207.7-200207.27" - process $proc$libresoc.v:200207$14592 + attribute \src "libresoc.v:199395.7-199395.27" + process $proc$libresoc.v:199395$14540 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:200211.14-200211.51" - process $proc$libresoc.v:200211$14593 + attribute \src "libresoc.v:199399.14-199399.51" + process $proc$libresoc.v:199399$14541 assign { } { } assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__fast1 $1\data_r1__fast1[63:0] end - attribute \src "libresoc.v:200215.7-200215.31" - process $proc$libresoc.v:200215$14594 + attribute \src "libresoc.v:199403.7-199403.31" + process $proc$libresoc.v:199403$14542 assign { } { } assign $1\data_r1__fast1_ok[0:0] 1'0 sync always sync init update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:200219.14-200219.51" - process $proc$libresoc.v:200219$14595 + attribute \src "libresoc.v:199407.14-199407.51" + process $proc$libresoc.v:199407$14543 assign { } { } assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast2 $1\data_r2__fast2[63:0] end - attribute \src "libresoc.v:200223.7-200223.31" - process $proc$libresoc.v:200223$14596 + attribute \src "libresoc.v:199411.7-199411.31" + process $proc$libresoc.v:199411$14544 assign { } { } assign $1\data_r2__fast2_ok[0:0] 1'0 sync always sync init update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:200227.14-200227.49" - process $proc$libresoc.v:200227$14597 + attribute \src "libresoc.v:199415.14-199415.49" + process $proc$libresoc.v:199415$14545 assign { } { } assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r3__nia $1\data_r3__nia[63:0] end - attribute \src "libresoc.v:200231.7-200231.29" - process $proc$libresoc.v:200231$14598 + attribute \src "libresoc.v:199419.7-199419.29" + process $proc$libresoc.v:199419$14546 assign { } { } assign $1\data_r3__nia_ok[0:0] 1'0 sync always sync init update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:200235.14-200235.49" - process $proc$libresoc.v:200235$14599 + attribute \src "libresoc.v:199423.14-199423.49" + process $proc$libresoc.v:199423$14547 assign { } { } assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r4__msr $1\data_r4__msr[63:0] end - attribute \src "libresoc.v:200239.7-200239.29" - process $proc$libresoc.v:200239$14600 + attribute \src "libresoc.v:199427.7-199427.29" + process $proc$libresoc.v:199427$14548 assign { } { } assign $1\data_r4__msr_ok[0:0] 1'0 sync always sync init update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:200270.7-200270.25" - process $proc$libresoc.v:200270$14601 + attribute \src "libresoc.v:199458.7-199458.25" + process $proc$libresoc.v:199458$14549 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:200274.7-200274.25" - process $proc$libresoc.v:200274$14602 + attribute \src "libresoc.v:199462.7-199462.25" + process $proc$libresoc.v:199462$14550 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:200386.13-200386.31" - process $proc$libresoc.v:200386$14603 + attribute \src "libresoc.v:199574.13-199574.31" + process $proc$libresoc.v:199574$14551 assign { } { } assign $1\prev_wr_go[4:0] 5'00000 sync always sync init update \prev_wr_go $1\prev_wr_go[4:0] end - attribute \src "libresoc.v:200394.13-200394.32" - process $proc$libresoc.v:200394$14604 + attribute \src "libresoc.v:199582.13-199582.32" + process $proc$libresoc.v:199582$14552 assign { } { } assign $1\req_l_r_req[4:0] 5'11111 sync always sync init update \req_l_r_req $1\req_l_r_req[4:0] end - attribute \src "libresoc.v:200398.13-200398.32" - process $proc$libresoc.v:200398$14605 + attribute \src "libresoc.v:199586.13-199586.32" + process $proc$libresoc.v:199586$14553 assign { } { } assign $1\req_l_s_req[4:0] 5'00000 sync always sync init update \req_l_s_req $1\req_l_s_req[4:0] end - attribute \src "libresoc.v:200410.7-200410.26" - process $proc$libresoc.v:200410$14606 + attribute \src "libresoc.v:199598.7-199598.26" + process $proc$libresoc.v:199598$14554 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:200414.7-200414.26" - process $proc$libresoc.v:200414$14607 + attribute \src "libresoc.v:199602.7-199602.26" + process $proc$libresoc.v:199602$14555 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:200418.7-200418.25" - process $proc$libresoc.v:200418$14608 + attribute \src "libresoc.v:199606.7-199606.25" + process $proc$libresoc.v:199606$14556 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:200422.7-200422.25" - process $proc$libresoc.v:200422$14609 + attribute \src "libresoc.v:199610.7-199610.25" + process $proc$libresoc.v:199610$14557 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:200438.13-200438.31" - process $proc$libresoc.v:200438$14610 + attribute \src "libresoc.v:199626.13-199626.31" + process $proc$libresoc.v:199626$14558 assign { } { } assign $1\src_l_r_src[3:0] 4'1111 sync always sync init update \src_l_r_src $1\src_l_r_src[3:0] end - attribute \src "libresoc.v:200442.13-200442.31" - process $proc$libresoc.v:200442$14611 + attribute \src "libresoc.v:199630.13-199630.31" + process $proc$libresoc.v:199630$14559 assign { } { } assign $1\src_l_s_src[3:0] 4'0000 sync always sync init update \src_l_s_src $1\src_l_s_src[3:0] end - attribute \src "libresoc.v:200446.14-200446.43" - process $proc$libresoc.v:200446$14612 + attribute \src "libresoc.v:199634.14-199634.43" + process $proc$libresoc.v:199634$14560 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:200450.14-200450.43" - process $proc$libresoc.v:200450$14613 + attribute \src "libresoc.v:199638.14-199638.43" + process $proc$libresoc.v:199638$14561 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:200454.14-200454.43" - process $proc$libresoc.v:200454$14614 + attribute \src "libresoc.v:199642.14-199642.43" + process $proc$libresoc.v:199642$14562 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:200458.14-200458.43" - process $proc$libresoc.v:200458$14615 + attribute \src "libresoc.v:199646.14-199646.43" + process $proc$libresoc.v:199646$14563 assign { } { } assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r3 $1\src_r3[63:0] end - attribute \src "libresoc.v:200524.3-200525.39" - process $proc$libresoc.v:200524$14423 + attribute \src "libresoc.v:199712.3-199713.39" + process $proc$libresoc.v:199712$14371 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:200526.3-200527.43" - process $proc$libresoc.v:200526$14424 + attribute \src "libresoc.v:199714.3-199715.43" + process $proc$libresoc.v:199714$14372 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:200528.3-200529.29" - process $proc$libresoc.v:200528$14425 + attribute \src "libresoc.v:199716.3-199717.29" + process $proc$libresoc.v:199716$14373 assign { } { } assign $0\src_r3[63:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[63:0] end - attribute \src "libresoc.v:200530.3-200531.29" - process $proc$libresoc.v:200530$14426 + attribute \src "libresoc.v:199718.3-199719.29" + process $proc$libresoc.v:199718$14374 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:200532.3-200533.29" - process $proc$libresoc.v:200532$14427 + attribute \src "libresoc.v:199720.3-199721.29" + process $proc$libresoc.v:199720$14375 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:200534.3-200535.29" - process $proc$libresoc.v:200534$14428 + attribute \src "libresoc.v:199722.3-199723.29" + process $proc$libresoc.v:199722$14376 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:200536.3-200537.41" - process $proc$libresoc.v:200536$14429 + attribute \src "libresoc.v:199724.3-199725.41" + process $proc$libresoc.v:199724$14377 assign { } { } assign $0\data_r4__msr[63:0] \data_r4__msr$next sync posedge \coresync_clk update \data_r4__msr $0\data_r4__msr[63:0] end - attribute \src "libresoc.v:200538.3-200539.47" - process $proc$libresoc.v:200538$14430 + attribute \src "libresoc.v:199726.3-199727.47" + process $proc$libresoc.v:199726$14378 assign { } { } assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next sync posedge \coresync_clk update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:200540.3-200541.41" - process $proc$libresoc.v:200540$14431 + attribute \src "libresoc.v:199728.3-199729.41" + process $proc$libresoc.v:199728$14379 assign { } { } assign $0\data_r3__nia[63:0] \data_r3__nia$next sync posedge \coresync_clk update \data_r3__nia $0\data_r3__nia[63:0] end - attribute \src "libresoc.v:200542.3-200543.47" - process $proc$libresoc.v:200542$14432 + attribute \src "libresoc.v:199730.3-199731.47" + process $proc$libresoc.v:199730$14380 assign { } { } assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next sync posedge \coresync_clk update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:200544.3-200545.45" - process $proc$libresoc.v:200544$14433 + attribute \src "libresoc.v:199732.3-199733.45" + process $proc$libresoc.v:199732$14381 assign { } { } assign $0\data_r2__fast2[63:0] \data_r2__fast2$next sync posedge \coresync_clk update \data_r2__fast2 $0\data_r2__fast2[63:0] end - attribute \src "libresoc.v:200546.3-200547.51" - process $proc$libresoc.v:200546$14434 + attribute \src "libresoc.v:199734.3-199735.51" + process $proc$libresoc.v:199734$14382 assign { } { } assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next sync posedge \coresync_clk update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:200548.3-200549.45" - process $proc$libresoc.v:200548$14435 + attribute \src "libresoc.v:199736.3-199737.45" + process $proc$libresoc.v:199736$14383 assign { } { } assign $0\data_r1__fast1[63:0] \data_r1__fast1$next sync posedge \coresync_clk update \data_r1__fast1 $0\data_r1__fast1[63:0] end - attribute \src "libresoc.v:200550.3-200551.51" - process $proc$libresoc.v:200550$14436 + attribute \src "libresoc.v:199738.3-199739.51" + process $proc$libresoc.v:199738$14384 assign { } { } assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next sync posedge \coresync_clk update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:200552.3-200553.37" - process $proc$libresoc.v:200552$14437 + attribute \src "libresoc.v:199740.3-199741.37" + process $proc$libresoc.v:199740$14385 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:200554.3-200555.43" - process $proc$libresoc.v:200554$14438 + attribute \src "libresoc.v:199742.3-199743.43" + process $proc$libresoc.v:199742$14386 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:200556.3-200557.73" - process $proc$libresoc.v:200556$14439 + attribute \src "libresoc.v:199744.3-199745.73" + process $proc$libresoc.v:199744$14387 assign { } { } assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:200558.3-200559.69" - process $proc$libresoc.v:200558$14440 + attribute \src "libresoc.v:199746.3-199747.69" + process $proc$libresoc.v:199746$14388 assign { } { } assign $0\alu_trap0_trap_op__fn_unit[13:0] \alu_trap0_trap_op__fn_unit$next sync posedge \coresync_clk update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:200560.3-200561.63" - process $proc$libresoc.v:200560$14441 + attribute \src "libresoc.v:199748.3-199749.63" + process $proc$libresoc.v:199748$14389 assign { } { } assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:200562.3-200563.61" - process $proc$libresoc.v:200562$14442 + attribute \src "libresoc.v:199750.3-199751.61" + process $proc$libresoc.v:199750$14390 assign { } { } assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next sync posedge \coresync_clk update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:200564.3-200565.61" - process $proc$libresoc.v:200564$14443 + attribute \src "libresoc.v:199752.3-199753.61" + process $proc$libresoc.v:199752$14391 assign { } { } assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next sync posedge \coresync_clk update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:200566.3-200567.71" - process $proc$libresoc.v:200566$14444 + attribute \src "libresoc.v:199754.3-199755.71" + process $proc$libresoc.v:199754$14392 assign { } { } assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next sync posedge \coresync_clk update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:200568.3-200569.71" - process $proc$libresoc.v:200568$14445 + attribute \src "libresoc.v:199756.3-199757.71" + process $proc$libresoc.v:199756$14393 assign { } { } assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next sync posedge \coresync_clk update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:200570.3-200571.71" - process $proc$libresoc.v:200570$14446 + attribute \src "libresoc.v:199758.3-199759.71" + process $proc$libresoc.v:199758$14394 assign { } { } assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next sync posedge \coresync_clk update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:200572.3-200573.71" - process $proc$libresoc.v:200572$14447 + attribute \src "libresoc.v:199760.3-199761.71" + process $proc$libresoc.v:199760$14395 assign { } { } assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next sync posedge \coresync_clk update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:200574.3-200575.39" - process $proc$libresoc.v:200574$14448 + attribute \src "libresoc.v:199762.3-199763.39" + process $proc$libresoc.v:199762$14396 assign { } { } assign $0\req_l_r_req[4:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[4:0] end - attribute \src "libresoc.v:200576.3-200577.39" - process $proc$libresoc.v:200576$14449 + attribute \src "libresoc.v:199764.3-199765.39" + process $proc$libresoc.v:199764$14397 assign { } { } assign $0\req_l_s_req[4:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[4:0] end - attribute \src "libresoc.v:200578.3-200579.39" - process $proc$libresoc.v:200578$14450 + attribute \src "libresoc.v:199766.3-199767.39" + process $proc$libresoc.v:199766$14398 assign { } { } assign $0\src_l_r_src[3:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[3:0] end - attribute \src "libresoc.v:200580.3-200581.39" - process $proc$libresoc.v:200580$14451 + attribute \src "libresoc.v:199768.3-199769.39" + process $proc$libresoc.v:199768$14399 assign { } { } assign $0\src_l_s_src[3:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[3:0] end - attribute \src "libresoc.v:200582.3-200583.39" - process $proc$libresoc.v:200582$14452 + attribute \src "libresoc.v:199770.3-199771.39" + process $proc$libresoc.v:199770$14400 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:200584.3-200585.39" - process $proc$libresoc.v:200584$14453 + attribute \src "libresoc.v:199772.3-199773.39" + process $proc$libresoc.v:199772$14401 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:200586.3-200587.39" - process $proc$libresoc.v:200586$14454 + attribute \src "libresoc.v:199774.3-199775.39" + process $proc$libresoc.v:199774$14402 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:200588.3-200589.39" - process $proc$libresoc.v:200588$14455 + attribute \src "libresoc.v:199776.3-199777.39" + process $proc$libresoc.v:199776$14403 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:200590.3-200591.41" - process $proc$libresoc.v:200590$14456 + attribute \src "libresoc.v:199778.3-199779.41" + process $proc$libresoc.v:199778$14404 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:200592.3-200593.41" - process $proc$libresoc.v:200592$14457 + attribute \src "libresoc.v:199780.3-199781.41" + process $proc$libresoc.v:199780$14405 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:200594.3-200595.37" - process $proc$libresoc.v:200594$14458 + attribute \src "libresoc.v:199782.3-199783.37" + process $proc$libresoc.v:199782$14406 assign { } { } assign $0\prev_wr_go[4:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[4:0] end - attribute \src "libresoc.v:200596.3-200597.41" - process $proc$libresoc.v:200596$14459 + attribute \src "libresoc.v:199784.3-199785.41" + process $proc$libresoc.v:199784$14407 assign { } { } assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:200598.3-200599.25" - process $proc$libresoc.v:200598$14460 + attribute \src "libresoc.v:199786.3-199787.25" + process $proc$libresoc.v:199786$14408 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:200679.3-200688.6" - process $proc$libresoc.v:200679$14461 + attribute \src "libresoc.v:199867.3-199876.6" + process $proc$libresoc.v:199867$14409 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:200680.5-200680.29" + attribute \src "libresoc.v:199868.5-199868.29" switch \initial - attribute \src "libresoc.v:200680.9-200680.17" + attribute \src "libresoc.v:199868.9-199868.17" case 1'1 case end @@ -419127,14 +414394,14 @@ module \trap0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:200689.3-200697.6" - process $proc$libresoc.v:200689$14462 + attribute \src "libresoc.v:199877.3-199885.6" + process $proc$libresoc.v:199877$14410 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$14463 $1\rok_l_s_rdok$next[0:0]$14464 - attribute \src "libresoc.v:200690.5-200690.29" + assign $0\rok_l_s_rdok$next[0:0]$14411 $1\rok_l_s_rdok$next[0:0]$14412 + attribute \src "libresoc.v:199878.5-199878.29" switch \initial - attribute \src "libresoc.v:200690.9-200690.17" + attribute \src "libresoc.v:199878.9-199878.17" case 1'1 case end @@ -419143,21 +414410,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$14464 1'0 + assign $1\rok_l_s_rdok$next[0:0]$14412 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$14464 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$14412 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14463 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14411 end - attribute \src "libresoc.v:200698.3-200706.6" - process $proc$libresoc.v:200698$14465 + attribute \src "libresoc.v:199886.3-199894.6" + process $proc$libresoc.v:199886$14413 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$14466 $1\rok_l_r_rdok$next[0:0]$14467 - attribute \src "libresoc.v:200699.5-200699.29" + assign $0\rok_l_r_rdok$next[0:0]$14414 $1\rok_l_r_rdok$next[0:0]$14415 + attribute \src "libresoc.v:199887.5-199887.29" switch \initial - attribute \src "libresoc.v:200699.9-200699.17" + attribute \src "libresoc.v:199887.9-199887.17" case 1'1 case end @@ -419166,21 +414433,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$14467 1'1 + assign $1\rok_l_r_rdok$next[0:0]$14415 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$14467 \$65 + assign $1\rok_l_r_rdok$next[0:0]$14415 \$65 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14466 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14414 end - attribute \src "libresoc.v:200707.3-200715.6" - process $proc$libresoc.v:200707$14468 + attribute \src "libresoc.v:199895.3-199903.6" + process $proc$libresoc.v:199895$14416 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$14469 $1\rst_l_s_rst$next[0:0]$14470 - attribute \src "libresoc.v:200708.5-200708.29" + assign $0\rst_l_s_rst$next[0:0]$14417 $1\rst_l_s_rst$next[0:0]$14418 + attribute \src "libresoc.v:199896.5-199896.29" switch \initial - attribute \src "libresoc.v:200708.9-200708.17" + attribute \src "libresoc.v:199896.9-199896.17" case 1'1 case end @@ -419189,21 +414456,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$14470 1'0 + assign $1\rst_l_s_rst$next[0:0]$14418 1'0 case - assign $1\rst_l_s_rst$next[0:0]$14470 \all_rd + assign $1\rst_l_s_rst$next[0:0]$14418 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14469 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14417 end - attribute \src "libresoc.v:200716.3-200724.6" - process $proc$libresoc.v:200716$14471 + attribute \src "libresoc.v:199904.3-199912.6" + process $proc$libresoc.v:199904$14419 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$14472 $1\rst_l_r_rst$next[0:0]$14473 - attribute \src "libresoc.v:200717.5-200717.29" + assign $0\rst_l_r_rst$next[0:0]$14420 $1\rst_l_r_rst$next[0:0]$14421 + attribute \src "libresoc.v:199905.5-199905.29" switch \initial - attribute \src "libresoc.v:200717.9-200717.17" + attribute \src "libresoc.v:199905.9-199905.17" case 1'1 case end @@ -419212,21 +414479,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$14473 1'1 + assign $1\rst_l_r_rst$next[0:0]$14421 1'1 case - assign $1\rst_l_r_rst$next[0:0]$14473 \rst_r + assign $1\rst_l_r_rst$next[0:0]$14421 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14472 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14420 end - attribute \src "libresoc.v:200725.3-200733.6" - process $proc$libresoc.v:200725$14474 + attribute \src "libresoc.v:199913.3-199921.6" + process $proc$libresoc.v:199913$14422 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$14475 $1\opc_l_s_opc$next[0:0]$14476 - attribute \src "libresoc.v:200726.5-200726.29" + assign $0\opc_l_s_opc$next[0:0]$14423 $1\opc_l_s_opc$next[0:0]$14424 + attribute \src "libresoc.v:199914.5-199914.29" switch \initial - attribute \src "libresoc.v:200726.9-200726.17" + attribute \src "libresoc.v:199914.9-199914.17" case 1'1 case end @@ -419235,21 +414502,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$14476 1'0 + assign $1\opc_l_s_opc$next[0:0]$14424 1'0 case - assign $1\opc_l_s_opc$next[0:0]$14476 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$14424 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14475 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14423 end - attribute \src "libresoc.v:200734.3-200742.6" - process $proc$libresoc.v:200734$14477 + attribute \src "libresoc.v:199922.3-199930.6" + process $proc$libresoc.v:199922$14425 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$14478 $1\opc_l_r_opc$next[0:0]$14479 - attribute \src "libresoc.v:200735.5-200735.29" + assign $0\opc_l_r_opc$next[0:0]$14426 $1\opc_l_r_opc$next[0:0]$14427 + attribute \src "libresoc.v:199923.5-199923.29" switch \initial - attribute \src "libresoc.v:200735.9-200735.17" + attribute \src "libresoc.v:199923.9-199923.17" case 1'1 case end @@ -419258,21 +414525,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$14479 1'1 + assign $1\opc_l_r_opc$next[0:0]$14427 1'1 case - assign $1\opc_l_r_opc$next[0:0]$14479 \req_done + assign $1\opc_l_r_opc$next[0:0]$14427 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14478 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14426 end - attribute \src "libresoc.v:200743.3-200751.6" - process $proc$libresoc.v:200743$14480 + attribute \src "libresoc.v:199931.3-199939.6" + process $proc$libresoc.v:199931$14428 assign { } { } assign { } { } - assign $0\src_l_s_src$next[3:0]$14481 $1\src_l_s_src$next[3:0]$14482 - attribute \src "libresoc.v:200744.5-200744.29" + assign $0\src_l_s_src$next[3:0]$14429 $1\src_l_s_src$next[3:0]$14430 + attribute \src "libresoc.v:199932.5-199932.29" switch \initial - attribute \src "libresoc.v:200744.9-200744.17" + attribute \src "libresoc.v:199932.9-199932.17" case 1'1 case end @@ -419281,21 +414548,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[3:0]$14482 4'0000 + assign $1\src_l_s_src$next[3:0]$14430 4'0000 case - assign $1\src_l_s_src$next[3:0]$14482 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[3:0]$14430 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14481 + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14429 end - attribute \src "libresoc.v:200752.3-200760.6" - process $proc$libresoc.v:200752$14483 + attribute \src "libresoc.v:199940.3-199948.6" + process $proc$libresoc.v:199940$14431 assign { } { } assign { } { } - assign $0\src_l_r_src$next[3:0]$14484 $1\src_l_r_src$next[3:0]$14485 - attribute \src "libresoc.v:200753.5-200753.29" + assign $0\src_l_r_src$next[3:0]$14432 $1\src_l_r_src$next[3:0]$14433 + attribute \src "libresoc.v:199941.5-199941.29" switch \initial - attribute \src "libresoc.v:200753.9-200753.17" + attribute \src "libresoc.v:199941.9-199941.17" case 1'1 case end @@ -419304,21 +414571,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[3:0]$14485 4'1111 + assign $1\src_l_r_src$next[3:0]$14433 4'1111 case - assign $1\src_l_r_src$next[3:0]$14485 \reset_r + assign $1\src_l_r_src$next[3:0]$14433 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14484 + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14432 end - attribute \src "libresoc.v:200761.3-200769.6" - process $proc$libresoc.v:200761$14486 + attribute \src "libresoc.v:199949.3-199957.6" + process $proc$libresoc.v:199949$14434 assign { } { } assign { } { } - assign $0\req_l_s_req$next[4:0]$14487 $1\req_l_s_req$next[4:0]$14488 - attribute \src "libresoc.v:200762.5-200762.29" + assign $0\req_l_s_req$next[4:0]$14435 $1\req_l_s_req$next[4:0]$14436 + attribute \src "libresoc.v:199950.5-199950.29" switch \initial - attribute \src "libresoc.v:200762.9-200762.17" + attribute \src "libresoc.v:199950.9-199950.17" case 1'1 case end @@ -419327,21 +414594,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[4:0]$14488 5'00000 + assign $1\req_l_s_req$next[4:0]$14436 5'00000 case - assign $1\req_l_s_req$next[4:0]$14488 \$67 + assign $1\req_l_s_req$next[4:0]$14436 \$67 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14487 + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14435 end - attribute \src "libresoc.v:200770.3-200778.6" - process $proc$libresoc.v:200770$14489 + attribute \src "libresoc.v:199958.3-199966.6" + process $proc$libresoc.v:199958$14437 assign { } { } assign { } { } - assign $0\req_l_r_req$next[4:0]$14490 $1\req_l_r_req$next[4:0]$14491 - attribute \src "libresoc.v:200771.5-200771.29" + assign $0\req_l_r_req$next[4:0]$14438 $1\req_l_r_req$next[4:0]$14439 + attribute \src "libresoc.v:199959.5-199959.29" switch \initial - attribute \src "libresoc.v:200771.9-200771.17" + attribute \src "libresoc.v:199959.9-199959.17" case 1'1 case end @@ -419350,15 +414617,15 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[4:0]$14491 5'11111 + assign $1\req_l_r_req$next[4:0]$14439 5'11111 case - assign $1\req_l_r_req$next[4:0]$14491 \$69 + assign $1\req_l_r_req$next[4:0]$14439 \$69 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14490 + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14438 end - attribute \src "libresoc.v:200779.3-200796.6" - process $proc$libresoc.v:200779$14492 + attribute \src "libresoc.v:199967.3-199984.6" + process $proc$libresoc.v:199967$14440 assign { } { } assign { } { } assign { } { } @@ -419377,18 +414644,18 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign $0\alu_trap0_trap_op__cia$next[63:0]$14493 $1\alu_trap0_trap_op__cia$next[63:0]$14502 - assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14494 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 - assign $0\alu_trap0_trap_op__insn$next[31:0]$14495 $1\alu_trap0_trap_op__insn$next[31:0]$14504 - assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14496 $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 - assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14497 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 - assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14498 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 - assign $0\alu_trap0_trap_op__msr$next[63:0]$14499 $1\alu_trap0_trap_op__msr$next[63:0]$14508 - assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14500 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 - assign $0\alu_trap0_trap_op__traptype$next[7:0]$14501 $1\alu_trap0_trap_op__traptype$next[7:0]$14510 - attribute \src "libresoc.v:200780.5-200780.29" + assign $0\alu_trap0_trap_op__cia$next[63:0]$14441 $1\alu_trap0_trap_op__cia$next[63:0]$14450 + assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14442 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14451 + assign $0\alu_trap0_trap_op__insn$next[31:0]$14443 $1\alu_trap0_trap_op__insn$next[31:0]$14452 + assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14444 $1\alu_trap0_trap_op__insn_type$next[6:0]$14453 + assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14445 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14454 + assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14446 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14455 + assign $0\alu_trap0_trap_op__msr$next[63:0]$14447 $1\alu_trap0_trap_op__msr$next[63:0]$14456 + assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14448 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14457 + assign $0\alu_trap0_trap_op__traptype$next[7:0]$14449 $1\alu_trap0_trap_op__traptype$next[7:0]$14458 + attribute \src "libresoc.v:199968.5-199968.29" switch \initial - attribute \src "libresoc.v:200780.9-200780.17" + attribute \src "libresoc.v:199968.9-199968.17" case 1'1 case end @@ -419405,43 +414672,43 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 $1\alu_trap0_trap_op__traptype$next[7:0]$14510 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 $1\alu_trap0_trap_op__cia$next[63:0]$14502 $1\alu_trap0_trap_op__msr$next[63:0]$14508 $1\alu_trap0_trap_op__insn$next[31:0]$14504 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } + assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14455 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14457 $1\alu_trap0_trap_op__traptype$next[7:0]$14458 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14454 $1\alu_trap0_trap_op__cia$next[63:0]$14450 $1\alu_trap0_trap_op__msr$next[63:0]$14456 $1\alu_trap0_trap_op__insn$next[31:0]$14452 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14451 $1\alu_trap0_trap_op__insn_type$next[6:0]$14453 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } case - assign $1\alu_trap0_trap_op__cia$next[63:0]$14502 \alu_trap0_trap_op__cia - assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14503 \alu_trap0_trap_op__fn_unit - assign $1\alu_trap0_trap_op__insn$next[31:0]$14504 \alu_trap0_trap_op__insn - assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14505 \alu_trap0_trap_op__insn_type - assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14506 \alu_trap0_trap_op__is_32bit - assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14507 \alu_trap0_trap_op__ldst_exc - assign $1\alu_trap0_trap_op__msr$next[63:0]$14508 \alu_trap0_trap_op__msr - assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14509 \alu_trap0_trap_op__trapaddr - assign $1\alu_trap0_trap_op__traptype$next[7:0]$14510 \alu_trap0_trap_op__traptype + assign $1\alu_trap0_trap_op__cia$next[63:0]$14450 \alu_trap0_trap_op__cia + assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14451 \alu_trap0_trap_op__fn_unit + assign $1\alu_trap0_trap_op__insn$next[31:0]$14452 \alu_trap0_trap_op__insn + assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14453 \alu_trap0_trap_op__insn_type + assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14454 \alu_trap0_trap_op__is_32bit + assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14455 \alu_trap0_trap_op__ldst_exc + assign $1\alu_trap0_trap_op__msr$next[63:0]$14456 \alu_trap0_trap_op__msr + assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14457 \alu_trap0_trap_op__trapaddr + assign $1\alu_trap0_trap_op__traptype$next[7:0]$14458 \alu_trap0_trap_op__traptype end sync always - update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14493 - update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14494 - update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14495 - update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14496 - update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14497 - update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14498 - update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14499 - update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14500 - update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14501 + update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14441 + update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14442 + update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14443 + update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14444 + update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14445 + update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14446 + update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14447 + update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14448 + update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14449 end - attribute \src "libresoc.v:200797.3-200818.6" - process $proc$libresoc.v:200797$14511 + attribute \src "libresoc.v:199985.3-200006.6" + process $proc$libresoc.v:199985$14459 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$14512 $2\data_r0__o$next[63:0]$14516 + assign $0\data_r0__o$next[63:0]$14460 $2\data_r0__o$next[63:0]$14464 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$14513 $3\data_r0__o_ok$next[0:0]$14518 - attribute \src "libresoc.v:200798.5-200798.29" + assign $0\data_r0__o_ok$next[0:0]$14461 $3\data_r0__o_ok$next[0:0]$14466 + attribute \src "libresoc.v:199986.5-199986.29" switch \initial - attribute \src "libresoc.v:200798.9-200798.17" + attribute \src "libresoc.v:199986.9-199986.17" case 1'1 case end @@ -419451,10 +414718,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$14515 $1\data_r0__o$next[63:0]$14514 } { \o_ok \alu_trap0_o } + assign { $1\data_r0__o_ok$next[0:0]$14463 $1\data_r0__o$next[63:0]$14462 } { \o_ok \alu_trap0_o } case - assign $1\data_r0__o$next[63:0]$14514 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$14515 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$14462 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$14463 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -419462,38 +414729,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$14517 $2\data_r0__o$next[63:0]$14516 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$14465 $2\data_r0__o$next[63:0]$14464 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$14516 $1\data_r0__o$next[63:0]$14514 - assign $2\data_r0__o_ok$next[0:0]$14517 $1\data_r0__o_ok$next[0:0]$14515 + assign $2\data_r0__o$next[63:0]$14464 $1\data_r0__o$next[63:0]$14462 + assign $2\data_r0__o_ok$next[0:0]$14465 $1\data_r0__o_ok$next[0:0]$14463 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$14518 1'0 + assign $3\data_r0__o_ok$next[0:0]$14466 1'0 case - assign $3\data_r0__o_ok$next[0:0]$14518 $2\data_r0__o_ok$next[0:0]$14517 + assign $3\data_r0__o_ok$next[0:0]$14466 $2\data_r0__o_ok$next[0:0]$14465 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$14512 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14513 + update \data_r0__o$next $0\data_r0__o$next[63:0]$14460 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14461 end - attribute \src "libresoc.v:200819.3-200840.6" - process $proc$libresoc.v:200819$14519 + attribute \src "libresoc.v:200007.3-200028.6" + process $proc$libresoc.v:200007$14467 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__fast1$next[63:0]$14520 $2\data_r1__fast1$next[63:0]$14524 + assign $0\data_r1__fast1$next[63:0]$14468 $2\data_r1__fast1$next[63:0]$14472 assign { } { } - assign $0\data_r1__fast1_ok$next[0:0]$14521 $3\data_r1__fast1_ok$next[0:0]$14526 - attribute \src "libresoc.v:200820.5-200820.29" + assign $0\data_r1__fast1_ok$next[0:0]$14469 $3\data_r1__fast1_ok$next[0:0]$14474 + attribute \src "libresoc.v:200008.5-200008.29" switch \initial - attribute \src "libresoc.v:200820.9-200820.17" + attribute \src "libresoc.v:200008.9-200008.17" case 1'1 case end @@ -419503,10 +414770,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__fast1_ok$next[0:0]$14523 $1\data_r1__fast1$next[63:0]$14522 } { \fast1_ok \alu_trap0_fast1 } + assign { $1\data_r1__fast1_ok$next[0:0]$14471 $1\data_r1__fast1$next[63:0]$14470 } { \fast1_ok \alu_trap0_fast1 } case - assign $1\data_r1__fast1$next[63:0]$14522 \data_r1__fast1 - assign $1\data_r1__fast1_ok$next[0:0]$14523 \data_r1__fast1_ok + assign $1\data_r1__fast1$next[63:0]$14470 \data_r1__fast1 + assign $1\data_r1__fast1_ok$next[0:0]$14471 \data_r1__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -419514,38 +414781,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__fast1_ok$next[0:0]$14525 $2\data_r1__fast1$next[63:0]$14524 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__fast1_ok$next[0:0]$14473 $2\data_r1__fast1$next[63:0]$14472 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__fast1$next[63:0]$14524 $1\data_r1__fast1$next[63:0]$14522 - assign $2\data_r1__fast1_ok$next[0:0]$14525 $1\data_r1__fast1_ok$next[0:0]$14523 + assign $2\data_r1__fast1$next[63:0]$14472 $1\data_r1__fast1$next[63:0]$14470 + assign $2\data_r1__fast1_ok$next[0:0]$14473 $1\data_r1__fast1_ok$next[0:0]$14471 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__fast1_ok$next[0:0]$14526 1'0 + assign $3\data_r1__fast1_ok$next[0:0]$14474 1'0 case - assign $3\data_r1__fast1_ok$next[0:0]$14526 $2\data_r1__fast1_ok$next[0:0]$14525 + assign $3\data_r1__fast1_ok$next[0:0]$14474 $2\data_r1__fast1_ok$next[0:0]$14473 end sync always - update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14520 - update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14521 + update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14468 + update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14469 end - attribute \src "libresoc.v:200841.3-200862.6" - process $proc$libresoc.v:200841$14527 + attribute \src "libresoc.v:200029.3-200050.6" + process $proc$libresoc.v:200029$14475 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast2$next[63:0]$14528 $2\data_r2__fast2$next[63:0]$14532 + assign $0\data_r2__fast2$next[63:0]$14476 $2\data_r2__fast2$next[63:0]$14480 assign { } { } - assign $0\data_r2__fast2_ok$next[0:0]$14529 $3\data_r2__fast2_ok$next[0:0]$14534 - attribute \src "libresoc.v:200842.5-200842.29" + assign $0\data_r2__fast2_ok$next[0:0]$14477 $3\data_r2__fast2_ok$next[0:0]$14482 + attribute \src "libresoc.v:200030.5-200030.29" switch \initial - attribute \src "libresoc.v:200842.9-200842.17" + attribute \src "libresoc.v:200030.9-200030.17" case 1'1 case end @@ -419555,10 +414822,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast2_ok$next[0:0]$14531 $1\data_r2__fast2$next[63:0]$14530 } { \fast2_ok \alu_trap0_fast2 } + assign { $1\data_r2__fast2_ok$next[0:0]$14479 $1\data_r2__fast2$next[63:0]$14478 } { \fast2_ok \alu_trap0_fast2 } case - assign $1\data_r2__fast2$next[63:0]$14530 \data_r2__fast2 - assign $1\data_r2__fast2_ok$next[0:0]$14531 \data_r2__fast2_ok + assign $1\data_r2__fast2$next[63:0]$14478 \data_r2__fast2 + assign $1\data_r2__fast2_ok$next[0:0]$14479 \data_r2__fast2_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -419566,38 +414833,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast2_ok$next[0:0]$14533 $2\data_r2__fast2$next[63:0]$14532 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast2_ok$next[0:0]$14481 $2\data_r2__fast2$next[63:0]$14480 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast2$next[63:0]$14532 $1\data_r2__fast2$next[63:0]$14530 - assign $2\data_r2__fast2_ok$next[0:0]$14533 $1\data_r2__fast2_ok$next[0:0]$14531 + assign $2\data_r2__fast2$next[63:0]$14480 $1\data_r2__fast2$next[63:0]$14478 + assign $2\data_r2__fast2_ok$next[0:0]$14481 $1\data_r2__fast2_ok$next[0:0]$14479 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast2_ok$next[0:0]$14534 1'0 + assign $3\data_r2__fast2_ok$next[0:0]$14482 1'0 case - assign $3\data_r2__fast2_ok$next[0:0]$14534 $2\data_r2__fast2_ok$next[0:0]$14533 + assign $3\data_r2__fast2_ok$next[0:0]$14482 $2\data_r2__fast2_ok$next[0:0]$14481 end sync always - update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14528 - update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14529 + update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14476 + update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14477 end - attribute \src "libresoc.v:200863.3-200884.6" - process $proc$libresoc.v:200863$14535 + attribute \src "libresoc.v:200051.3-200072.6" + process $proc$libresoc.v:200051$14483 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__nia$next[63:0]$14536 $2\data_r3__nia$next[63:0]$14540 + assign $0\data_r3__nia$next[63:0]$14484 $2\data_r3__nia$next[63:0]$14488 assign { } { } - assign $0\data_r3__nia_ok$next[0:0]$14537 $3\data_r3__nia_ok$next[0:0]$14542 - attribute \src "libresoc.v:200864.5-200864.29" + assign $0\data_r3__nia_ok$next[0:0]$14485 $3\data_r3__nia_ok$next[0:0]$14490 + attribute \src "libresoc.v:200052.5-200052.29" switch \initial - attribute \src "libresoc.v:200864.9-200864.17" + attribute \src "libresoc.v:200052.9-200052.17" case 1'1 case end @@ -419607,10 +414874,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__nia_ok$next[0:0]$14539 $1\data_r3__nia$next[63:0]$14538 } { \nia_ok \alu_trap0_nia } + assign { $1\data_r3__nia_ok$next[0:0]$14487 $1\data_r3__nia$next[63:0]$14486 } { \nia_ok \alu_trap0_nia } case - assign $1\data_r3__nia$next[63:0]$14538 \data_r3__nia - assign $1\data_r3__nia_ok$next[0:0]$14539 \data_r3__nia_ok + assign $1\data_r3__nia$next[63:0]$14486 \data_r3__nia + assign $1\data_r3__nia_ok$next[0:0]$14487 \data_r3__nia_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -419618,38 +414885,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__nia_ok$next[0:0]$14541 $2\data_r3__nia$next[63:0]$14540 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r3__nia_ok$next[0:0]$14489 $2\data_r3__nia$next[63:0]$14488 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r3__nia$next[63:0]$14540 $1\data_r3__nia$next[63:0]$14538 - assign $2\data_r3__nia_ok$next[0:0]$14541 $1\data_r3__nia_ok$next[0:0]$14539 + assign $2\data_r3__nia$next[63:0]$14488 $1\data_r3__nia$next[63:0]$14486 + assign $2\data_r3__nia_ok$next[0:0]$14489 $1\data_r3__nia_ok$next[0:0]$14487 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__nia_ok$next[0:0]$14542 1'0 + assign $3\data_r3__nia_ok$next[0:0]$14490 1'0 case - assign $3\data_r3__nia_ok$next[0:0]$14542 $2\data_r3__nia_ok$next[0:0]$14541 + assign $3\data_r3__nia_ok$next[0:0]$14490 $2\data_r3__nia_ok$next[0:0]$14489 end sync always - update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14536 - update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14537 + update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14484 + update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14485 end - attribute \src "libresoc.v:200885.3-200906.6" - process $proc$libresoc.v:200885$14543 + attribute \src "libresoc.v:200073.3-200094.6" + process $proc$libresoc.v:200073$14491 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__msr$next[63:0]$14544 $2\data_r4__msr$next[63:0]$14548 + assign $0\data_r4__msr$next[63:0]$14492 $2\data_r4__msr$next[63:0]$14496 assign { } { } - assign $0\data_r4__msr_ok$next[0:0]$14545 $3\data_r4__msr_ok$next[0:0]$14550 - attribute \src "libresoc.v:200886.5-200886.29" + assign $0\data_r4__msr_ok$next[0:0]$14493 $3\data_r4__msr_ok$next[0:0]$14498 + attribute \src "libresoc.v:200074.5-200074.29" switch \initial - attribute \src "libresoc.v:200886.9-200886.17" + attribute \src "libresoc.v:200074.9-200074.17" case 1'1 case end @@ -419659,10 +414926,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__msr_ok$next[0:0]$14547 $1\data_r4__msr$next[63:0]$14546 } { \msr_ok \alu_trap0_msr } + assign { $1\data_r4__msr_ok$next[0:0]$14495 $1\data_r4__msr$next[63:0]$14494 } { \msr_ok \alu_trap0_msr } case - assign $1\data_r4__msr$next[63:0]$14546 \data_r4__msr - assign $1\data_r4__msr_ok$next[0:0]$14547 \data_r4__msr_ok + assign $1\data_r4__msr$next[63:0]$14494 \data_r4__msr + assign $1\data_r4__msr_ok$next[0:0]$14495 \data_r4__msr_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -419670,32 +414937,32 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__msr_ok$next[0:0]$14549 $2\data_r4__msr$next[63:0]$14548 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r4__msr_ok$next[0:0]$14497 $2\data_r4__msr$next[63:0]$14496 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r4__msr$next[63:0]$14548 $1\data_r4__msr$next[63:0]$14546 - assign $2\data_r4__msr_ok$next[0:0]$14549 $1\data_r4__msr_ok$next[0:0]$14547 + assign $2\data_r4__msr$next[63:0]$14496 $1\data_r4__msr$next[63:0]$14494 + assign $2\data_r4__msr_ok$next[0:0]$14497 $1\data_r4__msr_ok$next[0:0]$14495 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__msr_ok$next[0:0]$14550 1'0 + assign $3\data_r4__msr_ok$next[0:0]$14498 1'0 case - assign $3\data_r4__msr_ok$next[0:0]$14550 $2\data_r4__msr_ok$next[0:0]$14549 + assign $3\data_r4__msr_ok$next[0:0]$14498 $2\data_r4__msr_ok$next[0:0]$14497 end sync always - update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14544 - update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14545 + update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14492 + update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14493 end - attribute \src "libresoc.v:200907.3-200916.6" - process $proc$libresoc.v:200907$14551 + attribute \src "libresoc.v:200095.3-200104.6" + process $proc$libresoc.v:200095$14499 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$14552 $1\src_r0$next[63:0]$14553 - attribute \src "libresoc.v:200908.5-200908.29" + assign $0\src_r0$next[63:0]$14500 $1\src_r0$next[63:0]$14501 + attribute \src "libresoc.v:200096.5-200096.29" switch \initial - attribute \src "libresoc.v:200908.9-200908.17" + attribute \src "libresoc.v:200096.9-200096.17" case 1'1 case end @@ -419704,21 +414971,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$14553 \src1_i + assign $1\src_r0$next[63:0]$14501 \src1_i case - assign $1\src_r0$next[63:0]$14553 \src_r0 + assign $1\src_r0$next[63:0]$14501 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$14552 + update \src_r0$next $0\src_r0$next[63:0]$14500 end - attribute \src "libresoc.v:200917.3-200926.6" - process $proc$libresoc.v:200917$14554 + attribute \src "libresoc.v:200105.3-200114.6" + process $proc$libresoc.v:200105$14502 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$14555 $1\src_r1$next[63:0]$14556 - attribute \src "libresoc.v:200918.5-200918.29" + assign $0\src_r1$next[63:0]$14503 $1\src_r1$next[63:0]$14504 + attribute \src "libresoc.v:200106.5-200106.29" switch \initial - attribute \src "libresoc.v:200918.9-200918.17" + attribute \src "libresoc.v:200106.9-200106.17" case 1'1 case end @@ -419727,21 +414994,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$14556 \src2_i + assign $1\src_r1$next[63:0]$14504 \src2_i case - assign $1\src_r1$next[63:0]$14556 \src_r1 + assign $1\src_r1$next[63:0]$14504 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$14555 + update \src_r1$next $0\src_r1$next[63:0]$14503 end - attribute \src "libresoc.v:200927.3-200936.6" - process $proc$libresoc.v:200927$14557 + attribute \src "libresoc.v:200115.3-200124.6" + process $proc$libresoc.v:200115$14505 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$14558 $1\src_r2$next[63:0]$14559 - attribute \src "libresoc.v:200928.5-200928.29" + assign $0\src_r2$next[63:0]$14506 $1\src_r2$next[63:0]$14507 + attribute \src "libresoc.v:200116.5-200116.29" switch \initial - attribute \src "libresoc.v:200928.9-200928.17" + attribute \src "libresoc.v:200116.9-200116.17" case 1'1 case end @@ -419750,21 +415017,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$14559 \src3_i + assign $1\src_r2$next[63:0]$14507 \src3_i case - assign $1\src_r2$next[63:0]$14559 \src_r2 + assign $1\src_r2$next[63:0]$14507 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$14558 + update \src_r2$next $0\src_r2$next[63:0]$14506 end - attribute \src "libresoc.v:200937.3-200946.6" - process $proc$libresoc.v:200937$14560 + attribute \src "libresoc.v:200125.3-200134.6" + process $proc$libresoc.v:200125$14508 assign { } { } assign { } { } - assign $0\src_r3$next[63:0]$14561 $1\src_r3$next[63:0]$14562 - attribute \src "libresoc.v:200938.5-200938.29" + assign $0\src_r3$next[63:0]$14509 $1\src_r3$next[63:0]$14510 + attribute \src "libresoc.v:200126.5-200126.29" switch \initial - attribute \src "libresoc.v:200938.9-200938.17" + attribute \src "libresoc.v:200126.9-200126.17" case 1'1 case end @@ -419773,21 +415040,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[63:0]$14562 \src4_i + assign $1\src_r3$next[63:0]$14510 \src4_i case - assign $1\src_r3$next[63:0]$14562 \src_r3 + assign $1\src_r3$next[63:0]$14510 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[63:0]$14561 + update \src_r3$next $0\src_r3$next[63:0]$14509 end - attribute \src "libresoc.v:200947.3-200955.6" - process $proc$libresoc.v:200947$14563 + attribute \src "libresoc.v:200135.3-200143.6" + process $proc$libresoc.v:200135$14511 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$14564 $1\alui_l_r_alui$next[0:0]$14565 - attribute \src "libresoc.v:200948.5-200948.29" + assign $0\alui_l_r_alui$next[0:0]$14512 $1\alui_l_r_alui$next[0:0]$14513 + attribute \src "libresoc.v:200136.5-200136.29" switch \initial - attribute \src "libresoc.v:200948.9-200948.17" + attribute \src "libresoc.v:200136.9-200136.17" case 1'1 case end @@ -419796,21 +415063,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$14565 1'1 + assign $1\alui_l_r_alui$next[0:0]$14513 1'1 case - assign $1\alui_l_r_alui$next[0:0]$14565 \$89 + assign $1\alui_l_r_alui$next[0:0]$14513 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14564 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14512 end - attribute \src "libresoc.v:200956.3-200964.6" - process $proc$libresoc.v:200956$14566 + attribute \src "libresoc.v:200144.3-200152.6" + process $proc$libresoc.v:200144$14514 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$14567 $1\alu_l_r_alu$next[0:0]$14568 - attribute \src "libresoc.v:200957.5-200957.29" + assign $0\alu_l_r_alu$next[0:0]$14515 $1\alu_l_r_alu$next[0:0]$14516 + attribute \src "libresoc.v:200145.5-200145.29" switch \initial - attribute \src "libresoc.v:200957.9-200957.17" + attribute \src "libresoc.v:200145.9-200145.17" case 1'1 case end @@ -419819,21 +415086,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$14568 1'1 + assign $1\alu_l_r_alu$next[0:0]$14516 1'1 case - assign $1\alu_l_r_alu$next[0:0]$14568 \$91 + assign $1\alu_l_r_alu$next[0:0]$14516 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14567 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14515 end - attribute \src "libresoc.v:200965.3-200974.6" - process $proc$libresoc.v:200965$14569 + attribute \src "libresoc.v:200153.3-200162.6" + process $proc$libresoc.v:200153$14517 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:200966.5-200966.29" + attribute \src "libresoc.v:200154.5-200154.29" switch \initial - attribute \src "libresoc.v:200966.9-200966.17" + attribute \src "libresoc.v:200154.9-200154.17" case 1'1 case end @@ -419849,14 +415116,14 @@ module \trap0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:200975.3-200984.6" - process $proc$libresoc.v:200975$14570 + attribute \src "libresoc.v:200163.3-200172.6" + process $proc$libresoc.v:200163$14518 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:200976.5-200976.29" + attribute \src "libresoc.v:200164.5-200164.29" switch \initial - attribute \src "libresoc.v:200976.9-200976.17" + attribute \src "libresoc.v:200164.9-200164.17" case 1'1 case end @@ -419872,14 +415139,14 @@ module \trap0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:200985.3-200994.6" - process $proc$libresoc.v:200985$14571 + attribute \src "libresoc.v:200173.3-200182.6" + process $proc$libresoc.v:200173$14519 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:200986.5-200986.29" + attribute \src "libresoc.v:200174.5-200174.29" switch \initial - attribute \src "libresoc.v:200986.9-200986.17" + attribute \src "libresoc.v:200174.9-200174.17" case 1'1 case end @@ -419895,14 +415162,14 @@ module \trap0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:200995.3-201004.6" - process $proc$libresoc.v:200995$14572 + attribute \src "libresoc.v:200183.3-200192.6" + process $proc$libresoc.v:200183$14520 assign { } { } assign { } { } assign $0\dest4_o[63:0] $1\dest4_o[63:0] - attribute \src "libresoc.v:200996.5-200996.29" + attribute \src "libresoc.v:200184.5-200184.29" switch \initial - attribute \src "libresoc.v:200996.9-200996.17" + attribute \src "libresoc.v:200184.9-200184.17" case 1'1 case end @@ -419918,14 +415185,14 @@ module \trap0 sync always update \dest4_o $0\dest4_o[63:0] end - attribute \src "libresoc.v:201005.3-201014.6" - process $proc$libresoc.v:201005$14573 + attribute \src "libresoc.v:200193.3-200202.6" + process $proc$libresoc.v:200193$14521 assign { } { } assign { } { } assign $0\dest5_o[63:0] $1\dest5_o[63:0] - attribute \src "libresoc.v:201006.5-201006.29" + attribute \src "libresoc.v:200194.5-200194.29" switch \initial - attribute \src "libresoc.v:201006.9-201006.17" + attribute \src "libresoc.v:200194.9-200194.17" case 1'1 case end @@ -419941,14 +415208,14 @@ module \trap0 sync always update \dest5_o $0\dest5_o[63:0] end - attribute \src "libresoc.v:201015.3-201023.6" - process $proc$libresoc.v:201015$14574 + attribute \src "libresoc.v:200203.3-200211.6" + process $proc$libresoc.v:200203$14522 assign { } { } assign { } { } - assign $0\prev_wr_go$next[4:0]$14575 $1\prev_wr_go$next[4:0]$14576 - attribute \src "libresoc.v:201016.5-201016.29" + assign $0\prev_wr_go$next[4:0]$14523 $1\prev_wr_go$next[4:0]$14524 + attribute \src "libresoc.v:200204.5-200204.29" switch \initial - attribute \src "libresoc.v:201016.9-201016.17" + attribute \src "libresoc.v:200204.9-200204.17" case 1'1 case end @@ -419957,74 +415224,74 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[4:0]$14576 5'00000 - case - assign $1\prev_wr_go$next[4:0]$14576 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14575 - end - connect \$5 $reduce_and$libresoc.v:200463$14362_Y - connect \$99 $and$libresoc.v:200464$14363_Y - connect \$101 $and$libresoc.v:200465$14364_Y - connect \$103 $and$libresoc.v:200466$14365_Y - connect \$105 $and$libresoc.v:200467$14366_Y - connect \$107 $and$libresoc.v:200468$14367_Y - connect \$109 $and$libresoc.v:200469$14368_Y - connect \$111 $and$libresoc.v:200470$14369_Y - connect \$113 $and$libresoc.v:200471$14370_Y - connect \$115 $and$libresoc.v:200472$14371_Y - connect \$117 $and$libresoc.v:200473$14372_Y - connect \$11 $and$libresoc.v:200474$14373_Y - connect \$119 $and$libresoc.v:200475$14374_Y - connect \$121 $and$libresoc.v:200476$14375_Y - connect \$123 $and$libresoc.v:200477$14376_Y - connect \$13 $not$libresoc.v:200478$14377_Y - connect \$15 $and$libresoc.v:200479$14378_Y - connect \$17 $not$libresoc.v:200480$14379_Y - connect \$19 $and$libresoc.v:200481$14380_Y - connect \$21 $and$libresoc.v:200482$14381_Y - connect \$25 $not$libresoc.v:200483$14382_Y - connect \$27 $and$libresoc.v:200484$14383_Y - connect \$24 $reduce_or$libresoc.v:200485$14384_Y - connect \$23 $not$libresoc.v:200486$14385_Y - connect \$31 $and$libresoc.v:200487$14386_Y - connect \$33 $reduce_or$libresoc.v:200488$14387_Y - connect \$35 $reduce_or$libresoc.v:200489$14388_Y - connect \$37 $or$libresoc.v:200490$14389_Y - connect \$3 $and$libresoc.v:200491$14390_Y - connect \$39 $not$libresoc.v:200492$14391_Y - connect \$41 $and$libresoc.v:200493$14392_Y - connect \$43 $and$libresoc.v:200494$14393_Y - connect \$45 $eq$libresoc.v:200495$14394_Y - connect \$47 $and$libresoc.v:200496$14395_Y - connect \$49 $eq$libresoc.v:200497$14396_Y - connect \$51 $and$libresoc.v:200498$14397_Y - connect \$53 $and$libresoc.v:200499$14398_Y - connect \$55 $and$libresoc.v:200500$14399_Y - connect \$57 $or$libresoc.v:200501$14400_Y - connect \$59 $or$libresoc.v:200502$14401_Y - connect \$61 $or$libresoc.v:200503$14402_Y - connect \$63 $or$libresoc.v:200504$14403_Y - connect \$65 $and$libresoc.v:200505$14404_Y - connect \$67 $and$libresoc.v:200506$14405_Y - connect \$6 $not$libresoc.v:200507$14406_Y - connect \$69 $or$libresoc.v:200508$14407_Y - connect \$71 $and$libresoc.v:200509$14408_Y - connect \$73 $and$libresoc.v:200510$14409_Y - connect \$75 $and$libresoc.v:200511$14410_Y - connect \$77 $and$libresoc.v:200512$14411_Y - connect \$79 $and$libresoc.v:200513$14412_Y - connect \$81 $ternary$libresoc.v:200514$14413_Y - connect \$83 $ternary$libresoc.v:200515$14414_Y - connect \$85 $ternary$libresoc.v:200516$14415_Y - connect \$87 $ternary$libresoc.v:200517$14416_Y - connect \$8 $or$libresoc.v:200518$14417_Y - connect \$89 $and$libresoc.v:200519$14418_Y - connect \$91 $and$libresoc.v:200520$14419_Y - connect \$93 $and$libresoc.v:200521$14420_Y - connect \$95 $and$libresoc.v:200522$14421_Y - connect \$97 $not$libresoc.v:200523$14422_Y + assign $1\prev_wr_go$next[4:0]$14524 5'00000 + case + assign $1\prev_wr_go$next[4:0]$14524 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14523 + end + connect \$5 $reduce_and$libresoc.v:199651$14310_Y + connect \$99 $and$libresoc.v:199652$14311_Y + connect \$101 $and$libresoc.v:199653$14312_Y + connect \$103 $and$libresoc.v:199654$14313_Y + connect \$105 $and$libresoc.v:199655$14314_Y + connect \$107 $and$libresoc.v:199656$14315_Y + connect \$109 $and$libresoc.v:199657$14316_Y + connect \$111 $and$libresoc.v:199658$14317_Y + connect \$113 $and$libresoc.v:199659$14318_Y + connect \$115 $and$libresoc.v:199660$14319_Y + connect \$117 $and$libresoc.v:199661$14320_Y + connect \$11 $and$libresoc.v:199662$14321_Y + connect \$119 $and$libresoc.v:199663$14322_Y + connect \$121 $and$libresoc.v:199664$14323_Y + connect \$123 $and$libresoc.v:199665$14324_Y + connect \$13 $not$libresoc.v:199666$14325_Y + connect \$15 $and$libresoc.v:199667$14326_Y + connect \$17 $not$libresoc.v:199668$14327_Y + connect \$19 $and$libresoc.v:199669$14328_Y + connect \$21 $and$libresoc.v:199670$14329_Y + connect \$25 $not$libresoc.v:199671$14330_Y + connect \$27 $and$libresoc.v:199672$14331_Y + connect \$24 $reduce_or$libresoc.v:199673$14332_Y + connect \$23 $not$libresoc.v:199674$14333_Y + connect \$31 $and$libresoc.v:199675$14334_Y + connect \$33 $reduce_or$libresoc.v:199676$14335_Y + connect \$35 $reduce_or$libresoc.v:199677$14336_Y + connect \$37 $or$libresoc.v:199678$14337_Y + connect \$3 $and$libresoc.v:199679$14338_Y + connect \$39 $not$libresoc.v:199680$14339_Y + connect \$41 $and$libresoc.v:199681$14340_Y + connect \$43 $and$libresoc.v:199682$14341_Y + connect \$45 $eq$libresoc.v:199683$14342_Y + connect \$47 $and$libresoc.v:199684$14343_Y + connect \$49 $eq$libresoc.v:199685$14344_Y + connect \$51 $and$libresoc.v:199686$14345_Y + connect \$53 $and$libresoc.v:199687$14346_Y + connect \$55 $and$libresoc.v:199688$14347_Y + connect \$57 $or$libresoc.v:199689$14348_Y + connect \$59 $or$libresoc.v:199690$14349_Y + connect \$61 $or$libresoc.v:199691$14350_Y + connect \$63 $or$libresoc.v:199692$14351_Y + connect \$65 $and$libresoc.v:199693$14352_Y + connect \$67 $and$libresoc.v:199694$14353_Y + connect \$6 $not$libresoc.v:199695$14354_Y + connect \$69 $or$libresoc.v:199696$14355_Y + connect \$71 $and$libresoc.v:199697$14356_Y + connect \$73 $and$libresoc.v:199698$14357_Y + connect \$75 $and$libresoc.v:199699$14358_Y + connect \$77 $and$libresoc.v:199700$14359_Y + connect \$79 $and$libresoc.v:199701$14360_Y + connect \$81 $ternary$libresoc.v:199702$14361_Y + connect \$83 $ternary$libresoc.v:199703$14362_Y + connect \$85 $ternary$libresoc.v:199704$14363_Y + connect \$87 $ternary$libresoc.v:199705$14364_Y + connect \$8 $or$libresoc.v:199706$14365_Y + connect \$89 $and$libresoc.v:199707$14366_Y + connect \$91 $and$libresoc.v:199708$14367_Y + connect \$93 $and$libresoc.v:199709$14368_Y + connect \$95 $and$libresoc.v:199710$14369_Y + connect \$97 $not$libresoc.v:199711$14370_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$113 @@ -420055,37 +415322,37 @@ module \trap0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:201057.1-201115.10" +attribute \src "libresoc.v:200245.1-200303.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l" attribute \generator "nMigen" module \upd_l - attribute \src "libresoc.v:201058.7-201058.20" + attribute \src "libresoc.v:200246.7-200246.20" wire $0\initial[0:0] - attribute \src "libresoc.v:201103.3-201111.6" - wire $0\q_int$next[0:0]$14626 - attribute \src "libresoc.v:201101.3-201102.27" + attribute \src "libresoc.v:200291.3-200299.6" + wire $0\q_int$next[0:0]$14574 + attribute \src "libresoc.v:200289.3-200290.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:201103.3-201111.6" - wire $1\q_int$next[0:0]$14627 - attribute \src "libresoc.v:201080.7-201080.19" + attribute \src "libresoc.v:200291.3-200299.6" + wire $1\q_int$next[0:0]$14575 + attribute \src "libresoc.v:200268.7-200268.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:201093.17-201093.96" - wire $and$libresoc.v:201093$14616_Y - attribute \src "libresoc.v:201098.17-201098.96" - wire $and$libresoc.v:201098$14621_Y - attribute \src "libresoc.v:201095.18-201095.93" - wire $not$libresoc.v:201095$14618_Y - attribute \src "libresoc.v:201097.17-201097.92" - wire $not$libresoc.v:201097$14620_Y - attribute \src "libresoc.v:201100.17-201100.92" - wire $not$libresoc.v:201100$14623_Y - attribute \src "libresoc.v:201094.18-201094.98" - wire $or$libresoc.v:201094$14617_Y - attribute \src "libresoc.v:201096.18-201096.99" - wire $or$libresoc.v:201096$14619_Y - attribute \src "libresoc.v:201099.17-201099.97" - wire $or$libresoc.v:201099$14622_Y + attribute \src "libresoc.v:200281.17-200281.96" + wire $and$libresoc.v:200281$14564_Y + attribute \src "libresoc.v:200286.17-200286.96" + wire $and$libresoc.v:200286$14569_Y + attribute \src "libresoc.v:200283.18-200283.93" + wire $not$libresoc.v:200283$14566_Y + attribute \src "libresoc.v:200285.17-200285.92" + wire $not$libresoc.v:200285$14568_Y + attribute \src "libresoc.v:200288.17-200288.92" + wire $not$libresoc.v:200288$14571_Y + attribute \src "libresoc.v:200282.18-200282.98" + wire $or$libresoc.v:200282$14565_Y + attribute \src "libresoc.v:200284.18-200284.99" + wire $or$libresoc.v:200284$14567_Y + attribute \src "libresoc.v:200287.17-200287.97" + wire $or$libresoc.v:200287$14570_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -420106,7 +415373,7 @@ module \upd_l wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:201058.7-201058.15" + attribute \src "libresoc.v:200246.7-200246.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -420123,7 +415390,7 @@ module \upd_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:201093$14616 + cell $and $and$libresoc.v:200281$14564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420131,10 +415398,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:201093$14616_Y + connect \Y $and$libresoc.v:200281$14564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:201098$14621 + cell $and $and$libresoc.v:200286$14569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420142,34 +415409,34 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:201098$14621_Y + connect \Y $and$libresoc.v:200286$14569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:201095$14618 + cell $not $not$libresoc.v:200283$14566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_upd - connect \Y $not$libresoc.v:201095$14618_Y + connect \Y $not$libresoc.v:200283$14566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:201097$14620 + cell $not $not$libresoc.v:200285$14568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:201097$14620_Y + connect \Y $not$libresoc.v:200285$14568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:201100$14623 + cell $not $not$libresoc.v:200288$14571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:201100$14623_Y + connect \Y $not$libresoc.v:200288$14571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:201094$14617 + cell $or $or$libresoc.v:200282$14565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420177,10 +415444,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_upd - connect \Y $or$libresoc.v:201094$14617_Y + connect \Y $or$libresoc.v:200282$14565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:201096$14619 + cell $or $or$libresoc.v:200284$14567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420188,10 +415455,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_upd connect \B \q_int - connect \Y $or$libresoc.v:201096$14619_Y + connect \Y $or$libresoc.v:200284$14567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:201099$14622 + cell $or $or$libresoc.v:200287$14570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420199,39 +415466,39 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_upd - connect \Y $or$libresoc.v:201099$14622_Y + connect \Y $or$libresoc.v:200287$14570_Y end - attribute \src "libresoc.v:201058.7-201058.20" - process $proc$libresoc.v:201058$14628 + attribute \src "libresoc.v:200246.7-200246.20" + process $proc$libresoc.v:200246$14576 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:201080.7-201080.19" - process $proc$libresoc.v:201080$14629 + attribute \src "libresoc.v:200268.7-200268.19" + process $proc$libresoc.v:200268$14577 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:201101.3-201102.27" - process $proc$libresoc.v:201101$14624 + attribute \src "libresoc.v:200289.3-200290.27" + process $proc$libresoc.v:200289$14572 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:201103.3-201111.6" - process $proc$libresoc.v:201103$14625 + attribute \src "libresoc.v:200291.3-200299.6" + process $proc$libresoc.v:200291$14573 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14626 $1\q_int$next[0:0]$14627 - attribute \src "libresoc.v:201104.5-201104.29" + assign $0\q_int$next[0:0]$14574 $1\q_int$next[0:0]$14575 + attribute \src "libresoc.v:200292.5-200292.29" switch \initial - attribute \src "libresoc.v:201104.9-201104.17" + attribute \src "libresoc.v:200292.9-200292.17" case 1'1 case end @@ -420240,56 +415507,56 @@ module \upd_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14627 1'0 + assign $1\q_int$next[0:0]$14575 1'0 case - assign $1\q_int$next[0:0]$14627 \$5 + assign $1\q_int$next[0:0]$14575 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14626 + update \q_int$next $0\q_int$next[0:0]$14574 end - connect \$9 $and$libresoc.v:201093$14616_Y - connect \$11 $or$libresoc.v:201094$14617_Y - connect \$13 $not$libresoc.v:201095$14618_Y - connect \$15 $or$libresoc.v:201096$14619_Y - connect \$1 $not$libresoc.v:201097$14620_Y - connect \$3 $and$libresoc.v:201098$14621_Y - connect \$5 $or$libresoc.v:201099$14622_Y - connect \$7 $not$libresoc.v:201100$14623_Y + connect \$9 $and$libresoc.v:200281$14564_Y + connect \$11 $or$libresoc.v:200282$14565_Y + connect \$13 $not$libresoc.v:200283$14566_Y + connect \$15 $or$libresoc.v:200284$14567_Y + connect \$1 $not$libresoc.v:200285$14568_Y + connect \$3 $and$libresoc.v:200286$14569_Y + connect \$5 $or$libresoc.v:200287$14570_Y + connect \$7 $not$libresoc.v:200288$14571_Y connect \qlq_upd \$15 connect \qn_upd \$13 connect \q_upd \$11 end -attribute \src "libresoc.v:201119.1-201177.10" +attribute \src "libresoc.v:200307.1-200365.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l" attribute \generator "nMigen" module \valid_l - attribute \src "libresoc.v:201120.7-201120.20" + attribute \src "libresoc.v:200308.7-200308.20" wire $0\initial[0:0] - attribute \src "libresoc.v:201165.3-201173.6" - wire $0\q_int$next[0:0]$14640 - attribute \src "libresoc.v:201163.3-201164.27" + attribute \src "libresoc.v:200353.3-200361.6" + wire $0\q_int$next[0:0]$14588 + attribute \src "libresoc.v:200351.3-200352.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:201165.3-201173.6" - wire $1\q_int$next[0:0]$14641 - attribute \src "libresoc.v:201142.7-201142.19" + attribute \src "libresoc.v:200353.3-200361.6" + wire $1\q_int$next[0:0]$14589 + attribute \src "libresoc.v:200330.7-200330.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:201155.17-201155.96" - wire $and$libresoc.v:201155$14630_Y - attribute \src "libresoc.v:201160.17-201160.96" - wire $and$libresoc.v:201160$14635_Y - attribute \src "libresoc.v:201157.18-201157.95" - wire $not$libresoc.v:201157$14632_Y - attribute \src "libresoc.v:201159.17-201159.94" - wire $not$libresoc.v:201159$14634_Y - attribute \src "libresoc.v:201162.17-201162.94" - wire $not$libresoc.v:201162$14637_Y - attribute \src "libresoc.v:201156.18-201156.100" - wire $or$libresoc.v:201156$14631_Y - attribute \src "libresoc.v:201158.18-201158.101" - wire $or$libresoc.v:201158$14633_Y - attribute \src "libresoc.v:201161.17-201161.99" - wire $or$libresoc.v:201161$14636_Y + attribute \src "libresoc.v:200343.17-200343.96" + wire $and$libresoc.v:200343$14578_Y + attribute \src "libresoc.v:200348.17-200348.96" + wire $and$libresoc.v:200348$14583_Y + attribute \src "libresoc.v:200345.18-200345.95" + wire $not$libresoc.v:200345$14580_Y + attribute \src "libresoc.v:200347.17-200347.94" + wire $not$libresoc.v:200347$14582_Y + attribute \src "libresoc.v:200350.17-200350.94" + wire $not$libresoc.v:200350$14585_Y + attribute \src "libresoc.v:200344.18-200344.100" + wire $or$libresoc.v:200344$14579_Y + attribute \src "libresoc.v:200346.18-200346.101" + wire $or$libresoc.v:200346$14581_Y + attribute \src "libresoc.v:200349.17-200349.99" + wire $or$libresoc.v:200349$14584_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -420310,7 +415577,7 @@ module \valid_l wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:201120.7-201120.15" + attribute \src "libresoc.v:200308.7-200308.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -420327,7 +415594,7 @@ module \valid_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_valid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:201155$14630 + cell $and $and$libresoc.v:200343$14578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420335,10 +415602,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:201155$14630_Y + connect \Y $and$libresoc.v:200343$14578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:201160$14635 + cell $and $and$libresoc.v:200348$14583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420346,34 +415613,34 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:201160$14635_Y + connect \Y $and$libresoc.v:200348$14583_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:201157$14632 + cell $not $not$libresoc.v:200345$14580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_valid - connect \Y $not$libresoc.v:201157$14632_Y + connect \Y $not$libresoc.v:200345$14580_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:201159$14634 + cell $not $not$libresoc.v:200347$14582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:201159$14634_Y + connect \Y $not$libresoc.v:200347$14582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:201162$14637 + cell $not $not$libresoc.v:200350$14585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:201162$14637_Y + connect \Y $not$libresoc.v:200350$14585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:201156$14631 + cell $or $or$libresoc.v:200344$14579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420381,10 +415648,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_valid - connect \Y $or$libresoc.v:201156$14631_Y + connect \Y $or$libresoc.v:200344$14579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:201158$14633 + cell $or $or$libresoc.v:200346$14581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420392,10 +415659,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_valid connect \B \q_int - connect \Y $or$libresoc.v:201158$14633_Y + connect \Y $or$libresoc.v:200346$14581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:201161$14636 + cell $or $or$libresoc.v:200349$14584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420403,39 +415670,39 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_valid - connect \Y $or$libresoc.v:201161$14636_Y + connect \Y $or$libresoc.v:200349$14584_Y end - attribute \src "libresoc.v:201120.7-201120.20" - process $proc$libresoc.v:201120$14642 + attribute \src "libresoc.v:200308.7-200308.20" + process $proc$libresoc.v:200308$14590 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:201142.7-201142.19" - process $proc$libresoc.v:201142$14643 + attribute \src "libresoc.v:200330.7-200330.19" + process $proc$libresoc.v:200330$14591 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:201163.3-201164.27" - process $proc$libresoc.v:201163$14638 + attribute \src "libresoc.v:200351.3-200352.27" + process $proc$libresoc.v:200351$14586 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:201165.3-201173.6" - process $proc$libresoc.v:201165$14639 + attribute \src "libresoc.v:200353.3-200361.6" + process $proc$libresoc.v:200353$14587 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14640 $1\q_int$next[0:0]$14641 - attribute \src "libresoc.v:201166.5-201166.29" + assign $0\q_int$next[0:0]$14588 $1\q_int$next[0:0]$14589 + attribute \src "libresoc.v:200354.5-200354.29" switch \initial - attribute \src "libresoc.v:201166.9-201166.17" + attribute \src "libresoc.v:200354.9-200354.17" case 1'1 case end @@ -420444,56 +415711,56 @@ module \valid_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14641 1'0 + assign $1\q_int$next[0:0]$14589 1'0 case - assign $1\q_int$next[0:0]$14641 \$5 + assign $1\q_int$next[0:0]$14589 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14640 + update \q_int$next $0\q_int$next[0:0]$14588 end - connect \$9 $and$libresoc.v:201155$14630_Y - connect \$11 $or$libresoc.v:201156$14631_Y - connect \$13 $not$libresoc.v:201157$14632_Y - connect \$15 $or$libresoc.v:201158$14633_Y - connect \$1 $not$libresoc.v:201159$14634_Y - connect \$3 $and$libresoc.v:201160$14635_Y - connect \$5 $or$libresoc.v:201161$14636_Y - connect \$7 $not$libresoc.v:201162$14637_Y + connect \$9 $and$libresoc.v:200343$14578_Y + connect \$11 $or$libresoc.v:200344$14579_Y + connect \$13 $not$libresoc.v:200345$14580_Y + connect \$15 $or$libresoc.v:200346$14581_Y + connect \$1 $not$libresoc.v:200347$14582_Y + connect \$3 $and$libresoc.v:200348$14583_Y + connect \$5 $or$libresoc.v:200349$14584_Y + connect \$7 $not$libresoc.v:200350$14585_Y connect \qlq_valid \$15 connect \qn_valid \$13 connect \q_valid \$11 end -attribute \src "libresoc.v:201181.1-201239.10" +attribute \src "libresoc.v:200369.1-200427.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l" attribute \generator "nMigen" module \wri_l - attribute \src "libresoc.v:201182.7-201182.20" + attribute \src "libresoc.v:200370.7-200370.20" wire $0\initial[0:0] - attribute \src "libresoc.v:201227.3-201235.6" - wire $0\q_int$next[0:0]$14654 - attribute \src "libresoc.v:201225.3-201226.27" + attribute \src "libresoc.v:200415.3-200423.6" + wire $0\q_int$next[0:0]$14602 + attribute \src "libresoc.v:200413.3-200414.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:201227.3-201235.6" - wire $1\q_int$next[0:0]$14655 - attribute \src "libresoc.v:201204.7-201204.19" + attribute \src "libresoc.v:200415.3-200423.6" + wire $1\q_int$next[0:0]$14603 + attribute \src "libresoc.v:200392.7-200392.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:201217.17-201217.96" - wire $and$libresoc.v:201217$14644_Y - attribute \src "libresoc.v:201222.17-201222.96" - wire $and$libresoc.v:201222$14649_Y - attribute \src "libresoc.v:201219.18-201219.93" - wire $not$libresoc.v:201219$14646_Y - attribute \src "libresoc.v:201221.17-201221.92" - wire $not$libresoc.v:201221$14648_Y - attribute \src "libresoc.v:201224.17-201224.92" - wire $not$libresoc.v:201224$14651_Y - attribute \src "libresoc.v:201218.18-201218.98" - wire $or$libresoc.v:201218$14645_Y - attribute \src "libresoc.v:201220.18-201220.99" - wire $or$libresoc.v:201220$14647_Y - attribute \src "libresoc.v:201223.17-201223.97" - wire $or$libresoc.v:201223$14650_Y + attribute \src "libresoc.v:200405.17-200405.96" + wire $and$libresoc.v:200405$14592_Y + attribute \src "libresoc.v:200410.17-200410.96" + wire $and$libresoc.v:200410$14597_Y + attribute \src "libresoc.v:200407.18-200407.93" + wire $not$libresoc.v:200407$14594_Y + attribute \src "libresoc.v:200409.17-200409.92" + wire $not$libresoc.v:200409$14596_Y + attribute \src "libresoc.v:200412.17-200412.92" + wire $not$libresoc.v:200412$14599_Y + attribute \src "libresoc.v:200406.18-200406.98" + wire $or$libresoc.v:200406$14593_Y + attribute \src "libresoc.v:200408.18-200408.99" + wire $or$libresoc.v:200408$14595_Y + attribute \src "libresoc.v:200411.17-200411.97" + wire $or$libresoc.v:200411$14598_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -420514,7 +415781,7 @@ module \wri_l wire input 5 \coresync_clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \coresync_rst - attribute \src "libresoc.v:201182.7-201182.15" + attribute \src "libresoc.v:200370.7-200370.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -420531,7 +415798,7 @@ module \wri_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:201217$14644 + cell $and $and$libresoc.v:200405$14592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420539,10 +415806,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:201217$14644_Y + connect \Y $and$libresoc.v:200405$14592_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:201222$14649 + cell $and $and$libresoc.v:200410$14597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420550,34 +415817,34 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:201222$14649_Y + connect \Y $and$libresoc.v:200410$14597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:201219$14646 + cell $not $not$libresoc.v:200407$14594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_wri - connect \Y $not$libresoc.v:201219$14646_Y + connect \Y $not$libresoc.v:200407$14594_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:201221$14648 + cell $not $not$libresoc.v:200409$14596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:201221$14648_Y + connect \Y $not$libresoc.v:200409$14596_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:201224$14651 + cell $not $not$libresoc.v:200412$14599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:201224$14651_Y + connect \Y $not$libresoc.v:200412$14599_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:201218$14645 + cell $or $or$libresoc.v:200406$14593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420585,10 +415852,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_wri - connect \Y $or$libresoc.v:201218$14645_Y + connect \Y $or$libresoc.v:200406$14593_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:201220$14647 + cell $or $or$libresoc.v:200408$14595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420596,10 +415863,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_wri connect \B \q_int - connect \Y $or$libresoc.v:201220$14647_Y + connect \Y $or$libresoc.v:200408$14595_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:201223$14650 + cell $or $or$libresoc.v:200411$14598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420607,39 +415874,39 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_wri - connect \Y $or$libresoc.v:201223$14650_Y + connect \Y $or$libresoc.v:200411$14598_Y end - attribute \src "libresoc.v:201182.7-201182.20" - process $proc$libresoc.v:201182$14656 + attribute \src "libresoc.v:200370.7-200370.20" + process $proc$libresoc.v:200370$14604 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:201204.7-201204.19" - process $proc$libresoc.v:201204$14657 + attribute \src "libresoc.v:200392.7-200392.19" + process $proc$libresoc.v:200392$14605 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:201225.3-201226.27" - process $proc$libresoc.v:201225$14652 + attribute \src "libresoc.v:200413.3-200414.27" + process $proc$libresoc.v:200413$14600 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:201227.3-201235.6" - process $proc$libresoc.v:201227$14653 + attribute \src "libresoc.v:200415.3-200423.6" + process $proc$libresoc.v:200415$14601 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14654 $1\q_int$next[0:0]$14655 - attribute \src "libresoc.v:201228.5-201228.29" + assign $0\q_int$next[0:0]$14602 $1\q_int$next[0:0]$14603 + attribute \src "libresoc.v:200416.5-200416.29" switch \initial - attribute \src "libresoc.v:201228.9-201228.17" + attribute \src "libresoc.v:200416.9-200416.17" case 1'1 case end @@ -420648,54 +415915,54 @@ module \wri_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14655 1'0 + assign $1\q_int$next[0:0]$14603 1'0 case - assign $1\q_int$next[0:0]$14655 \$5 + assign $1\q_int$next[0:0]$14603 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14654 + update \q_int$next $0\q_int$next[0:0]$14602 end - connect \$9 $and$libresoc.v:201217$14644_Y - connect \$11 $or$libresoc.v:201218$14645_Y - connect \$13 $not$libresoc.v:201219$14646_Y - connect \$15 $or$libresoc.v:201220$14647_Y - connect \$1 $not$libresoc.v:201221$14648_Y - connect \$3 $and$libresoc.v:201222$14649_Y - connect \$5 $or$libresoc.v:201223$14650_Y - connect \$7 $not$libresoc.v:201224$14651_Y + connect \$9 $and$libresoc.v:200405$14592_Y + connect \$11 $or$libresoc.v:200406$14593_Y + connect \$13 $not$libresoc.v:200407$14594_Y + connect \$15 $or$libresoc.v:200408$14595_Y + connect \$1 $not$libresoc.v:200409$14596_Y + connect \$3 $and$libresoc.v:200410$14597_Y + connect \$5 $or$libresoc.v:200411$14598_Y + connect \$7 $not$libresoc.v:200412$14599_Y connect \qlq_wri \$15 connect \qn_wri \$13 connect \q_wri \$11 end -attribute \src "libresoc.v:201243.1-201309.10" +attribute \src "libresoc.v:200431.1-200497.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a" attribute \generator "nMigen" module \wrpick_CR_cr_a - attribute \src "libresoc.v:201288.17-201288.91" - wire $not$libresoc.v:201288$14658_Y - attribute \src "libresoc.v:201290.18-201290.93" - wire $not$libresoc.v:201290$14660_Y - attribute \src "libresoc.v:201292.18-201292.93" - wire $not$libresoc.v:201292$14662_Y - attribute \src "libresoc.v:201293.17-201293.89" - wire width 6 $not$libresoc.v:201293$14663_Y - attribute \src "libresoc.v:201295.18-201295.93" - wire $not$libresoc.v:201295$14665_Y - attribute \src "libresoc.v:201298.17-201298.91" - wire $not$libresoc.v:201298$14668_Y - attribute \src "libresoc.v:201289.18-201289.106" - wire $reduce_or$libresoc.v:201289$14659_Y - attribute \src "libresoc.v:201291.18-201291.106" - wire $reduce_or$libresoc.v:201291$14661_Y - attribute \src "libresoc.v:201294.18-201294.106" - wire $reduce_or$libresoc.v:201294$14664_Y - attribute \src "libresoc.v:201296.18-201296.90" - wire $reduce_or$libresoc.v:201296$14666_Y - attribute \src "libresoc.v:201297.17-201297.103" - wire $reduce_or$libresoc.v:201297$14667_Y - attribute \src "libresoc.v:201299.17-201299.105" - wire $reduce_or$libresoc.v:201299$14669_Y + attribute \src "libresoc.v:200476.17-200476.91" + wire $not$libresoc.v:200476$14606_Y + attribute \src "libresoc.v:200478.18-200478.93" + wire $not$libresoc.v:200478$14608_Y + attribute \src "libresoc.v:200480.18-200480.93" + wire $not$libresoc.v:200480$14610_Y + attribute \src "libresoc.v:200481.17-200481.89" + wire width 6 $not$libresoc.v:200481$14611_Y + attribute \src "libresoc.v:200483.18-200483.93" + wire $not$libresoc.v:200483$14613_Y + attribute \src "libresoc.v:200486.17-200486.91" + wire $not$libresoc.v:200486$14616_Y + attribute \src "libresoc.v:200477.18-200477.106" + wire $reduce_or$libresoc.v:200477$14607_Y + attribute \src "libresoc.v:200479.18-200479.106" + wire $reduce_or$libresoc.v:200479$14609_Y + attribute \src "libresoc.v:200482.18-200482.106" + wire $reduce_or$libresoc.v:200482$14612_Y + attribute \src "libresoc.v:200484.18-200484.90" + wire $reduce_or$libresoc.v:200484$14614_Y + attribute \src "libresoc.v:200485.17-200485.103" + wire $reduce_or$libresoc.v:200485$14615_Y + attribute \src "libresoc.v:200487.17-200487.105" + wire $reduce_or$libresoc.v:200487$14617_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -420741,113 +416008,113 @@ module \wrpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201288$14658 + cell $not $not$libresoc.v:200476$14606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:201288$14658_Y + connect \Y $not$libresoc.v:200476$14606_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201290$14660 + cell $not $not$libresoc.v:200478$14608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:201290$14660_Y + connect \Y $not$libresoc.v:200478$14608_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201292$14662 + cell $not $not$libresoc.v:200480$14610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:201292$14662_Y + connect \Y $not$libresoc.v:200480$14610_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201293$14663 + cell $not $not$libresoc.v:200481$14611 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:201293$14663_Y + connect \Y $not$libresoc.v:200481$14611_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201295$14665 + cell $not $not$libresoc.v:200483$14613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:201295$14665_Y + connect \Y $not$libresoc.v:200483$14613_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201298$14668 + cell $not $not$libresoc.v:200486$14616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:201298$14668_Y + connect \Y $not$libresoc.v:200486$14616_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201289$14659 + cell $reduce_or $reduce_or$libresoc.v:200477$14607 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:201289$14659_Y + connect \Y $reduce_or$libresoc.v:200477$14607_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201291$14661 + cell $reduce_or $reduce_or$libresoc.v:200479$14609 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:201291$14661_Y + connect \Y $reduce_or$libresoc.v:200479$14609_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201294$14664 + cell $reduce_or $reduce_or$libresoc.v:200482$14612 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:201294$14664_Y + connect \Y $reduce_or$libresoc.v:200482$14612_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201296$14666 + cell $reduce_or $reduce_or$libresoc.v:200484$14614 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201296$14666_Y + connect \Y $reduce_or$libresoc.v:200484$14614_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201297$14667 + cell $reduce_or $reduce_or$libresoc.v:200485$14615 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:201297$14667_Y + connect \Y $reduce_or$libresoc.v:200485$14615_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201299$14669 + cell $reduce_or $reduce_or$libresoc.v:200487$14617 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:201299$14669_Y - end - connect \$7 $not$libresoc.v:201288$14658_Y - connect \$12 $reduce_or$libresoc.v:201289$14659_Y - connect \$11 $not$libresoc.v:201290$14660_Y - connect \$16 $reduce_or$libresoc.v:201291$14661_Y - connect \$15 $not$libresoc.v:201292$14662_Y - connect \$1 $not$libresoc.v:201293$14663_Y - connect \$20 $reduce_or$libresoc.v:201294$14664_Y - connect \$19 $not$libresoc.v:201295$14665_Y - connect \$23 $reduce_or$libresoc.v:201296$14666_Y - connect \$4 $reduce_or$libresoc.v:201297$14667_Y - connect \$3 $not$libresoc.v:201298$14668_Y - connect \$8 $reduce_or$libresoc.v:201299$14669_Y + connect \Y $reduce_or$libresoc.v:200487$14617_Y + end + connect \$7 $not$libresoc.v:200476$14606_Y + connect \$12 $reduce_or$libresoc.v:200477$14607_Y + connect \$11 $not$libresoc.v:200478$14608_Y + connect \$16 $reduce_or$libresoc.v:200479$14609_Y + connect \$15 $not$libresoc.v:200480$14610_Y + connect \$1 $not$libresoc.v:200481$14611_Y + connect \$20 $reduce_or$libresoc.v:200482$14612_Y + connect \$19 $not$libresoc.v:200483$14613_Y + connect \$23 $reduce_or$libresoc.v:200484$14614_Y + connect \$4 $reduce_or$libresoc.v:200485$14615_Y + connect \$3 $not$libresoc.v:200486$14616_Y + connect \$8 $reduce_or$libresoc.v:200487$14617_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -420858,15 +416125,15 @@ module \wrpick_CR_cr_a connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:201313.1-201334.10" +attribute \src "libresoc.v:200501.1-200522.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr" attribute \generator "nMigen" module \wrpick_CR_full_cr - attribute \src "libresoc.v:201328.17-201328.89" - wire $not$libresoc.v:201328$14670_Y - attribute \src "libresoc.v:201329.17-201329.89" - wire $reduce_or$libresoc.v:201329$14671_Y + attribute \src "libresoc.v:200516.17-200516.89" + wire $not$libresoc.v:200516$14618_Y + attribute \src "libresoc.v:200517.17-200517.89" + wire $reduce_or$libresoc.v:200517$14619_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -420882,53 +416149,53 @@ module \wrpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201328$14670 + cell $not $not$libresoc.v:200516$14618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:201328$14670_Y + connect \Y $not$libresoc.v:200516$14618_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201329$14671 + cell $reduce_or $reduce_or$libresoc.v:200517$14619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201329$14671_Y + connect \Y $reduce_or$libresoc.v:200517$14619_Y end - connect \$1 $not$libresoc.v:201328$14670_Y - connect \$3 $reduce_or$libresoc.v:201329$14671_Y + connect \$1 $not$libresoc.v:200516$14618_Y + connect \$3 $reduce_or$libresoc.v:200517$14619_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:201338.1-201395.10" +attribute \src "libresoc.v:200526.1-200583.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1" attribute \generator "nMigen" module \wrpick_FAST_fast1 - attribute \src "libresoc.v:201377.17-201377.91" - wire $not$libresoc.v:201377$14672_Y - attribute \src "libresoc.v:201379.18-201379.93" - wire $not$libresoc.v:201379$14674_Y - attribute \src "libresoc.v:201381.18-201381.93" - wire $not$libresoc.v:201381$14676_Y - attribute \src "libresoc.v:201382.17-201382.89" - wire width 5 $not$libresoc.v:201382$14677_Y - attribute \src "libresoc.v:201385.17-201385.91" - wire $not$libresoc.v:201385$14680_Y - attribute \src "libresoc.v:201378.18-201378.106" - wire $reduce_or$libresoc.v:201378$14673_Y - attribute \src "libresoc.v:201380.18-201380.106" - wire $reduce_or$libresoc.v:201380$14675_Y - attribute \src "libresoc.v:201383.18-201383.90" - wire $reduce_or$libresoc.v:201383$14678_Y - attribute \src "libresoc.v:201384.17-201384.103" - wire $reduce_or$libresoc.v:201384$14679_Y - attribute \src "libresoc.v:201386.17-201386.105" - wire $reduce_or$libresoc.v:201386$14681_Y + attribute \src "libresoc.v:200565.17-200565.91" + wire $not$libresoc.v:200565$14620_Y + attribute \src "libresoc.v:200567.18-200567.93" + wire $not$libresoc.v:200567$14622_Y + attribute \src "libresoc.v:200569.18-200569.93" + wire $not$libresoc.v:200569$14624_Y + attribute \src "libresoc.v:200570.17-200570.89" + wire width 5 $not$libresoc.v:200570$14625_Y + attribute \src "libresoc.v:200573.17-200573.91" + wire $not$libresoc.v:200573$14628_Y + attribute \src "libresoc.v:200566.18-200566.106" + wire $reduce_or$libresoc.v:200566$14621_Y + attribute \src "libresoc.v:200568.18-200568.106" + wire $reduce_or$libresoc.v:200568$14623_Y + attribute \src "libresoc.v:200571.18-200571.90" + wire $reduce_or$libresoc.v:200571$14626_Y + attribute \src "libresoc.v:200572.17-200572.103" + wire $reduce_or$libresoc.v:200572$14627_Y + attribute \src "libresoc.v:200574.17-200574.105" + wire $reduce_or$libresoc.v:200574$14629_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -420968,95 +416235,95 @@ module \wrpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201377$14672 + cell $not $not$libresoc.v:200565$14620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:201377$14672_Y + connect \Y $not$libresoc.v:200565$14620_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201379$14674 + cell $not $not$libresoc.v:200567$14622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:201379$14674_Y + connect \Y $not$libresoc.v:200567$14622_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201381$14676 + cell $not $not$libresoc.v:200569$14624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:201381$14676_Y + connect \Y $not$libresoc.v:200569$14624_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201382$14677 + cell $not $not$libresoc.v:200570$14625 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \i - connect \Y $not$libresoc.v:201382$14677_Y + connect \Y $not$libresoc.v:200570$14625_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201385$14680 + cell $not $not$libresoc.v:200573$14628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:201385$14680_Y + connect \Y $not$libresoc.v:200573$14628_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201378$14673 + cell $reduce_or $reduce_or$libresoc.v:200566$14621 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:201378$14673_Y + connect \Y $reduce_or$libresoc.v:200566$14621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201380$14675 + cell $reduce_or $reduce_or$libresoc.v:200568$14623 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:201380$14675_Y + connect \Y $reduce_or$libresoc.v:200568$14623_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201383$14678 + cell $reduce_or $reduce_or$libresoc.v:200571$14626 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201383$14678_Y + connect \Y $reduce_or$libresoc.v:200571$14626_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201384$14679 + cell $reduce_or $reduce_or$libresoc.v:200572$14627 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:201384$14679_Y + connect \Y $reduce_or$libresoc.v:200572$14627_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201386$14681 + cell $reduce_or $reduce_or$libresoc.v:200574$14629 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:201386$14681_Y - end - connect \$7 $not$libresoc.v:201377$14672_Y - connect \$12 $reduce_or$libresoc.v:201378$14673_Y - connect \$11 $not$libresoc.v:201379$14674_Y - connect \$16 $reduce_or$libresoc.v:201380$14675_Y - connect \$15 $not$libresoc.v:201381$14676_Y - connect \$1 $not$libresoc.v:201382$14677_Y - connect \$19 $reduce_or$libresoc.v:201383$14678_Y - connect \$4 $reduce_or$libresoc.v:201384$14679_Y - connect \$3 $not$libresoc.v:201385$14680_Y - connect \$8 $reduce_or$libresoc.v:201386$14681_Y + connect \Y $reduce_or$libresoc.v:200574$14629_Y + end + connect \$7 $not$libresoc.v:200565$14620_Y + connect \$12 $reduce_or$libresoc.v:200566$14621_Y + connect \$11 $not$libresoc.v:200567$14622_Y + connect \$16 $reduce_or$libresoc.v:200568$14623_Y + connect \$15 $not$libresoc.v:200569$14624_Y + connect \$1 $not$libresoc.v:200570$14625_Y + connect \$19 $reduce_or$libresoc.v:200571$14626_Y + connect \$4 $reduce_or$libresoc.v:200572$14627_Y + connect \$3 $not$libresoc.v:200573$14628_Y + connect \$8 $reduce_or$libresoc.v:200574$14629_Y connect \en_o \$19 connect \o { \t4 \t3 \t2 \t1 \t0 } connect \t4 \$15 @@ -421066,51 +416333,51 @@ module \wrpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:201399.1-201501.10" +attribute \src "libresoc.v:200587.1-200689.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o" attribute \generator "nMigen" module \wrpick_INT_o - attribute \src "libresoc.v:201468.17-201468.91" - wire $not$libresoc.v:201468$14682_Y - attribute \src "libresoc.v:201470.18-201470.93" - wire $not$libresoc.v:201470$14684_Y - attribute \src "libresoc.v:201472.18-201472.93" - wire $not$libresoc.v:201472$14686_Y - attribute \src "libresoc.v:201473.17-201473.89" - wire width 10 $not$libresoc.v:201473$14687_Y - attribute \src "libresoc.v:201475.18-201475.93" - wire $not$libresoc.v:201475$14689_Y - attribute \src "libresoc.v:201477.18-201477.93" - wire $not$libresoc.v:201477$14691_Y - attribute \src "libresoc.v:201479.18-201479.93" - wire $not$libresoc.v:201479$14693_Y - attribute \src "libresoc.v:201481.18-201481.93" - wire $not$libresoc.v:201481$14695_Y - attribute \src "libresoc.v:201483.18-201483.93" - wire $not$libresoc.v:201483$14697_Y - attribute \src "libresoc.v:201486.17-201486.91" - wire $not$libresoc.v:201486$14700_Y - attribute \src "libresoc.v:201469.18-201469.106" - wire $reduce_or$libresoc.v:201469$14683_Y - attribute \src "libresoc.v:201471.18-201471.106" - wire $reduce_or$libresoc.v:201471$14685_Y - attribute \src "libresoc.v:201474.18-201474.106" - wire $reduce_or$libresoc.v:201474$14688_Y - attribute \src "libresoc.v:201476.18-201476.106" - wire $reduce_or$libresoc.v:201476$14690_Y - attribute \src "libresoc.v:201478.18-201478.106" - wire $reduce_or$libresoc.v:201478$14692_Y - attribute \src "libresoc.v:201480.18-201480.106" - wire $reduce_or$libresoc.v:201480$14694_Y - attribute \src "libresoc.v:201482.18-201482.106" - wire $reduce_or$libresoc.v:201482$14696_Y - attribute \src "libresoc.v:201484.18-201484.90" - wire $reduce_or$libresoc.v:201484$14698_Y - attribute \src "libresoc.v:201485.17-201485.103" - wire $reduce_or$libresoc.v:201485$14699_Y - attribute \src "libresoc.v:201487.17-201487.105" - wire $reduce_or$libresoc.v:201487$14701_Y + attribute \src "libresoc.v:200656.17-200656.91" + wire $not$libresoc.v:200656$14630_Y + attribute \src "libresoc.v:200658.18-200658.93" + wire $not$libresoc.v:200658$14632_Y + attribute \src "libresoc.v:200660.18-200660.93" + wire $not$libresoc.v:200660$14634_Y + attribute \src "libresoc.v:200661.17-200661.89" + wire width 10 $not$libresoc.v:200661$14635_Y + attribute \src "libresoc.v:200663.18-200663.93" + wire $not$libresoc.v:200663$14637_Y + attribute \src "libresoc.v:200665.18-200665.93" + wire $not$libresoc.v:200665$14639_Y + attribute \src "libresoc.v:200667.18-200667.93" + wire $not$libresoc.v:200667$14641_Y + attribute \src "libresoc.v:200669.18-200669.93" + wire $not$libresoc.v:200669$14643_Y + attribute \src "libresoc.v:200671.18-200671.93" + wire $not$libresoc.v:200671$14645_Y + attribute \src "libresoc.v:200674.17-200674.91" + wire $not$libresoc.v:200674$14648_Y + attribute \src "libresoc.v:200657.18-200657.106" + wire $reduce_or$libresoc.v:200657$14631_Y + attribute \src "libresoc.v:200659.18-200659.106" + wire $reduce_or$libresoc.v:200659$14633_Y + attribute \src "libresoc.v:200662.18-200662.106" + wire $reduce_or$libresoc.v:200662$14636_Y + attribute \src "libresoc.v:200664.18-200664.106" + wire $reduce_or$libresoc.v:200664$14638_Y + attribute \src "libresoc.v:200666.18-200666.106" + wire $reduce_or$libresoc.v:200666$14640_Y + attribute \src "libresoc.v:200668.18-200668.106" + wire $reduce_or$libresoc.v:200668$14642_Y + attribute \src "libresoc.v:200670.18-200670.106" + wire $reduce_or$libresoc.v:200670$14644_Y + attribute \src "libresoc.v:200672.18-200672.90" + wire $reduce_or$libresoc.v:200672$14646_Y + attribute \src "libresoc.v:200673.17-200673.103" + wire $reduce_or$libresoc.v:200673$14647_Y + attribute \src "libresoc.v:200675.17-200675.105" + wire $reduce_or$libresoc.v:200675$14649_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 10 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -421180,185 +416447,185 @@ module \wrpick_INT_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201468$14682 + cell $not $not$libresoc.v:200656$14630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:201468$14682_Y + connect \Y $not$libresoc.v:200656$14630_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201470$14684 + cell $not $not$libresoc.v:200658$14632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:201470$14684_Y + connect \Y $not$libresoc.v:200658$14632_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201472$14686 + cell $not $not$libresoc.v:200660$14634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:201472$14686_Y + connect \Y $not$libresoc.v:200660$14634_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201473$14687 + cell $not $not$libresoc.v:200661$14635 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 10 connect \A \i - connect \Y $not$libresoc.v:201473$14687_Y + connect \Y $not$libresoc.v:200661$14635_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201475$14689 + cell $not $not$libresoc.v:200663$14637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:201475$14689_Y + connect \Y $not$libresoc.v:200663$14637_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201477$14691 + cell $not $not$libresoc.v:200665$14639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:201477$14691_Y + connect \Y $not$libresoc.v:200665$14639_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201479$14693 + cell $not $not$libresoc.v:200667$14641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:201479$14693_Y + connect \Y $not$libresoc.v:200667$14641_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201481$14695 + cell $not $not$libresoc.v:200669$14643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:201481$14695_Y + connect \Y $not$libresoc.v:200669$14643_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201483$14697 + cell $not $not$libresoc.v:200671$14645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$36 - connect \Y $not$libresoc.v:201483$14697_Y + connect \Y $not$libresoc.v:200671$14645_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201486$14700 + cell $not $not$libresoc.v:200674$14648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:201486$14700_Y + connect \Y $not$libresoc.v:200674$14648_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201469$14683 + cell $reduce_or $reduce_or$libresoc.v:200657$14631 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:201469$14683_Y + connect \Y $reduce_or$libresoc.v:200657$14631_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201471$14685 + cell $reduce_or $reduce_or$libresoc.v:200659$14633 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:201471$14685_Y + connect \Y $reduce_or$libresoc.v:200659$14633_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201474$14688 + cell $reduce_or $reduce_or$libresoc.v:200662$14636 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:201474$14688_Y + connect \Y $reduce_or$libresoc.v:200662$14636_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201476$14690 + cell $reduce_or $reduce_or$libresoc.v:200664$14638 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:201476$14690_Y + connect \Y $reduce_or$libresoc.v:200664$14638_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201478$14692 + cell $reduce_or $reduce_or$libresoc.v:200666$14640 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:201478$14692_Y + connect \Y $reduce_or$libresoc.v:200666$14640_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201480$14694 + cell $reduce_or $reduce_or$libresoc.v:200668$14642 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:201480$14694_Y + connect \Y $reduce_or$libresoc.v:200668$14642_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201482$14696 + cell $reduce_or $reduce_or$libresoc.v:200670$14644 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A { \i [8:0] \ni [9] } - connect \Y $reduce_or$libresoc.v:201482$14696_Y + connect \Y $reduce_or$libresoc.v:200670$14644_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201484$14698 + cell $reduce_or $reduce_or$libresoc.v:200672$14646 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201484$14698_Y + connect \Y $reduce_or$libresoc.v:200672$14646_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201485$14699 + cell $reduce_or $reduce_or$libresoc.v:200673$14647 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:201485$14699_Y + connect \Y $reduce_or$libresoc.v:200673$14647_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201487$14701 + cell $reduce_or $reduce_or$libresoc.v:200675$14649 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:201487$14701_Y - end - connect \$7 $not$libresoc.v:201468$14682_Y - connect \$12 $reduce_or$libresoc.v:201469$14683_Y - connect \$11 $not$libresoc.v:201470$14684_Y - connect \$16 $reduce_or$libresoc.v:201471$14685_Y - connect \$15 $not$libresoc.v:201472$14686_Y - connect \$1 $not$libresoc.v:201473$14687_Y - connect \$20 $reduce_or$libresoc.v:201474$14688_Y - connect \$19 $not$libresoc.v:201475$14689_Y - connect \$24 $reduce_or$libresoc.v:201476$14690_Y - connect \$23 $not$libresoc.v:201477$14691_Y - connect \$28 $reduce_or$libresoc.v:201478$14692_Y - connect \$27 $not$libresoc.v:201479$14693_Y - connect \$32 $reduce_or$libresoc.v:201480$14694_Y - connect \$31 $not$libresoc.v:201481$14695_Y - connect \$36 $reduce_or$libresoc.v:201482$14696_Y - connect \$35 $not$libresoc.v:201483$14697_Y - connect \$39 $reduce_or$libresoc.v:201484$14698_Y - connect \$4 $reduce_or$libresoc.v:201485$14699_Y - connect \$3 $not$libresoc.v:201486$14700_Y - connect \$8 $reduce_or$libresoc.v:201487$14701_Y + connect \Y $reduce_or$libresoc.v:200675$14649_Y + end + connect \$7 $not$libresoc.v:200656$14630_Y + connect \$12 $reduce_or$libresoc.v:200657$14631_Y + connect \$11 $not$libresoc.v:200658$14632_Y + connect \$16 $reduce_or$libresoc.v:200659$14633_Y + connect \$15 $not$libresoc.v:200660$14634_Y + connect \$1 $not$libresoc.v:200661$14635_Y + connect \$20 $reduce_or$libresoc.v:200662$14636_Y + connect \$19 $not$libresoc.v:200663$14637_Y + connect \$24 $reduce_or$libresoc.v:200664$14638_Y + connect \$23 $not$libresoc.v:200665$14639_Y + connect \$28 $reduce_or$libresoc.v:200666$14640_Y + connect \$27 $not$libresoc.v:200667$14641_Y + connect \$32 $reduce_or$libresoc.v:200668$14642_Y + connect \$31 $not$libresoc.v:200669$14643_Y + connect \$36 $reduce_or$libresoc.v:200670$14644_Y + connect \$35 $not$libresoc.v:200671$14645_Y + connect \$39 $reduce_or$libresoc.v:200672$14646_Y + connect \$4 $reduce_or$libresoc.v:200673$14647_Y + connect \$3 $not$libresoc.v:200674$14648_Y + connect \$8 $reduce_or$libresoc.v:200675$14649_Y connect \en_o \$39 connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t9 \$35 @@ -421373,15 +416640,15 @@ module \wrpick_INT_o connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:201505.1-201526.10" +attribute \src "libresoc.v:200693.1-200714.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1" attribute \generator "nMigen" module \wrpick_SPR_spr1 - attribute \src "libresoc.v:201520.17-201520.89" - wire $not$libresoc.v:201520$14702_Y - attribute \src "libresoc.v:201521.17-201521.89" - wire $reduce_or$libresoc.v:201521$14703_Y + attribute \src "libresoc.v:200708.17-200708.89" + wire $not$libresoc.v:200708$14650_Y + attribute \src "libresoc.v:200709.17-200709.89" + wire $reduce_or$libresoc.v:200709$14651_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -421397,37 +416664,37 @@ module \wrpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201520$14702 + cell $not $not$libresoc.v:200708$14650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:201520$14702_Y + connect \Y $not$libresoc.v:200708$14650_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201521$14703 + cell $reduce_or $reduce_or$libresoc.v:200709$14651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201521$14703_Y + connect \Y $reduce_or$libresoc.v:200709$14651_Y end - connect \$1 $not$libresoc.v:201520$14702_Y - connect \$3 $reduce_or$libresoc.v:201521$14703_Y + connect \$1 $not$libresoc.v:200708$14650_Y + connect \$3 $reduce_or$libresoc.v:200709$14651_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:201530.1-201551.10" +attribute \src "libresoc.v:200718.1-200739.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr" attribute \generator "nMigen" module \wrpick_STATE_msr - attribute \src "libresoc.v:201545.17-201545.89" - wire $not$libresoc.v:201545$14704_Y - attribute \src "libresoc.v:201546.17-201546.89" - wire $reduce_or$libresoc.v:201546$14705_Y + attribute \src "libresoc.v:200733.17-200733.89" + wire $not$libresoc.v:200733$14652_Y + attribute \src "libresoc.v:200734.17-200734.89" + wire $reduce_or$libresoc.v:200734$14653_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -421443,41 +416710,41 @@ module \wrpick_STATE_msr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201545$14704 + cell $not $not$libresoc.v:200733$14652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:201545$14704_Y + connect \Y $not$libresoc.v:200733$14652_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201546$14705 + cell $reduce_or $reduce_or$libresoc.v:200734$14653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201546$14705_Y + connect \Y $reduce_or$libresoc.v:200734$14653_Y end - connect \$1 $not$libresoc.v:201545$14704_Y - connect \$3 $reduce_or$libresoc.v:201546$14705_Y + connect \$1 $not$libresoc.v:200733$14652_Y + connect \$3 $reduce_or$libresoc.v:200734$14653_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:201555.1-201585.10" +attribute \src "libresoc.v:200743.1-200773.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia" attribute \generator "nMigen" module \wrpick_STATE_nia - attribute \src "libresoc.v:201576.17-201576.89" - wire width 2 $not$libresoc.v:201576$14706_Y - attribute \src "libresoc.v:201578.17-201578.91" - wire $not$libresoc.v:201578$14708_Y - attribute \src "libresoc.v:201577.17-201577.103" - wire $reduce_or$libresoc.v:201577$14707_Y - attribute \src "libresoc.v:201579.17-201579.89" - wire $reduce_or$libresoc.v:201579$14709_Y + attribute \src "libresoc.v:200764.17-200764.89" + wire width 2 $not$libresoc.v:200764$14654_Y + attribute \src "libresoc.v:200766.17-200766.91" + wire $not$libresoc.v:200766$14656_Y + attribute \src "libresoc.v:200765.17-200765.103" + wire $reduce_or$libresoc.v:200765$14655_Y + attribute \src "libresoc.v:200767.17-200767.89" + wire $reduce_or$libresoc.v:200767$14657_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -421499,64 +416766,64 @@ module \wrpick_STATE_nia attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201576$14706 + cell $not $not$libresoc.v:200764$14654 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:201576$14706_Y + connect \Y $not$libresoc.v:200764$14654_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201578$14708 + cell $not $not$libresoc.v:200766$14656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:201578$14708_Y + connect \Y $not$libresoc.v:200766$14656_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201577$14707 + cell $reduce_or $reduce_or$libresoc.v:200765$14655 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:201577$14707_Y + connect \Y $reduce_or$libresoc.v:200765$14655_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201579$14709 + cell $reduce_or $reduce_or$libresoc.v:200767$14657 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201579$14709_Y + connect \Y $reduce_or$libresoc.v:200767$14657_Y end - connect \$1 $not$libresoc.v:201576$14706_Y - connect \$4 $reduce_or$libresoc.v:201577$14707_Y - connect \$3 $not$libresoc.v:201578$14708_Y - connect \$7 $reduce_or$libresoc.v:201579$14709_Y + connect \$1 $not$libresoc.v:200764$14654_Y + connect \$4 $reduce_or$libresoc.v:200765$14655_Y + connect \$3 $not$libresoc.v:200766$14656_Y + connect \$7 $reduce_or$libresoc.v:200767$14657_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:201589.1-201628.10" +attribute \src "libresoc.v:200777.1-200816.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca" attribute \generator "nMigen" module \wrpick_XER_xer_ca - attribute \src "libresoc.v:201616.17-201616.91" - wire $not$libresoc.v:201616$14710_Y - attribute \src "libresoc.v:201618.17-201618.89" - wire width 3 $not$libresoc.v:201618$14712_Y - attribute \src "libresoc.v:201620.17-201620.91" - wire $not$libresoc.v:201620$14714_Y - attribute \src "libresoc.v:201617.18-201617.90" - wire $reduce_or$libresoc.v:201617$14711_Y - attribute \src "libresoc.v:201619.17-201619.103" - wire $reduce_or$libresoc.v:201619$14713_Y - attribute \src "libresoc.v:201621.17-201621.105" - wire $reduce_or$libresoc.v:201621$14715_Y + attribute \src "libresoc.v:200804.17-200804.91" + wire $not$libresoc.v:200804$14658_Y + attribute \src "libresoc.v:200806.17-200806.89" + wire width 3 $not$libresoc.v:200806$14660_Y + attribute \src "libresoc.v:200808.17-200808.91" + wire $not$libresoc.v:200808$14662_Y + attribute \src "libresoc.v:200805.18-200805.90" + wire $reduce_or$libresoc.v:200805$14659_Y + attribute \src "libresoc.v:200807.17-200807.103" + wire $reduce_or$libresoc.v:200807$14661_Y + attribute \src "libresoc.v:200809.17-200809.105" + wire $reduce_or$libresoc.v:200809$14663_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -421584,59 +416851,59 @@ module \wrpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201616$14710 + cell $not $not$libresoc.v:200804$14658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:201616$14710_Y + connect \Y $not$libresoc.v:200804$14658_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201618$14712 + cell $not $not$libresoc.v:200806$14660 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:201618$14712_Y + connect \Y $not$libresoc.v:200806$14660_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201620$14714 + cell $not $not$libresoc.v:200808$14662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:201620$14714_Y + connect \Y $not$libresoc.v:200808$14662_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201617$14711 + cell $reduce_or $reduce_or$libresoc.v:200805$14659 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201617$14711_Y + connect \Y $reduce_or$libresoc.v:200805$14659_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201619$14713 + cell $reduce_or $reduce_or$libresoc.v:200807$14661 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:201619$14713_Y + connect \Y $reduce_or$libresoc.v:200807$14661_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201621$14715 + cell $reduce_or $reduce_or$libresoc.v:200809$14663 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:201621$14715_Y - end - connect \$7 $not$libresoc.v:201616$14710_Y - connect \$11 $reduce_or$libresoc.v:201617$14711_Y - connect \$1 $not$libresoc.v:201618$14712_Y - connect \$4 $reduce_or$libresoc.v:201619$14713_Y - connect \$3 $not$libresoc.v:201620$14714_Y - connect \$8 $reduce_or$libresoc.v:201621$14715_Y + connect \Y $reduce_or$libresoc.v:200809$14663_Y + end + connect \$7 $not$libresoc.v:200804$14658_Y + connect \$11 $reduce_or$libresoc.v:200805$14659_Y + connect \$1 $not$libresoc.v:200806$14660_Y + connect \$4 $reduce_or$libresoc.v:200807$14661_Y + connect \$3 $not$libresoc.v:200808$14662_Y + connect \$8 $reduce_or$libresoc.v:200809$14663_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -421644,27 +416911,27 @@ module \wrpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:201632.1-201680.10" +attribute \src "libresoc.v:200820.1-200868.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov" attribute \generator "nMigen" module \wrpick_XER_xer_ov - attribute \src "libresoc.v:201665.17-201665.91" - wire $not$libresoc.v:201665$14716_Y - attribute \src "libresoc.v:201667.18-201667.93" - wire $not$libresoc.v:201667$14718_Y - attribute \src "libresoc.v:201669.17-201669.89" - wire width 4 $not$libresoc.v:201669$14720_Y - attribute \src "libresoc.v:201671.17-201671.91" - wire $not$libresoc.v:201671$14722_Y - attribute \src "libresoc.v:201666.18-201666.106" - wire $reduce_or$libresoc.v:201666$14717_Y - attribute \src "libresoc.v:201668.18-201668.90" - wire $reduce_or$libresoc.v:201668$14719_Y - attribute \src "libresoc.v:201670.17-201670.103" - wire $reduce_or$libresoc.v:201670$14721_Y - attribute \src "libresoc.v:201672.17-201672.105" - wire $reduce_or$libresoc.v:201672$14723_Y + attribute \src "libresoc.v:200853.17-200853.91" + wire $not$libresoc.v:200853$14664_Y + attribute \src "libresoc.v:200855.18-200855.93" + wire $not$libresoc.v:200855$14666_Y + attribute \src "libresoc.v:200857.17-200857.89" + wire width 4 $not$libresoc.v:200857$14668_Y + attribute \src "libresoc.v:200859.17-200859.91" + wire $not$libresoc.v:200859$14670_Y + attribute \src "libresoc.v:200854.18-200854.106" + wire $reduce_or$libresoc.v:200854$14665_Y + attribute \src "libresoc.v:200856.18-200856.90" + wire $reduce_or$libresoc.v:200856$14667_Y + attribute \src "libresoc.v:200858.17-200858.103" + wire $reduce_or$libresoc.v:200858$14669_Y + attribute \src "libresoc.v:200860.17-200860.105" + wire $reduce_or$libresoc.v:200860$14671_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -421698,77 +416965,77 @@ module \wrpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201665$14716 + cell $not $not$libresoc.v:200853$14664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:201665$14716_Y + connect \Y $not$libresoc.v:200853$14664_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201667$14718 + cell $not $not$libresoc.v:200855$14666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:201667$14718_Y + connect \Y $not$libresoc.v:200855$14666_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201669$14720 + cell $not $not$libresoc.v:200857$14668 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:201669$14720_Y + connect \Y $not$libresoc.v:200857$14668_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201671$14722 + cell $not $not$libresoc.v:200859$14670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:201671$14722_Y + connect \Y $not$libresoc.v:200859$14670_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201666$14717 + cell $reduce_or $reduce_or$libresoc.v:200854$14665 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:201666$14717_Y + connect \Y $reduce_or$libresoc.v:200854$14665_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201668$14719 + cell $reduce_or $reduce_or$libresoc.v:200856$14667 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201668$14719_Y + connect \Y $reduce_or$libresoc.v:200856$14667_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201670$14721 + cell $reduce_or $reduce_or$libresoc.v:200858$14669 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:201670$14721_Y + connect \Y $reduce_or$libresoc.v:200858$14669_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201672$14723 + cell $reduce_or $reduce_or$libresoc.v:200860$14671 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:201672$14723_Y - end - connect \$7 $not$libresoc.v:201665$14716_Y - connect \$12 $reduce_or$libresoc.v:201666$14717_Y - connect \$11 $not$libresoc.v:201667$14718_Y - connect \$15 $reduce_or$libresoc.v:201668$14719_Y - connect \$1 $not$libresoc.v:201669$14720_Y - connect \$4 $reduce_or$libresoc.v:201670$14721_Y - connect \$3 $not$libresoc.v:201671$14722_Y - connect \$8 $reduce_or$libresoc.v:201672$14723_Y + connect \Y $reduce_or$libresoc.v:200860$14671_Y + end + connect \$7 $not$libresoc.v:200853$14664_Y + connect \$12 $reduce_or$libresoc.v:200854$14665_Y + connect \$11 $not$libresoc.v:200855$14666_Y + connect \$15 $reduce_or$libresoc.v:200856$14667_Y + connect \$1 $not$libresoc.v:200857$14668_Y + connect \$4 $reduce_or$libresoc.v:200858$14669_Y + connect \$3 $not$libresoc.v:200859$14670_Y + connect \$8 $reduce_or$libresoc.v:200860$14671_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -421777,27 +417044,27 @@ module \wrpick_XER_xer_ov connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:201684.1-201732.10" +attribute \src "libresoc.v:200872.1-200920.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_so" attribute \generator "nMigen" module \wrpick_XER_xer_so - attribute \src "libresoc.v:201717.17-201717.91" - wire $not$libresoc.v:201717$14724_Y - attribute \src "libresoc.v:201719.18-201719.93" - wire $not$libresoc.v:201719$14726_Y - attribute \src "libresoc.v:201721.17-201721.89" - wire width 4 $not$libresoc.v:201721$14728_Y - attribute \src "libresoc.v:201723.17-201723.91" - wire $not$libresoc.v:201723$14730_Y - attribute \src "libresoc.v:201718.18-201718.106" - wire $reduce_or$libresoc.v:201718$14725_Y - attribute \src "libresoc.v:201720.18-201720.90" - wire $reduce_or$libresoc.v:201720$14727_Y - attribute \src "libresoc.v:201722.17-201722.103" - wire $reduce_or$libresoc.v:201722$14729_Y - attribute \src "libresoc.v:201724.17-201724.105" - wire $reduce_or$libresoc.v:201724$14731_Y + attribute \src "libresoc.v:200905.17-200905.91" + wire $not$libresoc.v:200905$14672_Y + attribute \src "libresoc.v:200907.18-200907.93" + wire $not$libresoc.v:200907$14674_Y + attribute \src "libresoc.v:200909.17-200909.89" + wire width 4 $not$libresoc.v:200909$14676_Y + attribute \src "libresoc.v:200911.17-200911.91" + wire $not$libresoc.v:200911$14678_Y + attribute \src "libresoc.v:200906.18-200906.106" + wire $reduce_or$libresoc.v:200906$14673_Y + attribute \src "libresoc.v:200908.18-200908.90" + wire $reduce_or$libresoc.v:200908$14675_Y + attribute \src "libresoc.v:200910.17-200910.103" + wire $reduce_or$libresoc.v:200910$14677_Y + attribute \src "libresoc.v:200912.17-200912.105" + wire $reduce_or$libresoc.v:200912$14679_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -421831,77 +417098,77 @@ module \wrpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201717$14724 + cell $not $not$libresoc.v:200905$14672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:201717$14724_Y + connect \Y $not$libresoc.v:200905$14672_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201719$14726 + cell $not $not$libresoc.v:200907$14674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:201719$14726_Y + connect \Y $not$libresoc.v:200907$14674_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:201721$14728 + cell $not $not$libresoc.v:200909$14676 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:201721$14728_Y + connect \Y $not$libresoc.v:200909$14676_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:201723$14730 + cell $not $not$libresoc.v:200911$14678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:201723$14730_Y + connect \Y $not$libresoc.v:200911$14678_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201718$14725 + cell $reduce_or $reduce_or$libresoc.v:200906$14673 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:201718$14725_Y + connect \Y $reduce_or$libresoc.v:200906$14673_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:201720$14727 + cell $reduce_or $reduce_or$libresoc.v:200908$14675 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:201720$14727_Y + connect \Y $reduce_or$libresoc.v:200908$14675_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201722$14729 + cell $reduce_or $reduce_or$libresoc.v:200910$14677 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:201722$14729_Y + connect \Y $reduce_or$libresoc.v:200910$14677_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:201724$14731 + cell $reduce_or $reduce_or$libresoc.v:200912$14679 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:201724$14731_Y - end - connect \$7 $not$libresoc.v:201717$14724_Y - connect \$12 $reduce_or$libresoc.v:201718$14725_Y - connect \$11 $not$libresoc.v:201719$14726_Y - connect \$15 $reduce_or$libresoc.v:201720$14727_Y - connect \$1 $not$libresoc.v:201721$14728_Y - connect \$4 $reduce_or$libresoc.v:201722$14729_Y - connect \$3 $not$libresoc.v:201723$14730_Y - connect \$8 $reduce_or$libresoc.v:201724$14731_Y + connect \Y $reduce_or$libresoc.v:200912$14679_Y + end + connect \$7 $not$libresoc.v:200905$14672_Y + connect \$12 $reduce_or$libresoc.v:200906$14673_Y + connect \$11 $not$libresoc.v:200907$14674_Y + connect \$15 $reduce_or$libresoc.v:200908$14675_Y + connect \$1 $not$libresoc.v:200909$14676_Y + connect \$4 $reduce_or$libresoc.v:200910$14677_Y + connect \$3 $not$libresoc.v:200911$14678_Y + connect \$8 $reduce_or$libresoc.v:200912$14679_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -421910,67 +417177,67 @@ module \wrpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:201736.1-202056.10" +attribute \src "libresoc.v:200924.1-201244.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer" attribute \generator "nMigen" module \xer - attribute \src "libresoc.v:201737.7-201737.20" + attribute \src "libresoc.v:200925.7-200925.20" wire $0\initial[0:0] - attribute \src "libresoc.v:202016.3-202024.6" - wire width 3 $0\ren_delay$11$next[2:0]$14755 - attribute \src "libresoc.v:201914.3-201915.43" - wire width 3 $0\ren_delay$11[2:0]$14744 - attribute \src "libresoc.v:201873.13-201873.34" - wire width 3 $0\ren_delay$11[2:0]$14761 - attribute \src "libresoc.v:201978.3-201986.6" - wire width 3 $0\ren_delay$18$next[2:0]$14747 - attribute \src "libresoc.v:201912.3-201913.43" - wire width 3 $0\ren_delay$18[2:0]$14742 - attribute \src "libresoc.v:201877.13-201877.34" - wire width 3 $0\ren_delay$18[2:0]$14763 - attribute \src "libresoc.v:201997.3-202005.6" - wire width 3 $0\ren_delay$next[2:0]$14751 - attribute \src "libresoc.v:201916.3-201917.35" + attribute \src "libresoc.v:201204.3-201212.6" + wire width 3 $0\ren_delay$11$next[2:0]$14703 + attribute \src "libresoc.v:201102.3-201103.43" + wire width 3 $0\ren_delay$11[2:0]$14692 + attribute \src "libresoc.v:201061.13-201061.34" + wire width 3 $0\ren_delay$11[2:0]$14709 + attribute \src "libresoc.v:201166.3-201174.6" + wire width 3 $0\ren_delay$18$next[2:0]$14695 + attribute \src "libresoc.v:201100.3-201101.43" + wire width 3 $0\ren_delay$18[2:0]$14690 + attribute \src "libresoc.v:201065.13-201065.34" + wire width 3 $0\ren_delay$18[2:0]$14711 + attribute \src "libresoc.v:201185.3-201193.6" + wire width 3 $0\ren_delay$next[2:0]$14699 + attribute \src "libresoc.v:201104.3-201105.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:202006.3-202015.6" + attribute \src "libresoc.v:201194.3-201203.6" wire width 2 $0\src1__data_o[1:0] - attribute \src "libresoc.v:202025.3-202034.6" + attribute \src "libresoc.v:201213.3-201222.6" wire width 2 $0\src2__data_o[1:0] - attribute \src "libresoc.v:201987.3-201996.6" + attribute \src "libresoc.v:201175.3-201184.6" wire width 2 $0\src3__data_o[1:0] - attribute \src "libresoc.v:202016.3-202024.6" - wire width 3 $1\ren_delay$11$next[2:0]$14756 - attribute \src "libresoc.v:201978.3-201986.6" - wire width 3 $1\ren_delay$18$next[2:0]$14748 - attribute \src "libresoc.v:201997.3-202005.6" - wire width 3 $1\ren_delay$next[2:0]$14752 - attribute \src "libresoc.v:201871.13-201871.29" + attribute \src "libresoc.v:201204.3-201212.6" + wire width 3 $1\ren_delay$11$next[2:0]$14704 + attribute \src "libresoc.v:201166.3-201174.6" + wire width 3 $1\ren_delay$18$next[2:0]$14696 + attribute \src "libresoc.v:201185.3-201193.6" + wire width 3 $1\ren_delay$next[2:0]$14700 + attribute \src "libresoc.v:201059.13-201059.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:202006.3-202015.6" + attribute \src "libresoc.v:201194.3-201203.6" wire width 2 $1\src1__data_o[1:0] - attribute \src "libresoc.v:202025.3-202034.6" + attribute \src "libresoc.v:201213.3-201222.6" wire width 2 $1\src2__data_o[1:0] - attribute \src "libresoc.v:201987.3-201996.6" + attribute \src "libresoc.v:201175.3-201184.6" wire width 2 $1\src3__data_o[1:0] - attribute \src "libresoc.v:201903.17-201903.109" - wire width 2 $or$libresoc.v:201903$14732_Y - attribute \src "libresoc.v:201905.18-201905.126" - wire width 2 $or$libresoc.v:201905$14734_Y - attribute \src "libresoc.v:201906.18-201906.111" - wire width 2 $or$libresoc.v:201906$14735_Y - attribute \src "libresoc.v:201908.18-201908.126" - wire width 2 $or$libresoc.v:201908$14737_Y - attribute \src "libresoc.v:201909.18-201909.111" - wire width 2 $or$libresoc.v:201909$14738_Y - attribute \src "libresoc.v:201911.17-201911.125" - wire width 2 $or$libresoc.v:201911$14740_Y - attribute \src "libresoc.v:201904.18-201904.100" - wire $reduce_or$libresoc.v:201904$14733_Y - attribute \src "libresoc.v:201907.18-201907.100" - wire $reduce_or$libresoc.v:201907$14736_Y - attribute \src "libresoc.v:201910.17-201910.95" - wire $reduce_or$libresoc.v:201910$14739_Y + attribute \src "libresoc.v:201091.17-201091.109" + wire width 2 $or$libresoc.v:201091$14680_Y + attribute \src "libresoc.v:201093.18-201093.126" + wire width 2 $or$libresoc.v:201093$14682_Y + attribute \src "libresoc.v:201094.18-201094.111" + wire width 2 $or$libresoc.v:201094$14683_Y + attribute \src "libresoc.v:201096.18-201096.126" + wire width 2 $or$libresoc.v:201096$14685_Y + attribute \src "libresoc.v:201097.18-201097.111" + wire width 2 $or$libresoc.v:201097$14686_Y + attribute \src "libresoc.v:201099.17-201099.125" + wire width 2 $or$libresoc.v:201099$14688_Y + attribute \src "libresoc.v:201092.18-201092.100" + wire $reduce_or$libresoc.v:201092$14681_Y + attribute \src "libresoc.v:201095.18-201095.100" + wire $reduce_or$libresoc.v:201095$14684_Y + attribute \src "libresoc.v:201098.17-201098.95" + wire $reduce_or$libresoc.v:201098$14687_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" @@ -422007,7 +417274,7 @@ module \xer wire width 6 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \full_wr__wen - attribute \src "libresoc.v:201737.7-201737.15" + attribute \src "libresoc.v:200925.7-200925.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_dest10__data_i @@ -422136,7 +417403,7 @@ module \xer attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:201903$14732 + cell $or $or$libresoc.v:201091$14680 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -422144,10 +417411,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src10__data_o connect \B \$7 - connect \Y $or$libresoc.v:201903$14732_Y + connect \Y $or$libresoc.v:201091$14680_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:201905$14734 + cell $or $or$libresoc.v:201093$14682 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -422155,10 +417422,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src21__data_o connect \B \reg_2_src22__data_o - connect \Y $or$libresoc.v:201905$14734_Y + connect \Y $or$libresoc.v:201093$14682_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:201906$14735 + cell $or $or$libresoc.v:201094$14683 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -422166,10 +417433,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src20__data_o connect \B \$14 - connect \Y $or$libresoc.v:201906$14735_Y + connect \Y $or$libresoc.v:201094$14683_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:201908$14737 + cell $or $or$libresoc.v:201096$14685 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -422177,10 +417444,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src31__data_o connect \B \reg_2_src32__data_o - connect \Y $or$libresoc.v:201908$14737_Y + connect \Y $or$libresoc.v:201096$14685_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:201909$14738 + cell $or $or$libresoc.v:201097$14686 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -422188,10 +417455,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src30__data_o connect \B \$21 - connect \Y $or$libresoc.v:201909$14738_Y + connect \Y $or$libresoc.v:201097$14686_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:201911$14740 + cell $or $or$libresoc.v:201099$14688 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -422199,34 +417466,34 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src11__data_o connect \B \reg_2_src12__data_o - connect \Y $or$libresoc.v:201911$14740_Y + connect \Y $or$libresoc.v:201099$14688_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:201904$14733 + cell $reduce_or $reduce_or$libresoc.v:201092$14681 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$11 - connect \Y $reduce_or$libresoc.v:201904$14733_Y + connect \Y $reduce_or$libresoc.v:201092$14681_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:201907$14736 + cell $reduce_or $reduce_or$libresoc.v:201095$14684 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$18 - connect \Y $reduce_or$libresoc.v:201907$14736_Y + connect \Y $reduce_or$libresoc.v:201095$14684_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:201910$14739 + cell $reduce_or $reduce_or$libresoc.v:201098$14687 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:201910$14739_Y + connect \Y $reduce_or$libresoc.v:201098$14687_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:201918.15-201937.4" + attribute \src "libresoc.v:201106.15-201125.4" cell \reg_0$132 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -422248,7 +417515,7 @@ module \xer connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:201938.15-201957.4" + attribute \src "libresoc.v:201126.15-201145.4" cell \reg_1$133 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -422270,7 +417537,7 @@ module \xer connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:201958.15-201977.4" + attribute \src "libresoc.v:201146.15-201165.4" cell \reg_2$134 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -422291,67 +417558,67 @@ module \xer connect \w2__data_i \reg_2_w2__data_i connect \w2__wen \reg_2_w2__wen end - attribute \src "libresoc.v:201737.7-201737.20" - process $proc$libresoc.v:201737$14758 + attribute \src "libresoc.v:200925.7-200925.20" + process $proc$libresoc.v:200925$14706 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:201871.13-201871.29" - process $proc$libresoc.v:201871$14759 + attribute \src "libresoc.v:201059.13-201059.29" + process $proc$libresoc.v:201059$14707 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:201873.13-201873.34" - process $proc$libresoc.v:201873$14760 + attribute \src "libresoc.v:201061.13-201061.34" + process $proc$libresoc.v:201061$14708 assign { } { } - assign $0\ren_delay$11[2:0]$14761 3'000 + assign $0\ren_delay$11[2:0]$14709 3'000 sync always sync init - update \ren_delay$11 $0\ren_delay$11[2:0]$14761 + update \ren_delay$11 $0\ren_delay$11[2:0]$14709 end - attribute \src "libresoc.v:201877.13-201877.34" - process $proc$libresoc.v:201877$14762 + attribute \src "libresoc.v:201065.13-201065.34" + process $proc$libresoc.v:201065$14710 assign { } { } - assign $0\ren_delay$18[2:0]$14763 3'000 + assign $0\ren_delay$18[2:0]$14711 3'000 sync always sync init - update \ren_delay$18 $0\ren_delay$18[2:0]$14763 + update \ren_delay$18 $0\ren_delay$18[2:0]$14711 end - attribute \src "libresoc.v:201912.3-201913.43" - process $proc$libresoc.v:201912$14741 + attribute \src "libresoc.v:201100.3-201101.43" + process $proc$libresoc.v:201100$14689 assign { } { } - assign $0\ren_delay$18[2:0]$14742 \ren_delay$18$next + assign $0\ren_delay$18[2:0]$14690 \ren_delay$18$next sync posedge \coresync_clk - update \ren_delay$18 $0\ren_delay$18[2:0]$14742 + update \ren_delay$18 $0\ren_delay$18[2:0]$14690 end - attribute \src "libresoc.v:201914.3-201915.43" - process $proc$libresoc.v:201914$14743 + attribute \src "libresoc.v:201102.3-201103.43" + process $proc$libresoc.v:201102$14691 assign { } { } - assign $0\ren_delay$11[2:0]$14744 \ren_delay$11$next + assign $0\ren_delay$11[2:0]$14692 \ren_delay$11$next sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[2:0]$14744 + update \ren_delay$11 $0\ren_delay$11[2:0]$14692 end - attribute \src "libresoc.v:201916.3-201917.35" - process $proc$libresoc.v:201916$14745 + attribute \src "libresoc.v:201104.3-201105.35" + process $proc$libresoc.v:201104$14693 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:201978.3-201986.6" - process $proc$libresoc.v:201978$14746 + attribute \src "libresoc.v:201166.3-201174.6" + process $proc$libresoc.v:201166$14694 assign { } { } assign { } { } - assign $0\ren_delay$18$next[2:0]$14747 $1\ren_delay$18$next[2:0]$14748 - attribute \src "libresoc.v:201979.5-201979.29" + assign $0\ren_delay$18$next[2:0]$14695 $1\ren_delay$18$next[2:0]$14696 + attribute \src "libresoc.v:201167.5-201167.29" switch \initial - attribute \src "libresoc.v:201979.9-201979.17" + attribute \src "libresoc.v:201167.9-201167.17" case 1'1 case end @@ -422360,21 +417627,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$18$next[2:0]$14748 3'000 + assign $1\ren_delay$18$next[2:0]$14696 3'000 case - assign $1\ren_delay$18$next[2:0]$14748 \src3__ren + assign $1\ren_delay$18$next[2:0]$14696 \src3__ren end sync always - update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14747 + update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14695 end - attribute \src "libresoc.v:201987.3-201996.6" - process $proc$libresoc.v:201987$14749 + attribute \src "libresoc.v:201175.3-201184.6" + process $proc$libresoc.v:201175$14697 assign { } { } assign { } { } assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] - attribute \src "libresoc.v:201988.5-201988.29" + attribute \src "libresoc.v:201176.5-201176.29" switch \initial - attribute \src "libresoc.v:201988.9-201988.17" + attribute \src "libresoc.v:201176.9-201176.17" case 1'1 case end @@ -422390,14 +417657,14 @@ module \xer sync always update \src3__data_o $0\src3__data_o[1:0] end - attribute \src "libresoc.v:201997.3-202005.6" - process $proc$libresoc.v:201997$14750 + attribute \src "libresoc.v:201185.3-201193.6" + process $proc$libresoc.v:201185$14698 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$14751 $1\ren_delay$next[2:0]$14752 - attribute \src "libresoc.v:201998.5-201998.29" + assign $0\ren_delay$next[2:0]$14699 $1\ren_delay$next[2:0]$14700 + attribute \src "libresoc.v:201186.5-201186.29" switch \initial - attribute \src "libresoc.v:201998.9-201998.17" + attribute \src "libresoc.v:201186.9-201186.17" case 1'1 case end @@ -422406,21 +417673,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$14752 3'000 + assign $1\ren_delay$next[2:0]$14700 3'000 case - assign $1\ren_delay$next[2:0]$14752 \src1__ren + assign $1\ren_delay$next[2:0]$14700 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$14751 + update \ren_delay$next $0\ren_delay$next[2:0]$14699 end - attribute \src "libresoc.v:202006.3-202015.6" - process $proc$libresoc.v:202006$14753 + attribute \src "libresoc.v:201194.3-201203.6" + process $proc$libresoc.v:201194$14701 assign { } { } assign { } { } assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] - attribute \src "libresoc.v:202007.5-202007.29" + attribute \src "libresoc.v:201195.5-201195.29" switch \initial - attribute \src "libresoc.v:202007.9-202007.17" + attribute \src "libresoc.v:201195.9-201195.17" case 1'1 case end @@ -422436,14 +417703,14 @@ module \xer sync always update \src1__data_o $0\src1__data_o[1:0] end - attribute \src "libresoc.v:202016.3-202024.6" - process $proc$libresoc.v:202016$14754 + attribute \src "libresoc.v:201204.3-201212.6" + process $proc$libresoc.v:201204$14702 assign { } { } assign { } { } - assign $0\ren_delay$11$next[2:0]$14755 $1\ren_delay$11$next[2:0]$14756 - attribute \src "libresoc.v:202017.5-202017.29" + assign $0\ren_delay$11$next[2:0]$14703 $1\ren_delay$11$next[2:0]$14704 + attribute \src "libresoc.v:201205.5-201205.29" switch \initial - attribute \src "libresoc.v:202017.9-202017.17" + attribute \src "libresoc.v:201205.9-201205.17" case 1'1 case end @@ -422452,21 +417719,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[2:0]$14756 3'000 + assign $1\ren_delay$11$next[2:0]$14704 3'000 case - assign $1\ren_delay$11$next[2:0]$14756 \src2__ren + assign $1\ren_delay$11$next[2:0]$14704 \src2__ren end sync always - update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14755 + update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14703 end - attribute \src "libresoc.v:202025.3-202034.6" - process $proc$libresoc.v:202025$14757 + attribute \src "libresoc.v:201213.3-201222.6" + process $proc$libresoc.v:201213$14705 assign { } { } assign { } { } assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] - attribute \src "libresoc.v:202026.5-202026.29" + attribute \src "libresoc.v:201214.5-201214.29" switch \initial - attribute \src "libresoc.v:202026.9-202026.17" + attribute \src "libresoc.v:201214.9-201214.17" case 1'1 case end @@ -422482,15 +417749,15 @@ module \xer sync always update \src2__data_o $0\src2__data_o[1:0] end - connect \$9 $or$libresoc.v:201903$14732_Y - connect \$12 $reduce_or$libresoc.v:201904$14733_Y - connect \$14 $or$libresoc.v:201905$14734_Y - connect \$16 $or$libresoc.v:201906$14735_Y - connect \$19 $reduce_or$libresoc.v:201907$14736_Y - connect \$21 $or$libresoc.v:201908$14737_Y - connect \$23 $or$libresoc.v:201909$14738_Y - connect \$5 $reduce_or$libresoc.v:201910$14739_Y - connect \$7 $or$libresoc.v:201911$14740_Y + connect \$9 $or$libresoc.v:201091$14680_Y + connect \$12 $reduce_or$libresoc.v:201092$14681_Y + connect \$14 $or$libresoc.v:201093$14682_Y + connect \$16 $or$libresoc.v:201094$14683_Y + connect \$19 $reduce_or$libresoc.v:201095$14684_Y + connect \$21 $or$libresoc.v:201096$14685_Y + connect \$23 $or$libresoc.v:201097$14686_Y + connect \$5 $reduce_or$libresoc.v:201098$14687_Y + connect \$7 $or$libresoc.v:201099$14688_Y connect \full_wr__data_i 6'000000 connect \full_wr__wen 3'000 connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 @@ -422513,153 +417780,153 @@ module \xer connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end -attribute \src "libresoc.v:202060.1-202374.10" +attribute \src "libresoc.v:201248.1-201562.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" attribute \generator "nMigen" module \xics_icp - attribute \src "libresoc.v:202238.3-202266.6" + attribute \src "libresoc.v:201426.3-201454.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:202289.3-202297.6" - wire $0\core_irq_o$next[0:0]$14799 - attribute \src "libresoc.v:202180.3-202181.37" + attribute \src "libresoc.v:201477.3-201485.6" + wire $0\core_irq_o$next[0:0]$14747 + attribute \src "libresoc.v:201368.3-201369.37" wire $0\core_irq_o[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $0\cppr$10[7:0]$14803 - attribute \src "libresoc.v:202194.3-202209.6" - wire width 8 $0\cppr$next[7:0]$14782 - attribute \src "libresoc.v:202184.3-202185.25" + attribute \src "libresoc.v:201496.3-201558.6" + wire width 8 $0\cppr$10[7:0]$14751 + attribute \src "libresoc.v:201382.3-201397.6" + wire width 8 $0\cppr$next[7:0]$14730 + attribute \src "libresoc.v:201372.3-201373.25" wire width 8 $0\cppr[7:0] - attribute \src "libresoc.v:202298.3-202307.6" + attribute \src "libresoc.v:201486.3-201495.6" wire width 32 $0\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:202061.7-202061.20" + attribute \src "libresoc.v:201249.7-201249.20" wire $0\initial[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire $0\irq$12[0:0]$14804 - attribute \src "libresoc.v:202194.3-202209.6" - wire $0\irq$next[0:0]$14783 - attribute \src "libresoc.v:202188.3-202189.23" + attribute \src "libresoc.v:201496.3-201558.6" + wire $0\irq$12[0:0]$14752 + attribute \src "libresoc.v:201382.3-201397.6" + wire $0\irq$next[0:0]$14731 + attribute \src "libresoc.v:201376.3-201377.23" wire $0\irq[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $0\mfrr$11[7:0]$14805 - attribute \src "libresoc.v:202194.3-202209.6" - wire width 8 $0\mfrr$next[7:0]$14784 - attribute \src "libresoc.v:202186.3-202187.25" + attribute \src "libresoc.v:201496.3-201558.6" + wire width 8 $0\mfrr$11[7:0]$14753 + attribute \src "libresoc.v:201382.3-201397.6" + wire width 8 $0\mfrr$next[7:0]$14732 + attribute \src "libresoc.v:201374.3-201375.25" wire width 8 $0\mfrr[7:0] - attribute \src "libresoc.v:202277.3-202288.6" + attribute \src "libresoc.v:201465.3-201476.6" wire width 8 $0\min_pri[7:0] - attribute \src "libresoc.v:202267.3-202276.6" + attribute \src "libresoc.v:201455.3-201464.6" wire width 8 $0\pending_priority[7:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire $0\wb_ack$14[0:0]$14806 - attribute \src "libresoc.v:202194.3-202209.6" - wire $0\wb_ack$next[0:0]$14785 - attribute \src "libresoc.v:202192.3-202193.29" + attribute \src "libresoc.v:201496.3-201558.6" + wire $0\wb_ack$14[0:0]$14754 + attribute \src "libresoc.v:201382.3-201397.6" + wire $0\wb_ack$next[0:0]$14733 + attribute \src "libresoc.v:201380.3-201381.29" wire $0\wb_ack[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 32 $0\wb_rd_data$13[31:0]$14807 - attribute \src "libresoc.v:202194.3-202209.6" - wire width 32 $0\wb_rd_data$next[31:0]$14786 - attribute \src "libresoc.v:202190.3-202191.37" + attribute \src "libresoc.v:201496.3-201558.6" + wire width 32 $0\wb_rd_data$13[31:0]$14755 + attribute \src "libresoc.v:201382.3-201397.6" + wire width 32 $0\wb_rd_data$next[31:0]$14734 + attribute \src "libresoc.v:201378.3-201379.37" wire width 32 $0\wb_rd_data[31:0] - attribute \src "libresoc.v:202210.3-202237.6" + attribute \src "libresoc.v:201398.3-201425.6" wire $0\xirr_accept_rd[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 24 $0\xisr$9[23:0]$14808 - attribute \src "libresoc.v:202194.3-202209.6" - wire width 24 $0\xisr$next[23:0]$14787 - attribute \src "libresoc.v:202182.3-202183.25" + attribute \src "libresoc.v:201496.3-201558.6" + wire width 24 $0\xisr$9[23:0]$14756 + attribute \src "libresoc.v:201382.3-201397.6" + wire width 24 $0\xisr$next[23:0]$14735 + attribute \src "libresoc.v:201370.3-201371.25" wire width 24 $0\xisr[23:0] - attribute \src "libresoc.v:202238.3-202266.6" + attribute \src "libresoc.v:201426.3-201454.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:202289.3-202297.6" - wire $1\core_irq_o$next[0:0]$14800 - attribute \src "libresoc.v:202090.7-202090.24" + attribute \src "libresoc.v:201477.3-201485.6" + wire $1\core_irq_o$next[0:0]$14748 + attribute \src "libresoc.v:201278.7-201278.24" wire $1\core_irq_o[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $1\cppr$10[7:0]$14809 - attribute \src "libresoc.v:202194.3-202209.6" - wire width 8 $1\cppr$next[7:0]$14788 - attribute \src "libresoc.v:202094.13-202094.25" + attribute \src "libresoc.v:201496.3-201558.6" + wire width 8 $1\cppr$10[7:0]$14757 + attribute \src "libresoc.v:201382.3-201397.6" + wire width 8 $1\cppr$next[7:0]$14736 + attribute \src "libresoc.v:201282.13-201282.25" wire width 8 $1\cppr[7:0] - attribute \src "libresoc.v:202298.3-202307.6" + attribute \src "libresoc.v:201486.3-201495.6" wire width 32 $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire $1\irq$12[0:0]$14819 - attribute \src "libresoc.v:202194.3-202209.6" - wire $1\irq$next[0:0]$14789 - attribute \src "libresoc.v:202123.7-202123.17" + attribute \src "libresoc.v:201496.3-201558.6" + wire $1\irq$12[0:0]$14767 + attribute \src "libresoc.v:201382.3-201397.6" + wire $1\irq$next[0:0]$14737 + attribute \src "libresoc.v:201311.7-201311.17" wire $1\irq[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $1\mfrr$11[7:0]$14810 - attribute \src "libresoc.v:202194.3-202209.6" - wire width 8 $1\mfrr$next[7:0]$14790 - attribute \src "libresoc.v:202131.13-202131.25" + attribute \src "libresoc.v:201496.3-201558.6" + wire width 8 $1\mfrr$11[7:0]$14758 + attribute \src "libresoc.v:201382.3-201397.6" + wire width 8 $1\mfrr$next[7:0]$14738 + attribute \src "libresoc.v:201319.13-201319.25" wire width 8 $1\mfrr[7:0] - attribute \src "libresoc.v:202277.3-202288.6" + attribute \src "libresoc.v:201465.3-201476.6" wire width 8 $1\min_pri[7:0] - attribute \src "libresoc.v:202267.3-202276.6" + attribute \src "libresoc.v:201455.3-201464.6" wire width 8 $1\pending_priority[7:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire $1\wb_ack$14[0:0]$14811 - attribute \src "libresoc.v:202194.3-202209.6" - wire $1\wb_ack$next[0:0]$14791 - attribute \src "libresoc.v:202145.7-202145.20" + attribute \src "libresoc.v:201496.3-201558.6" + wire $1\wb_ack$14[0:0]$14759 + attribute \src "libresoc.v:201382.3-201397.6" + wire $1\wb_ack$next[0:0]$14739 + attribute \src "libresoc.v:201333.7-201333.20" wire $1\wb_ack[0:0] - attribute \src "libresoc.v:202194.3-202209.6" - wire width 32 $1\wb_rd_data$next[31:0]$14792 - attribute \src "libresoc.v:202153.14-202153.32" + attribute \src "libresoc.v:201382.3-201397.6" + wire width 32 $1\wb_rd_data$next[31:0]$14740 + attribute \src "libresoc.v:201341.14-201341.32" wire width 32 $1\wb_rd_data[31:0] - attribute \src "libresoc.v:202210.3-202237.6" + attribute \src "libresoc.v:201398.3-201425.6" wire $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 24 $1\xisr$9[23:0]$14816 - attribute \src "libresoc.v:202194.3-202209.6" - wire width 24 $1\xisr$next[23:0]$14793 - attribute \src "libresoc.v:202163.14-202163.31" + attribute \src "libresoc.v:201496.3-201558.6" + wire width 24 $1\xisr$9[23:0]$14764 + attribute \src "libresoc.v:201382.3-201397.6" + wire width 24 $1\xisr$next[23:0]$14741 + attribute \src "libresoc.v:201351.14-201351.31" wire width 24 $1\xisr[23:0] - attribute \src "libresoc.v:202238.3-202266.6" + attribute \src "libresoc.v:201426.3-201454.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $2\cppr$10[7:0]$14812 - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $2\mfrr$11[7:0]$14813 - attribute \src "libresoc.v:202210.3-202237.6" + attribute \src "libresoc.v:201496.3-201558.6" + wire width 8 $2\cppr$10[7:0]$14760 + attribute \src "libresoc.v:201496.3-201558.6" + wire width 8 $2\mfrr$11[7:0]$14761 + attribute \src "libresoc.v:201398.3-201425.6" wire $2\xirr_accept_rd[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 24 $2\xisr$9[23:0]$14817 - attribute \src "libresoc.v:202238.3-202266.6" + attribute \src "libresoc.v:201496.3-201558.6" + wire width 24 $2\xisr$9[23:0]$14765 + attribute \src "libresoc.v:201426.3-201454.6" wire width 32 $3\be_out[31:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $3\cppr$10[7:0]$14814 - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $3\mfrr$11[7:0]$14815 - attribute \src "libresoc.v:202210.3-202237.6" + attribute \src "libresoc.v:201496.3-201558.6" + wire width 8 $3\cppr$10[7:0]$14762 + attribute \src "libresoc.v:201496.3-201558.6" + wire width 8 $3\mfrr$11[7:0]$14763 + attribute \src "libresoc.v:201398.3-201425.6" wire $3\xirr_accept_rd[0:0] - attribute \src "libresoc.v:202308.3-202370.6" - wire width 8 $4\cppr$10[7:0]$14818 - attribute \src "libresoc.v:202210.3-202237.6" + attribute \src "libresoc.v:201496.3-201558.6" + wire width 8 $4\cppr$10[7:0]$14766 + attribute \src "libresoc.v:201398.3-201425.6" wire $4\xirr_accept_rd[0:0] - attribute \src "libresoc.v:202170.18-202170.116" - wire $and$libresoc.v:202170$14764_Y - attribute \src "libresoc.v:202174.18-202174.116" - wire $and$libresoc.v:202174$14768_Y - attribute \src "libresoc.v:202176.18-202176.116" - wire $and$libresoc.v:202176$14770_Y - attribute \src "libresoc.v:202179.17-202179.109" - wire $and$libresoc.v:202179$14773_Y - attribute \src "libresoc.v:202175.18-202175.110" - wire $eq$libresoc.v:202175$14769_Y - attribute \src "libresoc.v:202172.18-202172.114" - wire $lt$libresoc.v:202172$14766_Y - attribute \src "libresoc.v:202173.18-202173.109" - wire $lt$libresoc.v:202173$14767_Y - attribute \src "libresoc.v:202178.18-202178.114" - wire $lt$libresoc.v:202178$14772_Y - attribute \src "libresoc.v:202171.18-202171.109" - wire $ne$libresoc.v:202171$14765_Y - attribute \src "libresoc.v:202177.18-202177.109" - wire $ne$libresoc.v:202177$14771_Y + attribute \src "libresoc.v:201358.18-201358.116" + wire $and$libresoc.v:201358$14712_Y + attribute \src "libresoc.v:201362.18-201362.116" + wire $and$libresoc.v:201362$14716_Y + attribute \src "libresoc.v:201364.18-201364.116" + wire $and$libresoc.v:201364$14718_Y + attribute \src "libresoc.v:201367.17-201367.109" + wire $and$libresoc.v:201367$14721_Y + attribute \src "libresoc.v:201363.18-201363.110" + wire $eq$libresoc.v:201363$14717_Y + attribute \src "libresoc.v:201360.18-201360.114" + wire $lt$libresoc.v:201360$14714_Y + attribute \src "libresoc.v:201361.18-201361.109" + wire $lt$libresoc.v:201361$14715_Y + attribute \src "libresoc.v:201366.18-201366.114" + wire $lt$libresoc.v:201366$14720_Y + attribute \src "libresoc.v:201359.18-201359.109" + wire $ne$libresoc.v:201359$14713_Y + attribute \src "libresoc.v:201365.18-201365.109" + wire $ne$libresoc.v:201365$14719_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" @@ -422718,7 +417985,7 @@ module \xics_icp wire width 8 input 3 \ics_i_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 input 2 \ics_i_src - attribute \src "libresoc.v:202061.7-202061.15" + attribute \src "libresoc.v:201249.7-201249.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" wire \irq @@ -422769,7 +418036,7 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" wire width 24 \xisr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:202170$14764 + cell $and $and$libresoc.v:201358$14712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -422777,10 +418044,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:202170$14764_Y + connect \Y $and$libresoc.v:201358$14712_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:202174$14768 + cell $and $and$libresoc.v:201362$14716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -422788,10 +418055,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:202174$14768_Y + connect \Y $and$libresoc.v:201362$14716_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:202176$14770 + cell $and $and$libresoc.v:201364$14718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -422799,10 +418066,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:202176$14770_Y + connect \Y $and$libresoc.v:201364$14718_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" - cell $and $and$libresoc.v:202179$14773 + cell $and $and$libresoc.v:201367$14721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -422810,10 +418077,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \wb_ack connect \B \icp_wb__cyc - connect \Y $and$libresoc.v:202179$14773_Y + connect \Y $and$libresoc.v:201367$14721_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" - cell $eq $eq$libresoc.v:202175$14769 + cell $eq $eq$libresoc.v:201363$14717 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -422821,10 +418088,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__sel connect \B 4'1111 - connect \Y $eq$libresoc.v:202175$14769_Y + connect \Y $eq$libresoc.v:201363$14717_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:202172$14766 + cell $lt $lt$libresoc.v:201360$14714 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -422832,10 +418099,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:202172$14766_Y + connect \Y $lt$libresoc.v:201360$14714_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" - cell $lt $lt$libresoc.v:202173$14767 + cell $lt $lt$libresoc.v:201361$14715 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -422843,10 +418110,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \min_pri connect \B \cppr$10 - connect \Y $lt$libresoc.v:202173$14767_Y + connect \Y $lt$libresoc.v:201361$14715_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:202178$14772 + cell $lt $lt$libresoc.v:201366$14720 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -422854,10 +418121,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:202178$14772_Y + connect \Y $lt$libresoc.v:201366$14720_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:202171$14765 + cell $ne $ne$libresoc.v:201359$14713 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -422865,10 +418132,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:202171$14765_Y + connect \Y $ne$libresoc.v:201359$14713_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:202177$14771 + cell $ne $ne$libresoc.v:201365$14719 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -422876,123 +418143,123 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:202177$14771_Y + connect \Y $ne$libresoc.v:201365$14719_Y end - attribute \src "libresoc.v:202061.7-202061.20" - process $proc$libresoc.v:202061$14820 + attribute \src "libresoc.v:201249.7-201249.20" + process $proc$libresoc.v:201249$14768 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:202090.7-202090.24" - process $proc$libresoc.v:202090$14821 + attribute \src "libresoc.v:201278.7-201278.24" + process $proc$libresoc.v:201278$14769 assign { } { } assign $1\core_irq_o[0:0] 1'0 sync always sync init update \core_irq_o $1\core_irq_o[0:0] end - attribute \src "libresoc.v:202094.13-202094.25" - process $proc$libresoc.v:202094$14822 + attribute \src "libresoc.v:201282.13-201282.25" + process $proc$libresoc.v:201282$14770 assign { } { } assign $1\cppr[7:0] 8'00000000 sync always sync init update \cppr $1\cppr[7:0] end - attribute \src "libresoc.v:202123.7-202123.17" - process $proc$libresoc.v:202123$14823 + attribute \src "libresoc.v:201311.7-201311.17" + process $proc$libresoc.v:201311$14771 assign { } { } assign $1\irq[0:0] 1'0 sync always sync init update \irq $1\irq[0:0] end - attribute \src "libresoc.v:202131.13-202131.25" - process $proc$libresoc.v:202131$14824 + attribute \src "libresoc.v:201319.13-201319.25" + process $proc$libresoc.v:201319$14772 assign { } { } assign $1\mfrr[7:0] 8'11111111 sync always sync init update \mfrr $1\mfrr[7:0] end - attribute \src "libresoc.v:202145.7-202145.20" - process $proc$libresoc.v:202145$14825 + attribute \src "libresoc.v:201333.7-201333.20" + process $proc$libresoc.v:201333$14773 assign { } { } assign $1\wb_ack[0:0] 1'0 sync always sync init update \wb_ack $1\wb_ack[0:0] end - attribute \src "libresoc.v:202153.14-202153.32" - process $proc$libresoc.v:202153$14826 + attribute \src "libresoc.v:201341.14-201341.32" + process $proc$libresoc.v:201341$14774 assign { } { } assign $1\wb_rd_data[31:0] 0 sync always sync init update \wb_rd_data $1\wb_rd_data[31:0] end - attribute \src "libresoc.v:202163.14-202163.31" - process $proc$libresoc.v:202163$14827 + attribute \src "libresoc.v:201351.14-201351.31" + process $proc$libresoc.v:201351$14775 assign { } { } assign $1\xisr[23:0] 24'000000000000000000000000 sync always sync init update \xisr $1\xisr[23:0] end - attribute \src "libresoc.v:202180.3-202181.37" - process $proc$libresoc.v:202180$14774 + attribute \src "libresoc.v:201368.3-201369.37" + process $proc$libresoc.v:201368$14722 assign { } { } assign $0\core_irq_o[0:0] \core_irq_o$next sync posedge \clk update \core_irq_o $0\core_irq_o[0:0] end - attribute \src "libresoc.v:202182.3-202183.25" - process $proc$libresoc.v:202182$14775 + attribute \src "libresoc.v:201370.3-201371.25" + process $proc$libresoc.v:201370$14723 assign { } { } assign $0\xisr[23:0] \xisr$next sync posedge \clk update \xisr $0\xisr[23:0] end - attribute \src "libresoc.v:202184.3-202185.25" - process $proc$libresoc.v:202184$14776 + attribute \src "libresoc.v:201372.3-201373.25" + process $proc$libresoc.v:201372$14724 assign { } { } assign $0\cppr[7:0] \cppr$next sync posedge \clk update \cppr $0\cppr[7:0] end - attribute \src "libresoc.v:202186.3-202187.25" - process $proc$libresoc.v:202186$14777 + attribute \src "libresoc.v:201374.3-201375.25" + process $proc$libresoc.v:201374$14725 assign { } { } assign $0\mfrr[7:0] \mfrr$next sync posedge \clk update \mfrr $0\mfrr[7:0] end - attribute \src "libresoc.v:202188.3-202189.23" - process $proc$libresoc.v:202188$14778 + attribute \src "libresoc.v:201376.3-201377.23" + process $proc$libresoc.v:201376$14726 assign { } { } assign $0\irq[0:0] \irq$next sync posedge \clk update \irq $0\irq[0:0] end - attribute \src "libresoc.v:202190.3-202191.37" - process $proc$libresoc.v:202190$14779 + attribute \src "libresoc.v:201378.3-201379.37" + process $proc$libresoc.v:201378$14727 assign { } { } assign $0\wb_rd_data[31:0] \wb_rd_data$next sync posedge \clk update \wb_rd_data $0\wb_rd_data[31:0] end - attribute \src "libresoc.v:202192.3-202193.29" - process $proc$libresoc.v:202192$14780 + attribute \src "libresoc.v:201380.3-201381.29" + process $proc$libresoc.v:201380$14728 assign { } { } assign $0\wb_ack[0:0] \wb_ack$next sync posedge \clk update \wb_ack $0\wb_ack[0:0] end - attribute \src "libresoc.v:202194.3-202209.6" - process $proc$libresoc.v:202194$14781 + attribute \src "libresoc.v:201382.3-201397.6" + process $proc$libresoc.v:201382$14729 assign { } { } assign { } { } assign { } { } @@ -423000,15 +418267,15 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\cppr$next[7:0]$14782 $1\cppr$next[7:0]$14788 - assign $0\irq$next[0:0]$14783 $1\irq$next[0:0]$14789 - assign $0\mfrr$next[7:0]$14784 $1\mfrr$next[7:0]$14790 - assign $0\wb_ack$next[0:0]$14785 $1\wb_ack$next[0:0]$14791 - assign $0\wb_rd_data$next[31:0]$14786 $1\wb_rd_data$next[31:0]$14792 - assign $0\xisr$next[23:0]$14787 $1\xisr$next[23:0]$14793 - attribute \src "libresoc.v:202195.5-202195.29" + assign $0\cppr$next[7:0]$14730 $1\cppr$next[7:0]$14736 + assign $0\irq$next[0:0]$14731 $1\irq$next[0:0]$14737 + assign $0\mfrr$next[7:0]$14732 $1\mfrr$next[7:0]$14738 + assign $0\wb_ack$next[0:0]$14733 $1\wb_ack$next[0:0]$14739 + assign $0\wb_rd_data$next[31:0]$14734 $1\wb_rd_data$next[31:0]$14740 + assign $0\xisr$next[23:0]$14735 $1\xisr$next[23:0]$14741 + attribute \src "libresoc.v:201383.5-201383.29" switch \initial - attribute \src "libresoc.v:202195.9-202195.17" + attribute \src "libresoc.v:201383.9-201383.17" case 1'1 case end @@ -423022,36 +418289,36 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\xisr$next[23:0]$14793 24'000000000000000000000000 - assign $1\cppr$next[7:0]$14788 8'00000000 - assign $1\mfrr$next[7:0]$14790 8'11111111 - assign $1\irq$next[0:0]$14789 1'0 - assign $1\wb_rd_data$next[31:0]$14792 0 - assign $1\wb_ack$next[0:0]$14791 1'0 + assign $1\xisr$next[23:0]$14741 24'000000000000000000000000 + assign $1\cppr$next[7:0]$14736 8'00000000 + assign $1\mfrr$next[7:0]$14738 8'11111111 + assign $1\irq$next[0:0]$14737 1'0 + assign $1\wb_rd_data$next[31:0]$14740 0 + assign $1\wb_ack$next[0:0]$14739 1'0 case - assign $1\cppr$next[7:0]$14788 \cppr$2 - assign $1\irq$next[0:0]$14789 \irq$4 - assign $1\mfrr$next[7:0]$14790 \mfrr$3 - assign $1\wb_ack$next[0:0]$14791 \wb_ack$6 - assign $1\wb_rd_data$next[31:0]$14792 \wb_rd_data$5 - assign $1\xisr$next[23:0]$14793 \xisr$1 + assign $1\cppr$next[7:0]$14736 \cppr$2 + assign $1\irq$next[0:0]$14737 \irq$4 + assign $1\mfrr$next[7:0]$14738 \mfrr$3 + assign $1\wb_ack$next[0:0]$14739 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$14740 \wb_rd_data$5 + assign $1\xisr$next[23:0]$14741 \xisr$1 end sync always - update \cppr$next $0\cppr$next[7:0]$14782 - update \irq$next $0\irq$next[0:0]$14783 - update \mfrr$next $0\mfrr$next[7:0]$14784 - update \wb_ack$next $0\wb_ack$next[0:0]$14785 - update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14786 - update \xisr$next $0\xisr$next[23:0]$14787 + update \cppr$next $0\cppr$next[7:0]$14730 + update \irq$next $0\irq$next[0:0]$14731 + update \mfrr$next $0\mfrr$next[7:0]$14732 + update \wb_ack$next $0\wb_ack$next[0:0]$14733 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14734 + update \xisr$next $0\xisr$next[23:0]$14735 end - attribute \src "libresoc.v:202210.3-202237.6" - process $proc$libresoc.v:202210$14794 + attribute \src "libresoc.v:201398.3-201425.6" + process $proc$libresoc.v:201398$14742 assign { } { } assign { } { } assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:202211.5-202211.29" + attribute \src "libresoc.v:201399.5-201399.29" switch \initial - attribute \src "libresoc.v:202211.9-202211.17" + attribute \src "libresoc.v:201399.9-201399.17" case 1'1 case end @@ -423095,14 +418362,14 @@ module \xics_icp sync always update \xirr_accept_rd $0\xirr_accept_rd[0:0] end - attribute \src "libresoc.v:202238.3-202266.6" - process $proc$libresoc.v:202238$14795 + attribute \src "libresoc.v:201426.3-201454.6" + process $proc$libresoc.v:201426$14743 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:202239.5-202239.29" + attribute \src "libresoc.v:201427.5-201427.29" switch \initial - attribute \src "libresoc.v:202239.9-202239.17" + attribute \src "libresoc.v:201427.9-201427.17" case 1'1 case end @@ -423145,14 +418412,14 @@ module \xics_icp sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:202267.3-202276.6" - process $proc$libresoc.v:202267$14796 + attribute \src "libresoc.v:201455.3-201464.6" + process $proc$libresoc.v:201455$14744 assign { } { } assign { } { } assign $0\pending_priority[7:0] $1\pending_priority[7:0] - attribute \src "libresoc.v:202268.5-202268.29" + attribute \src "libresoc.v:201456.5-201456.29" switch \initial - attribute \src "libresoc.v:202268.9-202268.17" + attribute \src "libresoc.v:201456.9-201456.17" case 1'1 case end @@ -423168,13 +418435,13 @@ module \xics_icp sync always update \pending_priority $0\pending_priority[7:0] end - attribute \src "libresoc.v:202277.3-202288.6" - process $proc$libresoc.v:202277$14797 + attribute \src "libresoc.v:201465.3-201476.6" + process $proc$libresoc.v:201465$14745 assign { } { } assign $0\min_pri[7:0] $1\min_pri[7:0] - attribute \src "libresoc.v:202278.5-202278.29" + attribute \src "libresoc.v:201466.5-201466.29" switch \initial - attribute \src "libresoc.v:202278.9-202278.17" + attribute \src "libresoc.v:201466.9-201466.17" case 1'1 case end @@ -423192,14 +418459,14 @@ module \xics_icp sync always update \min_pri $0\min_pri[7:0] end - attribute \src "libresoc.v:202289.3-202297.6" - process $proc$libresoc.v:202289$14798 + attribute \src "libresoc.v:201477.3-201485.6" + process $proc$libresoc.v:201477$14746 assign { } { } assign { } { } - assign $0\core_irq_o$next[0:0]$14799 $1\core_irq_o$next[0:0]$14800 - attribute \src "libresoc.v:202290.5-202290.29" + assign $0\core_irq_o$next[0:0]$14747 $1\core_irq_o$next[0:0]$14748 + attribute \src "libresoc.v:201478.5-201478.29" switch \initial - attribute \src "libresoc.v:202290.9-202290.17" + attribute \src "libresoc.v:201478.9-201478.17" case 1'1 case end @@ -423208,21 +418475,21 @@ module \xics_icp attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_irq_o$next[0:0]$14800 1'0 + assign $1\core_irq_o$next[0:0]$14748 1'0 case - assign $1\core_irq_o$next[0:0]$14800 \irq + assign $1\core_irq_o$next[0:0]$14748 \irq end sync always - update \core_irq_o$next $0\core_irq_o$next[0:0]$14799 + update \core_irq_o$next $0\core_irq_o$next[0:0]$14747 end - attribute \src "libresoc.v:202298.3-202307.6" - process $proc$libresoc.v:202298$14801 + attribute \src "libresoc.v:201486.3-201495.6" + process $proc$libresoc.v:201486$14749 assign { } { } assign { } { } assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:202299.5-202299.29" + attribute \src "libresoc.v:201487.5-201487.29" switch \initial - attribute \src "libresoc.v:202299.9-202299.17" + attribute \src "libresoc.v:201487.9-201487.17" case 1'1 case end @@ -423238,8 +418505,8 @@ module \xics_icp sync always update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] end - attribute \src "libresoc.v:202308.3-202370.6" - process $proc$libresoc.v:202308$14802 + attribute \src "libresoc.v:201496.3-201558.6" + process $proc$libresoc.v:201496$14750 assign { } { } assign { } { } assign { } { } @@ -423249,18 +418516,18 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\mfrr$11[7:0]$14805 $1\mfrr$11[7:0]$14810 - assign $0\wb_ack$14[0:0]$14806 $1\wb_ack$14[0:0]$14811 + assign $0\mfrr$11[7:0]$14753 $1\mfrr$11[7:0]$14758 + assign $0\wb_ack$14[0:0]$14754 $1\wb_ack$14[0:0]$14759 assign { } { } assign { } { } assign { } { } - assign $0\xisr$9[23:0]$14808 $2\xisr$9[23:0]$14817 - assign $0\cppr$10[7:0]$14803 $4\cppr$10[7:0]$14818 - assign $0\wb_rd_data$13[31:0]$14807 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } - assign $0\irq$12[0:0]$14804 $1\irq$12[0:0]$14819 - attribute \src "libresoc.v:202309.5-202309.29" + assign $0\xisr$9[23:0]$14756 $2\xisr$9[23:0]$14765 + assign $0\cppr$10[7:0]$14751 $4\cppr$10[7:0]$14766 + assign $0\wb_rd_data$13[31:0]$14755 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$14752 $1\irq$12[0:0]$14767 + attribute \src "libresoc.v:201497.5-201497.29" switch \initial - attribute \src "libresoc.v:202309.9-202309.17" + attribute \src "libresoc.v:201497.9-201497.17" case 1'1 case end @@ -423271,712 +418538,712 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\wb_ack$14[0:0]$14811 1'1 - assign $1\cppr$10[7:0]$14809 $2\cppr$10[7:0]$14812 - assign $1\mfrr$11[7:0]$14810 $2\mfrr$11[7:0]$14813 + assign $1\wb_ack$14[0:0]$14759 1'1 + assign $1\cppr$10[7:0]$14757 $2\cppr$10[7:0]$14760 + assign $1\mfrr$11[7:0]$14758 $2\mfrr$11[7:0]$14761 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign $2\cppr$10[7:0]$14812 $3\cppr$10[7:0]$14814 - assign $2\mfrr$11[7:0]$14813 $3\mfrr$11[7:0]$14815 + assign $2\cppr$10[7:0]$14760 $3\cppr$10[7:0]$14762 + assign $2\mfrr$11[7:0]$14761 $3\mfrr$11[7:0]$14763 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" switch \icp_wb__adr [5:0] attribute \src "libresoc.v:0.0-0.0" case 6'000000 assign { } { } - assign $3\mfrr$11[7:0]$14815 \mfrr - assign $3\cppr$10[7:0]$14814 \be_in [31:24] + assign $3\mfrr$11[7:0]$14763 \mfrr + assign $3\cppr$10[7:0]$14762 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } - assign $3\mfrr$11[7:0]$14815 \mfrr - assign $3\cppr$10[7:0]$14814 \be_in [31:24] + assign $3\mfrr$11[7:0]$14763 \mfrr + assign $3\cppr$10[7:0]$14762 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000011 - assign $3\cppr$10[7:0]$14814 \cppr + assign $3\cppr$10[7:0]$14762 \cppr assign { } { } - assign $3\mfrr$11[7:0]$14815 \be_in [31:24] + assign $3\mfrr$11[7:0]$14763 \be_in [31:24] case - assign $3\cppr$10[7:0]$14814 \cppr - assign $3\mfrr$11[7:0]$14815 \mfrr + assign $3\cppr$10[7:0]$14762 \cppr + assign $3\mfrr$11[7:0]$14763 \mfrr end case - assign $2\cppr$10[7:0]$14812 \cppr - assign $2\mfrr$11[7:0]$14813 \mfrr + assign $2\cppr$10[7:0]$14760 \cppr + assign $2\mfrr$11[7:0]$14761 \mfrr end case - assign $1\cppr$10[7:0]$14809 \cppr - assign $1\mfrr$11[7:0]$14810 \mfrr - assign $1\wb_ack$14[0:0]$14811 1'0 + assign $1\cppr$10[7:0]$14757 \cppr + assign $1\mfrr$11[7:0]$14758 \mfrr + assign $1\wb_ack$14[0:0]$14759 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xisr$9[23:0]$14816 { 20'00000000000000000001 \ics_i_src } + assign $1\xisr$9[23:0]$14764 { 20'00000000000000000001 \ics_i_src } case - assign $1\xisr$9[23:0]$14816 24'000000000000000000000000 + assign $1\xisr$9[23:0]$14764 24'000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xisr$9[23:0]$14817 24'000000000000000000000010 + assign $2\xisr$9[23:0]$14765 24'000000000000000000000010 case - assign $2\xisr$9[23:0]$14817 $1\xisr$9[23:0]$14816 + assign $2\xisr$9[23:0]$14765 $1\xisr$9[23:0]$14764 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" switch \xirr_accept_rd attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cppr$10[7:0]$14818 \min_pri + assign $4\cppr$10[7:0]$14766 \min_pri case - assign $4\cppr$10[7:0]$14818 $1\cppr$10[7:0]$14809 + assign $4\cppr$10[7:0]$14766 $1\cppr$10[7:0]$14757 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" switch { \irq \$21 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\irq$12[0:0]$14819 1'1 + assign $1\irq$12[0:0]$14767 1'1 case - assign $1\irq$12[0:0]$14819 1'0 + assign $1\irq$12[0:0]$14767 1'0 end sync always - update \cppr$10 $0\cppr$10[7:0]$14803 - update \irq$12 $0\irq$12[0:0]$14804 - update \mfrr$11 $0\mfrr$11[7:0]$14805 - update \wb_ack$14 $0\wb_ack$14[0:0]$14806 - update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14807 - update \xisr$9 $0\xisr$9[23:0]$14808 + update \cppr$10 $0\cppr$10[7:0]$14751 + update \irq$12 $0\irq$12[0:0]$14752 + update \mfrr$11 $0\mfrr$11[7:0]$14753 + update \wb_ack$14 $0\wb_ack$14[0:0]$14754 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14755 + update \xisr$9 $0\xisr$9[23:0]$14756 end - connect \$15 $and$libresoc.v:202170$14764_Y - connect \$17 $ne$libresoc.v:202171$14765_Y - connect \$19 $lt$libresoc.v:202172$14766_Y - connect \$21 $lt$libresoc.v:202173$14767_Y - connect \$23 $and$libresoc.v:202174$14768_Y - connect \$25 $eq$libresoc.v:202175$14769_Y - connect \$27 $and$libresoc.v:202176$14770_Y - connect \$29 $ne$libresoc.v:202177$14771_Y - connect \$31 $lt$libresoc.v:202178$14772_Y - connect \$7 $and$libresoc.v:202179$14773_Y + connect \$15 $and$libresoc.v:201358$14712_Y + connect \$17 $ne$libresoc.v:201359$14713_Y + connect \$19 $lt$libresoc.v:201360$14714_Y + connect \$21 $lt$libresoc.v:201361$14715_Y + connect \$23 $and$libresoc.v:201362$14716_Y + connect \$25 $eq$libresoc.v:201363$14717_Y + connect \$27 $and$libresoc.v:201364$14718_Y + connect \$29 $ne$libresoc.v:201365$14719_Y + connect \$31 $lt$libresoc.v:201366$14720_Y + connect \$7 $and$libresoc.v:201367$14721_Y connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } connect \icp_wb__ack \$7 end -attribute \src "libresoc.v:202378.1-203427.10" +attribute \src "libresoc.v:201566.1-202615.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" attribute \generator "nMigen" module \xics_ics - attribute \src "libresoc.v:203308.3-203357.6" + attribute \src "libresoc.v:202496.3-202545.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:203019.3-203028.6" + attribute \src "libresoc.v:202207.3-202216.6" wire width 4 $0\cur_idx0[3:0] - attribute \src "libresoc.v:203228.3-203237.6" + attribute \src "libresoc.v:202416.3-202425.6" wire width 4 $0\cur_idx10[3:0] - attribute \src "libresoc.v:203248.3-203257.6" + attribute \src "libresoc.v:202436.3-202445.6" wire width 4 $0\cur_idx11[3:0] - attribute \src "libresoc.v:203268.3-203277.6" + attribute \src "libresoc.v:202456.3-202465.6" wire width 4 $0\cur_idx12[3:0] - attribute \src "libresoc.v:203288.3-203297.6" + attribute \src "libresoc.v:202476.3-202485.6" wire width 4 $0\cur_idx13[3:0] - attribute \src "libresoc.v:203358.3-203367.6" + attribute \src "libresoc.v:202546.3-202555.6" wire width 4 $0\cur_idx14[3:0] - attribute \src "libresoc.v:203378.3-203387.6" + attribute \src "libresoc.v:202566.3-202575.6" wire width 4 $0\cur_idx15[3:0] - attribute \src "libresoc.v:203039.3-203048.6" + attribute \src "libresoc.v:202227.3-202236.6" wire width 4 $0\cur_idx1[3:0] - attribute \src "libresoc.v:203059.3-203068.6" + attribute \src "libresoc.v:202247.3-202256.6" wire width 4 $0\cur_idx2[3:0] - attribute \src "libresoc.v:203079.3-203088.6" + attribute \src "libresoc.v:202267.3-202276.6" wire width 4 $0\cur_idx3[3:0] - attribute \src "libresoc.v:203108.3-203117.6" + attribute \src "libresoc.v:202296.3-202305.6" wire width 4 $0\cur_idx4[3:0] - attribute \src "libresoc.v:203128.3-203137.6" + attribute \src "libresoc.v:202316.3-202325.6" wire width 4 $0\cur_idx5[3:0] - attribute \src "libresoc.v:203148.3-203157.6" + attribute \src "libresoc.v:202336.3-202345.6" wire width 4 $0\cur_idx6[3:0] - attribute \src "libresoc.v:203168.3-203177.6" + attribute \src "libresoc.v:202356.3-202365.6" wire width 4 $0\cur_idx7[3:0] - attribute \src "libresoc.v:203188.3-203197.6" + attribute \src "libresoc.v:202376.3-202385.6" wire width 4 $0\cur_idx8[3:0] - attribute \src "libresoc.v:203208.3-203217.6" + attribute \src "libresoc.v:202396.3-202405.6" wire width 4 $0\cur_idx9[3:0] - attribute \src "libresoc.v:203009.3-203018.6" + attribute \src "libresoc.v:202197.3-202206.6" wire width 8 $0\cur_pri0[7:0] - attribute \src "libresoc.v:203218.3-203227.6" + attribute \src "libresoc.v:202406.3-202415.6" wire width 8 $0\cur_pri10[7:0] - attribute \src "libresoc.v:203238.3-203247.6" + attribute \src "libresoc.v:202426.3-202435.6" wire width 8 $0\cur_pri11[7:0] - attribute \src "libresoc.v:203258.3-203267.6" + attribute \src "libresoc.v:202446.3-202455.6" wire width 8 $0\cur_pri12[7:0] - attribute \src "libresoc.v:203278.3-203287.6" + attribute \src "libresoc.v:202466.3-202475.6" wire width 8 $0\cur_pri13[7:0] - attribute \src "libresoc.v:203298.3-203307.6" + attribute \src "libresoc.v:202486.3-202495.6" wire width 8 $0\cur_pri14[7:0] - attribute \src "libresoc.v:203368.3-203377.6" + attribute \src "libresoc.v:202556.3-202565.6" wire width 8 $0\cur_pri15[7:0] - attribute \src "libresoc.v:203029.3-203038.6" + attribute \src "libresoc.v:202217.3-202226.6" wire width 8 $0\cur_pri1[7:0] - attribute \src "libresoc.v:203049.3-203058.6" + attribute \src "libresoc.v:202237.3-202246.6" wire width 8 $0\cur_pri2[7:0] - attribute \src "libresoc.v:203069.3-203078.6" + attribute \src "libresoc.v:202257.3-202266.6" wire width 8 $0\cur_pri3[7:0] - attribute \src "libresoc.v:203089.3-203098.6" + attribute \src "libresoc.v:202277.3-202286.6" wire width 8 $0\cur_pri4[7:0] - attribute \src "libresoc.v:203118.3-203127.6" + attribute \src "libresoc.v:202306.3-202315.6" wire width 8 $0\cur_pri5[7:0] - attribute \src "libresoc.v:203138.3-203147.6" + attribute \src "libresoc.v:202326.3-202335.6" wire width 8 $0\cur_pri6[7:0] - attribute \src "libresoc.v:203158.3-203167.6" + attribute \src "libresoc.v:202346.3-202355.6" wire width 8 $0\cur_pri7[7:0] - attribute \src "libresoc.v:203178.3-203187.6" + attribute \src "libresoc.v:202366.3-202375.6" wire width 8 $0\cur_pri8[7:0] - attribute \src "libresoc.v:203198.3-203207.6" + attribute \src "libresoc.v:202386.3-202395.6" wire width 8 $0\cur_pri9[7:0] - attribute \src "libresoc.v:203388.3-203397.6" + attribute \src "libresoc.v:202576.3-202585.6" wire $0\ibit[0:0] - attribute \src "libresoc.v:202883.3-202884.25" + attribute \src "libresoc.v:202071.3-202072.25" wire width 8 $0\icp_o_pri[7:0] - attribute \src "libresoc.v:202881.3-202882.28" + attribute \src "libresoc.v:202069.3-202070.28" wire width 4 $0\icp_o_src[3:0] - attribute \src "libresoc.v:203407.3-203415.6" - wire $0\ics_wb__ack$next[0:0]$15074 - attribute \src "libresoc.v:202917.3-202918.39" + attribute \src "libresoc.v:202595.3-202603.6" + wire $0\ics_wb__ack$next[0:0]$15022 + attribute \src "libresoc.v:202105.3-202106.39" wire $0\ics_wb__ack[0:0] - attribute \src "libresoc.v:203398.3-203406.6" - wire width 32 $0\ics_wb__dat_r$next[31:0]$15071 - attribute \src "libresoc.v:202919.3-202920.43" + attribute \src "libresoc.v:202586.3-202594.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$15019 + attribute \src "libresoc.v:202107.3-202108.43" wire width 32 $0\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:202379.7-202379.20" + attribute \src "libresoc.v:201567.7-201567.20" wire $0\initial[0:0] - attribute \src "libresoc.v:203099.3-203107.6" - wire width 16 $0\int_level_l$next[15:0]$15043 - attribute \src "libresoc.v:202921.3-202922.39" + attribute \src "libresoc.v:202287.3-202295.6" + wire width 16 $0\int_level_l$next[15:0]$14991 + attribute \src "libresoc.v:202109.3-202110.39" wire width 16 $0\int_level_l[15:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive0_pri$next[7:0]$14953 - attribute \src "libresoc.v:202885.3-202886.35" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $0\xive0_pri$next[7:0]$14901 + attribute \src "libresoc.v:202073.3-202074.35" wire width 8 $0\xive0_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive10_pri$next[7:0]$14954 - attribute \src "libresoc.v:202905.3-202906.37" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $0\xive10_pri$next[7:0]$14902 + attribute \src "libresoc.v:202093.3-202094.37" wire width 8 $0\xive10_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive11_pri$next[7:0]$14955 - attribute \src "libresoc.v:202907.3-202908.37" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $0\xive11_pri$next[7:0]$14903 + attribute \src "libresoc.v:202095.3-202096.37" wire width 8 $0\xive11_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive12_pri$next[7:0]$14956 - attribute \src "libresoc.v:202909.3-202910.37" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $0\xive12_pri$next[7:0]$14904 + attribute \src "libresoc.v:202097.3-202098.37" wire width 8 $0\xive12_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive13_pri$next[7:0]$14957 - attribute \src "libresoc.v:202911.3-202912.37" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $0\xive13_pri$next[7:0]$14905 + attribute \src "libresoc.v:202099.3-202100.37" wire width 8 $0\xive13_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive14_pri$next[7:0]$14958 - attribute \src "libresoc.v:202913.3-202914.37" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $0\xive14_pri$next[7:0]$14906 + attribute \src "libresoc.v:202101.3-202102.37" wire width 8 $0\xive14_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive15_pri$next[7:0]$14959 - attribute \src "libresoc.v:202915.3-202916.37" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $0\xive15_pri$next[7:0]$14907 + attribute \src "libresoc.v:202103.3-202104.37" wire width 8 $0\xive15_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive1_pri$next[7:0]$14960 - attribute \src "libresoc.v:202887.3-202888.35" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $0\xive1_pri$next[7:0]$14908 + attribute \src "libresoc.v:202075.3-202076.35" wire width 8 $0\xive1_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive2_pri$next[7:0]$14961 - attribute \src "libresoc.v:202889.3-202890.35" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $0\xive2_pri$next[7:0]$14909 + attribute \src "libresoc.v:202077.3-202078.35" wire width 8 $0\xive2_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive3_pri$next[7:0]$14962 - attribute \src "libresoc.v:202891.3-202892.35" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $0\xive3_pri$next[7:0]$14910 + attribute \src "libresoc.v:202079.3-202080.35" wire width 8 $0\xive3_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive4_pri$next[7:0]$14963 - attribute \src "libresoc.v:202893.3-202894.35" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $0\xive4_pri$next[7:0]$14911 + attribute \src "libresoc.v:202081.3-202082.35" wire width 8 $0\xive4_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive5_pri$next[7:0]$14964 - attribute \src "libresoc.v:202895.3-202896.35" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $0\xive5_pri$next[7:0]$14912 + attribute \src "libresoc.v:202083.3-202084.35" wire width 8 $0\xive5_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive6_pri$next[7:0]$14965 - attribute \src "libresoc.v:202897.3-202898.35" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $0\xive6_pri$next[7:0]$14913 + attribute \src "libresoc.v:202085.3-202086.35" wire width 8 $0\xive6_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive7_pri$next[7:0]$14966 - attribute \src "libresoc.v:202899.3-202900.35" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $0\xive7_pri$next[7:0]$14914 + attribute \src "libresoc.v:202087.3-202088.35" wire width 8 $0\xive7_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive8_pri$next[7:0]$14967 - attribute \src "libresoc.v:202901.3-202902.35" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $0\xive8_pri$next[7:0]$14915 + attribute \src "libresoc.v:202089.3-202090.35" wire width 8 $0\xive8_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $0\xive9_pri$next[7:0]$14968 - attribute \src "libresoc.v:202903.3-202904.35" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $0\xive9_pri$next[7:0]$14916 + attribute \src "libresoc.v:202091.3-202092.35" wire width 8 $0\xive9_pri[7:0] - attribute \src "libresoc.v:203308.3-203357.6" + attribute \src "libresoc.v:202496.3-202545.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:203019.3-203028.6" + attribute \src "libresoc.v:202207.3-202216.6" wire width 4 $1\cur_idx0[3:0] - attribute \src "libresoc.v:203228.3-203237.6" + attribute \src "libresoc.v:202416.3-202425.6" wire width 4 $1\cur_idx10[3:0] - attribute \src "libresoc.v:203248.3-203257.6" + attribute \src "libresoc.v:202436.3-202445.6" wire width 4 $1\cur_idx11[3:0] - attribute \src "libresoc.v:203268.3-203277.6" + attribute \src "libresoc.v:202456.3-202465.6" wire width 4 $1\cur_idx12[3:0] - attribute \src "libresoc.v:203288.3-203297.6" + attribute \src "libresoc.v:202476.3-202485.6" wire width 4 $1\cur_idx13[3:0] - attribute \src "libresoc.v:203358.3-203367.6" + attribute \src "libresoc.v:202546.3-202555.6" wire width 4 $1\cur_idx14[3:0] - attribute \src "libresoc.v:203378.3-203387.6" + attribute \src "libresoc.v:202566.3-202575.6" wire width 4 $1\cur_idx15[3:0] - attribute \src "libresoc.v:203039.3-203048.6" + attribute \src "libresoc.v:202227.3-202236.6" wire width 4 $1\cur_idx1[3:0] - attribute \src "libresoc.v:203059.3-203068.6" + attribute \src "libresoc.v:202247.3-202256.6" wire width 4 $1\cur_idx2[3:0] - attribute \src "libresoc.v:203079.3-203088.6" + attribute \src "libresoc.v:202267.3-202276.6" wire width 4 $1\cur_idx3[3:0] - attribute \src "libresoc.v:203108.3-203117.6" + attribute \src "libresoc.v:202296.3-202305.6" wire width 4 $1\cur_idx4[3:0] - attribute \src "libresoc.v:203128.3-203137.6" + attribute \src "libresoc.v:202316.3-202325.6" wire width 4 $1\cur_idx5[3:0] - attribute \src "libresoc.v:203148.3-203157.6" + attribute \src "libresoc.v:202336.3-202345.6" wire width 4 $1\cur_idx6[3:0] - attribute \src "libresoc.v:203168.3-203177.6" + attribute \src "libresoc.v:202356.3-202365.6" wire width 4 $1\cur_idx7[3:0] - attribute \src "libresoc.v:203188.3-203197.6" + attribute \src "libresoc.v:202376.3-202385.6" wire width 4 $1\cur_idx8[3:0] - attribute \src "libresoc.v:203208.3-203217.6" + attribute \src "libresoc.v:202396.3-202405.6" wire width 4 $1\cur_idx9[3:0] - attribute \src "libresoc.v:203009.3-203018.6" + attribute \src "libresoc.v:202197.3-202206.6" wire width 8 $1\cur_pri0[7:0] - attribute \src "libresoc.v:203218.3-203227.6" + attribute \src "libresoc.v:202406.3-202415.6" wire width 8 $1\cur_pri10[7:0] - attribute \src "libresoc.v:203238.3-203247.6" + attribute \src "libresoc.v:202426.3-202435.6" wire width 8 $1\cur_pri11[7:0] - attribute \src "libresoc.v:203258.3-203267.6" + attribute \src "libresoc.v:202446.3-202455.6" wire width 8 $1\cur_pri12[7:0] - attribute \src "libresoc.v:203278.3-203287.6" + attribute \src "libresoc.v:202466.3-202475.6" wire width 8 $1\cur_pri13[7:0] - attribute \src "libresoc.v:203298.3-203307.6" + attribute \src "libresoc.v:202486.3-202495.6" wire width 8 $1\cur_pri14[7:0] - attribute \src "libresoc.v:203368.3-203377.6" + attribute \src "libresoc.v:202556.3-202565.6" wire width 8 $1\cur_pri15[7:0] - attribute \src "libresoc.v:203029.3-203038.6" + attribute \src "libresoc.v:202217.3-202226.6" wire width 8 $1\cur_pri1[7:0] - attribute \src "libresoc.v:203049.3-203058.6" + attribute \src "libresoc.v:202237.3-202246.6" wire width 8 $1\cur_pri2[7:0] - attribute \src "libresoc.v:203069.3-203078.6" + attribute \src "libresoc.v:202257.3-202266.6" wire width 8 $1\cur_pri3[7:0] - attribute \src "libresoc.v:203089.3-203098.6" + attribute \src "libresoc.v:202277.3-202286.6" wire width 8 $1\cur_pri4[7:0] - attribute \src "libresoc.v:203118.3-203127.6" + attribute \src "libresoc.v:202306.3-202315.6" wire width 8 $1\cur_pri5[7:0] - attribute \src "libresoc.v:203138.3-203147.6" + attribute \src "libresoc.v:202326.3-202335.6" wire width 8 $1\cur_pri6[7:0] - attribute \src "libresoc.v:203158.3-203167.6" + attribute \src "libresoc.v:202346.3-202355.6" wire width 8 $1\cur_pri7[7:0] - attribute \src "libresoc.v:203178.3-203187.6" + attribute \src "libresoc.v:202366.3-202375.6" wire width 8 $1\cur_pri8[7:0] - attribute \src "libresoc.v:203198.3-203207.6" + attribute \src "libresoc.v:202386.3-202395.6" wire width 8 $1\cur_pri9[7:0] - attribute \src "libresoc.v:203388.3-203397.6" + attribute \src "libresoc.v:202576.3-202585.6" wire $1\ibit[0:0] - attribute \src "libresoc.v:202660.13-202660.30" + attribute \src "libresoc.v:201848.13-201848.30" wire width 8 $1\icp_o_pri[7:0] - attribute \src "libresoc.v:202665.13-202665.29" + attribute \src "libresoc.v:201853.13-201853.29" wire width 4 $1\icp_o_src[3:0] - attribute \src "libresoc.v:203407.3-203415.6" - wire $1\ics_wb__ack$next[0:0]$15075 - attribute \src "libresoc.v:202674.7-202674.25" + attribute \src "libresoc.v:202595.3-202603.6" + wire $1\ics_wb__ack$next[0:0]$15023 + attribute \src "libresoc.v:201862.7-201862.25" wire $1\ics_wb__ack[0:0] - attribute \src "libresoc.v:203398.3-203406.6" - wire width 32 $1\ics_wb__dat_r$next[31:0]$15072 - attribute \src "libresoc.v:202683.14-202683.35" + attribute \src "libresoc.v:202586.3-202594.6" + wire width 32 $1\ics_wb__dat_r$next[31:0]$15020 + attribute \src "libresoc.v:201871.14-201871.35" wire width 32 $1\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:203099.3-203107.6" - wire width 16 $1\int_level_l$next[15:0]$15044 - attribute \src "libresoc.v:202695.14-202695.36" + attribute \src "libresoc.v:202287.3-202295.6" + wire width 16 $1\int_level_l$next[15:0]$14992 + attribute \src "libresoc.v:201883.14-201883.36" wire width 16 $1\int_level_l[15:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive0_pri$next[7:0]$14969 - attribute \src "libresoc.v:202715.13-202715.30" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $1\xive0_pri$next[7:0]$14917 + attribute \src "libresoc.v:201903.13-201903.30" wire width 8 $1\xive0_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive10_pri$next[7:0]$14970 - attribute \src "libresoc.v:202719.13-202719.31" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $1\xive10_pri$next[7:0]$14918 + attribute \src "libresoc.v:201907.13-201907.31" wire width 8 $1\xive10_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive11_pri$next[7:0]$14971 - attribute \src "libresoc.v:202723.13-202723.31" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $1\xive11_pri$next[7:0]$14919 + attribute \src "libresoc.v:201911.13-201911.31" wire width 8 $1\xive11_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive12_pri$next[7:0]$14972 - attribute \src "libresoc.v:202727.13-202727.31" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $1\xive12_pri$next[7:0]$14920 + attribute \src "libresoc.v:201915.13-201915.31" wire width 8 $1\xive12_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive13_pri$next[7:0]$14973 - attribute \src "libresoc.v:202731.13-202731.31" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $1\xive13_pri$next[7:0]$14921 + attribute \src "libresoc.v:201919.13-201919.31" wire width 8 $1\xive13_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive14_pri$next[7:0]$14974 - attribute \src "libresoc.v:202735.13-202735.31" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $1\xive14_pri$next[7:0]$14922 + attribute \src "libresoc.v:201923.13-201923.31" wire width 8 $1\xive14_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive15_pri$next[7:0]$14975 - attribute \src "libresoc.v:202739.13-202739.31" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $1\xive15_pri$next[7:0]$14923 + attribute \src "libresoc.v:201927.13-201927.31" wire width 8 $1\xive15_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive1_pri$next[7:0]$14976 - attribute \src "libresoc.v:202743.13-202743.30" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $1\xive1_pri$next[7:0]$14924 + attribute \src "libresoc.v:201931.13-201931.30" wire width 8 $1\xive1_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive2_pri$next[7:0]$14977 - attribute \src "libresoc.v:202747.13-202747.30" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $1\xive2_pri$next[7:0]$14925 + attribute \src "libresoc.v:201935.13-201935.30" wire width 8 $1\xive2_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive3_pri$next[7:0]$14978 - attribute \src "libresoc.v:202751.13-202751.30" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $1\xive3_pri$next[7:0]$14926 + attribute \src "libresoc.v:201939.13-201939.30" wire width 8 $1\xive3_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive4_pri$next[7:0]$14979 - attribute \src "libresoc.v:202755.13-202755.30" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $1\xive4_pri$next[7:0]$14927 + attribute \src "libresoc.v:201943.13-201943.30" wire width 8 $1\xive4_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive5_pri$next[7:0]$14980 - attribute \src "libresoc.v:202759.13-202759.30" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $1\xive5_pri$next[7:0]$14928 + attribute \src "libresoc.v:201947.13-201947.30" wire width 8 $1\xive5_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive6_pri$next[7:0]$14981 - attribute \src "libresoc.v:202763.13-202763.30" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $1\xive6_pri$next[7:0]$14929 + attribute \src "libresoc.v:201951.13-201951.30" wire width 8 $1\xive6_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive7_pri$next[7:0]$14982 - attribute \src "libresoc.v:202767.13-202767.30" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $1\xive7_pri$next[7:0]$14930 + attribute \src "libresoc.v:201955.13-201955.30" wire width 8 $1\xive7_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive8_pri$next[7:0]$14983 - attribute \src "libresoc.v:202771.13-202771.30" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $1\xive8_pri$next[7:0]$14931 + attribute \src "libresoc.v:201959.13-201959.30" wire width 8 $1\xive8_pri[7:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $1\xive9_pri$next[7:0]$14984 - attribute \src "libresoc.v:202775.13-202775.30" + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $1\xive9_pri$next[7:0]$14932 + attribute \src "libresoc.v:201963.13-201963.30" wire width 8 $1\xive9_pri[7:0] - attribute \src "libresoc.v:203308.3-203357.6" + attribute \src "libresoc.v:202496.3-202545.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive0_pri$next[7:0]$14985 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive10_pri$next[7:0]$14986 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive11_pri$next[7:0]$14987 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive12_pri$next[7:0]$14988 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive13_pri$next[7:0]$14989 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive14_pri$next[7:0]$14990 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive15_pri$next[7:0]$14991 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive1_pri$next[7:0]$14992 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive2_pri$next[7:0]$14993 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive3_pri$next[7:0]$14994 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive4_pri$next[7:0]$14995 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive5_pri$next[7:0]$14996 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive6_pri$next[7:0]$14997 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive7_pri$next[7:0]$14998 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive8_pri$next[7:0]$14999 - attribute \src "libresoc.v:202923.3-203008.6" - wire width 8 $2\xive9_pri$next[7:0]$15000 - attribute \src "libresoc.v:202923.3-203008.6" - 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$and$libresoc.v:202828$14878_Y - attribute \src "libresoc.v:202830.19-202830.115" - wire $and$libresoc.v:202830$14880_Y - attribute \src "libresoc.v:202832.19-202832.115" - wire $and$libresoc.v:202832$14882_Y - attribute \src "libresoc.v:202835.19-202835.115" - wire $and$libresoc.v:202835$14885_Y - attribute \src "libresoc.v:202859.17-202859.115" - wire $and$libresoc.v:202859$14909_Y - attribute \src "libresoc.v:202867.18-202867.112" - wire $and$libresoc.v:202867$14917_Y - attribute \src "libresoc.v:202869.18-202869.112" - wire $and$libresoc.v:202869$14919_Y - attribute \src "libresoc.v:202871.18-202871.112" - wire $and$libresoc.v:202871$14921_Y - attribute \src "libresoc.v:202873.18-202873.112" - wire $and$libresoc.v:202873$14923_Y - attribute \src "libresoc.v:202876.18-202876.112" - wire $and$libresoc.v:202876$14926_Y - attribute \src "libresoc.v:202878.18-202878.112" - wire $and$libresoc.v:202878$14928_Y - attribute \src "libresoc.v:202880.18-202880.112" - wire $and$libresoc.v:202880$14930_Y - attribute \src "libresoc.v:202794.18-202794.109" - wire $eq$libresoc.v:202794$14844_Y - attribute \src "libresoc.v:202816.18-202816.109" - wire $eq$libresoc.v:202816$14866_Y - attribute \src "libresoc.v:202833.17-202833.114" - wire $eq$libresoc.v:202833$14883_Y - attribute \src "libresoc.v:202836.19-202836.110" - wire $eq$libresoc.v:202836$14886_Y - attribute \src "libresoc.v:202838.18-202838.109" - wire $eq$libresoc.v:202838$14888_Y - attribute \src "libresoc.v:202840.18-202840.109" - wire $eq$libresoc.v:202840$14890_Y - attribute \src "libresoc.v:202842.18-202842.109" - wire $eq$libresoc.v:202842$14892_Y - attribute \src "libresoc.v:202844.18-202844.109" - wire $eq$libresoc.v:202844$14894_Y - attribute \src "libresoc.v:202846.18-202846.109" - wire $eq$libresoc.v:202846$14896_Y - attribute \src "libresoc.v:202848.17-202848.114" - wire $eq$libresoc.v:202848$14898_Y - attribute \src "libresoc.v:202849.18-202849.109" - wire $eq$libresoc.v:202849$14899_Y - attribute \src "libresoc.v:202851.18-202851.109" - wire $eq$libresoc.v:202851$14901_Y - attribute \src "libresoc.v:202853.18-202853.110" - wire $eq$libresoc.v:202853$14903_Y - attribute \src "libresoc.v:202855.18-202855.110" - wire $eq$libresoc.v:202855$14905_Y - attribute \src "libresoc.v:202857.18-202857.110" - wire $eq$libresoc.v:202857$14907_Y - attribute \src "libresoc.v:202860.18-202860.110" - wire $eq$libresoc.v:202860$14910_Y - attribute \src "libresoc.v:202862.18-202862.110" - wire $eq$libresoc.v:202862$14912_Y - attribute \src "libresoc.v:202864.18-202864.110" - wire $eq$libresoc.v:202864$14914_Y - attribute \src "libresoc.v:202875.17-202875.108" - wire $eq$libresoc.v:202875$14925_Y - attribute \src "libresoc.v:202779.18-202779.111" - wire $lt$libresoc.v:202779$14829_Y - attribute \src "libresoc.v:202781.19-202781.112" - wire $lt$libresoc.v:202781$14831_Y - attribute \src "libresoc.v:202783.19-202783.112" - wire $lt$libresoc.v:202783$14833_Y - attribute \src "libresoc.v:202785.19-202785.112" - wire $lt$libresoc.v:202785$14835_Y - attribute \src "libresoc.v:202787.19-202787.112" - wire $lt$libresoc.v:202787$14837_Y - attribute \src "libresoc.v:202789.19-202789.112" - wire $lt$libresoc.v:202789$14839_Y - attribute \src "libresoc.v:202791.19-202791.112" - wire $lt$libresoc.v:202791$14841_Y - attribute \src "libresoc.v:202793.19-202793.112" - wire $lt$libresoc.v:202793$14843_Y - attribute \src "libresoc.v:202796.19-202796.112" - wire $lt$libresoc.v:202796$14846_Y - attribute \src "libresoc.v:202798.19-202798.112" - wire $lt$libresoc.v:202798$14848_Y - attribute \src "libresoc.v:202801.19-202801.112" - wire $lt$libresoc.v:202801$14851_Y - attribute \src "libresoc.v:202803.19-202803.112" - wire $lt$libresoc.v:202803$14853_Y - attribute \src "libresoc.v:202805.19-202805.112" - wire $lt$libresoc.v:202805$14855_Y - attribute \src "libresoc.v:202807.19-202807.112" - wire $lt$libresoc.v:202807$14857_Y - attribute \src "libresoc.v:202809.19-202809.113" - wire $lt$libresoc.v:202809$14859_Y - attribute \src "libresoc.v:202811.19-202811.113" - wire $lt$libresoc.v:202811$14861_Y - attribute \src "libresoc.v:202813.19-202813.114" - wire $lt$libresoc.v:202813$14863_Y - attribute \src "libresoc.v:202815.19-202815.114" - wire $lt$libresoc.v:202815$14865_Y - attribute \src "libresoc.v:202818.19-202818.114" - wire $lt$libresoc.v:202818$14868_Y - attribute \src "libresoc.v:202820.19-202820.114" - wire $lt$libresoc.v:202820$14870_Y - attribute \src "libresoc.v:202823.19-202823.114" - wire $lt$libresoc.v:202823$14873_Y - attribute \src "libresoc.v:202825.19-202825.114" - wire $lt$libresoc.v:202825$14875_Y - attribute \src "libresoc.v:202827.19-202827.114" - wire $lt$libresoc.v:202827$14877_Y - attribute \src "libresoc.v:202829.19-202829.114" - wire $lt$libresoc.v:202829$14879_Y - attribute \src "libresoc.v:202831.19-202831.114" - wire $lt$libresoc.v:202831$14881_Y - attribute \src "libresoc.v:202834.19-202834.114" - wire $lt$libresoc.v:202834$14884_Y - attribute \src "libresoc.v:202868.18-202868.110" - wire $lt$libresoc.v:202868$14918_Y - attribute \src "libresoc.v:202870.18-202870.110" - wire $lt$libresoc.v:202870$14920_Y - attribute \src "libresoc.v:202872.18-202872.111" - wire $lt$libresoc.v:202872$14922_Y - attribute \src "libresoc.v:202874.18-202874.111" - wire $lt$libresoc.v:202874$14924_Y - attribute \src "libresoc.v:202877.18-202877.111" - wire $lt$libresoc.v:202877$14927_Y - attribute \src "libresoc.v:202879.18-202879.111" - wire $lt$libresoc.v:202879$14929_Y - attribute \src "libresoc.v:202866.18-202866.40" - wire width 16 $shr$libresoc.v:202866$14916_Y - attribute \src "libresoc.v:202778.17-202778.114" - wire width 8 $ternary$libresoc.v:202778$14828_Y - attribute \src "libresoc.v:202800.18-202800.116" - wire width 8 $ternary$libresoc.v:202800$14850_Y - attribute \src "libresoc.v:202822.18-202822.116" - wire width 8 $ternary$libresoc.v:202822$14872_Y - attribute \src "libresoc.v:202837.19-202837.118" - wire width 8 $ternary$libresoc.v:202837$14887_Y - attribute \src "libresoc.v:202839.18-202839.116" - wire width 8 $ternary$libresoc.v:202839$14889_Y - attribute \src "libresoc.v:202841.18-202841.116" - wire width 8 $ternary$libresoc.v:202841$14891_Y - attribute \src "libresoc.v:202843.18-202843.116" - wire width 8 $ternary$libresoc.v:202843$14893_Y - attribute \src "libresoc.v:202845.18-202845.116" - wire width 8 $ternary$libresoc.v:202845$14895_Y - attribute \src "libresoc.v:202847.18-202847.116" - wire width 8 $ternary$libresoc.v:202847$14897_Y - attribute \src "libresoc.v:202850.18-202850.116" - wire width 8 $ternary$libresoc.v:202850$14900_Y - attribute \src "libresoc.v:202852.18-202852.116" - wire width 8 $ternary$libresoc.v:202852$14902_Y - attribute \src "libresoc.v:202854.18-202854.117" - wire width 8 $ternary$libresoc.v:202854$14904_Y - attribute \src "libresoc.v:202856.18-202856.117" - wire width 8 $ternary$libresoc.v:202856$14906_Y - attribute \src "libresoc.v:202858.18-202858.117" - wire width 8 $ternary$libresoc.v:202858$14908_Y - attribute \src "libresoc.v:202861.18-202861.117" - wire width 8 $ternary$libresoc.v:202861$14911_Y - attribute \src "libresoc.v:202863.18-202863.117" - wire width 8 $ternary$libresoc.v:202863$14913_Y - attribute \src "libresoc.v:202865.18-202865.117" - wire width 8 $ternary$libresoc.v:202865$14915_Y + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $2\xive0_pri$next[7:0]$14933 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $2\xive10_pri$next[7:0]$14934 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $2\xive11_pri$next[7:0]$14935 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $2\xive12_pri$next[7:0]$14936 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $2\xive13_pri$next[7:0]$14937 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $2\xive14_pri$next[7:0]$14938 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $2\xive15_pri$next[7:0]$14939 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $2\xive1_pri$next[7:0]$14940 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $2\xive2_pri$next[7:0]$14941 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $2\xive3_pri$next[7:0]$14942 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $2\xive4_pri$next[7:0]$14943 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $2\xive5_pri$next[7:0]$14944 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $2\xive6_pri$next[7:0]$14945 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $2\xive7_pri$next[7:0]$14946 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $2\xive8_pri$next[7:0]$14947 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $2\xive9_pri$next[7:0]$14948 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $3\xive0_pri$next[7:0]$14949 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $3\xive10_pri$next[7:0]$14950 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $3\xive11_pri$next[7:0]$14951 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $3\xive12_pri$next[7:0]$14952 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $3\xive13_pri$next[7:0]$14953 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $3\xive14_pri$next[7:0]$14954 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $3\xive15_pri$next[7:0]$14955 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $3\xive1_pri$next[7:0]$14956 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $3\xive2_pri$next[7:0]$14957 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $3\xive3_pri$next[7:0]$14958 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $3\xive4_pri$next[7:0]$14959 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $3\xive5_pri$next[7:0]$14960 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $3\xive6_pri$next[7:0]$14961 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $3\xive7_pri$next[7:0]$14962 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $3\xive8_pri$next[7:0]$14963 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $3\xive9_pri$next[7:0]$14964 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $4\xive0_pri$next[7:0]$14965 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $4\xive10_pri$next[7:0]$14966 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $4\xive11_pri$next[7:0]$14967 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $4\xive12_pri$next[7:0]$14968 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $4\xive13_pri$next[7:0]$14969 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $4\xive14_pri$next[7:0]$14970 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $4\xive15_pri$next[7:0]$14971 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $4\xive1_pri$next[7:0]$14972 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $4\xive2_pri$next[7:0]$14973 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $4\xive3_pri$next[7:0]$14974 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $4\xive4_pri$next[7:0]$14975 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $4\xive5_pri$next[7:0]$14976 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $4\xive6_pri$next[7:0]$14977 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $4\xive7_pri$next[7:0]$14978 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $4\xive8_pri$next[7:0]$14979 + attribute \src "libresoc.v:202111.3-202196.6" + wire width 8 $4\xive9_pri$next[7:0]$14980 + attribute \src "libresoc.v:201968.19-201968.113" + wire $and$libresoc.v:201968$14778_Y + attribute \src "libresoc.v:201970.19-201970.114" + wire $and$libresoc.v:201970$14780_Y + attribute \src "libresoc.v:201972.19-201972.114" + wire $and$libresoc.v:201972$14782_Y + attribute \src "libresoc.v:201974.19-201974.114" + wire $and$libresoc.v:201974$14784_Y + attribute \src "libresoc.v:201976.19-201976.114" + wire $and$libresoc.v:201976$14786_Y + attribute \src "libresoc.v:201978.19-201978.114" + wire $and$libresoc.v:201978$14788_Y + attribute \src "libresoc.v:201980.19-201980.114" + wire $and$libresoc.v:201980$14790_Y + attribute \src "libresoc.v:201983.19-201983.114" + wire $and$libresoc.v:201983$14793_Y + attribute \src "libresoc.v:201985.19-201985.114" + wire $and$libresoc.v:201985$14795_Y + attribute \src "libresoc.v:201987.19-201987.114" + wire $and$libresoc.v:201987$14797_Y + attribute \src "libresoc.v:201990.19-201990.114" + wire $and$libresoc.v:201990$14800_Y + attribute \src "libresoc.v:201992.19-201992.114" + wire $and$libresoc.v:201992$14802_Y + attribute \src "libresoc.v:201994.19-201994.114" + wire $and$libresoc.v:201994$14804_Y + attribute \src "libresoc.v:201996.19-201996.114" + wire $and$libresoc.v:201996$14806_Y + attribute \src "libresoc.v:201998.19-201998.115" + wire $and$libresoc.v:201998$14808_Y + attribute \src "libresoc.v:202000.19-202000.115" + wire $and$libresoc.v:202000$14810_Y + attribute \src "libresoc.v:202002.19-202002.115" + wire $and$libresoc.v:202002$14812_Y + attribute \src "libresoc.v:202005.19-202005.115" + wire $and$libresoc.v:202005$14815_Y + attribute \src "libresoc.v:202007.19-202007.115" + wire $and$libresoc.v:202007$14817_Y + attribute \src "libresoc.v:202009.19-202009.115" + wire $and$libresoc.v:202009$14819_Y + attribute \src "libresoc.v:202012.19-202012.115" + wire $and$libresoc.v:202012$14822_Y + attribute \src "libresoc.v:202014.19-202014.115" + wire $and$libresoc.v:202014$14824_Y + attribute \src "libresoc.v:202016.19-202016.115" + wire $and$libresoc.v:202016$14826_Y + attribute \src "libresoc.v:202018.19-202018.115" + wire $and$libresoc.v:202018$14828_Y + attribute \src "libresoc.v:202020.19-202020.115" + wire $and$libresoc.v:202020$14830_Y + attribute \src "libresoc.v:202023.19-202023.115" + wire $and$libresoc.v:202023$14833_Y + attribute \src "libresoc.v:202047.17-202047.115" + wire $and$libresoc.v:202047$14857_Y + attribute \src "libresoc.v:202055.18-202055.112" + wire $and$libresoc.v:202055$14865_Y + attribute \src "libresoc.v:202057.18-202057.112" + wire $and$libresoc.v:202057$14867_Y + attribute \src "libresoc.v:202059.18-202059.112" + wire $and$libresoc.v:202059$14869_Y + attribute \src "libresoc.v:202061.18-202061.112" + wire $and$libresoc.v:202061$14871_Y + attribute \src "libresoc.v:202064.18-202064.112" + wire $and$libresoc.v:202064$14874_Y + attribute \src "libresoc.v:202066.18-202066.112" + wire $and$libresoc.v:202066$14876_Y + attribute \src "libresoc.v:202068.18-202068.112" + wire $and$libresoc.v:202068$14878_Y + attribute \src "libresoc.v:201982.18-201982.109" + wire $eq$libresoc.v:201982$14792_Y + attribute \src "libresoc.v:202004.18-202004.109" + wire $eq$libresoc.v:202004$14814_Y + attribute \src "libresoc.v:202021.17-202021.114" + wire $eq$libresoc.v:202021$14831_Y + attribute \src "libresoc.v:202024.19-202024.110" + wire $eq$libresoc.v:202024$14834_Y + attribute \src "libresoc.v:202026.18-202026.109" + wire $eq$libresoc.v:202026$14836_Y + attribute \src "libresoc.v:202028.18-202028.109" + wire $eq$libresoc.v:202028$14838_Y + attribute \src "libresoc.v:202030.18-202030.109" + wire $eq$libresoc.v:202030$14840_Y + attribute \src "libresoc.v:202032.18-202032.109" + wire $eq$libresoc.v:202032$14842_Y + attribute \src "libresoc.v:202034.18-202034.109" + wire $eq$libresoc.v:202034$14844_Y + attribute \src "libresoc.v:202036.17-202036.114" + wire $eq$libresoc.v:202036$14846_Y + attribute \src "libresoc.v:202037.18-202037.109" + wire $eq$libresoc.v:202037$14847_Y + attribute \src "libresoc.v:202039.18-202039.109" + wire $eq$libresoc.v:202039$14849_Y + attribute \src "libresoc.v:202041.18-202041.110" + wire $eq$libresoc.v:202041$14851_Y + attribute \src "libresoc.v:202043.18-202043.110" + wire $eq$libresoc.v:202043$14853_Y + attribute \src "libresoc.v:202045.18-202045.110" + wire $eq$libresoc.v:202045$14855_Y + attribute \src "libresoc.v:202048.18-202048.110" + wire $eq$libresoc.v:202048$14858_Y + attribute \src "libresoc.v:202050.18-202050.110" + wire $eq$libresoc.v:202050$14860_Y + attribute \src "libresoc.v:202052.18-202052.110" + wire $eq$libresoc.v:202052$14862_Y + attribute \src "libresoc.v:202063.17-202063.108" + wire $eq$libresoc.v:202063$14873_Y + attribute \src "libresoc.v:201967.18-201967.111" + wire $lt$libresoc.v:201967$14777_Y + attribute \src "libresoc.v:201969.19-201969.112" + wire $lt$libresoc.v:201969$14779_Y + attribute \src "libresoc.v:201971.19-201971.112" + wire $lt$libresoc.v:201971$14781_Y + attribute \src "libresoc.v:201973.19-201973.112" + wire $lt$libresoc.v:201973$14783_Y + attribute \src "libresoc.v:201975.19-201975.112" + wire $lt$libresoc.v:201975$14785_Y + attribute \src "libresoc.v:201977.19-201977.112" + wire $lt$libresoc.v:201977$14787_Y + attribute \src "libresoc.v:201979.19-201979.112" + wire $lt$libresoc.v:201979$14789_Y + attribute \src "libresoc.v:201981.19-201981.112" + wire $lt$libresoc.v:201981$14791_Y + attribute \src "libresoc.v:201984.19-201984.112" + wire $lt$libresoc.v:201984$14794_Y + attribute \src "libresoc.v:201986.19-201986.112" + wire $lt$libresoc.v:201986$14796_Y + attribute \src "libresoc.v:201989.19-201989.112" + wire $lt$libresoc.v:201989$14799_Y + attribute \src "libresoc.v:201991.19-201991.112" + wire $lt$libresoc.v:201991$14801_Y + attribute \src "libresoc.v:201993.19-201993.112" + wire $lt$libresoc.v:201993$14803_Y + attribute \src "libresoc.v:201995.19-201995.112" + wire $lt$libresoc.v:201995$14805_Y + attribute \src "libresoc.v:201997.19-201997.113" + wire $lt$libresoc.v:201997$14807_Y + attribute \src "libresoc.v:201999.19-201999.113" + wire $lt$libresoc.v:201999$14809_Y + attribute \src "libresoc.v:202001.19-202001.114" + wire $lt$libresoc.v:202001$14811_Y + attribute \src "libresoc.v:202003.19-202003.114" + wire $lt$libresoc.v:202003$14813_Y + attribute \src "libresoc.v:202006.19-202006.114" + wire $lt$libresoc.v:202006$14816_Y + attribute \src "libresoc.v:202008.19-202008.114" + wire $lt$libresoc.v:202008$14818_Y + attribute \src "libresoc.v:202011.19-202011.114" + wire $lt$libresoc.v:202011$14821_Y + attribute \src "libresoc.v:202013.19-202013.114" + wire $lt$libresoc.v:202013$14823_Y + attribute \src "libresoc.v:202015.19-202015.114" + wire $lt$libresoc.v:202015$14825_Y + attribute \src "libresoc.v:202017.19-202017.114" + wire $lt$libresoc.v:202017$14827_Y + attribute \src "libresoc.v:202019.19-202019.114" + wire $lt$libresoc.v:202019$14829_Y + attribute \src "libresoc.v:202022.19-202022.114" + wire $lt$libresoc.v:202022$14832_Y + attribute \src "libresoc.v:202056.18-202056.110" + wire $lt$libresoc.v:202056$14866_Y + attribute \src "libresoc.v:202058.18-202058.110" + wire $lt$libresoc.v:202058$14868_Y + attribute \src "libresoc.v:202060.18-202060.111" + wire $lt$libresoc.v:202060$14870_Y + attribute \src "libresoc.v:202062.18-202062.111" + wire $lt$libresoc.v:202062$14872_Y + attribute \src "libresoc.v:202065.18-202065.111" + wire $lt$libresoc.v:202065$14875_Y + attribute \src "libresoc.v:202067.18-202067.111" + wire $lt$libresoc.v:202067$14877_Y + attribute \src "libresoc.v:202054.18-202054.40" + wire width 16 $shr$libresoc.v:202054$14864_Y + attribute \src "libresoc.v:201966.17-201966.114" + wire width 8 $ternary$libresoc.v:201966$14776_Y + attribute \src "libresoc.v:201988.18-201988.116" + wire width 8 $ternary$libresoc.v:201988$14798_Y + attribute \src "libresoc.v:202010.18-202010.116" + wire width 8 $ternary$libresoc.v:202010$14820_Y + attribute \src "libresoc.v:202025.19-202025.118" + wire width 8 $ternary$libresoc.v:202025$14835_Y + attribute \src "libresoc.v:202027.18-202027.116" + wire width 8 $ternary$libresoc.v:202027$14837_Y + attribute \src "libresoc.v:202029.18-202029.116" + wire width 8 $ternary$libresoc.v:202029$14839_Y + attribute \src "libresoc.v:202031.18-202031.116" + wire width 8 $ternary$libresoc.v:202031$14841_Y + attribute \src "libresoc.v:202033.18-202033.116" + wire width 8 $ternary$libresoc.v:202033$14843_Y + attribute \src "libresoc.v:202035.18-202035.116" + wire width 8 $ternary$libresoc.v:202035$14845_Y + attribute \src "libresoc.v:202038.18-202038.116" + wire width 8 $ternary$libresoc.v:202038$14848_Y + attribute \src "libresoc.v:202040.18-202040.116" + wire width 8 $ternary$libresoc.v:202040$14850_Y + attribute \src "libresoc.v:202042.18-202042.117" + wire width 8 $ternary$libresoc.v:202042$14852_Y + attribute \src "libresoc.v:202044.18-202044.117" + wire width 8 $ternary$libresoc.v:202044$14854_Y + attribute \src "libresoc.v:202046.18-202046.117" + wire width 8 $ternary$libresoc.v:202046$14856_Y + attribute \src "libresoc.v:202049.18-202049.117" + wire width 8 $ternary$libresoc.v:202049$14859_Y + attribute \src "libresoc.v:202051.18-202051.117" + wire width 8 $ternary$libresoc.v:202051$14861_Y + attribute \src "libresoc.v:202053.18-202053.117" + wire width 8 $ternary$libresoc.v:202053$14863_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" @@ -424285,7 +419552,7 @@ module \xics_ics wire input 7 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 11 \ics_wb__we - attribute \src "libresoc.v:202379.7-202379.15" + attribute \src "libresoc.v:201567.7-201567.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 5 \int_level_i @@ -424374,7 +419641,7 @@ module \xics_ics attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive9_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202780$14830 + cell $and $and$libresoc.v:201968$14778 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424382,10 +419649,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$99 - connect \Y $and$libresoc.v:202780$14830_Y + connect \Y $and$libresoc.v:201968$14778_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202782$14832 + cell $and $and$libresoc.v:201970$14780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424393,10 +419660,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$103 - connect \Y $and$libresoc.v:202782$14832_Y + connect \Y $and$libresoc.v:201970$14780_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202784$14834 + cell $and $and$libresoc.v:201972$14782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424404,10 +419671,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$107 - connect \Y $and$libresoc.v:202784$14834_Y + connect \Y $and$libresoc.v:201972$14782_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202786$14836 + cell $and $and$libresoc.v:201974$14784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424415,10 +419682,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$111 - connect \Y $and$libresoc.v:202786$14836_Y + connect \Y $and$libresoc.v:201974$14784_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202788$14838 + cell $and $and$libresoc.v:201976$14786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424426,10 +419693,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$115 - connect \Y $and$libresoc.v:202788$14838_Y + connect \Y $and$libresoc.v:201976$14786_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202790$14840 + cell $and $and$libresoc.v:201978$14788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424437,10 +419704,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$119 - connect \Y $and$libresoc.v:202790$14840_Y + connect \Y $and$libresoc.v:201978$14788_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202792$14842 + cell $and $and$libresoc.v:201980$14790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424448,10 +419715,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$123 - connect \Y $and$libresoc.v:202792$14842_Y + connect \Y $and$libresoc.v:201980$14790_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202795$14845 + cell $and $and$libresoc.v:201983$14793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424459,10 +419726,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$127 - connect \Y $and$libresoc.v:202795$14845_Y + connect \Y $and$libresoc.v:201983$14793_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202797$14847 + cell $and $and$libresoc.v:201985$14795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424470,10 +419737,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$131 - connect \Y $and$libresoc.v:202797$14847_Y + connect \Y $and$libresoc.v:201985$14795_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202799$14849 + cell $and $and$libresoc.v:201987$14797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424481,10 +419748,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$135 - connect \Y $and$libresoc.v:202799$14849_Y + connect \Y $and$libresoc.v:201987$14797_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202802$14852 + cell $and $and$libresoc.v:201990$14800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424492,10 +419759,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$139 - connect \Y $and$libresoc.v:202802$14852_Y + connect \Y $and$libresoc.v:201990$14800_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202804$14854 + cell $and $and$libresoc.v:201992$14802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424503,10 +419770,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$143 - connect \Y $and$libresoc.v:202804$14854_Y + connect \Y $and$libresoc.v:201992$14802_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202806$14856 + cell $and $and$libresoc.v:201994$14804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424514,10 +419781,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$147 - connect \Y $and$libresoc.v:202806$14856_Y + connect \Y $and$libresoc.v:201994$14804_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202808$14858 + cell $and $and$libresoc.v:201996$14806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424525,10 +419792,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$151 - connect \Y $and$libresoc.v:202808$14858_Y + connect \Y $and$libresoc.v:201996$14806_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202810$14860 + cell $and $and$libresoc.v:201998$14808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424536,10 +419803,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$155 - connect \Y $and$libresoc.v:202810$14860_Y + connect \Y $and$libresoc.v:201998$14808_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202812$14862 + cell $and $and$libresoc.v:202000$14810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424547,10 +419814,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$159 - connect \Y $and$libresoc.v:202812$14862_Y + connect \Y $and$libresoc.v:202000$14810_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202814$14864 + cell $and $and$libresoc.v:202002$14812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424558,10 +419825,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$163 - connect \Y $and$libresoc.v:202814$14864_Y + connect \Y $and$libresoc.v:202002$14812_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202817$14867 + cell $and $and$libresoc.v:202005$14815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424569,10 +419836,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$167 - connect \Y $and$libresoc.v:202817$14867_Y + connect \Y $and$libresoc.v:202005$14815_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202819$14869 + cell $and $and$libresoc.v:202007$14817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424580,10 +419847,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$171 - connect \Y $and$libresoc.v:202819$14869_Y + connect \Y $and$libresoc.v:202007$14817_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202821$14871 + cell $and $and$libresoc.v:202009$14819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424591,10 +419858,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$175 - connect \Y $and$libresoc.v:202821$14871_Y + connect \Y $and$libresoc.v:202009$14819_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202824$14874 + cell $and $and$libresoc.v:202012$14822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424602,10 +419869,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$179 - connect \Y $and$libresoc.v:202824$14874_Y + connect \Y $and$libresoc.v:202012$14822_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202826$14876 + cell $and $and$libresoc.v:202014$14824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424613,10 +419880,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$183 - connect \Y $and$libresoc.v:202826$14876_Y + connect \Y $and$libresoc.v:202014$14824_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202828$14878 + cell $and $and$libresoc.v:202016$14826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424624,10 +419891,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$187 - connect \Y $and$libresoc.v:202828$14878_Y + connect \Y $and$libresoc.v:202016$14826_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202830$14880 + cell $and $and$libresoc.v:202018$14828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424635,10 +419902,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$191 - connect \Y $and$libresoc.v:202830$14880_Y + connect \Y $and$libresoc.v:202018$14828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202832$14882 + cell $and $and$libresoc.v:202020$14830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424646,10 +419913,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$195 - connect \Y $and$libresoc.v:202832$14882_Y + connect \Y $and$libresoc.v:202020$14830_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202835$14885 + cell $and $and$libresoc.v:202023$14833 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424657,10 +419924,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$199 - connect \Y $and$libresoc.v:202835$14885_Y + connect \Y $and$libresoc.v:202023$14833_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" - cell $and $and$libresoc.v:202859$14909 + cell $and $and$libresoc.v:202047$14857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424668,10 +419935,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__cyc connect \B \ics_wb__stb - connect \Y $and$libresoc.v:202859$14909_Y + connect \Y $and$libresoc.v:202047$14857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" - cell $and $and$libresoc.v:202867$14917 + cell $and $and$libresoc.v:202055$14865 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424679,10 +419946,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \wb_valid connect \B \ics_wb__we - connect \Y $and$libresoc.v:202867$14917_Y + connect \Y $and$libresoc.v:202055$14865_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202869$14919 + cell $and $and$libresoc.v:202057$14867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424690,10 +419957,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$75 - connect \Y $and$libresoc.v:202869$14919_Y + connect \Y $and$libresoc.v:202057$14867_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202871$14921 + cell $and $and$libresoc.v:202059$14869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424701,10 +419968,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$79 - connect \Y $and$libresoc.v:202871$14921_Y + connect \Y $and$libresoc.v:202059$14869_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202873$14923 + cell $and $and$libresoc.v:202061$14871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424712,10 +419979,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$83 - connect \Y $and$libresoc.v:202873$14923_Y + connect \Y $and$libresoc.v:202061$14871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202876$14926 + cell $and $and$libresoc.v:202064$14874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424723,10 +419990,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$87 - connect \Y $and$libresoc.v:202876$14926_Y + connect \Y $and$libresoc.v:202064$14874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202878$14928 + cell $and $and$libresoc.v:202066$14876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424734,10 +420001,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$91 - connect \Y $and$libresoc.v:202878$14928_Y + connect \Y $and$libresoc.v:202066$14876_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202880$14930 + cell $and $and$libresoc.v:202068$14878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -424745,10 +420012,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$95 - connect \Y $and$libresoc.v:202880$14930_Y + connect \Y $and$libresoc.v:202068$14878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202794$14844 + cell $eq $eq$libresoc.v:201982$14792 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424756,10 +420023,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202794$14844_Y + connect \Y $eq$libresoc.v:201982$14792_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202816$14866 + cell $eq $eq$libresoc.v:202004$14814 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424767,10 +420034,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202816$14866_Y + connect \Y $eq$libresoc.v:202004$14814_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" - cell $eq $eq$libresoc.v:202833$14883 + cell $eq $eq$libresoc.v:202021$14831 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -424778,10 +420045,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 1'0 - connect \Y $eq$libresoc.v:202833$14883_Y + connect \Y $eq$libresoc.v:202021$14831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202836$14886 + cell $eq $eq$libresoc.v:202024$14834 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424789,10 +420056,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \cur_pri15 connect \B 8'11111111 - connect \Y $eq$libresoc.v:202836$14886_Y + connect \Y $eq$libresoc.v:202024$14834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202838$14888 + cell $eq $eq$libresoc.v:202026$14836 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424800,10 +420067,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202838$14888_Y + connect \Y $eq$libresoc.v:202026$14836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202840$14890 + cell $eq $eq$libresoc.v:202028$14838 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424811,10 +420078,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202840$14890_Y + connect \Y $eq$libresoc.v:202028$14838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202842$14892 + cell $eq $eq$libresoc.v:202030$14840 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424822,10 +420089,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202842$14892_Y + connect \Y $eq$libresoc.v:202030$14840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202844$14894 + cell $eq $eq$libresoc.v:202032$14842 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424833,10 +420100,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202844$14894_Y + connect \Y $eq$libresoc.v:202032$14842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202846$14896 + cell $eq $eq$libresoc.v:202034$14844 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424844,10 +420111,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202846$14896_Y + connect \Y $eq$libresoc.v:202034$14844_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" - cell $eq $eq$libresoc.v:202848$14898 + cell $eq $eq$libresoc.v:202036$14846 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -424855,10 +420122,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 3'100 - connect \Y $eq$libresoc.v:202848$14898_Y + connect \Y $eq$libresoc.v:202036$14846_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202849$14899 + cell $eq $eq$libresoc.v:202037$14847 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424866,10 +420133,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202849$14899_Y + connect \Y $eq$libresoc.v:202037$14847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202851$14901 + cell $eq $eq$libresoc.v:202039$14849 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424877,10 +420144,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202851$14901_Y + connect \Y $eq$libresoc.v:202039$14849_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202853$14903 + cell $eq $eq$libresoc.v:202041$14851 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424888,10 +420155,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202853$14903_Y + connect \Y $eq$libresoc.v:202041$14851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202855$14905 + cell $eq $eq$libresoc.v:202043$14853 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424899,10 +420166,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202855$14905_Y + connect \Y $eq$libresoc.v:202043$14853_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202857$14907 + cell $eq $eq$libresoc.v:202045$14855 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424910,10 +420177,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202857$14907_Y + connect \Y $eq$libresoc.v:202045$14855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202860$14910 + cell $eq $eq$libresoc.v:202048$14858 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424921,10 +420188,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202860$14910_Y + connect \Y $eq$libresoc.v:202048$14858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202862$14912 + cell $eq $eq$libresoc.v:202050$14860 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424932,10 +420199,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202862$14912_Y + connect \Y $eq$libresoc.v:202050$14860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202864$14914 + cell $eq $eq$libresoc.v:202052$14862 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424943,10 +420210,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202864$14914_Y + connect \Y $eq$libresoc.v:202052$14862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202875$14925 + cell $eq $eq$libresoc.v:202063$14873 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424954,10 +420221,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202875$14925_Y + connect \Y $eq$libresoc.v:202063$14873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202779$14829 + cell $lt $lt$libresoc.v:201967$14777 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424965,10 +420232,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:202779$14829_Y + connect \Y $lt$libresoc.v:201967$14777_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202781$14831 + cell $lt $lt$libresoc.v:201969$14779 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424976,10 +420243,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:202781$14831_Y + connect \Y $lt$libresoc.v:201969$14779_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202783$14833 + cell $lt $lt$libresoc.v:201971$14781 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424987,10 +420254,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:202783$14833_Y + connect \Y $lt$libresoc.v:201971$14781_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202785$14835 + cell $lt $lt$libresoc.v:201973$14783 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -424998,10 +420265,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:202785$14835_Y + connect \Y $lt$libresoc.v:201973$14783_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202787$14837 + cell $lt $lt$libresoc.v:201975$14785 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425009,10 +420276,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:202787$14837_Y + connect \Y $lt$libresoc.v:201975$14785_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202789$14839 + cell $lt $lt$libresoc.v:201977$14787 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425020,10 +420287,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:202789$14839_Y + connect \Y $lt$libresoc.v:201977$14787_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202791$14841 + cell $lt $lt$libresoc.v:201979$14789 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425031,10 +420298,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:202791$14841_Y + connect \Y $lt$libresoc.v:201979$14789_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202793$14843 + cell $lt $lt$libresoc.v:201981$14791 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425042,10 +420309,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:202793$14843_Y + connect \Y $lt$libresoc.v:201981$14791_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202796$14846 + cell $lt $lt$libresoc.v:201984$14794 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425053,10 +420320,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:202796$14846_Y + connect \Y $lt$libresoc.v:201984$14794_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202798$14848 + cell $lt $lt$libresoc.v:201986$14796 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425064,10 +420331,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:202798$14848_Y + connect \Y $lt$libresoc.v:201986$14796_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202801$14851 + cell $lt $lt$libresoc.v:201989$14799 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425075,10 +420342,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:202801$14851_Y + connect \Y $lt$libresoc.v:201989$14799_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202803$14853 + cell $lt $lt$libresoc.v:201991$14801 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425086,10 +420353,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:202803$14853_Y + connect \Y $lt$libresoc.v:201991$14801_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202805$14855 + cell $lt $lt$libresoc.v:201993$14803 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425097,10 +420364,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:202805$14855_Y + connect \Y $lt$libresoc.v:201993$14803_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202807$14857 + cell $lt $lt$libresoc.v:201995$14805 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425108,10 +420375,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:202807$14857_Y + connect \Y $lt$libresoc.v:201995$14805_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202809$14859 + cell $lt $lt$libresoc.v:201997$14807 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425119,10 +420386,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:202809$14859_Y + connect \Y $lt$libresoc.v:201997$14807_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202811$14861 + cell $lt $lt$libresoc.v:201999$14809 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425130,10 +420397,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:202811$14861_Y + connect \Y $lt$libresoc.v:201999$14809_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202813$14863 + cell $lt $lt$libresoc.v:202001$14811 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425141,10 +420408,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:202813$14863_Y + connect \Y $lt$libresoc.v:202001$14811_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202815$14865 + cell $lt $lt$libresoc.v:202003$14813 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425152,10 +420419,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:202815$14865_Y + connect \Y $lt$libresoc.v:202003$14813_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202818$14868 + cell $lt $lt$libresoc.v:202006$14816 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425163,10 +420430,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:202818$14868_Y + connect \Y $lt$libresoc.v:202006$14816_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202820$14870 + cell $lt $lt$libresoc.v:202008$14818 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425174,10 +420441,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:202820$14870_Y + connect \Y $lt$libresoc.v:202008$14818_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202823$14873 + cell $lt $lt$libresoc.v:202011$14821 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425185,10 +420452,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:202823$14873_Y + connect \Y $lt$libresoc.v:202011$14821_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202825$14875 + cell $lt $lt$libresoc.v:202013$14823 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425196,10 +420463,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:202825$14875_Y + connect \Y $lt$libresoc.v:202013$14823_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202827$14877 + cell $lt $lt$libresoc.v:202015$14825 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425207,10 +420474,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:202827$14877_Y + connect \Y $lt$libresoc.v:202015$14825_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202829$14879 + cell $lt $lt$libresoc.v:202017$14827 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425218,10 +420485,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:202829$14879_Y + connect \Y $lt$libresoc.v:202017$14827_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202831$14881 + cell $lt $lt$libresoc.v:202019$14829 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425229,10 +420496,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:202831$14881_Y + connect \Y $lt$libresoc.v:202019$14829_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202834$14884 + cell $lt $lt$libresoc.v:202022$14832 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425240,10 +420507,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:202834$14884_Y + connect \Y $lt$libresoc.v:202022$14832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202868$14918 + cell $lt $lt$libresoc.v:202056$14866 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425251,10 +420518,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:202868$14918_Y + connect \Y $lt$libresoc.v:202056$14866_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202870$14920 + cell $lt $lt$libresoc.v:202058$14868 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425262,10 +420529,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:202870$14920_Y + connect \Y $lt$libresoc.v:202058$14868_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202872$14922 + cell $lt $lt$libresoc.v:202060$14870 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425273,10 +420540,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:202872$14922_Y + connect \Y $lt$libresoc.v:202060$14870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202874$14924 + cell $lt $lt$libresoc.v:202062$14872 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425284,10 +420551,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:202874$14924_Y + connect \Y $lt$libresoc.v:202062$14872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202877$14927 + cell $lt $lt$libresoc.v:202065$14875 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425295,10 +420562,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:202877$14927_Y + connect \Y $lt$libresoc.v:202065$14875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202879$14929 + cell $lt $lt$libresoc.v:202067$14877 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -425306,10 +420573,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:202879$14929_Y + connect \Y $lt$libresoc.v:202067$14877_Y end - attribute \src "libresoc.v:202866.18-202866.40" - cell $shr $shr$libresoc.v:202866$14916 + attribute \src "libresoc.v:202054.18-202054.40" + cell $shr $shr$libresoc.v:202054$14864 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -425317,469 +420584,469 @@ module \xics_ics parameter \Y_WIDTH 16 connect \A \int_level_l connect \B \reg_idx - connect \Y $shr$libresoc.v:202866$14916_Y + connect \Y $shr$libresoc.v:202054$14864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202778$14828 + cell $mux $ternary$libresoc.v:201966$14776 parameter \WIDTH 8 connect \A \xive0_pri connect \B 8'11111111 connect \S \$8 - connect \Y $ternary$libresoc.v:202778$14828_Y + connect \Y $ternary$libresoc.v:201966$14776_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202800$14850 + cell $mux $ternary$libresoc.v:201988$14798 parameter \WIDTH 8 connect \A \xive1_pri connect \B 8'11111111 connect \S \$12 - connect \Y $ternary$libresoc.v:202800$14850_Y + connect \Y $ternary$libresoc.v:201988$14798_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202822$14872 + cell $mux $ternary$libresoc.v:202010$14820 parameter \WIDTH 8 connect \A \xive2_pri connect \B 8'11111111 connect \S \$16 - connect \Y $ternary$libresoc.v:202822$14872_Y + connect \Y $ternary$libresoc.v:202010$14820_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202837$14887 + cell $mux $ternary$libresoc.v:202025$14835 parameter \WIDTH 8 connect \A \cur_pri15 connect \B 8'11111111 connect \S \$204 - connect \Y $ternary$libresoc.v:202837$14887_Y + connect \Y $ternary$libresoc.v:202025$14835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202839$14889 + cell $mux $ternary$libresoc.v:202027$14837 parameter \WIDTH 8 connect \A \xive3_pri connect \B 8'11111111 connect \S \$20 - connect \Y $ternary$libresoc.v:202839$14889_Y + connect \Y $ternary$libresoc.v:202027$14837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202841$14891 + cell $mux $ternary$libresoc.v:202029$14839 parameter \WIDTH 8 connect \A \xive4_pri connect \B 8'11111111 connect \S \$24 - connect \Y $ternary$libresoc.v:202841$14891_Y + connect \Y $ternary$libresoc.v:202029$14839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202843$14893 + cell $mux $ternary$libresoc.v:202031$14841 parameter \WIDTH 8 connect \A \xive5_pri connect \B 8'11111111 connect \S \$28 - connect \Y $ternary$libresoc.v:202843$14893_Y + connect \Y $ternary$libresoc.v:202031$14841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202845$14895 + cell $mux $ternary$libresoc.v:202033$14843 parameter \WIDTH 8 connect \A \xive6_pri connect \B 8'11111111 connect \S \$32 - connect \Y $ternary$libresoc.v:202845$14895_Y + connect \Y $ternary$libresoc.v:202033$14843_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202847$14897 + cell $mux $ternary$libresoc.v:202035$14845 parameter \WIDTH 8 connect \A \xive7_pri connect \B 8'11111111 connect \S \$36 - connect \Y $ternary$libresoc.v:202847$14897_Y + connect \Y $ternary$libresoc.v:202035$14845_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202850$14900 + cell $mux $ternary$libresoc.v:202038$14848 parameter \WIDTH 8 connect \A \xive8_pri connect \B 8'11111111 connect \S \$40 - connect \Y $ternary$libresoc.v:202850$14900_Y + connect \Y $ternary$libresoc.v:202038$14848_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202852$14902 + cell $mux $ternary$libresoc.v:202040$14850 parameter \WIDTH 8 connect \A \xive9_pri connect \B 8'11111111 connect \S \$44 - connect \Y $ternary$libresoc.v:202852$14902_Y + connect \Y $ternary$libresoc.v:202040$14850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202854$14904 + cell $mux $ternary$libresoc.v:202042$14852 parameter \WIDTH 8 connect \A \xive10_pri connect \B 8'11111111 connect \S \$48 - connect \Y $ternary$libresoc.v:202854$14904_Y + connect \Y $ternary$libresoc.v:202042$14852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202856$14906 + cell $mux $ternary$libresoc.v:202044$14854 parameter \WIDTH 8 connect \A \xive11_pri connect \B 8'11111111 connect \S \$52 - connect \Y $ternary$libresoc.v:202856$14906_Y + connect \Y $ternary$libresoc.v:202044$14854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202858$14908 + cell $mux $ternary$libresoc.v:202046$14856 parameter \WIDTH 8 connect \A \xive12_pri connect \B 8'11111111 connect \S \$56 - connect \Y $ternary$libresoc.v:202858$14908_Y + connect \Y $ternary$libresoc.v:202046$14856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202861$14911 + cell $mux $ternary$libresoc.v:202049$14859 parameter \WIDTH 8 connect \A \xive13_pri connect \B 8'11111111 connect \S \$60 - connect \Y $ternary$libresoc.v:202861$14911_Y + connect \Y $ternary$libresoc.v:202049$14859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202863$14913 + cell $mux $ternary$libresoc.v:202051$14861 parameter \WIDTH 8 connect \A \xive14_pri connect \B 8'11111111 connect \S \$64 - connect \Y $ternary$libresoc.v:202863$14913_Y + connect \Y $ternary$libresoc.v:202051$14861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202865$14915 + cell $mux $ternary$libresoc.v:202053$14863 parameter \WIDTH 8 connect \A \xive15_pri connect \B 8'11111111 connect \S \$68 - connect \Y $ternary$libresoc.v:202865$14915_Y + connect \Y $ternary$libresoc.v:202053$14863_Y end - attribute \src "libresoc.v:202379.7-202379.20" - process $proc$libresoc.v:202379$15076 + attribute \src "libresoc.v:201567.7-201567.20" + process $proc$libresoc.v:201567$15024 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:202660.13-202660.30" - process $proc$libresoc.v:202660$15077 + attribute \src "libresoc.v:201848.13-201848.30" + process $proc$libresoc.v:201848$15025 assign { } { } assign $1\icp_o_pri[7:0] 8'00000000 sync always sync init update \icp_o_pri $1\icp_o_pri[7:0] end - attribute \src "libresoc.v:202665.13-202665.29" - process $proc$libresoc.v:202665$15078 + attribute \src "libresoc.v:201853.13-201853.29" + process $proc$libresoc.v:201853$15026 assign { } { } assign $1\icp_o_src[3:0] 4'0000 sync always sync init update \icp_o_src $1\icp_o_src[3:0] end - attribute \src "libresoc.v:202674.7-202674.25" - process $proc$libresoc.v:202674$15079 + attribute \src "libresoc.v:201862.7-201862.25" + process $proc$libresoc.v:201862$15027 assign { } { } assign $1\ics_wb__ack[0:0] 1'0 sync always sync init update \ics_wb__ack $1\ics_wb__ack[0:0] end - attribute \src "libresoc.v:202683.14-202683.35" - process $proc$libresoc.v:202683$15080 + attribute \src "libresoc.v:201871.14-201871.35" + process $proc$libresoc.v:201871$15028 assign { } { } assign $1\ics_wb__dat_r[31:0] 0 sync always sync init update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:202695.14-202695.36" - process $proc$libresoc.v:202695$15081 + attribute \src "libresoc.v:201883.14-201883.36" + process $proc$libresoc.v:201883$15029 assign { } { } assign $1\int_level_l[15:0] 16'0000000000000000 sync always sync init update \int_level_l $1\int_level_l[15:0] end - attribute \src "libresoc.v:202715.13-202715.30" - process $proc$libresoc.v:202715$15082 + attribute \src "libresoc.v:201903.13-201903.30" + process $proc$libresoc.v:201903$15030 assign { } { } assign $1\xive0_pri[7:0] 8'11111111 sync always sync init update \xive0_pri $1\xive0_pri[7:0] end - attribute \src "libresoc.v:202719.13-202719.31" - process $proc$libresoc.v:202719$15083 + attribute \src "libresoc.v:201907.13-201907.31" + process $proc$libresoc.v:201907$15031 assign { } { } assign $1\xive10_pri[7:0] 8'11111111 sync always sync init update \xive10_pri $1\xive10_pri[7:0] end - attribute \src "libresoc.v:202723.13-202723.31" - process $proc$libresoc.v:202723$15084 + attribute \src "libresoc.v:201911.13-201911.31" + process $proc$libresoc.v:201911$15032 assign { } { } assign $1\xive11_pri[7:0] 8'11111111 sync always sync init update \xive11_pri $1\xive11_pri[7:0] end - attribute \src "libresoc.v:202727.13-202727.31" - process $proc$libresoc.v:202727$15085 + attribute \src "libresoc.v:201915.13-201915.31" + process $proc$libresoc.v:201915$15033 assign { } { } assign $1\xive12_pri[7:0] 8'11111111 sync always sync init update \xive12_pri $1\xive12_pri[7:0] end - attribute \src "libresoc.v:202731.13-202731.31" - process $proc$libresoc.v:202731$15086 + attribute \src "libresoc.v:201919.13-201919.31" + process $proc$libresoc.v:201919$15034 assign { } { } assign $1\xive13_pri[7:0] 8'11111111 sync always sync init update \xive13_pri $1\xive13_pri[7:0] end - attribute \src "libresoc.v:202735.13-202735.31" - process $proc$libresoc.v:202735$15087 + attribute \src "libresoc.v:201923.13-201923.31" + process $proc$libresoc.v:201923$15035 assign { } { } assign $1\xive14_pri[7:0] 8'11111111 sync always sync init update \xive14_pri $1\xive14_pri[7:0] end - attribute \src "libresoc.v:202739.13-202739.31" - process $proc$libresoc.v:202739$15088 + attribute \src "libresoc.v:201927.13-201927.31" + process $proc$libresoc.v:201927$15036 assign { } { } assign $1\xive15_pri[7:0] 8'11111111 sync always sync init update \xive15_pri $1\xive15_pri[7:0] end - attribute \src "libresoc.v:202743.13-202743.30" - process $proc$libresoc.v:202743$15089 + attribute \src "libresoc.v:201931.13-201931.30" + process $proc$libresoc.v:201931$15037 assign { } { } assign $1\xive1_pri[7:0] 8'11111111 sync always sync init update \xive1_pri $1\xive1_pri[7:0] end - attribute \src "libresoc.v:202747.13-202747.30" - process $proc$libresoc.v:202747$15090 + attribute \src "libresoc.v:201935.13-201935.30" + process $proc$libresoc.v:201935$15038 assign { } { } assign $1\xive2_pri[7:0] 8'11111111 sync always sync init update \xive2_pri $1\xive2_pri[7:0] end - attribute \src "libresoc.v:202751.13-202751.30" - process $proc$libresoc.v:202751$15091 + attribute \src "libresoc.v:201939.13-201939.30" + process $proc$libresoc.v:201939$15039 assign { } { } assign $1\xive3_pri[7:0] 8'11111111 sync always sync init update \xive3_pri $1\xive3_pri[7:0] end - attribute \src "libresoc.v:202755.13-202755.30" - process $proc$libresoc.v:202755$15092 + attribute \src "libresoc.v:201943.13-201943.30" + process $proc$libresoc.v:201943$15040 assign { } { } assign $1\xive4_pri[7:0] 8'11111111 sync always sync init update \xive4_pri $1\xive4_pri[7:0] end - attribute \src "libresoc.v:202759.13-202759.30" - process $proc$libresoc.v:202759$15093 + attribute \src "libresoc.v:201947.13-201947.30" + process $proc$libresoc.v:201947$15041 assign { } { } assign $1\xive5_pri[7:0] 8'11111111 sync always sync init update \xive5_pri $1\xive5_pri[7:0] end - attribute \src "libresoc.v:202763.13-202763.30" - process $proc$libresoc.v:202763$15094 + attribute \src "libresoc.v:201951.13-201951.30" + process $proc$libresoc.v:201951$15042 assign { } { } assign $1\xive6_pri[7:0] 8'11111111 sync always sync init update \xive6_pri $1\xive6_pri[7:0] end - attribute \src "libresoc.v:202767.13-202767.30" - process $proc$libresoc.v:202767$15095 + attribute \src "libresoc.v:201955.13-201955.30" + process $proc$libresoc.v:201955$15043 assign { } { } assign $1\xive7_pri[7:0] 8'11111111 sync always sync init update \xive7_pri $1\xive7_pri[7:0] end - attribute \src "libresoc.v:202771.13-202771.30" - process $proc$libresoc.v:202771$15096 + attribute \src "libresoc.v:201959.13-201959.30" + process $proc$libresoc.v:201959$15044 assign { } { } assign $1\xive8_pri[7:0] 8'11111111 sync always sync init update \xive8_pri $1\xive8_pri[7:0] end - attribute \src "libresoc.v:202775.13-202775.30" - process $proc$libresoc.v:202775$15097 + attribute \src "libresoc.v:201963.13-201963.30" + process $proc$libresoc.v:201963$15045 assign { } { } assign $1\xive9_pri[7:0] 8'11111111 sync always sync init update \xive9_pri $1\xive9_pri[7:0] end - attribute \src "libresoc.v:202881.3-202882.28" - process $proc$libresoc.v:202881$14931 + attribute \src "libresoc.v:202069.3-202070.28" + process $proc$libresoc.v:202069$14879 assign { } { } assign $0\icp_o_src[3:0] \cur_idx15 sync posedge \clk update \icp_o_src $0\icp_o_src[3:0] end - attribute \src "libresoc.v:202883.3-202884.25" - process $proc$libresoc.v:202883$14932 + attribute \src "libresoc.v:202071.3-202072.25" + process $proc$libresoc.v:202071$14880 assign { } { } assign $0\icp_o_pri[7:0] \$203 sync posedge \clk update \icp_o_pri $0\icp_o_pri[7:0] end - attribute \src "libresoc.v:202885.3-202886.35" - process $proc$libresoc.v:202885$14933 + attribute \src "libresoc.v:202073.3-202074.35" + process $proc$libresoc.v:202073$14881 assign { } { } assign $0\xive0_pri[7:0] \xive0_pri$next sync posedge \clk update \xive0_pri $0\xive0_pri[7:0] end - attribute \src "libresoc.v:202887.3-202888.35" - process $proc$libresoc.v:202887$14934 + attribute \src "libresoc.v:202075.3-202076.35" + process $proc$libresoc.v:202075$14882 assign { } { } assign $0\xive1_pri[7:0] \xive1_pri$next sync posedge \clk update \xive1_pri $0\xive1_pri[7:0] end - attribute \src "libresoc.v:202889.3-202890.35" - process $proc$libresoc.v:202889$14935 + attribute \src "libresoc.v:202077.3-202078.35" + process $proc$libresoc.v:202077$14883 assign { } { } assign $0\xive2_pri[7:0] \xive2_pri$next sync posedge \clk update \xive2_pri $0\xive2_pri[7:0] end - attribute \src "libresoc.v:202891.3-202892.35" - process $proc$libresoc.v:202891$14936 + attribute \src "libresoc.v:202079.3-202080.35" + process $proc$libresoc.v:202079$14884 assign { } { } assign $0\xive3_pri[7:0] \xive3_pri$next sync posedge \clk update \xive3_pri $0\xive3_pri[7:0] end - attribute \src "libresoc.v:202893.3-202894.35" - process $proc$libresoc.v:202893$14937 + attribute \src "libresoc.v:202081.3-202082.35" + process $proc$libresoc.v:202081$14885 assign { } { } assign $0\xive4_pri[7:0] \xive4_pri$next sync posedge \clk update \xive4_pri $0\xive4_pri[7:0] end - attribute \src "libresoc.v:202895.3-202896.35" - process $proc$libresoc.v:202895$14938 + attribute \src "libresoc.v:202083.3-202084.35" + process $proc$libresoc.v:202083$14886 assign { } { } assign $0\xive5_pri[7:0] \xive5_pri$next sync posedge \clk update \xive5_pri $0\xive5_pri[7:0] end - attribute \src "libresoc.v:202897.3-202898.35" - process $proc$libresoc.v:202897$14939 + attribute \src "libresoc.v:202085.3-202086.35" + process $proc$libresoc.v:202085$14887 assign { } { } assign $0\xive6_pri[7:0] \xive6_pri$next sync posedge \clk update \xive6_pri $0\xive6_pri[7:0] end - attribute \src "libresoc.v:202899.3-202900.35" - process $proc$libresoc.v:202899$14940 + attribute \src "libresoc.v:202087.3-202088.35" + process $proc$libresoc.v:202087$14888 assign { } { } assign $0\xive7_pri[7:0] \xive7_pri$next sync posedge \clk update \xive7_pri $0\xive7_pri[7:0] end - attribute \src "libresoc.v:202901.3-202902.35" - process $proc$libresoc.v:202901$14941 + attribute \src "libresoc.v:202089.3-202090.35" + process $proc$libresoc.v:202089$14889 assign { } { } assign $0\xive8_pri[7:0] \xive8_pri$next sync posedge \clk update \xive8_pri $0\xive8_pri[7:0] end - attribute \src "libresoc.v:202903.3-202904.35" - process $proc$libresoc.v:202903$14942 + attribute \src "libresoc.v:202091.3-202092.35" + process $proc$libresoc.v:202091$14890 assign { } { } assign $0\xive9_pri[7:0] \xive9_pri$next sync posedge \clk update \xive9_pri $0\xive9_pri[7:0] end - attribute \src "libresoc.v:202905.3-202906.37" - process $proc$libresoc.v:202905$14943 + attribute \src "libresoc.v:202093.3-202094.37" + process $proc$libresoc.v:202093$14891 assign { } { } assign $0\xive10_pri[7:0] \xive10_pri$next sync posedge \clk update \xive10_pri $0\xive10_pri[7:0] end - attribute \src "libresoc.v:202907.3-202908.37" - process $proc$libresoc.v:202907$14944 + attribute \src "libresoc.v:202095.3-202096.37" + process $proc$libresoc.v:202095$14892 assign { } { } assign $0\xive11_pri[7:0] \xive11_pri$next sync posedge \clk update \xive11_pri $0\xive11_pri[7:0] end - attribute \src "libresoc.v:202909.3-202910.37" - process $proc$libresoc.v:202909$14945 + attribute \src "libresoc.v:202097.3-202098.37" + process $proc$libresoc.v:202097$14893 assign { } { } assign $0\xive12_pri[7:0] \xive12_pri$next sync posedge \clk update \xive12_pri $0\xive12_pri[7:0] end - attribute \src "libresoc.v:202911.3-202912.37" - process $proc$libresoc.v:202911$14946 + attribute \src "libresoc.v:202099.3-202100.37" + process $proc$libresoc.v:202099$14894 assign { } { } assign $0\xive13_pri[7:0] \xive13_pri$next sync posedge \clk update \xive13_pri $0\xive13_pri[7:0] end - attribute \src "libresoc.v:202913.3-202914.37" - process $proc$libresoc.v:202913$14947 + attribute \src "libresoc.v:202101.3-202102.37" + process $proc$libresoc.v:202101$14895 assign { } { } assign $0\xive14_pri[7:0] \xive14_pri$next sync posedge \clk update \xive14_pri $0\xive14_pri[7:0] end - attribute \src "libresoc.v:202915.3-202916.37" - process $proc$libresoc.v:202915$14948 + attribute \src "libresoc.v:202103.3-202104.37" + process $proc$libresoc.v:202103$14896 assign { } { } assign $0\xive15_pri[7:0] \xive15_pri$next sync posedge \clk update \xive15_pri $0\xive15_pri[7:0] end - attribute \src "libresoc.v:202917.3-202918.39" - process $proc$libresoc.v:202917$14949 + attribute \src "libresoc.v:202105.3-202106.39" + process $proc$libresoc.v:202105$14897 assign { } { } assign $0\ics_wb__ack[0:0] \ics_wb__ack$next sync posedge \clk update \ics_wb__ack $0\ics_wb__ack[0:0] end - attribute \src "libresoc.v:202919.3-202920.43" - process $proc$libresoc.v:202919$14950 + attribute \src "libresoc.v:202107.3-202108.43" + process $proc$libresoc.v:202107$14898 assign { } { } assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next sync posedge \clk update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:202921.3-202922.39" - process $proc$libresoc.v:202921$14951 + attribute \src "libresoc.v:202109.3-202110.39" + process $proc$libresoc.v:202109$14899 assign { } { } assign $0\int_level_l[15:0] \int_level_l$next sync posedge \clk update \int_level_l $0\int_level_l[15:0] end - attribute \src "libresoc.v:202923.3-203008.6" - process $proc$libresoc.v:202923$14952 + attribute \src "libresoc.v:202111.3-202196.6" + process $proc$libresoc.v:202111$14900 assign { } { } assign { } { } assign { } { } @@ -425828,25 +421095,25 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $0\xive0_pri$next[7:0]$14953 $4\xive0_pri$next[7:0]$15017 - assign $0\xive10_pri$next[7:0]$14954 $4\xive10_pri$next[7:0]$15018 - assign $0\xive11_pri$next[7:0]$14955 $4\xive11_pri$next[7:0]$15019 - assign $0\xive12_pri$next[7:0]$14956 $4\xive12_pri$next[7:0]$15020 - assign $0\xive13_pri$next[7:0]$14957 $4\xive13_pri$next[7:0]$15021 - assign $0\xive14_pri$next[7:0]$14958 $4\xive14_pri$next[7:0]$15022 - assign $0\xive15_pri$next[7:0]$14959 $4\xive15_pri$next[7:0]$15023 - assign $0\xive1_pri$next[7:0]$14960 $4\xive1_pri$next[7:0]$15024 - assign $0\xive2_pri$next[7:0]$14961 $4\xive2_pri$next[7:0]$15025 - assign $0\xive3_pri$next[7:0]$14962 $4\xive3_pri$next[7:0]$15026 - assign $0\xive4_pri$next[7:0]$14963 $4\xive4_pri$next[7:0]$15027 - assign $0\xive5_pri$next[7:0]$14964 $4\xive5_pri$next[7:0]$15028 - assign $0\xive6_pri$next[7:0]$14965 $4\xive6_pri$next[7:0]$15029 - assign $0\xive7_pri$next[7:0]$14966 $4\xive7_pri$next[7:0]$15030 - assign $0\xive8_pri$next[7:0]$14967 $4\xive8_pri$next[7:0]$15031 - assign $0\xive9_pri$next[7:0]$14968 $4\xive9_pri$next[7:0]$15032 - attribute \src "libresoc.v:202924.5-202924.29" + assign $0\xive0_pri$next[7:0]$14901 $4\xive0_pri$next[7:0]$14965 + assign $0\xive10_pri$next[7:0]$14902 $4\xive10_pri$next[7:0]$14966 + assign $0\xive11_pri$next[7:0]$14903 $4\xive11_pri$next[7:0]$14967 + assign $0\xive12_pri$next[7:0]$14904 $4\xive12_pri$next[7:0]$14968 + assign $0\xive13_pri$next[7:0]$14905 $4\xive13_pri$next[7:0]$14969 + assign $0\xive14_pri$next[7:0]$14906 $4\xive14_pri$next[7:0]$14970 + assign $0\xive15_pri$next[7:0]$14907 $4\xive15_pri$next[7:0]$14971 + assign $0\xive1_pri$next[7:0]$14908 $4\xive1_pri$next[7:0]$14972 + assign $0\xive2_pri$next[7:0]$14909 $4\xive2_pri$next[7:0]$14973 + assign $0\xive3_pri$next[7:0]$14910 $4\xive3_pri$next[7:0]$14974 + assign $0\xive4_pri$next[7:0]$14911 $4\xive4_pri$next[7:0]$14975 + assign $0\xive5_pri$next[7:0]$14912 $4\xive5_pri$next[7:0]$14976 + assign $0\xive6_pri$next[7:0]$14913 $4\xive6_pri$next[7:0]$14977 + assign $0\xive7_pri$next[7:0]$14914 $4\xive7_pri$next[7:0]$14978 + assign $0\xive8_pri$next[7:0]$14915 $4\xive8_pri$next[7:0]$14979 + assign $0\xive9_pri$next[7:0]$14916 $4\xive9_pri$next[7:0]$14980 + attribute \src "libresoc.v:202112.5-202112.29" switch \initial - attribute \src "libresoc.v:202924.9-202924.17" + attribute \src "libresoc.v:202112.9-202112.17" case 1'1 case end @@ -425870,22 +421137,22 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $1\xive0_pri$next[7:0]$14969 $2\xive0_pri$next[7:0]$14985 - assign $1\xive10_pri$next[7:0]$14970 $2\xive10_pri$next[7:0]$14986 - assign $1\xive11_pri$next[7:0]$14971 $2\xive11_pri$next[7:0]$14987 - assign $1\xive12_pri$next[7:0]$14972 $2\xive12_pri$next[7:0]$14988 - assign $1\xive13_pri$next[7:0]$14973 $2\xive13_pri$next[7:0]$14989 - assign $1\xive14_pri$next[7:0]$14974 $2\xive14_pri$next[7:0]$14990 - assign $1\xive15_pri$next[7:0]$14975 $2\xive15_pri$next[7:0]$14991 - assign $1\xive1_pri$next[7:0]$14976 $2\xive1_pri$next[7:0]$14992 - assign $1\xive2_pri$next[7:0]$14977 $2\xive2_pri$next[7:0]$14993 - assign $1\xive3_pri$next[7:0]$14978 $2\xive3_pri$next[7:0]$14994 - assign $1\xive4_pri$next[7:0]$14979 $2\xive4_pri$next[7:0]$14995 - assign $1\xive5_pri$next[7:0]$14980 $2\xive5_pri$next[7:0]$14996 - assign $1\xive6_pri$next[7:0]$14981 $2\xive6_pri$next[7:0]$14997 - assign $1\xive7_pri$next[7:0]$14982 $2\xive7_pri$next[7:0]$14998 - assign $1\xive8_pri$next[7:0]$14983 $2\xive8_pri$next[7:0]$14999 - assign $1\xive9_pri$next[7:0]$14984 $2\xive9_pri$next[7:0]$15000 + assign $1\xive0_pri$next[7:0]$14917 $2\xive0_pri$next[7:0]$14933 + assign $1\xive10_pri$next[7:0]$14918 $2\xive10_pri$next[7:0]$14934 + assign $1\xive11_pri$next[7:0]$14919 $2\xive11_pri$next[7:0]$14935 + assign $1\xive12_pri$next[7:0]$14920 $2\xive12_pri$next[7:0]$14936 + assign $1\xive13_pri$next[7:0]$14921 $2\xive13_pri$next[7:0]$14937 + assign $1\xive14_pri$next[7:0]$14922 $2\xive14_pri$next[7:0]$14938 + assign $1\xive15_pri$next[7:0]$14923 $2\xive15_pri$next[7:0]$14939 + assign $1\xive1_pri$next[7:0]$14924 $2\xive1_pri$next[7:0]$14940 + assign $1\xive2_pri$next[7:0]$14925 $2\xive2_pri$next[7:0]$14941 + assign $1\xive3_pri$next[7:0]$14926 $2\xive3_pri$next[7:0]$14942 + assign $1\xive4_pri$next[7:0]$14927 $2\xive4_pri$next[7:0]$14943 + assign $1\xive5_pri$next[7:0]$14928 $2\xive5_pri$next[7:0]$14944 + assign $1\xive6_pri$next[7:0]$14929 $2\xive6_pri$next[7:0]$14945 + assign $1\xive7_pri$next[7:0]$14930 $2\xive7_pri$next[7:0]$14946 + assign $1\xive8_pri$next[7:0]$14931 $2\xive8_pri$next[7:0]$14947 + assign $1\xive9_pri$next[7:0]$14932 $2\xive9_pri$next[7:0]$14948 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" switch \reg_is_xive attribute \src "libresoc.v:0.0-0.0" @@ -425906,381 +421173,381 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $2\xive0_pri$next[7:0]$14985 $3\xive0_pri$next[7:0]$15001 - assign $2\xive10_pri$next[7:0]$14986 $3\xive10_pri$next[7:0]$15002 - assign $2\xive11_pri$next[7:0]$14987 $3\xive11_pri$next[7:0]$15003 - assign $2\xive12_pri$next[7:0]$14988 $3\xive12_pri$next[7:0]$15004 - assign $2\xive13_pri$next[7:0]$14989 $3\xive13_pri$next[7:0]$15005 - assign $2\xive14_pri$next[7:0]$14990 $3\xive14_pri$next[7:0]$15006 - assign $2\xive15_pri$next[7:0]$14991 $3\xive15_pri$next[7:0]$15007 - assign $2\xive1_pri$next[7:0]$14992 $3\xive1_pri$next[7:0]$15008 - assign $2\xive2_pri$next[7:0]$14993 $3\xive2_pri$next[7:0]$15009 - assign $2\xive3_pri$next[7:0]$14994 $3\xive3_pri$next[7:0]$15010 - assign $2\xive4_pri$next[7:0]$14995 $3\xive4_pri$next[7:0]$15011 - assign $2\xive5_pri$next[7:0]$14996 $3\xive5_pri$next[7:0]$15012 - assign $2\xive6_pri$next[7:0]$14997 $3\xive6_pri$next[7:0]$15013 - assign $2\xive7_pri$next[7:0]$14998 $3\xive7_pri$next[7:0]$15014 - assign $2\xive8_pri$next[7:0]$14999 $3\xive8_pri$next[7:0]$15015 - assign $2\xive9_pri$next[7:0]$15000 $3\xive9_pri$next[7:0]$15016 + assign $2\xive0_pri$next[7:0]$14933 $3\xive0_pri$next[7:0]$14949 + assign $2\xive10_pri$next[7:0]$14934 $3\xive10_pri$next[7:0]$14950 + assign $2\xive11_pri$next[7:0]$14935 $3\xive11_pri$next[7:0]$14951 + assign $2\xive12_pri$next[7:0]$14936 $3\xive12_pri$next[7:0]$14952 + assign $2\xive13_pri$next[7:0]$14937 $3\xive13_pri$next[7:0]$14953 + assign $2\xive14_pri$next[7:0]$14938 $3\xive14_pri$next[7:0]$14954 + assign $2\xive15_pri$next[7:0]$14939 $3\xive15_pri$next[7:0]$14955 + assign $2\xive1_pri$next[7:0]$14940 $3\xive1_pri$next[7:0]$14956 + assign $2\xive2_pri$next[7:0]$14941 $3\xive2_pri$next[7:0]$14957 + assign $2\xive3_pri$next[7:0]$14942 $3\xive3_pri$next[7:0]$14958 + assign $2\xive4_pri$next[7:0]$14943 $3\xive4_pri$next[7:0]$14959 + assign $2\xive5_pri$next[7:0]$14944 $3\xive5_pri$next[7:0]$14960 + assign $2\xive6_pri$next[7:0]$14945 $3\xive6_pri$next[7:0]$14961 + assign $2\xive7_pri$next[7:0]$14946 $3\xive7_pri$next[7:0]$14962 + assign $2\xive8_pri$next[7:0]$14947 $3\xive8_pri$next[7:0]$14963 + assign $2\xive9_pri$next[7:0]$14948 $3\xive9_pri$next[7:0]$14964 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" switch \reg_idx attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive0_pri$next[7:0]$15001 \be_in [7:0] + assign $3\xive10_pri$next[7:0]$14950 \xive10_pri + assign $3\xive11_pri$next[7:0]$14951 \xive11_pri + assign $3\xive12_pri$next[7:0]$14952 \xive12_pri + assign $3\xive13_pri$next[7:0]$14953 \xive13_pri + assign $3\xive14_pri$next[7:0]$14954 \xive14_pri + assign $3\xive15_pri$next[7:0]$14955 \xive15_pri + assign $3\xive1_pri$next[7:0]$14956 \xive1_pri + assign $3\xive2_pri$next[7:0]$14957 \xive2_pri + assign $3\xive3_pri$next[7:0]$14958 \xive3_pri + assign $3\xive4_pri$next[7:0]$14959 \xive4_pri + assign $3\xive5_pri$next[7:0]$14960 \xive5_pri + assign $3\xive6_pri$next[7:0]$14961 \xive6_pri + assign $3\xive7_pri$next[7:0]$14962 \xive7_pri + assign $3\xive8_pri$next[7:0]$14963 \xive8_pri + assign $3\xive9_pri$next[7:0]$14964 \xive9_pri + assign $3\xive0_pri$next[7:0]$14949 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0001 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri + assign $3\xive0_pri$next[7:0]$14949 \xive0_pri + assign $3\xive10_pri$next[7:0]$14950 \xive10_pri + assign $3\xive11_pri$next[7:0]$14951 \xive11_pri + assign $3\xive12_pri$next[7:0]$14952 \xive12_pri + assign $3\xive13_pri$next[7:0]$14953 \xive13_pri + assign $3\xive14_pri$next[7:0]$14954 \xive14_pri + assign $3\xive15_pri$next[7:0]$14955 \xive15_pri assign { } { } - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive1_pri$next[7:0]$15008 \be_in [7:0] + assign $3\xive2_pri$next[7:0]$14957 \xive2_pri + assign $3\xive3_pri$next[7:0]$14958 \xive3_pri + assign $3\xive4_pri$next[7:0]$14959 \xive4_pri + assign $3\xive5_pri$next[7:0]$14960 \xive5_pri + assign $3\xive6_pri$next[7:0]$14961 \xive6_pri + assign $3\xive7_pri$next[7:0]$14962 \xive7_pri + assign $3\xive8_pri$next[7:0]$14963 \xive8_pri + assign $3\xive9_pri$next[7:0]$14964 \xive9_pri + assign $3\xive1_pri$next[7:0]$14956 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0010 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri + assign $3\xive0_pri$next[7:0]$14949 \xive0_pri + assign $3\xive10_pri$next[7:0]$14950 \xive10_pri + assign $3\xive11_pri$next[7:0]$14951 \xive11_pri + assign $3\xive12_pri$next[7:0]$14952 \xive12_pri + assign $3\xive13_pri$next[7:0]$14953 \xive13_pri + assign $3\xive14_pri$next[7:0]$14954 \xive14_pri + assign $3\xive15_pri$next[7:0]$14955 \xive15_pri + assign $3\xive1_pri$next[7:0]$14956 \xive1_pri assign { } { } - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive2_pri$next[7:0]$15009 \be_in [7:0] + assign $3\xive3_pri$next[7:0]$14958 \xive3_pri + assign $3\xive4_pri$next[7:0]$14959 \xive4_pri + assign $3\xive5_pri$next[7:0]$14960 \xive5_pri + assign $3\xive6_pri$next[7:0]$14961 \xive6_pri + assign $3\xive7_pri$next[7:0]$14962 \xive7_pri + assign $3\xive8_pri$next[7:0]$14963 \xive8_pri + assign $3\xive9_pri$next[7:0]$14964 \xive9_pri + assign $3\xive2_pri$next[7:0]$14957 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0011 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri + assign $3\xive0_pri$next[7:0]$14949 \xive0_pri + assign $3\xive10_pri$next[7:0]$14950 \xive10_pri + assign $3\xive11_pri$next[7:0]$14951 \xive11_pri + assign $3\xive12_pri$next[7:0]$14952 \xive12_pri + assign $3\xive13_pri$next[7:0]$14953 \xive13_pri + assign $3\xive14_pri$next[7:0]$14954 \xive14_pri + assign $3\xive15_pri$next[7:0]$14955 \xive15_pri + assign $3\xive1_pri$next[7:0]$14956 \xive1_pri + assign $3\xive2_pri$next[7:0]$14957 \xive2_pri assign { } { } - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive3_pri$next[7:0]$15010 \be_in [7:0] + assign $3\xive4_pri$next[7:0]$14959 \xive4_pri + assign $3\xive5_pri$next[7:0]$14960 \xive5_pri + assign $3\xive6_pri$next[7:0]$14961 \xive6_pri + assign $3\xive7_pri$next[7:0]$14962 \xive7_pri + assign $3\xive8_pri$next[7:0]$14963 \xive8_pri + assign $3\xive9_pri$next[7:0]$14964 \xive9_pri + assign $3\xive3_pri$next[7:0]$14958 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0100 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri + assign $3\xive0_pri$next[7:0]$14949 \xive0_pri + assign $3\xive10_pri$next[7:0]$14950 \xive10_pri + assign $3\xive11_pri$next[7:0]$14951 \xive11_pri + assign $3\xive12_pri$next[7:0]$14952 \xive12_pri + assign $3\xive13_pri$next[7:0]$14953 \xive13_pri + assign $3\xive14_pri$next[7:0]$14954 \xive14_pri + assign $3\xive15_pri$next[7:0]$14955 \xive15_pri + assign $3\xive1_pri$next[7:0]$14956 \xive1_pri + assign $3\xive2_pri$next[7:0]$14957 \xive2_pri + assign $3\xive3_pri$next[7:0]$14958 \xive3_pri assign { } { } - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive4_pri$next[7:0]$15011 \be_in [7:0] + assign $3\xive5_pri$next[7:0]$14960 \xive5_pri + assign $3\xive6_pri$next[7:0]$14961 \xive6_pri + assign $3\xive7_pri$next[7:0]$14962 \xive7_pri + assign $3\xive8_pri$next[7:0]$14963 \xive8_pri + assign $3\xive9_pri$next[7:0]$14964 \xive9_pri + assign $3\xive4_pri$next[7:0]$14959 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0101 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri + assign $3\xive0_pri$next[7:0]$14949 \xive0_pri + assign $3\xive10_pri$next[7:0]$14950 \xive10_pri + assign $3\xive11_pri$next[7:0]$14951 \xive11_pri + assign $3\xive12_pri$next[7:0]$14952 \xive12_pri + assign $3\xive13_pri$next[7:0]$14953 \xive13_pri + assign $3\xive14_pri$next[7:0]$14954 \xive14_pri + assign $3\xive15_pri$next[7:0]$14955 \xive15_pri + assign $3\xive1_pri$next[7:0]$14956 \xive1_pri + assign $3\xive2_pri$next[7:0]$14957 \xive2_pri + assign $3\xive3_pri$next[7:0]$14958 \xive3_pri + assign $3\xive4_pri$next[7:0]$14959 \xive4_pri assign { } { } - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive5_pri$next[7:0]$15012 \be_in [7:0] + assign $3\xive6_pri$next[7:0]$14961 \xive6_pri + assign $3\xive7_pri$next[7:0]$14962 \xive7_pri + assign $3\xive8_pri$next[7:0]$14963 \xive8_pri + assign $3\xive9_pri$next[7:0]$14964 \xive9_pri + assign $3\xive5_pri$next[7:0]$14960 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0110 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri + assign $3\xive0_pri$next[7:0]$14949 \xive0_pri + assign $3\xive10_pri$next[7:0]$14950 \xive10_pri + assign $3\xive11_pri$next[7:0]$14951 \xive11_pri + assign $3\xive12_pri$next[7:0]$14952 \xive12_pri + assign $3\xive13_pri$next[7:0]$14953 \xive13_pri + assign $3\xive14_pri$next[7:0]$14954 \xive14_pri + assign $3\xive15_pri$next[7:0]$14955 \xive15_pri + assign $3\xive1_pri$next[7:0]$14956 \xive1_pri + assign $3\xive2_pri$next[7:0]$14957 \xive2_pri + assign $3\xive3_pri$next[7:0]$14958 \xive3_pri + assign $3\xive4_pri$next[7:0]$14959 \xive4_pri + assign $3\xive5_pri$next[7:0]$14960 \xive5_pri assign { } { } - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive6_pri$next[7:0]$15013 \be_in [7:0] + assign $3\xive7_pri$next[7:0]$14962 \xive7_pri + assign $3\xive8_pri$next[7:0]$14963 \xive8_pri + assign $3\xive9_pri$next[7:0]$14964 \xive9_pri + assign $3\xive6_pri$next[7:0]$14961 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0111 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri + assign $3\xive0_pri$next[7:0]$14949 \xive0_pri + assign $3\xive10_pri$next[7:0]$14950 \xive10_pri + assign $3\xive11_pri$next[7:0]$14951 \xive11_pri + assign $3\xive12_pri$next[7:0]$14952 \xive12_pri + assign $3\xive13_pri$next[7:0]$14953 \xive13_pri + assign $3\xive14_pri$next[7:0]$14954 \xive14_pri + assign $3\xive15_pri$next[7:0]$14955 \xive15_pri + assign $3\xive1_pri$next[7:0]$14956 \xive1_pri + assign $3\xive2_pri$next[7:0]$14957 \xive2_pri + assign $3\xive3_pri$next[7:0]$14958 \xive3_pri + assign $3\xive4_pri$next[7:0]$14959 \xive4_pri + assign $3\xive5_pri$next[7:0]$14960 \xive5_pri + assign $3\xive6_pri$next[7:0]$14961 \xive6_pri assign { } { } - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive7_pri$next[7:0]$15014 \be_in [7:0] + assign $3\xive8_pri$next[7:0]$14963 \xive8_pri + assign $3\xive9_pri$next[7:0]$14964 \xive9_pri + assign $3\xive7_pri$next[7:0]$14962 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1000 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri + assign $3\xive0_pri$next[7:0]$14949 \xive0_pri + assign $3\xive10_pri$next[7:0]$14950 \xive10_pri + assign $3\xive11_pri$next[7:0]$14951 \xive11_pri + assign $3\xive12_pri$next[7:0]$14952 \xive12_pri + assign $3\xive13_pri$next[7:0]$14953 \xive13_pri + assign $3\xive14_pri$next[7:0]$14954 \xive14_pri + assign $3\xive15_pri$next[7:0]$14955 \xive15_pri + assign $3\xive1_pri$next[7:0]$14956 \xive1_pri + assign $3\xive2_pri$next[7:0]$14957 \xive2_pri + assign $3\xive3_pri$next[7:0]$14958 \xive3_pri + assign $3\xive4_pri$next[7:0]$14959 \xive4_pri + assign $3\xive5_pri$next[7:0]$14960 \xive5_pri + assign $3\xive6_pri$next[7:0]$14961 \xive6_pri + assign $3\xive7_pri$next[7:0]$14962 \xive7_pri assign { } { } - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive8_pri$next[7:0]$15015 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14964 \xive9_pri + assign $3\xive8_pri$next[7:0]$14963 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1001 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri + assign $3\xive0_pri$next[7:0]$14949 \xive0_pri + assign $3\xive10_pri$next[7:0]$14950 \xive10_pri + assign $3\xive11_pri$next[7:0]$14951 \xive11_pri + assign $3\xive12_pri$next[7:0]$14952 \xive12_pri + assign $3\xive13_pri$next[7:0]$14953 \xive13_pri + assign $3\xive14_pri$next[7:0]$14954 \xive14_pri + assign $3\xive15_pri$next[7:0]$14955 \xive15_pri + assign $3\xive1_pri$next[7:0]$14956 \xive1_pri + assign $3\xive2_pri$next[7:0]$14957 \xive2_pri + assign $3\xive3_pri$next[7:0]$14958 \xive3_pri + assign $3\xive4_pri$next[7:0]$14959 \xive4_pri + assign $3\xive5_pri$next[7:0]$14960 \xive5_pri + assign $3\xive6_pri$next[7:0]$14961 \xive6_pri + assign $3\xive7_pri$next[7:0]$14962 \xive7_pri + assign $3\xive8_pri$next[7:0]$14963 \xive8_pri assign { } { } - assign $3\xive9_pri$next[7:0]$15016 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14964 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1010 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri + assign $3\xive0_pri$next[7:0]$14949 \xive0_pri assign { } { } - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive10_pri$next[7:0]$15002 \be_in [7:0] + assign $3\xive11_pri$next[7:0]$14951 \xive11_pri + assign $3\xive12_pri$next[7:0]$14952 \xive12_pri + assign $3\xive13_pri$next[7:0]$14953 \xive13_pri + assign $3\xive14_pri$next[7:0]$14954 \xive14_pri + assign $3\xive15_pri$next[7:0]$14955 \xive15_pri + assign $3\xive1_pri$next[7:0]$14956 \xive1_pri + assign $3\xive2_pri$next[7:0]$14957 \xive2_pri + assign $3\xive3_pri$next[7:0]$14958 \xive3_pri + assign $3\xive4_pri$next[7:0]$14959 \xive4_pri + assign $3\xive5_pri$next[7:0]$14960 \xive5_pri + assign $3\xive6_pri$next[7:0]$14961 \xive6_pri + assign $3\xive7_pri$next[7:0]$14962 \xive7_pri + assign $3\xive8_pri$next[7:0]$14963 \xive8_pri + assign $3\xive9_pri$next[7:0]$14964 \xive9_pri + assign $3\xive10_pri$next[7:0]$14950 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1011 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri + assign $3\xive0_pri$next[7:0]$14949 \xive0_pri + assign $3\xive10_pri$next[7:0]$14950 \xive10_pri assign { } { } - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive11_pri$next[7:0]$15003 \be_in [7:0] + assign $3\xive12_pri$next[7:0]$14952 \xive12_pri + assign $3\xive13_pri$next[7:0]$14953 \xive13_pri + assign $3\xive14_pri$next[7:0]$14954 \xive14_pri + assign $3\xive15_pri$next[7:0]$14955 \xive15_pri + assign $3\xive1_pri$next[7:0]$14956 \xive1_pri + assign $3\xive2_pri$next[7:0]$14957 \xive2_pri + assign $3\xive3_pri$next[7:0]$14958 \xive3_pri + assign $3\xive4_pri$next[7:0]$14959 \xive4_pri + assign $3\xive5_pri$next[7:0]$14960 \xive5_pri + assign $3\xive6_pri$next[7:0]$14961 \xive6_pri + assign $3\xive7_pri$next[7:0]$14962 \xive7_pri + assign $3\xive8_pri$next[7:0]$14963 \xive8_pri + assign $3\xive9_pri$next[7:0]$14964 \xive9_pri + assign $3\xive11_pri$next[7:0]$14951 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1100 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri + assign $3\xive0_pri$next[7:0]$14949 \xive0_pri + assign $3\xive10_pri$next[7:0]$14950 \xive10_pri + assign $3\xive11_pri$next[7:0]$14951 \xive11_pri assign { } { } - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive12_pri$next[7:0]$15004 \be_in [7:0] + assign $3\xive13_pri$next[7:0]$14953 \xive13_pri + assign $3\xive14_pri$next[7:0]$14954 \xive14_pri + assign $3\xive15_pri$next[7:0]$14955 \xive15_pri + assign $3\xive1_pri$next[7:0]$14956 \xive1_pri + assign $3\xive2_pri$next[7:0]$14957 \xive2_pri + assign $3\xive3_pri$next[7:0]$14958 \xive3_pri + assign $3\xive4_pri$next[7:0]$14959 \xive4_pri + assign $3\xive5_pri$next[7:0]$14960 \xive5_pri + assign $3\xive6_pri$next[7:0]$14961 \xive6_pri + assign $3\xive7_pri$next[7:0]$14962 \xive7_pri + assign $3\xive8_pri$next[7:0]$14963 \xive8_pri + assign $3\xive9_pri$next[7:0]$14964 \xive9_pri + assign $3\xive12_pri$next[7:0]$14952 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1101 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri + assign $3\xive0_pri$next[7:0]$14949 \xive0_pri + assign $3\xive10_pri$next[7:0]$14950 \xive10_pri + assign $3\xive11_pri$next[7:0]$14951 \xive11_pri + assign $3\xive12_pri$next[7:0]$14952 \xive12_pri assign { } { } - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive13_pri$next[7:0]$15005 \be_in [7:0] + assign $3\xive14_pri$next[7:0]$14954 \xive14_pri + assign $3\xive15_pri$next[7:0]$14955 \xive15_pri + assign $3\xive1_pri$next[7:0]$14956 \xive1_pri + assign $3\xive2_pri$next[7:0]$14957 \xive2_pri + assign $3\xive3_pri$next[7:0]$14958 \xive3_pri + assign $3\xive4_pri$next[7:0]$14959 \xive4_pri + assign $3\xive5_pri$next[7:0]$14960 \xive5_pri + assign $3\xive6_pri$next[7:0]$14961 \xive6_pri + assign $3\xive7_pri$next[7:0]$14962 \xive7_pri + assign $3\xive8_pri$next[7:0]$14963 \xive8_pri + assign $3\xive9_pri$next[7:0]$14964 \xive9_pri + assign $3\xive13_pri$next[7:0]$14953 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1110 - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri + assign $3\xive0_pri$next[7:0]$14949 \xive0_pri + assign $3\xive10_pri$next[7:0]$14950 \xive10_pri + assign $3\xive11_pri$next[7:0]$14951 \xive11_pri + assign $3\xive12_pri$next[7:0]$14952 \xive12_pri + assign $3\xive13_pri$next[7:0]$14953 \xive13_pri assign { } { } - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive14_pri$next[7:0]$15006 \be_in [7:0] + assign $3\xive15_pri$next[7:0]$14955 \xive15_pri + assign $3\xive1_pri$next[7:0]$14956 \xive1_pri + assign $3\xive2_pri$next[7:0]$14957 \xive2_pri + assign $3\xive3_pri$next[7:0]$14958 \xive3_pri + assign $3\xive4_pri$next[7:0]$14959 \xive4_pri + assign $3\xive5_pri$next[7:0]$14960 \xive5_pri + assign $3\xive6_pri$next[7:0]$14961 \xive6_pri + assign $3\xive7_pri$next[7:0]$14962 \xive7_pri + assign $3\xive8_pri$next[7:0]$14963 \xive8_pri + assign $3\xive9_pri$next[7:0]$14964 \xive9_pri + assign $3\xive14_pri$next[7:0]$14954 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'---- - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri + assign $3\xive0_pri$next[7:0]$14949 \xive0_pri + assign $3\xive10_pri$next[7:0]$14950 \xive10_pri + assign $3\xive11_pri$next[7:0]$14951 \xive11_pri + assign $3\xive12_pri$next[7:0]$14952 \xive12_pri + assign $3\xive13_pri$next[7:0]$14953 \xive13_pri + assign $3\xive14_pri$next[7:0]$14954 \xive14_pri assign { } { } - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri - assign $3\xive15_pri$next[7:0]$15007 \be_in [7:0] + assign $3\xive1_pri$next[7:0]$14956 \xive1_pri + assign $3\xive2_pri$next[7:0]$14957 \xive2_pri + assign $3\xive3_pri$next[7:0]$14958 \xive3_pri + assign $3\xive4_pri$next[7:0]$14959 \xive4_pri + assign $3\xive5_pri$next[7:0]$14960 \xive5_pri + assign $3\xive6_pri$next[7:0]$14961 \xive6_pri + assign $3\xive7_pri$next[7:0]$14962 \xive7_pri + assign $3\xive8_pri$next[7:0]$14963 \xive8_pri + assign $3\xive9_pri$next[7:0]$14964 \xive9_pri + assign $3\xive15_pri$next[7:0]$14955 \be_in [7:0] case - assign $3\xive0_pri$next[7:0]$15001 \xive0_pri - assign $3\xive10_pri$next[7:0]$15002 \xive10_pri - assign $3\xive11_pri$next[7:0]$15003 \xive11_pri - assign $3\xive12_pri$next[7:0]$15004 \xive12_pri - assign $3\xive13_pri$next[7:0]$15005 \xive13_pri - assign $3\xive14_pri$next[7:0]$15006 \xive14_pri - assign $3\xive15_pri$next[7:0]$15007 \xive15_pri - assign $3\xive1_pri$next[7:0]$15008 \xive1_pri - assign $3\xive2_pri$next[7:0]$15009 \xive2_pri - assign $3\xive3_pri$next[7:0]$15010 \xive3_pri - assign $3\xive4_pri$next[7:0]$15011 \xive4_pri - assign $3\xive5_pri$next[7:0]$15012 \xive5_pri - assign $3\xive6_pri$next[7:0]$15013 \xive6_pri - assign $3\xive7_pri$next[7:0]$15014 \xive7_pri - assign $3\xive8_pri$next[7:0]$15015 \xive8_pri - assign $3\xive9_pri$next[7:0]$15016 \xive9_pri + assign $3\xive0_pri$next[7:0]$14949 \xive0_pri + assign $3\xive10_pri$next[7:0]$14950 \xive10_pri + assign $3\xive11_pri$next[7:0]$14951 \xive11_pri + assign $3\xive12_pri$next[7:0]$14952 \xive12_pri + assign $3\xive13_pri$next[7:0]$14953 \xive13_pri + assign $3\xive14_pri$next[7:0]$14954 \xive14_pri + assign $3\xive15_pri$next[7:0]$14955 \xive15_pri + assign $3\xive1_pri$next[7:0]$14956 \xive1_pri + assign $3\xive2_pri$next[7:0]$14957 \xive2_pri + assign $3\xive3_pri$next[7:0]$14958 \xive3_pri + assign $3\xive4_pri$next[7:0]$14959 \xive4_pri + assign $3\xive5_pri$next[7:0]$14960 \xive5_pri + assign $3\xive6_pri$next[7:0]$14961 \xive6_pri + assign $3\xive7_pri$next[7:0]$14962 \xive7_pri + assign $3\xive8_pri$next[7:0]$14963 \xive8_pri + assign $3\xive9_pri$next[7:0]$14964 \xive9_pri end case - assign $2\xive0_pri$next[7:0]$14985 \xive0_pri - assign $2\xive10_pri$next[7:0]$14986 \xive10_pri - assign $2\xive11_pri$next[7:0]$14987 \xive11_pri - assign $2\xive12_pri$next[7:0]$14988 \xive12_pri - assign $2\xive13_pri$next[7:0]$14989 \xive13_pri - assign $2\xive14_pri$next[7:0]$14990 \xive14_pri - assign $2\xive15_pri$next[7:0]$14991 \xive15_pri - assign $2\xive1_pri$next[7:0]$14992 \xive1_pri - assign $2\xive2_pri$next[7:0]$14993 \xive2_pri - assign $2\xive3_pri$next[7:0]$14994 \xive3_pri - assign $2\xive4_pri$next[7:0]$14995 \xive4_pri - assign $2\xive5_pri$next[7:0]$14996 \xive5_pri - assign $2\xive6_pri$next[7:0]$14997 \xive6_pri - assign $2\xive7_pri$next[7:0]$14998 \xive7_pri - assign $2\xive8_pri$next[7:0]$14999 \xive8_pri - assign $2\xive9_pri$next[7:0]$15000 \xive9_pri - end - case - assign $1\xive0_pri$next[7:0]$14969 \xive0_pri - assign $1\xive10_pri$next[7:0]$14970 \xive10_pri - assign $1\xive11_pri$next[7:0]$14971 \xive11_pri - assign $1\xive12_pri$next[7:0]$14972 \xive12_pri - assign $1\xive13_pri$next[7:0]$14973 \xive13_pri - assign $1\xive14_pri$next[7:0]$14974 \xive14_pri - assign $1\xive15_pri$next[7:0]$14975 \xive15_pri - assign $1\xive1_pri$next[7:0]$14976 \xive1_pri - assign $1\xive2_pri$next[7:0]$14977 \xive2_pri - assign $1\xive3_pri$next[7:0]$14978 \xive3_pri - assign $1\xive4_pri$next[7:0]$14979 \xive4_pri - assign $1\xive5_pri$next[7:0]$14980 \xive5_pri - assign $1\xive6_pri$next[7:0]$14981 \xive6_pri - assign $1\xive7_pri$next[7:0]$14982 \xive7_pri - assign $1\xive8_pri$next[7:0]$14983 \xive8_pri - assign $1\xive9_pri$next[7:0]$14984 \xive9_pri + assign $2\xive0_pri$next[7:0]$14933 \xive0_pri + assign $2\xive10_pri$next[7:0]$14934 \xive10_pri + assign $2\xive11_pri$next[7:0]$14935 \xive11_pri + assign $2\xive12_pri$next[7:0]$14936 \xive12_pri + assign $2\xive13_pri$next[7:0]$14937 \xive13_pri + assign $2\xive14_pri$next[7:0]$14938 \xive14_pri + assign $2\xive15_pri$next[7:0]$14939 \xive15_pri + assign $2\xive1_pri$next[7:0]$14940 \xive1_pri + assign $2\xive2_pri$next[7:0]$14941 \xive2_pri + assign $2\xive3_pri$next[7:0]$14942 \xive3_pri + assign $2\xive4_pri$next[7:0]$14943 \xive4_pri + assign $2\xive5_pri$next[7:0]$14944 \xive5_pri + assign $2\xive6_pri$next[7:0]$14945 \xive6_pri + assign $2\xive7_pri$next[7:0]$14946 \xive7_pri + assign $2\xive8_pri$next[7:0]$14947 \xive8_pri + assign $2\xive9_pri$next[7:0]$14948 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$14917 \xive0_pri + assign $1\xive10_pri$next[7:0]$14918 \xive10_pri + assign $1\xive11_pri$next[7:0]$14919 \xive11_pri + assign $1\xive12_pri$next[7:0]$14920 \xive12_pri + assign $1\xive13_pri$next[7:0]$14921 \xive13_pri + assign $1\xive14_pri$next[7:0]$14922 \xive14_pri + assign $1\xive15_pri$next[7:0]$14923 \xive15_pri + assign $1\xive1_pri$next[7:0]$14924 \xive1_pri + assign $1\xive2_pri$next[7:0]$14925 \xive2_pri + assign $1\xive3_pri$next[7:0]$14926 \xive3_pri + assign $1\xive4_pri$next[7:0]$14927 \xive4_pri + assign $1\xive5_pri$next[7:0]$14928 \xive5_pri + assign $1\xive6_pri$next[7:0]$14929 \xive6_pri + assign $1\xive7_pri$next[7:0]$14930 \xive7_pri + assign $1\xive8_pri$next[7:0]$14931 \xive8_pri + assign $1\xive9_pri$next[7:0]$14932 \xive9_pri end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -426302,66 +421569,66 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $4\xive0_pri$next[7:0]$15017 8'11111111 - assign $4\xive1_pri$next[7:0]$15024 8'11111111 - assign $4\xive2_pri$next[7:0]$15025 8'11111111 - assign $4\xive3_pri$next[7:0]$15026 8'11111111 - assign $4\xive4_pri$next[7:0]$15027 8'11111111 - assign $4\xive5_pri$next[7:0]$15028 8'11111111 - assign $4\xive6_pri$next[7:0]$15029 8'11111111 - assign $4\xive7_pri$next[7:0]$15030 8'11111111 - assign $4\xive8_pri$next[7:0]$15031 8'11111111 - assign $4\xive9_pri$next[7:0]$15032 8'11111111 - assign $4\xive10_pri$next[7:0]$15018 8'11111111 - assign $4\xive11_pri$next[7:0]$15019 8'11111111 - assign $4\xive12_pri$next[7:0]$15020 8'11111111 - assign $4\xive13_pri$next[7:0]$15021 8'11111111 - assign $4\xive14_pri$next[7:0]$15022 8'11111111 - assign $4\xive15_pri$next[7:0]$15023 8'11111111 + assign $4\xive0_pri$next[7:0]$14965 8'11111111 + assign $4\xive1_pri$next[7:0]$14972 8'11111111 + assign $4\xive2_pri$next[7:0]$14973 8'11111111 + assign $4\xive3_pri$next[7:0]$14974 8'11111111 + assign $4\xive4_pri$next[7:0]$14975 8'11111111 + assign $4\xive5_pri$next[7:0]$14976 8'11111111 + assign $4\xive6_pri$next[7:0]$14977 8'11111111 + assign $4\xive7_pri$next[7:0]$14978 8'11111111 + assign $4\xive8_pri$next[7:0]$14979 8'11111111 + assign $4\xive9_pri$next[7:0]$14980 8'11111111 + assign $4\xive10_pri$next[7:0]$14966 8'11111111 + assign $4\xive11_pri$next[7:0]$14967 8'11111111 + assign $4\xive12_pri$next[7:0]$14968 8'11111111 + assign $4\xive13_pri$next[7:0]$14969 8'11111111 + assign $4\xive14_pri$next[7:0]$14970 8'11111111 + assign $4\xive15_pri$next[7:0]$14971 8'11111111 case - assign $4\xive0_pri$next[7:0]$15017 $1\xive0_pri$next[7:0]$14969 - assign $4\xive10_pri$next[7:0]$15018 $1\xive10_pri$next[7:0]$14970 - assign $4\xive11_pri$next[7:0]$15019 $1\xive11_pri$next[7:0]$14971 - assign $4\xive12_pri$next[7:0]$15020 $1\xive12_pri$next[7:0]$14972 - assign $4\xive13_pri$next[7:0]$15021 $1\xive13_pri$next[7:0]$14973 - assign $4\xive14_pri$next[7:0]$15022 $1\xive14_pri$next[7:0]$14974 - assign $4\xive15_pri$next[7:0]$15023 $1\xive15_pri$next[7:0]$14975 - assign $4\xive1_pri$next[7:0]$15024 $1\xive1_pri$next[7:0]$14976 - assign $4\xive2_pri$next[7:0]$15025 $1\xive2_pri$next[7:0]$14977 - assign $4\xive3_pri$next[7:0]$15026 $1\xive3_pri$next[7:0]$14978 - assign $4\xive4_pri$next[7:0]$15027 $1\xive4_pri$next[7:0]$14979 - assign $4\xive5_pri$next[7:0]$15028 $1\xive5_pri$next[7:0]$14980 - assign $4\xive6_pri$next[7:0]$15029 $1\xive6_pri$next[7:0]$14981 - assign $4\xive7_pri$next[7:0]$15030 $1\xive7_pri$next[7:0]$14982 - assign $4\xive8_pri$next[7:0]$15031 $1\xive8_pri$next[7:0]$14983 - assign $4\xive9_pri$next[7:0]$15032 $1\xive9_pri$next[7:0]$14984 + assign $4\xive0_pri$next[7:0]$14965 $1\xive0_pri$next[7:0]$14917 + assign $4\xive10_pri$next[7:0]$14966 $1\xive10_pri$next[7:0]$14918 + assign $4\xive11_pri$next[7:0]$14967 $1\xive11_pri$next[7:0]$14919 + assign $4\xive12_pri$next[7:0]$14968 $1\xive12_pri$next[7:0]$14920 + assign $4\xive13_pri$next[7:0]$14969 $1\xive13_pri$next[7:0]$14921 + assign $4\xive14_pri$next[7:0]$14970 $1\xive14_pri$next[7:0]$14922 + assign $4\xive15_pri$next[7:0]$14971 $1\xive15_pri$next[7:0]$14923 + assign $4\xive1_pri$next[7:0]$14972 $1\xive1_pri$next[7:0]$14924 + assign $4\xive2_pri$next[7:0]$14973 $1\xive2_pri$next[7:0]$14925 + assign $4\xive3_pri$next[7:0]$14974 $1\xive3_pri$next[7:0]$14926 + assign $4\xive4_pri$next[7:0]$14975 $1\xive4_pri$next[7:0]$14927 + assign $4\xive5_pri$next[7:0]$14976 $1\xive5_pri$next[7:0]$14928 + assign $4\xive6_pri$next[7:0]$14977 $1\xive6_pri$next[7:0]$14929 + assign $4\xive7_pri$next[7:0]$14978 $1\xive7_pri$next[7:0]$14930 + assign $4\xive8_pri$next[7:0]$14979 $1\xive8_pri$next[7:0]$14931 + assign $4\xive9_pri$next[7:0]$14980 $1\xive9_pri$next[7:0]$14932 end sync always - update \xive0_pri$next $0\xive0_pri$next[7:0]$14953 - update \xive10_pri$next $0\xive10_pri$next[7:0]$14954 - update \xive11_pri$next $0\xive11_pri$next[7:0]$14955 - update \xive12_pri$next $0\xive12_pri$next[7:0]$14956 - update \xive13_pri$next $0\xive13_pri$next[7:0]$14957 - update \xive14_pri$next $0\xive14_pri$next[7:0]$14958 - update \xive15_pri$next $0\xive15_pri$next[7:0]$14959 - update \xive1_pri$next $0\xive1_pri$next[7:0]$14960 - update \xive2_pri$next $0\xive2_pri$next[7:0]$14961 - update \xive3_pri$next $0\xive3_pri$next[7:0]$14962 - update \xive4_pri$next $0\xive4_pri$next[7:0]$14963 - update \xive5_pri$next $0\xive5_pri$next[7:0]$14964 - update \xive6_pri$next $0\xive6_pri$next[7:0]$14965 - update \xive7_pri$next $0\xive7_pri$next[7:0]$14966 - update \xive8_pri$next $0\xive8_pri$next[7:0]$14967 - update \xive9_pri$next $0\xive9_pri$next[7:0]$14968 + update \xive0_pri$next $0\xive0_pri$next[7:0]$14901 + update \xive10_pri$next $0\xive10_pri$next[7:0]$14902 + update \xive11_pri$next $0\xive11_pri$next[7:0]$14903 + update \xive12_pri$next $0\xive12_pri$next[7:0]$14904 + update \xive13_pri$next $0\xive13_pri$next[7:0]$14905 + update \xive14_pri$next $0\xive14_pri$next[7:0]$14906 + update \xive15_pri$next $0\xive15_pri$next[7:0]$14907 + update \xive1_pri$next $0\xive1_pri$next[7:0]$14908 + update \xive2_pri$next $0\xive2_pri$next[7:0]$14909 + update \xive3_pri$next $0\xive3_pri$next[7:0]$14910 + update \xive4_pri$next $0\xive4_pri$next[7:0]$14911 + update \xive5_pri$next $0\xive5_pri$next[7:0]$14912 + update \xive6_pri$next $0\xive6_pri$next[7:0]$14913 + update \xive7_pri$next $0\xive7_pri$next[7:0]$14914 + update \xive8_pri$next $0\xive8_pri$next[7:0]$14915 + update \xive9_pri$next $0\xive9_pri$next[7:0]$14916 end - attribute \src "libresoc.v:203009.3-203018.6" - process $proc$libresoc.v:203009$15033 + attribute \src "libresoc.v:202197.3-202206.6" + process $proc$libresoc.v:202197$14981 assign { } { } assign { } { } assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] - attribute \src "libresoc.v:203010.5-203010.29" + attribute \src "libresoc.v:202198.5-202198.29" switch \initial - attribute \src "libresoc.v:203010.9-203010.17" + attribute \src "libresoc.v:202198.9-202198.17" case 1'1 case end @@ -426377,14 +421644,14 @@ module \xics_ics sync always update \cur_pri0 $0\cur_pri0[7:0] end - attribute \src "libresoc.v:203019.3-203028.6" - process $proc$libresoc.v:203019$15034 + attribute \src "libresoc.v:202207.3-202216.6" + process $proc$libresoc.v:202207$14982 assign { } { } assign { } { } assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] - attribute \src "libresoc.v:203020.5-203020.29" + attribute \src "libresoc.v:202208.5-202208.29" switch \initial - attribute \src "libresoc.v:203020.9-203020.17" + attribute \src "libresoc.v:202208.9-202208.17" case 1'1 case end @@ -426400,14 +421667,14 @@ module \xics_ics sync always update \cur_idx0 $0\cur_idx0[3:0] end - attribute \src "libresoc.v:203029.3-203038.6" - process $proc$libresoc.v:203029$15035 + attribute \src "libresoc.v:202217.3-202226.6" + process $proc$libresoc.v:202217$14983 assign { } { } assign { } { } assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] - attribute \src "libresoc.v:203030.5-203030.29" + attribute \src "libresoc.v:202218.5-202218.29" switch \initial - attribute \src "libresoc.v:203030.9-203030.17" + attribute \src "libresoc.v:202218.9-202218.17" case 1'1 case end @@ -426423,14 +421690,14 @@ module \xics_ics sync always update \cur_pri1 $0\cur_pri1[7:0] end - attribute \src "libresoc.v:203039.3-203048.6" - process $proc$libresoc.v:203039$15036 + attribute \src "libresoc.v:202227.3-202236.6" + process $proc$libresoc.v:202227$14984 assign { } { } assign { } { } assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] - attribute \src "libresoc.v:203040.5-203040.29" + attribute \src "libresoc.v:202228.5-202228.29" switch \initial - attribute \src "libresoc.v:203040.9-203040.17" + attribute \src "libresoc.v:202228.9-202228.17" case 1'1 case end @@ -426446,14 +421713,14 @@ module \xics_ics sync always update \cur_idx1 $0\cur_idx1[3:0] end - attribute \src "libresoc.v:203049.3-203058.6" - process $proc$libresoc.v:203049$15037 + attribute \src "libresoc.v:202237.3-202246.6" + process $proc$libresoc.v:202237$14985 assign { } { } assign { } { } assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] - attribute \src "libresoc.v:203050.5-203050.29" + attribute \src "libresoc.v:202238.5-202238.29" switch \initial - attribute \src "libresoc.v:203050.9-203050.17" + attribute \src "libresoc.v:202238.9-202238.17" case 1'1 case end @@ -426469,14 +421736,14 @@ module \xics_ics sync always update \cur_pri2 $0\cur_pri2[7:0] end - attribute \src "libresoc.v:203059.3-203068.6" - process $proc$libresoc.v:203059$15038 + attribute \src "libresoc.v:202247.3-202256.6" + process $proc$libresoc.v:202247$14986 assign { } { } assign { } { } assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] - attribute \src "libresoc.v:203060.5-203060.29" + attribute \src "libresoc.v:202248.5-202248.29" switch \initial - attribute \src "libresoc.v:203060.9-203060.17" + attribute \src "libresoc.v:202248.9-202248.17" case 1'1 case end @@ -426492,14 +421759,14 @@ module \xics_ics sync always update \cur_idx2 $0\cur_idx2[3:0] end - attribute \src "libresoc.v:203069.3-203078.6" - process $proc$libresoc.v:203069$15039 + attribute \src "libresoc.v:202257.3-202266.6" + process $proc$libresoc.v:202257$14987 assign { } { } assign { } { } assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] - attribute \src "libresoc.v:203070.5-203070.29" + attribute \src "libresoc.v:202258.5-202258.29" switch \initial - attribute \src "libresoc.v:203070.9-203070.17" + attribute \src "libresoc.v:202258.9-202258.17" case 1'1 case end @@ -426515,14 +421782,14 @@ module \xics_ics sync always update \cur_pri3 $0\cur_pri3[7:0] end - attribute \src "libresoc.v:203079.3-203088.6" - process $proc$libresoc.v:203079$15040 + attribute \src "libresoc.v:202267.3-202276.6" + process $proc$libresoc.v:202267$14988 assign { } { } assign { } { } assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] - attribute \src "libresoc.v:203080.5-203080.29" + attribute \src "libresoc.v:202268.5-202268.29" switch \initial - attribute \src "libresoc.v:203080.9-203080.17" + attribute \src "libresoc.v:202268.9-202268.17" case 1'1 case end @@ -426538,14 +421805,14 @@ module \xics_ics sync always update \cur_idx3 $0\cur_idx3[3:0] end - attribute \src "libresoc.v:203089.3-203098.6" - process $proc$libresoc.v:203089$15041 + attribute \src "libresoc.v:202277.3-202286.6" + process $proc$libresoc.v:202277$14989 assign { } { } assign { } { } assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] - attribute \src "libresoc.v:203090.5-203090.29" + attribute \src "libresoc.v:202278.5-202278.29" switch \initial - attribute \src "libresoc.v:203090.9-203090.17" + attribute \src "libresoc.v:202278.9-202278.17" case 1'1 case end @@ -426561,14 +421828,14 @@ module \xics_ics sync always update \cur_pri4 $0\cur_pri4[7:0] end - attribute \src "libresoc.v:203099.3-203107.6" - process $proc$libresoc.v:203099$15042 + attribute \src "libresoc.v:202287.3-202295.6" + process $proc$libresoc.v:202287$14990 assign { } { } assign { } { } - assign $0\int_level_l$next[15:0]$15043 $1\int_level_l$next[15:0]$15044 - attribute \src "libresoc.v:203100.5-203100.29" + assign $0\int_level_l$next[15:0]$14991 $1\int_level_l$next[15:0]$14992 + attribute \src "libresoc.v:202288.5-202288.29" switch \initial - attribute \src "libresoc.v:203100.9-203100.17" + attribute \src "libresoc.v:202288.9-202288.17" case 1'1 case end @@ -426577,21 +421844,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\int_level_l$next[15:0]$15044 16'0000000000000000 + assign $1\int_level_l$next[15:0]$14992 16'0000000000000000 case - assign $1\int_level_l$next[15:0]$15044 \int_level_i + assign $1\int_level_l$next[15:0]$14992 \int_level_i end sync always - update \int_level_l$next $0\int_level_l$next[15:0]$15043 + update \int_level_l$next $0\int_level_l$next[15:0]$14991 end - attribute \src "libresoc.v:203108.3-203117.6" - process $proc$libresoc.v:203108$15045 + attribute \src "libresoc.v:202296.3-202305.6" + process $proc$libresoc.v:202296$14993 assign { } { } assign { } { } assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] - attribute \src "libresoc.v:203109.5-203109.29" + attribute \src "libresoc.v:202297.5-202297.29" switch \initial - attribute \src "libresoc.v:203109.9-203109.17" + attribute \src "libresoc.v:202297.9-202297.17" case 1'1 case end @@ -426607,14 +421874,14 @@ module \xics_ics sync always update \cur_idx4 $0\cur_idx4[3:0] end - attribute \src "libresoc.v:203118.3-203127.6" - process $proc$libresoc.v:203118$15046 + attribute \src "libresoc.v:202306.3-202315.6" + process $proc$libresoc.v:202306$14994 assign { } { } assign { } { } assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] - attribute \src "libresoc.v:203119.5-203119.29" + attribute \src "libresoc.v:202307.5-202307.29" switch \initial - attribute \src "libresoc.v:203119.9-203119.17" + attribute \src "libresoc.v:202307.9-202307.17" case 1'1 case end @@ -426630,14 +421897,14 @@ module \xics_ics sync always update \cur_pri5 $0\cur_pri5[7:0] end - attribute \src "libresoc.v:203128.3-203137.6" - process $proc$libresoc.v:203128$15047 + attribute \src "libresoc.v:202316.3-202325.6" + process $proc$libresoc.v:202316$14995 assign { } { } assign { } { } assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] - attribute \src "libresoc.v:203129.5-203129.29" + attribute \src "libresoc.v:202317.5-202317.29" switch \initial - attribute \src "libresoc.v:203129.9-203129.17" + attribute \src "libresoc.v:202317.9-202317.17" case 1'1 case end @@ -426653,14 +421920,14 @@ module \xics_ics sync always update \cur_idx5 $0\cur_idx5[3:0] end - attribute \src "libresoc.v:203138.3-203147.6" - process $proc$libresoc.v:203138$15048 + attribute \src "libresoc.v:202326.3-202335.6" + process $proc$libresoc.v:202326$14996 assign { } { } assign { } { } assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] - attribute \src "libresoc.v:203139.5-203139.29" + attribute \src "libresoc.v:202327.5-202327.29" switch \initial - attribute \src "libresoc.v:203139.9-203139.17" + attribute \src "libresoc.v:202327.9-202327.17" case 1'1 case end @@ -426676,14 +421943,14 @@ module \xics_ics sync always update \cur_pri6 $0\cur_pri6[7:0] end - attribute \src "libresoc.v:203148.3-203157.6" - process $proc$libresoc.v:203148$15049 + attribute \src "libresoc.v:202336.3-202345.6" + process $proc$libresoc.v:202336$14997 assign { } { } assign { } { } assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] - attribute \src "libresoc.v:203149.5-203149.29" + attribute \src "libresoc.v:202337.5-202337.29" switch \initial - attribute \src "libresoc.v:203149.9-203149.17" + attribute \src "libresoc.v:202337.9-202337.17" case 1'1 case end @@ -426699,14 +421966,14 @@ module \xics_ics sync always update \cur_idx6 $0\cur_idx6[3:0] end - attribute \src "libresoc.v:203158.3-203167.6" - process $proc$libresoc.v:203158$15050 + attribute \src "libresoc.v:202346.3-202355.6" + process $proc$libresoc.v:202346$14998 assign { } { } assign { } { } assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] - attribute \src "libresoc.v:203159.5-203159.29" + attribute \src "libresoc.v:202347.5-202347.29" switch \initial - attribute \src "libresoc.v:203159.9-203159.17" + attribute \src "libresoc.v:202347.9-202347.17" case 1'1 case end @@ -426722,14 +421989,14 @@ module \xics_ics sync always update \cur_pri7 $0\cur_pri7[7:0] end - attribute \src "libresoc.v:203168.3-203177.6" - process $proc$libresoc.v:203168$15051 + attribute \src "libresoc.v:202356.3-202365.6" + process $proc$libresoc.v:202356$14999 assign { } { } assign { } { } assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] - attribute \src "libresoc.v:203169.5-203169.29" + attribute \src "libresoc.v:202357.5-202357.29" switch \initial - attribute \src "libresoc.v:203169.9-203169.17" + attribute \src "libresoc.v:202357.9-202357.17" case 1'1 case end @@ -426745,14 +422012,14 @@ module \xics_ics sync always update \cur_idx7 $0\cur_idx7[3:0] end - attribute \src "libresoc.v:203178.3-203187.6" - process $proc$libresoc.v:203178$15052 + attribute \src "libresoc.v:202366.3-202375.6" + process $proc$libresoc.v:202366$15000 assign { } { } assign { } { } assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] - attribute \src "libresoc.v:203179.5-203179.29" + attribute \src "libresoc.v:202367.5-202367.29" switch \initial - attribute \src "libresoc.v:203179.9-203179.17" + attribute \src "libresoc.v:202367.9-202367.17" case 1'1 case end @@ -426768,14 +422035,14 @@ module \xics_ics sync always update \cur_pri8 $0\cur_pri8[7:0] end - attribute \src "libresoc.v:203188.3-203197.6" - process $proc$libresoc.v:203188$15053 + attribute \src "libresoc.v:202376.3-202385.6" + process $proc$libresoc.v:202376$15001 assign { } { } assign { } { } assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] - attribute \src "libresoc.v:203189.5-203189.29" + attribute \src "libresoc.v:202377.5-202377.29" switch \initial - attribute \src "libresoc.v:203189.9-203189.17" + attribute \src "libresoc.v:202377.9-202377.17" case 1'1 case end @@ -426791,14 +422058,14 @@ module \xics_ics sync always update \cur_idx8 $0\cur_idx8[3:0] end - attribute \src "libresoc.v:203198.3-203207.6" - process $proc$libresoc.v:203198$15054 + attribute \src "libresoc.v:202386.3-202395.6" + process $proc$libresoc.v:202386$15002 assign { } { } assign { } { } assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] - attribute \src "libresoc.v:203199.5-203199.29" + attribute \src "libresoc.v:202387.5-202387.29" switch \initial - attribute \src "libresoc.v:203199.9-203199.17" + attribute \src "libresoc.v:202387.9-202387.17" case 1'1 case end @@ -426814,14 +422081,14 @@ module \xics_ics sync always update \cur_pri9 $0\cur_pri9[7:0] end - attribute \src "libresoc.v:203208.3-203217.6" - process $proc$libresoc.v:203208$15055 + attribute \src "libresoc.v:202396.3-202405.6" + process $proc$libresoc.v:202396$15003 assign { } { } assign { } { } assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] - attribute \src "libresoc.v:203209.5-203209.29" + attribute \src "libresoc.v:202397.5-202397.29" switch \initial - attribute \src "libresoc.v:203209.9-203209.17" + attribute \src "libresoc.v:202397.9-202397.17" case 1'1 case end @@ -426837,14 +422104,14 @@ module \xics_ics sync always update \cur_idx9 $0\cur_idx9[3:0] end - attribute \src "libresoc.v:203218.3-203227.6" - process $proc$libresoc.v:203218$15056 + attribute \src "libresoc.v:202406.3-202415.6" + process $proc$libresoc.v:202406$15004 assign { } { } assign { } { } assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] - attribute \src "libresoc.v:203219.5-203219.29" + attribute \src "libresoc.v:202407.5-202407.29" switch \initial - attribute \src "libresoc.v:203219.9-203219.17" + attribute \src "libresoc.v:202407.9-202407.17" case 1'1 case end @@ -426860,14 +422127,14 @@ module \xics_ics sync always update \cur_pri10 $0\cur_pri10[7:0] end - attribute \src "libresoc.v:203228.3-203237.6" - process $proc$libresoc.v:203228$15057 + attribute \src "libresoc.v:202416.3-202425.6" + process $proc$libresoc.v:202416$15005 assign { } { } assign { } { } assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] - attribute \src "libresoc.v:203229.5-203229.29" + attribute \src "libresoc.v:202417.5-202417.29" switch \initial - attribute \src "libresoc.v:203229.9-203229.17" + attribute \src "libresoc.v:202417.9-202417.17" case 1'1 case end @@ -426883,14 +422150,14 @@ module \xics_ics sync always update \cur_idx10 $0\cur_idx10[3:0] end - attribute \src "libresoc.v:203238.3-203247.6" - process $proc$libresoc.v:203238$15058 + attribute \src "libresoc.v:202426.3-202435.6" + process $proc$libresoc.v:202426$15006 assign { } { } assign { } { } assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] - attribute \src "libresoc.v:203239.5-203239.29" + attribute \src "libresoc.v:202427.5-202427.29" switch \initial - attribute \src "libresoc.v:203239.9-203239.17" + attribute \src "libresoc.v:202427.9-202427.17" case 1'1 case end @@ -426906,14 +422173,14 @@ module \xics_ics sync always update \cur_pri11 $0\cur_pri11[7:0] end - attribute \src "libresoc.v:203248.3-203257.6" - process $proc$libresoc.v:203248$15059 + attribute \src "libresoc.v:202436.3-202445.6" + process $proc$libresoc.v:202436$15007 assign { } { } assign { } { } assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] - attribute \src "libresoc.v:203249.5-203249.29" + attribute \src "libresoc.v:202437.5-202437.29" switch \initial - attribute \src "libresoc.v:203249.9-203249.17" + attribute \src "libresoc.v:202437.9-202437.17" case 1'1 case end @@ -426929,14 +422196,14 @@ module \xics_ics sync always update \cur_idx11 $0\cur_idx11[3:0] end - attribute \src "libresoc.v:203258.3-203267.6" - process $proc$libresoc.v:203258$15060 + attribute \src "libresoc.v:202446.3-202455.6" + process $proc$libresoc.v:202446$15008 assign { } { } assign { } { } assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] - attribute \src "libresoc.v:203259.5-203259.29" + attribute \src "libresoc.v:202447.5-202447.29" switch \initial - attribute \src "libresoc.v:203259.9-203259.17" + attribute \src "libresoc.v:202447.9-202447.17" case 1'1 case end @@ -426952,14 +422219,14 @@ module \xics_ics sync always update \cur_pri12 $0\cur_pri12[7:0] end - attribute \src "libresoc.v:203268.3-203277.6" - process $proc$libresoc.v:203268$15061 + attribute \src "libresoc.v:202456.3-202465.6" + process $proc$libresoc.v:202456$15009 assign { } { } assign { } { } assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] - attribute \src "libresoc.v:203269.5-203269.29" + attribute \src "libresoc.v:202457.5-202457.29" switch \initial - attribute \src "libresoc.v:203269.9-203269.17" + attribute \src "libresoc.v:202457.9-202457.17" case 1'1 case end @@ -426975,14 +422242,14 @@ module \xics_ics sync always update \cur_idx12 $0\cur_idx12[3:0] end - attribute \src "libresoc.v:203278.3-203287.6" - process $proc$libresoc.v:203278$15062 + attribute \src "libresoc.v:202466.3-202475.6" + process $proc$libresoc.v:202466$15010 assign { } { } assign { } { } assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] - attribute \src "libresoc.v:203279.5-203279.29" + attribute \src "libresoc.v:202467.5-202467.29" switch \initial - attribute \src "libresoc.v:203279.9-203279.17" + attribute \src "libresoc.v:202467.9-202467.17" case 1'1 case end @@ -426998,14 +422265,14 @@ module \xics_ics sync always update \cur_pri13 $0\cur_pri13[7:0] end - attribute \src "libresoc.v:203288.3-203297.6" - process $proc$libresoc.v:203288$15063 + attribute \src "libresoc.v:202476.3-202485.6" + process $proc$libresoc.v:202476$15011 assign { } { } assign { } { } assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] - attribute \src "libresoc.v:203289.5-203289.29" + attribute \src "libresoc.v:202477.5-202477.29" switch \initial - attribute \src "libresoc.v:203289.9-203289.17" + attribute \src "libresoc.v:202477.9-202477.17" case 1'1 case end @@ -427021,14 +422288,14 @@ module \xics_ics sync always update \cur_idx13 $0\cur_idx13[3:0] end - attribute \src "libresoc.v:203298.3-203307.6" - process $proc$libresoc.v:203298$15064 + attribute \src "libresoc.v:202486.3-202495.6" + process $proc$libresoc.v:202486$15012 assign { } { } assign { } { } assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] - attribute \src "libresoc.v:203299.5-203299.29" + attribute \src "libresoc.v:202487.5-202487.29" switch \initial - attribute \src "libresoc.v:203299.9-203299.17" + attribute \src "libresoc.v:202487.9-202487.17" case 1'1 case end @@ -427044,14 +422311,14 @@ module \xics_ics sync always update \cur_pri14 $0\cur_pri14[7:0] end - attribute \src "libresoc.v:203308.3-203357.6" - process $proc$libresoc.v:203308$15065 + attribute \src "libresoc.v:202496.3-202545.6" + process $proc$libresoc.v:202496$15013 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:203309.5-203309.29" + attribute \src "libresoc.v:202497.5-202497.29" switch \initial - attribute \src "libresoc.v:203309.9-203309.17" + attribute \src "libresoc.v:202497.9-202497.17" case 1'1 case end @@ -427144,14 +422411,14 @@ module \xics_ics sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:203358.3-203367.6" - process $proc$libresoc.v:203358$15066 + attribute \src "libresoc.v:202546.3-202555.6" + process $proc$libresoc.v:202546$15014 assign { } { } assign { } { } assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] - attribute \src "libresoc.v:203359.5-203359.29" + attribute \src "libresoc.v:202547.5-202547.29" switch \initial - attribute \src "libresoc.v:203359.9-203359.17" + attribute \src "libresoc.v:202547.9-202547.17" case 1'1 case end @@ -427167,14 +422434,14 @@ module \xics_ics sync always update \cur_idx14 $0\cur_idx14[3:0] end - attribute \src "libresoc.v:203368.3-203377.6" - process $proc$libresoc.v:203368$15067 + attribute \src "libresoc.v:202556.3-202565.6" + process $proc$libresoc.v:202556$15015 assign { } { } assign { } { } assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] - attribute \src "libresoc.v:203369.5-203369.29" + attribute \src "libresoc.v:202557.5-202557.29" switch \initial - attribute \src "libresoc.v:203369.9-203369.17" + attribute \src "libresoc.v:202557.9-202557.17" case 1'1 case end @@ -427190,14 +422457,14 @@ module \xics_ics sync always update \cur_pri15 $0\cur_pri15[7:0] end - attribute \src "libresoc.v:203378.3-203387.6" - process $proc$libresoc.v:203378$15068 + attribute \src "libresoc.v:202566.3-202575.6" + process $proc$libresoc.v:202566$15016 assign { } { } assign { } { } assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] - attribute \src "libresoc.v:203379.5-203379.29" + attribute \src "libresoc.v:202567.5-202567.29" switch \initial - attribute \src "libresoc.v:203379.9-203379.17" + attribute \src "libresoc.v:202567.9-202567.17" case 1'1 case end @@ -427213,14 +422480,14 @@ module \xics_ics sync always update \cur_idx15 $0\cur_idx15[3:0] end - attribute \src "libresoc.v:203388.3-203397.6" - process $proc$libresoc.v:203388$15069 + attribute \src "libresoc.v:202576.3-202585.6" + process $proc$libresoc.v:202576$15017 assign { } { } assign { } { } assign $0\ibit[0:0] $1\ibit[0:0] - attribute \src "libresoc.v:203389.5-203389.29" + attribute \src "libresoc.v:202577.5-202577.29" switch \initial - attribute \src "libresoc.v:203389.9-203389.17" + attribute \src "libresoc.v:202577.9-202577.17" case 1'1 case end @@ -427236,14 +422503,14 @@ module \xics_ics sync always update \ibit $0\ibit[0:0] end - attribute \src "libresoc.v:203398.3-203406.6" - process $proc$libresoc.v:203398$15070 + attribute \src "libresoc.v:202586.3-202594.6" + process $proc$libresoc.v:202586$15018 assign { } { } assign { } { } - assign $0\ics_wb__dat_r$next[31:0]$15071 $1\ics_wb__dat_r$next[31:0]$15072 - attribute \src "libresoc.v:203399.5-203399.29" + assign $0\ics_wb__dat_r$next[31:0]$15019 $1\ics_wb__dat_r$next[31:0]$15020 + attribute \src "libresoc.v:202587.5-202587.29" switch \initial - attribute \src "libresoc.v:203399.9-203399.17" + attribute \src "libresoc.v:202587.9-202587.17" case 1'1 case end @@ -427252,21 +422519,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__dat_r$next[31:0]$15072 0 + assign $1\ics_wb__dat_r$next[31:0]$15020 0 case - assign $1\ics_wb__dat_r$next[31:0]$15072 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $1\ics_wb__dat_r$next[31:0]$15020 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } end sync always - update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$15071 + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$15019 end - attribute \src "libresoc.v:203407.3-203415.6" - process $proc$libresoc.v:203407$15073 + attribute \src "libresoc.v:202595.3-202603.6" + process $proc$libresoc.v:202595$15021 assign { } { } assign { } { } - assign $0\ics_wb__ack$next[0:0]$15074 $1\ics_wb__ack$next[0:0]$15075 - attribute \src "libresoc.v:203408.5-203408.29" + assign $0\ics_wb__ack$next[0:0]$15022 $1\ics_wb__ack$next[0:0]$15023 + attribute \src "libresoc.v:202596.5-202596.29" switch \initial - attribute \src "libresoc.v:203408.9-203408.17" + attribute \src "libresoc.v:202596.9-202596.17" case 1'1 case end @@ -427275,116 +422542,116 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__ack$next[0:0]$15075 1'0 - case - assign $1\ics_wb__ack$next[0:0]$15075 \wb_valid - end - sync always - update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$15074 - end - connect \$7 $ternary$libresoc.v:202778$14828_Y - connect \$99 $lt$libresoc.v:202779$14829_Y - connect \$101 $and$libresoc.v:202780$14830_Y - connect \$103 $lt$libresoc.v:202781$14831_Y - connect \$105 $and$libresoc.v:202782$14832_Y - connect \$107 $lt$libresoc.v:202783$14833_Y - connect \$109 $and$libresoc.v:202784$14834_Y - connect \$111 $lt$libresoc.v:202785$14835_Y - connect \$113 $and$libresoc.v:202786$14836_Y - connect \$115 $lt$libresoc.v:202787$14837_Y - connect \$117 $and$libresoc.v:202788$14838_Y - connect \$119 $lt$libresoc.v:202789$14839_Y - connect \$121 $and$libresoc.v:202790$14840_Y - connect \$123 $lt$libresoc.v:202791$14841_Y - connect \$125 $and$libresoc.v:202792$14842_Y - connect \$127 $lt$libresoc.v:202793$14843_Y - connect \$12 $eq$libresoc.v:202794$14844_Y - connect \$129 $and$libresoc.v:202795$14845_Y - connect \$131 $lt$libresoc.v:202796$14846_Y - connect \$133 $and$libresoc.v:202797$14847_Y - connect \$135 $lt$libresoc.v:202798$14848_Y - connect \$137 $and$libresoc.v:202799$14849_Y - connect \$11 $ternary$libresoc.v:202800$14850_Y - connect \$139 $lt$libresoc.v:202801$14851_Y - connect \$141 $and$libresoc.v:202802$14852_Y - connect \$143 $lt$libresoc.v:202803$14853_Y - connect \$145 $and$libresoc.v:202804$14854_Y - connect \$147 $lt$libresoc.v:202805$14855_Y - connect \$149 $and$libresoc.v:202806$14856_Y - connect \$151 $lt$libresoc.v:202807$14857_Y - connect \$153 $and$libresoc.v:202808$14858_Y - connect \$155 $lt$libresoc.v:202809$14859_Y - connect \$157 $and$libresoc.v:202810$14860_Y - connect \$159 $lt$libresoc.v:202811$14861_Y - connect \$161 $and$libresoc.v:202812$14862_Y - connect \$163 $lt$libresoc.v:202813$14863_Y - connect \$165 $and$libresoc.v:202814$14864_Y - connect \$167 $lt$libresoc.v:202815$14865_Y - connect \$16 $eq$libresoc.v:202816$14866_Y - connect \$169 $and$libresoc.v:202817$14867_Y - connect \$171 $lt$libresoc.v:202818$14868_Y - connect \$173 $and$libresoc.v:202819$14869_Y - connect \$175 $lt$libresoc.v:202820$14870_Y - connect \$177 $and$libresoc.v:202821$14871_Y - connect \$15 $ternary$libresoc.v:202822$14872_Y - connect \$179 $lt$libresoc.v:202823$14873_Y - connect \$181 $and$libresoc.v:202824$14874_Y - connect \$183 $lt$libresoc.v:202825$14875_Y - connect \$185 $and$libresoc.v:202826$14876_Y - connect \$187 $lt$libresoc.v:202827$14877_Y - connect \$189 $and$libresoc.v:202828$14878_Y - connect \$191 $lt$libresoc.v:202829$14879_Y - connect \$193 $and$libresoc.v:202830$14880_Y - connect \$195 $lt$libresoc.v:202831$14881_Y - connect \$197 $and$libresoc.v:202832$14882_Y - connect \$1 $eq$libresoc.v:202833$14883_Y - connect \$199 $lt$libresoc.v:202834$14884_Y - connect \$201 $and$libresoc.v:202835$14885_Y - connect \$204 $eq$libresoc.v:202836$14886_Y - connect \$203 $ternary$libresoc.v:202837$14887_Y - connect \$20 $eq$libresoc.v:202838$14888_Y - connect \$19 $ternary$libresoc.v:202839$14889_Y - connect \$24 $eq$libresoc.v:202840$14890_Y - connect \$23 $ternary$libresoc.v:202841$14891_Y - connect \$28 $eq$libresoc.v:202842$14892_Y - connect \$27 $ternary$libresoc.v:202843$14893_Y - connect \$32 $eq$libresoc.v:202844$14894_Y - connect \$31 $ternary$libresoc.v:202845$14895_Y - connect \$36 $eq$libresoc.v:202846$14896_Y - connect \$35 $ternary$libresoc.v:202847$14897_Y - connect \$3 $eq$libresoc.v:202848$14898_Y - connect \$40 $eq$libresoc.v:202849$14899_Y - connect \$39 $ternary$libresoc.v:202850$14900_Y - connect \$44 $eq$libresoc.v:202851$14901_Y - connect \$43 $ternary$libresoc.v:202852$14902_Y - connect \$48 $eq$libresoc.v:202853$14903_Y - connect \$47 $ternary$libresoc.v:202854$14904_Y - connect \$52 $eq$libresoc.v:202855$14905_Y - connect \$51 $ternary$libresoc.v:202856$14906_Y - connect \$56 $eq$libresoc.v:202857$14907_Y - connect \$55 $ternary$libresoc.v:202858$14908_Y - connect \$5 $and$libresoc.v:202859$14909_Y - connect \$60 $eq$libresoc.v:202860$14910_Y - connect \$59 $ternary$libresoc.v:202861$14911_Y - connect \$64 $eq$libresoc.v:202862$14912_Y - connect \$63 $ternary$libresoc.v:202863$14913_Y - connect \$68 $eq$libresoc.v:202864$14914_Y - connect \$67 $ternary$libresoc.v:202865$14915_Y - connect \$71 $shr$libresoc.v:202866$14916_Y [0] - connect \$73 $and$libresoc.v:202867$14917_Y - connect \$75 $lt$libresoc.v:202868$14918_Y - connect \$77 $and$libresoc.v:202869$14919_Y - connect \$79 $lt$libresoc.v:202870$14920_Y - connect \$81 $and$libresoc.v:202871$14921_Y - connect \$83 $lt$libresoc.v:202872$14922_Y - connect \$85 $and$libresoc.v:202873$14923_Y - connect \$87 $lt$libresoc.v:202874$14924_Y - connect \$8 $eq$libresoc.v:202875$14925_Y - connect \$89 $and$libresoc.v:202876$14926_Y - connect \$91 $lt$libresoc.v:202877$14927_Y - connect \$93 $and$libresoc.v:202878$14928_Y - connect \$95 $lt$libresoc.v:202879$14929_Y - connect \$97 $and$libresoc.v:202880$14930_Y + assign $1\ics_wb__ack$next[0:0]$15023 1'0 + case + assign $1\ics_wb__ack$next[0:0]$15023 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$15022 + end + connect \$7 $ternary$libresoc.v:201966$14776_Y + connect \$99 $lt$libresoc.v:201967$14777_Y + connect \$101 $and$libresoc.v:201968$14778_Y + connect \$103 $lt$libresoc.v:201969$14779_Y + connect \$105 $and$libresoc.v:201970$14780_Y + connect \$107 $lt$libresoc.v:201971$14781_Y + connect \$109 $and$libresoc.v:201972$14782_Y + connect \$111 $lt$libresoc.v:201973$14783_Y + connect \$113 $and$libresoc.v:201974$14784_Y + connect \$115 $lt$libresoc.v:201975$14785_Y + connect \$117 $and$libresoc.v:201976$14786_Y + connect \$119 $lt$libresoc.v:201977$14787_Y + connect \$121 $and$libresoc.v:201978$14788_Y + connect \$123 $lt$libresoc.v:201979$14789_Y + connect \$125 $and$libresoc.v:201980$14790_Y + connect \$127 $lt$libresoc.v:201981$14791_Y + connect \$12 $eq$libresoc.v:201982$14792_Y + connect \$129 $and$libresoc.v:201983$14793_Y + connect \$131 $lt$libresoc.v:201984$14794_Y + connect \$133 $and$libresoc.v:201985$14795_Y + connect \$135 $lt$libresoc.v:201986$14796_Y + connect \$137 $and$libresoc.v:201987$14797_Y + connect \$11 $ternary$libresoc.v:201988$14798_Y + connect \$139 $lt$libresoc.v:201989$14799_Y + connect \$141 $and$libresoc.v:201990$14800_Y + connect \$143 $lt$libresoc.v:201991$14801_Y + connect \$145 $and$libresoc.v:201992$14802_Y + connect \$147 $lt$libresoc.v:201993$14803_Y + connect \$149 $and$libresoc.v:201994$14804_Y + connect \$151 $lt$libresoc.v:201995$14805_Y + connect \$153 $and$libresoc.v:201996$14806_Y + connect \$155 $lt$libresoc.v:201997$14807_Y + connect \$157 $and$libresoc.v:201998$14808_Y + connect \$159 $lt$libresoc.v:201999$14809_Y + connect \$161 $and$libresoc.v:202000$14810_Y + connect \$163 $lt$libresoc.v:202001$14811_Y + connect \$165 $and$libresoc.v:202002$14812_Y + connect \$167 $lt$libresoc.v:202003$14813_Y + connect \$16 $eq$libresoc.v:202004$14814_Y + connect \$169 $and$libresoc.v:202005$14815_Y + connect \$171 $lt$libresoc.v:202006$14816_Y + connect \$173 $and$libresoc.v:202007$14817_Y + connect \$175 $lt$libresoc.v:202008$14818_Y + connect \$177 $and$libresoc.v:202009$14819_Y + connect \$15 $ternary$libresoc.v:202010$14820_Y + connect \$179 $lt$libresoc.v:202011$14821_Y + connect \$181 $and$libresoc.v:202012$14822_Y + connect \$183 $lt$libresoc.v:202013$14823_Y + connect \$185 $and$libresoc.v:202014$14824_Y + connect \$187 $lt$libresoc.v:202015$14825_Y + connect \$189 $and$libresoc.v:202016$14826_Y + connect \$191 $lt$libresoc.v:202017$14827_Y + connect \$193 $and$libresoc.v:202018$14828_Y + connect \$195 $lt$libresoc.v:202019$14829_Y + connect \$197 $and$libresoc.v:202020$14830_Y + connect \$1 $eq$libresoc.v:202021$14831_Y + connect \$199 $lt$libresoc.v:202022$14832_Y + connect \$201 $and$libresoc.v:202023$14833_Y + connect \$204 $eq$libresoc.v:202024$14834_Y + connect \$203 $ternary$libresoc.v:202025$14835_Y + connect \$20 $eq$libresoc.v:202026$14836_Y + connect \$19 $ternary$libresoc.v:202027$14837_Y + connect \$24 $eq$libresoc.v:202028$14838_Y + connect \$23 $ternary$libresoc.v:202029$14839_Y + connect \$28 $eq$libresoc.v:202030$14840_Y + connect \$27 $ternary$libresoc.v:202031$14841_Y + connect \$32 $eq$libresoc.v:202032$14842_Y + connect \$31 $ternary$libresoc.v:202033$14843_Y + connect \$36 $eq$libresoc.v:202034$14844_Y + connect \$35 $ternary$libresoc.v:202035$14845_Y + connect \$3 $eq$libresoc.v:202036$14846_Y + connect \$40 $eq$libresoc.v:202037$14847_Y + connect \$39 $ternary$libresoc.v:202038$14848_Y + connect \$44 $eq$libresoc.v:202039$14849_Y + connect \$43 $ternary$libresoc.v:202040$14850_Y + connect \$48 $eq$libresoc.v:202041$14851_Y + connect \$47 $ternary$libresoc.v:202042$14852_Y + connect \$52 $eq$libresoc.v:202043$14853_Y + connect \$51 $ternary$libresoc.v:202044$14854_Y + connect \$56 $eq$libresoc.v:202045$14855_Y + connect \$55 $ternary$libresoc.v:202046$14856_Y + connect \$5 $and$libresoc.v:202047$14857_Y + connect \$60 $eq$libresoc.v:202048$14858_Y + connect \$59 $ternary$libresoc.v:202049$14859_Y + connect \$64 $eq$libresoc.v:202050$14860_Y + connect \$63 $ternary$libresoc.v:202051$14861_Y + connect \$68 $eq$libresoc.v:202052$14862_Y + connect \$67 $ternary$libresoc.v:202053$14863_Y + connect \$71 $shr$libresoc.v:202054$14864_Y [0] + connect \$73 $and$libresoc.v:202055$14865_Y + connect \$75 $lt$libresoc.v:202056$14866_Y + connect \$77 $and$libresoc.v:202057$14867_Y + connect \$79 $lt$libresoc.v:202058$14868_Y + connect \$81 $and$libresoc.v:202059$14869_Y + connect \$83 $lt$libresoc.v:202060$14870_Y + connect \$85 $and$libresoc.v:202061$14871_Y + connect \$87 $lt$libresoc.v:202062$14872_Y + connect \$8 $eq$libresoc.v:202063$14873_Y + connect \$89 $and$libresoc.v:202064$14874_Y + connect \$91 $lt$libresoc.v:202065$14875_Y + connect \$93 $and$libresoc.v:202066$14876_Y + connect \$95 $lt$libresoc.v:202067$14877_Y + connect \$97 $and$libresoc.v:202068$14878_Y connect \icp_r_pri \$203 connect \icp_r_src \cur_idx15 connect \max_idx 4'0000 -- 2.30.2