From f6dd997ef43f52f80f5cdb43cd32614ce4169960 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Wed, 27 Jun 2018 09:35:11 +0100 Subject: [PATCH] arch-arm: Fix incorrect t{0,1}sz field in TTBCR The t0sz and t1sz fields in TTBCR only are only three bits wide unlike aarch64 which has a 6-bit wide field. The higher bits of the aarch64-equivalent should be treated as RES0. Change-Id: I60df73105c34500c0348a44a491c117e9b28f18f Signed-off-by: Andreas Sandberg Reviewed-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/11589 Maintainer: Giacomo Travaglini --- src/arch/arm/miscregs.hh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index f9386b412..1a88c927e 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -1722,13 +1722,13 @@ namespace ArmISA Bitfield<4> pd0; Bitfield<5> pd1; // Long-descriptor translation table format - Bitfield<5, 0> t0sz; + Bitfield<2, 0> t0sz; Bitfield<7> epd0; Bitfield<9, 8> irgn0; Bitfield<11, 10> orgn0; Bitfield<13, 12> sh0; Bitfield<14> tg0; - Bitfield<21, 16> t1sz; + Bitfield<18, 16> t1sz; Bitfield<22> a1; Bitfield<23> epd1; Bitfield<25, 24> irgn1; -- 2.30.2