From f717bc2ba64501d2956cf7ef64738c1a3206e676 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 12 Apr 2021 16:44:51 +0000 Subject: [PATCH] experimentation to get experiment10_verilog work with FreePDK --- .../freepdk_c4m45/doDesign.py | 28 +++++++++++++++---- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/experiments10_verilog/freepdk_c4m45/doDesign.py b/experiments10_verilog/freepdk_c4m45/doDesign.py index 63a7235..10dd423 100644 --- a/experiments10_verilog/freepdk_c4m45/doDesign.py +++ b/experiments10_verilog/freepdk_c4m45/doDesign.py @@ -7,9 +7,10 @@ import helpers from helpers.io import ErrorMessage from helpers.io import WarningMessage from helpers import trace +from helpers.overlay import UpdateSession from helpers import l, u, n import plugins -from Hurricane import DbU +from Hurricane import DbU, Box from plugins.alpha.block.block import Block from plugins.alpha.block.configuration import IoPin from plugins.alpha.block.configuration import GaugeConf @@ -20,11 +21,18 @@ from plugins.alpha.chip.chip import Chip af = CRL.AllianceFramework.get() +def rsetAbutmentBox ( cell, ab ): + for occurrence in cell.getNonTerminalNetlistInstanceOccurrences(): + masterCell = occurrence.getEntity().getMasterCell() + masterCell.setAbutmentBox( ab ) + def scriptMain ( **kw ): """The mandatory function to be called by Coriolis CGT/Unicorn.""" global af rvalue = True + coreSize = u(6*90.0) + chipBorder = u(2*214.0 + 10*13.0) try: helpers.setTraceLevel( 550 ) cell, editor = plugins.kwParseMain( **kw ) @@ -66,8 +74,13 @@ def scriptMain ( **kw ): adderConf.cfg.etesian.uniformDensity = True adderConf.cfg.etesian.aspectRatio = 1.0 adderConf.cfg.etesian.spaceMargin = 0.05 - adderConf.cfg.block.spareSide = l(700) - adderConf.cfg.chip.padCoreSide = 'North' + adderConf.cfg.anabatic.searchHalo = 2 + adderConf.cfg.anabatic.globalIterations = 20 + adderConf.cfg.anabatic.topRoutingLayer = 'METAL5' + adderConf.cfg.block.spareSide = u(7*13) + #adderConf.cfg.chip.padCoreSide = 'North' + adderConf.cfg.chip.supplyRailWidth = u(35) + adderConf.cfg.chip.supplyRailPitch = u(90) adderConf.editor = editor adderConf.useSpares = True adderConf.useClockTree = True @@ -76,11 +89,16 @@ def scriptMain ( **kw ): adderConf.bRows = 2 adderConf.chipConf.name = 'chip' adderConf.chipConf.ioPadGauge = 'LibreSOCIO' - adderConf.coreSize = ( l(12000), l(12000) ) - adderConf.chipSize = ( l(25000), l(25000) ) + adderConf.coreSize = (coreSize, coreSize) + adderConf.chipSize = (coreSize + chipBorder, coreSize + chipBorder) adderToChip = CoreToChip( adderConf ) adderToChip.buildChip() + with UpdateSession(): + sliceHeight = adderConf.sliceHeight + coreAb = Box( 0, 0, coreSize, coreSize ) + rsetAbutmentBox( cell, coreAb ) + chipBuilder = Chip( adderConf ) chipBuilder.doChipFloorplan() -- 2.30.2