From f72e27f609953cf3af99fdf4262355cf314dfcd9 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Thu, 6 Aug 2020 12:30:21 +0200 Subject: [PATCH] gram.test: Use correct timing for simulations --- gram/test/test_common.py | 2 +- gram/test/test_core_multiplexer.py | 8 ++++---- gram/test/test_core_refresher.py | 6 +++--- gram/test/utils.py | 2 +- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/gram/test/test_common.py b/gram/test/test_common.py index f775ea1..fdcd025 100644 --- a/gram/test/test_common.py +++ b/gram/test/test_common.py @@ -22,7 +22,7 @@ class tXXDControllerTestCase(FHDLTestCase): dut = tXXDController(txxd) yield dut.valid.eq(1) - yield; yield Delay(1e-8) + yield; yield Delay(1e-9) self.assertFalse((yield dut.ready)) yield dut.valid.eq(0) diff --git a/gram/test/test_core_multiplexer.py b/gram/test/test_core_multiplexer.py index 0be117f..0bbce8e 100644 --- a/gram/test/test_core_multiplexer.py +++ b/gram/test/test_core_multiplexer.py @@ -35,13 +35,13 @@ class CommandChooserTestCase(FHDLTestCase): # want_writes yield dut.want_writes.eq(1) - yield; yield Delay(1e-8) + yield; yield Delay(1e-9) self.assertEqual((yield dut.cmd.a), 7) # want_reads yield dut.want_writes.eq(0) yield dut.want_reads.eq(1) - yield; yield Delay(1e-8) + yield; yield Delay(1e-9) self.assertEqual((yield dut.cmd.a), 5) runSimulation(dut, process, "test_core_multiplexer_commandchooser.vcd") @@ -65,14 +65,14 @@ class CommandChooserTestCase(FHDLTestCase): # want_writes yield dut.want_writes.eq(1) - yield; yield Delay(1e-8) + yield; yield Delay(1e-9) self.assertTrue((yield dut.write())) self.assertFalse((yield dut.read())) # want_reads yield dut.want_writes.eq(0) yield dut.want_reads.eq(1) - yield; yield Delay(1e-8) + yield; yield Delay(1e-9) self.assertTrue((yield dut.read())) self.assertFalse((yield dut.write())) diff --git a/gram/test/test_core_refresher.py b/gram/test/test_core_refresher.py index 6c924d1..ac963bf 100644 --- a/gram/test/test_core_refresher.py +++ b/gram/test/test_core_refresher.py @@ -13,11 +13,11 @@ class RefreshExecuterTestCase(FHDLTestCase): def process(): yield dut.start.eq(1) - yield; yield Delay(1e-8) + yield; yield Delay(1e-9) self.assertEqual((yield dut.a), 2**10) for i in range(trp): yield - yield Delay(1e-8) + yield Delay(1e-9) self.assertEqual((yield dut.a), 0) runSimulation(dut, process, "test_refreshexecuter.vcd") @@ -77,7 +77,7 @@ class RefreshPostponerTestCase(FHDLTestCase): yield yield dut.req_i.eq(0) - yield; yield Delay(1e-8) + yield; yield Delay(1e-9) self.assertFalse((yield dut.req_o)) diff --git a/gram/test/utils.py b/gram/test/utils.py index aa22a39..ed34d11 100644 --- a/gram/test/utils.py +++ b/gram/test/utils.py @@ -17,7 +17,7 @@ from nmigen._toolchain import require_tool __all__ = ["FHDLTestCase", "runSimulation", "wb_read", "wb_write", "PulseCounter", "Delay"] -def runSimulation(module, process, vcd_filename="anonymous.vcd", clock=1e-6): +def runSimulation(module, process, vcd_filename="anonymous.vcd", clock=1e-8): sim = Simulator(module) with sim.write_vcd(vcd_filename): sim.add_clock(clock) -- 2.30.2