From f7311258cf61308eeeaaf86d44b83b31ca8a7d1d Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 30 Sep 2021 21:46:18 +0100 Subject: [PATCH] --- 3d_gpu/architecture/dynamic_simd/logicops.mdwn | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/3d_gpu/architecture/dynamic_simd/logicops.mdwn b/3d_gpu/architecture/dynamic_simd/logicops.mdwn index f44712a19..bb26d2ac8 100644 --- a/3d_gpu/architecture/dynamic_simd/logicops.mdwn +++ b/3d_gpu/architecture/dynamic_simd/logicops.mdwn @@ -10,13 +10,15 @@ These are **not** the same as bitwise logical operations equivalent to: for i in range(64): result[i] = a[i] xor b[i] # 2 operands +The above returns a 64 bit result for 64 bit inputs. + they are instead SIMD versions of: result = 0 # initial value (single bit) for i in range(64): result = result xor a[i] # one operand -Each of the logic ops, "some bool any all xor" are a single bit for +Each of the logic ops, "some bool any all xor" are a **single bit** for scalar, but for Partitioned SIMD produce one bit per lane. # Requirements -- 2.30.2