From f73bcc0718f7de750ef212e86307531e2f20688a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 2 Jun 2021 13:23:44 +0100 Subject: [PATCH] appears that the FP operation takes place at full 64-bit precision then is truncated afterwards to 32-bit, then converted to fit into 64 --- src/openpower/decoder/helpers.py | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py index 3f0c7fcd..7e83faef 100644 --- a/src/openpower/decoder/helpers.py +++ b/src/openpower/decoder/helpers.py @@ -253,8 +253,9 @@ def fp64toselectable(frt): def FPADD32(FRA, FRB): - FRA = DOUBLE(SINGLE(FRA)) - FRB = DOUBLE(SINGLE(FRB)) + #return FPADD64(FRA, FRB) + #FRA = DOUBLE(SINGLE(FRA)) + #FRB = DOUBLE(SINGLE(FRB)) result = float(FRA) + float(FRB) cvt = fp64toselectable(result) cvt = DOUBLE(SINGLE(cvt)) @@ -263,8 +264,9 @@ def FPADD32(FRA, FRB): def FPSUB32(FRA, FRB): - FRA = DOUBLE(SINGLE(FRA)) - FRB = DOUBLE(SINGLE(FRB)) + #return FPSUB64(FRA, FRB) + #FRA = DOUBLE(SINGLE(FRA)) + #FRB = DOUBLE(SINGLE(FRB)) result = float(FRA) - float(FRB) cvt = fp64toselectable(result) cvt = DOUBLE(SINGLE(cvt)) @@ -273,8 +275,9 @@ def FPSUB32(FRA, FRB): def FPMUL32(FRA, FRB): - FRA = DOUBLE(SINGLE(FRA)) - FRB = DOUBLE(SINGLE(FRB)) + #return FPMUL64(FRA, FRB) + #FRA = DOUBLE(SINGLE(FRA)) + #FRB = DOUBLE(SINGLE(FRB)) result = float(FRA) * float(FRB) cvt = fp64toselectable(result) cvt = DOUBLE(SINGLE(cvt)) @@ -283,8 +286,9 @@ def FPMUL32(FRA, FRB): def FPDIV32(FRA, FRB): - FRA = DOUBLE(SINGLE(FRA)) - FRB = DOUBLE(SINGLE(FRB)) + #return FPDIV64(FRA, FRB) + #FRA = DOUBLE(SINGLE(FRA)) + #FRB = DOUBLE(SINGLE(FRB)) result = float(FRA) / float(FRB) cvt = fp64toselectable(result) cvt = DOUBLE(SINGLE(cvt)) -- 2.30.2