From f747ad69cedf95e6154a4de141530e4ebcd48279 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 14 Jul 2020 20:31:05 +0100 Subject: [PATCH] attempting to access self.msr directly --- src/soc/decoder/isa/caller.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 2833e6f3..aea6d035 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -577,8 +577,9 @@ class ISACaller: MicrOp.OP_MTSPR.value] and spr_msb: instr_is_privileged = True + print ("is priv", instr_is_privileged, self.msr[63-MSR.PR]) # check MSR priv bit and whether op is privileged: if so, throw trap - if instr_is_privileged and self.namespace['MSR'][63-MSR.PR] == 1: + if instr_is_privileged and self.msr[63-MSR.PR] == 1: self.TRAP(0x700, PI.PRIV) return -- 2.30.2